1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "linux-ppc-tdesc-init.h"
33 #include "tracepoint.h"
35 #define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37 #define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
46 /* Holds the AT_HWCAP auxv entry. */
48 static unsigned long ppc_hwcap
;
50 /* Holds the AT_HWCAP2 auxv entry. */
52 static unsigned long ppc_hwcap2
;
55 #define ppc_num_regs 73
58 /* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60 static int ppc_regmap
[] =
61 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
62 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
63 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
64 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
65 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
66 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
67 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
68 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
69 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
70 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
71 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
72 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
73 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
74 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
75 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
76 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
77 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
78 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
79 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
81 /* Currently, don't check/send MQ. */
82 static int ppc_regmap
[] =
83 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
84 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
85 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
86 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
87 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
88 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
89 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
90 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
91 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
92 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
93 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
94 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
95 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
96 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
97 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
98 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
99 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
100 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
101 PT_ORIG_R3
* 4, PT_TRAP
* 4
104 static int ppc_regmap_e500
[] =
105 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
106 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
107 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
108 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
109 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
110 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
111 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
112 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
121 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
122 PT_CTR
* 4, PT_XER
* 4, -1,
123 PT_ORIG_R3
* 4, PT_TRAP
* 4
127 /* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
131 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
133 void *buf
= alloca (regsetsize
);
137 iov
.iov_len
= regsetsize
;
139 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
146 ppc_cannot_store_register (int regno
)
148 const struct target_desc
*tdesc
= current_process ()->tdesc
;
150 #ifndef __powerpc64__
151 /* Some kernels do not allow us to store fpscr. */
152 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
153 && regno
== find_regno (tdesc
, "fpscr"))
157 /* Some kernels do not allow us to store orig_r3 or trap. */
158 if (regno
== find_regno (tdesc
, "orig_r3")
159 || regno
== find_regno (tdesc
, "trap"))
166 ppc_cannot_fetch_register (int regno
)
172 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
174 memset (buf
, 0, sizeof (long));
176 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache
, regno
, buf
);
181 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size
= register_size (regcache
->tdesc
, regno
);
188 if (size
< sizeof (long))
189 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
191 collect_register (regcache
, regno
, buf
);
194 perror_with_name ("Unexpected byte order");
198 ppc_supply_ptrace_register (struct regcache
*regcache
,
199 int regno
, const char *buf
)
201 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache
, regno
, buf
);
206 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size
= register_size (regcache
->tdesc
, regno
);
213 if (size
< sizeof (long))
214 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
216 supply_register (regcache
, regno
, buf
);
219 perror_with_name ("Unexpected byte order");
223 #define INSTR_SC 0x44000002
224 #define NR_spu_run 0x0116
226 /* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
230 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
236 if (register_size (regcache
->tdesc
, 0) == 4)
238 unsigned int pc
, r0
, r3
, r4
;
239 collect_register_by_name (regcache
, "pc", &pc
);
240 collect_register_by_name (regcache
, "r0", &r0
);
241 collect_register_by_name (regcache
, "orig_r3", &r3
);
242 collect_register_by_name (regcache
, "r4", &r4
);
243 curr_pc
= (CORE_ADDR
) pc
;
246 *addr
= (CORE_ADDR
) r4
;
250 unsigned long pc
, r0
, r3
, r4
;
251 collect_register_by_name (regcache
, "pc", &pc
);
252 collect_register_by_name (regcache
, "r0", &r0
);
253 collect_register_by_name (regcache
, "orig_r3", &r3
);
254 collect_register_by_name (regcache
, "r4", &r4
);
255 curr_pc
= (CORE_ADDR
) pc
;
258 *addr
= (CORE_ADDR
) r4
;
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target
->read_memory
) (curr_pc
- 4,
263 (unsigned char *) &curr_insn
, 4) != 0)
265 /* It should be a "sc" instruction. */
266 if (curr_insn
!= INSTR_SC
)
268 /* System call number should be NR_spu_run. */
269 if (curr_r0
!= NR_spu_run
)
276 ppc_get_pc (struct regcache
*regcache
)
281 if (parse_spufs_run (regcache
, &fd
, &addr
))
284 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
285 return ((CORE_ADDR
)1 << 63)
286 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
288 else if (register_size (regcache
->tdesc
, 0) == 4)
291 collect_register_by_name (regcache
, "pc", &pc
);
292 return (CORE_ADDR
) pc
;
297 collect_register_by_name (regcache
, "pc", &pc
);
298 return (CORE_ADDR
) pc
;
303 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
308 if (parse_spufs_run (regcache
, &fd
, &addr
))
310 unsigned int newpc
= pc
;
311 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
313 else if (register_size (regcache
->tdesc
, 0) == 4)
315 unsigned int newpc
= pc
;
316 supply_register_by_name (regcache
, "pc", &newpc
);
320 unsigned long newpc
= pc
;
321 supply_register_by_name (regcache
, "pc", &newpc
);
327 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
329 const struct target_desc
*tdesc
= current_process ()->tdesc
;
330 int wordsize
= register_size (tdesc
, 0);
331 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
334 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
338 unsigned int *data_p
= (unsigned int *)data
;
339 if (data_p
[0] == type
)
347 unsigned long *data_p
= (unsigned long *)data
;
348 if (data_p
[0] == type
)
355 offset
+= 2 * wordsize
;
362 #ifndef __powerpc64__
363 static int ppc_regmap_adjusted
;
367 /* Correct in either endianness.
368 This instruction is "twge r2, r2", which GDB uses as a software
370 static const unsigned int ppc_breakpoint
= 0x7d821008;
371 #define ppc_breakpoint_len 4
373 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
375 static const gdb_byte
*
376 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
378 *size
= ppc_breakpoint_len
;
379 return (const gdb_byte
*) &ppc_breakpoint
;
383 ppc_breakpoint_at (CORE_ADDR where
)
387 if (where
& ((CORE_ADDR
)1 << 63))
390 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
391 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
392 NULL
, where
& 0xffffffff, 4);
398 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
399 if (insn
== ppc_breakpoint
)
401 /* If necessary, recognize more trap instructions here. GDB only uses
408 /* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
415 ppc_supports_z_point_type (char z_type
)
422 case Z_PACKET_WRITE_WP
:
423 case Z_PACKET_ACCESS_WP
:
429 /* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
433 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
434 int size
, struct raw_breakpoint
*bp
)
438 case raw_bkpt_type_sw
:
439 return insert_memory_breakpoint (bp
);
441 case raw_bkpt_type_hw
:
442 case raw_bkpt_type_write_wp
:
443 case raw_bkpt_type_access_wp
:
450 /* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
454 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
455 int size
, struct raw_breakpoint
*bp
)
459 case raw_bkpt_type_sw
:
460 return remove_memory_breakpoint (bp
);
462 case raw_bkpt_type_hw
:
463 case raw_bkpt_type_write_wp
:
464 case raw_bkpt_type_access_wp
:
471 /* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
474 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
478 for (i
= 0; i
< 32; i
++)
479 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
481 for (i
= 64; i
< 70; i
++)
482 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
484 for (i
= 71; i
< 73; i
++)
485 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
488 /* Program Priority Register regset fill function. */
491 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
493 char *ppr
= (char *) buf
;
495 collect_register_by_name (regcache
, "ppr", ppr
);
498 /* Program Priority Register regset store function. */
501 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
503 const char *ppr
= (const char *) buf
;
505 supply_register_by_name (regcache
, "ppr", ppr
);
508 /* Data Stream Control Register regset fill function. */
511 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
513 char *dscr
= (char *) buf
;
515 collect_register_by_name (regcache
, "dscr", dscr
);
518 /* Data Stream Control Register regset store function. */
521 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
523 const char *dscr
= (const char *) buf
;
525 supply_register_by_name (regcache
, "dscr", dscr
);
528 /* Target Address Register regset fill function. */
531 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
533 char *tar
= (char *) buf
;
535 collect_register_by_name (regcache
, "tar", tar
);
538 /* Target Address Register regset store function. */
541 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
543 const char *tar
= (const char *) buf
;
545 supply_register_by_name (regcache
, "tar", tar
);
548 /* Event-Based Branching regset store function. Unless the inferior
549 has a perf event open, ptrace can return in error when reading and
550 writing to the regset, with ENODATA. For reading, the registers
551 will correctly show as unavailable. For writing, gdbserver
552 currently only caches any register writes from P and G packets and
553 the stub always tries to write all the regsets when resuming the
554 inferior, which would result in frequent warnings. For this
555 reason, we don't define a fill function. This also means that the
556 client-side regcache will be dirty if the user tries to write to
557 the EBB registers. G packets that the client sends to write to
558 unrelated registers will also include data for EBB registers, even
559 if they are unavailable. */
562 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
564 const char *regset
= (const char *) buf
;
566 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
567 .dat file is BESCR, EBBHR, EBBRR. */
568 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
569 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
570 supply_register_by_name (regcache
, "bescr", ®set
[16]);
573 /* Performance Monitoring Unit regset fill function. */
576 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
578 char *regset
= (char *) buf
;
580 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
581 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
582 collect_register_by_name (regcache
, "siar", ®set
[0]);
583 collect_register_by_name (regcache
, "sdar", ®set
[8]);
584 collect_register_by_name (regcache
, "sier", ®set
[16]);
585 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
586 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
589 /* Performance Monitoring Unit regset store function. */
592 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
594 const char *regset
= (const char *) buf
;
596 supply_register_by_name (regcache
, "siar", ®set
[0]);
597 supply_register_by_name (regcache
, "sdar", ®set
[8]);
598 supply_register_by_name (regcache
, "sier", ®set
[16]);
599 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
600 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
603 /* Hardware Transactional Memory special-purpose register regset fill
607 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
610 char *regset
= (char *) buf
;
612 base
= find_regno (regcache
->tdesc
, "tfhar");
613 for (i
= 0; i
< 3; i
++)
614 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
617 /* Hardware Transactional Memory special-purpose register regset store
621 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
624 const char *regset
= (const char *) buf
;
626 base
= find_regno (regcache
->tdesc
, "tfhar");
627 for (i
= 0; i
< 3; i
++)
628 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
631 /* For the same reasons as the EBB regset, none of the HTM
632 checkpointed regsets have a fill function. These registers are
633 only available if the inferior is in a transaction. */
635 /* Hardware Transactional Memory checkpointed general-purpose regset
639 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
641 int i
, base
, size
, endian_offset
;
642 const char *regset
= (const char *) buf
;
644 base
= find_regno (regcache
->tdesc
, "cr0");
645 size
= register_size (regcache
->tdesc
, base
);
647 gdb_assert (size
== 4 || size
== 8);
649 for (i
= 0; i
< 32; i
++)
650 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
654 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
657 supply_register_by_name (regcache
, "ccr",
658 ®set
[PT_CCR
* size
+ endian_offset
]);
660 supply_register_by_name (regcache
, "cxer",
661 ®set
[PT_XER
* size
+ endian_offset
]);
663 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
664 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
667 /* Hardware Transactional Memory checkpointed floating-point regset
671 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
674 const char *regset
= (const char *) buf
;
676 base
= find_regno (regcache
->tdesc
, "cf0");
678 for (i
= 0; i
< 32; i
++)
679 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
681 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
684 /* Hardware Transactional Memory checkpointed vector regset store
688 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
691 const char *regset
= (const char *) buf
;
694 base
= find_regno (regcache
->tdesc
, "cvr0");
696 for (i
= 0; i
< 32; i
++)
697 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
699 if (__BYTE_ORDER
== __BIG_ENDIAN
)
702 supply_register_by_name (regcache
, "cvscr",
703 ®set
[32 * 16 + vscr_offset
]);
705 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
708 /* Hardware Transactional Memory checkpointed vector-scalar regset
712 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
715 const char *regset
= (const char *) buf
;
717 base
= find_regno (regcache
->tdesc
, "cvs0h");
718 for (i
= 0; i
< 32; i
++)
719 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
722 /* Hardware Transactional Memory checkpointed Program Priority
723 Register regset store function. */
726 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
728 const char *cppr
= (const char *) buf
;
730 supply_register_by_name (regcache
, "cppr", cppr
);
733 /* Hardware Transactional Memory checkpointed Data Stream Control
734 Register regset store function. */
737 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
739 const char *cdscr
= (const char *) buf
;
741 supply_register_by_name (regcache
, "cdscr", cdscr
);
744 /* Hardware Transactional Memory checkpointed Target Address Register
745 regset store function. */
748 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
750 const char *ctar
= (const char *) buf
;
752 supply_register_by_name (regcache
, "ctar", ctar
);
756 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
759 char *regset
= (char *) buf
;
761 base
= find_regno (regcache
->tdesc
, "vs0h");
762 for (i
= 0; i
< 32; i
++)
763 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
767 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
770 const char *regset
= (const char *) buf
;
772 base
= find_regno (regcache
->tdesc
, "vs0h");
773 for (i
= 0; i
< 32; i
++)
774 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
778 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
781 char *regset
= (char *) buf
;
784 base
= find_regno (regcache
->tdesc
, "vr0");
785 for (i
= 0; i
< 32; i
++)
786 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
788 if (__BYTE_ORDER
== __BIG_ENDIAN
)
791 collect_register_by_name (regcache
, "vscr",
792 ®set
[32 * 16 + vscr_offset
]);
794 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
798 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
801 const char *regset
= (const char *) buf
;
804 base
= find_regno (regcache
->tdesc
, "vr0");
805 for (i
= 0; i
< 32; i
++)
806 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
808 if (__BYTE_ORDER
== __BIG_ENDIAN
)
811 supply_register_by_name (regcache
, "vscr",
812 ®set
[32 * 16 + vscr_offset
]);
813 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
816 struct gdb_evrregset_t
818 unsigned long evr
[32];
819 unsigned long long acc
;
820 unsigned long spefscr
;
824 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
827 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
829 ev0
= find_regno (regcache
->tdesc
, "ev0h");
830 for (i
= 0; i
< 32; i
++)
831 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
833 collect_register_by_name (regcache
, "acc", ®set
->acc
);
834 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
838 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
841 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
843 ev0
= find_regno (regcache
->tdesc
, "ev0h");
844 for (i
= 0; i
< 32; i
++)
845 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
847 supply_register_by_name (regcache
, "acc", ®set
->acc
);
848 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
851 /* Support for hardware single step. */
854 ppc_supports_hardware_single_step (void)
859 static struct regset_info ppc_regsets
[] = {
860 /* List the extra register sets before GENERAL_REGS. That way we will
861 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
862 general registers. Some kernels support these, but not the newer
863 PPC_PTRACE_GETREGS. */
864 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
865 NULL
, ppc_store_tm_ctarregset
},
866 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
867 NULL
, ppc_store_tm_cdscrregset
},
868 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
869 NULL
, ppc_store_tm_cpprregset
},
870 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
871 NULL
, ppc_store_tm_cvsxregset
},
872 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
873 NULL
, ppc_store_tm_cvrregset
},
874 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
875 NULL
, ppc_store_tm_cfprregset
},
876 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
877 NULL
, ppc_store_tm_cgprregset
},
878 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
879 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
880 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
881 NULL
, ppc_store_ebbregset
},
882 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
883 ppc_fill_pmuregset
, ppc_store_pmuregset
},
884 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
885 ppc_fill_tarregset
, ppc_store_tarregset
},
886 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
887 ppc_fill_pprregset
, ppc_store_pprregset
},
888 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
889 ppc_fill_dscrregset
, ppc_store_dscrregset
},
890 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
891 ppc_fill_vsxregset
, ppc_store_vsxregset
},
892 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
893 ppc_fill_vrregset
, ppc_store_vrregset
},
894 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
895 ppc_fill_evrregset
, ppc_store_evrregset
},
896 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
900 static struct usrregs_info ppc_usrregs_info
=
906 static struct regsets_info ppc_regsets_info
=
908 ppc_regsets
, /* regsets */
910 NULL
, /* disabled_regsets */
913 static struct regs_info regs_info
=
915 NULL
, /* regset_bitmap */
920 static const struct regs_info
*
927 ppc_arch_setup (void)
929 const struct target_desc
*tdesc
;
930 struct regset_info
*regset
;
931 struct ppc_linux_features features
= ppc_linux_no_features
;
933 int tid
= lwpid_of (current_thread
);
935 features
.wordsize
= ppc_linux_target_wordsize (tid
);
937 if (features
.wordsize
== 4)
938 tdesc
= tdesc_powerpc_32l
;
940 tdesc
= tdesc_powerpc_64l
;
942 current_process ()->tdesc
= tdesc
;
944 /* The value of current_process ()->tdesc needs to be set for this
946 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
947 ppc_get_auxv (AT_HWCAP2
, &ppc_hwcap2
);
949 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
951 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
954 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
955 features
.altivec
= true;
957 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
958 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
959 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
961 features
.ppr_dscr
= true;
962 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
963 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
964 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
965 && ppc_check_regset (tid
, NT_PPC_TAR
,
966 PPC_LINUX_SIZEOF_TARREGSET
)
967 && ppc_check_regset (tid
, NT_PPC_EBB
,
968 PPC_LINUX_SIZEOF_EBBREGSET
)
969 && ppc_check_regset (tid
, NT_PPC_PMU
,
970 PPC_LINUX_SIZEOF_PMUREGSET
))
972 features
.isa207
= true;
973 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
974 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
975 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
980 if (ppc_hwcap
& PPC_FEATURE_CELL
)
981 features
.cell
= true;
983 tdesc
= ppc_linux_match_description (features
);
985 /* On 32-bit machines, check for SPE registers.
986 Set the low target's regmap field as appropriately. */
987 #ifndef __powerpc64__
988 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
989 tdesc
= tdesc_powerpc_e500l
;
991 if (!ppc_regmap_adjusted
)
993 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
994 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
996 /* If the FPSCR is 64-bit wide, we need to fetch the whole
997 64-bit slot and not just its second word. The PT_FPSCR
998 supplied in a 32-bit GDB compilation doesn't reflect
1000 if (register_size (tdesc
, 70) == 8)
1001 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
1003 ppc_regmap_adjusted
= 1;
1007 current_process ()->tdesc
= tdesc
;
1009 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
1010 switch (regset
->get_request
)
1012 case PTRACE_GETVRREGS
:
1013 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
1015 case PTRACE_GETVSXREGS
:
1016 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
1018 case PTRACE_GETEVRREGS
:
1019 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
1020 regset
->size
= 32 * 4 + 8 + 4;
1024 case PTRACE_GETREGSET
:
1025 switch (regset
->nt_type
)
1028 regset
->size
= (features
.ppr_dscr
?
1029 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
1032 regset
->size
= (features
.ppr_dscr
?
1033 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
1036 regset
->size
= (features
.isa207
?
1037 PPC_LINUX_SIZEOF_TARREGSET
: 0);
1040 regset
->size
= (features
.isa207
?
1041 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
1044 regset
->size
= (features
.isa207
?
1045 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
1048 regset
->size
= (features
.htm
?
1049 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
1051 case NT_PPC_TM_CGPR
:
1052 if (features
.wordsize
== 4)
1053 regset
->size
= (features
.htm
?
1054 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
1056 regset
->size
= (features
.htm
?
1057 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
1059 case NT_PPC_TM_CFPR
:
1060 regset
->size
= (features
.htm
?
1061 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
1063 case NT_PPC_TM_CVMX
:
1064 regset
->size
= (features
.htm
?
1065 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
1067 case NT_PPC_TM_CVSX
:
1068 regset
->size
= (features
.htm
?
1069 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
1071 case NT_PPC_TM_CPPR
:
1072 regset
->size
= (features
.htm
?
1073 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
1075 case NT_PPC_TM_CDSCR
:
1076 regset
->size
= (features
.htm
?
1077 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1079 case NT_PPC_TM_CTAR
:
1080 regset
->size
= (features
.htm
?
1081 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1092 /* Implementation of linux_target_ops method "supports_tracepoints". */
1095 ppc_supports_tracepoints (void)
1100 /* Get the thread area address. This is used to recognize which
1101 thread is which when tracing with the in-process agent library. We
1102 don't read anything from the address, and treat it as opaque; it's
1103 the address itself that we assume is unique per-thread. */
1106 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1108 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1109 struct thread_info
*thr
= get_lwp_thread (lwp
);
1110 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1113 #ifdef __powerpc64__
1114 if (register_size (regcache
->tdesc
, 0) == 8)
1115 collect_register_by_name (regcache
, "r13", &tp
);
1118 collect_register_by_name (regcache
, "r2", &tp
);
1125 #ifdef __powerpc64__
1127 /* Older glibc doesn't provide this. */
1129 #ifndef EF_PPC64_ABI
1130 #define EF_PPC64_ABI 3
1133 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1137 is_elfv2_inferior (void)
1139 /* To be used as fallback if we're unable to determine the right result -
1140 assume inferior uses the same ABI as gdbserver. */
1142 const int def_res
= 1;
1144 const int def_res
= 0;
1149 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
1152 /* Assume ELF header is at the beginning of the page where program headers
1153 are located. If it doesn't look like one, bail. */
1155 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1156 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1159 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1164 /* Generate a ds-form instruction in BUF and return the number of bytes written
1167 | OPCD | RST | RA | DS |XO| */
1169 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1171 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1175 gdb_assert ((opcd
& ~0x3f) == 0);
1176 gdb_assert ((rst
& ~0x1f) == 0);
1177 gdb_assert ((ra
& ~0x1f) == 0);
1178 gdb_assert ((xo
& ~0x3) == 0);
1180 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1181 *buf
= (opcd
<< 26) | insn
;
1185 /* Followings are frequently used ds-form instructions. */
1187 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1188 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1189 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1190 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1192 /* Generate a d-form instruction in BUF.
1195 | OPCD | RST | RA | D | */
1198 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1202 gdb_assert ((opcd
& ~0x3f) == 0);
1203 gdb_assert ((rst
& ~0x1f) == 0);
1204 gdb_assert ((ra
& ~0x1f) == 0);
1206 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1207 *buf
= (opcd
<< 26) | insn
;
1211 /* Followings are frequently used d-form instructions. */
1213 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1214 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1215 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1216 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1217 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1218 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1219 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1220 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1221 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1223 /* Generate a xfx-form instruction in BUF and return the number of bytes
1227 | OPCD | RST | RI | XO |/| */
1230 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1233 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1235 gdb_assert ((opcd
& ~0x3f) == 0);
1236 gdb_assert ((rst
& ~0x1f) == 0);
1237 gdb_assert ((xo
& ~0x3ff) == 0);
1239 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1240 *buf
= (opcd
<< 26) | insn
;
1244 /* Followings are frequently used xfx-form instructions. */
1246 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1247 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1248 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1249 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1250 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1252 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1255 /* Generate a x-form instruction in BUF and return the number of bytes written.
1258 | OPCD | RST | RA | RB | XO |RC| */
1261 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1265 gdb_assert ((opcd
& ~0x3f) == 0);
1266 gdb_assert ((rst
& ~0x1f) == 0);
1267 gdb_assert ((ra
& ~0x1f) == 0);
1268 gdb_assert ((rb
& ~0x1f) == 0);
1269 gdb_assert ((xo
& ~0x3ff) == 0);
1270 gdb_assert ((rc
& ~1) == 0);
1272 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1273 *buf
= (opcd
<< 26) | insn
;
1277 /* Followings are frequently used x-form instructions. */
1279 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1280 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1281 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1282 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1283 /* Assume bf = cr7. */
1284 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1287 /* Generate a md-form instruction in BUF and return the number of bytes written.
1289 0 6 11 16 21 27 30 31 32
1290 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1293 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1297 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1298 unsigned int sh0_4
= sh
& 0x1f;
1299 unsigned int sh5
= (sh
>> 5) & 1;
1301 gdb_assert ((opcd
& ~0x3f) == 0);
1302 gdb_assert ((rs
& ~0x1f) == 0);
1303 gdb_assert ((ra
& ~0x1f) == 0);
1304 gdb_assert ((sh
& ~0x3f) == 0);
1305 gdb_assert ((mb
& ~0x3f) == 0);
1306 gdb_assert ((xo
& ~0x7) == 0);
1307 gdb_assert ((rc
& ~0x1) == 0);
1309 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1310 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1311 *buf
= (opcd
<< 26) | insn
;
1315 /* The following are frequently used md-form instructions. */
1317 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1318 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1319 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1320 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1322 /* Generate a i-form instruction in BUF and return the number of bytes written.
1325 | OPCD | LI |AA|LK| */
1328 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1332 gdb_assert ((opcd
& ~0x3f) == 0);
1334 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1335 *buf
= (opcd
<< 26) | insn
;
1339 /* The following are frequently used i-form instructions. */
1341 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1342 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1344 /* Generate a b-form instruction in BUF and return the number of bytes written.
1347 | OPCD | BO | BI | BD |AA|LK| */
1350 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1355 gdb_assert ((opcd
& ~0x3f) == 0);
1356 gdb_assert ((bo
& ~0x1f) == 0);
1357 gdb_assert ((bi
& ~0x1f) == 0);
1359 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1360 *buf
= (opcd
<< 26) | insn
;
1364 /* The following are frequently used b-form instructions. */
1365 /* Assume bi = cr7. */
1366 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1368 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1369 respectively. They are primary used for save/restore GPRs in jump-pad,
1370 not used for bytecode compiling. */
1372 #ifdef __powerpc64__
1373 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1374 GEN_LD (buf, rt, ra, si) : \
1375 GEN_LWZ (buf, rt, ra, si))
1376 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1377 GEN_STD (buf, rt, ra, si) : \
1378 GEN_STW (buf, rt, ra, si))
1380 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1381 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1384 /* Generate a sequence of instructions to load IMM in the register REG.
1385 Write the instructions in BUF and return the number of bytes written. */
1388 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1392 if ((imm
+ 32768) < 65536)
1394 /* li reg, imm[15:0] */
1395 p
+= GEN_LI (p
, reg
, imm
);
1397 else if ((imm
>> 32) == 0)
1399 /* lis reg, imm[31:16]
1400 ori reg, reg, imm[15:0]
1401 rldicl reg, reg, 0, 32 */
1402 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1403 if ((imm
& 0xffff) != 0)
1404 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1405 /* Clear upper 32-bit if sign-bit is set. */
1406 if (imm
& (1u << 31) && is_64
)
1407 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1412 /* lis reg, <imm[63:48]>
1413 ori reg, reg, <imm[48:32]>
1414 rldicr reg, reg, 32, 31
1415 oris reg, reg, <imm[31:16]>
1416 ori reg, reg, <imm[15:0]> */
1417 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1418 if (((imm
>> 32) & 0xffff) != 0)
1419 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1420 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1421 if (((imm
>> 16) & 0xffff) != 0)
1422 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1423 if ((imm
& 0xffff) != 0)
1424 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1430 /* Generate a sequence for atomically exchange at location LOCK.
1431 This code sequence clobbers r6, r7, r8. LOCK is the location for
1432 the atomic-xchg, OLD_VALUE is expected old value stored in the
1433 location, and R_NEW is a register for the new value. */
1436 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1439 const int r_lock
= 6;
1440 const int r_old
= 7;
1441 const int r_tmp
= 8;
1445 1: lwarx TMP, 0, LOCK
1451 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1452 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1454 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1455 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1456 p
+= GEN_BNE (p
, -8);
1457 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1458 p
+= GEN_BNE (p
, -16);
1463 /* Generate a sequence of instructions for calling a function
1464 at address of FN. Return the number of bytes are written in BUF. */
1467 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1471 /* Must be called by r12 for caller to calculate TOC address. */
1472 p
+= gen_limm (p
, 12, fn
, is_64
);
1475 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1476 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1477 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1479 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1480 *p
++ = 0x4e800421; /* bctrl */
1485 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1486 of instruction. This function is used to adjust pc-relative instructions
1490 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1495 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1496 op6
= PPC_OP6 (insn
);
1498 if (op6
== 18 && (insn
& 2) == 0)
1500 /* branch && AA = 0 */
1501 rel
= PPC_LI (insn
);
1502 newrel
= (oldloc
- *to
) + rel
;
1504 /* Out of range. Cannot relocate instruction. */
1505 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1508 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1510 else if (op6
== 16 && (insn
& 2) == 0)
1512 /* conditional branch && AA = 0 */
1514 /* If the new relocation is too big for even a 26-bit unconditional
1515 branch, there is nothing we can do. Just abort.
1517 Otherwise, if it can be fit in 16-bit conditional branch, just
1518 copy the instruction and relocate the address.
1520 If the it's big for conditional-branch (16-bit), try to invert the
1521 condition and jump with 26-bit branch. For example,
1532 After this transform, we are actually jump from *TO+4 instead of *TO,
1533 so check the relocation again because it will be 1-insn farther then
1534 before if *TO is after OLDLOC.
1537 For BDNZT (or so) is transformed from
1549 See also "BO field encodings". */
1551 rel
= PPC_BD (insn
);
1552 newrel
= (oldloc
- *to
) + rel
;
1554 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1555 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1556 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1560 /* Out of range. Cannot relocate instruction. */
1561 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1564 if ((PPC_BO (insn
) & 0x14) == 0x4)
1566 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1569 /* Jump over the unconditional branch. */
1570 insn
= (insn
& ~0xfffc) | 0x8;
1571 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1574 /* Build a unconditional branch and copy LK bit. */
1575 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1576 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1581 else if ((PPC_BO (insn
) & 0x14) == 0)
1583 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1584 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1588 /* Out of range. Cannot relocate instruction. */
1589 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1592 /* Copy BI field. */
1593 bf_insn
|= (insn
& 0x1f0000);
1595 /* Invert condition. */
1596 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1597 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1599 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1601 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1604 /* Build a unconditional branch and copy LK bit. */
1605 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1606 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1611 else /* (BO & 0x14) == 0x14, branch always. */
1613 /* Out of range. Cannot relocate instruction. */
1614 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1617 /* Build a unconditional branch and copy LK bit. */
1618 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1619 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1626 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1630 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1631 See target.h for details. */
1634 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1635 CORE_ADDR collector
,
1638 CORE_ADDR
*jump_entry
,
1639 CORE_ADDR
*trampoline
,
1640 ULONGEST
*trampoline_size
,
1641 unsigned char *jjump_pad_insn
,
1642 ULONGEST
*jjump_pad_insn_size
,
1643 CORE_ADDR
*adjusted_insn_addr
,
1644 CORE_ADDR
*adjusted_insn_addr_end
,
1650 CORE_ADDR buildaddr
= *jump_entry
;
1651 const CORE_ADDR entryaddr
= *jump_entry
;
1652 int rsz
, min_frame
, frame_size
, tp_reg
;
1653 #ifdef __powerpc64__
1654 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1655 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1656 int is_opd
= is_64
&& !is_elfv2_inferior ();
1658 int is_64
= 0, is_opd
= 0;
1661 #ifdef __powerpc64__
1664 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1667 frame_size
= (40 * rsz
) + min_frame
;
1675 frame_size
= (40 * rsz
) + min_frame
;
1677 #ifdef __powerpc64__
1681 /* Stack frame layout for this jump pad,
1683 High thread_area (r13/r2) |
1684 tpoint - collecting_t obj
1694 R0 - collected registers
1700 The code flow of this jump pad,
1705 4. Call gdb_collector
1706 5. Restore GPR and SPR
1708 7. Build a jump for back to the program
1709 8. Copy/relocate original instruction
1710 9. Build a jump for replacing orignal instruction. */
1712 /* Adjust stack pointer. */
1714 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1716 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1718 /* Store GPRs. Save R1 later, because it had just been modified, but
1719 we want the original value. */
1720 for (j
= 2; j
< 32; j
++)
1721 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1722 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1723 /* Set r0 to the original value of r1 before adjusting stack frame,
1724 and then save it. */
1725 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1726 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1728 /* Save CR, XER, LR, and CTR. */
1729 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1730 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1731 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1732 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1733 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1734 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1735 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1736 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1738 /* Save PC<tpaddr> */
1739 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1740 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1743 /* Setup arguments to collector. */
1744 /* Set r4 to collected registers. */
1745 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1746 /* Set r3 to TPOINT. */
1747 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1749 /* Prepare collecting_t object for lock. */
1750 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1751 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1752 /* Set R5 to collecting object. */
1753 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1755 p
+= GEN_LWSYNC (p
);
1756 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1757 p
+= GEN_LWSYNC (p
);
1759 /* Call to collector. */
1760 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1762 /* Simply write 0 to release the lock. */
1763 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1764 p
+= gen_limm (p
, 4, 0, is_64
);
1765 p
+= GEN_LWSYNC (p
);
1766 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1768 /* Restore stack and registers. */
1769 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1770 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1771 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1772 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1773 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1774 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1775 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1776 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1779 for (j
= 2; j
< 32; j
++)
1780 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1781 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1783 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1785 /* Flush instructions to inferior memory. */
1786 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1788 /* Now, insert the original instruction to execute in the jump pad. */
1789 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1790 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1791 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1793 /* Verify the relocation size. If should be 4 for normal copy,
1794 8 or 12 for some conditional branch. */
1795 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1796 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1798 sprintf (err
, "E.Unexpected instruction length = %d"
1799 "when relocate instruction.",
1800 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1804 buildaddr
= *adjusted_insn_addr_end
;
1806 /* Finally, write a jump back to the program. */
1807 offset
= (tpaddr
+ 4) - buildaddr
;
1808 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1810 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1811 "(offset 0x%x > 26-bit).", offset
);
1815 p
+= GEN_B (p
, offset
);
1816 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1817 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1819 /* The jump pad is now built. Wire in a jump to our jump pad. This
1820 is always done last (by our caller actually), so that we can
1821 install fast tracepoints with threads running. This relies on
1822 the agent's atomic write support. */
1823 offset
= entryaddr
- tpaddr
;
1824 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1826 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1827 "(offset 0x%x > 26-bit).", offset
);
1831 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1832 *jjump_pad_insn_size
= 4;
1837 /* Returns the minimum instruction length for installing a tracepoint. */
1840 ppc_get_min_fast_tracepoint_insn_len (void)
1845 /* Emits a given buffer into the target at current_insn_ptr. Length
1846 is in units of 32-bit words. */
1849 emit_insns (uint32_t *buf
, int n
)
1851 n
= n
* sizeof (uint32_t);
1852 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1853 current_insn_ptr
+= n
;
1856 #define __EMIT_ASM(NAME, INSNS) \
1859 extern uint32_t start_bcax_ ## NAME []; \
1860 extern uint32_t end_bcax_ ## NAME []; \
1861 emit_insns (start_bcax_ ## NAME, \
1862 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1863 __asm__ (".section .text.__ppcbcax\n\t" \
1864 "start_bcax_" #NAME ":\n\t" \
1866 "end_bcax_" #NAME ":\n\t" \
1870 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1871 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1875 Bytecode execution stack frame - 32-bit
1877 | LR save area (SP + 4)
1878 SP' -> +- Back chain (SP + 0)
1879 | Save r31 for access saved arguments
1880 | Save r30 for bytecode stack pointer
1881 | Save r4 for incoming argument *value
1882 | Save r3 for incoming argument regs
1883 r30 -> +- Bytecode execution stack
1885 | 64-byte (8 doublewords) at initial.
1886 | Expand stack as needed.
1889 | Some padding for minimum stack frame and 16-byte alignment.
1891 SP +- Back-chain (SP')
1897 r30 is the stack-pointer for bytecode machine.
1898 It should point to next-empty, so we can use LDU for pop.
1899 r3 is used for cache of the high part of TOP value.
1900 It was the first argument, pointer to regs.
1901 r4 is used for cache of the low part of TOP value.
1902 It was the second argument, pointer to the result.
1903 We should set *result = TOP after leaving this function.
1906 * To restore stack at epilogue
1908 * To check stack is big enough for bytecode execution.
1910 * To return execution result.
1915 /* Regardless of endian, register 3 is always high part, 4 is low part.
1916 These defines are used when the register pair is stored/loaded.
1917 Likewise, to simplify code, have a similiar define for 5:6. */
1919 #if __BYTE_ORDER == __LITTLE_ENDIAN
1920 #define TOP_FIRST "4"
1921 #define TOP_SECOND "3"
1922 #define TMP_FIRST "6"
1923 #define TMP_SECOND "5"
1925 #define TOP_FIRST "3"
1926 #define TOP_SECOND "4"
1927 #define TMP_FIRST "5"
1928 #define TMP_SECOND "6"
1931 /* Emit prologue in inferior memory. See above comments. */
1934 ppc_emit_prologue (void)
1936 EMIT_ASM (/* Save return address. */
1939 /* Adjust SP. 96 is the initial frame size. */
1941 /* Save r30 and incoming arguments. */
1942 "stw 31, 96-4(1) \n"
1943 "stw 30, 96-8(1) \n"
1944 "stw 4, 96-12(1) \n"
1945 "stw 3, 96-16(1) \n"
1946 /* Point r31 to original r1 for access arguments. */
1948 /* Set r30 to pointing stack-top. */
1950 /* Initial r3/TOP to 0. */
1955 /* Emit epilogue in inferior memory. See above comments. */
1958 ppc_emit_epilogue (void)
1960 EMIT_ASM (/* *result = TOP */
1962 "stw " TOP_FIRST
", 0(5) \n"
1963 "stw " TOP_SECOND
", 4(5) \n"
1964 /* Restore registers. */
1971 /* Return 0 for no-error. */
1977 /* TOP = stack[--sp] + TOP */
1982 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1983 "lwz " TMP_SECOND
", 4(30)\n"
1988 /* TOP = stack[--sp] - TOP */
1993 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1994 "lwz " TMP_SECOND
", 4(30) \n"
1996 "subfe 3, 3, 5 \n");
1999 /* TOP = stack[--sp] * TOP */
2004 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2005 "lwz " TMP_SECOND
", 4(30) \n"
2014 /* TOP = stack[--sp] << TOP */
2019 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2020 "lwz " TMP_SECOND
", 4(30) \n"
2021 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2022 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2023 "slw 5, 5, 4\n" /* Shift high part left */
2024 "slw 4, 6, 4\n" /* Shift low part left */
2025 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
2026 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
2028 "or 3, 7, 3\n"); /* Assemble high part */
2031 /* Top = stack[--sp] >> TOP
2032 (Arithmetic shift right) */
2035 ppc_emit_rsh_signed (void)
2037 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2038 "lwz " TMP_SECOND
", 4(30) \n"
2039 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2040 "sraw 3, 5, 4\n" /* Shift high part right */
2042 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
2043 "sraw 4, 5, 7\n" /* Shift high to low */
2046 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2047 "srw 4, 6, 4\n" /* Shift low part right */
2048 "slw 5, 5, 7\n" /* Shift high to low */
2049 "or 4, 4, 5\n" /* Assemble low part */
2053 /* Top = stack[--sp] >> TOP
2054 (Logical shift right) */
2057 ppc_emit_rsh_unsigned (void)
2059 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2060 "lwz " TMP_SECOND
", 4(30) \n"
2061 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2062 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2063 "srw 6, 6, 4\n" /* Shift low part right */
2064 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2065 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2067 "srw 3, 5, 4\n" /* Shift high part right */
2068 "or 4, 6, 7\n"); /* Assemble low part */
2071 /* Emit code for signed-extension specified by ARG. */
2074 ppc_emit_ext (int arg
)
2079 EMIT_ASM ("extsb 4, 4\n"
2083 EMIT_ASM ("extsh 4, 4\n"
2087 EMIT_ASM ("srawi 3, 4, 31");
2094 /* Emit code for zero-extension specified by ARG. */
2097 ppc_emit_zero_ext (int arg
)
2102 EMIT_ASM ("clrlwi 4,4,24\n"
2106 EMIT_ASM ("clrlwi 4,4,16\n"
2110 EMIT_ASM ("li 3, 0");
2118 i.e., TOP = (TOP == 0) ? 1 : 0; */
2121 ppc_emit_log_not (void)
2123 EMIT_ASM ("or 4, 3, 4 \n"
2129 /* TOP = stack[--sp] & TOP */
2132 ppc_emit_bit_and (void)
2134 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2135 "lwz " TMP_SECOND
", 4(30) \n"
2140 /* TOP = stack[--sp] | TOP */
2143 ppc_emit_bit_or (void)
2145 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2146 "lwz " TMP_SECOND
", 4(30) \n"
2151 /* TOP = stack[--sp] ^ TOP */
2154 ppc_emit_bit_xor (void)
2156 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2157 "lwz " TMP_SECOND
", 4(30) \n"
2163 i.e., TOP = ~(TOP | TOP) */
2166 ppc_emit_bit_not (void)
2168 EMIT_ASM ("nor 3, 3, 3 \n"
2172 /* TOP = stack[--sp] == TOP */
2175 ppc_emit_equal (void)
2177 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2178 "lwz " TMP_SECOND
", 4(30) \n"
2187 /* TOP = stack[--sp] < TOP
2188 (Signed comparison) */
2191 ppc_emit_less_signed (void)
2193 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2194 "lwz " TMP_SECOND
", 4(30) \n"
2197 /* CR6 bit 0 = low less and high equal */
2198 "crand 6*4+0, 6*4+0, 7*4+2\n"
2199 /* CR7 bit 0 = (low less and high equal) or high less */
2200 "cror 7*4+0, 7*4+0, 6*4+0\n"
2202 "rlwinm 4, 4, 29, 31, 31 \n"
2206 /* TOP = stack[--sp] < TOP
2207 (Unsigned comparison) */
2210 ppc_emit_less_unsigned (void)
2212 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2213 "lwz " TMP_SECOND
", 4(30) \n"
2216 /* CR6 bit 0 = low less and high equal */
2217 "crand 6*4+0, 6*4+0, 7*4+2\n"
2218 /* CR7 bit 0 = (low less and high equal) or high less */
2219 "cror 7*4+0, 7*4+0, 6*4+0\n"
2221 "rlwinm 4, 4, 29, 31, 31 \n"
2225 /* Access the memory address in TOP in size of SIZE.
2226 Zero-extend the read value. */
2229 ppc_emit_ref (int size
)
2234 EMIT_ASM ("lbz 4, 0(4)\n"
2238 EMIT_ASM ("lhz 4, 0(4)\n"
2242 EMIT_ASM ("lwz 4, 0(4)\n"
2246 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2247 EMIT_ASM ("lwz 3, 4(4)\n"
2250 EMIT_ASM ("lwz 3, 0(4)\n"
2259 ppc_emit_const (LONGEST num
)
2264 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2265 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2267 emit_insns (buf
, p
- buf
);
2268 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2271 /* Set TOP to the value of register REG by calling get_raw_reg function
2272 with two argument, collected buffer and register number. */
2275 ppc_emit_reg (int reg
)
2280 /* fctx->regs is passed in r3 and then saved in -16(31). */
2281 p
+= GEN_LWZ (p
, 3, 31, -16);
2282 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2283 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2285 emit_insns (buf
, p
- buf
);
2286 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2288 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2290 EMIT_ASM ("mr 5, 4\n"
2296 /* TOP = stack[--sp] */
2301 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2302 "lwz " TOP_SECOND
", 4(30) \n");
2305 /* stack[sp++] = TOP
2307 Because we may use up bytecode stack, expand 8 doublewords more
2311 ppc_emit_stack_flush (void)
2313 /* Make sure bytecode stack is big enough before push.
2314 Otherwise, expand 64-byte more. */
2316 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2317 " stw " TOP_SECOND
", 4(30)\n"
2318 " addi 5, 30, -(8 + 8) \n"
2321 " stwu 31, -64(1) \n"
2322 "1:addi 30, 30, -8 \n");
2325 /* Swap TOP and stack[sp-1] */
2328 ppc_emit_swap (void)
2330 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2331 "lwz " TMP_SECOND
", 12(30) \n"
2332 "stw " TOP_FIRST
", 8(30) \n"
2333 "stw " TOP_SECOND
", 12(30) \n"
2338 /* Discard N elements in the stack. Also used for ppc64. */
2341 ppc_emit_stack_adjust (int n
)
2353 p
+= GEN_ADDI (p
, 30, 30, n
);
2355 emit_insns (buf
, p
- buf
);
2356 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2359 /* Call function FN. */
2362 ppc_emit_call (CORE_ADDR fn
)
2367 p
+= gen_call (p
, fn
, 0, 0);
2369 emit_insns (buf
, p
- buf
);
2370 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2373 /* FN's prototype is `LONGEST(*fn)(int)'.
2378 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2383 /* Setup argument. arg1 is a 16-bit value. */
2384 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2385 p
+= gen_call (p
, fn
, 0, 0);
2387 emit_insns (buf
, p
- buf
);
2388 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2390 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2392 EMIT_ASM ("mr 5, 4\n"
2398 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2401 TOP should be preserved/restored before/after the call. */
2404 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2409 /* Save TOP. 0(30) is next-empty. */
2410 p
+= GEN_STW (p
, 3, 30, 0);
2411 p
+= GEN_STW (p
, 4, 30, 4);
2413 /* Setup argument. arg1 is a 16-bit value. */
2414 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2416 p
+= GEN_MR (p
, 5, 4);
2417 p
+= GEN_MR (p
, 6, 3);
2421 p
+= GEN_MR (p
, 5, 3);
2422 p
+= GEN_MR (p
, 6, 4);
2424 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2425 p
+= gen_call (p
, fn
, 0, 0);
2428 p
+= GEN_LWZ (p
, 3, 30, 0);
2429 p
+= GEN_LWZ (p
, 4, 30, 4);
2431 emit_insns (buf
, p
- buf
);
2432 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2435 /* Note in the following goto ops:
2437 When emitting goto, the target address is later relocated by
2438 write_goto_address. OFFSET_P is the offset of the branch instruction
2439 in the code sequence, and SIZE_P is how to relocate the instruction,
2440 recognized by ppc_write_goto_address. In current implementation,
2441 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2444 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2447 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2449 EMIT_ASM ("or. 3, 3, 4 \n"
2450 "lwzu " TOP_FIRST
", 8(30) \n"
2451 "lwz " TOP_SECOND
", 4(30) \n"
2460 /* Unconditional goto. Also used for ppc64. */
2463 ppc_emit_goto (int *offset_p
, int *size_p
)
2465 EMIT_ASM ("1:b 1b");
2473 /* Goto if stack[--sp] == TOP */
2476 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2478 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2479 "lwz " TMP_SECOND
", 4(30) \n"
2483 "lwzu " TOP_FIRST
", 8(30) \n"
2484 "lwz " TOP_SECOND
", 4(30) \n"
2493 /* Goto if stack[--sp] != TOP */
2496 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2498 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2499 "lwz " TMP_SECOND
", 4(30) \n"
2503 "lwzu " TOP_FIRST
", 8(30) \n"
2504 "lwz " TOP_SECOND
", 4(30) \n"
2513 /* Goto if stack[--sp] < TOP */
2516 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2518 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2519 "lwz " TMP_SECOND
", 4(30) \n"
2522 /* CR6 bit 0 = low less and high equal */
2523 "crand 6*4+0, 6*4+0, 7*4+2\n"
2524 /* CR7 bit 0 = (low less and high equal) or high less */
2525 "cror 7*4+0, 7*4+0, 6*4+0\n"
2526 "lwzu " TOP_FIRST
", 8(30) \n"
2527 "lwz " TOP_SECOND
", 4(30)\n"
2536 /* Goto if stack[--sp] <= TOP */
2539 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2541 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2542 "lwz " TMP_SECOND
", 4(30) \n"
2545 /* CR6 bit 0 = low less/equal and high equal */
2546 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2547 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2548 "cror 7*4+0, 7*4+0, 6*4+0\n"
2549 "lwzu " TOP_FIRST
", 8(30) \n"
2550 "lwz " TOP_SECOND
", 4(30)\n"
2559 /* Goto if stack[--sp] > TOP */
2562 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2564 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2565 "lwz " TMP_SECOND
", 4(30) \n"
2568 /* CR6 bit 0 = low greater and high equal */
2569 "crand 6*4+0, 6*4+1, 7*4+2\n"
2570 /* CR7 bit 0 = (low greater and high equal) or high greater */
2571 "cror 7*4+0, 7*4+1, 6*4+0\n"
2572 "lwzu " TOP_FIRST
", 8(30) \n"
2573 "lwz " TOP_SECOND
", 4(30)\n"
2582 /* Goto if stack[--sp] >= TOP */
2585 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2587 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2588 "lwz " TMP_SECOND
", 4(30) \n"
2591 /* CR6 bit 0 = low ge and high equal */
2592 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2593 /* CR7 bit 0 = (low ge and high equal) or high greater */
2594 "cror 7*4+0, 7*4+1, 6*4+0\n"
2595 "lwzu " TOP_FIRST
", 8(30)\n"
2596 "lwz " TOP_SECOND
", 4(30)\n"
2605 /* Relocate previous emitted branch instruction. FROM is the address
2606 of the branch instruction, TO is the goto target address, and SIZE
2607 if the value we set by *SIZE_P before. Currently, it is either
2608 24 or 14 of branch and conditional-branch instruction.
2609 Also used for ppc64. */
2612 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2614 long rel
= to
- from
;
2618 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2619 opcd
= (insn
>> 26) & 0x3f;
2625 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2627 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2631 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2633 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2640 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2643 /* Table of emit ops for 32-bit. */
2645 static struct emit_ops ppc_emit_ops_impl
=
2653 ppc_emit_rsh_signed
,
2654 ppc_emit_rsh_unsigned
,
2662 ppc_emit_less_signed
,
2663 ppc_emit_less_unsigned
,
2667 ppc_write_goto_address
,
2672 ppc_emit_stack_flush
,
2675 ppc_emit_stack_adjust
,
2676 ppc_emit_int_call_1
,
2677 ppc_emit_void_call_2
,
2686 #ifdef __powerpc64__
2690 Bytecode execution stack frame - 64-bit
2692 | LR save area (SP + 16)
2693 | CR save area (SP + 8)
2694 SP' -> +- Back chain (SP + 0)
2695 | Save r31 for access saved arguments
2696 | Save r30 for bytecode stack pointer
2697 | Save r4 for incoming argument *value
2698 | Save r3 for incoming argument regs
2699 r30 -> +- Bytecode execution stack
2701 | 64-byte (8 doublewords) at initial.
2702 | Expand stack as needed.
2705 | Some padding for minimum stack frame.
2707 SP +- Back-chain (SP')
2710 = 112 + (4 * 8) + 64
2713 r30 is the stack-pointer for bytecode machine.
2714 It should point to next-empty, so we can use LDU for pop.
2715 r3 is used for cache of TOP value.
2716 It was the first argument, pointer to regs.
2717 r4 is the second argument, pointer to the result.
2718 We should set *result = TOP after leaving this function.
2721 * To restore stack at epilogue
2723 * To check stack is big enough for bytecode execution.
2724 => r30 - 8 > SP + 112
2725 * To return execution result.
2730 /* Emit prologue in inferior memory. See above comments. */
2733 ppc64v1_emit_prologue (void)
2735 /* On ELFv1, function pointers really point to function descriptor,
2736 so emit one here. We don't care about contents of words 1 and 2,
2737 so let them just overlap out code. */
2738 uint64_t opd
= current_insn_ptr
+ 8;
2741 /* Mind the strict aliasing rules. */
2742 memcpy (buf
, &opd
, sizeof buf
);
2744 EMIT_ASM (/* Save return address. */
2747 /* Save r30 and incoming arguments. */
2752 /* Point r31 to current r1 for access arguments. */
2754 /* Adjust SP. 208 is the initial frame size. */
2755 "stdu 1, -208(1) \n"
2756 /* Set r30 to pointing stack-top. */
2757 "addi 30, 1, 168 \n"
2758 /* Initial r3/TOP to 0. */
2762 /* Emit prologue in inferior memory. See above comments. */
2765 ppc64v2_emit_prologue (void)
2767 EMIT_ASM (/* Save return address. */
2770 /* Save r30 and incoming arguments. */
2775 /* Point r31 to current r1 for access arguments. */
2777 /* Adjust SP. 208 is the initial frame size. */
2778 "stdu 1, -208(1) \n"
2779 /* Set r30 to pointing stack-top. */
2780 "addi 30, 1, 168 \n"
2781 /* Initial r3/TOP to 0. */
2785 /* Emit epilogue in inferior memory. See above comments. */
2788 ppc64_emit_epilogue (void)
2790 EMIT_ASM (/* Restore SP. */
2795 /* Restore registers. */
2800 /* Return 0 for no-error. */
2806 /* TOP = stack[--sp] + TOP */
2809 ppc64_emit_add (void)
2811 EMIT_ASM ("ldu 4, 8(30) \n"
2815 /* TOP = stack[--sp] - TOP */
2818 ppc64_emit_sub (void)
2820 EMIT_ASM ("ldu 4, 8(30) \n"
2824 /* TOP = stack[--sp] * TOP */
2827 ppc64_emit_mul (void)
2829 EMIT_ASM ("ldu 4, 8(30) \n"
2830 "mulld 3, 4, 3 \n");
2833 /* TOP = stack[--sp] << TOP */
2836 ppc64_emit_lsh (void)
2838 EMIT_ASM ("ldu 4, 8(30) \n"
2842 /* Top = stack[--sp] >> TOP
2843 (Arithmetic shift right) */
2846 ppc64_emit_rsh_signed (void)
2848 EMIT_ASM ("ldu 4, 8(30) \n"
2852 /* Top = stack[--sp] >> TOP
2853 (Logical shift right) */
2856 ppc64_emit_rsh_unsigned (void)
2858 EMIT_ASM ("ldu 4, 8(30) \n"
2862 /* Emit code for signed-extension specified by ARG. */
2865 ppc64_emit_ext (int arg
)
2870 EMIT_ASM ("extsb 3, 3");
2873 EMIT_ASM ("extsh 3, 3");
2876 EMIT_ASM ("extsw 3, 3");
2883 /* Emit code for zero-extension specified by ARG. */
2886 ppc64_emit_zero_ext (int arg
)
2891 EMIT_ASM ("rldicl 3,3,0,56");
2894 EMIT_ASM ("rldicl 3,3,0,48");
2897 EMIT_ASM ("rldicl 3,3,0,32");
2905 i.e., TOP = (TOP == 0) ? 1 : 0; */
2908 ppc64_emit_log_not (void)
2910 EMIT_ASM ("cntlzd 3, 3 \n"
2914 /* TOP = stack[--sp] & TOP */
2917 ppc64_emit_bit_and (void)
2919 EMIT_ASM ("ldu 4, 8(30) \n"
2923 /* TOP = stack[--sp] | TOP */
2926 ppc64_emit_bit_or (void)
2928 EMIT_ASM ("ldu 4, 8(30) \n"
2932 /* TOP = stack[--sp] ^ TOP */
2935 ppc64_emit_bit_xor (void)
2937 EMIT_ASM ("ldu 4, 8(30) \n"
2942 i.e., TOP = ~(TOP | TOP) */
2945 ppc64_emit_bit_not (void)
2947 EMIT_ASM ("nor 3, 3, 3 \n");
2950 /* TOP = stack[--sp] == TOP */
2953 ppc64_emit_equal (void)
2955 EMIT_ASM ("ldu 4, 8(30) \n"
2961 /* TOP = stack[--sp] < TOP
2962 (Signed comparison) */
2965 ppc64_emit_less_signed (void)
2967 EMIT_ASM ("ldu 4, 8(30) \n"
2970 "rlwinm 3, 3, 29, 31, 31 \n");
2973 /* TOP = stack[--sp] < TOP
2974 (Unsigned comparison) */
2977 ppc64_emit_less_unsigned (void)
2979 EMIT_ASM ("ldu 4, 8(30) \n"
2982 "rlwinm 3, 3, 29, 31, 31 \n");
2985 /* Access the memory address in TOP in size of SIZE.
2986 Zero-extend the read value. */
2989 ppc64_emit_ref (int size
)
2994 EMIT_ASM ("lbz 3, 0(3)");
2997 EMIT_ASM ("lhz 3, 0(3)");
3000 EMIT_ASM ("lwz 3, 0(3)");
3003 EMIT_ASM ("ld 3, 0(3)");
3011 ppc64_emit_const (LONGEST num
)
3016 p
+= gen_limm (p
, 3, num
, 1);
3018 emit_insns (buf
, p
- buf
);
3019 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3022 /* Set TOP to the value of register REG by calling get_raw_reg function
3023 with two argument, collected buffer and register number. */
3026 ppc64v1_emit_reg (int reg
)
3031 /* fctx->regs is passed in r3 and then saved in 176(1). */
3032 p
+= GEN_LD (p
, 3, 31, -32);
3033 p
+= GEN_LI (p
, 4, reg
);
3034 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3035 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
3036 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3038 emit_insns (buf
, p
- buf
);
3039 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3042 /* Likewise, for ELFv2. */
3045 ppc64v2_emit_reg (int reg
)
3050 /* fctx->regs is passed in r3 and then saved in 176(1). */
3051 p
+= GEN_LD (p
, 3, 31, -32);
3052 p
+= GEN_LI (p
, 4, reg
);
3053 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3054 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
3055 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3057 emit_insns (buf
, p
- buf
);
3058 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3061 /* TOP = stack[--sp] */
3064 ppc64_emit_pop (void)
3066 EMIT_ASM ("ldu 3, 8(30)");
3069 /* stack[sp++] = TOP
3071 Because we may use up bytecode stack, expand 8 doublewords more
3075 ppc64_emit_stack_flush (void)
3077 /* Make sure bytecode stack is big enough before push.
3078 Otherwise, expand 64-byte more. */
3080 EMIT_ASM (" std 3, 0(30) \n"
3081 " addi 4, 30, -(112 + 8) \n"
3084 " stdu 31, -64(1) \n"
3085 "1:addi 30, 30, -8 \n");
3088 /* Swap TOP and stack[sp-1] */
3091 ppc64_emit_swap (void)
3093 EMIT_ASM ("ld 4, 8(30) \n"
3098 /* Call function FN - ELFv1. */
3101 ppc64v1_emit_call (CORE_ADDR fn
)
3106 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3107 p
+= gen_call (p
, fn
, 1, 1);
3108 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3110 emit_insns (buf
, p
- buf
);
3111 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3114 /* Call function FN - ELFv2. */
3117 ppc64v2_emit_call (CORE_ADDR fn
)
3122 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3123 p
+= gen_call (p
, fn
, 1, 0);
3124 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3126 emit_insns (buf
, p
- buf
);
3127 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3130 /* FN's prototype is `LONGEST(*fn)(int)'.
3135 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3140 /* Setup argument. arg1 is a 16-bit value. */
3141 p
+= gen_limm (p
, 3, arg1
, 1);
3142 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3143 p
+= gen_call (p
, fn
, 1, 1);
3144 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3146 emit_insns (buf
, p
- buf
);
3147 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3150 /* Likewise for ELFv2. */
3153 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3158 /* Setup argument. arg1 is a 16-bit value. */
3159 p
+= gen_limm (p
, 3, arg1
, 1);
3160 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3161 p
+= gen_call (p
, fn
, 1, 0);
3162 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3164 emit_insns (buf
, p
- buf
);
3165 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3168 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3171 TOP should be preserved/restored before/after the call. */
3174 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3179 /* Save TOP. 0(30) is next-empty. */
3180 p
+= GEN_STD (p
, 3, 30, 0);
3182 /* Setup argument. arg1 is a 16-bit value. */
3183 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3184 p
+= gen_limm (p
, 3, arg1
, 1);
3185 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3186 p
+= gen_call (p
, fn
, 1, 1);
3187 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3190 p
+= GEN_LD (p
, 3, 30, 0);
3192 emit_insns (buf
, p
- buf
);
3193 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3196 /* Likewise for ELFv2. */
3199 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3204 /* Save TOP. 0(30) is next-empty. */
3205 p
+= GEN_STD (p
, 3, 30, 0);
3207 /* Setup argument. arg1 is a 16-bit value. */
3208 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3209 p
+= gen_limm (p
, 3, arg1
, 1);
3210 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3211 p
+= gen_call (p
, fn
, 1, 0);
3212 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3215 p
+= GEN_LD (p
, 3, 30, 0);
3217 emit_insns (buf
, p
- buf
);
3218 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3221 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3224 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3226 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3236 /* Goto if stack[--sp] == TOP */
3239 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3241 EMIT_ASM ("ldu 4, 8(30) \n"
3252 /* Goto if stack[--sp] != TOP */
3255 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3257 EMIT_ASM ("ldu 4, 8(30) \n"
3268 /* Goto if stack[--sp] < TOP */
3271 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3273 EMIT_ASM ("ldu 4, 8(30) \n"
3284 /* Goto if stack[--sp] <= TOP */
3287 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3289 EMIT_ASM ("ldu 4, 8(30) \n"
3300 /* Goto if stack[--sp] > TOP */
3303 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3305 EMIT_ASM ("ldu 4, 8(30) \n"
3316 /* Goto if stack[--sp] >= TOP */
3319 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3321 EMIT_ASM ("ldu 4, 8(30) \n"
3332 /* Table of emit ops for 64-bit ELFv1. */
3334 static struct emit_ops ppc64v1_emit_ops_impl
=
3336 ppc64v1_emit_prologue
,
3337 ppc64_emit_epilogue
,
3342 ppc64_emit_rsh_signed
,
3343 ppc64_emit_rsh_unsigned
,
3351 ppc64_emit_less_signed
,
3352 ppc64_emit_less_unsigned
,
3356 ppc_write_goto_address
,
3361 ppc64_emit_stack_flush
,
3362 ppc64_emit_zero_ext
,
3364 ppc_emit_stack_adjust
,
3365 ppc64v1_emit_int_call_1
,
3366 ppc64v1_emit_void_call_2
,
3375 /* Table of emit ops for 64-bit ELFv2. */
3377 static struct emit_ops ppc64v2_emit_ops_impl
=
3379 ppc64v2_emit_prologue
,
3380 ppc64_emit_epilogue
,
3385 ppc64_emit_rsh_signed
,
3386 ppc64_emit_rsh_unsigned
,
3394 ppc64_emit_less_signed
,
3395 ppc64_emit_less_unsigned
,
3399 ppc_write_goto_address
,
3404 ppc64_emit_stack_flush
,
3405 ppc64_emit_zero_ext
,
3407 ppc_emit_stack_adjust
,
3408 ppc64v2_emit_int_call_1
,
3409 ppc64v2_emit_void_call_2
,
3420 /* Implementation of linux_target_ops method "emit_ops". */
3422 static struct emit_ops
*
3425 #ifdef __powerpc64__
3426 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3428 if (register_size (regcache
->tdesc
, 0) == 8)
3430 if (is_elfv2_inferior ())
3431 return &ppc64v2_emit_ops_impl
;
3433 return &ppc64v1_emit_ops_impl
;
3436 return &ppc_emit_ops_impl
;
3439 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3442 ppc_get_ipa_tdesc_idx (void)
3444 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3445 const struct target_desc
*tdesc
= regcache
->tdesc
;
3447 #ifdef __powerpc64__
3448 if (tdesc
== tdesc_powerpc_64l
)
3449 return PPC_TDESC_BASE
;
3450 if (tdesc
== tdesc_powerpc_altivec64l
)
3451 return PPC_TDESC_ALTIVEC
;
3452 if (tdesc
== tdesc_powerpc_cell64l
)
3453 return PPC_TDESC_CELL
;
3454 if (tdesc
== tdesc_powerpc_vsx64l
)
3455 return PPC_TDESC_VSX
;
3456 if (tdesc
== tdesc_powerpc_isa205_64l
)
3457 return PPC_TDESC_ISA205
;
3458 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3459 return PPC_TDESC_ISA205_ALTIVEC
;
3460 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3461 return PPC_TDESC_ISA205_VSX
;
3462 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3463 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3464 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3465 return PPC_TDESC_ISA207_VSX
;
3466 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3467 return PPC_TDESC_ISA207_HTM_VSX
;
3470 if (tdesc
== tdesc_powerpc_32l
)
3471 return PPC_TDESC_BASE
;
3472 if (tdesc
== tdesc_powerpc_altivec32l
)
3473 return PPC_TDESC_ALTIVEC
;
3474 if (tdesc
== tdesc_powerpc_cell32l
)
3475 return PPC_TDESC_CELL
;
3476 if (tdesc
== tdesc_powerpc_vsx32l
)
3477 return PPC_TDESC_VSX
;
3478 if (tdesc
== tdesc_powerpc_isa205_32l
)
3479 return PPC_TDESC_ISA205
;
3480 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3481 return PPC_TDESC_ISA205_ALTIVEC
;
3482 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3483 return PPC_TDESC_ISA205_VSX
;
3484 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3485 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3486 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3487 return PPC_TDESC_ISA207_VSX
;
3488 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3489 return PPC_TDESC_ISA207_HTM_VSX
;
3490 if (tdesc
== tdesc_powerpc_e500l
)
3491 return PPC_TDESC_E500
;
3496 struct linux_target_ops the_low_target
= {
3499 ppc_cannot_fetch_register
,
3500 ppc_cannot_store_register
,
3501 NULL
, /* fetch_register */
3504 NULL
, /* breakpoint_kind_from_pc */
3505 ppc_sw_breakpoint_from_kind
,
3509 ppc_supports_z_point_type
,
3514 ppc_collect_ptrace_register
,
3515 ppc_supply_ptrace_register
,
3516 NULL
, /* siginfo_fixup */
3517 NULL
, /* new_process */
3518 NULL
, /* delete_process */
3519 NULL
, /* new_thread */
3520 NULL
, /* delete_thread */
3521 NULL
, /* new_fork */
3522 NULL
, /* prepare_to_resume */
3523 NULL
, /* process_qsupported */
3524 ppc_supports_tracepoints
,
3525 ppc_get_thread_area
,
3526 ppc_install_fast_tracepoint_jump_pad
,
3528 ppc_get_min_fast_tracepoint_insn_len
,
3529 NULL
, /* supports_range_stepping */
3530 NULL
, /* breakpoint_kind_from_current_state */
3531 ppc_supports_hardware_single_step
,
3532 NULL
, /* get_syscall_trapinfo */
3533 ppc_get_ipa_tdesc_idx
,
3537 initialize_low_arch (void)
3539 /* Initialize the Linux target descriptions. */
3541 init_registers_powerpc_32l ();
3542 init_registers_powerpc_altivec32l ();
3543 init_registers_powerpc_cell32l ();
3544 init_registers_powerpc_vsx32l ();
3545 init_registers_powerpc_isa205_32l ();
3546 init_registers_powerpc_isa205_altivec32l ();
3547 init_registers_powerpc_isa205_vsx32l ();
3548 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3549 init_registers_powerpc_isa207_vsx32l ();
3550 init_registers_powerpc_isa207_htm_vsx32l ();
3551 init_registers_powerpc_e500l ();
3553 init_registers_powerpc_64l ();
3554 init_registers_powerpc_altivec64l ();
3555 init_registers_powerpc_cell64l ();
3556 init_registers_powerpc_vsx64l ();
3557 init_registers_powerpc_isa205_64l ();
3558 init_registers_powerpc_isa205_altivec64l ();
3559 init_registers_powerpc_isa205_vsx64l ();
3560 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3561 init_registers_powerpc_isa207_vsx64l ();
3562 init_registers_powerpc_isa207_htm_vsx64l ();
3565 initialize_regsets_info (&ppc_regsets_info
);