1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "linux-ppc-tdesc-init.h"
33 #include "tracepoint.h"
35 #define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37 #define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
46 /* Holds the AT_HWCAP auxv entry. */
48 static unsigned long ppc_hwcap
;
50 /* Holds the AT_HWCAP2 auxv entry. */
52 static unsigned long ppc_hwcap2
;
55 #define ppc_num_regs 73
58 /* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60 static int ppc_regmap
[] =
61 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
62 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
63 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
64 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
65 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
66 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
67 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
68 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
69 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
70 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
71 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
72 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
73 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
74 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
75 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
76 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
77 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
78 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
79 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
81 /* Currently, don't check/send MQ. */
82 static int ppc_regmap
[] =
83 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
84 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
85 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
86 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
87 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
88 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
89 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
90 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
91 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
92 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
93 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
94 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
95 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
96 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
97 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
98 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
99 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
100 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
101 PT_ORIG_R3
* 4, PT_TRAP
* 4
104 static int ppc_regmap_e500
[] =
105 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
106 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
107 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
108 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
109 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
110 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
111 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
112 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
121 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
122 PT_CTR
* 4, PT_XER
* 4, -1,
123 PT_ORIG_R3
* 4, PT_TRAP
* 4
127 /* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
131 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
133 void *buf
= alloca (regsetsize
);
137 iov
.iov_len
= regsetsize
;
139 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
146 ppc_cannot_store_register (int regno
)
148 const struct target_desc
*tdesc
= current_process ()->tdesc
;
150 #ifndef __powerpc64__
151 /* Some kernels do not allow us to store fpscr. */
152 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
153 && regno
== find_regno (tdesc
, "fpscr"))
157 /* Some kernels do not allow us to store orig_r3 or trap. */
158 if (regno
== find_regno (tdesc
, "orig_r3")
159 || regno
== find_regno (tdesc
, "trap"))
166 ppc_cannot_fetch_register (int regno
)
172 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
174 memset (buf
, 0, sizeof (long));
176 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache
, regno
, buf
);
181 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size
= register_size (regcache
->tdesc
, regno
);
188 if (size
< sizeof (long))
189 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
191 collect_register (regcache
, regno
, buf
);
194 perror_with_name ("Unexpected byte order");
198 ppc_supply_ptrace_register (struct regcache
*regcache
,
199 int regno
, const char *buf
)
201 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache
, regno
, buf
);
206 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size
= register_size (regcache
->tdesc
, regno
);
213 if (size
< sizeof (long))
214 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
216 supply_register (regcache
, regno
, buf
);
219 perror_with_name ("Unexpected byte order");
223 #define INSTR_SC 0x44000002
224 #define NR_spu_run 0x0116
226 /* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
230 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
236 if (register_size (regcache
->tdesc
, 0) == 4)
238 unsigned int pc
, r0
, r3
, r4
;
239 collect_register_by_name (regcache
, "pc", &pc
);
240 collect_register_by_name (regcache
, "r0", &r0
);
241 collect_register_by_name (regcache
, "orig_r3", &r3
);
242 collect_register_by_name (regcache
, "r4", &r4
);
243 curr_pc
= (CORE_ADDR
) pc
;
246 *addr
= (CORE_ADDR
) r4
;
250 unsigned long pc
, r0
, r3
, r4
;
251 collect_register_by_name (regcache
, "pc", &pc
);
252 collect_register_by_name (regcache
, "r0", &r0
);
253 collect_register_by_name (regcache
, "orig_r3", &r3
);
254 collect_register_by_name (regcache
, "r4", &r4
);
255 curr_pc
= (CORE_ADDR
) pc
;
258 *addr
= (CORE_ADDR
) r4
;
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target
->read_memory
) (curr_pc
- 4,
263 (unsigned char *) &curr_insn
, 4) != 0)
265 /* It should be a "sc" instruction. */
266 if (curr_insn
!= INSTR_SC
)
268 /* System call number should be NR_spu_run. */
269 if (curr_r0
!= NR_spu_run
)
276 ppc_get_pc (struct regcache
*regcache
)
281 if (parse_spufs_run (regcache
, &fd
, &addr
))
284 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
285 return ((CORE_ADDR
)1 << 63)
286 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
288 else if (register_size (regcache
->tdesc
, 0) == 4)
291 collect_register_by_name (regcache
, "pc", &pc
);
292 return (CORE_ADDR
) pc
;
297 collect_register_by_name (regcache
, "pc", &pc
);
298 return (CORE_ADDR
) pc
;
303 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
308 if (parse_spufs_run (regcache
, &fd
, &addr
))
310 unsigned int newpc
= pc
;
311 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
313 else if (register_size (regcache
->tdesc
, 0) == 4)
315 unsigned int newpc
= pc
;
316 supply_register_by_name (regcache
, "pc", &newpc
);
320 unsigned long newpc
= pc
;
321 supply_register_by_name (regcache
, "pc", &newpc
);
327 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
329 const struct target_desc
*tdesc
= current_process ()->tdesc
;
330 int wordsize
= register_size (tdesc
, 0);
331 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
334 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
338 unsigned int *data_p
= (unsigned int *)data
;
339 if (data_p
[0] == type
)
347 unsigned long *data_p
= (unsigned long *)data
;
348 if (data_p
[0] == type
)
355 offset
+= 2 * wordsize
;
362 #ifndef __powerpc64__
363 static int ppc_regmap_adjusted
;
367 /* Correct in either endianness.
368 This instruction is "twge r2, r2", which GDB uses as a software
370 static const unsigned int ppc_breakpoint
= 0x7d821008;
371 #define ppc_breakpoint_len 4
373 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
375 static const gdb_byte
*
376 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
378 *size
= ppc_breakpoint_len
;
379 return (const gdb_byte
*) &ppc_breakpoint
;
383 ppc_breakpoint_at (CORE_ADDR where
)
387 if (where
& ((CORE_ADDR
)1 << 63))
390 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
391 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
392 NULL
, where
& 0xffffffff, 4);
398 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
399 if (insn
== ppc_breakpoint
)
401 /* If necessary, recognize more trap instructions here. GDB only uses
408 /* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
415 ppc_supports_z_point_type (char z_type
)
422 case Z_PACKET_WRITE_WP
:
423 case Z_PACKET_ACCESS_WP
:
429 /* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
433 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
434 int size
, struct raw_breakpoint
*bp
)
438 case raw_bkpt_type_sw
:
439 return insert_memory_breakpoint (bp
);
441 case raw_bkpt_type_hw
:
442 case raw_bkpt_type_write_wp
:
443 case raw_bkpt_type_access_wp
:
450 /* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
454 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
455 int size
, struct raw_breakpoint
*bp
)
459 case raw_bkpt_type_sw
:
460 return remove_memory_breakpoint (bp
);
462 case raw_bkpt_type_hw
:
463 case raw_bkpt_type_write_wp
:
464 case raw_bkpt_type_access_wp
:
471 /* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
474 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
478 for (i
= 0; i
< 32; i
++)
479 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
481 for (i
= 64; i
< 70; i
++)
482 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
484 for (i
= 71; i
< 73; i
++)
485 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
488 /* Program Priority Register regset fill function. */
491 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
493 char *ppr
= (char *) buf
;
495 collect_register_by_name (regcache
, "ppr", ppr
);
498 /* Program Priority Register regset store function. */
501 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
503 const char *ppr
= (const char *) buf
;
505 supply_register_by_name (regcache
, "ppr", ppr
);
508 /* Data Stream Control Register regset fill function. */
511 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
513 char *dscr
= (char *) buf
;
515 collect_register_by_name (regcache
, "dscr", dscr
);
518 /* Data Stream Control Register regset store function. */
521 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
523 const char *dscr
= (const char *) buf
;
525 supply_register_by_name (regcache
, "dscr", dscr
);
528 /* Target Address Register regset fill function. */
531 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
533 char *tar
= (char *) buf
;
535 collect_register_by_name (regcache
, "tar", tar
);
538 /* Target Address Register regset store function. */
541 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
543 const char *tar
= (const char *) buf
;
545 supply_register_by_name (regcache
, "tar", tar
);
549 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
552 char *regset
= (char *) buf
;
554 base
= find_regno (regcache
->tdesc
, "vs0h");
555 for (i
= 0; i
< 32; i
++)
556 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
560 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
563 const char *regset
= (const char *) buf
;
565 base
= find_regno (regcache
->tdesc
, "vs0h");
566 for (i
= 0; i
< 32; i
++)
567 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
571 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
574 char *regset
= (char *) buf
;
577 base
= find_regno (regcache
->tdesc
, "vr0");
578 for (i
= 0; i
< 32; i
++)
579 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
581 if (__BYTE_ORDER
== __BIG_ENDIAN
)
584 collect_register_by_name (regcache
, "vscr",
585 ®set
[32 * 16 + vscr_offset
]);
587 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
591 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
594 const char *regset
= (const char *) buf
;
597 base
= find_regno (regcache
->tdesc
, "vr0");
598 for (i
= 0; i
< 32; i
++)
599 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
601 if (__BYTE_ORDER
== __BIG_ENDIAN
)
604 supply_register_by_name (regcache
, "vscr",
605 ®set
[32 * 16 + vscr_offset
]);
606 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
609 struct gdb_evrregset_t
611 unsigned long evr
[32];
612 unsigned long long acc
;
613 unsigned long spefscr
;
617 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
620 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
622 ev0
= find_regno (regcache
->tdesc
, "ev0h");
623 for (i
= 0; i
< 32; i
++)
624 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
626 collect_register_by_name (regcache
, "acc", ®set
->acc
);
627 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
631 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
634 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
636 ev0
= find_regno (regcache
->tdesc
, "ev0h");
637 for (i
= 0; i
< 32; i
++)
638 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
640 supply_register_by_name (regcache
, "acc", ®set
->acc
);
641 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
644 /* Support for hardware single step. */
647 ppc_supports_hardware_single_step (void)
652 static struct regset_info ppc_regsets
[] = {
653 /* List the extra register sets before GENERAL_REGS. That way we will
654 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
655 general registers. Some kernels support these, but not the newer
656 PPC_PTRACE_GETREGS. */
657 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
658 ppc_fill_tarregset
, ppc_store_tarregset
},
659 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
660 ppc_fill_pprregset
, ppc_store_pprregset
},
661 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
662 ppc_fill_dscrregset
, ppc_store_dscrregset
},
663 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
664 ppc_fill_vsxregset
, ppc_store_vsxregset
},
665 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
666 ppc_fill_vrregset
, ppc_store_vrregset
},
667 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
668 ppc_fill_evrregset
, ppc_store_evrregset
},
669 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
673 static struct usrregs_info ppc_usrregs_info
=
679 static struct regsets_info ppc_regsets_info
=
681 ppc_regsets
, /* regsets */
683 NULL
, /* disabled_regsets */
686 static struct regs_info regs_info
=
688 NULL
, /* regset_bitmap */
693 static const struct regs_info
*
700 ppc_arch_setup (void)
702 const struct target_desc
*tdesc
;
703 struct regset_info
*regset
;
704 struct ppc_linux_features features
= ppc_linux_no_features
;
706 int tid
= lwpid_of (current_thread
);
708 features
.wordsize
= ppc_linux_target_wordsize (tid
);
710 if (features
.wordsize
== 4)
711 tdesc
= tdesc_powerpc_32l
;
713 tdesc
= tdesc_powerpc_64l
;
715 current_process ()->tdesc
= tdesc
;
717 /* The value of current_process ()->tdesc needs to be set for this
719 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
720 ppc_get_auxv (AT_HWCAP2
, &ppc_hwcap2
);
722 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
724 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
727 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
728 features
.altivec
= true;
730 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
731 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
732 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
734 features
.ppr_dscr
= true;
735 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
736 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
737 && ppc_check_regset (tid
, NT_PPC_TAR
,
738 PPC_LINUX_SIZEOF_TARREGSET
))
739 features
.isa207
= true;
742 if (ppc_hwcap
& PPC_FEATURE_CELL
)
743 features
.cell
= true;
745 tdesc
= ppc_linux_match_description (features
);
747 /* On 32-bit machines, check for SPE registers.
748 Set the low target's regmap field as appropriately. */
749 #ifndef __powerpc64__
750 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
751 tdesc
= tdesc_powerpc_e500l
;
753 if (!ppc_regmap_adjusted
)
755 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
756 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
758 /* If the FPSCR is 64-bit wide, we need to fetch the whole
759 64-bit slot and not just its second word. The PT_FPSCR
760 supplied in a 32-bit GDB compilation doesn't reflect
762 if (register_size (tdesc
, 70) == 8)
763 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
765 ppc_regmap_adjusted
= 1;
769 current_process ()->tdesc
= tdesc
;
771 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
772 switch (regset
->get_request
)
774 case PTRACE_GETVRREGS
:
775 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
777 case PTRACE_GETVSXREGS
:
778 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
780 case PTRACE_GETEVRREGS
:
781 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
782 regset
->size
= 32 * 4 + 8 + 4;
786 case PTRACE_GETREGSET
:
787 switch (regset
->nt_type
)
790 regset
->size
= (features
.ppr_dscr
?
791 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
794 regset
->size
= (features
.ppr_dscr
?
795 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
798 regset
->size
= (features
.isa207
?
799 PPC_LINUX_SIZEOF_TARREGSET
: 0);
810 /* Implementation of linux_target_ops method "supports_tracepoints". */
813 ppc_supports_tracepoints (void)
818 /* Get the thread area address. This is used to recognize which
819 thread is which when tracing with the in-process agent library. We
820 don't read anything from the address, and treat it as opaque; it's
821 the address itself that we assume is unique per-thread. */
824 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
826 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
827 struct thread_info
*thr
= get_lwp_thread (lwp
);
828 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
832 if (register_size (regcache
->tdesc
, 0) == 8)
833 collect_register_by_name (regcache
, "r13", &tp
);
836 collect_register_by_name (regcache
, "r2", &tp
);
845 /* Older glibc doesn't provide this. */
848 #define EF_PPC64_ABI 3
851 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
855 is_elfv2_inferior (void)
857 /* To be used as fallback if we're unable to determine the right result -
858 assume inferior uses the same ABI as gdbserver. */
860 const int def_res
= 1;
862 const int def_res
= 0;
867 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
870 /* Assume ELF header is at the beginning of the page where program headers
871 are located. If it doesn't look like one, bail. */
873 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
874 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
877 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
882 /* Generate a ds-form instruction in BUF and return the number of bytes written
885 | OPCD | RST | RA | DS |XO| */
887 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
889 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
893 gdb_assert ((opcd
& ~0x3f) == 0);
894 gdb_assert ((rst
& ~0x1f) == 0);
895 gdb_assert ((ra
& ~0x1f) == 0);
896 gdb_assert ((xo
& ~0x3) == 0);
898 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
899 *buf
= (opcd
<< 26) | insn
;
903 /* Followings are frequently used ds-form instructions. */
905 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
906 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
907 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
908 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
910 /* Generate a d-form instruction in BUF.
913 | OPCD | RST | RA | D | */
916 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
920 gdb_assert ((opcd
& ~0x3f) == 0);
921 gdb_assert ((rst
& ~0x1f) == 0);
922 gdb_assert ((ra
& ~0x1f) == 0);
924 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
925 *buf
= (opcd
<< 26) | insn
;
929 /* Followings are frequently used d-form instructions. */
931 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
932 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
933 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
934 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
935 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
936 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
937 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
938 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
939 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
941 /* Generate a xfx-form instruction in BUF and return the number of bytes
945 | OPCD | RST | RI | XO |/| */
948 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
951 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
953 gdb_assert ((opcd
& ~0x3f) == 0);
954 gdb_assert ((rst
& ~0x1f) == 0);
955 gdb_assert ((xo
& ~0x3ff) == 0);
957 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
958 *buf
= (opcd
<< 26) | insn
;
962 /* Followings are frequently used xfx-form instructions. */
964 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
965 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
966 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
967 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
968 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
970 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
973 /* Generate a x-form instruction in BUF and return the number of bytes written.
976 | OPCD | RST | RA | RB | XO |RC| */
979 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
983 gdb_assert ((opcd
& ~0x3f) == 0);
984 gdb_assert ((rst
& ~0x1f) == 0);
985 gdb_assert ((ra
& ~0x1f) == 0);
986 gdb_assert ((rb
& ~0x1f) == 0);
987 gdb_assert ((xo
& ~0x3ff) == 0);
988 gdb_assert ((rc
& ~1) == 0);
990 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
991 *buf
= (opcd
<< 26) | insn
;
995 /* Followings are frequently used x-form instructions. */
997 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
998 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
999 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1000 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1001 /* Assume bf = cr7. */
1002 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1005 /* Generate a md-form instruction in BUF and return the number of bytes written.
1007 0 6 11 16 21 27 30 31 32
1008 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1011 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1015 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1016 unsigned int sh0_4
= sh
& 0x1f;
1017 unsigned int sh5
= (sh
>> 5) & 1;
1019 gdb_assert ((opcd
& ~0x3f) == 0);
1020 gdb_assert ((rs
& ~0x1f) == 0);
1021 gdb_assert ((ra
& ~0x1f) == 0);
1022 gdb_assert ((sh
& ~0x3f) == 0);
1023 gdb_assert ((mb
& ~0x3f) == 0);
1024 gdb_assert ((xo
& ~0x7) == 0);
1025 gdb_assert ((rc
& ~0x1) == 0);
1027 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1028 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1029 *buf
= (opcd
<< 26) | insn
;
1033 /* The following are frequently used md-form instructions. */
1035 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1036 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1037 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1038 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1040 /* Generate a i-form instruction in BUF and return the number of bytes written.
1043 | OPCD | LI |AA|LK| */
1046 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1050 gdb_assert ((opcd
& ~0x3f) == 0);
1052 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1053 *buf
= (opcd
<< 26) | insn
;
1057 /* The following are frequently used i-form instructions. */
1059 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1060 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1062 /* Generate a b-form instruction in BUF and return the number of bytes written.
1065 | OPCD | BO | BI | BD |AA|LK| */
1068 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1073 gdb_assert ((opcd
& ~0x3f) == 0);
1074 gdb_assert ((bo
& ~0x1f) == 0);
1075 gdb_assert ((bi
& ~0x1f) == 0);
1077 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1078 *buf
= (opcd
<< 26) | insn
;
1082 /* The following are frequently used b-form instructions. */
1083 /* Assume bi = cr7. */
1084 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1086 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1087 respectively. They are primary used for save/restore GPRs in jump-pad,
1088 not used for bytecode compiling. */
1090 #ifdef __powerpc64__
1091 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1092 GEN_LD (buf, rt, ra, si) : \
1093 GEN_LWZ (buf, rt, ra, si))
1094 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1095 GEN_STD (buf, rt, ra, si) : \
1096 GEN_STW (buf, rt, ra, si))
1098 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1099 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1102 /* Generate a sequence of instructions to load IMM in the register REG.
1103 Write the instructions in BUF and return the number of bytes written. */
1106 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1110 if ((imm
+ 32768) < 65536)
1112 /* li reg, imm[15:0] */
1113 p
+= GEN_LI (p
, reg
, imm
);
1115 else if ((imm
>> 32) == 0)
1117 /* lis reg, imm[31:16]
1118 ori reg, reg, imm[15:0]
1119 rldicl reg, reg, 0, 32 */
1120 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1121 if ((imm
& 0xffff) != 0)
1122 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1123 /* Clear upper 32-bit if sign-bit is set. */
1124 if (imm
& (1u << 31) && is_64
)
1125 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1130 /* lis reg, <imm[63:48]>
1131 ori reg, reg, <imm[48:32]>
1132 rldicr reg, reg, 32, 31
1133 oris reg, reg, <imm[31:16]>
1134 ori reg, reg, <imm[15:0]> */
1135 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1136 if (((imm
>> 32) & 0xffff) != 0)
1137 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1138 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1139 if (((imm
>> 16) & 0xffff) != 0)
1140 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1141 if ((imm
& 0xffff) != 0)
1142 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1148 /* Generate a sequence for atomically exchange at location LOCK.
1149 This code sequence clobbers r6, r7, r8. LOCK is the location for
1150 the atomic-xchg, OLD_VALUE is expected old value stored in the
1151 location, and R_NEW is a register for the new value. */
1154 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1157 const int r_lock
= 6;
1158 const int r_old
= 7;
1159 const int r_tmp
= 8;
1163 1: lwarx TMP, 0, LOCK
1169 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1170 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1172 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1173 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1174 p
+= GEN_BNE (p
, -8);
1175 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1176 p
+= GEN_BNE (p
, -16);
1181 /* Generate a sequence of instructions for calling a function
1182 at address of FN. Return the number of bytes are written in BUF. */
1185 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1189 /* Must be called by r12 for caller to calculate TOC address. */
1190 p
+= gen_limm (p
, 12, fn
, is_64
);
1193 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1194 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1195 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1197 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1198 *p
++ = 0x4e800421; /* bctrl */
1203 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1204 of instruction. This function is used to adjust pc-relative instructions
1208 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1213 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1214 op6
= PPC_OP6 (insn
);
1216 if (op6
== 18 && (insn
& 2) == 0)
1218 /* branch && AA = 0 */
1219 rel
= PPC_LI (insn
);
1220 newrel
= (oldloc
- *to
) + rel
;
1222 /* Out of range. Cannot relocate instruction. */
1223 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1226 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1228 else if (op6
== 16 && (insn
& 2) == 0)
1230 /* conditional branch && AA = 0 */
1232 /* If the new relocation is too big for even a 26-bit unconditional
1233 branch, there is nothing we can do. Just abort.
1235 Otherwise, if it can be fit in 16-bit conditional branch, just
1236 copy the instruction and relocate the address.
1238 If the it's big for conditional-branch (16-bit), try to invert the
1239 condition and jump with 26-bit branch. For example,
1250 After this transform, we are actually jump from *TO+4 instead of *TO,
1251 so check the relocation again because it will be 1-insn farther then
1252 before if *TO is after OLDLOC.
1255 For BDNZT (or so) is transformed from
1267 See also "BO field encodings". */
1269 rel
= PPC_BD (insn
);
1270 newrel
= (oldloc
- *to
) + rel
;
1272 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1273 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1274 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1278 /* Out of range. Cannot relocate instruction. */
1279 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1282 if ((PPC_BO (insn
) & 0x14) == 0x4)
1284 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1287 /* Jump over the unconditional branch. */
1288 insn
= (insn
& ~0xfffc) | 0x8;
1289 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1292 /* Build a unconditional branch and copy LK bit. */
1293 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1294 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1299 else if ((PPC_BO (insn
) & 0x14) == 0)
1301 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1302 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1306 /* Out of range. Cannot relocate instruction. */
1307 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1310 /* Copy BI field. */
1311 bf_insn
|= (insn
& 0x1f0000);
1313 /* Invert condition. */
1314 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1315 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1317 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1319 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1322 /* Build a unconditional branch and copy LK bit. */
1323 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1324 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1329 else /* (BO & 0x14) == 0x14, branch always. */
1331 /* Out of range. Cannot relocate instruction. */
1332 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1335 /* Build a unconditional branch and copy LK bit. */
1336 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1337 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1344 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1348 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1349 See target.h for details. */
1352 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1353 CORE_ADDR collector
,
1356 CORE_ADDR
*jump_entry
,
1357 CORE_ADDR
*trampoline
,
1358 ULONGEST
*trampoline_size
,
1359 unsigned char *jjump_pad_insn
,
1360 ULONGEST
*jjump_pad_insn_size
,
1361 CORE_ADDR
*adjusted_insn_addr
,
1362 CORE_ADDR
*adjusted_insn_addr_end
,
1368 CORE_ADDR buildaddr
= *jump_entry
;
1369 const CORE_ADDR entryaddr
= *jump_entry
;
1370 int rsz
, min_frame
, frame_size
, tp_reg
;
1371 #ifdef __powerpc64__
1372 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1373 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1374 int is_opd
= is_64
&& !is_elfv2_inferior ();
1376 int is_64
= 0, is_opd
= 0;
1379 #ifdef __powerpc64__
1382 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1385 frame_size
= (40 * rsz
) + min_frame
;
1393 frame_size
= (40 * rsz
) + min_frame
;
1395 #ifdef __powerpc64__
1399 /* Stack frame layout for this jump pad,
1401 High thread_area (r13/r2) |
1402 tpoint - collecting_t obj
1412 R0 - collected registers
1418 The code flow of this jump pad,
1423 4. Call gdb_collector
1424 5. Restore GPR and SPR
1426 7. Build a jump for back to the program
1427 8. Copy/relocate original instruction
1428 9. Build a jump for replacing orignal instruction. */
1430 /* Adjust stack pointer. */
1432 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1434 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1436 /* Store GPRs. Save R1 later, because it had just been modified, but
1437 we want the original value. */
1438 for (j
= 2; j
< 32; j
++)
1439 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1440 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1441 /* Set r0 to the original value of r1 before adjusting stack frame,
1442 and then save it. */
1443 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1444 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1446 /* Save CR, XER, LR, and CTR. */
1447 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1448 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1449 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1450 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1451 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1452 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1453 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1454 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1456 /* Save PC<tpaddr> */
1457 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1458 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1461 /* Setup arguments to collector. */
1462 /* Set r4 to collected registers. */
1463 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1464 /* Set r3 to TPOINT. */
1465 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1467 /* Prepare collecting_t object for lock. */
1468 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1469 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1470 /* Set R5 to collecting object. */
1471 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1473 p
+= GEN_LWSYNC (p
);
1474 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1475 p
+= GEN_LWSYNC (p
);
1477 /* Call to collector. */
1478 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1480 /* Simply write 0 to release the lock. */
1481 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1482 p
+= gen_limm (p
, 4, 0, is_64
);
1483 p
+= GEN_LWSYNC (p
);
1484 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1486 /* Restore stack and registers. */
1487 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1488 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1489 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1490 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1491 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1492 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1493 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1494 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1497 for (j
= 2; j
< 32; j
++)
1498 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1499 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1501 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1503 /* Flush instructions to inferior memory. */
1504 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1506 /* Now, insert the original instruction to execute in the jump pad. */
1507 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1508 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1509 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1511 /* Verify the relocation size. If should be 4 for normal copy,
1512 8 or 12 for some conditional branch. */
1513 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1514 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1516 sprintf (err
, "E.Unexpected instruction length = %d"
1517 "when relocate instruction.",
1518 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1522 buildaddr
= *adjusted_insn_addr_end
;
1524 /* Finally, write a jump back to the program. */
1525 offset
= (tpaddr
+ 4) - buildaddr
;
1526 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1528 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1529 "(offset 0x%x > 26-bit).", offset
);
1533 p
+= GEN_B (p
, offset
);
1534 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1535 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1537 /* The jump pad is now built. Wire in a jump to our jump pad. This
1538 is always done last (by our caller actually), so that we can
1539 install fast tracepoints with threads running. This relies on
1540 the agent's atomic write support. */
1541 offset
= entryaddr
- tpaddr
;
1542 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1544 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1545 "(offset 0x%x > 26-bit).", offset
);
1549 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1550 *jjump_pad_insn_size
= 4;
1555 /* Returns the minimum instruction length for installing a tracepoint. */
1558 ppc_get_min_fast_tracepoint_insn_len (void)
1563 /* Emits a given buffer into the target at current_insn_ptr. Length
1564 is in units of 32-bit words. */
1567 emit_insns (uint32_t *buf
, int n
)
1569 n
= n
* sizeof (uint32_t);
1570 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1571 current_insn_ptr
+= n
;
1574 #define __EMIT_ASM(NAME, INSNS) \
1577 extern uint32_t start_bcax_ ## NAME []; \
1578 extern uint32_t end_bcax_ ## NAME []; \
1579 emit_insns (start_bcax_ ## NAME, \
1580 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1581 __asm__ (".section .text.__ppcbcax\n\t" \
1582 "start_bcax_" #NAME ":\n\t" \
1584 "end_bcax_" #NAME ":\n\t" \
1588 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1589 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1593 Bytecode execution stack frame - 32-bit
1595 | LR save area (SP + 4)
1596 SP' -> +- Back chain (SP + 0)
1597 | Save r31 for access saved arguments
1598 | Save r30 for bytecode stack pointer
1599 | Save r4 for incoming argument *value
1600 | Save r3 for incoming argument regs
1601 r30 -> +- Bytecode execution stack
1603 | 64-byte (8 doublewords) at initial.
1604 | Expand stack as needed.
1607 | Some padding for minimum stack frame and 16-byte alignment.
1609 SP +- Back-chain (SP')
1615 r30 is the stack-pointer for bytecode machine.
1616 It should point to next-empty, so we can use LDU for pop.
1617 r3 is used for cache of the high part of TOP value.
1618 It was the first argument, pointer to regs.
1619 r4 is used for cache of the low part of TOP value.
1620 It was the second argument, pointer to the result.
1621 We should set *result = TOP after leaving this function.
1624 * To restore stack at epilogue
1626 * To check stack is big enough for bytecode execution.
1628 * To return execution result.
1633 /* Regardless of endian, register 3 is always high part, 4 is low part.
1634 These defines are used when the register pair is stored/loaded.
1635 Likewise, to simplify code, have a similiar define for 5:6. */
1637 #if __BYTE_ORDER == __LITTLE_ENDIAN
1638 #define TOP_FIRST "4"
1639 #define TOP_SECOND "3"
1640 #define TMP_FIRST "6"
1641 #define TMP_SECOND "5"
1643 #define TOP_FIRST "3"
1644 #define TOP_SECOND "4"
1645 #define TMP_FIRST "5"
1646 #define TMP_SECOND "6"
1649 /* Emit prologue in inferior memory. See above comments. */
1652 ppc_emit_prologue (void)
1654 EMIT_ASM (/* Save return address. */
1657 /* Adjust SP. 96 is the initial frame size. */
1659 /* Save r30 and incoming arguments. */
1660 "stw 31, 96-4(1) \n"
1661 "stw 30, 96-8(1) \n"
1662 "stw 4, 96-12(1) \n"
1663 "stw 3, 96-16(1) \n"
1664 /* Point r31 to original r1 for access arguments. */
1666 /* Set r30 to pointing stack-top. */
1668 /* Initial r3/TOP to 0. */
1673 /* Emit epilogue in inferior memory. See above comments. */
1676 ppc_emit_epilogue (void)
1678 EMIT_ASM (/* *result = TOP */
1680 "stw " TOP_FIRST
", 0(5) \n"
1681 "stw " TOP_SECOND
", 4(5) \n"
1682 /* Restore registers. */
1689 /* Return 0 for no-error. */
1695 /* TOP = stack[--sp] + TOP */
1700 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1701 "lwz " TMP_SECOND
", 4(30)\n"
1706 /* TOP = stack[--sp] - TOP */
1711 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1712 "lwz " TMP_SECOND
", 4(30) \n"
1714 "subfe 3, 3, 5 \n");
1717 /* TOP = stack[--sp] * TOP */
1722 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1723 "lwz " TMP_SECOND
", 4(30) \n"
1732 /* TOP = stack[--sp] << TOP */
1737 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1738 "lwz " TMP_SECOND
", 4(30) \n"
1739 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1740 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1741 "slw 5, 5, 4\n" /* Shift high part left */
1742 "slw 4, 6, 4\n" /* Shift low part left */
1743 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1744 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1746 "or 3, 7, 3\n"); /* Assemble high part */
1749 /* Top = stack[--sp] >> TOP
1750 (Arithmetic shift right) */
1753 ppc_emit_rsh_signed (void)
1755 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1756 "lwz " TMP_SECOND
", 4(30) \n"
1757 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1758 "sraw 3, 5, 4\n" /* Shift high part right */
1760 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1761 "sraw 4, 5, 7\n" /* Shift high to low */
1764 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1765 "srw 4, 6, 4\n" /* Shift low part right */
1766 "slw 5, 5, 7\n" /* Shift high to low */
1767 "or 4, 4, 5\n" /* Assemble low part */
1771 /* Top = stack[--sp] >> TOP
1772 (Logical shift right) */
1775 ppc_emit_rsh_unsigned (void)
1777 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1778 "lwz " TMP_SECOND
", 4(30) \n"
1779 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1780 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1781 "srw 6, 6, 4\n" /* Shift low part right */
1782 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1783 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1785 "srw 3, 5, 4\n" /* Shift high part right */
1786 "or 4, 6, 7\n"); /* Assemble low part */
1789 /* Emit code for signed-extension specified by ARG. */
1792 ppc_emit_ext (int arg
)
1797 EMIT_ASM ("extsb 4, 4\n"
1801 EMIT_ASM ("extsh 4, 4\n"
1805 EMIT_ASM ("srawi 3, 4, 31");
1812 /* Emit code for zero-extension specified by ARG. */
1815 ppc_emit_zero_ext (int arg
)
1820 EMIT_ASM ("clrlwi 4,4,24\n"
1824 EMIT_ASM ("clrlwi 4,4,16\n"
1828 EMIT_ASM ("li 3, 0");
1836 i.e., TOP = (TOP == 0) ? 1 : 0; */
1839 ppc_emit_log_not (void)
1841 EMIT_ASM ("or 4, 3, 4 \n"
1847 /* TOP = stack[--sp] & TOP */
1850 ppc_emit_bit_and (void)
1852 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1853 "lwz " TMP_SECOND
", 4(30) \n"
1858 /* TOP = stack[--sp] | TOP */
1861 ppc_emit_bit_or (void)
1863 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1864 "lwz " TMP_SECOND
", 4(30) \n"
1869 /* TOP = stack[--sp] ^ TOP */
1872 ppc_emit_bit_xor (void)
1874 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1875 "lwz " TMP_SECOND
", 4(30) \n"
1881 i.e., TOP = ~(TOP | TOP) */
1884 ppc_emit_bit_not (void)
1886 EMIT_ASM ("nor 3, 3, 3 \n"
1890 /* TOP = stack[--sp] == TOP */
1893 ppc_emit_equal (void)
1895 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1896 "lwz " TMP_SECOND
", 4(30) \n"
1905 /* TOP = stack[--sp] < TOP
1906 (Signed comparison) */
1909 ppc_emit_less_signed (void)
1911 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1912 "lwz " TMP_SECOND
", 4(30) \n"
1915 /* CR6 bit 0 = low less and high equal */
1916 "crand 6*4+0, 6*4+0, 7*4+2\n"
1917 /* CR7 bit 0 = (low less and high equal) or high less */
1918 "cror 7*4+0, 7*4+0, 6*4+0\n"
1920 "rlwinm 4, 4, 29, 31, 31 \n"
1924 /* TOP = stack[--sp] < TOP
1925 (Unsigned comparison) */
1928 ppc_emit_less_unsigned (void)
1930 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1931 "lwz " TMP_SECOND
", 4(30) \n"
1934 /* CR6 bit 0 = low less and high equal */
1935 "crand 6*4+0, 6*4+0, 7*4+2\n"
1936 /* CR7 bit 0 = (low less and high equal) or high less */
1937 "cror 7*4+0, 7*4+0, 6*4+0\n"
1939 "rlwinm 4, 4, 29, 31, 31 \n"
1943 /* Access the memory address in TOP in size of SIZE.
1944 Zero-extend the read value. */
1947 ppc_emit_ref (int size
)
1952 EMIT_ASM ("lbz 4, 0(4)\n"
1956 EMIT_ASM ("lhz 4, 0(4)\n"
1960 EMIT_ASM ("lwz 4, 0(4)\n"
1964 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1965 EMIT_ASM ("lwz 3, 4(4)\n"
1968 EMIT_ASM ("lwz 3, 0(4)\n"
1977 ppc_emit_const (LONGEST num
)
1982 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
1983 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
1985 emit_insns (buf
, p
- buf
);
1986 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1989 /* Set TOP to the value of register REG by calling get_raw_reg function
1990 with two argument, collected buffer and register number. */
1993 ppc_emit_reg (int reg
)
1998 /* fctx->regs is passed in r3 and then saved in -16(31). */
1999 p
+= GEN_LWZ (p
, 3, 31, -16);
2000 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2001 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2003 emit_insns (buf
, p
- buf
);
2004 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2006 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2008 EMIT_ASM ("mr 5, 4\n"
2014 /* TOP = stack[--sp] */
2019 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2020 "lwz " TOP_SECOND
", 4(30) \n");
2023 /* stack[sp++] = TOP
2025 Because we may use up bytecode stack, expand 8 doublewords more
2029 ppc_emit_stack_flush (void)
2031 /* Make sure bytecode stack is big enough before push.
2032 Otherwise, expand 64-byte more. */
2034 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2035 " stw " TOP_SECOND
", 4(30)\n"
2036 " addi 5, 30, -(8 + 8) \n"
2039 " stwu 31, -64(1) \n"
2040 "1:addi 30, 30, -8 \n");
2043 /* Swap TOP and stack[sp-1] */
2046 ppc_emit_swap (void)
2048 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2049 "lwz " TMP_SECOND
", 12(30) \n"
2050 "stw " TOP_FIRST
", 8(30) \n"
2051 "stw " TOP_SECOND
", 12(30) \n"
2056 /* Discard N elements in the stack. Also used for ppc64. */
2059 ppc_emit_stack_adjust (int n
)
2071 p
+= GEN_ADDI (p
, 30, 30, n
);
2073 emit_insns (buf
, p
- buf
);
2074 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2077 /* Call function FN. */
2080 ppc_emit_call (CORE_ADDR fn
)
2085 p
+= gen_call (p
, fn
, 0, 0);
2087 emit_insns (buf
, p
- buf
);
2088 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2091 /* FN's prototype is `LONGEST(*fn)(int)'.
2096 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2101 /* Setup argument. arg1 is a 16-bit value. */
2102 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2103 p
+= gen_call (p
, fn
, 0, 0);
2105 emit_insns (buf
, p
- buf
);
2106 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2108 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2110 EMIT_ASM ("mr 5, 4\n"
2116 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2119 TOP should be preserved/restored before/after the call. */
2122 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2127 /* Save TOP. 0(30) is next-empty. */
2128 p
+= GEN_STW (p
, 3, 30, 0);
2129 p
+= GEN_STW (p
, 4, 30, 4);
2131 /* Setup argument. arg1 is a 16-bit value. */
2132 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2134 p
+= GEN_MR (p
, 5, 4);
2135 p
+= GEN_MR (p
, 6, 3);
2139 p
+= GEN_MR (p
, 5, 3);
2140 p
+= GEN_MR (p
, 6, 4);
2142 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2143 p
+= gen_call (p
, fn
, 0, 0);
2146 p
+= GEN_LWZ (p
, 3, 30, 0);
2147 p
+= GEN_LWZ (p
, 4, 30, 4);
2149 emit_insns (buf
, p
- buf
);
2150 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2153 /* Note in the following goto ops:
2155 When emitting goto, the target address is later relocated by
2156 write_goto_address. OFFSET_P is the offset of the branch instruction
2157 in the code sequence, and SIZE_P is how to relocate the instruction,
2158 recognized by ppc_write_goto_address. In current implementation,
2159 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2162 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2165 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2167 EMIT_ASM ("or. 3, 3, 4 \n"
2168 "lwzu " TOP_FIRST
", 8(30) \n"
2169 "lwz " TOP_SECOND
", 4(30) \n"
2178 /* Unconditional goto. Also used for ppc64. */
2181 ppc_emit_goto (int *offset_p
, int *size_p
)
2183 EMIT_ASM ("1:b 1b");
2191 /* Goto if stack[--sp] == TOP */
2194 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2196 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2197 "lwz " TMP_SECOND
", 4(30) \n"
2201 "lwzu " TOP_FIRST
", 8(30) \n"
2202 "lwz " TOP_SECOND
", 4(30) \n"
2211 /* Goto if stack[--sp] != TOP */
2214 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2216 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2217 "lwz " TMP_SECOND
", 4(30) \n"
2221 "lwzu " TOP_FIRST
", 8(30) \n"
2222 "lwz " TOP_SECOND
", 4(30) \n"
2231 /* Goto if stack[--sp] < TOP */
2234 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2236 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2237 "lwz " TMP_SECOND
", 4(30) \n"
2240 /* CR6 bit 0 = low less and high equal */
2241 "crand 6*4+0, 6*4+0, 7*4+2\n"
2242 /* CR7 bit 0 = (low less and high equal) or high less */
2243 "cror 7*4+0, 7*4+0, 6*4+0\n"
2244 "lwzu " TOP_FIRST
", 8(30) \n"
2245 "lwz " TOP_SECOND
", 4(30)\n"
2254 /* Goto if stack[--sp] <= TOP */
2257 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2259 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2260 "lwz " TMP_SECOND
", 4(30) \n"
2263 /* CR6 bit 0 = low less/equal and high equal */
2264 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2265 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2266 "cror 7*4+0, 7*4+0, 6*4+0\n"
2267 "lwzu " TOP_FIRST
", 8(30) \n"
2268 "lwz " TOP_SECOND
", 4(30)\n"
2277 /* Goto if stack[--sp] > TOP */
2280 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2282 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2283 "lwz " TMP_SECOND
", 4(30) \n"
2286 /* CR6 bit 0 = low greater and high equal */
2287 "crand 6*4+0, 6*4+1, 7*4+2\n"
2288 /* CR7 bit 0 = (low greater and high equal) or high greater */
2289 "cror 7*4+0, 7*4+1, 6*4+0\n"
2290 "lwzu " TOP_FIRST
", 8(30) \n"
2291 "lwz " TOP_SECOND
", 4(30)\n"
2300 /* Goto if stack[--sp] >= TOP */
2303 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2305 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2306 "lwz " TMP_SECOND
", 4(30) \n"
2309 /* CR6 bit 0 = low ge and high equal */
2310 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2311 /* CR7 bit 0 = (low ge and high equal) or high greater */
2312 "cror 7*4+0, 7*4+1, 6*4+0\n"
2313 "lwzu " TOP_FIRST
", 8(30)\n"
2314 "lwz " TOP_SECOND
", 4(30)\n"
2323 /* Relocate previous emitted branch instruction. FROM is the address
2324 of the branch instruction, TO is the goto target address, and SIZE
2325 if the value we set by *SIZE_P before. Currently, it is either
2326 24 or 14 of branch and conditional-branch instruction.
2327 Also used for ppc64. */
2330 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2332 long rel
= to
- from
;
2336 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2337 opcd
= (insn
>> 26) & 0x3f;
2343 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2345 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2349 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2351 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2358 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2361 /* Table of emit ops for 32-bit. */
2363 static struct emit_ops ppc_emit_ops_impl
=
2371 ppc_emit_rsh_signed
,
2372 ppc_emit_rsh_unsigned
,
2380 ppc_emit_less_signed
,
2381 ppc_emit_less_unsigned
,
2385 ppc_write_goto_address
,
2390 ppc_emit_stack_flush
,
2393 ppc_emit_stack_adjust
,
2394 ppc_emit_int_call_1
,
2395 ppc_emit_void_call_2
,
2404 #ifdef __powerpc64__
2408 Bytecode execution stack frame - 64-bit
2410 | LR save area (SP + 16)
2411 | CR save area (SP + 8)
2412 SP' -> +- Back chain (SP + 0)
2413 | Save r31 for access saved arguments
2414 | Save r30 for bytecode stack pointer
2415 | Save r4 for incoming argument *value
2416 | Save r3 for incoming argument regs
2417 r30 -> +- Bytecode execution stack
2419 | 64-byte (8 doublewords) at initial.
2420 | Expand stack as needed.
2423 | Some padding for minimum stack frame.
2425 SP +- Back-chain (SP')
2428 = 112 + (4 * 8) + 64
2431 r30 is the stack-pointer for bytecode machine.
2432 It should point to next-empty, so we can use LDU for pop.
2433 r3 is used for cache of TOP value.
2434 It was the first argument, pointer to regs.
2435 r4 is the second argument, pointer to the result.
2436 We should set *result = TOP after leaving this function.
2439 * To restore stack at epilogue
2441 * To check stack is big enough for bytecode execution.
2442 => r30 - 8 > SP + 112
2443 * To return execution result.
2448 /* Emit prologue in inferior memory. See above comments. */
2451 ppc64v1_emit_prologue (void)
2453 /* On ELFv1, function pointers really point to function descriptor,
2454 so emit one here. We don't care about contents of words 1 and 2,
2455 so let them just overlap out code. */
2456 uint64_t opd
= current_insn_ptr
+ 8;
2459 /* Mind the strict aliasing rules. */
2460 memcpy (buf
, &opd
, sizeof buf
);
2462 EMIT_ASM (/* Save return address. */
2465 /* Save r30 and incoming arguments. */
2470 /* Point r31 to current r1 for access arguments. */
2472 /* Adjust SP. 208 is the initial frame size. */
2473 "stdu 1, -208(1) \n"
2474 /* Set r30 to pointing stack-top. */
2475 "addi 30, 1, 168 \n"
2476 /* Initial r3/TOP to 0. */
2480 /* Emit prologue in inferior memory. See above comments. */
2483 ppc64v2_emit_prologue (void)
2485 EMIT_ASM (/* Save return address. */
2488 /* Save r30 and incoming arguments. */
2493 /* Point r31 to current r1 for access arguments. */
2495 /* Adjust SP. 208 is the initial frame size. */
2496 "stdu 1, -208(1) \n"
2497 /* Set r30 to pointing stack-top. */
2498 "addi 30, 1, 168 \n"
2499 /* Initial r3/TOP to 0. */
2503 /* Emit epilogue in inferior memory. See above comments. */
2506 ppc64_emit_epilogue (void)
2508 EMIT_ASM (/* Restore SP. */
2513 /* Restore registers. */
2518 /* Return 0 for no-error. */
2524 /* TOP = stack[--sp] + TOP */
2527 ppc64_emit_add (void)
2529 EMIT_ASM ("ldu 4, 8(30) \n"
2533 /* TOP = stack[--sp] - TOP */
2536 ppc64_emit_sub (void)
2538 EMIT_ASM ("ldu 4, 8(30) \n"
2542 /* TOP = stack[--sp] * TOP */
2545 ppc64_emit_mul (void)
2547 EMIT_ASM ("ldu 4, 8(30) \n"
2548 "mulld 3, 4, 3 \n");
2551 /* TOP = stack[--sp] << TOP */
2554 ppc64_emit_lsh (void)
2556 EMIT_ASM ("ldu 4, 8(30) \n"
2560 /* Top = stack[--sp] >> TOP
2561 (Arithmetic shift right) */
2564 ppc64_emit_rsh_signed (void)
2566 EMIT_ASM ("ldu 4, 8(30) \n"
2570 /* Top = stack[--sp] >> TOP
2571 (Logical shift right) */
2574 ppc64_emit_rsh_unsigned (void)
2576 EMIT_ASM ("ldu 4, 8(30) \n"
2580 /* Emit code for signed-extension specified by ARG. */
2583 ppc64_emit_ext (int arg
)
2588 EMIT_ASM ("extsb 3, 3");
2591 EMIT_ASM ("extsh 3, 3");
2594 EMIT_ASM ("extsw 3, 3");
2601 /* Emit code for zero-extension specified by ARG. */
2604 ppc64_emit_zero_ext (int arg
)
2609 EMIT_ASM ("rldicl 3,3,0,56");
2612 EMIT_ASM ("rldicl 3,3,0,48");
2615 EMIT_ASM ("rldicl 3,3,0,32");
2623 i.e., TOP = (TOP == 0) ? 1 : 0; */
2626 ppc64_emit_log_not (void)
2628 EMIT_ASM ("cntlzd 3, 3 \n"
2632 /* TOP = stack[--sp] & TOP */
2635 ppc64_emit_bit_and (void)
2637 EMIT_ASM ("ldu 4, 8(30) \n"
2641 /* TOP = stack[--sp] | TOP */
2644 ppc64_emit_bit_or (void)
2646 EMIT_ASM ("ldu 4, 8(30) \n"
2650 /* TOP = stack[--sp] ^ TOP */
2653 ppc64_emit_bit_xor (void)
2655 EMIT_ASM ("ldu 4, 8(30) \n"
2660 i.e., TOP = ~(TOP | TOP) */
2663 ppc64_emit_bit_not (void)
2665 EMIT_ASM ("nor 3, 3, 3 \n");
2668 /* TOP = stack[--sp] == TOP */
2671 ppc64_emit_equal (void)
2673 EMIT_ASM ("ldu 4, 8(30) \n"
2679 /* TOP = stack[--sp] < TOP
2680 (Signed comparison) */
2683 ppc64_emit_less_signed (void)
2685 EMIT_ASM ("ldu 4, 8(30) \n"
2688 "rlwinm 3, 3, 29, 31, 31 \n");
2691 /* TOP = stack[--sp] < TOP
2692 (Unsigned comparison) */
2695 ppc64_emit_less_unsigned (void)
2697 EMIT_ASM ("ldu 4, 8(30) \n"
2700 "rlwinm 3, 3, 29, 31, 31 \n");
2703 /* Access the memory address in TOP in size of SIZE.
2704 Zero-extend the read value. */
2707 ppc64_emit_ref (int size
)
2712 EMIT_ASM ("lbz 3, 0(3)");
2715 EMIT_ASM ("lhz 3, 0(3)");
2718 EMIT_ASM ("lwz 3, 0(3)");
2721 EMIT_ASM ("ld 3, 0(3)");
2729 ppc64_emit_const (LONGEST num
)
2734 p
+= gen_limm (p
, 3, num
, 1);
2736 emit_insns (buf
, p
- buf
);
2737 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2740 /* Set TOP to the value of register REG by calling get_raw_reg function
2741 with two argument, collected buffer and register number. */
2744 ppc64v1_emit_reg (int reg
)
2749 /* fctx->regs is passed in r3 and then saved in 176(1). */
2750 p
+= GEN_LD (p
, 3, 31, -32);
2751 p
+= GEN_LI (p
, 4, reg
);
2752 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2753 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2754 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2756 emit_insns (buf
, p
- buf
);
2757 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2760 /* Likewise, for ELFv2. */
2763 ppc64v2_emit_reg (int reg
)
2768 /* fctx->regs is passed in r3 and then saved in 176(1). */
2769 p
+= GEN_LD (p
, 3, 31, -32);
2770 p
+= GEN_LI (p
, 4, reg
);
2771 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2772 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2773 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2775 emit_insns (buf
, p
- buf
);
2776 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2779 /* TOP = stack[--sp] */
2782 ppc64_emit_pop (void)
2784 EMIT_ASM ("ldu 3, 8(30)");
2787 /* stack[sp++] = TOP
2789 Because we may use up bytecode stack, expand 8 doublewords more
2793 ppc64_emit_stack_flush (void)
2795 /* Make sure bytecode stack is big enough before push.
2796 Otherwise, expand 64-byte more. */
2798 EMIT_ASM (" std 3, 0(30) \n"
2799 " addi 4, 30, -(112 + 8) \n"
2802 " stdu 31, -64(1) \n"
2803 "1:addi 30, 30, -8 \n");
2806 /* Swap TOP and stack[sp-1] */
2809 ppc64_emit_swap (void)
2811 EMIT_ASM ("ld 4, 8(30) \n"
2816 /* Call function FN - ELFv1. */
2819 ppc64v1_emit_call (CORE_ADDR fn
)
2824 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2825 p
+= gen_call (p
, fn
, 1, 1);
2826 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2828 emit_insns (buf
, p
- buf
);
2829 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2832 /* Call function FN - ELFv2. */
2835 ppc64v2_emit_call (CORE_ADDR fn
)
2840 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2841 p
+= gen_call (p
, fn
, 1, 0);
2842 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2844 emit_insns (buf
, p
- buf
);
2845 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2848 /* FN's prototype is `LONGEST(*fn)(int)'.
2853 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2858 /* Setup argument. arg1 is a 16-bit value. */
2859 p
+= gen_limm (p
, 3, arg1
, 1);
2860 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2861 p
+= gen_call (p
, fn
, 1, 1);
2862 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2864 emit_insns (buf
, p
- buf
);
2865 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2868 /* Likewise for ELFv2. */
2871 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2876 /* Setup argument. arg1 is a 16-bit value. */
2877 p
+= gen_limm (p
, 3, arg1
, 1);
2878 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2879 p
+= gen_call (p
, fn
, 1, 0);
2880 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2882 emit_insns (buf
, p
- buf
);
2883 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2886 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2889 TOP should be preserved/restored before/after the call. */
2892 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2897 /* Save TOP. 0(30) is next-empty. */
2898 p
+= GEN_STD (p
, 3, 30, 0);
2900 /* Setup argument. arg1 is a 16-bit value. */
2901 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2902 p
+= gen_limm (p
, 3, arg1
, 1);
2903 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2904 p
+= gen_call (p
, fn
, 1, 1);
2905 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2908 p
+= GEN_LD (p
, 3, 30, 0);
2910 emit_insns (buf
, p
- buf
);
2911 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2914 /* Likewise for ELFv2. */
2917 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2922 /* Save TOP. 0(30) is next-empty. */
2923 p
+= GEN_STD (p
, 3, 30, 0);
2925 /* Setup argument. arg1 is a 16-bit value. */
2926 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2927 p
+= gen_limm (p
, 3, arg1
, 1);
2928 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2929 p
+= gen_call (p
, fn
, 1, 0);
2930 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2933 p
+= GEN_LD (p
, 3, 30, 0);
2935 emit_insns (buf
, p
- buf
);
2936 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2939 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2942 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
2944 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2954 /* Goto if stack[--sp] == TOP */
2957 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
2959 EMIT_ASM ("ldu 4, 8(30) \n"
2970 /* Goto if stack[--sp] != TOP */
2973 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
2975 EMIT_ASM ("ldu 4, 8(30) \n"
2986 /* Goto if stack[--sp] < TOP */
2989 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
2991 EMIT_ASM ("ldu 4, 8(30) \n"
3002 /* Goto if stack[--sp] <= TOP */
3005 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3007 EMIT_ASM ("ldu 4, 8(30) \n"
3018 /* Goto if stack[--sp] > TOP */
3021 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3023 EMIT_ASM ("ldu 4, 8(30) \n"
3034 /* Goto if stack[--sp] >= TOP */
3037 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3039 EMIT_ASM ("ldu 4, 8(30) \n"
3050 /* Table of emit ops for 64-bit ELFv1. */
3052 static struct emit_ops ppc64v1_emit_ops_impl
=
3054 ppc64v1_emit_prologue
,
3055 ppc64_emit_epilogue
,
3060 ppc64_emit_rsh_signed
,
3061 ppc64_emit_rsh_unsigned
,
3069 ppc64_emit_less_signed
,
3070 ppc64_emit_less_unsigned
,
3074 ppc_write_goto_address
,
3079 ppc64_emit_stack_flush
,
3080 ppc64_emit_zero_ext
,
3082 ppc_emit_stack_adjust
,
3083 ppc64v1_emit_int_call_1
,
3084 ppc64v1_emit_void_call_2
,
3093 /* Table of emit ops for 64-bit ELFv2. */
3095 static struct emit_ops ppc64v2_emit_ops_impl
=
3097 ppc64v2_emit_prologue
,
3098 ppc64_emit_epilogue
,
3103 ppc64_emit_rsh_signed
,
3104 ppc64_emit_rsh_unsigned
,
3112 ppc64_emit_less_signed
,
3113 ppc64_emit_less_unsigned
,
3117 ppc_write_goto_address
,
3122 ppc64_emit_stack_flush
,
3123 ppc64_emit_zero_ext
,
3125 ppc_emit_stack_adjust
,
3126 ppc64v2_emit_int_call_1
,
3127 ppc64v2_emit_void_call_2
,
3138 /* Implementation of linux_target_ops method "emit_ops". */
3140 static struct emit_ops
*
3143 #ifdef __powerpc64__
3144 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3146 if (register_size (regcache
->tdesc
, 0) == 8)
3148 if (is_elfv2_inferior ())
3149 return &ppc64v2_emit_ops_impl
;
3151 return &ppc64v1_emit_ops_impl
;
3154 return &ppc_emit_ops_impl
;
3157 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3160 ppc_get_ipa_tdesc_idx (void)
3162 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3163 const struct target_desc
*tdesc
= regcache
->tdesc
;
3165 #ifdef __powerpc64__
3166 if (tdesc
== tdesc_powerpc_64l
)
3167 return PPC_TDESC_BASE
;
3168 if (tdesc
== tdesc_powerpc_altivec64l
)
3169 return PPC_TDESC_ALTIVEC
;
3170 if (tdesc
== tdesc_powerpc_cell64l
)
3171 return PPC_TDESC_CELL
;
3172 if (tdesc
== tdesc_powerpc_vsx64l
)
3173 return PPC_TDESC_VSX
;
3174 if (tdesc
== tdesc_powerpc_isa205_64l
)
3175 return PPC_TDESC_ISA205
;
3176 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3177 return PPC_TDESC_ISA205_ALTIVEC
;
3178 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3179 return PPC_TDESC_ISA205_VSX
;
3180 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3181 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3182 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3183 return PPC_TDESC_ISA207_VSX
;
3186 if (tdesc
== tdesc_powerpc_32l
)
3187 return PPC_TDESC_BASE
;
3188 if (tdesc
== tdesc_powerpc_altivec32l
)
3189 return PPC_TDESC_ALTIVEC
;
3190 if (tdesc
== tdesc_powerpc_cell32l
)
3191 return PPC_TDESC_CELL
;
3192 if (tdesc
== tdesc_powerpc_vsx32l
)
3193 return PPC_TDESC_VSX
;
3194 if (tdesc
== tdesc_powerpc_isa205_32l
)
3195 return PPC_TDESC_ISA205
;
3196 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3197 return PPC_TDESC_ISA205_ALTIVEC
;
3198 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3199 return PPC_TDESC_ISA205_VSX
;
3200 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3201 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3202 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3203 return PPC_TDESC_ISA207_VSX
;
3204 if (tdesc
== tdesc_powerpc_e500l
)
3205 return PPC_TDESC_E500
;
3210 struct linux_target_ops the_low_target
= {
3213 ppc_cannot_fetch_register
,
3214 ppc_cannot_store_register
,
3215 NULL
, /* fetch_register */
3218 NULL
, /* breakpoint_kind_from_pc */
3219 ppc_sw_breakpoint_from_kind
,
3223 ppc_supports_z_point_type
,
3228 ppc_collect_ptrace_register
,
3229 ppc_supply_ptrace_register
,
3230 NULL
, /* siginfo_fixup */
3231 NULL
, /* new_process */
3232 NULL
, /* delete_process */
3233 NULL
, /* new_thread */
3234 NULL
, /* delete_thread */
3235 NULL
, /* new_fork */
3236 NULL
, /* prepare_to_resume */
3237 NULL
, /* process_qsupported */
3238 ppc_supports_tracepoints
,
3239 ppc_get_thread_area
,
3240 ppc_install_fast_tracepoint_jump_pad
,
3242 ppc_get_min_fast_tracepoint_insn_len
,
3243 NULL
, /* supports_range_stepping */
3244 NULL
, /* breakpoint_kind_from_current_state */
3245 ppc_supports_hardware_single_step
,
3246 NULL
, /* get_syscall_trapinfo */
3247 ppc_get_ipa_tdesc_idx
,
3251 initialize_low_arch (void)
3253 /* Initialize the Linux target descriptions. */
3255 init_registers_powerpc_32l ();
3256 init_registers_powerpc_altivec32l ();
3257 init_registers_powerpc_cell32l ();
3258 init_registers_powerpc_vsx32l ();
3259 init_registers_powerpc_isa205_32l ();
3260 init_registers_powerpc_isa205_altivec32l ();
3261 init_registers_powerpc_isa205_vsx32l ();
3262 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3263 init_registers_powerpc_isa207_vsx32l ();
3264 init_registers_powerpc_e500l ();
3266 init_registers_powerpc_64l ();
3267 init_registers_powerpc_altivec64l ();
3268 init_registers_powerpc_cell64l ();
3269 init_registers_powerpc_vsx64l ();
3270 init_registers_powerpc_isa205_64l ();
3271 init_registers_powerpc_isa205_altivec64l ();
3272 init_registers_powerpc_isa205_vsx64l ();
3273 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3274 init_registers_powerpc_isa207_vsx64l ();
3277 initialize_regsets_info (&ppc_regsets_info
);