649baaf56bf64d030983a9d380c43e39cad7e0c5
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 1989 Free Software Foundation, Inc.
4 This file is part of GDB.
6 GDB is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 1, or (at your option)
11 GDB is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GDB; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 * The main tables describing the instructions is essentially a copy
27 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
28 * Programmers Manual. Usually, there is a capital letter, followed
29 * by a small letter. The capital letter tell the addressing mode,
30 * and the small letter tells about the operand size. Refer to
31 * the Intel manual for details.
37 #define Eb OP_E, b_mode
38 #define indirEb OP_indirE, b_mode
39 #define Gb OP_G, b_mode
40 #define Ev OP_E, v_mode
41 #define indirEv OP_indirE, v_mode
42 #define Ew OP_E, w_mode
43 #define Ma OP_E, v_mode
45 #define Mp OP_E, 0 /* ? */
46 #define Gv OP_G, v_mode
47 #define Gw OP_G, w_mode
48 #define Rw OP_rm, w_mode
49 #define Rd OP_rm, d_mode
50 #define Ib OP_I, b_mode
51 #define sIb OP_sI, b_mode /* sign extened byte */
52 #define Iv OP_I, v_mode
53 #define Iw OP_I, w_mode
54 #define Jb OP_J, b_mode
55 #define Jv OP_J, v_mode
57 #define Cd OP_C, d_mode
58 #define Dd OP_D, d_mode
59 #define Td OP_T, d_mode
61 #define eAX OP_REG, eAX_reg
62 #define eBX OP_REG, eBX_reg
63 #define eCX OP_REG, eCX_reg
64 #define eDX OP_REG, eDX_reg
65 #define eSP OP_REG, eSP_reg
66 #define eBP OP_REG, eBP_reg
67 #define eSI OP_REG, eSI_reg
68 #define eDI OP_REG, eDI_reg
69 #define AL OP_REG, al_reg
70 #define CL OP_REG, cl_reg
71 #define DL OP_REG, dl_reg
72 #define BL OP_REG, bl_reg
73 #define AH OP_REG, ah_reg
74 #define CH OP_REG, ch_reg
75 #define DH OP_REG, dh_reg
76 #define BH OP_REG, bh_reg
77 #define AX OP_REG, ax_reg
78 #define DX OP_REG, dx_reg
79 #define indirDX OP_REG, indir_dx_reg
81 #define Sw OP_SEG, w_mode
82 #define Ap OP_DIR, lptr
83 #define Av OP_DIR, v_mode
84 #define Ob OP_OFF, b_mode
85 #define Ov OP_OFF, v_mode
86 #define Xb OP_DSSI, b_mode
87 #define Xv OP_DSSI, v_mode
88 #define Yb OP_ESDI, b_mode
89 #define Yv OP_ESDI, v_mode
91 #define es OP_REG, es_reg
92 #define ss OP_REG, ss_reg
93 #define cs OP_REG, cs_reg
94 #define ds OP_REG, ds_reg
95 #define fs OP_REG, fs_reg
96 #define gs OP_REG, gs_reg
98 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
100 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
101 int OP_D(), OP_T(), OP_rm();
144 #define indir_dx_reg 150
146 #define GRP1b NULL, NULL, 0
147 #define GRP1S NULL, NULL, 1
148 #define GRP1Ss NULL, NULL, 2
149 #define GRP2b NULL, NULL, 3
150 #define GRP2S NULL, NULL, 4
151 #define GRP2b_one NULL, NULL, 5
152 #define GRP2S_one NULL, NULL, 6
153 #define GRP2b_cl NULL, NULL, 7
154 #define GRP2S_cl NULL, NULL, 8
155 #define GRP3b NULL, NULL, 9
156 #define GRP3S NULL, NULL, 10
157 #define GRP4 NULL, NULL, 11
158 #define GRP5 NULL, NULL, 12
159 #define GRP6 NULL, NULL, 13
160 #define GRP7 NULL, NULL, 14
161 #define GRP8 NULL, NULL, 15
164 #define FLOAT NULL, NULL, FLOATCODE
176 struct dis386 dis386
[] = {
194 { "(bad)" }, /* 0x0f extended opcode escape */
220 { "(bad)" }, /* SEG ES prefix */
229 { "(bad)" }, /* SEG CS prefix */
238 { "(bad)" }, /* SEG SS prefix */
247 { "(bad)" }, /* SEG DS prefix */
288 { "boundS", Gv
, Ma
},
290 { "(bad)" }, /* seg fs */
291 { "(bad)" }, /* seg gs */
292 { "(bad)" }, /* op size prefix */
293 { "(bad)" }, /* adr size prefix */
295 { "pushS", Iv
}, /* 386 book wrong */
296 { "imulS", Gv
, Ev
, Iv
},
297 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
298 { "imulS", Gv
, Ev
, Ib
},
299 { "insb", Yb
, indirDX
},
300 { "insS", Yv
, indirDX
},
301 { "outsb", indirDX
, Xb
},
302 { "outsS", indirDX
, Xv
},
341 { "xchgS", eCX
, eAX
},
342 { "xchgS", eDX
, eAX
},
343 { "xchgS", eBX
, eAX
},
344 { "xchgS", eSP
, eAX
},
345 { "xchgS", eBP
, eAX
},
346 { "xchgS", eSI
, eAX
},
347 { "xchgS", eDI
, eAX
},
352 { "(bad)" }, /* fwait */
368 { "testS", eAX
, Iv
},
370 { "stosS", Yv
, eAX
},
372 { "lodsS", eAX
, Xv
},
374 { "scasS", eAX
, Xv
},
443 { "inb", AL
, indirDX
},
444 { "inS", eAX
, indirDX
},
445 { "outb", indirDX
, AL
},
446 { "outS", indirDX
, eAX
},
448 { "(bad)" }, /* lock prefix */
450 { "(bad)" }, /* repne */
451 { "(bad)" }, /* repz */
467 struct dis386 dis386_twobyte
[] = {
478 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
479 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
481 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
482 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
484 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
485 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
487 /* these are all backward in appendix A of the intel book */
497 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
498 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
500 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
501 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
503 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
504 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
507 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
510 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
513 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
516 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
519 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
522 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
525 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
528 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
570 { "shldS", Ev
, Gv
, Ib
},
571 { "shldS", Ev
, Gv
, CL
},
579 { "shrdS", Ev
, Gv
, Ib
},
580 { "shrdS", Ev
, Gv
, CL
},
586 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
588 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
589 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
590 { "movzbS", Gv
, Eb
},
591 { "movzwS", Gv
, Ew
},
599 { "movsbS", Gv
, Eb
},
600 { "movswS", Gv
, Ew
},
602 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
603 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
605 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
606 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
608 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
609 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
612 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
615 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
618 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
621 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
624 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
627 static char obuf
[100];
629 static char scratchbuf
[100];
630 static unsigned char *start_codep
;
631 static unsigned char *codep
;
636 static char *names32
[]={
637 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
639 static char *names16
[] = {
640 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
642 static char *names8
[] = {
643 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
645 static char *names_seg
[] = {
646 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
649 struct dis386 grps
[][8] = {
767 { "imulS", eAX
, Ev
},
769 { "idivS", eAX
, Ev
},
787 { "lcall", indirEv
},
828 #define PREFIX_REPZ 1
829 #define PREFIX_REPNZ 2
830 #define PREFIX_LOCK 4
832 #define PREFIX_SS 0x10
833 #define PREFIX_DS 0x20
834 #define PREFIX_ES 0x40
835 #define PREFIX_FS 0x80
836 #define PREFIX_GS 0x100
837 #define PREFIX_DATA 0x200
838 #define PREFIX_ADR 0x400
839 #define PREFIX_FWAIT 0x800
851 prefixes
|= PREFIX_REPZ
;
854 prefixes
|= PREFIX_REPNZ
;
857 prefixes
|= PREFIX_LOCK
;
860 prefixes
|= PREFIX_CS
;
863 prefixes
|= PREFIX_SS
;
866 prefixes
|= PREFIX_DS
;
869 prefixes
|= PREFIX_ES
;
872 prefixes
|= PREFIX_FS
;
875 prefixes
|= PREFIX_GS
;
878 prefixes
|= PREFIX_DATA
;
881 prefixes
|= PREFIX_ADR
;
884 prefixes
|= PREFIX_FWAIT
;
896 static char op1out
[100], op2out
[100], op3out
[100];
900 * disassemble the first instruction in 'inbuf'. You have to make
901 * sure all of the bytes of the instruction are filled in.
902 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
903 * (see topic "Redundant prefixes" in the "Differences from 8086"
904 * section of the "Virtual 8086 Mode" chapter.)
905 * 'pc' should be the address of this instruction, it will
906 * be used to print the target address if this is a relative jump or call
907 * 'outbuf' gets filled in with the disassembled instruction. it should
908 * be long enough to hold the longest disassembled instruction.
909 * 100 bytes is certainly enough, unless symbol printing is added later
910 * The function returns the length of this instruction in bytes.
912 i386dis (pc
, inbuf
, outbuf
)
914 unsigned char *inbuf
;
920 int enter_instruction
;
921 char *first
, *second
, *third
;
936 enter_instruction
= 1;
938 enter_instruction
= 0;
942 if (prefixes
& PREFIX_REPZ
)
944 if (prefixes
& PREFIX_REPNZ
)
946 if (prefixes
& PREFIX_LOCK
)
949 if ((prefixes
& PREFIX_FWAIT
)
950 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
952 /* fwait not followed by floating point instruction */
954 strcpy (outbuf
, obuf
);
958 /* these would be initialized to 0 if disassembling for 8086 or 286 */
962 if (prefixes
& PREFIX_DATA
)
965 if (prefixes
& PREFIX_ADR
)
972 dp
= &dis386_twobyte
[*++codep
];
974 dp
= &dis386
[*codep
];
976 mod
= (*codep
>> 6) & 3;
977 reg
= (*codep
>> 3) & 7;
980 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
986 if (dp
->name
== NULL
)
987 dp
= &grps
[dp
->bytemode1
][reg
];
993 (*dp
->op1
)(dp
->bytemode1
);
997 (*dp
->op2
)(dp
->bytemode2
);
1001 (*dp
->op3
)(dp
->bytemode3
);
1004 obufp
= obuf
+ strlen (obuf
);
1005 for (i
= strlen (obuf
); i
< 6; i
++)
1009 /* enter instruction is printed with operands in the
1010 * same order as the intel book; everything else
1011 * is printed in reverse order
1013 if (enter_instruction
)
1044 strcpy (outbuf
, obuf
);
1045 return (codep
- inbuf
);
1048 char *float_mem
[] = {
1124 #define STi OP_STi, 0
1125 int OP_ST(), OP_STi();
1127 #define FGRPd9_2 NULL, NULL, 0
1128 #define FGRPd9_4 NULL, NULL, 1
1129 #define FGRPd9_5 NULL, NULL, 2
1130 #define FGRPd9_6 NULL, NULL, 3
1131 #define FGRPd9_7 NULL, NULL, 4
1132 #define FGRPda_5 NULL, NULL, 5
1133 #define FGRPdb_4 NULL, NULL, 6
1134 #define FGRPde_3 NULL, NULL, 7
1135 #define FGRPdf_4 NULL, NULL, 8
1137 struct dis386 float_reg
[][8] = {
1140 { "fadd", ST
, STi
},
1141 { "fmul", ST
, STi
},
1144 { "fsub", ST
, STi
},
1145 { "fsubr", ST
, STi
},
1146 { "fdiv", ST
, STi
},
1147 { "fdivr", ST
, STi
},
1184 { "fadd", STi
, ST
},
1185 { "fmul", STi
, ST
},
1188 { "fsub", STi
, ST
},
1189 { "fsubr", STi
, ST
},
1190 { "fdiv", STi
, ST
},
1191 { "fdivr", STi
, ST
},
1206 { "faddp", STi
, ST
},
1207 { "fmulp", STi
, ST
},
1210 { "fsubp", STi
, ST
},
1211 { "fsubrp", STi
, ST
},
1212 { "fdivp", STi
, ST
},
1213 { "fdivrp", STi
, ST
},
1229 char *fgrps
[][8] = {
1232 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1237 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1242 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1247 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1252 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1257 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1262 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1263 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1268 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1273 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1281 unsigned char floatop
;
1283 floatop
= codep
[-1];
1287 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1294 dp
= &float_reg
[floatop
- 0xd8][reg
];
1295 if (dp
->name
== NULL
)
1297 putop (fgrps
[dp
->bytemode1
][rm
]);
1298 /* instruction fnstsw is only one with strange arg */
1299 if (floatop
== 0xdf && *codep
== 0xe0)
1300 strcpy (op1out
, "%eax");
1307 (*dp
->op1
)(dp
->bytemode1
);
1310 (*dp
->op2
)(dp
->bytemode2
);
1323 sprintf (scratchbuf
, "%%st(%d)", rm
);
1324 oappend (scratchbuf
);
1328 /* capital letters in template are macros */
1334 for (p
= template; *p
; p
++)
1341 case 'C': /* For jcxz/jecxz */
1346 if ((prefixes
& PREFIX_FWAIT
) == 0)
1350 /* operand size flag */
1365 obufp
+= strlen (s
);
1371 if (prefixes
& PREFIX_CS
)
1373 if (prefixes
& PREFIX_DS
)
1375 if (prefixes
& PREFIX_SS
)
1377 if (prefixes
& PREFIX_ES
)
1379 if (prefixes
& PREFIX_FS
)
1381 if (prefixes
& PREFIX_GS
)
1385 OP_indirE (bytemode
)
1401 /* skip mod/rm byte */
1413 oappend (names8
[rm
]);
1416 oappend (names16
[rm
]);
1420 oappend (names32
[rm
]);
1422 oappend (names16
[rm
]);
1425 oappend ("<bad dis table>");
1436 scale
= (*codep
>> 6) & 3;
1437 index
= (*codep
>> 3) & 7;
1448 /* implies havesib and havebase */
1464 disp
= *(char *)codep
++;
1481 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1483 sprintf (scratchbuf
, "%d", disp
);
1484 oappend (scratchbuf
);
1487 if (havebase
|| havesib
)
1491 oappend (names32
[base
]);
1496 sprintf (scratchbuf
, ",%s", names32
[index
]);
1497 oappend (scratchbuf
);
1499 sprintf (scratchbuf
, ",%d", 1 << scale
);
1500 oappend (scratchbuf
);
1511 oappend (names8
[reg
]);
1514 oappend (names16
[reg
]);
1517 oappend (names32
[reg
]);
1521 oappend (names32
[reg
]);
1523 oappend (names16
[reg
]);
1526 oappend ("<internal disassembler error>");
1535 x
= *codep
++ & 0xff;
1536 x
|= (*codep
++ & 0xff) << 8;
1537 x
|= (*codep
++ & 0xff) << 16;
1538 x
|= (*codep
++ & 0xff) << 24;
1546 x
= *codep
++ & 0xff;
1547 x
|= (*codep
++ & 0xff) << 8;
1557 case indir_dx_reg
: s
= "(%dx)"; break;
1558 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1559 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1560 s
= names16
[code
- ax_reg
];
1562 case es_reg
: case ss_reg
: case cs_reg
:
1563 case ds_reg
: case fs_reg
: case gs_reg
:
1564 s
= names_seg
[code
- es_reg
];
1566 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1567 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1568 s
= names8
[code
- al_reg
];
1570 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1571 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1573 s
= names32
[code
- eAX_reg
];
1575 s
= names16
[code
- eAX_reg
];
1578 s
= "<internal disassembler error>";
1591 op
= *codep
++ & 0xff;
1603 oappend ("<internal disassembler error>");
1606 sprintf (scratchbuf
, "$0x%x", op
);
1607 oappend (scratchbuf
);
1617 op
= *(char *)codep
++;
1623 op
= (short)get16();
1626 op
= (short)get16 ();
1629 oappend ("<internal disassembler error>");
1632 sprintf (scratchbuf
, "$0x%x", op
);
1633 oappend (scratchbuf
);
1644 disp
= *(char *)codep
++;
1651 disp
= (short)get16 ();
1652 /* for some reason, a data16 prefix on a jump instruction
1653 means that the pc is masked to 16 bits after the
1654 displacement is added! */
1659 oappend ("<internal disassembelr error>");
1663 sprintf (scratchbuf
, "0x%x",
1664 (start_pc
+ codep
- start_codep
+ disp
) & mask
);
1665 oappend (scratchbuf
);
1671 static char *sreg
[] = {
1672 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1675 oappend (sreg
[reg
]);
1695 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1696 oappend (scratchbuf
);
1702 offset
= (short)get16 ();
1704 sprintf (scratchbuf
, "0x%x",
1705 start_pc
+ codep
- start_codep
+ offset
);
1706 oappend (scratchbuf
);
1709 oappend ("<internal disassembler error>");
1724 sprintf (scratchbuf
, "0x%x", off
);
1725 oappend (scratchbuf
);
1732 oappend (aflag
? "%edi" : "%di");
1740 oappend (aflag
? "%esi" : "%si");
1753 codep
++; /* skip mod/rm */
1754 sprintf (scratchbuf
, "%%cr%d", reg
);
1755 oappend (scratchbuf
);
1761 codep
++; /* skip mod/rm */
1762 sprintf (scratchbuf
, "%%db%d", reg
);
1763 oappend (scratchbuf
);
1769 codep
++; /* skip mod/rm */
1770 sprintf (scratchbuf
, "%%tr%d", reg
);
1771 oappend (scratchbuf
);
1779 oappend (names32
[rm
]);
1782 oappend (names16
[rm
]);
1792 #include "inferior.h"
1795 print_insn (memaddr
, stream
)
1799 unsigned char buffer
[MAXLEN
];
1800 /* should be expanded if disassembler prints symbol names */
1804 read_memory (memaddr
, buffer
, MAXLEN
);
1806 n
= i386dis ((int)memaddr
, buffer
, outbuf
);
1808 fputs (outbuf
, stream
);
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