* defs.h (extract_signed_integer, extract_unsigned_integer,
[deliverable/binutils-gdb.git] / gdb / i386-tdep.c
1 /* Intel 386 target-dependent stuff.
2
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
25 #include "command.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
28 #include "doublest.h"
29 #include "frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "inferior.h"
33 #include "gdbcmd.h"
34 #include "gdbcore.h"
35 #include "gdbtypes.h"
36 #include "objfiles.h"
37 #include "osabi.h"
38 #include "regcache.h"
39 #include "reggroups.h"
40 #include "regset.h"
41 #include "symfile.h"
42 #include "symtab.h"
43 #include "target.h"
44 #include "value.h"
45 #include "dis-asm.h"
46
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
49
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52
53 #include "record.h"
54 #include <stdint.h>
55
56 /* Register names. */
57
58 static char *i386_register_names[] =
59 {
60 "eax", "ecx", "edx", "ebx",
61 "esp", "ebp", "esi", "edi",
62 "eip", "eflags", "cs", "ss",
63 "ds", "es", "fs", "gs",
64 "st0", "st1", "st2", "st3",
65 "st4", "st5", "st6", "st7",
66 "fctrl", "fstat", "ftag", "fiseg",
67 "fioff", "foseg", "fooff", "fop",
68 "xmm0", "xmm1", "xmm2", "xmm3",
69 "xmm4", "xmm5", "xmm6", "xmm7",
70 "mxcsr"
71 };
72
73 static const int i386_num_register_names = ARRAY_SIZE (i386_register_names);
74
75 /* Register names for MMX pseudo-registers. */
76
77 static char *i386_mmx_names[] =
78 {
79 "mm0", "mm1", "mm2", "mm3",
80 "mm4", "mm5", "mm6", "mm7"
81 };
82
83 static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names);
84
85 static int
86 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
87 {
88 int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum;
89
90 if (mm0_regnum < 0)
91 return 0;
92
93 return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs);
94 }
95
96 /* SSE register? */
97
98 static int
99 i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum)
100 {
101 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
102
103 if (I387_NUM_XMM_REGS (tdep) == 0)
104 return 0;
105
106 return (I387_XMM0_REGNUM (tdep) <= regnum
107 && regnum < I387_MXCSR_REGNUM (tdep));
108 }
109
110 static int
111 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
112 {
113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
114
115 if (I387_NUM_XMM_REGS (tdep) == 0)
116 return 0;
117
118 return (regnum == I387_MXCSR_REGNUM (tdep));
119 }
120
121 /* FP register? */
122
123 int
124 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
125 {
126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
127
128 if (I387_ST0_REGNUM (tdep) < 0)
129 return 0;
130
131 return (I387_ST0_REGNUM (tdep) <= regnum
132 && regnum < I387_FCTRL_REGNUM (tdep));
133 }
134
135 int
136 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
137 {
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
139
140 if (I387_ST0_REGNUM (tdep) < 0)
141 return 0;
142
143 return (I387_FCTRL_REGNUM (tdep) <= regnum
144 && regnum < I387_XMM0_REGNUM (tdep));
145 }
146
147 /* Return the name of register REGNUM. */
148
149 const char *
150 i386_register_name (struct gdbarch *gdbarch, int regnum)
151 {
152 if (i386_mmx_regnum_p (gdbarch, regnum))
153 return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))];
154
155 if (regnum >= 0 && regnum < i386_num_register_names)
156 return i386_register_names[regnum];
157
158 return NULL;
159 }
160
161 /* Convert a dbx register number REG to the appropriate register
162 number used by GDB. */
163
164 static int
165 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
166 {
167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
168
169 /* This implements what GCC calls the "default" register map
170 (dbx_register_map[]). */
171
172 if (reg >= 0 && reg <= 7)
173 {
174 /* General-purpose registers. The debug info calls %ebp
175 register 4, and %esp register 5. */
176 if (reg == 4)
177 return 5;
178 else if (reg == 5)
179 return 4;
180 else return reg;
181 }
182 else if (reg >= 12 && reg <= 19)
183 {
184 /* Floating-point registers. */
185 return reg - 12 + I387_ST0_REGNUM (tdep);
186 }
187 else if (reg >= 21 && reg <= 28)
188 {
189 /* SSE registers. */
190 return reg - 21 + I387_XMM0_REGNUM (tdep);
191 }
192 else if (reg >= 29 && reg <= 36)
193 {
194 /* MMX registers. */
195 return reg - 29 + I387_MM0_REGNUM (tdep);
196 }
197
198 /* This will hopefully provoke a warning. */
199 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
200 }
201
202 /* Convert SVR4 register number REG to the appropriate register number
203 used by GDB. */
204
205 static int
206 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
207 {
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
209
210 /* This implements the GCC register map that tries to be compatible
211 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
212
213 /* The SVR4 register numbering includes %eip and %eflags, and
214 numbers the floating point registers differently. */
215 if (reg >= 0 && reg <= 9)
216 {
217 /* General-purpose registers. */
218 return reg;
219 }
220 else if (reg >= 11 && reg <= 18)
221 {
222 /* Floating-point registers. */
223 return reg - 11 + I387_ST0_REGNUM (tdep);
224 }
225 else if (reg >= 21 && reg <= 36)
226 {
227 /* The SSE and MMX registers have the same numbers as with dbx. */
228 return i386_dbx_reg_to_regnum (gdbarch, reg);
229 }
230
231 switch (reg)
232 {
233 case 37: return I387_FCTRL_REGNUM (tdep);
234 case 38: return I387_FSTAT_REGNUM (tdep);
235 case 39: return I387_MXCSR_REGNUM (tdep);
236 case 40: return I386_ES_REGNUM;
237 case 41: return I386_CS_REGNUM;
238 case 42: return I386_SS_REGNUM;
239 case 43: return I386_DS_REGNUM;
240 case 44: return I386_FS_REGNUM;
241 case 45: return I386_GS_REGNUM;
242 }
243
244 /* This will hopefully provoke a warning. */
245 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
246 }
247
248 \f
249
250 /* This is the variable that is set with "set disassembly-flavor", and
251 its legitimate values. */
252 static const char att_flavor[] = "att";
253 static const char intel_flavor[] = "intel";
254 static const char *valid_flavors[] =
255 {
256 att_flavor,
257 intel_flavor,
258 NULL
259 };
260 static const char *disassembly_flavor = att_flavor;
261 \f
262
263 /* Use the program counter to determine the contents and size of a
264 breakpoint instruction. Return a pointer to a string of bytes that
265 encode a breakpoint instruction, store the length of the string in
266 *LEN and optionally adjust *PC to point to the correct memory
267 location for inserting the breakpoint.
268
269 On the i386 we have a single breakpoint that fits in a single byte
270 and can be inserted anywhere.
271
272 This function is 64-bit safe. */
273
274 static const gdb_byte *
275 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
276 {
277 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
278
279 *len = sizeof (break_insn);
280 return break_insn;
281 }
282 \f
283 /* Displaced instruction handling. */
284
285 /* Skip the legacy instruction prefixes in INSN.
286 Not all prefixes are valid for any particular insn
287 but we needn't care, the insn will fault if it's invalid.
288 The result is a pointer to the first opcode byte,
289 or NULL if we run off the end of the buffer. */
290
291 static gdb_byte *
292 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
293 {
294 gdb_byte *end = insn + max_len;
295
296 while (insn < end)
297 {
298 switch (*insn)
299 {
300 case DATA_PREFIX_OPCODE:
301 case ADDR_PREFIX_OPCODE:
302 case CS_PREFIX_OPCODE:
303 case DS_PREFIX_OPCODE:
304 case ES_PREFIX_OPCODE:
305 case FS_PREFIX_OPCODE:
306 case GS_PREFIX_OPCODE:
307 case SS_PREFIX_OPCODE:
308 case LOCK_PREFIX_OPCODE:
309 case REPE_PREFIX_OPCODE:
310 case REPNE_PREFIX_OPCODE:
311 ++insn;
312 continue;
313 default:
314 return insn;
315 }
316 }
317
318 return NULL;
319 }
320
321 static int
322 i386_absolute_jmp_p (const gdb_byte *insn)
323 {
324 /* jmp far (absolute address in operand) */
325 if (insn[0] == 0xea)
326 return 1;
327
328 if (insn[0] == 0xff)
329 {
330 /* jump near, absolute indirect (/4) */
331 if ((insn[1] & 0x38) == 0x20)
332 return 1;
333
334 /* jump far, absolute indirect (/5) */
335 if ((insn[1] & 0x38) == 0x28)
336 return 1;
337 }
338
339 return 0;
340 }
341
342 static int
343 i386_absolute_call_p (const gdb_byte *insn)
344 {
345 /* call far, absolute */
346 if (insn[0] == 0x9a)
347 return 1;
348
349 if (insn[0] == 0xff)
350 {
351 /* Call near, absolute indirect (/2) */
352 if ((insn[1] & 0x38) == 0x10)
353 return 1;
354
355 /* Call far, absolute indirect (/3) */
356 if ((insn[1] & 0x38) == 0x18)
357 return 1;
358 }
359
360 return 0;
361 }
362
363 static int
364 i386_ret_p (const gdb_byte *insn)
365 {
366 switch (insn[0])
367 {
368 case 0xc2: /* ret near, pop N bytes */
369 case 0xc3: /* ret near */
370 case 0xca: /* ret far, pop N bytes */
371 case 0xcb: /* ret far */
372 case 0xcf: /* iret */
373 return 1;
374
375 default:
376 return 0;
377 }
378 }
379
380 static int
381 i386_call_p (const gdb_byte *insn)
382 {
383 if (i386_absolute_call_p (insn))
384 return 1;
385
386 /* call near, relative */
387 if (insn[0] == 0xe8)
388 return 1;
389
390 return 0;
391 }
392
393 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
394 length in bytes. Otherwise, return zero. */
395
396 static int
397 i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp)
398 {
399 if (insn[0] == 0xcd)
400 {
401 *lengthp = 2;
402 return 1;
403 }
404
405 return 0;
406 }
407
408 /* Fix up the state of registers and memory after having single-stepped
409 a displaced instruction. */
410
411 void
412 i386_displaced_step_fixup (struct gdbarch *gdbarch,
413 struct displaced_step_closure *closure,
414 CORE_ADDR from, CORE_ADDR to,
415 struct regcache *regs)
416 {
417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
418
419 /* The offset we applied to the instruction's address.
420 This could well be negative (when viewed as a signed 32-bit
421 value), but ULONGEST won't reflect that, so take care when
422 applying it. */
423 ULONGEST insn_offset = to - from;
424
425 /* Since we use simple_displaced_step_copy_insn, our closure is a
426 copy of the instruction. */
427 gdb_byte *insn = (gdb_byte *) closure;
428 /* The start of the insn, needed in case we see some prefixes. */
429 gdb_byte *insn_start = insn;
430
431 if (debug_displaced)
432 fprintf_unfiltered (gdb_stdlog,
433 "displaced: fixup (%s, %s), "
434 "insn = 0x%02x 0x%02x ...\n",
435 paddress (gdbarch, from), paddress (gdbarch, to),
436 insn[0], insn[1]);
437
438 /* The list of issues to contend with here is taken from
439 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
440 Yay for Free Software! */
441
442 /* Relocate the %eip, if necessary. */
443
444 /* The instruction recognizers we use assume any leading prefixes
445 have been skipped. */
446 {
447 /* This is the size of the buffer in closure. */
448 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
449 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
450 /* If there are too many prefixes, just ignore the insn.
451 It will fault when run. */
452 if (opcode != NULL)
453 insn = opcode;
454 }
455
456 /* Except in the case of absolute or indirect jump or call
457 instructions, or a return instruction, the new eip is relative to
458 the displaced instruction; make it relative. Well, signal
459 handler returns don't need relocation either, but we use the
460 value of %eip to recognize those; see below. */
461 if (! i386_absolute_jmp_p (insn)
462 && ! i386_absolute_call_p (insn)
463 && ! i386_ret_p (insn))
464 {
465 ULONGEST orig_eip;
466 ULONGEST insn_len;
467
468 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
469
470 /* A signal trampoline system call changes the %eip, resuming
471 execution of the main program after the signal handler has
472 returned. That makes them like 'return' instructions; we
473 shouldn't relocate %eip.
474
475 But most system calls don't, and we do need to relocate %eip.
476
477 Our heuristic for distinguishing these cases: if stepping
478 over the system call instruction left control directly after
479 the instruction, the we relocate --- control almost certainly
480 doesn't belong in the displaced copy. Otherwise, we assume
481 the instruction has put control where it belongs, and leave
482 it unrelocated. Goodness help us if there are PC-relative
483 system calls. */
484 if (i386_syscall_p (insn, &insn_len)
485 && orig_eip != to + (insn - insn_start) + insn_len)
486 {
487 if (debug_displaced)
488 fprintf_unfiltered (gdb_stdlog,
489 "displaced: syscall changed %%eip; "
490 "not relocating\n");
491 }
492 else
493 {
494 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
495
496 /* If we just stepped over a breakpoint insn, we don't backup
497 the pc on purpose; this is to match behaviour without
498 stepping. */
499
500 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
501
502 if (debug_displaced)
503 fprintf_unfiltered (gdb_stdlog,
504 "displaced: "
505 "relocated %%eip from %s to %s\n",
506 paddress (gdbarch, orig_eip),
507 paddress (gdbarch, eip));
508 }
509 }
510
511 /* If the instruction was PUSHFL, then the TF bit will be set in the
512 pushed value, and should be cleared. We'll leave this for later,
513 since GDB already messes up the TF flag when stepping over a
514 pushfl. */
515
516 /* If the instruction was a call, the return address now atop the
517 stack is the address following the copied instruction. We need
518 to make it the address following the original instruction. */
519 if (i386_call_p (insn))
520 {
521 ULONGEST esp;
522 ULONGEST retaddr;
523 const ULONGEST retaddr_len = 4;
524
525 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
526 retaddr = read_memory_unsigned_integer (esp, byte_order, retaddr_len);
527 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
528 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
529
530 if (debug_displaced)
531 fprintf_unfiltered (gdb_stdlog,
532 "displaced: relocated return addr at %s to %s\n",
533 paddress (gdbarch, esp),
534 paddress (gdbarch, retaddr));
535 }
536 }
537 \f
538 #ifdef I386_REGNO_TO_SYMMETRY
539 #error "The Sequent Symmetry is no longer supported."
540 #endif
541
542 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
543 and %esp "belong" to the calling function. Therefore these
544 registers should be saved if they're going to be modified. */
545
546 /* The maximum number of saved registers. This should include all
547 registers mentioned above, and %eip. */
548 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
549
550 struct i386_frame_cache
551 {
552 /* Base address. */
553 CORE_ADDR base;
554 LONGEST sp_offset;
555 CORE_ADDR pc;
556
557 /* Saved registers. */
558 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
559 CORE_ADDR saved_sp;
560 int saved_sp_reg;
561 int pc_in_eax;
562
563 /* Stack space reserved for local variables. */
564 long locals;
565 };
566
567 /* Allocate and initialize a frame cache. */
568
569 static struct i386_frame_cache *
570 i386_alloc_frame_cache (void)
571 {
572 struct i386_frame_cache *cache;
573 int i;
574
575 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
576
577 /* Base address. */
578 cache->base = 0;
579 cache->sp_offset = -4;
580 cache->pc = 0;
581
582 /* Saved registers. We initialize these to -1 since zero is a valid
583 offset (that's where %ebp is supposed to be stored). */
584 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
585 cache->saved_regs[i] = -1;
586 cache->saved_sp = 0;
587 cache->saved_sp_reg = -1;
588 cache->pc_in_eax = 0;
589
590 /* Frameless until proven otherwise. */
591 cache->locals = -1;
592
593 return cache;
594 }
595
596 /* If the instruction at PC is a jump, return the address of its
597 target. Otherwise, return PC. */
598
599 static CORE_ADDR
600 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
601 {
602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
603 gdb_byte op;
604 long delta = 0;
605 int data16 = 0;
606
607 target_read_memory (pc, &op, 1);
608 if (op == 0x66)
609 {
610 data16 = 1;
611 op = read_memory_unsigned_integer (pc + 1, 1, byte_order);
612 }
613
614 switch (op)
615 {
616 case 0xe9:
617 /* Relative jump: if data16 == 0, disp32, else disp16. */
618 if (data16)
619 {
620 delta = read_memory_integer (pc + 2, 2, byte_order);
621
622 /* Include the size of the jmp instruction (including the
623 0x66 prefix). */
624 delta += 4;
625 }
626 else
627 {
628 delta = read_memory_integer (pc + 1, 4, byte_order);
629
630 /* Include the size of the jmp instruction. */
631 delta += 5;
632 }
633 break;
634 case 0xeb:
635 /* Relative jump, disp8 (ignore data16). */
636 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
637
638 delta += data16 + 2;
639 break;
640 }
641
642 return pc + delta;
643 }
644
645 /* Check whether PC points at a prologue for a function returning a
646 structure or union. If so, it updates CACHE and returns the
647 address of the first instruction after the code sequence that
648 removes the "hidden" argument from the stack or CURRENT_PC,
649 whichever is smaller. Otherwise, return PC. */
650
651 static CORE_ADDR
652 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
653 struct i386_frame_cache *cache)
654 {
655 /* Functions that return a structure or union start with:
656
657 popl %eax 0x58
658 xchgl %eax, (%esp) 0x87 0x04 0x24
659 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
660
661 (the System V compiler puts out the second `xchg' instruction,
662 and the assembler doesn't try to optimize it, so the 'sib' form
663 gets generated). This sequence is used to get the address of the
664 return buffer for a function that returns a structure. */
665 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
666 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
667 gdb_byte buf[4];
668 gdb_byte op;
669
670 if (current_pc <= pc)
671 return pc;
672
673 target_read_memory (pc, &op, 1);
674
675 if (op != 0x58) /* popl %eax */
676 return pc;
677
678 target_read_memory (pc + 1, buf, 4);
679 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
680 return pc;
681
682 if (current_pc == pc)
683 {
684 cache->sp_offset += 4;
685 return current_pc;
686 }
687
688 if (current_pc == pc + 1)
689 {
690 cache->pc_in_eax = 1;
691 return current_pc;
692 }
693
694 if (buf[1] == proto1[1])
695 return pc + 4;
696 else
697 return pc + 5;
698 }
699
700 static CORE_ADDR
701 i386_skip_probe (CORE_ADDR pc)
702 {
703 /* A function may start with
704
705 pushl constant
706 call _probe
707 addl $4, %esp
708
709 followed by
710
711 pushl %ebp
712
713 etc. */
714 gdb_byte buf[8];
715 gdb_byte op;
716
717 target_read_memory (pc, &op, 1);
718
719 if (op == 0x68 || op == 0x6a)
720 {
721 int delta;
722
723 /* Skip past the `pushl' instruction; it has either a one-byte or a
724 four-byte operand, depending on the opcode. */
725 if (op == 0x68)
726 delta = 5;
727 else
728 delta = 2;
729
730 /* Read the following 8 bytes, which should be `call _probe' (6
731 bytes) followed by `addl $4,%esp' (2 bytes). */
732 read_memory (pc + delta, buf, sizeof (buf));
733 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
734 pc += delta + sizeof (buf);
735 }
736
737 return pc;
738 }
739
740 /* GCC 4.1 and later, can put code in the prologue to realign the
741 stack pointer. Check whether PC points to such code, and update
742 CACHE accordingly. Return the first instruction after the code
743 sequence or CURRENT_PC, whichever is smaller. If we don't
744 recognize the code, return PC. */
745
746 static CORE_ADDR
747 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
748 struct i386_frame_cache *cache)
749 {
750 /* There are 2 code sequences to re-align stack before the frame
751 gets set up:
752
753 1. Use a caller-saved saved register:
754
755 leal 4(%esp), %reg
756 andl $-XXX, %esp
757 pushl -4(%reg)
758
759 2. Use a callee-saved saved register:
760
761 pushl %reg
762 leal 8(%esp), %reg
763 andl $-XXX, %esp
764 pushl -4(%reg)
765
766 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
767
768 0x83 0xe4 0xf0 andl $-16, %esp
769 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
770 */
771
772 gdb_byte buf[14];
773 int reg;
774 int offset, offset_and;
775 static int regnums[8] = {
776 I386_EAX_REGNUM, /* %eax */
777 I386_ECX_REGNUM, /* %ecx */
778 I386_EDX_REGNUM, /* %edx */
779 I386_EBX_REGNUM, /* %ebx */
780 I386_ESP_REGNUM, /* %esp */
781 I386_EBP_REGNUM, /* %ebp */
782 I386_ESI_REGNUM, /* %esi */
783 I386_EDI_REGNUM /* %edi */
784 };
785
786 if (target_read_memory (pc, buf, sizeof buf))
787 return pc;
788
789 /* Check caller-saved saved register. The first instruction has
790 to be "leal 4(%esp), %reg". */
791 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
792 {
793 /* MOD must be binary 10 and R/M must be binary 100. */
794 if ((buf[1] & 0xc7) != 0x44)
795 return pc;
796
797 /* REG has register number. */
798 reg = (buf[1] >> 3) & 7;
799 offset = 4;
800 }
801 else
802 {
803 /* Check callee-saved saved register. The first instruction
804 has to be "pushl %reg". */
805 if ((buf[0] & 0xf8) != 0x50)
806 return pc;
807
808 /* Get register. */
809 reg = buf[0] & 0x7;
810
811 /* The next instruction has to be "leal 8(%esp), %reg". */
812 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
813 return pc;
814
815 /* MOD must be binary 10 and R/M must be binary 100. */
816 if ((buf[2] & 0xc7) != 0x44)
817 return pc;
818
819 /* REG has register number. Registers in pushl and leal have to
820 be the same. */
821 if (reg != ((buf[2] >> 3) & 7))
822 return pc;
823
824 offset = 5;
825 }
826
827 /* Rigister can't be %esp nor %ebp. */
828 if (reg == 4 || reg == 5)
829 return pc;
830
831 /* The next instruction has to be "andl $-XXX, %esp". */
832 if (buf[offset + 1] != 0xe4
833 || (buf[offset] != 0x81 && buf[offset] != 0x83))
834 return pc;
835
836 offset_and = offset;
837 offset += buf[offset] == 0x81 ? 6 : 3;
838
839 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
840 0xfc. REG must be binary 110 and MOD must be binary 01. */
841 if (buf[offset] != 0xff
842 || buf[offset + 2] != 0xfc
843 || (buf[offset + 1] & 0xf8) != 0x70)
844 return pc;
845
846 /* R/M has register. Registers in leal and pushl have to be the
847 same. */
848 if (reg != (buf[offset + 1] & 7))
849 return pc;
850
851 if (current_pc > pc + offset_and)
852 cache->saved_sp_reg = regnums[reg];
853
854 return min (pc + offset + 3, current_pc);
855 }
856
857 /* Maximum instruction length we need to handle. */
858 #define I386_MAX_MATCHED_INSN_LEN 6
859
860 /* Instruction description. */
861 struct i386_insn
862 {
863 size_t len;
864 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
865 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
866 };
867
868 /* Search for the instruction at PC in the list SKIP_INSNS. Return
869 the first instruction description that matches. Otherwise, return
870 NULL. */
871
872 static struct i386_insn *
873 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns)
874 {
875 struct i386_insn *insn;
876 gdb_byte op;
877
878 target_read_memory (pc, &op, 1);
879
880 for (insn = skip_insns; insn->len > 0; insn++)
881 {
882 if ((op & insn->mask[0]) == insn->insn[0])
883 {
884 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
885 int insn_matched = 1;
886 size_t i;
887
888 gdb_assert (insn->len > 1);
889 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN);
890
891 target_read_memory (pc + 1, buf, insn->len - 1);
892 for (i = 1; i < insn->len; i++)
893 {
894 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i])
895 insn_matched = 0;
896 }
897
898 if (insn_matched)
899 return insn;
900 }
901 }
902
903 return NULL;
904 }
905
906 /* Some special instructions that might be migrated by GCC into the
907 part of the prologue that sets up the new stack frame. Because the
908 stack frame hasn't been setup yet, no registers have been saved
909 yet, and only the scratch registers %eax, %ecx and %edx can be
910 touched. */
911
912 struct i386_insn i386_frame_setup_skip_insns[] =
913 {
914 /* Check for `movb imm8, r' and `movl imm32, r'.
915
916 ??? Should we handle 16-bit operand-sizes here? */
917
918 /* `movb imm8, %al' and `movb imm8, %ah' */
919 /* `movb imm8, %cl' and `movb imm8, %ch' */
920 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
921 /* `movb imm8, %dl' and `movb imm8, %dh' */
922 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
923 /* `movl imm32, %eax' and `movl imm32, %ecx' */
924 { 5, { 0xb8 }, { 0xfe } },
925 /* `movl imm32, %edx' */
926 { 5, { 0xba }, { 0xff } },
927
928 /* Check for `mov imm32, r32'. Note that there is an alternative
929 encoding for `mov m32, %eax'.
930
931 ??? Should we handle SIB adressing here?
932 ??? Should we handle 16-bit operand-sizes here? */
933
934 /* `movl m32, %eax' */
935 { 5, { 0xa1 }, { 0xff } },
936 /* `movl m32, %eax' and `mov; m32, %ecx' */
937 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
938 /* `movl m32, %edx' */
939 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
940
941 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
942 Because of the symmetry, there are actually two ways to encode
943 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
944 opcode bytes 0x31 and 0x33 for `xorl'. */
945
946 /* `subl %eax, %eax' */
947 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
948 /* `subl %ecx, %ecx' */
949 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
950 /* `subl %edx, %edx' */
951 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
952 /* `xorl %eax, %eax' */
953 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
954 /* `xorl %ecx, %ecx' */
955 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
956 /* `xorl %edx, %edx' */
957 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
958 { 0 }
959 };
960
961
962 /* Check whether PC points to a no-op instruction. */
963 static CORE_ADDR
964 i386_skip_noop (CORE_ADDR pc)
965 {
966 gdb_byte op;
967 int check = 1;
968
969 target_read_memory (pc, &op, 1);
970
971 while (check)
972 {
973 check = 0;
974 /* Ignore `nop' instruction. */
975 if (op == 0x90)
976 {
977 pc += 1;
978 target_read_memory (pc, &op, 1);
979 check = 1;
980 }
981 /* Ignore no-op instruction `mov %edi, %edi'.
982 Microsoft system dlls often start with
983 a `mov %edi,%edi' instruction.
984 The 5 bytes before the function start are
985 filled with `nop' instructions.
986 This pattern can be used for hot-patching:
987 The `mov %edi, %edi' instruction can be replaced by a
988 near jump to the location of the 5 `nop' instructions
989 which can be replaced by a 32-bit jump to anywhere
990 in the 32-bit address space. */
991
992 else if (op == 0x8b)
993 {
994 target_read_memory (pc + 1, &op, 1);
995 if (op == 0xff)
996 {
997 pc += 2;
998 target_read_memory (pc, &op, 1);
999 check = 1;
1000 }
1001 }
1002 }
1003 return pc;
1004 }
1005
1006 /* Check whether PC points at a code that sets up a new stack frame.
1007 If so, it updates CACHE and returns the address of the first
1008 instruction after the sequence that sets up the frame or LIMIT,
1009 whichever is smaller. If we don't recognize the code, return PC. */
1010
1011 static CORE_ADDR
1012 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1013 CORE_ADDR pc, CORE_ADDR limit,
1014 struct i386_frame_cache *cache)
1015 {
1016 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1017 struct i386_insn *insn;
1018 gdb_byte op;
1019 int skip = 0;
1020
1021 if (limit <= pc)
1022 return limit;
1023
1024 target_read_memory (pc, &op, 1);
1025
1026 if (op == 0x55) /* pushl %ebp */
1027 {
1028 /* Take into account that we've executed the `pushl %ebp' that
1029 starts this instruction sequence. */
1030 cache->saved_regs[I386_EBP_REGNUM] = 0;
1031 cache->sp_offset += 4;
1032 pc++;
1033
1034 /* If that's all, return now. */
1035 if (limit <= pc)
1036 return limit;
1037
1038 /* Check for some special instructions that might be migrated by
1039 GCC into the prologue and skip them. At this point in the
1040 prologue, code should only touch the scratch registers %eax,
1041 %ecx and %edx, so while the number of posibilities is sheer,
1042 it is limited.
1043
1044 Make sure we only skip these instructions if we later see the
1045 `movl %esp, %ebp' that actually sets up the frame. */
1046 while (pc + skip < limit)
1047 {
1048 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1049 if (insn == NULL)
1050 break;
1051
1052 skip += insn->len;
1053 }
1054
1055 /* If that's all, return now. */
1056 if (limit <= pc + skip)
1057 return limit;
1058
1059 target_read_memory (pc + skip, &op, 1);
1060
1061 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1062 switch (op)
1063 {
1064 case 0x8b:
1065 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1066 != 0xec)
1067 return pc;
1068 break;
1069 case 0x89:
1070 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order)
1071 != 0xe5)
1072 return pc;
1073 break;
1074 default:
1075 return pc;
1076 }
1077
1078 /* OK, we actually have a frame. We just don't know how large
1079 it is yet. Set its size to zero. We'll adjust it if
1080 necessary. We also now commit to skipping the special
1081 instructions mentioned before. */
1082 cache->locals = 0;
1083 pc += (skip + 2);
1084
1085 /* If that's all, return now. */
1086 if (limit <= pc)
1087 return limit;
1088
1089 /* Check for stack adjustment
1090
1091 subl $XXX, %esp
1092
1093 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1094 reg, so we don't have to worry about a data16 prefix. */
1095 target_read_memory (pc, &op, 1);
1096 if (op == 0x83)
1097 {
1098 /* `subl' with 8-bit immediate. */
1099 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1100 /* Some instruction starting with 0x83 other than `subl'. */
1101 return pc;
1102
1103 /* `subl' with signed 8-bit immediate (though it wouldn't
1104 make sense to be negative). */
1105 cache->locals = read_memory_integer (pc + 2, 1, byte_order);
1106 return pc + 3;
1107 }
1108 else if (op == 0x81)
1109 {
1110 /* Maybe it is `subl' with a 32-bit immediate. */
1111 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1112 /* Some instruction starting with 0x81 other than `subl'. */
1113 return pc;
1114
1115 /* It is `subl' with a 32-bit immediate. */
1116 cache->locals = read_memory_integer (pc + 2, 4, byte_order);
1117 return pc + 6;
1118 }
1119 else
1120 {
1121 /* Some instruction other than `subl'. */
1122 return pc;
1123 }
1124 }
1125 else if (op == 0xc8) /* enter */
1126 {
1127 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order);
1128 return pc + 4;
1129 }
1130
1131 return pc;
1132 }
1133
1134 /* Check whether PC points at code that saves registers on the stack.
1135 If so, it updates CACHE and returns the address of the first
1136 instruction after the register saves or CURRENT_PC, whichever is
1137 smaller. Otherwise, return PC. */
1138
1139 static CORE_ADDR
1140 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1141 struct i386_frame_cache *cache)
1142 {
1143 CORE_ADDR offset = 0;
1144 gdb_byte op;
1145 int i;
1146
1147 if (cache->locals > 0)
1148 offset -= cache->locals;
1149 for (i = 0; i < 8 && pc < current_pc; i++)
1150 {
1151 target_read_memory (pc, &op, 1);
1152 if (op < 0x50 || op > 0x57)
1153 break;
1154
1155 offset -= 4;
1156 cache->saved_regs[op - 0x50] = offset;
1157 cache->sp_offset += 4;
1158 pc++;
1159 }
1160
1161 return pc;
1162 }
1163
1164 /* Do a full analysis of the prologue at PC and update CACHE
1165 accordingly. Bail out early if CURRENT_PC is reached. Return the
1166 address where the analysis stopped.
1167
1168 We handle these cases:
1169
1170 The startup sequence can be at the start of the function, or the
1171 function can start with a branch to startup code at the end.
1172
1173 %ebp can be set up with either the 'enter' instruction, or "pushl
1174 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1175 once used in the System V compiler).
1176
1177 Local space is allocated just below the saved %ebp by either the
1178 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1179 16-bit unsigned argument for space to allocate, and the 'addl'
1180 instruction could have either a signed byte, or 32-bit immediate.
1181
1182 Next, the registers used by this function are pushed. With the
1183 System V compiler they will always be in the order: %edi, %esi,
1184 %ebx (and sometimes a harmless bug causes it to also save but not
1185 restore %eax); however, the code below is willing to see the pushes
1186 in any order, and will handle up to 8 of them.
1187
1188 If the setup sequence is at the end of the function, then the next
1189 instruction will be a branch back to the start. */
1190
1191 static CORE_ADDR
1192 i386_analyze_prologue (struct gdbarch *gdbarch,
1193 CORE_ADDR pc, CORE_ADDR current_pc,
1194 struct i386_frame_cache *cache)
1195 {
1196 pc = i386_skip_noop (pc);
1197 pc = i386_follow_jump (gdbarch, pc);
1198 pc = i386_analyze_struct_return (pc, current_pc, cache);
1199 pc = i386_skip_probe (pc);
1200 pc = i386_analyze_stack_align (pc, current_pc, cache);
1201 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1202 return i386_analyze_register_saves (pc, current_pc, cache);
1203 }
1204
1205 /* Return PC of first real instruction. */
1206
1207 static CORE_ADDR
1208 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1209 {
1210 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1211
1212 static gdb_byte pic_pat[6] =
1213 {
1214 0xe8, 0, 0, 0, 0, /* call 0x0 */
1215 0x5b, /* popl %ebx */
1216 };
1217 struct i386_frame_cache cache;
1218 CORE_ADDR pc;
1219 gdb_byte op;
1220 int i;
1221
1222 cache.locals = -1;
1223 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1224 if (cache.locals < 0)
1225 return start_pc;
1226
1227 /* Found valid frame setup. */
1228
1229 /* The native cc on SVR4 in -K PIC mode inserts the following code
1230 to get the address of the global offset table (GOT) into register
1231 %ebx:
1232
1233 call 0x0
1234 popl %ebx
1235 movl %ebx,x(%ebp) (optional)
1236 addl y,%ebx
1237
1238 This code is with the rest of the prologue (at the end of the
1239 function), so we have to skip it to get to the first real
1240 instruction at the start of the function. */
1241
1242 for (i = 0; i < 6; i++)
1243 {
1244 target_read_memory (pc + i, &op, 1);
1245 if (pic_pat[i] != op)
1246 break;
1247 }
1248 if (i == 6)
1249 {
1250 int delta = 6;
1251
1252 target_read_memory (pc + delta, &op, 1);
1253
1254 if (op == 0x89) /* movl %ebx, x(%ebp) */
1255 {
1256 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order);
1257
1258 if (op == 0x5d) /* One byte offset from %ebp. */
1259 delta += 3;
1260 else if (op == 0x9d) /* Four byte offset from %ebp. */
1261 delta += 6;
1262 else /* Unexpected instruction. */
1263 delta = 0;
1264
1265 target_read_memory (pc + delta, &op, 1);
1266 }
1267
1268 /* addl y,%ebx */
1269 if (delta > 0 && op == 0x81
1270 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order)
1271 == 0xc3)
1272 {
1273 pc += delta + 6;
1274 }
1275 }
1276
1277 /* If the function starts with a branch (to startup code at the end)
1278 the last instruction should bring us back to the first
1279 instruction of the real code. */
1280 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1281 pc = i386_follow_jump (gdbarch, pc);
1282
1283 return pc;
1284 }
1285
1286 /* Check that the code pointed to by PC corresponds to a call to
1287 __main, skip it if so. Return PC otherwise. */
1288
1289 CORE_ADDR
1290 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1291 {
1292 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1293 gdb_byte op;
1294
1295 target_read_memory (pc, &op, 1);
1296 if (op == 0xe8)
1297 {
1298 gdb_byte buf[4];
1299
1300 if (target_read_memory (pc + 1, buf, sizeof buf) == 0)
1301 {
1302 /* Make sure address is computed correctly as a 32bit
1303 integer even if CORE_ADDR is 64 bit wide. */
1304 struct minimal_symbol *s;
1305 CORE_ADDR call_dest;
1306
1307 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1308 call_dest = call_dest & 0xffffffffU;
1309 s = lookup_minimal_symbol_by_pc (call_dest);
1310 if (s != NULL
1311 && SYMBOL_LINKAGE_NAME (s) != NULL
1312 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1313 pc += 5;
1314 }
1315 }
1316
1317 return pc;
1318 }
1319
1320 /* This function is 64-bit safe. */
1321
1322 static CORE_ADDR
1323 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1324 {
1325 gdb_byte buf[8];
1326
1327 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1328 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1329 }
1330 \f
1331
1332 /* Normal frames. */
1333
1334 static struct i386_frame_cache *
1335 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
1336 {
1337 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1338 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1339 struct i386_frame_cache *cache;
1340 gdb_byte buf[4];
1341 int i;
1342
1343 if (*this_cache)
1344 return *this_cache;
1345
1346 cache = i386_alloc_frame_cache ();
1347 *this_cache = cache;
1348
1349 /* In principle, for normal frames, %ebp holds the frame pointer,
1350 which holds the base address for the current stack frame.
1351 However, for functions that don't need it, the frame pointer is
1352 optional. For these "frameless" functions the frame pointer is
1353 actually the frame pointer of the calling frame. Signal
1354 trampolines are just a special case of a "frameless" function.
1355 They (usually) share their frame pointer with the frame that was
1356 in progress when the signal occurred. */
1357
1358 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1359 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1360 if (cache->base == 0)
1361 return cache;
1362
1363 /* For normal frames, %eip is stored at 4(%ebp). */
1364 cache->saved_regs[I386_EIP_REGNUM] = 4;
1365
1366 cache->pc = get_frame_func (this_frame);
1367 if (cache->pc != 0)
1368 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1369 cache);
1370
1371 if (cache->saved_sp_reg != -1)
1372 {
1373 /* Saved stack pointer has been saved. */
1374 get_frame_register (this_frame, cache->saved_sp_reg, buf);
1375 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1376 }
1377
1378 if (cache->locals < 0)
1379 {
1380 /* We didn't find a valid frame, which means that CACHE->base
1381 currently holds the frame pointer for our calling frame. If
1382 we're at the start of a function, or somewhere half-way its
1383 prologue, the function's frame probably hasn't been fully
1384 setup yet. Try to reconstruct the base address for the stack
1385 frame by looking at the stack pointer. For truly "frameless"
1386 functions this might work too. */
1387
1388 if (cache->saved_sp_reg != -1)
1389 {
1390 /* We're halfway aligning the stack. */
1391 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1392 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
1393
1394 /* This will be added back below. */
1395 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
1396 }
1397 else
1398 {
1399 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1400 cache->base = extract_unsigned_integer (buf, 4, byte_order)
1401 + cache->sp_offset;
1402 }
1403 }
1404
1405 /* Now that we have the base address for the stack frame we can
1406 calculate the value of %esp in the calling frame. */
1407 if (cache->saved_sp == 0)
1408 cache->saved_sp = cache->base + 8;
1409
1410 /* Adjust all the saved registers such that they contain addresses
1411 instead of offsets. */
1412 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1413 if (cache->saved_regs[i] != -1)
1414 cache->saved_regs[i] += cache->base;
1415
1416 return cache;
1417 }
1418
1419 static void
1420 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
1421 struct frame_id *this_id)
1422 {
1423 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1424
1425 /* This marks the outermost frame. */
1426 if (cache->base == 0)
1427 return;
1428
1429 /* See the end of i386_push_dummy_call. */
1430 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
1431 }
1432
1433 static struct value *
1434 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1435 int regnum)
1436 {
1437 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1438
1439 gdb_assert (regnum >= 0);
1440
1441 /* The System V ABI says that:
1442
1443 "The flags register contains the system flags, such as the
1444 direction flag and the carry flag. The direction flag must be
1445 set to the forward (that is, zero) direction before entry and
1446 upon exit from a function. Other user flags have no specified
1447 role in the standard calling sequence and are not preserved."
1448
1449 To guarantee the "upon exit" part of that statement we fake a
1450 saved flags register that has its direction flag cleared.
1451
1452 Note that GCC doesn't seem to rely on the fact that the direction
1453 flag is cleared after a function return; it always explicitly
1454 clears the flag before operations where it matters.
1455
1456 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1457 right thing to do. The way we fake the flags register here makes
1458 it impossible to change it. */
1459
1460 if (regnum == I386_EFLAGS_REGNUM)
1461 {
1462 ULONGEST val;
1463
1464 val = get_frame_register_unsigned (this_frame, regnum);
1465 val &= ~(1 << 10);
1466 return frame_unwind_got_constant (this_frame, regnum, val);
1467 }
1468
1469 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
1470 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
1471
1472 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
1473 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1474
1475 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1476 return frame_unwind_got_memory (this_frame, regnum,
1477 cache->saved_regs[regnum]);
1478
1479 return frame_unwind_got_register (this_frame, regnum, regnum);
1480 }
1481
1482 static const struct frame_unwind i386_frame_unwind =
1483 {
1484 NORMAL_FRAME,
1485 i386_frame_this_id,
1486 i386_frame_prev_register,
1487 NULL,
1488 default_frame_sniffer
1489 };
1490 \f
1491
1492 /* Signal trampolines. */
1493
1494 static struct i386_frame_cache *
1495 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
1496 {
1497 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1498 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1499 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1500 struct i386_frame_cache *cache;
1501 CORE_ADDR addr;
1502 gdb_byte buf[4];
1503
1504 if (*this_cache)
1505 return *this_cache;
1506
1507 cache = i386_alloc_frame_cache ();
1508
1509 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
1510 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
1511
1512 addr = tdep->sigcontext_addr (this_frame);
1513 if (tdep->sc_reg_offset)
1514 {
1515 int i;
1516
1517 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
1518
1519 for (i = 0; i < tdep->sc_num_regs; i++)
1520 if (tdep->sc_reg_offset[i] != -1)
1521 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
1522 }
1523 else
1524 {
1525 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
1526 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
1527 }
1528
1529 *this_cache = cache;
1530 return cache;
1531 }
1532
1533 static void
1534 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
1535 struct frame_id *this_id)
1536 {
1537 struct i386_frame_cache *cache =
1538 i386_sigtramp_frame_cache (this_frame, this_cache);
1539
1540 /* See the end of i386_push_dummy_call. */
1541 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
1542 }
1543
1544 static struct value *
1545 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
1546 void **this_cache, int regnum)
1547 {
1548 /* Make sure we've initialized the cache. */
1549 i386_sigtramp_frame_cache (this_frame, this_cache);
1550
1551 return i386_frame_prev_register (this_frame, this_cache, regnum);
1552 }
1553
1554 static int
1555 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
1556 struct frame_info *this_frame,
1557 void **this_prologue_cache)
1558 {
1559 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1560
1561 /* We shouldn't even bother if we don't have a sigcontext_addr
1562 handler. */
1563 if (tdep->sigcontext_addr == NULL)
1564 return 0;
1565
1566 if (tdep->sigtramp_p != NULL)
1567 {
1568 if (tdep->sigtramp_p (this_frame))
1569 return 1;
1570 }
1571
1572 if (tdep->sigtramp_start != 0)
1573 {
1574 CORE_ADDR pc = get_frame_pc (this_frame);
1575
1576 gdb_assert (tdep->sigtramp_end != 0);
1577 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1578 return 1;
1579 }
1580
1581 return 0;
1582 }
1583
1584 static const struct frame_unwind i386_sigtramp_frame_unwind =
1585 {
1586 SIGTRAMP_FRAME,
1587 i386_sigtramp_frame_this_id,
1588 i386_sigtramp_frame_prev_register,
1589 NULL,
1590 i386_sigtramp_frame_sniffer
1591 };
1592 \f
1593
1594 static CORE_ADDR
1595 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
1596 {
1597 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
1598
1599 return cache->base;
1600 }
1601
1602 static const struct frame_base i386_frame_base =
1603 {
1604 &i386_frame_unwind,
1605 i386_frame_base_address,
1606 i386_frame_base_address,
1607 i386_frame_base_address
1608 };
1609
1610 static struct frame_id
1611 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1612 {
1613 CORE_ADDR fp;
1614
1615 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
1616
1617 /* See the end of i386_push_dummy_call. */
1618 return frame_id_build (fp + 8, get_frame_pc (this_frame));
1619 }
1620 \f
1621
1622 /* Figure out where the longjmp will land. Slurp the args out of the
1623 stack. We expect the first arg to be a pointer to the jmp_buf
1624 structure from which we extract the address that we will land at.
1625 This address is copied into PC. This routine returns non-zero on
1626 success. */
1627
1628 static int
1629 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1630 {
1631 gdb_byte buf[4];
1632 CORE_ADDR sp, jb_addr;
1633 struct gdbarch *gdbarch = get_frame_arch (frame);
1634 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1635 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
1636
1637 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1638 longjmp will land. */
1639 if (jb_pc_offset == -1)
1640 return 0;
1641
1642 get_frame_register (frame, I386_ESP_REGNUM, buf);
1643 sp = extract_unsigned_integer (buf, 4, byte_order);
1644 if (target_read_memory (sp + 4, buf, 4))
1645 return 0;
1646
1647 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1648 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
1649 return 0;
1650
1651 *pc = extract_unsigned_integer (buf, 4, byte_order);
1652 return 1;
1653 }
1654 \f
1655
1656 /* Check whether TYPE must be 16-byte-aligned when passed as a
1657 function argument. 16-byte vectors, _Decimal128 and structures or
1658 unions containing such types must be 16-byte-aligned; other
1659 arguments are 4-byte-aligned. */
1660
1661 static int
1662 i386_16_byte_align_p (struct type *type)
1663 {
1664 type = check_typedef (type);
1665 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
1666 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
1667 && TYPE_LENGTH (type) == 16)
1668 return 1;
1669 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1670 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
1671 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1672 || TYPE_CODE (type) == TYPE_CODE_UNION)
1673 {
1674 int i;
1675 for (i = 0; i < TYPE_NFIELDS (type); i++)
1676 {
1677 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
1678 return 1;
1679 }
1680 }
1681 return 0;
1682 }
1683
1684 static CORE_ADDR
1685 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1686 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1687 struct value **args, CORE_ADDR sp, int struct_return,
1688 CORE_ADDR struct_addr)
1689 {
1690 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1691 gdb_byte buf[4];
1692 int i;
1693 int write_pass;
1694 int args_space = 0;
1695
1696 /* Determine the total space required for arguments and struct
1697 return address in a first pass (allowing for 16-byte-aligned
1698 arguments), then push arguments in a second pass. */
1699
1700 for (write_pass = 0; write_pass < 2; write_pass++)
1701 {
1702 int args_space_used = 0;
1703 int have_16_byte_aligned_arg = 0;
1704
1705 if (struct_return)
1706 {
1707 if (write_pass)
1708 {
1709 /* Push value address. */
1710 store_unsigned_integer (buf, 4, byte_order, struct_addr);
1711 write_memory (sp, buf, 4);
1712 args_space_used += 4;
1713 }
1714 else
1715 args_space += 4;
1716 }
1717
1718 for (i = 0; i < nargs; i++)
1719 {
1720 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
1721
1722 if (write_pass)
1723 {
1724 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1725 args_space_used = align_up (args_space_used, 16);
1726
1727 write_memory (sp + args_space_used,
1728 value_contents_all (args[i]), len);
1729 /* The System V ABI says that:
1730
1731 "An argument's size is increased, if necessary, to make it a
1732 multiple of [32-bit] words. This may require tail padding,
1733 depending on the size of the argument."
1734
1735 This makes sure the stack stays word-aligned. */
1736 args_space_used += align_up (len, 4);
1737 }
1738 else
1739 {
1740 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
1741 {
1742 args_space = align_up (args_space, 16);
1743 have_16_byte_aligned_arg = 1;
1744 }
1745 args_space += align_up (len, 4);
1746 }
1747 }
1748
1749 if (!write_pass)
1750 {
1751 if (have_16_byte_aligned_arg)
1752 args_space = align_up (args_space, 16);
1753 sp -= args_space;
1754 }
1755 }
1756
1757 /* Store return address. */
1758 sp -= 4;
1759 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1760 write_memory (sp, buf, 4);
1761
1762 /* Finally, update the stack pointer... */
1763 store_unsigned_integer (buf, 4, byte_order, sp);
1764 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1765
1766 /* ...and fake a frame pointer. */
1767 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1768
1769 /* MarkK wrote: This "+ 8" is all over the place:
1770 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1771 i386_dummy_id). It's there, since all frame unwinders for
1772 a given target have to agree (within a certain margin) on the
1773 definition of the stack address of a frame. Otherwise frame id
1774 comparison might not work correctly. Since DWARF2/GCC uses the
1775 stack address *before* the function call as a frame's CFA. On
1776 the i386, when %ebp is used as a frame pointer, the offset
1777 between the contents %ebp and the CFA as defined by GCC. */
1778 return sp + 8;
1779 }
1780
1781 /* These registers are used for returning integers (and on some
1782 targets also for returning `struct' and `union' values when their
1783 size and alignment match an integer type). */
1784 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1785 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1786
1787 /* Read, for architecture GDBARCH, a function return value of TYPE
1788 from REGCACHE, and copy that into VALBUF. */
1789
1790 static void
1791 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1792 struct regcache *regcache, gdb_byte *valbuf)
1793 {
1794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1795 int len = TYPE_LENGTH (type);
1796 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1797
1798 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1799 {
1800 if (tdep->st0_regnum < 0)
1801 {
1802 warning (_("Cannot find floating-point return value."));
1803 memset (valbuf, 0, len);
1804 return;
1805 }
1806
1807 /* Floating-point return values can be found in %st(0). Convert
1808 its contents to the desired type. This is probably not
1809 exactly how it would happen on the target itself, but it is
1810 the best we can do. */
1811 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
1812 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
1813 }
1814 else
1815 {
1816 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1817 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1818
1819 if (len <= low_size)
1820 {
1821 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1822 memcpy (valbuf, buf, len);
1823 }
1824 else if (len <= (low_size + high_size))
1825 {
1826 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
1827 memcpy (valbuf, buf, low_size);
1828 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
1829 memcpy (valbuf + low_size, buf, len - low_size);
1830 }
1831 else
1832 internal_error (__FILE__, __LINE__,
1833 _("Cannot extract return value of %d bytes long."), len);
1834 }
1835 }
1836
1837 /* Write, for architecture GDBARCH, a function return value of TYPE
1838 from VALBUF into REGCACHE. */
1839
1840 static void
1841 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
1842 struct regcache *regcache, const gdb_byte *valbuf)
1843 {
1844 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1845 int len = TYPE_LENGTH (type);
1846
1847 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1848 {
1849 ULONGEST fstat;
1850 gdb_byte buf[I386_MAX_REGISTER_SIZE];
1851
1852 if (tdep->st0_regnum < 0)
1853 {
1854 warning (_("Cannot set floating-point return value."));
1855 return;
1856 }
1857
1858 /* Returning floating-point values is a bit tricky. Apart from
1859 storing the return value in %st(0), we have to simulate the
1860 state of the FPU at function return point. */
1861
1862 /* Convert the value found in VALBUF to the extended
1863 floating-point format used by the FPU. This is probably
1864 not exactly how it would happen on the target itself, but
1865 it is the best we can do. */
1866 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
1867 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
1868
1869 /* Set the top of the floating-point register stack to 7. The
1870 actual value doesn't really matter, but 7 is what a normal
1871 function return would end up with if the program started out
1872 with a freshly initialized FPU. */
1873 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1874 fstat |= (7 << 11);
1875 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1876
1877 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1878 the floating-point register stack to 7, the appropriate value
1879 for the tag word is 0x3fff. */
1880 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1881 }
1882 else
1883 {
1884 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
1885 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
1886
1887 if (len <= low_size)
1888 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
1889 else if (len <= (low_size + high_size))
1890 {
1891 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
1892 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
1893 len - low_size, valbuf + low_size);
1894 }
1895 else
1896 internal_error (__FILE__, __LINE__,
1897 _("Cannot store return value of %d bytes long."), len);
1898 }
1899 }
1900 \f
1901
1902 /* This is the variable that is set with "set struct-convention", and
1903 its legitimate values. */
1904 static const char default_struct_convention[] = "default";
1905 static const char pcc_struct_convention[] = "pcc";
1906 static const char reg_struct_convention[] = "reg";
1907 static const char *valid_conventions[] =
1908 {
1909 default_struct_convention,
1910 pcc_struct_convention,
1911 reg_struct_convention,
1912 NULL
1913 };
1914 static const char *struct_convention = default_struct_convention;
1915
1916 /* Return non-zero if TYPE, which is assumed to be a structure,
1917 a union type, or an array type, should be returned in registers
1918 for architecture GDBARCH. */
1919
1920 static int
1921 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
1922 {
1923 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1924 enum type_code code = TYPE_CODE (type);
1925 int len = TYPE_LENGTH (type);
1926
1927 gdb_assert (code == TYPE_CODE_STRUCT
1928 || code == TYPE_CODE_UNION
1929 || code == TYPE_CODE_ARRAY);
1930
1931 if (struct_convention == pcc_struct_convention
1932 || (struct_convention == default_struct_convention
1933 && tdep->struct_return == pcc_struct_return))
1934 return 0;
1935
1936 /* Structures consisting of a single `float', `double' or 'long
1937 double' member are returned in %st(0). */
1938 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
1939 {
1940 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1941 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1942 return (len == 4 || len == 8 || len == 12);
1943 }
1944
1945 return (len == 1 || len == 2 || len == 4 || len == 8);
1946 }
1947
1948 /* Determine, for architecture GDBARCH, how a return value of TYPE
1949 should be returned. If it is supposed to be returned in registers,
1950 and READBUF is non-zero, read the appropriate value from REGCACHE,
1951 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1952 from WRITEBUF into REGCACHE. */
1953
1954 static enum return_value_convention
1955 i386_return_value (struct gdbarch *gdbarch, struct type *func_type,
1956 struct type *type, struct regcache *regcache,
1957 gdb_byte *readbuf, const gdb_byte *writebuf)
1958 {
1959 enum type_code code = TYPE_CODE (type);
1960
1961 if (((code == TYPE_CODE_STRUCT
1962 || code == TYPE_CODE_UNION
1963 || code == TYPE_CODE_ARRAY)
1964 && !i386_reg_struct_return_p (gdbarch, type))
1965 /* 128-bit decimal float uses the struct return convention. */
1966 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
1967 {
1968 /* The System V ABI says that:
1969
1970 "A function that returns a structure or union also sets %eax
1971 to the value of the original address of the caller's area
1972 before it returns. Thus when the caller receives control
1973 again, the address of the returned object resides in register
1974 %eax and can be used to access the object."
1975
1976 So the ABI guarantees that we can always find the return
1977 value just after the function has returned. */
1978
1979 /* Note that the ABI doesn't mention functions returning arrays,
1980 which is something possible in certain languages such as Ada.
1981 In this case, the value is returned as if it was wrapped in
1982 a record, so the convention applied to records also applies
1983 to arrays. */
1984
1985 if (readbuf)
1986 {
1987 ULONGEST addr;
1988
1989 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
1990 read_memory (addr, readbuf, TYPE_LENGTH (type));
1991 }
1992
1993 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
1994 }
1995
1996 /* This special case is for structures consisting of a single
1997 `float', `double' or 'long double' member. These structures are
1998 returned in %st(0). For these structures, we call ourselves
1999 recursively, changing TYPE into the type of the first member of
2000 the structure. Since that should work for all structures that
2001 have only one member, we don't bother to check the member's type
2002 here. */
2003 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2004 {
2005 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2006 return i386_return_value (gdbarch, func_type, type, regcache,
2007 readbuf, writebuf);
2008 }
2009
2010 if (readbuf)
2011 i386_extract_return_value (gdbarch, type, regcache, readbuf);
2012 if (writebuf)
2013 i386_store_return_value (gdbarch, type, regcache, writebuf);
2014
2015 return RETURN_VALUE_REGISTER_CONVENTION;
2016 }
2017 \f
2018
2019 /* Construct types for ISA-specific registers. */
2020 struct type *
2021 i386_eflags_type (struct gdbarch *gdbarch)
2022 {
2023 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2024
2025 if (!tdep->i386_eflags_type)
2026 {
2027 struct type *type;
2028
2029 type = arch_flags_type (gdbarch, "builtin_type_i386_eflags", 4);
2030 append_flags_type_flag (type, 0, "CF");
2031 append_flags_type_flag (type, 1, NULL);
2032 append_flags_type_flag (type, 2, "PF");
2033 append_flags_type_flag (type, 4, "AF");
2034 append_flags_type_flag (type, 6, "ZF");
2035 append_flags_type_flag (type, 7, "SF");
2036 append_flags_type_flag (type, 8, "TF");
2037 append_flags_type_flag (type, 9, "IF");
2038 append_flags_type_flag (type, 10, "DF");
2039 append_flags_type_flag (type, 11, "OF");
2040 append_flags_type_flag (type, 14, "NT");
2041 append_flags_type_flag (type, 16, "RF");
2042 append_flags_type_flag (type, 17, "VM");
2043 append_flags_type_flag (type, 18, "AC");
2044 append_flags_type_flag (type, 19, "VIF");
2045 append_flags_type_flag (type, 20, "VIP");
2046 append_flags_type_flag (type, 21, "ID");
2047
2048 tdep->i386_eflags_type = type;
2049 }
2050
2051 return tdep->i386_eflags_type;
2052 }
2053
2054 struct type *
2055 i386_mxcsr_type (struct gdbarch *gdbarch)
2056 {
2057 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2058
2059 if (!tdep->i386_mxcsr_type)
2060 {
2061 struct type *type;
2062
2063 type = arch_flags_type (gdbarch, "builtin_type_i386_mxcsr", 4);
2064 append_flags_type_flag (type, 0, "IE");
2065 append_flags_type_flag (type, 1, "DE");
2066 append_flags_type_flag (type, 2, "ZE");
2067 append_flags_type_flag (type, 3, "OE");
2068 append_flags_type_flag (type, 4, "UE");
2069 append_flags_type_flag (type, 5, "PE");
2070 append_flags_type_flag (type, 6, "DAZ");
2071 append_flags_type_flag (type, 7, "IM");
2072 append_flags_type_flag (type, 8, "DM");
2073 append_flags_type_flag (type, 9, "ZM");
2074 append_flags_type_flag (type, 10, "OM");
2075 append_flags_type_flag (type, 11, "UM");
2076 append_flags_type_flag (type, 12, "PM");
2077 append_flags_type_flag (type, 15, "FZ");
2078
2079 tdep->i386_mxcsr_type = type;
2080 }
2081
2082 return tdep->i386_mxcsr_type;
2083 }
2084
2085 struct type *
2086 i387_ext_type (struct gdbarch *gdbarch)
2087 {
2088 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2089
2090 if (!tdep->i387_ext_type)
2091 tdep->i387_ext_type
2092 = arch_float_type (gdbarch, -1, "builtin_type_i387_ext",
2093 floatformats_i387_ext);
2094
2095 return tdep->i387_ext_type;
2096 }
2097
2098 /* Construct vector type for MMX registers. */
2099 struct type *
2100 i386_mmx_type (struct gdbarch *gdbarch)
2101 {
2102 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2103
2104 if (!tdep->i386_mmx_type)
2105 {
2106 const struct builtin_type *bt = builtin_type (gdbarch);
2107
2108 /* The type we're building is this: */
2109 #if 0
2110 union __gdb_builtin_type_vec64i
2111 {
2112 int64_t uint64;
2113 int32_t v2_int32[2];
2114 int16_t v4_int16[4];
2115 int8_t v8_int8[8];
2116 };
2117 #endif
2118
2119 struct type *t;
2120
2121 t = arch_composite_type (gdbarch,
2122 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
2123
2124 append_composite_type_field (t, "uint64", bt->builtin_int64);
2125 append_composite_type_field (t, "v2_int32",
2126 init_vector_type (bt->builtin_int32, 2));
2127 append_composite_type_field (t, "v4_int16",
2128 init_vector_type (bt->builtin_int16, 4));
2129 append_composite_type_field (t, "v8_int8",
2130 init_vector_type (bt->builtin_int8, 8));
2131
2132 TYPE_VECTOR (t) = 1;
2133 TYPE_NAME (t) = "builtin_type_vec64i";
2134 tdep->i386_mmx_type = t;
2135 }
2136
2137 return tdep->i386_mmx_type;
2138 }
2139
2140 struct type *
2141 i386_sse_type (struct gdbarch *gdbarch)
2142 {
2143 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2144
2145 if (!tdep->i386_sse_type)
2146 {
2147 const struct builtin_type *bt = builtin_type (gdbarch);
2148
2149 /* The type we're building is this: */
2150 #if 0
2151 union __gdb_builtin_type_vec128i
2152 {
2153 int128_t uint128;
2154 int64_t v2_int64[2];
2155 int32_t v4_int32[4];
2156 int16_t v8_int16[8];
2157 int8_t v16_int8[16];
2158 double v2_double[2];
2159 float v4_float[4];
2160 };
2161 #endif
2162
2163 struct type *t;
2164
2165 t = arch_composite_type (gdbarch,
2166 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION);
2167 append_composite_type_field (t, "v4_float",
2168 init_vector_type (bt->builtin_float, 4));
2169 append_composite_type_field (t, "v2_double",
2170 init_vector_type (bt->builtin_double, 2));
2171 append_composite_type_field (t, "v16_int8",
2172 init_vector_type (bt->builtin_int8, 16));
2173 append_composite_type_field (t, "v8_int16",
2174 init_vector_type (bt->builtin_int16, 8));
2175 append_composite_type_field (t, "v4_int32",
2176 init_vector_type (bt->builtin_int32, 4));
2177 append_composite_type_field (t, "v2_int64",
2178 init_vector_type (bt->builtin_int64, 2));
2179 append_composite_type_field (t, "uint128", bt->builtin_int128);
2180
2181 TYPE_VECTOR (t) = 1;
2182 TYPE_NAME (t) = "builtin_type_vec128i";
2183 tdep->i386_sse_type = t;
2184 }
2185
2186 return tdep->i386_sse_type;
2187 }
2188
2189 /* Return the GDB type object for the "standard" data type of data in
2190 register REGNUM. Perhaps %esi and %edi should go here, but
2191 potentially they could be used for things other than address. */
2192
2193 static struct type *
2194 i386_register_type (struct gdbarch *gdbarch, int regnum)
2195 {
2196 if (regnum == I386_EIP_REGNUM)
2197 return builtin_type (gdbarch)->builtin_func_ptr;
2198
2199 if (regnum == I386_EFLAGS_REGNUM)
2200 return i386_eflags_type (gdbarch);
2201
2202 if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM)
2203 return builtin_type (gdbarch)->builtin_data_ptr;
2204
2205 if (i386_fp_regnum_p (gdbarch, regnum))
2206 return i387_ext_type (gdbarch);
2207
2208 if (i386_mmx_regnum_p (gdbarch, regnum))
2209 return i386_mmx_type (gdbarch);
2210
2211 if (i386_sse_regnum_p (gdbarch, regnum))
2212 return i386_sse_type (gdbarch);
2213
2214 if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch)))
2215 return i386_mxcsr_type (gdbarch);
2216
2217 return builtin_type (gdbarch)->builtin_int;
2218 }
2219
2220 /* Map a cooked register onto a raw register or memory. For the i386,
2221 the MMX registers need to be mapped onto floating point registers. */
2222
2223 static int
2224 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
2225 {
2226 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
2227 int mmxreg, fpreg;
2228 ULONGEST fstat;
2229 int tos;
2230
2231 mmxreg = regnum - tdep->mm0_regnum;
2232 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2233 tos = (fstat >> 11) & 0x7;
2234 fpreg = (mmxreg + tos) % 8;
2235
2236 return (I387_ST0_REGNUM (tdep) + fpreg);
2237 }
2238
2239 static void
2240 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2241 int regnum, gdb_byte *buf)
2242 {
2243 if (i386_mmx_regnum_p (gdbarch, regnum))
2244 {
2245 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2246 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2247
2248 /* Extract (always little endian). */
2249 regcache_raw_read (regcache, fpnum, mmx_buf);
2250 memcpy (buf, mmx_buf, register_size (gdbarch, regnum));
2251 }
2252 else
2253 regcache_raw_read (regcache, regnum, buf);
2254 }
2255
2256 static void
2257 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2258 int regnum, const gdb_byte *buf)
2259 {
2260 if (i386_mmx_regnum_p (gdbarch, regnum))
2261 {
2262 gdb_byte mmx_buf[MAX_REGISTER_SIZE];
2263 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
2264
2265 /* Read ... */
2266 regcache_raw_read (regcache, fpnum, mmx_buf);
2267 /* ... Modify ... (always little endian). */
2268 memcpy (mmx_buf, buf, register_size (gdbarch, regnum));
2269 /* ... Write. */
2270 regcache_raw_write (regcache, fpnum, mmx_buf);
2271 }
2272 else
2273 regcache_raw_write (regcache, regnum, buf);
2274 }
2275 \f
2276
2277 /* Return the register number of the register allocated by GCC after
2278 REGNUM, or -1 if there is no such register. */
2279
2280 static int
2281 i386_next_regnum (int regnum)
2282 {
2283 /* GCC allocates the registers in the order:
2284
2285 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2286
2287 Since storing a variable in %esp doesn't make any sense we return
2288 -1 for %ebp and for %esp itself. */
2289 static int next_regnum[] =
2290 {
2291 I386_EDX_REGNUM, /* Slot for %eax. */
2292 I386_EBX_REGNUM, /* Slot for %ecx. */
2293 I386_ECX_REGNUM, /* Slot for %edx. */
2294 I386_ESI_REGNUM, /* Slot for %ebx. */
2295 -1, -1, /* Slots for %esp and %ebp. */
2296 I386_EDI_REGNUM, /* Slot for %esi. */
2297 I386_EBP_REGNUM /* Slot for %edi. */
2298 };
2299
2300 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
2301 return next_regnum[regnum];
2302
2303 return -1;
2304 }
2305
2306 /* Return nonzero if a value of type TYPE stored in register REGNUM
2307 needs any special handling. */
2308
2309 static int
2310 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
2311 {
2312 int len = TYPE_LENGTH (type);
2313
2314 /* Values may be spread across multiple registers. Most debugging
2315 formats aren't expressive enough to specify the locations, so
2316 some heuristics is involved. Right now we only handle types that
2317 have a length that is a multiple of the word size, since GCC
2318 doesn't seem to put any other types into registers. */
2319 if (len > 4 && len % 4 == 0)
2320 {
2321 int last_regnum = regnum;
2322
2323 while (len > 4)
2324 {
2325 last_regnum = i386_next_regnum (last_regnum);
2326 len -= 4;
2327 }
2328
2329 if (last_regnum != -1)
2330 return 1;
2331 }
2332
2333 return i387_convert_register_p (gdbarch, regnum, type);
2334 }
2335
2336 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2337 return its contents in TO. */
2338
2339 static void
2340 i386_register_to_value (struct frame_info *frame, int regnum,
2341 struct type *type, gdb_byte *to)
2342 {
2343 struct gdbarch *gdbarch = get_frame_arch (frame);
2344 int len = TYPE_LENGTH (type);
2345
2346 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2347 available in FRAME (i.e. if it wasn't saved)? */
2348
2349 if (i386_fp_regnum_p (gdbarch, regnum))
2350 {
2351 i387_register_to_value (frame, regnum, type, to);
2352 return;
2353 }
2354
2355 /* Read a value spread across multiple registers. */
2356
2357 gdb_assert (len > 4 && len % 4 == 0);
2358
2359 while (len > 0)
2360 {
2361 gdb_assert (regnum != -1);
2362 gdb_assert (register_size (gdbarch, regnum) == 4);
2363
2364 get_frame_register (frame, regnum, to);
2365 regnum = i386_next_regnum (regnum);
2366 len -= 4;
2367 to += 4;
2368 }
2369 }
2370
2371 /* Write the contents FROM of a value of type TYPE into register
2372 REGNUM in frame FRAME. */
2373
2374 static void
2375 i386_value_to_register (struct frame_info *frame, int regnum,
2376 struct type *type, const gdb_byte *from)
2377 {
2378 int len = TYPE_LENGTH (type);
2379
2380 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
2381 {
2382 i387_value_to_register (frame, regnum, type, from);
2383 return;
2384 }
2385
2386 /* Write a value spread across multiple registers. */
2387
2388 gdb_assert (len > 4 && len % 4 == 0);
2389
2390 while (len > 0)
2391 {
2392 gdb_assert (regnum != -1);
2393 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
2394
2395 put_frame_register (frame, regnum, from);
2396 regnum = i386_next_regnum (regnum);
2397 len -= 4;
2398 from += 4;
2399 }
2400 }
2401 \f
2402 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2403 in the general-purpose register set REGSET to register cache
2404 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2405
2406 void
2407 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
2408 int regnum, const void *gregs, size_t len)
2409 {
2410 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2411 const gdb_byte *regs = gregs;
2412 int i;
2413
2414 gdb_assert (len == tdep->sizeof_gregset);
2415
2416 for (i = 0; i < tdep->gregset_num_regs; i++)
2417 {
2418 if ((regnum == i || regnum == -1)
2419 && tdep->gregset_reg_offset[i] != -1)
2420 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
2421 }
2422 }
2423
2424 /* Collect register REGNUM from the register cache REGCACHE and store
2425 it in the buffer specified by GREGS and LEN as described by the
2426 general-purpose register set REGSET. If REGNUM is -1, do this for
2427 all registers in REGSET. */
2428
2429 void
2430 i386_collect_gregset (const struct regset *regset,
2431 const struct regcache *regcache,
2432 int regnum, void *gregs, size_t len)
2433 {
2434 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2435 gdb_byte *regs = gregs;
2436 int i;
2437
2438 gdb_assert (len == tdep->sizeof_gregset);
2439
2440 for (i = 0; i < tdep->gregset_num_regs; i++)
2441 {
2442 if ((regnum == i || regnum == -1)
2443 && tdep->gregset_reg_offset[i] != -1)
2444 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
2445 }
2446 }
2447
2448 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2449 in the floating-point register set REGSET to register cache
2450 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2451
2452 static void
2453 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2454 int regnum, const void *fpregs, size_t len)
2455 {
2456 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2457
2458 if (len == I387_SIZEOF_FXSAVE)
2459 {
2460 i387_supply_fxsave (regcache, regnum, fpregs);
2461 return;
2462 }
2463
2464 gdb_assert (len == tdep->sizeof_fpregset);
2465 i387_supply_fsave (regcache, regnum, fpregs);
2466 }
2467
2468 /* Collect register REGNUM from the register cache REGCACHE and store
2469 it in the buffer specified by FPREGS and LEN as described by the
2470 floating-point register set REGSET. If REGNUM is -1, do this for
2471 all registers in REGSET. */
2472
2473 static void
2474 i386_collect_fpregset (const struct regset *regset,
2475 const struct regcache *regcache,
2476 int regnum, void *fpregs, size_t len)
2477 {
2478 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
2479
2480 if (len == I387_SIZEOF_FXSAVE)
2481 {
2482 i387_collect_fxsave (regcache, regnum, fpregs);
2483 return;
2484 }
2485
2486 gdb_assert (len == tdep->sizeof_fpregset);
2487 i387_collect_fsave (regcache, regnum, fpregs);
2488 }
2489
2490 /* Return the appropriate register set for the core section identified
2491 by SECT_NAME and SECT_SIZE. */
2492
2493 const struct regset *
2494 i386_regset_from_core_section (struct gdbarch *gdbarch,
2495 const char *sect_name, size_t sect_size)
2496 {
2497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2498
2499 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
2500 {
2501 if (tdep->gregset == NULL)
2502 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset,
2503 i386_collect_gregset);
2504 return tdep->gregset;
2505 }
2506
2507 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
2508 || (strcmp (sect_name, ".reg-xfp") == 0
2509 && sect_size == I387_SIZEOF_FXSAVE))
2510 {
2511 if (tdep->fpregset == NULL)
2512 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset,
2513 i386_collect_fpregset);
2514 return tdep->fpregset;
2515 }
2516
2517 return NULL;
2518 }
2519 \f
2520
2521 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2522
2523 CORE_ADDR
2524 i386_pe_skip_trampoline_code (struct frame_info *frame,
2525 CORE_ADDR pc, char *name)
2526 {
2527 struct gdbarch *gdbarch = get_frame_arch (frame);
2528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2529
2530 /* jmp *(dest) */
2531 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
2532 {
2533 unsigned long indirect =
2534 read_memory_unsigned_integer (pc + 2, 4, byte_order);
2535 struct minimal_symbol *indsym =
2536 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
2537 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
2538
2539 if (symname)
2540 {
2541 if (strncmp (symname, "__imp_", 6) == 0
2542 || strncmp (symname, "_imp_", 5) == 0)
2543 return name ? 1 :
2544 read_memory_unsigned_integer (indirect, 4, byte_order);
2545 }
2546 }
2547 return 0; /* Not a trampoline. */
2548 }
2549 \f
2550
2551 /* Return whether the THIS_FRAME corresponds to a sigtramp
2552 routine. */
2553
2554 int
2555 i386_sigtramp_p (struct frame_info *this_frame)
2556 {
2557 CORE_ADDR pc = get_frame_pc (this_frame);
2558 char *name;
2559
2560 find_pc_partial_function (pc, &name, NULL, NULL);
2561 return (name && strcmp ("_sigtramp", name) == 0);
2562 }
2563 \f
2564
2565 /* We have two flavours of disassembly. The machinery on this page
2566 deals with switching between those. */
2567
2568 static int
2569 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
2570 {
2571 gdb_assert (disassembly_flavor == att_flavor
2572 || disassembly_flavor == intel_flavor);
2573
2574 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2575 constified, cast to prevent a compiler warning. */
2576 info->disassembler_options = (char *) disassembly_flavor;
2577
2578 return print_insn_i386 (pc, info);
2579 }
2580 \f
2581
2582 /* There are a few i386 architecture variants that differ only
2583 slightly from the generic i386 target. For now, we don't give them
2584 their own source file, but include them here. As a consequence,
2585 they'll always be included. */
2586
2587 /* System V Release 4 (SVR4). */
2588
2589 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2590 routine. */
2591
2592 static int
2593 i386_svr4_sigtramp_p (struct frame_info *this_frame)
2594 {
2595 CORE_ADDR pc = get_frame_pc (this_frame);
2596 char *name;
2597
2598 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2599 currently unknown. */
2600 find_pc_partial_function (pc, &name, NULL, NULL);
2601 return (name && (strcmp ("_sigreturn", name) == 0
2602 || strcmp ("_sigacthandler", name) == 0
2603 || strcmp ("sigvechandler", name) == 0));
2604 }
2605
2606 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2607 address of the associated sigcontext (ucontext) structure. */
2608
2609 static CORE_ADDR
2610 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
2611 {
2612 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2614 gdb_byte buf[4];
2615 CORE_ADDR sp;
2616
2617 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2618 sp = extract_unsigned_integer (buf, 4, byte_order);
2619
2620 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
2621 }
2622 \f
2623
2624 /* Generic ELF. */
2625
2626 void
2627 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2628 {
2629 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2630 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2631 }
2632
2633 /* System V Release 4 (SVR4). */
2634
2635 void
2636 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2637 {
2638 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2639
2640 /* System V Release 4 uses ELF. */
2641 i386_elf_init_abi (info, gdbarch);
2642
2643 /* System V Release 4 has shared libraries. */
2644 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
2645
2646 tdep->sigtramp_p = i386_svr4_sigtramp_p;
2647 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
2648 tdep->sc_pc_offset = 36 + 14 * 4;
2649 tdep->sc_sp_offset = 36 + 17 * 4;
2650
2651 tdep->jb_pc_offset = 20;
2652 }
2653
2654 /* DJGPP. */
2655
2656 static void
2657 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2658 {
2659 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2660
2661 /* DJGPP doesn't have any special frames for signal handlers. */
2662 tdep->sigtramp_p = NULL;
2663
2664 tdep->jb_pc_offset = 36;
2665
2666 /* DJGPP does not support the SSE registers. */
2667 tdep->num_xmm_regs = 0;
2668 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS);
2669
2670 /* Native compiler is GCC, which uses the SVR4 register numbering
2671 even in COFF and STABS. See the comment in i386_gdbarch_init,
2672 before the calls to set_gdbarch_stab_reg_to_regnum and
2673 set_gdbarch_sdb_reg_to_regnum. */
2674 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2675 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
2676 }
2677 \f
2678
2679 /* i386 register groups. In addition to the normal groups, add "mmx"
2680 and "sse". */
2681
2682 static struct reggroup *i386_sse_reggroup;
2683 static struct reggroup *i386_mmx_reggroup;
2684
2685 static void
2686 i386_init_reggroups (void)
2687 {
2688 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
2689 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
2690 }
2691
2692 static void
2693 i386_add_reggroups (struct gdbarch *gdbarch)
2694 {
2695 reggroup_add (gdbarch, i386_sse_reggroup);
2696 reggroup_add (gdbarch, i386_mmx_reggroup);
2697 reggroup_add (gdbarch, general_reggroup);
2698 reggroup_add (gdbarch, float_reggroup);
2699 reggroup_add (gdbarch, all_reggroup);
2700 reggroup_add (gdbarch, save_reggroup);
2701 reggroup_add (gdbarch, restore_reggroup);
2702 reggroup_add (gdbarch, vector_reggroup);
2703 reggroup_add (gdbarch, system_reggroup);
2704 }
2705
2706 int
2707 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2708 struct reggroup *group)
2709 {
2710 int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum)
2711 || i386_mxcsr_regnum_p (gdbarch, regnum));
2712 int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
2713 || i386_fpc_regnum_p (gdbarch, regnum));
2714 int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum));
2715
2716 if (group == i386_mmx_reggroup)
2717 return mmx_regnum_p;
2718 if (group == i386_sse_reggroup)
2719 return sse_regnum_p;
2720 if (group == vector_reggroup)
2721 return (mmx_regnum_p || sse_regnum_p);
2722 if (group == float_reggroup)
2723 return fp_regnum_p;
2724 if (group == general_reggroup)
2725 return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p);
2726
2727 return default_register_reggroup_p (gdbarch, regnum, group);
2728 }
2729 \f
2730
2731 /* Get the ARGIth function argument for the current function. */
2732
2733 static CORE_ADDR
2734 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
2735 struct type *type)
2736 {
2737 struct gdbarch *gdbarch = get_frame_arch (frame);
2738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2739 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
2740 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
2741 }
2742
2743 static void
2744 i386_skip_permanent_breakpoint (struct regcache *regcache)
2745 {
2746 CORE_ADDR current_pc = regcache_read_pc (regcache);
2747
2748 /* On i386, breakpoint is exactly 1 byte long, so we just
2749 adjust the PC in the regcache. */
2750 current_pc += 1;
2751 regcache_write_pc (regcache, current_pc);
2752 }
2753
2754
2755 #define PREFIX_REPZ 0x01
2756 #define PREFIX_REPNZ 0x02
2757 #define PREFIX_LOCK 0x04
2758 #define PREFIX_DATA 0x08
2759 #define PREFIX_ADDR 0x10
2760
2761 /* operand size */
2762 enum
2763 {
2764 OT_BYTE = 0,
2765 OT_WORD,
2766 OT_LONG,
2767 };
2768
2769 /* i386 arith/logic operations */
2770 enum
2771 {
2772 OP_ADDL,
2773 OP_ORL,
2774 OP_ADCL,
2775 OP_SBBL,
2776 OP_ANDL,
2777 OP_SUBL,
2778 OP_XORL,
2779 OP_CMPL,
2780 };
2781
2782 struct i386_record_s
2783 {
2784 struct regcache *regcache;
2785 CORE_ADDR addr;
2786 int aflag;
2787 int dflag;
2788 int override;
2789 uint8_t modrm;
2790 uint8_t mod, reg, rm;
2791 int ot;
2792 };
2793
2794 /* Parse "modrm" part in current memory address that irp->addr point to
2795 Return -1 if something wrong. */
2796
2797 static int
2798 i386_record_modrm (struct i386_record_s *irp)
2799 {
2800 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
2801
2802 if (target_read_memory (irp->addr, &irp->modrm, 1))
2803 {
2804 if (record_debug)
2805 printf_unfiltered (_("Process record: error reading memory at "
2806 "addr %s len = 1.\n"),
2807 paddress (gdbarch, irp->addr));
2808 return -1;
2809 }
2810 irp->addr++;
2811 irp->mod = (irp->modrm >> 6) & 3;
2812 irp->reg = (irp->modrm >> 3) & 7;
2813 irp->rm = irp->modrm & 7;
2814
2815 return 0;
2816 }
2817
2818 /* Get the memory address that current instruction write to and set it to
2819 the argument "addr".
2820 Return -1 if something wrong. */
2821
2822 static int
2823 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr)
2824 {
2825 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
2826 uint8_t tmpu8;
2827 uint16_t tmpu16;
2828 uint32_t tmpu32;
2829
2830 *addr = 0;
2831 if (irp->aflag)
2832 {
2833 /* 32 bits */
2834 int havesib = 0;
2835 uint8_t scale = 0;
2836 uint8_t index = 0;
2837 uint8_t base = irp->rm;
2838
2839 if (base == 4)
2840 {
2841 havesib = 1;
2842 if (target_read_memory (irp->addr, &tmpu8, 1))
2843 {
2844 if (record_debug)
2845 printf_unfiltered (_("Process record: error reading memory "
2846 "at addr %s len = 1.\n"),
2847 paddress (gdbarch, irp->addr));
2848 return -1;
2849 }
2850 irp->addr++;
2851 scale = (tmpu8 >> 6) & 3;
2852 index = ((tmpu8 >> 3) & 7);
2853 base = (tmpu8 & 7);
2854 }
2855
2856 switch (irp->mod)
2857 {
2858 case 0:
2859 if ((base & 7) == 5)
2860 {
2861 base = 0xff;
2862 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2863 {
2864 if (record_debug)
2865 printf_unfiltered (_("Process record: error reading "
2866 "memory at addr %s len = 4.\n"),
2867 paddress (gdbarch, irp->addr));
2868 return -1;
2869 }
2870 irp->addr += 4;
2871 }
2872 else
2873 {
2874 *addr = 0;
2875 }
2876 break;
2877 case 1:
2878 if (target_read_memory (irp->addr, &tmpu8, 1))
2879 {
2880 if (record_debug)
2881 printf_unfiltered (_("Process record: error reading memory "
2882 "at addr %s len = 1.\n"),
2883 paddress (gdbarch, irp->addr));
2884 return -1;
2885 }
2886 irp->addr++;
2887 *addr = (int8_t) tmpu8;
2888 break;
2889 case 2:
2890 if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
2891 {
2892 if (record_debug)
2893 printf_unfiltered (_("Process record: error reading memory "
2894 "at addr %s len = 4.\n"),
2895 paddress (gdbarch, irp->addr));
2896 return -1;
2897 }
2898 irp->addr += 4;
2899 break;
2900 }
2901
2902 if (base != 0xff)
2903 {
2904 regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32);
2905 *addr += tmpu32;
2906 }
2907
2908 /* XXX: index == 4 is always invalid */
2909 if (havesib && (index != 4 || scale != 0))
2910 {
2911 regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32);
2912 *addr += tmpu32 << scale;
2913 }
2914 }
2915 else
2916 {
2917 /* 16 bits */
2918 switch (irp->mod)
2919 {
2920 case 0:
2921 if (irp->rm == 6)
2922 {
2923 if (target_read_memory
2924 (irp->addr, (gdb_byte *) & tmpu16, 2))
2925 {
2926 if (record_debug)
2927 printf_unfiltered (_("Process record: error reading "
2928 "memory at addr %s len = 2.\n"),
2929 paddress (gdbarch, irp->addr));
2930 return -1;
2931 }
2932 irp->addr += 2;
2933 *addr = (int16_t) tmpu16;
2934 irp->rm = 0;
2935 goto no_rm;
2936 }
2937 else
2938 {
2939 *addr = 0;
2940 }
2941 break;
2942 case 1:
2943 if (target_read_memory (irp->addr, &tmpu8, 1))
2944 {
2945 if (record_debug)
2946 printf_unfiltered (_("Process record: error reading memory "
2947 "at addr %s len = 1.\n"),
2948 paddress (gdbarch, irp->addr));
2949 return -1;
2950 }
2951 irp->addr++;
2952 *addr = (int8_t) tmpu8;
2953 break;
2954 case 2:
2955 if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2))
2956 {
2957 if (record_debug)
2958 printf_unfiltered (_("Process record: error reading memory "
2959 "at addr %s len = 2.\n"),
2960 paddress (gdbarch, irp->addr));
2961 return -1;
2962 }
2963 irp->addr += 2;
2964 *addr = (int16_t) tmpu16;
2965 break;
2966 }
2967
2968 switch (irp->rm)
2969 {
2970 case 0:
2971 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2972 (gdb_byte *) & tmpu32);
2973 *addr += tmpu32;
2974 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2975 (gdb_byte *) & tmpu32);
2976 *addr += tmpu32;
2977 break;
2978 case 1:
2979 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
2980 (gdb_byte *) & tmpu32);
2981 *addr += tmpu32;
2982 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2983 (gdb_byte *) & tmpu32);
2984 *addr += tmpu32;
2985 break;
2986 case 2:
2987 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2988 (gdb_byte *) & tmpu32);
2989 *addr += tmpu32;
2990 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
2991 (gdb_byte *) & tmpu32);
2992 *addr += tmpu32;
2993 break;
2994 case 3:
2995 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
2996 (gdb_byte *) & tmpu32);
2997 *addr += tmpu32;
2998 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
2999 (gdb_byte *) & tmpu32);
3000 *addr += tmpu32;
3001 break;
3002 case 4:
3003 regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
3004 (gdb_byte *) & tmpu32);
3005 *addr += tmpu32;
3006 break;
3007 case 5:
3008 regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
3009 (gdb_byte *) & tmpu32);
3010 *addr += tmpu32;
3011 break;
3012 case 6:
3013 regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
3014 (gdb_byte *) & tmpu32);
3015 *addr += tmpu32;
3016 break;
3017 case 7:
3018 regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
3019 (gdb_byte *) & tmpu32);
3020 *addr += tmpu32;
3021 break;
3022 }
3023 *addr &= 0xffff;
3024 }
3025
3026 no_rm:
3027 return 0;
3028 }
3029
3030 /* Record the value of the memory that willbe changed in current instruction
3031 to "record_arch_list".
3032 Return -1 if something wrong. */
3033
3034 static int
3035 i386_record_lea_modrm (struct i386_record_s *irp)
3036 {
3037 struct gdbarch *gdbarch = get_regcache_arch (irp->regcache);
3038 uint32_t addr;
3039
3040 if (irp->override)
3041 {
3042 if (record_debug)
3043 printf_unfiltered (_("Process record ignores the memory change "
3044 "of instruction at address %s because it "
3045 "can't get the value of the segment register.\n"),
3046 paddress (gdbarch, irp->addr));
3047 return 0;
3048 }
3049
3050 if (i386_record_lea_modrm_addr (irp, &addr))
3051 return -1;
3052
3053 if (record_arch_list_add_mem (addr, 1 << irp->ot))
3054 return -1;
3055
3056 return 0;
3057 }
3058
3059 /* Parse the current instruction and record the values of the registers and
3060 memory that will be changed in current instruction to "record_arch_list".
3061 Return -1 if something wrong. */
3062
3063 int
3064 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
3065 CORE_ADDR addr)
3066 {
3067 int prefixes = 0;
3068 uint8_t tmpu8;
3069 uint16_t tmpu16;
3070 uint32_t tmpu32;
3071 uint32_t opcode;
3072 struct i386_record_s ir;
3073
3074 memset (&ir, 0, sizeof (struct i386_record_s));
3075 ir.regcache = regcache;
3076 ir.addr = addr;
3077 ir.aflag = 1;
3078 ir.dflag = 1;
3079
3080 if (record_debug > 1)
3081 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
3082 "addr = %s\n",
3083 paddress (gdbarch, ir.addr));
3084
3085 /* prefixes */
3086 while (1)
3087 {
3088 if (target_read_memory (ir.addr, &tmpu8, 1))
3089 {
3090 if (record_debug)
3091 printf_unfiltered (_("Process record: error reading memory at "
3092 "addr %s len = 1.\n"),
3093 paddress (gdbarch, ir.addr));
3094 return -1;
3095 }
3096 ir.addr++;
3097 switch (tmpu8)
3098 {
3099 case 0xf3:
3100 prefixes |= PREFIX_REPZ;
3101 break;
3102 case 0xf2:
3103 prefixes |= PREFIX_REPNZ;
3104 break;
3105 case 0xf0:
3106 prefixes |= PREFIX_LOCK;
3107 break;
3108 case 0x2e:
3109 ir.override = I386_CS_REGNUM;
3110 break;
3111 case 0x36:
3112 ir.override = I386_SS_REGNUM;
3113 break;
3114 case 0x3e:
3115 ir.override = I386_DS_REGNUM;
3116 break;
3117 case 0x26:
3118 ir.override = I386_ES_REGNUM;
3119 break;
3120 case 0x64:
3121 ir.override = I386_FS_REGNUM;
3122 break;
3123 case 0x65:
3124 ir.override = I386_GS_REGNUM;
3125 break;
3126 case 0x66:
3127 prefixes |= PREFIX_DATA;
3128 break;
3129 case 0x67:
3130 prefixes |= PREFIX_ADDR;
3131 break;
3132 default:
3133 goto out_prefixes;
3134 break;
3135 }
3136 }
3137 out_prefixes:
3138 if (prefixes & PREFIX_DATA)
3139 ir.dflag ^= 1;
3140 if (prefixes & PREFIX_ADDR)
3141 ir.aflag ^= 1;
3142
3143 /* now check op code */
3144 opcode = (uint32_t) tmpu8;
3145 reswitch:
3146 switch (opcode)
3147 {
3148 case 0x0f:
3149 if (target_read_memory (ir.addr, &tmpu8, 1))
3150 {
3151 if (record_debug)
3152 printf_unfiltered (_("Process record: error reading memory at "
3153 "addr %s len = 1.\n"),
3154 paddress (gdbarch, ir.addr));
3155 return -1;
3156 }
3157 ir.addr++;
3158 opcode = (uint16_t) tmpu8 | 0x0f00;
3159 goto reswitch;
3160 break;
3161
3162 /* arith & logic */
3163 case 0x00:
3164 case 0x01:
3165 case 0x02:
3166 case 0x03:
3167 case 0x04:
3168 case 0x05:
3169 case 0x08:
3170 case 0x09:
3171 case 0x0a:
3172 case 0x0b:
3173 case 0x0c:
3174 case 0x0d:
3175 case 0x10:
3176 case 0x11:
3177 case 0x12:
3178 case 0x13:
3179 case 0x14:
3180 case 0x15:
3181 case 0x18:
3182 case 0x19:
3183 case 0x1a:
3184 case 0x1b:
3185 case 0x1c:
3186 case 0x1d:
3187 case 0x20:
3188 case 0x21:
3189 case 0x22:
3190 case 0x23:
3191 case 0x24:
3192 case 0x25:
3193 case 0x28:
3194 case 0x29:
3195 case 0x2a:
3196 case 0x2b:
3197 case 0x2c:
3198 case 0x2d:
3199 case 0x30:
3200 case 0x31:
3201 case 0x32:
3202 case 0x33:
3203 case 0x34:
3204 case 0x35:
3205 case 0x38:
3206 case 0x39:
3207 case 0x3a:
3208 case 0x3b:
3209 case 0x3c:
3210 case 0x3d:
3211 if (((opcode >> 3) & 7) != OP_CMPL)
3212 {
3213 if ((opcode & 1) == 0)
3214 ir.ot = OT_BYTE;
3215 else
3216 ir.ot = ir.dflag + OT_WORD;
3217
3218 switch ((opcode >> 1) & 3)
3219 {
3220 /* OP Ev, Gv */
3221 case 0:
3222 if (i386_record_modrm (&ir))
3223 return -1;
3224 if (ir.mod != 3)
3225 {
3226 if (i386_record_lea_modrm (&ir))
3227 return -1;
3228 }
3229 else
3230 {
3231 if (ir.ot == OT_BYTE)
3232 ir.rm &= 0x3;
3233 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3234 return -1;
3235 }
3236 break;
3237 /* OP Gv, Ev */
3238 case 1:
3239 if (i386_record_modrm (&ir))
3240 return -1;
3241 if (ir.ot == OT_BYTE)
3242 ir.reg &= 0x3;
3243 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3244 return -1;
3245 break;
3246 /* OP A, Iv */
3247 case 2:
3248 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3249 return -1;
3250 break;
3251 }
3252 }
3253 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3254 return -1;
3255 break;
3256
3257 /* GRP1 */
3258 case 0x80:
3259 case 0x81:
3260 case 0x82:
3261 case 0x83:
3262 if (i386_record_modrm (&ir))
3263 return -1;
3264
3265 if (ir.reg != OP_CMPL)
3266 {
3267 if ((opcode & 1) == 0)
3268 ir.ot = OT_BYTE;
3269 else
3270 ir.ot = ir.dflag + OT_WORD;
3271
3272 if (ir.mod != 3)
3273 {
3274 if (i386_record_lea_modrm (&ir))
3275 return -1;
3276 }
3277 else
3278 {
3279 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3280 return -1;
3281 }
3282 }
3283 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3284 return -1;
3285 break;
3286
3287 /* inv */
3288 case 0x40:
3289 case 0x41:
3290 case 0x42:
3291 case 0x43:
3292 case 0x44:
3293 case 0x45:
3294 case 0x46:
3295 case 0x47:
3296 /* dec */
3297 case 0x48:
3298 case 0x49:
3299 case 0x4a:
3300 case 0x4b:
3301 case 0x4c:
3302 case 0x4d:
3303 case 0x4e:
3304 case 0x4f:
3305 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
3306 return -1;
3307 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3308 return -1;
3309 break;
3310
3311 /* GRP3 */
3312 case 0xf6:
3313 case 0xf7:
3314 if ((opcode & 1) == 0)
3315 ir.ot = OT_BYTE;
3316 else
3317 ir.ot = ir.dflag + OT_WORD;
3318 if (i386_record_modrm (&ir))
3319 return -1;
3320
3321 switch (ir.reg)
3322 {
3323 /* test */
3324 case 0:
3325 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3326 return -1;
3327 break;
3328 /* not */
3329 case 2:
3330 if (ir.mod != 3)
3331 {
3332 if (i386_record_lea_modrm (&ir))
3333 return -1;
3334 }
3335 else
3336 {
3337 if (ir.ot == OT_BYTE)
3338 ir.rm &= 0x3;
3339 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3340 return -1;
3341 }
3342 break;
3343 /* neg */
3344 case 3:
3345 if (ir.mod != 3)
3346 {
3347 if (i386_record_lea_modrm (&ir))
3348 return -1;
3349 }
3350 else
3351 {
3352 if (ir.ot == OT_BYTE)
3353 ir.rm &= 0x3;
3354 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3355 return -1;
3356 }
3357 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3358 return -1;
3359 break;
3360 /* mul */
3361 case 4:
3362 /* imul */
3363 case 5:
3364 /* div */
3365 case 6:
3366 /* idiv */
3367 case 7:
3368 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3369 return -1;
3370 if (ir.ot != OT_BYTE)
3371 {
3372 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3373 return -1;
3374 }
3375 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3376 return -1;
3377 break;
3378 default:
3379 ir.addr -= 2;
3380 opcode = opcode << 8 | ir.modrm;
3381 goto no_support;
3382 break;
3383 }
3384 break;
3385
3386 /* GRP4 */
3387 case 0xfe:
3388 /* GRP5 */
3389 case 0xff:
3390 if ((opcode & 1) == 0)
3391 ir.ot = OT_BYTE;
3392 else
3393 ir.ot = ir.dflag + OT_WORD;
3394 if (i386_record_modrm (&ir))
3395 return -1;
3396 if (ir.reg >= 2 && opcode == 0xfe)
3397 {
3398 ir.addr -= 2;
3399 opcode = opcode << 8 | ir.modrm;
3400 goto no_support;
3401 }
3402
3403 switch (ir.reg)
3404 {
3405 /* inc */
3406 case 0:
3407 /* dec */
3408 case 1:
3409 if (ir.mod != 3)
3410 {
3411 if (i386_record_lea_modrm (&ir))
3412 return -1;
3413 }
3414 else
3415 {
3416 if (ir.ot == OT_BYTE)
3417 ir.rm &= 0x3;
3418 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3419 return -1;
3420 }
3421 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3422 return -1;
3423 break;
3424 /* call */
3425 case 2:
3426 /* push */
3427 case 6:
3428 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3429 return -1;
3430 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3431 (gdb_byte *) & tmpu32);
3432 if (record_arch_list_add_mem
3433 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3434 return -1;
3435 break;
3436 /* lcall */
3437 case 3:
3438 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3439 return -1;
3440 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
3441 return -1;
3442 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3443 (gdb_byte *) & tmpu32);
3444 if (record_arch_list_add_mem
3445 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
3446 return -1;
3447 break;
3448 /* jmp */
3449 case 4:
3450 /* ljmp */
3451 case 5:
3452 break;
3453 default:
3454 ir.addr -= 2;
3455 opcode = opcode << 8 | ir.modrm;
3456 goto no_support;
3457 break;
3458 }
3459 break;
3460
3461 /* test */
3462 case 0x84:
3463 case 0x85:
3464 case 0xa8:
3465 case 0xa9:
3466 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3467 return -1;
3468 break;
3469
3470 /* CWDE/CBW */
3471 case 0x98:
3472 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3473 return -1;
3474 break;
3475
3476 /* CDQ/CWD */
3477 case 0x99:
3478 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3479 return -1;
3480 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3481 return -1;
3482 break;
3483
3484 /* imul */
3485 case 0x0faf:
3486 case 0x69:
3487 case 0x6b:
3488 ir.ot = ir.dflag + OT_WORD;
3489 if (i386_record_modrm (&ir))
3490 return -1;
3491 if (ir.ot == OT_BYTE)
3492 ir.reg &= 0x3;
3493 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3494 return -1;
3495 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3496 return -1;
3497 break;
3498
3499 /* xadd */
3500 case 0x0fc0:
3501 case 0x0fc1:
3502 if ((opcode & 1) == 0)
3503 ir.ot = OT_BYTE;
3504 else
3505 ir.ot = ir.dflag + OT_WORD;
3506 if (i386_record_modrm (&ir))
3507 return -1;
3508 if (ir.mod == 3)
3509 {
3510 if (ir.ot == OT_BYTE)
3511 ir.reg &= 0x3;
3512 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3513 return -1;
3514 if (ir.ot == OT_BYTE)
3515 ir.rm &= 0x3;
3516 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3517 return -1;
3518 }
3519 else
3520 {
3521 if (i386_record_lea_modrm (&ir))
3522 return -1;
3523 if (ir.ot == OT_BYTE)
3524 ir.reg &= 0x3;
3525 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3526 return -1;
3527 }
3528 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3529 return -1;
3530 break;
3531
3532 /* cmpxchg */
3533 case 0x0fb0:
3534 case 0x0fb1:
3535 if ((opcode & 1) == 0)
3536 ir.ot = OT_BYTE;
3537 else
3538 ir.ot = ir.dflag + OT_WORD;
3539 if (i386_record_modrm (&ir))
3540 return -1;
3541 if (ir.mod == 3)
3542 {
3543 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3544 return -1;
3545 if (ir.ot == OT_BYTE)
3546 ir.reg &= 0x3;
3547 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3548 return -1;
3549 }
3550 else
3551 {
3552 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3553 return -1;
3554 if (i386_record_lea_modrm (&ir))
3555 return -1;
3556 }
3557 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3558 return -1;
3559 break;
3560
3561 /* cmpxchg8b */
3562 case 0x0fc7:
3563 if (i386_record_modrm (&ir))
3564 return -1;
3565 if (ir.mod == 3)
3566 {
3567 ir.addr -= 2;
3568 opcode = opcode << 8 | ir.modrm;
3569 goto no_support;
3570 }
3571 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3572 return -1;
3573 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
3574 return -1;
3575 if (i386_record_lea_modrm (&ir))
3576 return -1;
3577 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3578 return -1;
3579 break;
3580
3581 /* push */
3582 case 0x50:
3583 case 0x51:
3584 case 0x52:
3585 case 0x53:
3586 case 0x54:
3587 case 0x55:
3588 case 0x56:
3589 case 0x57:
3590 case 0x68:
3591 case 0x6a:
3592 /* push es */
3593 case 0x06:
3594 /* push cs */
3595 case 0x0e:
3596 /* push ss */
3597 case 0x16:
3598 /* push ds */
3599 case 0x1e:
3600 /* push fs */
3601 case 0x0fa0:
3602 /* push gs */
3603 case 0x0fa8:
3604 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3605 return -1;
3606 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3607 (gdb_byte *) & tmpu32);
3608 if (record_arch_list_add_mem
3609 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3610 return -1;
3611 break;
3612
3613 /* pop */
3614 case 0x58:
3615 case 0x59:
3616 case 0x5a:
3617 case 0x5b:
3618 case 0x5c:
3619 case 0x5d:
3620 case 0x5e:
3621 case 0x5f:
3622 ir.ot = ir.dflag + OT_WORD;
3623 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3624 return -1;
3625 if (ir.ot == OT_BYTE)
3626 opcode &= 0x3;
3627 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3628 return -1;
3629 break;
3630
3631 /* pusha */
3632 case 0x60:
3633 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3634 return -1;
3635 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3636 (gdb_byte *) & tmpu32);
3637 if (record_arch_list_add_mem
3638 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4))))
3639 return -1;
3640 break;
3641
3642 /* popa */
3643 case 0x61:
3644 for (tmpu8 = I386_EAX_REGNUM; tmpu8 <= I386_EDI_REGNUM; tmpu8++)
3645 {
3646 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3647 return -1;
3648 }
3649 break;
3650
3651 /* pop */
3652 case 0x8f:
3653 ir.ot = ir.dflag + OT_WORD;
3654 if (i386_record_modrm (&ir))
3655 return -1;
3656 if (ir.mod == 3)
3657 {
3658 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3659 return -1;
3660 }
3661 else
3662 {
3663 if (i386_record_lea_modrm (&ir))
3664 return -1;
3665 }
3666 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3667 return -1;
3668 break;
3669
3670 /* enter */
3671 case 0xc8:
3672 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3673 return -1;
3674 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3675 return -1;
3676 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
3677 (gdb_byte *) & tmpu32);
3678 if (record_arch_list_add_mem
3679 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
3680 return -1;
3681 break;
3682
3683 /* leave */
3684 case 0xc9:
3685 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3686 return -1;
3687 if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
3688 return -1;
3689 break;
3690
3691 /* pop es */
3692 case 0x07:
3693 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3694 return -1;
3695 if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM))
3696 return -1;
3697 break;
3698
3699 /* pop ss */
3700 case 0x17:
3701 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3702 return -1;
3703 if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM))
3704 return -1;
3705 break;
3706
3707 /* pop ds */
3708 case 0x1f:
3709 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3710 return -1;
3711 if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM))
3712 return -1;
3713 break;
3714
3715 /* pop fs */
3716 case 0x0fa1:
3717 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3718 return -1;
3719 if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM))
3720 return -1;
3721 break;
3722
3723 /* pop gs */
3724 case 0x0fa9:
3725 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
3726 return -1;
3727 if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM))
3728 return -1;
3729 break;
3730
3731 /* mov */
3732 case 0x88:
3733 case 0x89:
3734 case 0xc6:
3735 case 0xc7:
3736 if ((opcode & 1) == 0)
3737 ir.ot = OT_BYTE;
3738 else
3739 ir.ot = ir.dflag + OT_WORD;
3740
3741 if (i386_record_modrm (&ir))
3742 return -1;
3743
3744 if (ir.mod != 3)
3745 {
3746 if (i386_record_lea_modrm (&ir))
3747 return -1;
3748 }
3749 else
3750 {
3751 if (ir.ot == OT_BYTE)
3752 ir.rm &= 0x3;
3753 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3754 return -1;
3755 }
3756 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3757 return -1;
3758 break;
3759 /* mov */
3760 case 0x8a:
3761 case 0x8b:
3762 if ((opcode & 1) == 0)
3763 ir.ot = OT_BYTE;
3764 else
3765 ir.ot = ir.dflag + OT_WORD;
3766
3767 if (i386_record_modrm (&ir))
3768 return -1;
3769
3770 if (ir.ot == OT_BYTE)
3771 ir.reg &= 0x3;
3772 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3773 return -1;
3774
3775 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3776 return -1;
3777 break;
3778
3779 /* mov seg */
3780 case 0x8e:
3781 if (i386_record_modrm (&ir))
3782 return -1;
3783
3784 switch (ir.reg)
3785 {
3786 case 0:
3787 tmpu8 = I386_ES_REGNUM;
3788 break;
3789 case 2:
3790 tmpu8 = I386_SS_REGNUM;
3791 break;
3792 case 3:
3793 tmpu8 = I386_DS_REGNUM;
3794 break;
3795 case 4:
3796 tmpu8 = I386_FS_REGNUM;
3797 break;
3798 case 5:
3799 tmpu8 = I386_GS_REGNUM;
3800 break;
3801 default:
3802 ir.addr -= 2;
3803 opcode = opcode << 8 | ir.modrm;
3804 goto no_support;
3805 break;
3806 }
3807 if (record_arch_list_add_reg (ir.regcache, tmpu8))
3808 return -1;
3809
3810 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3811 return -1;
3812 break;
3813
3814 /* mov seg */
3815 case 0x8c:
3816 if (i386_record_modrm (&ir))
3817 return -1;
3818 if (ir.reg > 5)
3819 {
3820 ir.addr -= 2;
3821 opcode = opcode << 8 | ir.modrm;
3822 goto no_support;
3823 }
3824
3825 if (ir.mod == 3)
3826 {
3827 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3828 return -1;
3829 }
3830 else
3831 {
3832 ir.ot = OT_WORD;
3833 if (i386_record_lea_modrm (&ir))
3834 return -1;
3835 }
3836
3837 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
3838 return -1;
3839 break;
3840
3841 /* movzbS */
3842 case 0x0fb6:
3843 /* movzwS */
3844 case 0x0fb7:
3845 /* movsbS */
3846 case 0x0fbe:
3847 /* movswS */
3848 case 0x0fbf:
3849 if (i386_record_modrm (&ir))
3850 return -1;
3851 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3852 return -1;
3853 break;
3854
3855 /* lea */
3856 case 0x8d:
3857 if (i386_record_modrm (&ir))
3858 return -1;
3859 if (ir.mod == 3)
3860 {
3861 ir.addr -= 2;
3862 opcode = opcode << 8 | ir.modrm;
3863 goto no_support;
3864 }
3865
3866 ir.ot = ir.dflag;
3867 if (ir.ot == OT_BYTE)
3868 ir.reg &= 0x3;
3869 if (record_arch_list_add_reg (ir.regcache, ir.reg))
3870 return -1;
3871 break;
3872
3873 /* mov EAX */
3874 case 0xa0:
3875 case 0xa1:
3876 /* xlat */
3877 case 0xd7:
3878 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3879 return -1;
3880 break;
3881
3882 /* mov EAX */
3883 case 0xa2:
3884 case 0xa3:
3885 {
3886 uint32_t addr;
3887
3888 if (ir.override)
3889 {
3890 if (record_debug)
3891 printf_unfiltered (_("Process record ignores the memory change "
3892 "of instruction at address %s because "
3893 "it can't get the value of the segment "
3894 "register.\n"),
3895 paddress (gdbarch, ir.addr));
3896 }
3897 else
3898 {
3899 if ((opcode & 1) == 0)
3900 ir.ot = OT_BYTE;
3901 else
3902 ir.ot = ir.dflag + OT_WORD;
3903 if (ir.aflag)
3904 {
3905 if (target_read_memory
3906 (ir.addr, (gdb_byte *) & addr, 4))
3907 {
3908 if (record_debug)
3909 printf_unfiltered (_("Process record: error reading "
3910 "memory at addr %s len = 4.\n"),
3911 paddress (gdbarch, ir.addr));
3912 return -1;
3913 }
3914 ir.addr += 4;
3915 }
3916 else
3917 {
3918 if (target_read_memory
3919 (ir.addr, (gdb_byte *) & tmpu16, 4))
3920 {
3921 if (record_debug)
3922 printf_unfiltered (_("Process record: error reading "
3923 "memory at addr %s len = 4.\n"),
3924 paddress (gdbarch, ir.addr));
3925 return -1;
3926 }
3927 ir.addr += 2;
3928 addr = tmpu16;
3929 }
3930 if (record_arch_list_add_mem (addr, 1 << ir.ot))
3931 return -1;
3932 }
3933 }
3934 break;
3935
3936 /* mov R, Ib */
3937 case 0xb0:
3938 case 0xb1:
3939 case 0xb2:
3940 case 0xb3:
3941 case 0xb4:
3942 case 0xb5:
3943 case 0xb6:
3944 case 0xb7:
3945 if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3))
3946 return -1;
3947 break;
3948
3949 /* mov R, Iv */
3950 case 0xb8:
3951 case 0xb9:
3952 case 0xba:
3953 case 0xbb:
3954 case 0xbc:
3955 case 0xbd:
3956 case 0xbe:
3957 case 0xbf:
3958 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3959 return -1;
3960 break;
3961
3962 /* xchg R, EAX */
3963 case 0x91:
3964 case 0x92:
3965 case 0x93:
3966 case 0x94:
3967 case 0x95:
3968 case 0x96:
3969 case 0x97:
3970 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
3971 return -1;
3972 if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
3973 return -1;
3974 break;
3975
3976 /* xchg Ev, Gv */
3977 case 0x86:
3978 case 0x87:
3979 if ((opcode & 1) == 0)
3980 ir.ot = OT_BYTE;
3981 else
3982 ir.ot = ir.dflag + OT_WORD;
3983
3984 if (i386_record_modrm (&ir))
3985 return -1;
3986
3987 if (ir.mod == 3)
3988 {
3989 if (ir.ot == OT_BYTE)
3990 ir.rm &= 0x3;
3991 if (record_arch_list_add_reg (ir.regcache, ir.rm))
3992 return -1;
3993 }
3994 else
3995 {
3996 if (i386_record_lea_modrm (&ir))
3997 return -1;
3998 }
3999
4000 if (ir.ot == OT_BYTE)
4001 ir.reg &= 0x3;
4002 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4003 return -1;
4004 break;
4005
4006 /* les Gv */
4007 case 0xc4:
4008 /* lds Gv */
4009 case 0xc5:
4010 /* lss Gv */
4011 case 0x0fb2:
4012 /* lfs Gv */
4013 case 0x0fb4:
4014 /* lgs Gv */
4015 case 0x0fb5:
4016 if (i386_record_modrm (&ir))
4017 return -1;
4018 if (ir.mod == 3)
4019 {
4020 if (opcode > 0xff)
4021 ir.addr -= 3;
4022 else
4023 ir.addr -= 2;
4024 opcode = opcode << 8 | ir.modrm;
4025 goto no_support;
4026 }
4027
4028 switch (opcode)
4029 {
4030 /* les Gv */
4031 case 0xc4:
4032 tmpu8 = I386_ES_REGNUM;
4033 break;
4034 /* lds Gv */
4035 case 0xc5:
4036 tmpu8 = I386_DS_REGNUM;
4037 break;
4038 /* lss Gv */
4039 case 0x0fb2:
4040 tmpu8 = I386_SS_REGNUM;
4041 break;
4042 /* lfs Gv */
4043 case 0x0fb4:
4044 tmpu8 = I386_FS_REGNUM;
4045 break;
4046 /* lgs Gv */
4047 case 0x0fb5:
4048 tmpu8 = I386_GS_REGNUM;
4049 break;
4050 }
4051 if (record_arch_list_add_reg (ir.regcache, tmpu8))
4052 return -1;
4053
4054 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4055 return -1;
4056 break;
4057
4058 /* shifts */
4059 case 0xc0:
4060 case 0xc1:
4061 case 0xd0:
4062 case 0xd1:
4063 case 0xd2:
4064 case 0xd3:
4065 if ((opcode & 1) == 0)
4066 ir.ot = OT_BYTE;
4067 else
4068 ir.ot = ir.dflag + OT_WORD;
4069
4070 if (i386_record_modrm (&ir))
4071 return -1;
4072
4073 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
4074 {
4075 if (i386_record_lea_modrm (&ir))
4076 return -1;
4077 }
4078 else
4079 {
4080 if (ir.ot == OT_BYTE)
4081 ir.rm &= 0x3;
4082 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4083 return -1;
4084 }
4085
4086 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4087 return -1;
4088 break;
4089
4090 case 0x0fa4:
4091 case 0x0fa5:
4092 case 0x0fac:
4093 case 0x0fad:
4094 if (i386_record_modrm (&ir))
4095 return -1;
4096 if (ir.mod == 3)
4097 {
4098 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4099 return -1;
4100 }
4101 else
4102 {
4103 if (i386_record_lea_modrm (&ir))
4104 return -1;
4105 }
4106 break;
4107
4108 /* floats */
4109 /* It just record the memory change of instrcution. */
4110 case 0xd8:
4111 case 0xd9:
4112 case 0xda:
4113 case 0xdb:
4114 case 0xdc:
4115 case 0xdd:
4116 case 0xde:
4117 case 0xdf:
4118 if (i386_record_modrm (&ir))
4119 return -1;
4120 ir.reg |= ((opcode & 7) << 3);
4121 if (ir.mod != 3)
4122 {
4123 /* memory */
4124 uint32_t addr;
4125
4126 if (i386_record_lea_modrm_addr (&ir, &addr))
4127 return -1;
4128 switch (ir.reg)
4129 {
4130 case 0x00:
4131 case 0x01:
4132 case 0x02:
4133 case 0x03:
4134 case 0x04:
4135 case 0x05:
4136 case 0x06:
4137 case 0x07:
4138 case 0x10:
4139 case 0x11:
4140 case 0x12:
4141 case 0x13:
4142 case 0x14:
4143 case 0x15:
4144 case 0x16:
4145 case 0x17:
4146 case 0x20:
4147 case 0x21:
4148 case 0x22:
4149 case 0x23:
4150 case 0x24:
4151 case 0x25:
4152 case 0x26:
4153 case 0x27:
4154 case 0x30:
4155 case 0x31:
4156 case 0x32:
4157 case 0x33:
4158 case 0x34:
4159 case 0x35:
4160 case 0x36:
4161 case 0x37:
4162 break;
4163 case 0x08:
4164 case 0x0a:
4165 case 0x0b:
4166 case 0x18:
4167 case 0x19:
4168 case 0x1a:
4169 case 0x1b:
4170 case 0x28:
4171 case 0x29:
4172 case 0x2a:
4173 case 0x2b:
4174 case 0x38:
4175 case 0x39:
4176 case 0x3a:
4177 case 0x3b:
4178 switch (ir.reg & 7)
4179 {
4180 case 0:
4181 break;
4182 case 1:
4183 switch (ir.reg >> 4)
4184 {
4185 case 0:
4186 if (record_arch_list_add_mem (addr, 4))
4187 return -1;
4188 break;
4189 case 2:
4190 if (record_arch_list_add_mem (addr, 8))
4191 return -1;
4192 break;
4193 case 3:
4194 default:
4195 if (record_arch_list_add_mem (addr, 2))
4196 return -1;
4197 break;
4198 }
4199 break;
4200 default:
4201 switch (ir.reg >> 4)
4202 {
4203 case 0:
4204 case 1:
4205 if (record_arch_list_add_mem (addr, 4))
4206 return -1;
4207 break;
4208 case 2:
4209 if (record_arch_list_add_mem (addr, 8))
4210 return -1;
4211 break;
4212 case 3:
4213 default:
4214 if (record_arch_list_add_mem (addr, 2))
4215 return -1;
4216 break;
4217 }
4218 break;
4219 }
4220 break;
4221 case 0x0c:
4222 case 0x0d:
4223 case 0x1d:
4224 case 0x2c:
4225 case 0x3c:
4226 case 0x3d:
4227 break;
4228 case 0x0e:
4229 if (ir.dflag)
4230 {
4231 if (record_arch_list_add_mem (addr, 28))
4232 return -1;
4233 }
4234 else
4235 {
4236 if (record_arch_list_add_mem (addr, 14))
4237 return -1;
4238 }
4239 break;
4240 case 0x0f:
4241 case 0x2f:
4242 if (record_arch_list_add_mem (addr, 2))
4243 return -1;
4244 break;
4245 case 0x1f:
4246 case 0x3e:
4247 if (record_arch_list_add_mem (addr, 10))
4248 return -1;
4249 break;
4250 case 0x2e:
4251 if (ir.dflag)
4252 {
4253 if (record_arch_list_add_mem (addr, 28))
4254 return -1;
4255 addr += 28;
4256 }
4257 else
4258 {
4259 if (record_arch_list_add_mem (addr, 14))
4260 return -1;
4261 addr += 14;
4262 }
4263 if (record_arch_list_add_mem (addr, 80))
4264 return -1;
4265 break;
4266 case 0x3f:
4267 if (record_arch_list_add_mem (addr, 8))
4268 return -1;
4269 break;
4270 default:
4271 ir.addr -= 2;
4272 opcode = opcode << 8 | ir.modrm;
4273 goto no_support;
4274 break;
4275 }
4276 }
4277 break;
4278
4279 /* string ops */
4280 /* movsS */
4281 case 0xa4:
4282 case 0xa5:
4283 /* stosS */
4284 case 0xaa:
4285 case 0xab:
4286 /* insS */
4287 case 0x6c:
4288 case 0x6d:
4289 {
4290 uint32_t addr;
4291
4292 if ((opcode & 1) == 0)
4293 ir.ot = OT_BYTE;
4294 else
4295 ir.ot = ir.dflag + OT_WORD;
4296 if (opcode == 0xa4 || opcode == 0xa5)
4297 {
4298 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4299 return -1;
4300 }
4301 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4302 return -1;
4303
4304 regcache_raw_read (ir.regcache, I386_EDI_REGNUM,
4305 (gdb_byte *) & addr);
4306 if (!ir.aflag)
4307 {
4308 addr &= 0xffff;
4309 /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */
4310 if (record_debug)
4311 printf_unfiltered (_("Process record ignores the memory change "
4312 "of instruction at address %s because "
4313 "it can't get the value of the segment "
4314 "register.\n"),
4315 paddress (gdbarch, ir.addr));
4316 }
4317
4318 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4319 {
4320 uint32_t count;
4321
4322 regcache_raw_read (ir.regcache, I386_ECX_REGNUM,
4323 (gdb_byte *) & count);
4324 if (!ir.aflag)
4325 count &= 0xffff;
4326
4327 regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM,
4328 (gdb_byte *) & tmpu32);
4329 if ((tmpu32 >> 10) & 0x1)
4330 addr -= (count - 1) * (1 << ir.ot);
4331
4332 if (ir.aflag)
4333 {
4334 if (record_arch_list_add_mem (addr, count * (1 << ir.ot)))
4335 return -1;
4336 }
4337
4338 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4339 return -1;
4340 }
4341 else
4342 {
4343 if (ir.aflag)
4344 {
4345 if (record_arch_list_add_mem (addr, 1 << ir.ot))
4346 return -1;
4347 }
4348 }
4349 }
4350 break;
4351
4352 /* lodsS */
4353 case 0xac:
4354 case 0xad:
4355 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4356 return -1;
4357 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4358 return -1;
4359 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4360 {
4361 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4362 return -1;
4363 }
4364 break;
4365
4366 /* outsS */
4367 case 0x6e:
4368 case 0x6f:
4369 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4370 return -1;
4371 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4372 {
4373 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4374 return -1;
4375 }
4376 break;
4377
4378 /* scasS */
4379 case 0xae:
4380 case 0xaf:
4381 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4382 return -1;
4383 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4384 {
4385 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4386 return -1;
4387 }
4388 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4389 return -1;
4390 break;
4391
4392 /* cmpsS */
4393 case 0xa6:
4394 case 0xa7:
4395 if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
4396 return -1;
4397 if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
4398 return -1;
4399 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
4400 {
4401 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4402 return -1;
4403 }
4404 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4405 return -1;
4406 break;
4407
4408 /* port I/O */
4409 case 0xe4:
4410 case 0xe5:
4411 case 0xec:
4412 case 0xed:
4413 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4414 return -1;
4415 break;
4416
4417 case 0xe6:
4418 case 0xe7:
4419 case 0xee:
4420 case 0xef:
4421 break;
4422
4423 /* control */
4424 /* ret im */
4425 case 0xc2:
4426 /* ret */
4427 case 0xc3:
4428 /* lret im */
4429 case 0xca:
4430 /* lret */
4431 case 0xcb:
4432 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4433 return -1;
4434 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4435 return -1;
4436 break;
4437
4438 /* iret */
4439 case 0xcf:
4440 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4441 return -1;
4442 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4443 return -1;
4444 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4445 return -1;
4446 break;
4447
4448 /* call im */
4449 case 0xe8:
4450 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4451 return -1;
4452 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4453 (gdb_byte *) & tmpu32);
4454 if (record_arch_list_add_mem
4455 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4456 return -1;
4457 break;
4458
4459 /* lcall im */
4460 case 0x9a:
4461 if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
4462 return -1;
4463 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4464 return -1;
4465 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4466 (gdb_byte *) & tmpu32);
4467 if (record_arch_list_add_mem
4468 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
4469 return -1;
4470 break;
4471
4472 /* jmp im */
4473 case 0xe9:
4474 /* ljmp im */
4475 case 0xea:
4476 /* jmp Jb */
4477 case 0xeb:
4478 /* jcc Jb */
4479 case 0x70:
4480 case 0x71:
4481 case 0x72:
4482 case 0x73:
4483 case 0x74:
4484 case 0x75:
4485 case 0x76:
4486 case 0x77:
4487 case 0x78:
4488 case 0x79:
4489 case 0x7a:
4490 case 0x7b:
4491 case 0x7c:
4492 case 0x7d:
4493 case 0x7e:
4494 case 0x7f:
4495 /* jcc Jv */
4496 case 0x0f80:
4497 case 0x0f81:
4498 case 0x0f82:
4499 case 0x0f83:
4500 case 0x0f84:
4501 case 0x0f85:
4502 case 0x0f86:
4503 case 0x0f87:
4504 case 0x0f88:
4505 case 0x0f89:
4506 case 0x0f8a:
4507 case 0x0f8b:
4508 case 0x0f8c:
4509 case 0x0f8d:
4510 case 0x0f8e:
4511 case 0x0f8f:
4512 break;
4513
4514 /* setcc Gv */
4515 case 0x0f90:
4516 case 0x0f91:
4517 case 0x0f92:
4518 case 0x0f93:
4519 case 0x0f94:
4520 case 0x0f95:
4521 case 0x0f96:
4522 case 0x0f97:
4523 case 0x0f98:
4524 case 0x0f99:
4525 case 0x0f9a:
4526 case 0x0f9b:
4527 case 0x0f9c:
4528 case 0x0f9d:
4529 case 0x0f9e:
4530 case 0x0f9f:
4531 ir.ot = OT_BYTE;
4532 if (i386_record_modrm (&ir))
4533 return -1;
4534 if (ir.mod == 3)
4535 {
4536 if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3))
4537 return -1;
4538 }
4539 else
4540 {
4541 if (i386_record_lea_modrm (&ir))
4542 return -1;
4543 }
4544 break;
4545
4546 /* cmov Gv, Ev */
4547 case 0x0f40:
4548 case 0x0f41:
4549 case 0x0f42:
4550 case 0x0f43:
4551 case 0x0f44:
4552 case 0x0f45:
4553 case 0x0f46:
4554 case 0x0f47:
4555 case 0x0f48:
4556 case 0x0f49:
4557 case 0x0f4a:
4558 case 0x0f4b:
4559 case 0x0f4c:
4560 case 0x0f4d:
4561 case 0x0f4e:
4562 case 0x0f4f:
4563 if (i386_record_modrm (&ir))
4564 return -1;
4565 if (ir.dflag == OT_BYTE)
4566 ir.reg &= 0x3;
4567 if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3))
4568 return -1;
4569 break;
4570
4571 /* flags */
4572 /* pushf */
4573 case 0x9c:
4574 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4575 return -1;
4576 regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
4577 (gdb_byte *) & tmpu32);
4578 if (record_arch_list_add_mem
4579 ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
4580 return -1;
4581 break;
4582
4583 /* popf */
4584 case 0x9d:
4585 if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
4586 return -1;
4587 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4588 return -1;
4589 break;
4590
4591 /* sahf */
4592 case 0x9e:
4593 /* cmc */
4594 case 0xf5:
4595 /* clc */
4596 case 0xf8:
4597 /* stc */
4598 case 0xf9:
4599 /* cld */
4600 case 0xfc:
4601 /* std */
4602 case 0xfd:
4603 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4604 return -1;
4605 break;
4606
4607 /* lahf */
4608 case 0x9f:
4609 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4610 return -1;
4611 break;
4612
4613 /* bit operations */
4614 /* bt/bts/btr/btc Gv, im */
4615 case 0x0fba:
4616 /* bts */
4617 case 0x0fab:
4618 /* btr */
4619 case 0x0fb3:
4620 /* btc */
4621 case 0x0fbb:
4622 ir.ot = ir.dflag + OT_WORD;
4623 if (i386_record_modrm (&ir))
4624 return -1;
4625 if (ir.reg < 4)
4626 {
4627 ir.addr -= 3;
4628 opcode = opcode << 8 | ir.modrm;
4629 goto no_support;
4630 }
4631 ir.reg -= 4;
4632 if (ir.reg != 0)
4633 {
4634 if (ir.mod != 3)
4635 {
4636 if (i386_record_lea_modrm (&ir))
4637 return -1;
4638 }
4639 else
4640 {
4641 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4642 return -1;
4643 }
4644 }
4645 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4646 return -1;
4647 break;
4648
4649 /* bt Gv, Ev */
4650 case 0x0fa3:
4651 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4652 return -1;
4653 break;
4654
4655 /* bsf */
4656 case 0x0fbc:
4657 /* bsr */
4658 case 0x0fbd:
4659 if (record_arch_list_add_reg (ir.regcache, ir.reg))
4660 return -1;
4661 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4662 return -1;
4663 break;
4664
4665 /* bcd */
4666 /* daa */
4667 case 0x27:
4668 /* das */
4669 case 0x2f:
4670 /* aaa */
4671 case 0x37:
4672 /* aas */
4673 case 0x3f:
4674 /* aam */
4675 case 0xd4:
4676 /* aad */
4677 case 0xd5:
4678 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4679 return -1;
4680 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4681 return -1;
4682 break;
4683
4684 /* misc */
4685 /* nop */
4686 case 0x90:
4687 if (prefixes & PREFIX_LOCK)
4688 {
4689 ir.addr -= 1;
4690 goto no_support;
4691 }
4692 break;
4693
4694 /* fwait */
4695 /* XXX */
4696 case 0x9b:
4697 printf_unfiltered (_("Process record doesn't support instruction "
4698 "fwait.\n"));
4699 ir.addr -= 1;
4700 goto no_support;
4701 break;
4702
4703 /* int3 */
4704 /* XXX */
4705 case 0xcc:
4706 printf_unfiltered (_("Process record doesn't support instruction "
4707 "int3.\n"));
4708 ir.addr -= 1;
4709 goto no_support;
4710 break;
4711
4712 /* int */
4713 /* XXX */
4714 case 0xcd:
4715 {
4716 int ret;
4717 if (target_read_memory (ir.addr, &tmpu8, 1))
4718 {
4719 if (record_debug)
4720 printf_unfiltered (_("Process record: error reading memory "
4721 "at addr %s len = 1.\n"),
4722 paddress (gdbarch, ir.addr));
4723 return -1;
4724 }
4725 ir.addr++;
4726 if (tmpu8 != 0x80
4727 || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL)
4728 {
4729 printf_unfiltered (_("Process record doesn't support "
4730 "instruction int 0x%02x.\n"),
4731 tmpu8);
4732 ir.addr -= 2;
4733 goto no_support;
4734 }
4735 ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache);
4736 if (ret)
4737 return ret;
4738 }
4739 break;
4740
4741 /* into */
4742 /* XXX */
4743 case 0xce:
4744 printf_unfiltered (_("Process record doesn't support "
4745 "instruction into.\n"));
4746 ir.addr -= 1;
4747 goto no_support;
4748 break;
4749
4750 /* cli */
4751 case 0xfa:
4752 /* sti */
4753 case 0xfb:
4754 break;
4755
4756 /* bound */
4757 case 0x62:
4758 printf_unfiltered (_("Process record doesn't support "
4759 "instruction bound.\n"));
4760 ir.addr -= 1;
4761 goto no_support;
4762 break;
4763
4764 /* bswap reg */
4765 case 0x0fc8:
4766 case 0x0fc9:
4767 case 0x0fca:
4768 case 0x0fcb:
4769 case 0x0fcc:
4770 case 0x0fcd:
4771 case 0x0fce:
4772 case 0x0fcf:
4773 if (record_arch_list_add_reg (ir.regcache, opcode & 7))
4774 return -1;
4775 break;
4776
4777 /* salc */
4778 case 0xd6:
4779 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4780 return -1;
4781 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4782 return -1;
4783 break;
4784
4785 /* loopnz */
4786 case 0xe0:
4787 /* loopz */
4788 case 0xe1:
4789 /* loop */
4790 case 0xe2:
4791 /* jecxz */
4792 case 0xe3:
4793 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4794 return -1;
4795 break;
4796
4797 /* wrmsr */
4798 case 0x0f30:
4799 printf_unfiltered (_("Process record doesn't support "
4800 "instruction wrmsr.\n"));
4801 ir.addr -= 2;
4802 goto no_support;
4803 break;
4804
4805 /* rdmsr */
4806 case 0x0f32:
4807 printf_unfiltered (_("Process record doesn't support "
4808 "instruction rdmsr.\n"));
4809 ir.addr -= 2;
4810 goto no_support;
4811 break;
4812
4813 /* rdtsc */
4814 case 0x0f31:
4815 printf_unfiltered (_("Process record doesn't support "
4816 "instruction rdtsc.\n"));
4817 ir.addr -= 2;
4818 goto no_support;
4819 break;
4820
4821 /* sysenter */
4822 case 0x0f34:
4823 {
4824 int ret;
4825 if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL)
4826 {
4827 printf_unfiltered (_("Process record doesn't support "
4828 "instruction sysenter.\n"));
4829 ir.addr -= 2;
4830 goto no_support;
4831 }
4832 ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache);
4833 if (ret)
4834 return ret;
4835 }
4836 break;
4837
4838 /* sysexit */
4839 case 0x0f35:
4840 printf_unfiltered (_("Process record doesn't support "
4841 "instruction sysexit.\n"));
4842 ir.addr -= 2;
4843 goto no_support;
4844 break;
4845
4846 /* cpuid */
4847 case 0x0fa2:
4848 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
4849 return -1;
4850 if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
4851 return -1;
4852 if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
4853 return -1;
4854 if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM))
4855 return -1;
4856 break;
4857
4858 /* hlt */
4859 case 0xf4:
4860 printf_unfiltered (_("Process record doesn't support "
4861 "instruction hlt.\n"));
4862 ir.addr -= 1;
4863 goto no_support;
4864 break;
4865
4866 case 0x0f00:
4867 if (i386_record_modrm (&ir))
4868 return -1;
4869 switch (ir.reg)
4870 {
4871 /* sldt */
4872 case 0:
4873 /* str */
4874 case 1:
4875 if (ir.mod == 3)
4876 {
4877 if (record_arch_list_add_reg (ir.regcache, ir.rm))
4878 return -1;
4879 }
4880 else
4881 {
4882 ir.ot = OT_WORD;
4883 if (i386_record_lea_modrm (&ir))
4884 return -1;
4885 }
4886 break;
4887 /* lldt */
4888 case 2:
4889 /* ltr */
4890 case 3:
4891 break;
4892 /* verr */
4893 case 4:
4894 /* verw */
4895 case 5:
4896 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4897 return -1;
4898 break;
4899 default:
4900 ir.addr -= 3;
4901 opcode = opcode << 8 | ir.modrm;
4902 goto no_support;
4903 break;
4904 }
4905 break;
4906
4907 case 0x0f01:
4908 if (i386_record_modrm (&ir))
4909 return -1;
4910 switch (ir.reg)
4911 {
4912 /* sgdt */
4913 case 0:
4914 {
4915 uint32_t addr;
4916
4917 if (ir.mod == 3)
4918 {
4919 ir.addr -= 3;
4920 opcode = opcode << 8 | ir.modrm;
4921 goto no_support;
4922 }
4923
4924 if (ir.override)
4925 {
4926 if (record_debug)
4927 printf_unfiltered (_("Process record ignores the memory "
4928 "change of instruction at "
4929 "address %s because it can't get "
4930 "the value of the segment "
4931 "register.\n"),
4932 paddress (gdbarch, ir.addr));
4933 }
4934 else
4935 {
4936 if (i386_record_lea_modrm_addr (&ir, &addr))
4937 return -1;
4938 if (record_arch_list_add_mem (addr, 2))
4939 return -1;
4940 addr += 2;
4941 if (record_arch_list_add_mem (addr, 4))
4942 return -1;
4943 }
4944 }
4945 break;
4946 case 1:
4947 if (ir.mod == 3)
4948 {
4949 switch (ir.rm)
4950 {
4951 /* monitor */
4952 case 0:
4953 break;
4954 /* mwait */
4955 case 1:
4956 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
4957 return -1;
4958 break;
4959 default:
4960 ir.addr -= 3;
4961 opcode = opcode << 8 | ir.modrm;
4962 goto no_support;
4963 break;
4964 }
4965 }
4966 else
4967 {
4968 /* sidt */
4969 if (ir.override)
4970 {
4971 if (record_debug)
4972 printf_unfiltered (_("Process record ignores the memory "
4973 "change of instruction at "
4974 "address %s because it can't get "
4975 "the value of the segment "
4976 "register.\n"),
4977 paddress (gdbarch, ir.addr));
4978 }
4979 else
4980 {
4981 uint32_t addr;
4982
4983 if (i386_record_lea_modrm_addr (&ir, &addr))
4984 return -1;
4985 if (record_arch_list_add_mem (addr, 2))
4986 return -1;
4987 addr += 2;
4988 if (record_arch_list_add_mem (addr, 4))
4989 return -1;
4990 }
4991 }
4992 break;
4993 /* lgdt */
4994 case 2:
4995 /* lidt */
4996 case 3:
4997 /* invlpg */
4998 case 7:
4999 default:
5000 if (ir.mod == 3)
5001 {
5002 ir.addr -= 3;
5003 opcode = opcode << 8 | ir.modrm;
5004 goto no_support;
5005 }
5006 break;
5007 /* smsw */
5008 case 4:
5009 if (ir.mod == 3)
5010 {
5011 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5012 return -1;
5013 }
5014 else
5015 {
5016 ir.ot = OT_WORD;
5017 if (i386_record_lea_modrm (&ir))
5018 return -1;
5019 }
5020 break;
5021 /* lmsw */
5022 case 6:
5023 break;
5024 }
5025 break;
5026
5027 /* invd */
5028 case 0x0f08:
5029 /* wbinvd */
5030 case 0x0f09:
5031 break;
5032
5033 /* arpl */
5034 case 0x63:
5035 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
5036 if (i386_record_modrm (&ir))
5037 return -1;
5038 if (ir.mod != 3)
5039 {
5040 if (i386_record_lea_modrm (&ir))
5041 return -1;
5042 }
5043 else
5044 {
5045 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5046 return -1;
5047 }
5048 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
5049 return -1;
5050 break;
5051
5052 /* lar */
5053 case 0x0f02:
5054 /* lsl */
5055 case 0x0f03:
5056 if (i386_record_modrm (&ir))
5057 return -1;
5058 if (record_arch_list_add_reg (ir.regcache, ir.reg))
5059 return -1;
5060 if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
5061 return -1;
5062 break;
5063
5064 case 0x0f18:
5065 break;
5066
5067 /* nop (multi byte) */
5068 case 0x0f19:
5069 case 0x0f1a:
5070 case 0x0f1b:
5071 case 0x0f1c:
5072 case 0x0f1d:
5073 case 0x0f1e:
5074 case 0x0f1f:
5075 break;
5076
5077 /* mov reg, crN */
5078 case 0x0f20:
5079 /* mov crN, reg */
5080 case 0x0f22:
5081 if (i386_record_modrm (&ir))
5082 return -1;
5083 if ((ir.modrm & 0xc0) != 0xc0)
5084 {
5085 ir.addr -= 2;
5086 opcode = opcode << 8 | ir.modrm;
5087 goto no_support;
5088 }
5089 switch (ir.reg)
5090 {
5091 case 0:
5092 case 2:
5093 case 3:
5094 case 4:
5095 case 8:
5096 if (opcode & 2)
5097 {
5098 }
5099 else
5100 {
5101 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5102 return -1;
5103 }
5104 break;
5105 default:
5106 ir.addr -= 2;
5107 opcode = opcode << 8 | ir.modrm;
5108 goto no_support;
5109 break;
5110 }
5111 break;
5112
5113 /* mov reg, drN */
5114 case 0x0f21:
5115 /* mov drN, reg */
5116 case 0x0f23:
5117 if (i386_record_modrm (&ir))
5118 return -1;
5119 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
5120 || ir.reg == 5 || ir.reg >= 8)
5121 {
5122 ir.addr -= 2;
5123 opcode = opcode << 8 | ir.modrm;
5124 goto no_support;
5125 }
5126 if (opcode & 2)
5127 {
5128 }
5129 else
5130 {
5131 if (record_arch_list_add_reg (ir.regcache, ir.rm))
5132 return -1;
5133 }
5134 break;
5135
5136 /* clts */
5137 case 0x0f06:
5138 break;
5139
5140 /* MMX/SSE/SSE2/PNI support */
5141 /* XXX */
5142
5143 default:
5144 if (opcode > 0xff)
5145 ir.addr -= 2;
5146 else
5147 ir.addr -= 1;
5148 goto no_support;
5149 break;
5150 }
5151
5152 /* In the future, Maybe still need to deal with need_dasm */
5153 if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM))
5154 return -1;
5155 if (record_arch_list_add_end ())
5156 return -1;
5157
5158 return 0;
5159
5160 no_support:
5161 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5162 "at address %s.\n"),
5163 (unsigned int) (opcode), paddress (gdbarch, ir.addr));
5164 return -1;
5165 }
5166
5167 \f
5168 static struct gdbarch *
5169 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5170 {
5171 struct gdbarch_tdep *tdep;
5172 struct gdbarch *gdbarch;
5173
5174 /* If there is already a candidate, use it. */
5175 arches = gdbarch_list_lookup_by_info (arches, &info);
5176 if (arches != NULL)
5177 return arches->gdbarch;
5178
5179 /* Allocate space for the new architecture. */
5180 tdep = XCALLOC (1, struct gdbarch_tdep);
5181 gdbarch = gdbarch_alloc (&info, tdep);
5182
5183 /* General-purpose registers. */
5184 tdep->gregset = NULL;
5185 tdep->gregset_reg_offset = NULL;
5186 tdep->gregset_num_regs = I386_NUM_GREGS;
5187 tdep->sizeof_gregset = 0;
5188
5189 /* Floating-point registers. */
5190 tdep->fpregset = NULL;
5191 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
5192
5193 /* The default settings include the FPU registers, the MMX registers
5194 and the SSE registers. This can be overridden for a specific ABI
5195 by adjusting the members `st0_regnum', `mm0_regnum' and
5196 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5197 will show up in the output of "info all-registers". Ideally we
5198 should try to autodetect whether they are available, such that we
5199 can prevent "info all-registers" from displaying registers that
5200 aren't available.
5201
5202 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5203 [the SSE registers] always (even when they don't exist) or never
5204 showing them to the user (even when they do exist), I prefer the
5205 former over the latter. */
5206
5207 tdep->st0_regnum = I386_ST0_REGNUM;
5208
5209 /* The MMX registers are implemented as pseudo-registers. Put off
5210 calculating the register number for %mm0 until we know the number
5211 of raw registers. */
5212 tdep->mm0_regnum = 0;
5213
5214 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5215 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
5216
5217 tdep->jb_pc_offset = -1;
5218 tdep->struct_return = pcc_struct_return;
5219 tdep->sigtramp_start = 0;
5220 tdep->sigtramp_end = 0;
5221 tdep->sigtramp_p = i386_sigtramp_p;
5222 tdep->sigcontext_addr = NULL;
5223 tdep->sc_reg_offset = NULL;
5224 tdep->sc_pc_offset = -1;
5225 tdep->sc_sp_offset = -1;
5226
5227 /* The format used for `long double' on almost all i386 targets is
5228 the i387 extended floating-point format. In fact, of all targets
5229 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5230 on having a `long double' that's not `long' at all. */
5231 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
5232
5233 /* Although the i387 extended floating-point has only 80 significant
5234 bits, a `long double' actually takes up 96, probably to enforce
5235 alignment. */
5236 set_gdbarch_long_double_bit (gdbarch, 96);
5237
5238 /* The default ABI includes general-purpose registers,
5239 floating-point registers, and the SSE registers. */
5240 set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS);
5241 set_gdbarch_register_name (gdbarch, i386_register_name);
5242 set_gdbarch_register_type (gdbarch, i386_register_type);
5243
5244 /* Register numbers of various important registers. */
5245 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
5246 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
5247 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
5248 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
5249
5250 /* NOTE: kettenis/20040418: GCC does have two possible register
5251 numbering schemes on the i386: dbx and SVR4. These schemes
5252 differ in how they number %ebp, %esp, %eflags, and the
5253 floating-point registers, and are implemented by the arrays
5254 dbx_register_map[] and svr4_dbx_register_map in
5255 gcc/config/i386.c. GCC also defines a third numbering scheme in
5256 gcc/config/i386.c, which it designates as the "default" register
5257 map used in 64bit mode. This last register numbering scheme is
5258 implemented in dbx64_register_map, and is used for AMD64; see
5259 amd64-tdep.c.
5260
5261 Currently, each GCC i386 target always uses the same register
5262 numbering scheme across all its supported debugging formats
5263 i.e. SDB (COFF), stabs and DWARF 2. This is because
5264 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5265 DBX_REGISTER_NUMBER macro which is defined by each target's
5266 respective config header in a manner independent of the requested
5267 output debugging format.
5268
5269 This does not match the arrangement below, which presumes that
5270 the SDB and stabs numbering schemes differ from the DWARF and
5271 DWARF 2 ones. The reason for this arrangement is that it is
5272 likely to get the numbering scheme for the target's
5273 default/native debug format right. For targets where GCC is the
5274 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5275 targets where the native toolchain uses a different numbering
5276 scheme for a particular debug format (stabs-in-ELF on Solaris)
5277 the defaults below will have to be overridden, like
5278 i386_elf_init_abi() does. */
5279
5280 /* Use the dbx register numbering scheme for stabs and COFF. */
5281 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5282 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
5283
5284 /* Use the SVR4 register numbering scheme for DWARF 2. */
5285 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
5286
5287 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5288 be in use on any of the supported i386 targets. */
5289
5290 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
5291
5292 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
5293
5294 /* Call dummy code. */
5295 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
5296
5297 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
5298 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
5299 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
5300
5301 set_gdbarch_return_value (gdbarch, i386_return_value);
5302
5303 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
5304
5305 /* Stack grows downward. */
5306 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5307
5308 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
5309 set_gdbarch_decr_pc_after_break (gdbarch, 1);
5310 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
5311
5312 set_gdbarch_frame_args_skip (gdbarch, 8);
5313
5314 /* Wire in the MMX registers. */
5315 set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs);
5316 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
5317 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
5318
5319 set_gdbarch_print_insn (gdbarch, i386_print_insn);
5320
5321 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
5322
5323 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
5324
5325 /* Add the i386 register groups. */
5326 i386_add_reggroups (gdbarch);
5327 set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p);
5328
5329 /* Helper for function argument information. */
5330 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
5331
5332 /* Hook in the DWARF CFI frame unwinder. */
5333 dwarf2_append_unwinders (gdbarch);
5334
5335 frame_base_set_default (gdbarch, &i386_frame_base);
5336
5337 /* Hook in ABI-specific overrides, if they have been registered. */
5338 gdbarch_init_osabi (info, gdbarch);
5339
5340 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
5341 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
5342
5343 /* If we have a register mapping, enable the generic core file
5344 support, unless it has already been enabled. */
5345 if (tdep->gregset_reg_offset
5346 && !gdbarch_regset_from_core_section_p (gdbarch))
5347 set_gdbarch_regset_from_core_section (gdbarch,
5348 i386_regset_from_core_section);
5349
5350 /* Unless support for MMX has been disabled, make %mm0 the first
5351 pseudo-register. */
5352 if (tdep->mm0_regnum == 0)
5353 tdep->mm0_regnum = gdbarch_num_regs (gdbarch);
5354
5355 set_gdbarch_skip_permanent_breakpoint (gdbarch,
5356 i386_skip_permanent_breakpoint);
5357
5358 return gdbarch;
5359 }
5360
5361 static enum gdb_osabi
5362 i386_coff_osabi_sniffer (bfd *abfd)
5363 {
5364 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
5365 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
5366 return GDB_OSABI_GO32;
5367
5368 return GDB_OSABI_UNKNOWN;
5369 }
5370 \f
5371
5372 /* Provide a prototype to silence -Wmissing-prototypes. */
5373 void _initialize_i386_tdep (void);
5374
5375 void
5376 _initialize_i386_tdep (void)
5377 {
5378 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
5379
5380 /* Add the variable that controls the disassembly flavor. */
5381 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
5382 &disassembly_flavor, _("\
5383 Set the disassembly flavor."), _("\
5384 Show the disassembly flavor."), _("\
5385 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5386 NULL,
5387 NULL, /* FIXME: i18n: */
5388 &setlist, &showlist);
5389
5390 /* Add the variable that controls the convention for returning
5391 structs. */
5392 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
5393 &struct_convention, _("\
5394 Set the convention for returning small structs."), _("\
5395 Show the convention for returning small structs."), _("\
5396 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5397 is \"default\"."),
5398 NULL,
5399 NULL, /* FIXME: i18n: */
5400 &setlist, &showlist);
5401
5402 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
5403 i386_coff_osabi_sniffer);
5404
5405 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
5406 i386_svr4_init_abi);
5407 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
5408 i386_go32_init_abi);
5409
5410 /* Initialize the i386-specific register groups. */
5411 i386_init_reggroups ();
5412 }
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