1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
58 #include "features/i386/i386.c"
62 static const char *i386_register_names
[] =
64 "eax", "ecx", "edx", "ebx",
65 "esp", "ebp", "esi", "edi",
66 "eip", "eflags", "cs", "ss",
67 "ds", "es", "fs", "gs",
68 "st0", "st1", "st2", "st3",
69 "st4", "st5", "st6", "st7",
70 "fctrl", "fstat", "ftag", "fiseg",
71 "fioff", "foseg", "fooff", "fop",
72 "xmm0", "xmm1", "xmm2", "xmm3",
73 "xmm4", "xmm5", "xmm6", "xmm7",
77 /* Register names for MMX pseudo-registers. */
79 static const char *i386_mmx_names
[] =
81 "mm0", "mm1", "mm2", "mm3",
82 "mm4", "mm5", "mm6", "mm7"
85 /* Register names for byte pseudo-registers. */
87 static const char *i386_byte_names
[] =
89 "al", "cl", "dl", "bl",
90 "ah", "ch", "dh", "bh"
93 /* Register names for word pseudo-registers. */
95 static const char *i386_word_names
[] =
97 "ax", "cx", "dx", "bx",
104 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
107 int mm0_regnum
= tdep
->mm0_regnum
;
112 regnum
-= mm0_regnum
;
113 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
119 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
123 regnum
-= tdep
->al_regnum
;
124 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
130 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
132 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
134 regnum
-= tdep
->ax_regnum
;
135 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
138 /* Dword register? */
141 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
144 int eax_regnum
= tdep
->eax_regnum
;
149 regnum
-= eax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
156 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 if (I387_NUM_XMM_REGS (tdep
) == 0)
163 return (I387_XMM0_REGNUM (tdep
) <= regnum
164 && regnum
< I387_MXCSR_REGNUM (tdep
));
168 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 if (I387_NUM_XMM_REGS (tdep
) == 0)
175 return (regnum
== I387_MXCSR_REGNUM (tdep
));
181 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
185 if (I387_ST0_REGNUM (tdep
) < 0)
188 return (I387_ST0_REGNUM (tdep
) <= regnum
189 && regnum
< I387_FCTRL_REGNUM (tdep
));
193 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 if (I387_ST0_REGNUM (tdep
) < 0)
200 return (I387_FCTRL_REGNUM (tdep
) <= regnum
201 && regnum
< I387_XMM0_REGNUM (tdep
));
204 /* Return the name of register REGNUM. */
207 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 if (i386_mmx_regnum_p (gdbarch
, regnum
))
211 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
212 else if (i386_byte_regnum_p (gdbarch
, regnum
))
213 return i386_byte_names
[regnum
- tdep
->al_regnum
];
214 else if (i386_word_regnum_p (gdbarch
, regnum
))
215 return i386_word_names
[regnum
- tdep
->ax_regnum
];
217 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
220 /* Convert a dbx register number REG to the appropriate register
221 number used by GDB. */
224 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
228 /* This implements what GCC calls the "default" register map
229 (dbx_register_map[]). */
231 if (reg
>= 0 && reg
<= 7)
233 /* General-purpose registers. The debug info calls %ebp
234 register 4, and %esp register 5. */
241 else if (reg
>= 12 && reg
<= 19)
243 /* Floating-point registers. */
244 return reg
- 12 + I387_ST0_REGNUM (tdep
);
246 else if (reg
>= 21 && reg
<= 28)
249 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
251 else if (reg
>= 29 && reg
<= 36)
254 return reg
- 29 + I387_MM0_REGNUM (tdep
);
257 /* This will hopefully provoke a warning. */
258 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
261 /* Convert SVR4 register number REG to the appropriate register number
265 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
269 /* This implements the GCC register map that tries to be compatible
270 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
272 /* The SVR4 register numbering includes %eip and %eflags, and
273 numbers the floating point registers differently. */
274 if (reg
>= 0 && reg
<= 9)
276 /* General-purpose registers. */
279 else if (reg
>= 11 && reg
<= 18)
281 /* Floating-point registers. */
282 return reg
- 11 + I387_ST0_REGNUM (tdep
);
284 else if (reg
>= 21 && reg
<= 36)
286 /* The SSE and MMX registers have the same numbers as with dbx. */
287 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
292 case 37: return I387_FCTRL_REGNUM (tdep
);
293 case 38: return I387_FSTAT_REGNUM (tdep
);
294 case 39: return I387_MXCSR_REGNUM (tdep
);
295 case 40: return I386_ES_REGNUM
;
296 case 41: return I386_CS_REGNUM
;
297 case 42: return I386_SS_REGNUM
;
298 case 43: return I386_DS_REGNUM
;
299 case 44: return I386_FS_REGNUM
;
300 case 45: return I386_GS_REGNUM
;
303 /* This will hopefully provoke a warning. */
304 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
309 /* This is the variable that is set with "set disassembly-flavor", and
310 its legitimate values. */
311 static const char att_flavor
[] = "att";
312 static const char intel_flavor
[] = "intel";
313 static const char *valid_flavors
[] =
319 static const char *disassembly_flavor
= att_flavor
;
322 /* Use the program counter to determine the contents and size of a
323 breakpoint instruction. Return a pointer to a string of bytes that
324 encode a breakpoint instruction, store the length of the string in
325 *LEN and optionally adjust *PC to point to the correct memory
326 location for inserting the breakpoint.
328 On the i386 we have a single breakpoint that fits in a single byte
329 and can be inserted anywhere.
331 This function is 64-bit safe. */
333 static const gdb_byte
*
334 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
336 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
338 *len
= sizeof (break_insn
);
342 /* Displaced instruction handling. */
344 /* Skip the legacy instruction prefixes in INSN.
345 Not all prefixes are valid for any particular insn
346 but we needn't care, the insn will fault if it's invalid.
347 The result is a pointer to the first opcode byte,
348 or NULL if we run off the end of the buffer. */
351 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
353 gdb_byte
*end
= insn
+ max_len
;
359 case DATA_PREFIX_OPCODE
:
360 case ADDR_PREFIX_OPCODE
:
361 case CS_PREFIX_OPCODE
:
362 case DS_PREFIX_OPCODE
:
363 case ES_PREFIX_OPCODE
:
364 case FS_PREFIX_OPCODE
:
365 case GS_PREFIX_OPCODE
:
366 case SS_PREFIX_OPCODE
:
367 case LOCK_PREFIX_OPCODE
:
368 case REPE_PREFIX_OPCODE
:
369 case REPNE_PREFIX_OPCODE
:
381 i386_absolute_jmp_p (const gdb_byte
*insn
)
383 /* jmp far (absolute address in operand) */
389 /* jump near, absolute indirect (/4) */
390 if ((insn
[1] & 0x38) == 0x20)
393 /* jump far, absolute indirect (/5) */
394 if ((insn
[1] & 0x38) == 0x28)
402 i386_absolute_call_p (const gdb_byte
*insn
)
404 /* call far, absolute */
410 /* Call near, absolute indirect (/2) */
411 if ((insn
[1] & 0x38) == 0x10)
414 /* Call far, absolute indirect (/3) */
415 if ((insn
[1] & 0x38) == 0x18)
423 i386_ret_p (const gdb_byte
*insn
)
427 case 0xc2: /* ret near, pop N bytes */
428 case 0xc3: /* ret near */
429 case 0xca: /* ret far, pop N bytes */
430 case 0xcb: /* ret far */
431 case 0xcf: /* iret */
440 i386_call_p (const gdb_byte
*insn
)
442 if (i386_absolute_call_p (insn
))
445 /* call near, relative */
452 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
453 length in bytes. Otherwise, return zero. */
456 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
467 /* Fix up the state of registers and memory after having single-stepped
468 a displaced instruction. */
471 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
472 struct displaced_step_closure
*closure
,
473 CORE_ADDR from
, CORE_ADDR to
,
474 struct regcache
*regs
)
476 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
478 /* The offset we applied to the instruction's address.
479 This could well be negative (when viewed as a signed 32-bit
480 value), but ULONGEST won't reflect that, so take care when
482 ULONGEST insn_offset
= to
- from
;
484 /* Since we use simple_displaced_step_copy_insn, our closure is a
485 copy of the instruction. */
486 gdb_byte
*insn
= (gdb_byte
*) closure
;
487 /* The start of the insn, needed in case we see some prefixes. */
488 gdb_byte
*insn_start
= insn
;
491 fprintf_unfiltered (gdb_stdlog
,
492 "displaced: fixup (%s, %s), "
493 "insn = 0x%02x 0x%02x ...\n",
494 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
497 /* The list of issues to contend with here is taken from
498 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
499 Yay for Free Software! */
501 /* Relocate the %eip, if necessary. */
503 /* The instruction recognizers we use assume any leading prefixes
504 have been skipped. */
506 /* This is the size of the buffer in closure. */
507 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
508 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
509 /* If there are too many prefixes, just ignore the insn.
510 It will fault when run. */
515 /* Except in the case of absolute or indirect jump or call
516 instructions, or a return instruction, the new eip is relative to
517 the displaced instruction; make it relative. Well, signal
518 handler returns don't need relocation either, but we use the
519 value of %eip to recognize those; see below. */
520 if (! i386_absolute_jmp_p (insn
)
521 && ! i386_absolute_call_p (insn
)
522 && ! i386_ret_p (insn
))
527 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
529 /* A signal trampoline system call changes the %eip, resuming
530 execution of the main program after the signal handler has
531 returned. That makes them like 'return' instructions; we
532 shouldn't relocate %eip.
534 But most system calls don't, and we do need to relocate %eip.
536 Our heuristic for distinguishing these cases: if stepping
537 over the system call instruction left control directly after
538 the instruction, the we relocate --- control almost certainly
539 doesn't belong in the displaced copy. Otherwise, we assume
540 the instruction has put control where it belongs, and leave
541 it unrelocated. Goodness help us if there are PC-relative
543 if (i386_syscall_p (insn
, &insn_len
)
544 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
547 fprintf_unfiltered (gdb_stdlog
,
548 "displaced: syscall changed %%eip; "
553 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
555 /* If we just stepped over a breakpoint insn, we don't backup
556 the pc on purpose; this is to match behaviour without
559 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
562 fprintf_unfiltered (gdb_stdlog
,
564 "relocated %%eip from %s to %s\n",
565 paddress (gdbarch
, orig_eip
),
566 paddress (gdbarch
, eip
));
570 /* If the instruction was PUSHFL, then the TF bit will be set in the
571 pushed value, and should be cleared. We'll leave this for later,
572 since GDB already messes up the TF flag when stepping over a
575 /* If the instruction was a call, the return address now atop the
576 stack is the address following the copied instruction. We need
577 to make it the address following the original instruction. */
578 if (i386_call_p (insn
))
582 const ULONGEST retaddr_len
= 4;
584 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
585 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
586 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
587 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
590 fprintf_unfiltered (gdb_stdlog
,
591 "displaced: relocated return addr at %s to %s\n",
592 paddress (gdbarch
, esp
),
593 paddress (gdbarch
, retaddr
));
597 #ifdef I386_REGNO_TO_SYMMETRY
598 #error "The Sequent Symmetry is no longer supported."
601 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
602 and %esp "belong" to the calling function. Therefore these
603 registers should be saved if they're going to be modified. */
605 /* The maximum number of saved registers. This should include all
606 registers mentioned above, and %eip. */
607 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
609 struct i386_frame_cache
616 /* Saved registers. */
617 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
622 /* Stack space reserved for local variables. */
626 /* Allocate and initialize a frame cache. */
628 static struct i386_frame_cache
*
629 i386_alloc_frame_cache (void)
631 struct i386_frame_cache
*cache
;
634 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
638 cache
->sp_offset
= -4;
641 /* Saved registers. We initialize these to -1 since zero is a valid
642 offset (that's where %ebp is supposed to be stored). */
643 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
644 cache
->saved_regs
[i
] = -1;
646 cache
->saved_sp_reg
= -1;
647 cache
->pc_in_eax
= 0;
649 /* Frameless until proven otherwise. */
655 /* If the instruction at PC is a jump, return the address of its
656 target. Otherwise, return PC. */
659 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
661 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
666 target_read_memory (pc
, &op
, 1);
670 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
676 /* Relative jump: if data16 == 0, disp32, else disp16. */
679 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
681 /* Include the size of the jmp instruction (including the
687 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
689 /* Include the size of the jmp instruction. */
694 /* Relative jump, disp8 (ignore data16). */
695 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
704 /* Check whether PC points at a prologue for a function returning a
705 structure or union. If so, it updates CACHE and returns the
706 address of the first instruction after the code sequence that
707 removes the "hidden" argument from the stack or CURRENT_PC,
708 whichever is smaller. Otherwise, return PC. */
711 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
712 struct i386_frame_cache
*cache
)
714 /* Functions that return a structure or union start with:
717 xchgl %eax, (%esp) 0x87 0x04 0x24
718 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
720 (the System V compiler puts out the second `xchg' instruction,
721 and the assembler doesn't try to optimize it, so the 'sib' form
722 gets generated). This sequence is used to get the address of the
723 return buffer for a function that returns a structure. */
724 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
725 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
729 if (current_pc
<= pc
)
732 target_read_memory (pc
, &op
, 1);
734 if (op
!= 0x58) /* popl %eax */
737 target_read_memory (pc
+ 1, buf
, 4);
738 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
741 if (current_pc
== pc
)
743 cache
->sp_offset
+= 4;
747 if (current_pc
== pc
+ 1)
749 cache
->pc_in_eax
= 1;
753 if (buf
[1] == proto1
[1])
760 i386_skip_probe (CORE_ADDR pc
)
762 /* A function may start with
776 target_read_memory (pc
, &op
, 1);
778 if (op
== 0x68 || op
== 0x6a)
782 /* Skip past the `pushl' instruction; it has either a one-byte or a
783 four-byte operand, depending on the opcode. */
789 /* Read the following 8 bytes, which should be `call _probe' (6
790 bytes) followed by `addl $4,%esp' (2 bytes). */
791 read_memory (pc
+ delta
, buf
, sizeof (buf
));
792 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
793 pc
+= delta
+ sizeof (buf
);
799 /* GCC 4.1 and later, can put code in the prologue to realign the
800 stack pointer. Check whether PC points to such code, and update
801 CACHE accordingly. Return the first instruction after the code
802 sequence or CURRENT_PC, whichever is smaller. If we don't
803 recognize the code, return PC. */
806 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
807 struct i386_frame_cache
*cache
)
809 /* There are 2 code sequences to re-align stack before the frame
812 1. Use a caller-saved saved register:
818 2. Use a callee-saved saved register:
825 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
827 0x83 0xe4 0xf0 andl $-16, %esp
828 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
833 int offset
, offset_and
;
834 static int regnums
[8] = {
835 I386_EAX_REGNUM
, /* %eax */
836 I386_ECX_REGNUM
, /* %ecx */
837 I386_EDX_REGNUM
, /* %edx */
838 I386_EBX_REGNUM
, /* %ebx */
839 I386_ESP_REGNUM
, /* %esp */
840 I386_EBP_REGNUM
, /* %ebp */
841 I386_ESI_REGNUM
, /* %esi */
842 I386_EDI_REGNUM
/* %edi */
845 if (target_read_memory (pc
, buf
, sizeof buf
))
848 /* Check caller-saved saved register. The first instruction has
849 to be "leal 4(%esp), %reg". */
850 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
852 /* MOD must be binary 10 and R/M must be binary 100. */
853 if ((buf
[1] & 0xc7) != 0x44)
856 /* REG has register number. */
857 reg
= (buf
[1] >> 3) & 7;
862 /* Check callee-saved saved register. The first instruction
863 has to be "pushl %reg". */
864 if ((buf
[0] & 0xf8) != 0x50)
870 /* The next instruction has to be "leal 8(%esp), %reg". */
871 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
874 /* MOD must be binary 10 and R/M must be binary 100. */
875 if ((buf
[2] & 0xc7) != 0x44)
878 /* REG has register number. Registers in pushl and leal have to
880 if (reg
!= ((buf
[2] >> 3) & 7))
886 /* Rigister can't be %esp nor %ebp. */
887 if (reg
== 4 || reg
== 5)
890 /* The next instruction has to be "andl $-XXX, %esp". */
891 if (buf
[offset
+ 1] != 0xe4
892 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
896 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
898 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
899 0xfc. REG must be binary 110 and MOD must be binary 01. */
900 if (buf
[offset
] != 0xff
901 || buf
[offset
+ 2] != 0xfc
902 || (buf
[offset
+ 1] & 0xf8) != 0x70)
905 /* R/M has register. Registers in leal and pushl have to be the
907 if (reg
!= (buf
[offset
+ 1] & 7))
910 if (current_pc
> pc
+ offset_and
)
911 cache
->saved_sp_reg
= regnums
[reg
];
913 return min (pc
+ offset
+ 3, current_pc
);
916 /* Maximum instruction length we need to handle. */
917 #define I386_MAX_MATCHED_INSN_LEN 6
919 /* Instruction description. */
923 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
924 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
927 /* Search for the instruction at PC in the list SKIP_INSNS. Return
928 the first instruction description that matches. Otherwise, return
931 static struct i386_insn
*
932 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
934 struct i386_insn
*insn
;
937 target_read_memory (pc
, &op
, 1);
939 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
941 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
943 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
944 int insn_matched
= 1;
947 gdb_assert (insn
->len
> 1);
948 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
950 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
951 for (i
= 1; i
< insn
->len
; i
++)
953 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
965 /* Some special instructions that might be migrated by GCC into the
966 part of the prologue that sets up the new stack frame. Because the
967 stack frame hasn't been setup yet, no registers have been saved
968 yet, and only the scratch registers %eax, %ecx and %edx can be
971 struct i386_insn i386_frame_setup_skip_insns
[] =
973 /* Check for `movb imm8, r' and `movl imm32, r'.
975 ??? Should we handle 16-bit operand-sizes here? */
977 /* `movb imm8, %al' and `movb imm8, %ah' */
978 /* `movb imm8, %cl' and `movb imm8, %ch' */
979 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
980 /* `movb imm8, %dl' and `movb imm8, %dh' */
981 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
982 /* `movl imm32, %eax' and `movl imm32, %ecx' */
983 { 5, { 0xb8 }, { 0xfe } },
984 /* `movl imm32, %edx' */
985 { 5, { 0xba }, { 0xff } },
987 /* Check for `mov imm32, r32'. Note that there is an alternative
988 encoding for `mov m32, %eax'.
990 ??? Should we handle SIB adressing here?
991 ??? Should we handle 16-bit operand-sizes here? */
993 /* `movl m32, %eax' */
994 { 5, { 0xa1 }, { 0xff } },
995 /* `movl m32, %eax' and `mov; m32, %ecx' */
996 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
997 /* `movl m32, %edx' */
998 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1000 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1001 Because of the symmetry, there are actually two ways to encode
1002 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1003 opcode bytes 0x31 and 0x33 for `xorl'. */
1005 /* `subl %eax, %eax' */
1006 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1007 /* `subl %ecx, %ecx' */
1008 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1009 /* `subl %edx, %edx' */
1010 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1011 /* `xorl %eax, %eax' */
1012 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1013 /* `xorl %ecx, %ecx' */
1014 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1015 /* `xorl %edx, %edx' */
1016 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1021 /* Check whether PC points to a no-op instruction. */
1023 i386_skip_noop (CORE_ADDR pc
)
1028 target_read_memory (pc
, &op
, 1);
1033 /* Ignore `nop' instruction. */
1037 target_read_memory (pc
, &op
, 1);
1040 /* Ignore no-op instruction `mov %edi, %edi'.
1041 Microsoft system dlls often start with
1042 a `mov %edi,%edi' instruction.
1043 The 5 bytes before the function start are
1044 filled with `nop' instructions.
1045 This pattern can be used for hot-patching:
1046 The `mov %edi, %edi' instruction can be replaced by a
1047 near jump to the location of the 5 `nop' instructions
1048 which can be replaced by a 32-bit jump to anywhere
1049 in the 32-bit address space. */
1051 else if (op
== 0x8b)
1053 target_read_memory (pc
+ 1, &op
, 1);
1057 target_read_memory (pc
, &op
, 1);
1065 /* Check whether PC points at a code that sets up a new stack frame.
1066 If so, it updates CACHE and returns the address of the first
1067 instruction after the sequence that sets up the frame or LIMIT,
1068 whichever is smaller. If we don't recognize the code, return PC. */
1071 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1072 CORE_ADDR pc
, CORE_ADDR limit
,
1073 struct i386_frame_cache
*cache
)
1075 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1076 struct i386_insn
*insn
;
1083 target_read_memory (pc
, &op
, 1);
1085 if (op
== 0x55) /* pushl %ebp */
1087 /* Take into account that we've executed the `pushl %ebp' that
1088 starts this instruction sequence. */
1089 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1090 cache
->sp_offset
+= 4;
1093 /* If that's all, return now. */
1097 /* Check for some special instructions that might be migrated by
1098 GCC into the prologue and skip them. At this point in the
1099 prologue, code should only touch the scratch registers %eax,
1100 %ecx and %edx, so while the number of posibilities is sheer,
1103 Make sure we only skip these instructions if we later see the
1104 `movl %esp, %ebp' that actually sets up the frame. */
1105 while (pc
+ skip
< limit
)
1107 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1114 /* If that's all, return now. */
1115 if (limit
<= pc
+ skip
)
1118 target_read_memory (pc
+ skip
, &op
, 1);
1120 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1124 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1129 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1137 /* OK, we actually have a frame. We just don't know how large
1138 it is yet. Set its size to zero. We'll adjust it if
1139 necessary. We also now commit to skipping the special
1140 instructions mentioned before. */
1144 /* If that's all, return now. */
1148 /* Check for stack adjustment
1152 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1153 reg, so we don't have to worry about a data16 prefix. */
1154 target_read_memory (pc
, &op
, 1);
1157 /* `subl' with 8-bit immediate. */
1158 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1159 /* Some instruction starting with 0x83 other than `subl'. */
1162 /* `subl' with signed 8-bit immediate (though it wouldn't
1163 make sense to be negative). */
1164 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1167 else if (op
== 0x81)
1169 /* Maybe it is `subl' with a 32-bit immediate. */
1170 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1171 /* Some instruction starting with 0x81 other than `subl'. */
1174 /* It is `subl' with a 32-bit immediate. */
1175 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1180 /* Some instruction other than `subl'. */
1184 else if (op
== 0xc8) /* enter */
1186 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1193 /* Check whether PC points at code that saves registers on the stack.
1194 If so, it updates CACHE and returns the address of the first
1195 instruction after the register saves or CURRENT_PC, whichever is
1196 smaller. Otherwise, return PC. */
1199 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1200 struct i386_frame_cache
*cache
)
1202 CORE_ADDR offset
= 0;
1206 if (cache
->locals
> 0)
1207 offset
-= cache
->locals
;
1208 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1210 target_read_memory (pc
, &op
, 1);
1211 if (op
< 0x50 || op
> 0x57)
1215 cache
->saved_regs
[op
- 0x50] = offset
;
1216 cache
->sp_offset
+= 4;
1223 /* Do a full analysis of the prologue at PC and update CACHE
1224 accordingly. Bail out early if CURRENT_PC is reached. Return the
1225 address where the analysis stopped.
1227 We handle these cases:
1229 The startup sequence can be at the start of the function, or the
1230 function can start with a branch to startup code at the end.
1232 %ebp can be set up with either the 'enter' instruction, or "pushl
1233 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1234 once used in the System V compiler).
1236 Local space is allocated just below the saved %ebp by either the
1237 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1238 16-bit unsigned argument for space to allocate, and the 'addl'
1239 instruction could have either a signed byte, or 32-bit immediate.
1241 Next, the registers used by this function are pushed. With the
1242 System V compiler they will always be in the order: %edi, %esi,
1243 %ebx (and sometimes a harmless bug causes it to also save but not
1244 restore %eax); however, the code below is willing to see the pushes
1245 in any order, and will handle up to 8 of them.
1247 If the setup sequence is at the end of the function, then the next
1248 instruction will be a branch back to the start. */
1251 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1252 CORE_ADDR pc
, CORE_ADDR current_pc
,
1253 struct i386_frame_cache
*cache
)
1255 pc
= i386_skip_noop (pc
);
1256 pc
= i386_follow_jump (gdbarch
, pc
);
1257 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1258 pc
= i386_skip_probe (pc
);
1259 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1260 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1261 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1264 /* Return PC of first real instruction. */
1267 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1269 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1271 static gdb_byte pic_pat
[6] =
1273 0xe8, 0, 0, 0, 0, /* call 0x0 */
1274 0x5b, /* popl %ebx */
1276 struct i386_frame_cache cache
;
1282 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1283 if (cache
.locals
< 0)
1286 /* Found valid frame setup. */
1288 /* The native cc on SVR4 in -K PIC mode inserts the following code
1289 to get the address of the global offset table (GOT) into register
1294 movl %ebx,x(%ebp) (optional)
1297 This code is with the rest of the prologue (at the end of the
1298 function), so we have to skip it to get to the first real
1299 instruction at the start of the function. */
1301 for (i
= 0; i
< 6; i
++)
1303 target_read_memory (pc
+ i
, &op
, 1);
1304 if (pic_pat
[i
] != op
)
1311 target_read_memory (pc
+ delta
, &op
, 1);
1313 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1315 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1317 if (op
== 0x5d) /* One byte offset from %ebp. */
1319 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1321 else /* Unexpected instruction. */
1324 target_read_memory (pc
+ delta
, &op
, 1);
1328 if (delta
> 0 && op
== 0x81
1329 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1336 /* If the function starts with a branch (to startup code at the end)
1337 the last instruction should bring us back to the first
1338 instruction of the real code. */
1339 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1340 pc
= i386_follow_jump (gdbarch
, pc
);
1345 /* Check that the code pointed to by PC corresponds to a call to
1346 __main, skip it if so. Return PC otherwise. */
1349 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1351 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1354 target_read_memory (pc
, &op
, 1);
1359 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1361 /* Make sure address is computed correctly as a 32bit
1362 integer even if CORE_ADDR is 64 bit wide. */
1363 struct minimal_symbol
*s
;
1364 CORE_ADDR call_dest
;
1366 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1367 call_dest
= call_dest
& 0xffffffffU
;
1368 s
= lookup_minimal_symbol_by_pc (call_dest
);
1370 && SYMBOL_LINKAGE_NAME (s
) != NULL
1371 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1379 /* This function is 64-bit safe. */
1382 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1386 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1387 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1391 /* Normal frames. */
1393 static struct i386_frame_cache
*
1394 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1396 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1397 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1398 struct i386_frame_cache
*cache
;
1405 cache
= i386_alloc_frame_cache ();
1406 *this_cache
= cache
;
1408 /* In principle, for normal frames, %ebp holds the frame pointer,
1409 which holds the base address for the current stack frame.
1410 However, for functions that don't need it, the frame pointer is
1411 optional. For these "frameless" functions the frame pointer is
1412 actually the frame pointer of the calling frame. Signal
1413 trampolines are just a special case of a "frameless" function.
1414 They (usually) share their frame pointer with the frame that was
1415 in progress when the signal occurred. */
1417 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1418 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1419 if (cache
->base
== 0)
1422 /* For normal frames, %eip is stored at 4(%ebp). */
1423 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1425 cache
->pc
= get_frame_func (this_frame
);
1427 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1430 if (cache
->saved_sp_reg
!= -1)
1432 /* Saved stack pointer has been saved. */
1433 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1434 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1437 if (cache
->locals
< 0)
1439 /* We didn't find a valid frame, which means that CACHE->base
1440 currently holds the frame pointer for our calling frame. If
1441 we're at the start of a function, or somewhere half-way its
1442 prologue, the function's frame probably hasn't been fully
1443 setup yet. Try to reconstruct the base address for the stack
1444 frame by looking at the stack pointer. For truly "frameless"
1445 functions this might work too. */
1447 if (cache
->saved_sp_reg
!= -1)
1449 /* We're halfway aligning the stack. */
1450 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1451 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1453 /* This will be added back below. */
1454 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1456 else if (cache
->pc
!= 0
1457 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1459 /* We're in a known function, but did not find a frame
1460 setup. Assume that the function does not use %ebp.
1461 Alternatively, we may have jumped to an invalid
1462 address; in that case there is definitely no new
1464 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1465 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1469 /* We're in an unknown function. We could not find the start
1470 of the function to analyze the prologue; our best option is
1471 to assume a typical frame layout with the caller's %ebp
1473 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1476 /* Now that we have the base address for the stack frame we can
1477 calculate the value of %esp in the calling frame. */
1478 if (cache
->saved_sp
== 0)
1479 cache
->saved_sp
= cache
->base
+ 8;
1481 /* Adjust all the saved registers such that they contain addresses
1482 instead of offsets. */
1483 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1484 if (cache
->saved_regs
[i
] != -1)
1485 cache
->saved_regs
[i
] += cache
->base
;
1491 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1492 struct frame_id
*this_id
)
1494 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1496 /* This marks the outermost frame. */
1497 if (cache
->base
== 0)
1500 /* See the end of i386_push_dummy_call. */
1501 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1504 static struct value
*
1505 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1508 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1510 gdb_assert (regnum
>= 0);
1512 /* The System V ABI says that:
1514 "The flags register contains the system flags, such as the
1515 direction flag and the carry flag. The direction flag must be
1516 set to the forward (that is, zero) direction before entry and
1517 upon exit from a function. Other user flags have no specified
1518 role in the standard calling sequence and are not preserved."
1520 To guarantee the "upon exit" part of that statement we fake a
1521 saved flags register that has its direction flag cleared.
1523 Note that GCC doesn't seem to rely on the fact that the direction
1524 flag is cleared after a function return; it always explicitly
1525 clears the flag before operations where it matters.
1527 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1528 right thing to do. The way we fake the flags register here makes
1529 it impossible to change it. */
1531 if (regnum
== I386_EFLAGS_REGNUM
)
1535 val
= get_frame_register_unsigned (this_frame
, regnum
);
1537 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1540 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1541 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1543 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1544 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1546 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1547 return frame_unwind_got_memory (this_frame
, regnum
,
1548 cache
->saved_regs
[regnum
]);
1550 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1553 static const struct frame_unwind i386_frame_unwind
=
1557 i386_frame_prev_register
,
1559 default_frame_sniffer
1562 /* Normal frames, but in a function epilogue. */
1564 /* The epilogue is defined here as the 'ret' instruction, which will
1565 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1566 the function's stack frame. */
1569 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1573 if (target_read_memory (pc
, &insn
, 1))
1574 return 0; /* Can't read memory at pc. */
1576 if (insn
!= 0xc3) /* 'ret' instruction. */
1583 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1584 struct frame_info
*this_frame
,
1585 void **this_prologue_cache
)
1587 if (frame_relative_level (this_frame
) == 0)
1588 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1589 get_frame_pc (this_frame
));
1594 static struct i386_frame_cache
*
1595 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1597 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1599 struct i386_frame_cache
*cache
;
1605 cache
= i386_alloc_frame_cache ();
1606 *this_cache
= cache
;
1608 /* Cache base will be %esp plus cache->sp_offset (-4). */
1609 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1610 cache
->base
= extract_unsigned_integer (buf
, 4,
1611 byte_order
) + cache
->sp_offset
;
1613 /* Cache pc will be the frame func. */
1614 cache
->pc
= get_frame_pc (this_frame
);
1616 /* The saved %esp will be at cache->base plus 8. */
1617 cache
->saved_sp
= cache
->base
+ 8;
1619 /* The saved %eip will be at cache->base plus 4. */
1620 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1626 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1628 struct frame_id
*this_id
)
1630 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1633 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1636 static const struct frame_unwind i386_epilogue_frame_unwind
=
1639 i386_epilogue_frame_this_id
,
1640 i386_frame_prev_register
,
1642 i386_epilogue_frame_sniffer
1646 /* Signal trampolines. */
1648 static struct i386_frame_cache
*
1649 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1651 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1653 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1654 struct i386_frame_cache
*cache
;
1661 cache
= i386_alloc_frame_cache ();
1663 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1664 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1666 addr
= tdep
->sigcontext_addr (this_frame
);
1667 if (tdep
->sc_reg_offset
)
1671 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1673 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1674 if (tdep
->sc_reg_offset
[i
] != -1)
1675 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1679 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1680 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1683 *this_cache
= cache
;
1688 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1689 struct frame_id
*this_id
)
1691 struct i386_frame_cache
*cache
=
1692 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1694 /* See the end of i386_push_dummy_call. */
1695 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1698 static struct value
*
1699 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1700 void **this_cache
, int regnum
)
1702 /* Make sure we've initialized the cache. */
1703 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1705 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1709 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1710 struct frame_info
*this_frame
,
1711 void **this_prologue_cache
)
1713 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1715 /* We shouldn't even bother if we don't have a sigcontext_addr
1717 if (tdep
->sigcontext_addr
== NULL
)
1720 if (tdep
->sigtramp_p
!= NULL
)
1722 if (tdep
->sigtramp_p (this_frame
))
1726 if (tdep
->sigtramp_start
!= 0)
1728 CORE_ADDR pc
= get_frame_pc (this_frame
);
1730 gdb_assert (tdep
->sigtramp_end
!= 0);
1731 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1738 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1741 i386_sigtramp_frame_this_id
,
1742 i386_sigtramp_frame_prev_register
,
1744 i386_sigtramp_frame_sniffer
1749 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1751 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1756 static const struct frame_base i386_frame_base
=
1759 i386_frame_base_address
,
1760 i386_frame_base_address
,
1761 i386_frame_base_address
1764 static struct frame_id
1765 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1769 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1771 /* See the end of i386_push_dummy_call. */
1772 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1776 /* Figure out where the longjmp will land. Slurp the args out of the
1777 stack. We expect the first arg to be a pointer to the jmp_buf
1778 structure from which we extract the address that we will land at.
1779 This address is copied into PC. This routine returns non-zero on
1783 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1786 CORE_ADDR sp
, jb_addr
;
1787 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1788 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1789 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1791 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1792 longjmp will land. */
1793 if (jb_pc_offset
== -1)
1796 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1797 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1798 if (target_read_memory (sp
+ 4, buf
, 4))
1801 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1802 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1805 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1810 /* Check whether TYPE must be 16-byte-aligned when passed as a
1811 function argument. 16-byte vectors, _Decimal128 and structures or
1812 unions containing such types must be 16-byte-aligned; other
1813 arguments are 4-byte-aligned. */
1816 i386_16_byte_align_p (struct type
*type
)
1818 type
= check_typedef (type
);
1819 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1820 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1821 && TYPE_LENGTH (type
) == 16)
1823 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1824 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1825 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1826 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1829 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1831 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1839 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1840 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1841 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1842 CORE_ADDR struct_addr
)
1844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1850 /* Determine the total space required for arguments and struct
1851 return address in a first pass (allowing for 16-byte-aligned
1852 arguments), then push arguments in a second pass. */
1854 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1856 int args_space_used
= 0;
1857 int have_16_byte_aligned_arg
= 0;
1863 /* Push value address. */
1864 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1865 write_memory (sp
, buf
, 4);
1866 args_space_used
+= 4;
1872 for (i
= 0; i
< nargs
; i
++)
1874 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1878 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1879 args_space_used
= align_up (args_space_used
, 16);
1881 write_memory (sp
+ args_space_used
,
1882 value_contents_all (args
[i
]), len
);
1883 /* The System V ABI says that:
1885 "An argument's size is increased, if necessary, to make it a
1886 multiple of [32-bit] words. This may require tail padding,
1887 depending on the size of the argument."
1889 This makes sure the stack stays word-aligned. */
1890 args_space_used
+= align_up (len
, 4);
1894 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1896 args_space
= align_up (args_space
, 16);
1897 have_16_byte_aligned_arg
= 1;
1899 args_space
+= align_up (len
, 4);
1905 if (have_16_byte_aligned_arg
)
1906 args_space
= align_up (args_space
, 16);
1911 /* Store return address. */
1913 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1914 write_memory (sp
, buf
, 4);
1916 /* Finally, update the stack pointer... */
1917 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1918 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1920 /* ...and fake a frame pointer. */
1921 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1923 /* MarkK wrote: This "+ 8" is all over the place:
1924 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1925 i386_dummy_id). It's there, since all frame unwinders for
1926 a given target have to agree (within a certain margin) on the
1927 definition of the stack address of a frame. Otherwise frame id
1928 comparison might not work correctly. Since DWARF2/GCC uses the
1929 stack address *before* the function call as a frame's CFA. On
1930 the i386, when %ebp is used as a frame pointer, the offset
1931 between the contents %ebp and the CFA as defined by GCC. */
1935 /* These registers are used for returning integers (and on some
1936 targets also for returning `struct' and `union' values when their
1937 size and alignment match an integer type). */
1938 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1939 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1941 /* Read, for architecture GDBARCH, a function return value of TYPE
1942 from REGCACHE, and copy that into VALBUF. */
1945 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1946 struct regcache
*regcache
, gdb_byte
*valbuf
)
1948 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1949 int len
= TYPE_LENGTH (type
);
1950 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1952 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1954 if (tdep
->st0_regnum
< 0)
1956 warning (_("Cannot find floating-point return value."));
1957 memset (valbuf
, 0, len
);
1961 /* Floating-point return values can be found in %st(0). Convert
1962 its contents to the desired type. This is probably not
1963 exactly how it would happen on the target itself, but it is
1964 the best we can do. */
1965 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1966 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1970 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1971 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1973 if (len
<= low_size
)
1975 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1976 memcpy (valbuf
, buf
, len
);
1978 else if (len
<= (low_size
+ high_size
))
1980 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1981 memcpy (valbuf
, buf
, low_size
);
1982 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1983 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1986 internal_error (__FILE__
, __LINE__
,
1987 _("Cannot extract return value of %d bytes long."), len
);
1991 /* Write, for architecture GDBARCH, a function return value of TYPE
1992 from VALBUF into REGCACHE. */
1995 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1996 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1999 int len
= TYPE_LENGTH (type
);
2001 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2004 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2006 if (tdep
->st0_regnum
< 0)
2008 warning (_("Cannot set floating-point return value."));
2012 /* Returning floating-point values is a bit tricky. Apart from
2013 storing the return value in %st(0), we have to simulate the
2014 state of the FPU at function return point. */
2016 /* Convert the value found in VALBUF to the extended
2017 floating-point format used by the FPU. This is probably
2018 not exactly how it would happen on the target itself, but
2019 it is the best we can do. */
2020 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2021 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2023 /* Set the top of the floating-point register stack to 7. The
2024 actual value doesn't really matter, but 7 is what a normal
2025 function return would end up with if the program started out
2026 with a freshly initialized FPU. */
2027 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2029 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2031 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2032 the floating-point register stack to 7, the appropriate value
2033 for the tag word is 0x3fff. */
2034 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2038 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2039 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2041 if (len
<= low_size
)
2042 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2043 else if (len
<= (low_size
+ high_size
))
2045 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2046 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2047 len
- low_size
, valbuf
+ low_size
);
2050 internal_error (__FILE__
, __LINE__
,
2051 _("Cannot store return value of %d bytes long."), len
);
2056 /* This is the variable that is set with "set struct-convention", and
2057 its legitimate values. */
2058 static const char default_struct_convention
[] = "default";
2059 static const char pcc_struct_convention
[] = "pcc";
2060 static const char reg_struct_convention
[] = "reg";
2061 static const char *valid_conventions
[] =
2063 default_struct_convention
,
2064 pcc_struct_convention
,
2065 reg_struct_convention
,
2068 static const char *struct_convention
= default_struct_convention
;
2070 /* Return non-zero if TYPE, which is assumed to be a structure,
2071 a union type, or an array type, should be returned in registers
2072 for architecture GDBARCH. */
2075 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2077 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2078 enum type_code code
= TYPE_CODE (type
);
2079 int len
= TYPE_LENGTH (type
);
2081 gdb_assert (code
== TYPE_CODE_STRUCT
2082 || code
== TYPE_CODE_UNION
2083 || code
== TYPE_CODE_ARRAY
);
2085 if (struct_convention
== pcc_struct_convention
2086 || (struct_convention
== default_struct_convention
2087 && tdep
->struct_return
== pcc_struct_return
))
2090 /* Structures consisting of a single `float', `double' or 'long
2091 double' member are returned in %st(0). */
2092 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2094 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2095 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2096 return (len
== 4 || len
== 8 || len
== 12);
2099 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2102 /* Determine, for architecture GDBARCH, how a return value of TYPE
2103 should be returned. If it is supposed to be returned in registers,
2104 and READBUF is non-zero, read the appropriate value from REGCACHE,
2105 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2106 from WRITEBUF into REGCACHE. */
2108 static enum return_value_convention
2109 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2110 struct type
*type
, struct regcache
*regcache
,
2111 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2113 enum type_code code
= TYPE_CODE (type
);
2115 if (((code
== TYPE_CODE_STRUCT
2116 || code
== TYPE_CODE_UNION
2117 || code
== TYPE_CODE_ARRAY
)
2118 && !i386_reg_struct_return_p (gdbarch
, type
))
2119 /* 128-bit decimal float uses the struct return convention. */
2120 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2122 /* The System V ABI says that:
2124 "A function that returns a structure or union also sets %eax
2125 to the value of the original address of the caller's area
2126 before it returns. Thus when the caller receives control
2127 again, the address of the returned object resides in register
2128 %eax and can be used to access the object."
2130 So the ABI guarantees that we can always find the return
2131 value just after the function has returned. */
2133 /* Note that the ABI doesn't mention functions returning arrays,
2134 which is something possible in certain languages such as Ada.
2135 In this case, the value is returned as if it was wrapped in
2136 a record, so the convention applied to records also applies
2143 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2144 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2147 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2150 /* This special case is for structures consisting of a single
2151 `float', `double' or 'long double' member. These structures are
2152 returned in %st(0). For these structures, we call ourselves
2153 recursively, changing TYPE into the type of the first member of
2154 the structure. Since that should work for all structures that
2155 have only one member, we don't bother to check the member's type
2157 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2159 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2160 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2165 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2167 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2169 return RETURN_VALUE_REGISTER_CONVENTION
;
2174 i387_ext_type (struct gdbarch
*gdbarch
)
2176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2178 if (!tdep
->i387_ext_type
)
2180 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2181 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2184 return tdep
->i387_ext_type
;
2187 /* Construct vector type for MMX registers. */
2188 static struct type
*
2189 i386_mmx_type (struct gdbarch
*gdbarch
)
2191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2193 if (!tdep
->i386_mmx_type
)
2195 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2197 /* The type we're building is this: */
2199 union __gdb_builtin_type_vec64i
2202 int32_t v2_int32
[2];
2203 int16_t v4_int16
[4];
2210 t
= arch_composite_type (gdbarch
,
2211 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2213 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2214 append_composite_type_field (t
, "v2_int32",
2215 init_vector_type (bt
->builtin_int32
, 2));
2216 append_composite_type_field (t
, "v4_int16",
2217 init_vector_type (bt
->builtin_int16
, 4));
2218 append_composite_type_field (t
, "v8_int8",
2219 init_vector_type (bt
->builtin_int8
, 8));
2221 TYPE_VECTOR (t
) = 1;
2222 TYPE_NAME (t
) = "builtin_type_vec64i";
2223 tdep
->i386_mmx_type
= t
;
2226 return tdep
->i386_mmx_type
;
2229 /* Return the GDB type object for the "standard" data type of data in
2232 static struct type
*
2233 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2235 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2236 return i386_mmx_type (gdbarch
);
2239 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2240 if (i386_byte_regnum_p (gdbarch
, regnum
))
2241 return bt
->builtin_int8
;
2242 else if (i386_word_regnum_p (gdbarch
, regnum
))
2243 return bt
->builtin_int16
;
2244 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2245 return bt
->builtin_int32
;
2248 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2251 /* Map a cooked register onto a raw register or memory. For the i386,
2252 the MMX registers need to be mapped onto floating point registers. */
2255 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2262 mmxreg
= regnum
- tdep
->mm0_regnum
;
2263 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2264 tos
= (fstat
>> 11) & 0x7;
2265 fpreg
= (mmxreg
+ tos
) % 8;
2267 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2271 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2272 int regnum
, gdb_byte
*buf
)
2274 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2276 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2278 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2280 /* Extract (always little endian). */
2281 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2282 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2288 if (i386_word_regnum_p (gdbarch
, regnum
))
2290 int gpnum
= regnum
- tdep
->ax_regnum
;
2292 /* Extract (always little endian). */
2293 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2294 memcpy (buf
, raw_buf
, 2);
2296 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2298 /* Check byte pseudo registers last since this function will
2299 be called from amd64_pseudo_register_read, which handles
2300 byte pseudo registers differently. */
2301 int gpnum
= regnum
- tdep
->al_regnum
;
2303 /* Extract (always little endian). We read both lower and
2305 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2307 memcpy (buf
, raw_buf
+ 1, 1);
2309 memcpy (buf
, raw_buf
, 1);
2312 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2317 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2318 int regnum
, const gdb_byte
*buf
)
2320 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2322 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2324 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2327 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2328 /* ... Modify ... (always little endian). */
2329 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2331 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2337 if (i386_word_regnum_p (gdbarch
, regnum
))
2339 int gpnum
= regnum
- tdep
->ax_regnum
;
2342 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2343 /* ... Modify ... (always little endian). */
2344 memcpy (raw_buf
, buf
, 2);
2346 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2348 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2350 /* Check byte pseudo registers last since this function will
2351 be called from amd64_pseudo_register_read, which handles
2352 byte pseudo registers differently. */
2353 int gpnum
= regnum
- tdep
->al_regnum
;
2355 /* Read ... We read both lower and upper registers. */
2356 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2357 /* ... Modify ... (always little endian). */
2359 memcpy (raw_buf
+ 1, buf
, 1);
2361 memcpy (raw_buf
, buf
, 1);
2363 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2366 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2371 /* Return the register number of the register allocated by GCC after
2372 REGNUM, or -1 if there is no such register. */
2375 i386_next_regnum (int regnum
)
2377 /* GCC allocates the registers in the order:
2379 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2381 Since storing a variable in %esp doesn't make any sense we return
2382 -1 for %ebp and for %esp itself. */
2383 static int next_regnum
[] =
2385 I386_EDX_REGNUM
, /* Slot for %eax. */
2386 I386_EBX_REGNUM
, /* Slot for %ecx. */
2387 I386_ECX_REGNUM
, /* Slot for %edx. */
2388 I386_ESI_REGNUM
, /* Slot for %ebx. */
2389 -1, -1, /* Slots for %esp and %ebp. */
2390 I386_EDI_REGNUM
, /* Slot for %esi. */
2391 I386_EBP_REGNUM
/* Slot for %edi. */
2394 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2395 return next_regnum
[regnum
];
2400 /* Return nonzero if a value of type TYPE stored in register REGNUM
2401 needs any special handling. */
2404 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2406 int len
= TYPE_LENGTH (type
);
2408 /* Values may be spread across multiple registers. Most debugging
2409 formats aren't expressive enough to specify the locations, so
2410 some heuristics is involved. Right now we only handle types that
2411 have a length that is a multiple of the word size, since GCC
2412 doesn't seem to put any other types into registers. */
2413 if (len
> 4 && len
% 4 == 0)
2415 int last_regnum
= regnum
;
2419 last_regnum
= i386_next_regnum (last_regnum
);
2423 if (last_regnum
!= -1)
2427 return i387_convert_register_p (gdbarch
, regnum
, type
);
2430 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2431 return its contents in TO. */
2434 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2435 struct type
*type
, gdb_byte
*to
)
2437 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2438 int len
= TYPE_LENGTH (type
);
2440 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2441 available in FRAME (i.e. if it wasn't saved)? */
2443 if (i386_fp_regnum_p (gdbarch
, regnum
))
2445 i387_register_to_value (frame
, regnum
, type
, to
);
2449 /* Read a value spread across multiple registers. */
2451 gdb_assert (len
> 4 && len
% 4 == 0);
2455 gdb_assert (regnum
!= -1);
2456 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2458 get_frame_register (frame
, regnum
, to
);
2459 regnum
= i386_next_regnum (regnum
);
2465 /* Write the contents FROM of a value of type TYPE into register
2466 REGNUM in frame FRAME. */
2469 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2470 struct type
*type
, const gdb_byte
*from
)
2472 int len
= TYPE_LENGTH (type
);
2474 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2476 i387_value_to_register (frame
, regnum
, type
, from
);
2480 /* Write a value spread across multiple registers. */
2482 gdb_assert (len
> 4 && len
% 4 == 0);
2486 gdb_assert (regnum
!= -1);
2487 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2489 put_frame_register (frame
, regnum
, from
);
2490 regnum
= i386_next_regnum (regnum
);
2496 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2497 in the general-purpose register set REGSET to register cache
2498 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2501 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2502 int regnum
, const void *gregs
, size_t len
)
2504 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2505 const gdb_byte
*regs
= gregs
;
2508 gdb_assert (len
== tdep
->sizeof_gregset
);
2510 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2512 if ((regnum
== i
|| regnum
== -1)
2513 && tdep
->gregset_reg_offset
[i
] != -1)
2514 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2518 /* Collect register REGNUM from the register cache REGCACHE and store
2519 it in the buffer specified by GREGS and LEN as described by the
2520 general-purpose register set REGSET. If REGNUM is -1, do this for
2521 all registers in REGSET. */
2524 i386_collect_gregset (const struct regset
*regset
,
2525 const struct regcache
*regcache
,
2526 int regnum
, void *gregs
, size_t len
)
2528 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2529 gdb_byte
*regs
= gregs
;
2532 gdb_assert (len
== tdep
->sizeof_gregset
);
2534 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2536 if ((regnum
== i
|| regnum
== -1)
2537 && tdep
->gregset_reg_offset
[i
] != -1)
2538 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2542 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2543 in the floating-point register set REGSET to register cache
2544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2547 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2548 int regnum
, const void *fpregs
, size_t len
)
2550 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2552 if (len
== I387_SIZEOF_FXSAVE
)
2554 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2558 gdb_assert (len
== tdep
->sizeof_fpregset
);
2559 i387_supply_fsave (regcache
, regnum
, fpregs
);
2562 /* Collect register REGNUM from the register cache REGCACHE and store
2563 it in the buffer specified by FPREGS and LEN as described by the
2564 floating-point register set REGSET. If REGNUM is -1, do this for
2565 all registers in REGSET. */
2568 i386_collect_fpregset (const struct regset
*regset
,
2569 const struct regcache
*regcache
,
2570 int regnum
, void *fpregs
, size_t len
)
2572 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2574 if (len
== I387_SIZEOF_FXSAVE
)
2576 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2580 gdb_assert (len
== tdep
->sizeof_fpregset
);
2581 i387_collect_fsave (regcache
, regnum
, fpregs
);
2584 /* Return the appropriate register set for the core section identified
2585 by SECT_NAME and SECT_SIZE. */
2587 const struct regset
*
2588 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2589 const char *sect_name
, size_t sect_size
)
2591 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2593 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2595 if (tdep
->gregset
== NULL
)
2596 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2597 i386_collect_gregset
);
2598 return tdep
->gregset
;
2601 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2602 || (strcmp (sect_name
, ".reg-xfp") == 0
2603 && sect_size
== I387_SIZEOF_FXSAVE
))
2605 if (tdep
->fpregset
== NULL
)
2606 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2607 i386_collect_fpregset
);
2608 return tdep
->fpregset
;
2615 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2618 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2619 CORE_ADDR pc
, char *name
)
2621 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2622 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2625 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2627 unsigned long indirect
=
2628 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2629 struct minimal_symbol
*indsym
=
2630 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2631 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2635 if (strncmp (symname
, "__imp_", 6) == 0
2636 || strncmp (symname
, "_imp_", 5) == 0)
2638 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2641 return 0; /* Not a trampoline. */
2645 /* Return whether the THIS_FRAME corresponds to a sigtramp
2649 i386_sigtramp_p (struct frame_info
*this_frame
)
2651 CORE_ADDR pc
= get_frame_pc (this_frame
);
2654 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2655 return (name
&& strcmp ("_sigtramp", name
) == 0);
2659 /* We have two flavours of disassembly. The machinery on this page
2660 deals with switching between those. */
2663 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2665 gdb_assert (disassembly_flavor
== att_flavor
2666 || disassembly_flavor
== intel_flavor
);
2668 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2669 constified, cast to prevent a compiler warning. */
2670 info
->disassembler_options
= (char *) disassembly_flavor
;
2672 return print_insn_i386 (pc
, info
);
2676 /* There are a few i386 architecture variants that differ only
2677 slightly from the generic i386 target. For now, we don't give them
2678 their own source file, but include them here. As a consequence,
2679 they'll always be included. */
2681 /* System V Release 4 (SVR4). */
2683 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2687 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2689 CORE_ADDR pc
= get_frame_pc (this_frame
);
2692 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2693 currently unknown. */
2694 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2695 return (name
&& (strcmp ("_sigreturn", name
) == 0
2696 || strcmp ("_sigacthandler", name
) == 0
2697 || strcmp ("sigvechandler", name
) == 0));
2700 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2701 address of the associated sigcontext (ucontext) structure. */
2704 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2706 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2707 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2711 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2712 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2714 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2721 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2723 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2724 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2727 /* System V Release 4 (SVR4). */
2730 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2734 /* System V Release 4 uses ELF. */
2735 i386_elf_init_abi (info
, gdbarch
);
2737 /* System V Release 4 has shared libraries. */
2738 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2740 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2741 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2742 tdep
->sc_pc_offset
= 36 + 14 * 4;
2743 tdep
->sc_sp_offset
= 36 + 17 * 4;
2745 tdep
->jb_pc_offset
= 20;
2751 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2755 /* DJGPP doesn't have any special frames for signal handlers. */
2756 tdep
->sigtramp_p
= NULL
;
2758 tdep
->jb_pc_offset
= 36;
2760 /* DJGPP does not support the SSE registers. */
2761 tdep
->num_xmm_regs
= 0;
2762 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I387_NUM_REGS
);
2764 /* Native compiler is GCC, which uses the SVR4 register numbering
2765 even in COFF and STABS. See the comment in i386_gdbarch_init,
2766 before the calls to set_gdbarch_stab_reg_to_regnum and
2767 set_gdbarch_sdb_reg_to_regnum. */
2768 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2769 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2773 /* i386 register groups. In addition to the normal groups, add "mmx"
2776 static struct reggroup
*i386_sse_reggroup
;
2777 static struct reggroup
*i386_mmx_reggroup
;
2780 i386_init_reggroups (void)
2782 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2783 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2787 i386_add_reggroups (struct gdbarch
*gdbarch
)
2789 reggroup_add (gdbarch
, i386_sse_reggroup
);
2790 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2791 reggroup_add (gdbarch
, general_reggroup
);
2792 reggroup_add (gdbarch
, float_reggroup
);
2793 reggroup_add (gdbarch
, all_reggroup
);
2794 reggroup_add (gdbarch
, save_reggroup
);
2795 reggroup_add (gdbarch
, restore_reggroup
);
2796 reggroup_add (gdbarch
, vector_reggroup
);
2797 reggroup_add (gdbarch
, system_reggroup
);
2801 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2802 struct reggroup
*group
)
2804 int sse_regnum_p
, fp_regnum_p
, mmx_regnum_p
, byte_regnum_p
,
2805 word_regnum_p
, dword_regnum_p
;
2807 /* Don't include pseudo registers, except for MMX, in any register
2809 byte_regnum_p
= i386_byte_regnum_p (gdbarch
, regnum
);
2813 word_regnum_p
= i386_word_regnum_p (gdbarch
, regnum
);
2817 dword_regnum_p
= i386_dword_regnum_p (gdbarch
, regnum
);
2821 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
2822 if (group
== i386_mmx_reggroup
)
2823 return mmx_regnum_p
;
2825 sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2826 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2827 if (group
== i386_sse_reggroup
)
2828 return sse_regnum_p
;
2829 if (group
== vector_reggroup
)
2830 return mmx_regnum_p
|| sse_regnum_p
;
2832 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2833 || i386_fpc_regnum_p (gdbarch
, regnum
));
2834 if (group
== float_reggroup
)
2837 if (group
== general_reggroup
)
2838 return (!fp_regnum_p
2843 && !dword_regnum_p
);
2845 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2849 /* Get the ARGIth function argument for the current function. */
2852 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2855 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2856 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2857 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2858 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2862 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2864 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2866 /* On i386, breakpoint is exactly 1 byte long, so we just
2867 adjust the PC in the regcache. */
2869 regcache_write_pc (regcache
, current_pc
);
2873 #define PREFIX_REPZ 0x01
2874 #define PREFIX_REPNZ 0x02
2875 #define PREFIX_LOCK 0x04
2876 #define PREFIX_DATA 0x08
2877 #define PREFIX_ADDR 0x10
2889 /* i386 arith/logic operations */
2902 struct i386_record_s
2904 struct gdbarch
*gdbarch
;
2905 struct regcache
*regcache
;
2906 CORE_ADDR orig_addr
;
2912 uint8_t mod
, reg
, rm
;
2921 /* Parse "modrm" part in current memory address that irp->addr point to
2922 Return -1 if something wrong. */
2925 i386_record_modrm (struct i386_record_s
*irp
)
2927 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2929 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2932 printf_unfiltered (_("Process record: error reading memory at "
2933 "addr %s len = 1.\n"),
2934 paddress (gdbarch
, irp
->addr
));
2938 irp
->mod
= (irp
->modrm
>> 6) & 3;
2939 irp
->reg
= (irp
->modrm
>> 3) & 7;
2940 irp
->rm
= irp
->modrm
& 7;
2945 /* Get the memory address that current instruction write to and set it to
2946 the argument "addr".
2947 Return -1 if something wrong. */
2950 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2952 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2953 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2965 uint8_t base
= irp
->rm
;
2970 if (target_read_memory (irp
->addr
, &byte
, 1))
2973 printf_unfiltered (_("Process record: error reading memory "
2974 "at addr %s len = 1.\n"),
2975 paddress (gdbarch
, irp
->addr
));
2979 scale
= (byte
>> 6) & 3;
2980 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
2988 if ((base
& 7) == 5)
2991 if (target_read_memory (irp
->addr
, buf
, 4))
2994 printf_unfiltered (_("Process record: error reading "
2995 "memory at addr %s len = 4.\n"),
2996 paddress (gdbarch
, irp
->addr
));
3000 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3001 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3002 *addr
+= irp
->addr
+ irp
->rip_offset
;
3006 if (target_read_memory (irp
->addr
, buf
, 1))
3009 printf_unfiltered (_("Process record: error reading memory "
3010 "at addr %s len = 1.\n"),
3011 paddress (gdbarch
, irp
->addr
));
3015 *addr
= (int8_t) buf
[0];
3018 if (target_read_memory (irp
->addr
, buf
, 4))
3021 printf_unfiltered (_("Process record: error reading memory "
3022 "at addr %s len = 4.\n"),
3023 paddress (gdbarch
, irp
->addr
));
3026 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3034 if (base
== 4 && irp
->popl_esp_hack
)
3035 *addr
+= irp
->popl_esp_hack
;
3036 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3039 if (irp
->aflag
== 2)
3044 *addr
= (uint32_t) (offset64
+ *addr
);
3046 if (havesib
&& (index
!= 4 || scale
!= 0))
3048 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3050 if (irp
->aflag
== 2)
3051 *addr
+= offset64
<< scale
;
3053 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3064 if (target_read_memory (irp
->addr
, buf
, 2))
3067 printf_unfiltered (_("Process record: error reading "
3068 "memory at addr %s len = 2.\n"),
3069 paddress (gdbarch
, irp
->addr
));
3073 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3079 if (target_read_memory (irp
->addr
, buf
, 1))
3082 printf_unfiltered (_("Process record: error reading memory "
3083 "at addr %s len = 1.\n"),
3084 paddress (gdbarch
, irp
->addr
));
3088 *addr
= (int8_t) buf
[0];
3091 if (target_read_memory (irp
->addr
, buf
, 2))
3094 printf_unfiltered (_("Process record: error reading memory "
3095 "at addr %s len = 2.\n"),
3096 paddress (gdbarch
, irp
->addr
));
3100 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3107 regcache_raw_read_unsigned (irp
->regcache
,
3108 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3110 *addr
= (uint32_t) (*addr
+ offset64
);
3111 regcache_raw_read_unsigned (irp
->regcache
,
3112 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3114 *addr
= (uint32_t) (*addr
+ offset64
);
3117 regcache_raw_read_unsigned (irp
->regcache
,
3118 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3120 *addr
= (uint32_t) (*addr
+ offset64
);
3121 regcache_raw_read_unsigned (irp
->regcache
,
3122 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3124 *addr
= (uint32_t) (*addr
+ offset64
);
3127 regcache_raw_read_unsigned (irp
->regcache
,
3128 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3130 *addr
= (uint32_t) (*addr
+ offset64
);
3131 regcache_raw_read_unsigned (irp
->regcache
,
3132 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3134 *addr
= (uint32_t) (*addr
+ offset64
);
3137 regcache_raw_read_unsigned (irp
->regcache
,
3138 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3140 *addr
= (uint32_t) (*addr
+ offset64
);
3141 regcache_raw_read_unsigned (irp
->regcache
,
3142 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3144 *addr
= (uint32_t) (*addr
+ offset64
);
3147 regcache_raw_read_unsigned (irp
->regcache
,
3148 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3150 *addr
= (uint32_t) (*addr
+ offset64
);
3153 regcache_raw_read_unsigned (irp
->regcache
,
3154 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3156 *addr
= (uint32_t) (*addr
+ offset64
);
3159 regcache_raw_read_unsigned (irp
->regcache
,
3160 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3162 *addr
= (uint32_t) (*addr
+ offset64
);
3165 regcache_raw_read_unsigned (irp
->regcache
,
3166 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3168 *addr
= (uint32_t) (*addr
+ offset64
);
3178 /* Record the value of the memory that willbe changed in current instruction
3179 to "record_arch_list".
3180 Return -1 if something wrong. */
3183 i386_record_lea_modrm (struct i386_record_s
*irp
)
3185 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3188 if (irp
->override
>= 0)
3190 warning (_("Process record ignores the memory change "
3191 "of instruction at address %s because it "
3192 "can't get the value of the segment register."),
3193 paddress (gdbarch
, irp
->orig_addr
));
3197 if (i386_record_lea_modrm_addr (irp
, &addr
))
3200 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3206 /* Record the push operation to "record_arch_list".
3207 Return -1 if something wrong. */
3210 i386_record_push (struct i386_record_s
*irp
, int size
)
3214 if (record_arch_list_add_reg (irp
->regcache
,
3215 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3217 regcache_raw_read_unsigned (irp
->regcache
,
3218 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3220 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3227 /* Defines contents to record. */
3228 #define I386_SAVE_FPU_REGS 0xfffd
3229 #define I386_SAVE_FPU_ENV 0xfffe
3230 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3232 /* Record the value of floating point registers which will be changed by the
3233 current instruction to "record_arch_list". Return -1 if something is wrong.
3236 static int i386_record_floats (struct gdbarch
*gdbarch
,
3237 struct i386_record_s
*ir
,
3240 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3243 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3244 happen. Currently we store st0-st7 registers, but we need not store all
3245 registers all the time, in future we use ftag register and record only
3246 those who are not marked as an empty. */
3248 if (I386_SAVE_FPU_REGS
== iregnum
)
3250 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3252 if (record_arch_list_add_reg (ir
->regcache
, i
))
3256 else if (I386_SAVE_FPU_ENV
== iregnum
)
3258 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3260 if (record_arch_list_add_reg (ir
->regcache
, i
))
3264 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3266 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3268 if (record_arch_list_add_reg (ir
->regcache
, i
))
3272 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3273 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3275 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3280 /* Parameter error. */
3283 if(I386_SAVE_FPU_ENV
!= iregnum
)
3285 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3287 if (record_arch_list_add_reg (ir
->regcache
, i
))
3294 /* Parse the current instruction and record the values of the registers and
3295 memory that will be changed in current instruction to "record_arch_list".
3296 Return -1 if something wrong. */
3298 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3299 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3302 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3303 CORE_ADDR input_addr
)
3305 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3311 gdb_byte buf
[MAX_REGISTER_SIZE
];
3312 struct i386_record_s ir
;
3313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3318 memset (&ir
, 0, sizeof (struct i386_record_s
));
3319 ir
.regcache
= regcache
;
3320 ir
.addr
= input_addr
;
3321 ir
.orig_addr
= input_addr
;
3325 ir
.popl_esp_hack
= 0;
3326 ir
.regmap
= tdep
->record_regmap
;
3327 ir
.gdbarch
= gdbarch
;
3329 if (record_debug
> 1)
3330 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3332 paddress (gdbarch
, ir
.addr
));
3337 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3340 printf_unfiltered (_("Process record: error reading memory at "
3341 "addr %s len = 1.\n"),
3342 paddress (gdbarch
, ir
.addr
));
3346 switch (opcode8
) /* Instruction prefixes */
3348 case REPE_PREFIX_OPCODE
:
3349 prefixes
|= PREFIX_REPZ
;
3351 case REPNE_PREFIX_OPCODE
:
3352 prefixes
|= PREFIX_REPNZ
;
3354 case LOCK_PREFIX_OPCODE
:
3355 prefixes
|= PREFIX_LOCK
;
3357 case CS_PREFIX_OPCODE
:
3358 ir
.override
= X86_RECORD_CS_REGNUM
;
3360 case SS_PREFIX_OPCODE
:
3361 ir
.override
= X86_RECORD_SS_REGNUM
;
3363 case DS_PREFIX_OPCODE
:
3364 ir
.override
= X86_RECORD_DS_REGNUM
;
3366 case ES_PREFIX_OPCODE
:
3367 ir
.override
= X86_RECORD_ES_REGNUM
;
3369 case FS_PREFIX_OPCODE
:
3370 ir
.override
= X86_RECORD_FS_REGNUM
;
3372 case GS_PREFIX_OPCODE
:
3373 ir
.override
= X86_RECORD_GS_REGNUM
;
3375 case DATA_PREFIX_OPCODE
:
3376 prefixes
|= PREFIX_DATA
;
3378 case ADDR_PREFIX_OPCODE
:
3379 prefixes
|= PREFIX_ADDR
;
3381 case 0x40: /* i386 inc %eax */
3382 case 0x41: /* i386 inc %ecx */
3383 case 0x42: /* i386 inc %edx */
3384 case 0x43: /* i386 inc %ebx */
3385 case 0x44: /* i386 inc %esp */
3386 case 0x45: /* i386 inc %ebp */
3387 case 0x46: /* i386 inc %esi */
3388 case 0x47: /* i386 inc %edi */
3389 case 0x48: /* i386 dec %eax */
3390 case 0x49: /* i386 dec %ecx */
3391 case 0x4a: /* i386 dec %edx */
3392 case 0x4b: /* i386 dec %ebx */
3393 case 0x4c: /* i386 dec %esp */
3394 case 0x4d: /* i386 dec %ebp */
3395 case 0x4e: /* i386 dec %esi */
3396 case 0x4f: /* i386 dec %edi */
3397 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3401 rex_w
= (opcode8
>> 3) & 1;
3402 rex_r
= (opcode8
& 0x4) << 1;
3403 ir
.rex_x
= (opcode8
& 0x2) << 2;
3404 ir
.rex_b
= (opcode8
& 0x1) << 3;
3406 else /* 32 bit target */
3415 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3421 if (prefixes
& PREFIX_DATA
)
3424 if (prefixes
& PREFIX_ADDR
)
3426 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3429 /* now check op code */
3430 opcode
= (uint32_t) opcode8
;
3435 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3438 printf_unfiltered (_("Process record: error reading memory at "
3439 "addr %s len = 1.\n"),
3440 paddress (gdbarch
, ir
.addr
));
3444 opcode
= (uint32_t) opcode8
| 0x0f00;
3448 case 0x00: /* arith & logic */
3496 if (((opcode
>> 3) & 7) != OP_CMPL
)
3498 if ((opcode
& 1) == 0)
3501 ir
.ot
= ir
.dflag
+ OT_WORD
;
3503 switch ((opcode
>> 1) & 3)
3505 case 0: /* OP Ev, Gv */
3506 if (i386_record_modrm (&ir
))
3510 if (i386_record_lea_modrm (&ir
))
3516 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3518 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3521 case 1: /* OP Gv, Ev */
3522 if (i386_record_modrm (&ir
))
3525 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3527 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3529 case 2: /* OP A, Iv */
3530 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3537 case 0x80: /* GRP1 */
3541 if (i386_record_modrm (&ir
))
3544 if (ir
.reg
!= OP_CMPL
)
3546 if ((opcode
& 1) == 0)
3549 ir
.ot
= ir
.dflag
+ OT_WORD
;
3556 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3557 if (i386_record_lea_modrm (&ir
))
3561 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3563 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3566 case 0x40: /* inc */
3575 case 0x48: /* dec */
3584 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3588 case 0xf6: /* GRP3 */
3590 if ((opcode
& 1) == 0)
3593 ir
.ot
= ir
.dflag
+ OT_WORD
;
3594 if (i386_record_modrm (&ir
))
3597 if (ir
.mod
!= 3 && ir
.reg
== 0)
3598 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3609 if (i386_record_lea_modrm (&ir
))
3615 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3617 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3619 if (ir
.reg
== 3) /* neg */
3620 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3626 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3627 if (ir
.ot
!= OT_BYTE
)
3628 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3633 opcode
= opcode
<< 8 | ir
.modrm
;
3639 case 0xfe: /* GRP4 */
3640 case 0xff: /* GRP5 */
3641 if (i386_record_modrm (&ir
))
3643 if (ir
.reg
>= 2 && opcode
== 0xfe)
3646 opcode
= opcode
<< 8 | ir
.modrm
;
3653 if ((opcode
& 1) == 0)
3656 ir
.ot
= ir
.dflag
+ OT_WORD
;
3659 if (i386_record_lea_modrm (&ir
))
3665 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3667 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3669 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3672 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3674 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3680 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3686 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3689 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3691 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3696 opcode
= opcode
<< 8 | ir
.modrm
;
3702 case 0x84: /* test */
3706 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3709 case 0x98: /* CWDE/CBW */
3710 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3713 case 0x99: /* CDQ/CWD */
3714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3715 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3718 case 0x0faf: /* imul */
3721 ir
.ot
= ir
.dflag
+ OT_WORD
;
3722 if (i386_record_modrm (&ir
))
3725 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3726 else if (opcode
== 0x6b)
3729 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3731 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3732 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3735 case 0x0fc0: /* xadd */
3737 if ((opcode
& 1) == 0)
3740 ir
.ot
= ir
.dflag
+ OT_WORD
;
3741 if (i386_record_modrm (&ir
))
3746 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3748 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3749 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3751 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3755 if (i386_record_lea_modrm (&ir
))
3757 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3759 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3764 case 0x0fb0: /* cmpxchg */
3766 if ((opcode
& 1) == 0)
3769 ir
.ot
= ir
.dflag
+ OT_WORD
;
3770 if (i386_record_modrm (&ir
))
3775 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3776 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3778 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3782 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3783 if (i386_record_lea_modrm (&ir
))
3786 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3789 case 0x0fc7: /* cmpxchg8b */
3790 if (i386_record_modrm (&ir
))
3795 opcode
= opcode
<< 8 | ir
.modrm
;
3798 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3800 if (i386_record_lea_modrm (&ir
))
3802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3805 case 0x50: /* push */
3815 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3817 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3821 case 0x06: /* push es */
3822 case 0x0e: /* push cs */
3823 case 0x16: /* push ss */
3824 case 0x1e: /* push ds */
3825 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3830 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3834 case 0x0fa0: /* push fs */
3835 case 0x0fa8: /* push gs */
3836 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3841 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3845 case 0x60: /* pusha */
3846 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3851 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3855 case 0x58: /* pop */
3863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3864 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3867 case 0x61: /* popa */
3868 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3873 for (regnum
= X86_RECORD_REAX_REGNUM
;
3874 regnum
<= X86_RECORD_REDI_REGNUM
;
3876 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
3879 case 0x8f: /* pop */
3880 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3881 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3883 ir
.ot
= ir
.dflag
+ OT_WORD
;
3884 if (i386_record_modrm (&ir
))
3887 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3890 ir
.popl_esp_hack
= 1 << ir
.ot
;
3891 if (i386_record_lea_modrm (&ir
))
3894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3897 case 0xc8: /* enter */
3898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3899 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3901 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3905 case 0xc9: /* leave */
3906 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3910 case 0x07: /* pop es */
3911 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3917 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3918 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3921 case 0x17: /* pop ss */
3922 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3928 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3932 case 0x1f: /* pop ds */
3933 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3938 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3943 case 0x0fa1: /* pop fs */
3944 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3949 case 0x0fa9: /* pop gs */
3950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3955 case 0x88: /* mov */
3959 if ((opcode
& 1) == 0)
3962 ir
.ot
= ir
.dflag
+ OT_WORD
;
3964 if (i386_record_modrm (&ir
))
3969 if (opcode
== 0xc6 || opcode
== 0xc7)
3970 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3971 if (i386_record_lea_modrm (&ir
))
3976 if (opcode
== 0xc6 || opcode
== 0xc7)
3978 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3980 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3984 case 0x8a: /* mov */
3986 if ((opcode
& 1) == 0)
3989 ir
.ot
= ir
.dflag
+ OT_WORD
;
3990 if (i386_record_modrm (&ir
))
3993 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3995 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3998 case 0x8c: /* mov seg */
3999 if (i386_record_modrm (&ir
))
4004 opcode
= opcode
<< 8 | ir
.modrm
;
4009 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4013 if (i386_record_lea_modrm (&ir
))
4018 case 0x8e: /* mov seg */
4019 if (i386_record_modrm (&ir
))
4024 regnum
= X86_RECORD_ES_REGNUM
;
4027 regnum
= X86_RECORD_SS_REGNUM
;
4030 regnum
= X86_RECORD_DS_REGNUM
;
4033 regnum
= X86_RECORD_FS_REGNUM
;
4036 regnum
= X86_RECORD_GS_REGNUM
;
4040 opcode
= opcode
<< 8 | ir
.modrm
;
4044 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4045 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4048 case 0x0fb6: /* movzbS */
4049 case 0x0fb7: /* movzwS */
4050 case 0x0fbe: /* movsbS */
4051 case 0x0fbf: /* movswS */
4052 if (i386_record_modrm (&ir
))
4054 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4057 case 0x8d: /* lea */
4058 if (i386_record_modrm (&ir
))
4063 opcode
= opcode
<< 8 | ir
.modrm
;
4068 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4070 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4073 case 0xa0: /* mov EAX */
4076 case 0xd7: /* xlat */
4077 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4080 case 0xa2: /* mov EAX */
4082 if (ir
.override
>= 0)
4084 warning (_("Process record ignores the memory change "
4085 "of instruction at address %s because "
4086 "it can't get the value of the segment "
4088 paddress (gdbarch
, ir
.orig_addr
));
4092 if ((opcode
& 1) == 0)
4095 ir
.ot
= ir
.dflag
+ OT_WORD
;
4098 if (target_read_memory (ir
.addr
, buf
, 8))
4101 printf_unfiltered (_("Process record: error reading "
4102 "memory at addr 0x%s len = 8.\n"),
4103 paddress (gdbarch
, ir
.addr
));
4107 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4111 if (target_read_memory (ir
.addr
, buf
, 4))
4114 printf_unfiltered (_("Process record: error reading "
4115 "memory at addr 0x%s len = 4.\n"),
4116 paddress (gdbarch
, ir
.addr
));
4120 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4124 if (target_read_memory (ir
.addr
, buf
, 2))
4127 printf_unfiltered (_("Process record: error reading "
4128 "memory at addr 0x%s len = 2.\n"),
4129 paddress (gdbarch
, ir
.addr
));
4133 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4135 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4140 case 0xb0: /* mov R, Ib */
4148 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4149 ? ((opcode
& 0x7) | ir
.rex_b
)
4150 : ((opcode
& 0x7) & 0x3));
4153 case 0xb8: /* mov R, Iv */
4161 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4164 case 0x91: /* xchg R, EAX */
4171 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4172 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4175 case 0x86: /* xchg Ev, Gv */
4177 if ((opcode
& 1) == 0)
4180 ir
.ot
= ir
.dflag
+ OT_WORD
;
4181 if (i386_record_modrm (&ir
))
4186 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4188 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4192 if (i386_record_lea_modrm (&ir
))
4196 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4198 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4201 case 0xc4: /* les Gv */
4202 case 0xc5: /* lds Gv */
4203 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4208 case 0x0fb2: /* lss Gv */
4209 case 0x0fb4: /* lfs Gv */
4210 case 0x0fb5: /* lgs Gv */
4211 if (i386_record_modrm (&ir
))
4219 opcode
= opcode
<< 8 | ir
.modrm
;
4224 case 0xc4: /* les Gv */
4225 regnum
= X86_RECORD_ES_REGNUM
;
4227 case 0xc5: /* lds Gv */
4228 regnum
= X86_RECORD_DS_REGNUM
;
4230 case 0x0fb2: /* lss Gv */
4231 regnum
= X86_RECORD_SS_REGNUM
;
4233 case 0x0fb4: /* lfs Gv */
4234 regnum
= X86_RECORD_FS_REGNUM
;
4236 case 0x0fb5: /* lgs Gv */
4237 regnum
= X86_RECORD_GS_REGNUM
;
4240 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4241 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4242 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4245 case 0xc0: /* shifts */
4251 if ((opcode
& 1) == 0)
4254 ir
.ot
= ir
.dflag
+ OT_WORD
;
4255 if (i386_record_modrm (&ir
))
4257 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4259 if (i386_record_lea_modrm (&ir
))
4265 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4267 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4276 if (i386_record_modrm (&ir
))
4280 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4285 if (i386_record_lea_modrm (&ir
))
4290 case 0xd8: /* Floats. */
4298 if (i386_record_modrm (&ir
))
4300 ir
.reg
|= ((opcode
& 7) << 3);
4306 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4314 /* For fcom, ficom nothing to do. */
4320 /* For fcomp, ficomp pop FPU stack, store all. */
4321 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4348 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4349 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4350 of code, always affects st(0) register. */
4351 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4375 /* Handling fld, fild. */
4376 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4380 switch (ir
.reg
>> 4)
4383 if (record_arch_list_add_mem (addr64
, 4))
4387 if (record_arch_list_add_mem (addr64
, 8))
4393 if (record_arch_list_add_mem (addr64
, 2))
4399 switch (ir
.reg
>> 4)
4402 if (record_arch_list_add_mem (addr64
, 4))
4404 if (3 == (ir
.reg
& 7))
4406 /* For fstp m32fp. */
4407 if (i386_record_floats (gdbarch
, &ir
,
4408 I386_SAVE_FPU_REGS
))
4413 if (record_arch_list_add_mem (addr64
, 4))
4415 if ((3 == (ir
.reg
& 7))
4416 || (5 == (ir
.reg
& 7))
4417 || (7 == (ir
.reg
& 7)))
4419 /* For fstp insn. */
4420 if (i386_record_floats (gdbarch
, &ir
,
4421 I386_SAVE_FPU_REGS
))
4426 if (record_arch_list_add_mem (addr64
, 8))
4428 if (3 == (ir
.reg
& 7))
4430 /* For fstp m64fp. */
4431 if (i386_record_floats (gdbarch
, &ir
,
4432 I386_SAVE_FPU_REGS
))
4437 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4439 /* For fistp, fbld, fild, fbstp. */
4440 if (i386_record_floats (gdbarch
, &ir
,
4441 I386_SAVE_FPU_REGS
))
4446 if (record_arch_list_add_mem (addr64
, 2))
4455 if (i386_record_floats (gdbarch
, &ir
,
4456 I386_SAVE_FPU_ENV_REG_STACK
))
4461 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4466 if (i386_record_floats (gdbarch
, &ir
,
4467 I386_SAVE_FPU_ENV_REG_STACK
))
4473 if (record_arch_list_add_mem (addr64
, 28))
4478 if (record_arch_list_add_mem (addr64
, 14))
4484 if (record_arch_list_add_mem (addr64
, 2))
4486 /* Insn fstp, fbstp. */
4487 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4492 if (record_arch_list_add_mem (addr64
, 10))
4498 if (record_arch_list_add_mem (addr64
, 28))
4504 if (record_arch_list_add_mem (addr64
, 14))
4508 if (record_arch_list_add_mem (addr64
, 80))
4511 if (i386_record_floats (gdbarch
, &ir
,
4512 I386_SAVE_FPU_ENV_REG_STACK
))
4516 if (record_arch_list_add_mem (addr64
, 8))
4519 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4524 opcode
= opcode
<< 8 | ir
.modrm
;
4529 /* Opcode is an extension of modR/M byte. */
4535 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4539 if (0x0c == (ir
.modrm
>> 4))
4541 if ((ir
.modrm
& 0x0f) <= 7)
4543 if (i386_record_floats (gdbarch
, &ir
,
4544 I386_SAVE_FPU_REGS
))
4549 if (i386_record_floats (gdbarch
, &ir
,
4550 I387_ST0_REGNUM (tdep
)))
4552 /* If only st(0) is changing, then we have already
4554 if ((ir
.modrm
& 0x0f) - 0x08)
4556 if (i386_record_floats (gdbarch
, &ir
,
4557 I387_ST0_REGNUM (tdep
) +
4558 ((ir
.modrm
& 0x0f) - 0x08)))
4576 if (i386_record_floats (gdbarch
, &ir
,
4577 I387_ST0_REGNUM (tdep
)))
4595 if (i386_record_floats (gdbarch
, &ir
,
4596 I386_SAVE_FPU_REGS
))
4600 if (i386_record_floats (gdbarch
, &ir
,
4601 I387_ST0_REGNUM (tdep
)))
4603 if (i386_record_floats (gdbarch
, &ir
,
4604 I387_ST0_REGNUM (tdep
) + 1))
4611 if (0xe9 == ir
.modrm
)
4613 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4616 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4618 if (i386_record_floats (gdbarch
, &ir
,
4619 I387_ST0_REGNUM (tdep
)))
4621 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4623 if (i386_record_floats (gdbarch
, &ir
,
4624 I387_ST0_REGNUM (tdep
) +
4628 else if ((ir
.modrm
& 0x0f) - 0x08)
4630 if (i386_record_floats (gdbarch
, &ir
,
4631 I387_ST0_REGNUM (tdep
) +
4632 ((ir
.modrm
& 0x0f) - 0x08)))
4638 if (0xe3 == ir
.modrm
)
4640 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4643 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4645 if (i386_record_floats (gdbarch
, &ir
,
4646 I387_ST0_REGNUM (tdep
)))
4648 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4650 if (i386_record_floats (gdbarch
, &ir
,
4651 I387_ST0_REGNUM (tdep
) +
4655 else if ((ir
.modrm
& 0x0f) - 0x08)
4657 if (i386_record_floats (gdbarch
, &ir
,
4658 I387_ST0_REGNUM (tdep
) +
4659 ((ir
.modrm
& 0x0f) - 0x08)))
4665 if ((0x0c == ir
.modrm
>> 4)
4666 || (0x0d == ir
.modrm
>> 4)
4667 || (0x0f == ir
.modrm
>> 4))
4669 if ((ir
.modrm
& 0x0f) <= 7)
4671 if (i386_record_floats (gdbarch
, &ir
,
4672 I387_ST0_REGNUM (tdep
) +
4678 if (i386_record_floats (gdbarch
, &ir
,
4679 I387_ST0_REGNUM (tdep
) +
4680 ((ir
.modrm
& 0x0f) - 0x08)))
4686 if (0x0c == ir
.modrm
>> 4)
4688 if (i386_record_floats (gdbarch
, &ir
,
4689 I387_FTAG_REGNUM (tdep
)))
4692 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4694 if ((ir
.modrm
& 0x0f) <= 7)
4696 if (i386_record_floats (gdbarch
, &ir
,
4697 I387_ST0_REGNUM (tdep
) +
4703 if (i386_record_floats (gdbarch
, &ir
,
4704 I386_SAVE_FPU_REGS
))
4710 if ((0x0c == ir
.modrm
>> 4)
4711 || (0x0e == ir
.modrm
>> 4)
4712 || (0x0f == ir
.modrm
>> 4)
4713 || (0xd9 == ir
.modrm
))
4715 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4720 if (0xe0 == ir
.modrm
)
4722 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4725 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4727 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4735 case 0xa4: /* movsS */
4737 case 0xaa: /* stosS */
4739 case 0x6c: /* insS */
4741 regcache_raw_read_unsigned (ir
.regcache
,
4742 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4748 if ((opcode
& 1) == 0)
4751 ir
.ot
= ir
.dflag
+ OT_WORD
;
4752 regcache_raw_read_unsigned (ir
.regcache
,
4753 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4756 regcache_raw_read_unsigned (ir
.regcache
,
4757 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4759 regcache_raw_read_unsigned (ir
.regcache
,
4760 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4762 if (ir
.aflag
&& (es
!= ds
))
4764 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4765 warning (_("Process record ignores the memory "
4766 "change of instruction at address %s "
4767 "because it can't get the value of the "
4768 "ES segment register."),
4769 paddress (gdbarch
, ir
.orig_addr
));
4773 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4777 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4778 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4779 if (opcode
== 0xa4 || opcode
== 0xa5)
4780 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4782 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4786 case 0xa6: /* cmpsS */
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4789 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4790 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4791 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4795 case 0xac: /* lodsS */
4797 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4798 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4799 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4801 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4804 case 0xae: /* scasS */
4806 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4807 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4812 case 0x6e: /* outsS */
4814 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4815 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4820 case 0xe4: /* port I/O */
4824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4825 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4835 case 0xc2: /* ret im */
4836 case 0xc3: /* ret */
4837 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4838 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4841 case 0xca: /* lret im */
4842 case 0xcb: /* lret */
4843 case 0xcf: /* iret */
4844 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4845 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4849 case 0xe8: /* call im */
4850 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4852 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4856 case 0x9a: /* lcall im */
4857 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4862 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4863 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4867 case 0xe9: /* jmp im */
4868 case 0xea: /* ljmp im */
4869 case 0xeb: /* jmp Jb */
4870 case 0x70: /* jcc Jb */
4886 case 0x0f80: /* jcc Jv */
4904 case 0x0f90: /* setcc Gv */
4920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4922 if (i386_record_modrm (&ir
))
4925 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4929 if (i386_record_lea_modrm (&ir
))
4934 case 0x0f40: /* cmov Gv, Ev */
4950 if (i386_record_modrm (&ir
))
4953 if (ir
.dflag
== OT_BYTE
)
4955 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4959 case 0x9c: /* pushf */
4960 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4961 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4963 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4967 case 0x9d: /* popf */
4968 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4969 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4972 case 0x9e: /* sahf */
4973 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4978 case 0xf5: /* cmc */
4979 case 0xf8: /* clc */
4980 case 0xf9: /* stc */
4981 case 0xfc: /* cld */
4982 case 0xfd: /* std */
4983 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4986 case 0x9f: /* lahf */
4987 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4996 /* bit operations */
4997 case 0x0fba: /* bt/bts/btr/btc Gv, im */
4998 ir
.ot
= ir
.dflag
+ OT_WORD
;
4999 if (i386_record_modrm (&ir
))
5004 opcode
= opcode
<< 8 | ir
.modrm
;
5010 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5013 if (i386_record_lea_modrm (&ir
))
5017 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5020 case 0x0fa3: /* bt Gv, Ev */
5021 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5024 case 0x0fab: /* bts */
5025 case 0x0fb3: /* btr */
5026 case 0x0fbb: /* btc */
5027 ir
.ot
= ir
.dflag
+ OT_WORD
;
5028 if (i386_record_modrm (&ir
))
5031 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5035 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5037 regcache_raw_read_unsigned (ir
.regcache
,
5038 ir
.regmap
[ir
.reg
| rex_r
],
5043 addr64
+= ((int16_t) addr
>> 4) << 4;
5046 addr64
+= ((int32_t) addr
>> 5) << 5;
5049 addr64
+= ((int64_t) addr
>> 6) << 6;
5052 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5054 if (i386_record_lea_modrm (&ir
))
5057 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5060 case 0x0fbc: /* bsf */
5061 case 0x0fbd: /* bsr */
5062 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5067 case 0x27: /* daa */
5068 case 0x2f: /* das */
5069 case 0x37: /* aaa */
5070 case 0x3f: /* aas */
5071 case 0xd4: /* aam */
5072 case 0xd5: /* aad */
5073 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5078 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5079 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5083 case 0x90: /* nop */
5084 if (prefixes
& PREFIX_LOCK
)
5091 case 0x9b: /* fwait */
5092 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5095 printf_unfiltered (_("Process record: error reading memory at "
5096 "addr 0x%s len = 1.\n"),
5097 paddress (gdbarch
, ir
.addr
));
5100 opcode
= (uint32_t) opcode8
;
5106 case 0xcc: /* int3 */
5107 printf_unfiltered (_("Process record does not support instruction "
5114 case 0xcd: /* int */
5118 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5121 printf_unfiltered (_("Process record: error reading memory "
5122 "at addr %s len = 1.\n"),
5123 paddress (gdbarch
, ir
.addr
));
5127 if (interrupt
!= 0x80
5128 || tdep
->i386_intx80_record
== NULL
)
5130 printf_unfiltered (_("Process record does not support "
5131 "instruction int 0x%02x.\n"),
5136 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5143 case 0xce: /* into */
5144 printf_unfiltered (_("Process record does not support "
5145 "instruction into.\n"));
5150 case 0xfa: /* cli */
5151 case 0xfb: /* sti */
5154 case 0x62: /* bound */
5155 printf_unfiltered (_("Process record does not support "
5156 "instruction bound.\n"));
5161 case 0x0fc8: /* bswap reg */
5169 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5172 case 0xd6: /* salc */
5173 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5179 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5182 case 0xe0: /* loopnz */
5183 case 0xe1: /* loopz */
5184 case 0xe2: /* loop */
5185 case 0xe3: /* jecxz */
5186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5187 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5190 case 0x0f30: /* wrmsr */
5191 printf_unfiltered (_("Process record does not support "
5192 "instruction wrmsr.\n"));
5197 case 0x0f32: /* rdmsr */
5198 printf_unfiltered (_("Process record does not support "
5199 "instruction rdmsr.\n"));
5204 case 0x0f31: /* rdtsc */
5205 printf_unfiltered (_("Process record does not support "
5206 "instruction rdtsc.\n"));
5211 case 0x0f34: /* sysenter */
5214 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5219 if (tdep
->i386_sysenter_record
== NULL
)
5221 printf_unfiltered (_("Process record does not support "
5222 "instruction sysenter.\n"));
5226 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5232 case 0x0f35: /* sysexit */
5233 printf_unfiltered (_("Process record does not support "
5234 "instruction sysexit.\n"));
5239 case 0x0f05: /* syscall */
5242 if (tdep
->i386_syscall_record
== NULL
)
5244 printf_unfiltered (_("Process record does not support "
5245 "instruction syscall.\n"));
5249 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5255 case 0x0f07: /* sysret */
5256 printf_unfiltered (_("Process record does not support "
5257 "instruction sysret.\n"));
5262 case 0x0fa2: /* cpuid */
5263 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5264 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5265 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5269 case 0xf4: /* hlt */
5270 printf_unfiltered (_("Process record does not support "
5271 "instruction hlt.\n"));
5277 if (i386_record_modrm (&ir
))
5284 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5288 if (i386_record_lea_modrm (&ir
))
5297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5301 opcode
= opcode
<< 8 | ir
.modrm
;
5308 if (i386_record_modrm (&ir
))
5319 opcode
= opcode
<< 8 | ir
.modrm
;
5322 if (ir
.override
>= 0)
5324 warning (_("Process record ignores the memory "
5325 "change of instruction at "
5326 "address %s because it can't get "
5327 "the value of the segment "
5329 paddress (gdbarch
, ir
.orig_addr
));
5333 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5335 if (record_arch_list_add_mem (addr64
, 2))
5338 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5340 if (record_arch_list_add_mem (addr64
, 8))
5345 if (record_arch_list_add_mem (addr64
, 4))
5356 case 0: /* monitor */
5359 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5363 opcode
= opcode
<< 8 | ir
.modrm
;
5371 if (ir
.override
>= 0)
5373 warning (_("Process record ignores the memory "
5374 "change of instruction at "
5375 "address %s because it can't get "
5376 "the value of the segment "
5378 paddress (gdbarch
, ir
.orig_addr
));
5384 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5386 if (record_arch_list_add_mem (addr64
, 2))
5389 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5391 if (record_arch_list_add_mem (addr64
, 8))
5396 if (record_arch_list_add_mem (addr64
, 4))
5408 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5413 else if (ir
.rm
== 1)
5420 opcode
= opcode
<< 8 | ir
.modrm
;
5427 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5433 if (i386_record_lea_modrm (&ir
))
5436 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5439 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5441 case 7: /* invlpg */
5444 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5445 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5449 opcode
= opcode
<< 8 | ir
.modrm
;
5454 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5458 opcode
= opcode
<< 8 | ir
.modrm
;
5464 case 0x0f08: /* invd */
5465 case 0x0f09: /* wbinvd */
5468 case 0x63: /* arpl */
5469 if (i386_record_modrm (&ir
))
5471 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5473 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5474 ? (ir
.reg
| rex_r
) : ir
.rm
);
5478 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5479 if (i386_record_lea_modrm (&ir
))
5482 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5483 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5486 case 0x0f02: /* lar */
5487 case 0x0f03: /* lsl */
5488 if (i386_record_modrm (&ir
))
5490 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5495 if (i386_record_modrm (&ir
))
5497 if (ir
.mod
== 3 && ir
.reg
== 3)
5500 opcode
= opcode
<< 8 | ir
.modrm
;
5512 /* nop (multi byte) */
5515 case 0x0f20: /* mov reg, crN */
5516 case 0x0f22: /* mov crN, reg */
5517 if (i386_record_modrm (&ir
))
5519 if ((ir
.modrm
& 0xc0) != 0xc0)
5522 opcode
= opcode
<< 8 | ir
.modrm
;
5533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5535 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5539 opcode
= opcode
<< 8 | ir
.modrm
;
5545 case 0x0f21: /* mov reg, drN */
5546 case 0x0f23: /* mov drN, reg */
5547 if (i386_record_modrm (&ir
))
5549 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5550 || ir
.reg
== 5 || ir
.reg
>= 8)
5553 opcode
= opcode
<< 8 | ir
.modrm
;
5557 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5559 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5562 case 0x0f06: /* clts */
5563 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5566 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5568 case 0x0f0d: /* 3DNow! prefetch */
5571 case 0x0f0e: /* 3DNow! femms */
5572 case 0x0f77: /* emms */
5573 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
5575 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
5578 case 0x0f0f: /* 3DNow! data */
5579 if (i386_record_modrm (&ir
))
5581 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5583 printf_unfiltered (_("Process record: error reading memory at "
5584 "addr %s len = 1.\n"),
5585 paddress (gdbarch
, ir
.addr
));
5591 case 0x0c: /* 3DNow! pi2fw */
5592 case 0x0d: /* 3DNow! pi2fd */
5593 case 0x1c: /* 3DNow! pf2iw */
5594 case 0x1d: /* 3DNow! pf2id */
5595 case 0x8a: /* 3DNow! pfnacc */
5596 case 0x8e: /* 3DNow! pfpnacc */
5597 case 0x90: /* 3DNow! pfcmpge */
5598 case 0x94: /* 3DNow! pfmin */
5599 case 0x96: /* 3DNow! pfrcp */
5600 case 0x97: /* 3DNow! pfrsqrt */
5601 case 0x9a: /* 3DNow! pfsub */
5602 case 0x9e: /* 3DNow! pfadd */
5603 case 0xa0: /* 3DNow! pfcmpgt */
5604 case 0xa4: /* 3DNow! pfmax */
5605 case 0xa6: /* 3DNow! pfrcpit1 */
5606 case 0xa7: /* 3DNow! pfrsqit1 */
5607 case 0xaa: /* 3DNow! pfsubr */
5608 case 0xae: /* 3DNow! pfacc */
5609 case 0xb0: /* 3DNow! pfcmpeq */
5610 case 0xb4: /* 3DNow! pfmul */
5611 case 0xb6: /* 3DNow! pfrcpit2 */
5612 case 0xb7: /* 3DNow! pmulhrw */
5613 case 0xbb: /* 3DNow! pswapd */
5614 case 0xbf: /* 3DNow! pavgusb */
5615 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
5616 goto no_support_3dnow_data
;
5617 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
5621 no_support_3dnow_data
:
5622 opcode
= (opcode
<< 8) | opcode8
;
5628 case 0x0faa: /* rsm */
5629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5637 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5641 if (i386_record_modrm (&ir
))
5645 case 0: /* fxsave */
5649 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5650 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5652 if (record_arch_list_add_mem (tmpu64
, 512))
5657 case 1: /* fxrstor */
5661 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5663 for (i
= I387_MM0_REGNUM (tdep
);
5664 i386_mmx_regnum_p (gdbarch
, i
); i
++)
5665 record_arch_list_add_reg (ir
.regcache
, i
);
5667 for (i
= I387_XMM0_REGNUM (tdep
);
5668 i386_sse_regnum_p (gdbarch
, i
); i
++)
5669 record_arch_list_add_reg (ir
.regcache
, i
);
5671 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
5672 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
5674 for (i
= I387_ST0_REGNUM (tdep
);
5675 i386_fp_regnum_p (gdbarch
, i
); i
++)
5676 record_arch_list_add_reg (ir
.regcache
, i
);
5678 for (i
= I387_FCTRL_REGNUM (tdep
);
5679 i386_fpc_regnum_p (gdbarch
, i
); i
++)
5680 record_arch_list_add_reg (ir
.regcache
, i
);
5684 case 2: /* ldmxcsr */
5685 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
5687 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
5690 case 3: /* stmxcsr */
5692 if (i386_record_lea_modrm (&ir
))
5696 case 5: /* lfence */
5697 case 6: /* mfence */
5698 case 7: /* sfence clflush */
5702 opcode
= (opcode
<< 8) | ir
.modrm
;
5708 case 0x0fc3: /* movnti */
5709 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
5710 if (i386_record_modrm (&ir
))
5715 if (i386_record_lea_modrm (&ir
))
5719 /* Add prefix to opcode. */
5846 reswitch_prefix_add
:
5854 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5856 printf_unfiltered (_("Process record: error reading memory at "
5857 "addr %s len = 1.\n"),
5858 paddress (gdbarch
, ir
.addr
));
5862 opcode
= (uint32_t) opcode8
| opcode
<< 8;
5863 goto reswitch_prefix_add
;
5866 case 0x0f10: /* movups */
5867 case 0x660f10: /* movupd */
5868 case 0xf30f10: /* movss */
5869 case 0xf20f10: /* movsd */
5870 case 0x0f12: /* movlps */
5871 case 0x660f12: /* movlpd */
5872 case 0xf30f12: /* movsldup */
5873 case 0xf20f12: /* movddup */
5874 case 0x0f14: /* unpcklps */
5875 case 0x660f14: /* unpcklpd */
5876 case 0x0f15: /* unpckhps */
5877 case 0x660f15: /* unpckhpd */
5878 case 0x0f16: /* movhps */
5879 case 0x660f16: /* movhpd */
5880 case 0xf30f16: /* movshdup */
5881 case 0x0f28: /* movaps */
5882 case 0x660f28: /* movapd */
5883 case 0x0f2a: /* cvtpi2ps */
5884 case 0x660f2a: /* cvtpi2pd */
5885 case 0xf30f2a: /* cvtsi2ss */
5886 case 0xf20f2a: /* cvtsi2sd */
5887 case 0x0f2c: /* cvttps2pi */
5888 case 0x660f2c: /* cvttpd2pi */
5889 case 0x0f2d: /* cvtps2pi */
5890 case 0x660f2d: /* cvtpd2pi */
5891 case 0x660f3800: /* pshufb */
5892 case 0x660f3801: /* phaddw */
5893 case 0x660f3802: /* phaddd */
5894 case 0x660f3803: /* phaddsw */
5895 case 0x660f3804: /* pmaddubsw */
5896 case 0x660f3805: /* phsubw */
5897 case 0x660f3806: /* phsubd */
5898 case 0x660f3807: /* phaddsw */
5899 case 0x660f3808: /* psignb */
5900 case 0x660f3809: /* psignw */
5901 case 0x660f380a: /* psignd */
5902 case 0x660f380b: /* pmulhrsw */
5903 case 0x660f3810: /* pblendvb */
5904 case 0x660f3814: /* blendvps */
5905 case 0x660f3815: /* blendvpd */
5906 case 0x660f381c: /* pabsb */
5907 case 0x660f381d: /* pabsw */
5908 case 0x660f381e: /* pabsd */
5909 case 0x660f3820: /* pmovsxbw */
5910 case 0x660f3821: /* pmovsxbd */
5911 case 0x660f3822: /* pmovsxbq */
5912 case 0x660f3823: /* pmovsxwd */
5913 case 0x660f3824: /* pmovsxwq */
5914 case 0x660f3825: /* pmovsxdq */
5915 case 0x660f3828: /* pmuldq */
5916 case 0x660f3829: /* pcmpeqq */
5917 case 0x660f382a: /* movntdqa */
5918 case 0x660f3a08: /* roundps */
5919 case 0x660f3a09: /* roundpd */
5920 case 0x660f3a0a: /* roundss */
5921 case 0x660f3a0b: /* roundsd */
5922 case 0x660f3a0c: /* blendps */
5923 case 0x660f3a0d: /* blendpd */
5924 case 0x660f3a0e: /* pblendw */
5925 case 0x660f3a0f: /* palignr */
5926 case 0x660f3a20: /* pinsrb */
5927 case 0x660f3a21: /* insertps */
5928 case 0x660f3a22: /* pinsrd pinsrq */
5929 case 0x660f3a40: /* dpps */
5930 case 0x660f3a41: /* dppd */
5931 case 0x660f3a42: /* mpsadbw */
5932 case 0x660f3a60: /* pcmpestrm */
5933 case 0x660f3a61: /* pcmpestri */
5934 case 0x660f3a62: /* pcmpistrm */
5935 case 0x660f3a63: /* pcmpistri */
5936 case 0x0f51: /* sqrtps */
5937 case 0x660f51: /* sqrtpd */
5938 case 0xf20f51: /* sqrtsd */
5939 case 0xf30f51: /* sqrtss */
5940 case 0x0f52: /* rsqrtps */
5941 case 0xf30f52: /* rsqrtss */
5942 case 0x0f53: /* rcpps */
5943 case 0xf30f53: /* rcpss */
5944 case 0x0f54: /* andps */
5945 case 0x660f54: /* andpd */
5946 case 0x0f55: /* andnps */
5947 case 0x660f55: /* andnpd */
5948 case 0x0f56: /* orps */
5949 case 0x660f56: /* orpd */
5950 case 0x0f57: /* xorps */
5951 case 0x660f57: /* xorpd */
5952 case 0x0f58: /* addps */
5953 case 0x660f58: /* addpd */
5954 case 0xf20f58: /* addsd */
5955 case 0xf30f58: /* addss */
5956 case 0x0f59: /* mulps */
5957 case 0x660f59: /* mulpd */
5958 case 0xf20f59: /* mulsd */
5959 case 0xf30f59: /* mulss */
5960 case 0x0f5a: /* cvtps2pd */
5961 case 0x660f5a: /* cvtpd2ps */
5962 case 0xf20f5a: /* cvtsd2ss */
5963 case 0xf30f5a: /* cvtss2sd */
5964 case 0x0f5b: /* cvtdq2ps */
5965 case 0x660f5b: /* cvtps2dq */
5966 case 0xf30f5b: /* cvttps2dq */
5967 case 0x0f5c: /* subps */
5968 case 0x660f5c: /* subpd */
5969 case 0xf20f5c: /* subsd */
5970 case 0xf30f5c: /* subss */
5971 case 0x0f5d: /* minps */
5972 case 0x660f5d: /* minpd */
5973 case 0xf20f5d: /* minsd */
5974 case 0xf30f5d: /* minss */
5975 case 0x0f5e: /* divps */
5976 case 0x660f5e: /* divpd */
5977 case 0xf20f5e: /* divsd */
5978 case 0xf30f5e: /* divss */
5979 case 0x0f5f: /* maxps */
5980 case 0x660f5f: /* maxpd */
5981 case 0xf20f5f: /* maxsd */
5982 case 0xf30f5f: /* maxss */
5983 case 0x660f60: /* punpcklbw */
5984 case 0x660f61: /* punpcklwd */
5985 case 0x660f62: /* punpckldq */
5986 case 0x660f63: /* packsswb */
5987 case 0x660f64: /* pcmpgtb */
5988 case 0x660f65: /* pcmpgtw */
5989 case 0x660f66: /* pcmpgtl */
5990 case 0x660f67: /* packuswb */
5991 case 0x660f68: /* punpckhbw */
5992 case 0x660f69: /* punpckhwd */
5993 case 0x660f6a: /* punpckhdq */
5994 case 0x660f6b: /* packssdw */
5995 case 0x660f6c: /* punpcklqdq */
5996 case 0x660f6d: /* punpckhqdq */
5997 case 0x660f6e: /* movd */
5998 case 0x660f6f: /* movdqa */
5999 case 0xf30f6f: /* movdqu */
6000 case 0x660f70: /* pshufd */
6001 case 0xf20f70: /* pshuflw */
6002 case 0xf30f70: /* pshufhw */
6003 case 0x660f74: /* pcmpeqb */
6004 case 0x660f75: /* pcmpeqw */
6005 case 0x660f76: /* pcmpeql */
6006 case 0x660f7c: /* haddpd */
6007 case 0xf20f7c: /* haddps */
6008 case 0x660f7d: /* hsubpd */
6009 case 0xf20f7d: /* hsubps */
6010 case 0xf30f7e: /* movq */
6011 case 0x0fc2: /* cmpps */
6012 case 0x660fc2: /* cmppd */
6013 case 0xf20fc2: /* cmpsd */
6014 case 0xf30fc2: /* cmpss */
6015 case 0x660fc4: /* pinsrw */
6016 case 0x0fc6: /* shufps */
6017 case 0x660fc6: /* shufpd */
6018 case 0x660fd0: /* addsubpd */
6019 case 0xf20fd0: /* addsubps */
6020 case 0x660fd1: /* psrlw */
6021 case 0x660fd2: /* psrld */
6022 case 0x660fd3: /* psrlq */
6023 case 0x660fd4: /* paddq */
6024 case 0x660fd5: /* pmullw */
6025 case 0xf30fd6: /* movq2dq */
6026 case 0x660fd8: /* psubusb */
6027 case 0x660fd9: /* psubusw */
6028 case 0x660fda: /* pminub */
6029 case 0x660fdb: /* pand */
6030 case 0x660fdc: /* paddusb */
6031 case 0x660fdd: /* paddusw */
6032 case 0x660fde: /* pmaxub */
6033 case 0x660fdf: /* pandn */
6034 case 0x660fe0: /* pavgb */
6035 case 0x660fe1: /* psraw */
6036 case 0x660fe2: /* psrad */
6037 case 0x660fe3: /* pavgw */
6038 case 0x660fe4: /* pmulhuw */
6039 case 0x660fe5: /* pmulhw */
6040 case 0x660fe6: /* cvttpd2dq */
6041 case 0xf20fe6: /* cvtpd2dq */
6042 case 0xf30fe6: /* cvtdq2pd */
6043 case 0x660fe8: /* psubsb */
6044 case 0x660fe9: /* psubsw */
6045 case 0x660fea: /* pminsw */
6046 case 0x660feb: /* por */
6047 case 0x660fec: /* paddsb */
6048 case 0x660fed: /* paddsw */
6049 case 0x660fee: /* pmaxsw */
6050 case 0x660fef: /* pxor */
6051 case 0x660ff0: /* lddqu */
6052 case 0x660ff1: /* psllw */
6053 case 0x660ff2: /* pslld */
6054 case 0x660ff3: /* psllq */
6055 case 0x660ff4: /* pmuludq */
6056 case 0x660ff5: /* pmaddwd */
6057 case 0x660ff6: /* psadbw */
6058 case 0x660ff8: /* psubb */
6059 case 0x660ff9: /* psubw */
6060 case 0x660ffa: /* psubl */
6061 case 0x660ffb: /* psubq */
6062 case 0x660ffc: /* paddb */
6063 case 0x660ffd: /* paddw */
6064 case 0x660ffe: /* paddl */
6065 if (i386_record_modrm (&ir
))
6068 if (!i386_sse_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6070 record_arch_list_add_reg (ir
.regcache
,
6071 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6072 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6073 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6076 case 0x0f11: /* movups */
6077 case 0x660f11: /* movupd */
6078 case 0xf30f11: /* movss */
6079 case 0xf20f11: /* movsd */
6080 case 0x0f13: /* movlps */
6081 case 0x660f13: /* movlpd */
6082 case 0x0f17: /* movhps */
6083 case 0x660f17: /* movhpd */
6084 case 0x0f29: /* movaps */
6085 case 0x660f29: /* movapd */
6086 case 0x660f3a14: /* pextrb */
6087 case 0x660f3a15: /* pextrw */
6088 case 0x660f3a16: /* pextrd pextrq */
6089 case 0x660f3a17: /* extractps */
6090 case 0x660f7f: /* movdqa */
6091 case 0xf30f7f: /* movdqu */
6092 if (i386_record_modrm (&ir
))
6096 if (opcode
== 0x0f13 || opcode
== 0x660f13
6097 || opcode
== 0x0f17 || opcode
== 0x660f17)
6100 if (!i386_sse_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6102 record_arch_list_add_reg (ir
.regcache
,
6103 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6125 if (i386_record_lea_modrm (&ir
))
6130 case 0x0f2b: /* movntps */
6131 case 0x660f2b: /* movntpd */
6132 case 0x0fe7: /* movntq */
6133 case 0x660fe7: /* movntdq */
6136 if (opcode
== 0x0fe7)
6140 if (i386_record_lea_modrm (&ir
))
6144 case 0xf30f2c: /* cvttss2si */
6145 case 0xf20f2c: /* cvttsd2si */
6146 case 0xf30f2d: /* cvtss2si */
6147 case 0xf20f2d: /* cvtsd2si */
6148 case 0xf20f38f0: /* crc32 */
6149 case 0xf20f38f1: /* crc32 */
6150 case 0x0f50: /* movmskps */
6151 case 0x660f50: /* movmskpd */
6152 case 0x0fc5: /* pextrw */
6153 case 0x660fc5: /* pextrw */
6154 case 0x0fd7: /* pmovmskb */
6155 case 0x660fd7: /* pmovmskb */
6156 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6159 case 0x0f3800: /* pshufb */
6160 case 0x0f3801: /* phaddw */
6161 case 0x0f3802: /* phaddd */
6162 case 0x0f3803: /* phaddsw */
6163 case 0x0f3804: /* pmaddubsw */
6164 case 0x0f3805: /* phsubw */
6165 case 0x0f3806: /* phsubd */
6166 case 0x0f3807: /* phaddsw */
6167 case 0x0f3808: /* psignb */
6168 case 0x0f3809: /* psignw */
6169 case 0x0f380a: /* psignd */
6170 case 0x0f380b: /* pmulhrsw */
6171 case 0x0f381c: /* pabsb */
6172 case 0x0f381d: /* pabsw */
6173 case 0x0f381e: /* pabsd */
6174 case 0x0f382b: /* packusdw */
6175 case 0x0f3830: /* pmovzxbw */
6176 case 0x0f3831: /* pmovzxbd */
6177 case 0x0f3832: /* pmovzxbq */
6178 case 0x0f3833: /* pmovzxwd */
6179 case 0x0f3834: /* pmovzxwq */
6180 case 0x0f3835: /* pmovzxdq */
6181 case 0x0f3837: /* pcmpgtq */
6182 case 0x0f3838: /* pminsb */
6183 case 0x0f3839: /* pminsd */
6184 case 0x0f383a: /* pminuw */
6185 case 0x0f383b: /* pminud */
6186 case 0x0f383c: /* pmaxsb */
6187 case 0x0f383d: /* pmaxsd */
6188 case 0x0f383e: /* pmaxuw */
6189 case 0x0f383f: /* pmaxud */
6190 case 0x0f3840: /* pmulld */
6191 case 0x0f3841: /* phminposuw */
6192 case 0x0f3a0f: /* palignr */
6193 case 0x0f60: /* punpcklbw */
6194 case 0x0f61: /* punpcklwd */
6195 case 0x0f62: /* punpckldq */
6196 case 0x0f63: /* packsswb */
6197 case 0x0f64: /* pcmpgtb */
6198 case 0x0f65: /* pcmpgtw */
6199 case 0x0f66: /* pcmpgtl */
6200 case 0x0f67: /* packuswb */
6201 case 0x0f68: /* punpckhbw */
6202 case 0x0f69: /* punpckhwd */
6203 case 0x0f6a: /* punpckhdq */
6204 case 0x0f6b: /* packssdw */
6205 case 0x0f6e: /* movd */
6206 case 0x0f6f: /* movq */
6207 case 0x0f70: /* pshufw */
6208 case 0x0f74: /* pcmpeqb */
6209 case 0x0f75: /* pcmpeqw */
6210 case 0x0f76: /* pcmpeql */
6211 case 0x0fc4: /* pinsrw */
6212 case 0x0fd1: /* psrlw */
6213 case 0x0fd2: /* psrld */
6214 case 0x0fd3: /* psrlq */
6215 case 0x0fd4: /* paddq */
6216 case 0x0fd5: /* pmullw */
6217 case 0xf20fd6: /* movdq2q */
6218 case 0x0fd8: /* psubusb */
6219 case 0x0fd9: /* psubusw */
6220 case 0x0fda: /* pminub */
6221 case 0x0fdb: /* pand */
6222 case 0x0fdc: /* paddusb */
6223 case 0x0fdd: /* paddusw */
6224 case 0x0fde: /* pmaxub */
6225 case 0x0fdf: /* pandn */
6226 case 0x0fe0: /* pavgb */
6227 case 0x0fe1: /* psraw */
6228 case 0x0fe2: /* psrad */
6229 case 0x0fe3: /* pavgw */
6230 case 0x0fe4: /* pmulhuw */
6231 case 0x0fe5: /* pmulhw */
6232 case 0x0fe8: /* psubsb */
6233 case 0x0fe9: /* psubsw */
6234 case 0x0fea: /* pminsw */
6235 case 0x0feb: /* por */
6236 case 0x0fec: /* paddsb */
6237 case 0x0fed: /* paddsw */
6238 case 0x0fee: /* pmaxsw */
6239 case 0x0fef: /* pxor */
6240 case 0x0ff1: /* psllw */
6241 case 0x0ff2: /* pslld */
6242 case 0x0ff3: /* psllq */
6243 case 0x0ff4: /* pmuludq */
6244 case 0x0ff5: /* pmaddwd */
6245 case 0x0ff6: /* psadbw */
6246 case 0x0ff8: /* psubb */
6247 case 0x0ff9: /* psubw */
6248 case 0x0ffa: /* psubl */
6249 case 0x0ffb: /* psubq */
6250 case 0x0ffc: /* paddb */
6251 case 0x0ffd: /* paddw */
6252 case 0x0ffe: /* paddl */
6253 if (i386_record_modrm (&ir
))
6255 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6257 record_arch_list_add_reg (ir
.regcache
,
6258 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6261 case 0x0f71: /* psllw */
6262 case 0x0f72: /* pslld */
6263 case 0x0f73: /* psllq */
6264 if (i386_record_modrm (&ir
))
6266 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6268 record_arch_list_add_reg (ir
.regcache
,
6269 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6272 case 0x660f71: /* psllw */
6273 case 0x660f72: /* pslld */
6274 case 0x660f73: /* psllq */
6275 if (i386_record_modrm (&ir
))
6278 if (!i386_sse_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6280 record_arch_list_add_reg (ir
.regcache
,
6281 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6284 case 0x0f7e: /* movd */
6285 case 0x660f7e: /* movd */
6286 if (i386_record_modrm (&ir
))
6289 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6296 if (i386_record_lea_modrm (&ir
))
6301 case 0x0f7f: /* movq */
6302 if (i386_record_modrm (&ir
))
6306 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6308 record_arch_list_add_reg (ir
.regcache
,
6309 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6314 if (i386_record_lea_modrm (&ir
))
6319 case 0xf30fb8: /* popcnt */
6320 if (i386_record_modrm (&ir
))
6322 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6323 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6326 case 0x660fd6: /* movq */
6327 if (i386_record_modrm (&ir
))
6332 if (!i386_sse_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6334 record_arch_list_add_reg (ir
.regcache
,
6335 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6340 if (i386_record_lea_modrm (&ir
))
6345 case 0x660f3817: /* ptest */
6346 case 0x0f2e: /* ucomiss */
6347 case 0x660f2e: /* ucomisd */
6348 case 0x0f2f: /* comiss */
6349 case 0x660f2f: /* comisd */
6350 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6353 case 0x0ff7: /* maskmovq */
6354 regcache_raw_read_unsigned (ir
.regcache
,
6355 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6357 if (record_arch_list_add_mem (addr
, 64))
6361 case 0x660ff7: /* maskmovdqu */
6362 regcache_raw_read_unsigned (ir
.regcache
,
6363 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6365 if (record_arch_list_add_mem (addr
, 128))
6380 /* In the future, maybe still need to deal with need_dasm. */
6381 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6382 if (record_arch_list_add_end ())
6388 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6389 "at address %s.\n"),
6390 (unsigned int) (opcode
),
6391 paddress (gdbarch
, ir
.orig_addr
));
6395 static const int i386_record_regmap
[] =
6397 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6398 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6399 0, 0, 0, 0, 0, 0, 0, 0,
6400 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6401 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6404 /* Check that the given address appears suitable for a fast
6405 tracepoint, which on x86 means that we need an instruction of at
6406 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6407 jump and not have to worry about program jumps to an address in the
6408 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6409 of instruction to replace, and 0 if not, plus an explanatory
6413 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6414 CORE_ADDR addr
, int *isize
, char **msg
)
6417 static struct ui_file
*gdb_null
= NULL
;
6419 /* This is based on the target agent using a 4-byte relative jump.
6420 Alternate future possibilities include 8-byte offset for x86-84,
6421 or 3-byte jumps if the program has trampoline space close by. */
6424 /* Dummy file descriptor for the disassembler. */
6426 gdb_null
= ui_file_new ();
6428 /* Check for fit. */
6429 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6432 /* Return a bit of target-specific detail to add to the caller's
6433 generic failure message. */
6435 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
6448 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6449 struct tdesc_arch_data
*tdesc_data
)
6451 const struct target_desc
*tdesc
= tdep
->tdesc
;
6452 const struct tdesc_feature
*feature_core
, *feature_vector
;
6453 int i
, num_regs
, valid_p
;
6455 if (! tdesc_has_registers (tdesc
))
6458 /* Get core registers. */
6459 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6461 /* Get SSE registers. */
6462 feature_vector
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6464 if (feature_core
== NULL
|| feature_vector
== NULL
)
6469 num_regs
= tdep
->num_core_regs
;
6470 for (i
= 0; i
< num_regs
; i
++)
6471 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
6472 tdep
->register_names
[i
]);
6474 /* Need to include %mxcsr, so add one. */
6475 num_regs
+= tdep
->num_xmm_regs
+ 1;
6476 for (; i
< num_regs
; i
++)
6477 valid_p
&= tdesc_numbered_register (feature_vector
, tdesc_data
, i
,
6478 tdep
->register_names
[i
]);
6484 static struct gdbarch
*
6485 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6487 struct gdbarch_tdep
*tdep
;
6488 struct gdbarch
*gdbarch
;
6489 struct tdesc_arch_data
*tdesc_data
;
6490 const struct target_desc
*tdesc
;
6493 /* If there is already a candidate, use it. */
6494 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6496 return arches
->gdbarch
;
6498 /* Allocate space for the new architecture. */
6499 tdep
= XCALLOC (1, struct gdbarch_tdep
);
6500 gdbarch
= gdbarch_alloc (&info
, tdep
);
6502 /* General-purpose registers. */
6503 tdep
->gregset
= NULL
;
6504 tdep
->gregset_reg_offset
= NULL
;
6505 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
6506 tdep
->sizeof_gregset
= 0;
6508 /* Floating-point registers. */
6509 tdep
->fpregset
= NULL
;
6510 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
6512 /* The default settings include the FPU registers, the MMX registers
6513 and the SSE registers. This can be overridden for a specific ABI
6514 by adjusting the members `st0_regnum', `mm0_regnum' and
6515 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6516 will show up in the output of "info all-registers". Ideally we
6517 should try to autodetect whether they are available, such that we
6518 can prevent "info all-registers" from displaying registers that
6521 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
6522 [the SSE registers] always (even when they don't exist) or never
6523 showing them to the user (even when they do exist), I prefer the
6524 former over the latter. */
6526 tdep
->st0_regnum
= I386_ST0_REGNUM
;
6528 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6529 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
6531 tdep
->jb_pc_offset
= -1;
6532 tdep
->struct_return
= pcc_struct_return
;
6533 tdep
->sigtramp_start
= 0;
6534 tdep
->sigtramp_end
= 0;
6535 tdep
->sigtramp_p
= i386_sigtramp_p
;
6536 tdep
->sigcontext_addr
= NULL
;
6537 tdep
->sc_reg_offset
= NULL
;
6538 tdep
->sc_pc_offset
= -1;
6539 tdep
->sc_sp_offset
= -1;
6541 tdep
->record_regmap
= i386_record_regmap
;
6543 /* The format used for `long double' on almost all i386 targets is
6544 the i387 extended floating-point format. In fact, of all targets
6545 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6546 on having a `long double' that's not `long' at all. */
6547 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
6549 /* Although the i387 extended floating-point has only 80 significant
6550 bits, a `long double' actually takes up 96, probably to enforce
6552 set_gdbarch_long_double_bit (gdbarch
, 96);
6554 /* Register numbers of various important registers. */
6555 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
6556 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
6557 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
6558 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
6560 /* NOTE: kettenis/20040418: GCC does have two possible register
6561 numbering schemes on the i386: dbx and SVR4. These schemes
6562 differ in how they number %ebp, %esp, %eflags, and the
6563 floating-point registers, and are implemented by the arrays
6564 dbx_register_map[] and svr4_dbx_register_map in
6565 gcc/config/i386.c. GCC also defines a third numbering scheme in
6566 gcc/config/i386.c, which it designates as the "default" register
6567 map used in 64bit mode. This last register numbering scheme is
6568 implemented in dbx64_register_map, and is used for AMD64; see
6571 Currently, each GCC i386 target always uses the same register
6572 numbering scheme across all its supported debugging formats
6573 i.e. SDB (COFF), stabs and DWARF 2. This is because
6574 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6575 DBX_REGISTER_NUMBER macro which is defined by each target's
6576 respective config header in a manner independent of the requested
6577 output debugging format.
6579 This does not match the arrangement below, which presumes that
6580 the SDB and stabs numbering schemes differ from the DWARF and
6581 DWARF 2 ones. The reason for this arrangement is that it is
6582 likely to get the numbering scheme for the target's
6583 default/native debug format right. For targets where GCC is the
6584 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6585 targets where the native toolchain uses a different numbering
6586 scheme for a particular debug format (stabs-in-ELF on Solaris)
6587 the defaults below will have to be overridden, like
6588 i386_elf_init_abi() does. */
6590 /* Use the dbx register numbering scheme for stabs and COFF. */
6591 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6592 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6594 /* Use the SVR4 register numbering scheme for DWARF 2. */
6595 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
6597 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6598 be in use on any of the supported i386 targets. */
6600 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
6602 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
6604 /* Call dummy code. */
6605 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
6607 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
6608 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
6609 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
6611 set_gdbarch_return_value (gdbarch
, i386_return_value
);
6613 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
6615 /* Stack grows downward. */
6616 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6618 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
6619 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
6620 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
6622 set_gdbarch_frame_args_skip (gdbarch
, 8);
6624 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
6626 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
6628 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
6630 /* Add the i386 register groups. */
6631 i386_add_reggroups (gdbarch
);
6632 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
6634 /* Helper for function argument information. */
6635 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
6637 /* Hook the function epilogue frame unwinder. This unwinder is
6638 appended to the list first, so that it supercedes the Dwarf
6639 unwinder in function epilogues (where the Dwarf unwinder
6640 currently fails). */
6641 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
6643 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
6644 to the list before the prologue-based unwinders, so that Dwarf
6645 CFI info will be used if it is available. */
6646 dwarf2_append_unwinders (gdbarch
);
6648 frame_base_set_default (gdbarch
, &i386_frame_base
);
6650 /* Pseudo registers may be changed by amd64_init_abi. */
6651 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
6652 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
6654 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
6655 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
6657 /* The default ABI includes general-purpose registers,
6658 floating-point registers, and the SSE registers. */
6659 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
6661 /* Get the x86 target description from INFO. */
6662 tdesc
= info
.target_desc
;
6663 if (! tdesc_has_registers (tdesc
))
6665 tdep
->tdesc
= tdesc
;
6667 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
6668 tdep
->register_names
= i386_register_names
;
6670 tdep
->num_byte_regs
= 8;
6671 tdep
->num_word_regs
= 8;
6672 tdep
->num_dword_regs
= 0;
6673 tdep
->num_mmx_regs
= 8;
6675 tdesc_data
= tdesc_data_alloc ();
6677 /* Hook in ABI-specific overrides, if they have been registered. */
6678 info
.tdep_info
= (void *) tdesc_data
;
6679 gdbarch_init_osabi (info
, gdbarch
);
6681 /* Wire in pseudo registers. Number of pseudo registers may be
6683 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
6684 + tdep
->num_word_regs
6685 + tdep
->num_dword_regs
6686 + tdep
->num_mmx_regs
));
6688 /* Target description may be changed. */
6689 tdesc
= tdep
->tdesc
;
6691 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
6693 tdesc_data_cleanup (tdesc_data
);
6695 gdbarch_free (gdbarch
);
6699 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6701 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
6702 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
6704 /* Make %al the first pseudo-register. */
6705 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
6706 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
6708 mm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
6709 if (tdep
->num_dword_regs
)
6711 /* Support dword pseudo-registesr if it hasn't been disabled, */
6712 tdep
->eax_regnum
= mm0_regnum
;
6713 mm0_regnum
= tdep
->eax_regnum
+ tdep
->num_dword_regs
;
6716 tdep
->eax_regnum
= -1;
6718 if (tdep
->num_mmx_regs
!= 0)
6720 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
6721 tdep
->mm0_regnum
= mm0_regnum
;
6724 tdep
->mm0_regnum
= -1;
6726 /* Hook in the legacy prologue-based unwinders last (fallback). */
6727 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
6728 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
6730 /* If we have a register mapping, enable the generic core file
6731 support, unless it has already been enabled. */
6732 if (tdep
->gregset_reg_offset
6733 && !gdbarch_regset_from_core_section_p (gdbarch
))
6734 set_gdbarch_regset_from_core_section (gdbarch
,
6735 i386_regset_from_core_section
);
6737 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
6738 i386_skip_permanent_breakpoint
);
6740 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
6741 i386_fast_tracepoint_valid_at
);
6746 static enum gdb_osabi
6747 i386_coff_osabi_sniffer (bfd
*abfd
)
6749 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
6750 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
6751 return GDB_OSABI_GO32
;
6753 return GDB_OSABI_UNKNOWN
;
6757 /* Provide a prototype to silence -Wmissing-prototypes. */
6758 void _initialize_i386_tdep (void);
6761 _initialize_i386_tdep (void)
6763 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
6765 /* Add the variable that controls the disassembly flavor. */
6766 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
6767 &disassembly_flavor
, _("\
6768 Set the disassembly flavor."), _("\
6769 Show the disassembly flavor."), _("\
6770 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
6772 NULL
, /* FIXME: i18n: */
6773 &setlist
, &showlist
);
6775 /* Add the variable that controls the convention for returning
6777 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
6778 &struct_convention
, _("\
6779 Set the convention for returning small structs."), _("\
6780 Show the convention for returning small structs."), _("\
6781 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
6784 NULL
, /* FIXME: i18n: */
6785 &setlist
, &showlist
);
6787 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
6788 i386_coff_osabi_sniffer
);
6790 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
6791 i386_svr4_init_abi
);
6792 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
6793 i386_go32_init_abi
);
6795 /* Initialize the i386-specific register groups. */
6796 i386_init_reggroups ();
6798 /* Initialize the standard target descriptions. */
6799 initialize_tdesc_i386 ();
6801 /* Tell remote stub that we support XML target description. */
6802 register_remote_support_xml ("i386");