1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "gdb_assert.h"
49 #include "gdb_string.h"
51 #include "i386-tdep.h"
52 #include "i387-tdep.h"
57 #include "features/i386/i386.c"
61 static const char *i386_register_names
[] =
63 "eax", "ecx", "edx", "ebx",
64 "esp", "ebp", "esi", "edi",
65 "eip", "eflags", "cs", "ss",
66 "ds", "es", "fs", "gs",
67 "st0", "st1", "st2", "st3",
68 "st4", "st5", "st6", "st7",
69 "fctrl", "fstat", "ftag", "fiseg",
70 "fioff", "foseg", "fooff", "fop",
71 "xmm0", "xmm1", "xmm2", "xmm3",
72 "xmm4", "xmm5", "xmm6", "xmm7",
76 /* Register names for MMX pseudo-registers. */
78 static const char *i386_mmx_names
[] =
80 "mm0", "mm1", "mm2", "mm3",
81 "mm4", "mm5", "mm6", "mm7"
84 /* Register names for byte pseudo-registers. */
86 static const char *i386_byte_names
[] =
88 "al", "cl", "dl", "bl",
89 "ah", "ch", "dh", "bh"
92 /* Register names for word pseudo-registers. */
94 static const char *i386_word_names
[] =
96 "ax", "cx", "dx", "bx",
103 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
105 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
106 int mm0_regnum
= tdep
->mm0_regnum
;
111 regnum
-= mm0_regnum
;
112 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
118 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
120 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 regnum
-= tdep
->al_regnum
;
123 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
129 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
131 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
133 regnum
-= tdep
->ax_regnum
;
134 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
137 /* Dword register? */
140 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
143 int eax_regnum
= tdep
->eax_regnum
;
148 regnum
-= eax_regnum
;
149 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
155 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
157 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 if (I387_NUM_XMM_REGS (tdep
) == 0)
162 return (I387_XMM0_REGNUM (tdep
) <= regnum
163 && regnum
< I387_MXCSR_REGNUM (tdep
));
167 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 if (I387_NUM_XMM_REGS (tdep
) == 0)
174 return (regnum
== I387_MXCSR_REGNUM (tdep
));
180 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 if (I387_ST0_REGNUM (tdep
) < 0)
187 return (I387_ST0_REGNUM (tdep
) <= regnum
188 && regnum
< I387_FCTRL_REGNUM (tdep
));
192 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
196 if (I387_ST0_REGNUM (tdep
) < 0)
199 return (I387_FCTRL_REGNUM (tdep
) <= regnum
200 && regnum
< I387_XMM0_REGNUM (tdep
));
203 /* Return the name of register REGNUM. */
206 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
209 if (i386_mmx_regnum_p (gdbarch
, regnum
))
210 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
211 else if (i386_byte_regnum_p (gdbarch
, regnum
))
212 return i386_byte_names
[regnum
- tdep
->al_regnum
];
213 else if (i386_word_regnum_p (gdbarch
, regnum
))
214 return i386_word_names
[regnum
- tdep
->ax_regnum
];
216 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
219 /* Convert a dbx register number REG to the appropriate register
220 number used by GDB. */
223 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* This implements what GCC calls the "default" register map
228 (dbx_register_map[]). */
230 if (reg
>= 0 && reg
<= 7)
232 /* General-purpose registers. The debug info calls %ebp
233 register 4, and %esp register 5. */
240 else if (reg
>= 12 && reg
<= 19)
242 /* Floating-point registers. */
243 return reg
- 12 + I387_ST0_REGNUM (tdep
);
245 else if (reg
>= 21 && reg
<= 28)
248 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
250 else if (reg
>= 29 && reg
<= 36)
253 return reg
- 29 + I387_MM0_REGNUM (tdep
);
256 /* This will hopefully provoke a warning. */
257 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
260 /* Convert SVR4 register number REG to the appropriate register number
264 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
268 /* This implements the GCC register map that tries to be compatible
269 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
271 /* The SVR4 register numbering includes %eip and %eflags, and
272 numbers the floating point registers differently. */
273 if (reg
>= 0 && reg
<= 9)
275 /* General-purpose registers. */
278 else if (reg
>= 11 && reg
<= 18)
280 /* Floating-point registers. */
281 return reg
- 11 + I387_ST0_REGNUM (tdep
);
283 else if (reg
>= 21 && reg
<= 36)
285 /* The SSE and MMX registers have the same numbers as with dbx. */
286 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
291 case 37: return I387_FCTRL_REGNUM (tdep
);
292 case 38: return I387_FSTAT_REGNUM (tdep
);
293 case 39: return I387_MXCSR_REGNUM (tdep
);
294 case 40: return I386_ES_REGNUM
;
295 case 41: return I386_CS_REGNUM
;
296 case 42: return I386_SS_REGNUM
;
297 case 43: return I386_DS_REGNUM
;
298 case 44: return I386_FS_REGNUM
;
299 case 45: return I386_GS_REGNUM
;
302 /* This will hopefully provoke a warning. */
303 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
308 /* This is the variable that is set with "set disassembly-flavor", and
309 its legitimate values. */
310 static const char att_flavor
[] = "att";
311 static const char intel_flavor
[] = "intel";
312 static const char *valid_flavors
[] =
318 static const char *disassembly_flavor
= att_flavor
;
321 /* Use the program counter to determine the contents and size of a
322 breakpoint instruction. Return a pointer to a string of bytes that
323 encode a breakpoint instruction, store the length of the string in
324 *LEN and optionally adjust *PC to point to the correct memory
325 location for inserting the breakpoint.
327 On the i386 we have a single breakpoint that fits in a single byte
328 and can be inserted anywhere.
330 This function is 64-bit safe. */
332 static const gdb_byte
*
333 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
335 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
337 *len
= sizeof (break_insn
);
341 /* Displaced instruction handling. */
343 /* Skip the legacy instruction prefixes in INSN.
344 Not all prefixes are valid for any particular insn
345 but we needn't care, the insn will fault if it's invalid.
346 The result is a pointer to the first opcode byte,
347 or NULL if we run off the end of the buffer. */
350 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
352 gdb_byte
*end
= insn
+ max_len
;
358 case DATA_PREFIX_OPCODE
:
359 case ADDR_PREFIX_OPCODE
:
360 case CS_PREFIX_OPCODE
:
361 case DS_PREFIX_OPCODE
:
362 case ES_PREFIX_OPCODE
:
363 case FS_PREFIX_OPCODE
:
364 case GS_PREFIX_OPCODE
:
365 case SS_PREFIX_OPCODE
:
366 case LOCK_PREFIX_OPCODE
:
367 case REPE_PREFIX_OPCODE
:
368 case REPNE_PREFIX_OPCODE
:
380 i386_absolute_jmp_p (const gdb_byte
*insn
)
382 /* jmp far (absolute address in operand) */
388 /* jump near, absolute indirect (/4) */
389 if ((insn
[1] & 0x38) == 0x20)
392 /* jump far, absolute indirect (/5) */
393 if ((insn
[1] & 0x38) == 0x28)
401 i386_absolute_call_p (const gdb_byte
*insn
)
403 /* call far, absolute */
409 /* Call near, absolute indirect (/2) */
410 if ((insn
[1] & 0x38) == 0x10)
413 /* Call far, absolute indirect (/3) */
414 if ((insn
[1] & 0x38) == 0x18)
422 i386_ret_p (const gdb_byte
*insn
)
426 case 0xc2: /* ret near, pop N bytes */
427 case 0xc3: /* ret near */
428 case 0xca: /* ret far, pop N bytes */
429 case 0xcb: /* ret far */
430 case 0xcf: /* iret */
439 i386_call_p (const gdb_byte
*insn
)
441 if (i386_absolute_call_p (insn
))
444 /* call near, relative */
451 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
452 length in bytes. Otherwise, return zero. */
455 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
466 /* Fix up the state of registers and memory after having single-stepped
467 a displaced instruction. */
470 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
471 struct displaced_step_closure
*closure
,
472 CORE_ADDR from
, CORE_ADDR to
,
473 struct regcache
*regs
)
475 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
477 /* The offset we applied to the instruction's address.
478 This could well be negative (when viewed as a signed 32-bit
479 value), but ULONGEST won't reflect that, so take care when
481 ULONGEST insn_offset
= to
- from
;
483 /* Since we use simple_displaced_step_copy_insn, our closure is a
484 copy of the instruction. */
485 gdb_byte
*insn
= (gdb_byte
*) closure
;
486 /* The start of the insn, needed in case we see some prefixes. */
487 gdb_byte
*insn_start
= insn
;
490 fprintf_unfiltered (gdb_stdlog
,
491 "displaced: fixup (%s, %s), "
492 "insn = 0x%02x 0x%02x ...\n",
493 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
496 /* The list of issues to contend with here is taken from
497 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
498 Yay for Free Software! */
500 /* Relocate the %eip, if necessary. */
502 /* The instruction recognizers we use assume any leading prefixes
503 have been skipped. */
505 /* This is the size of the buffer in closure. */
506 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
507 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
508 /* If there are too many prefixes, just ignore the insn.
509 It will fault when run. */
514 /* Except in the case of absolute or indirect jump or call
515 instructions, or a return instruction, the new eip is relative to
516 the displaced instruction; make it relative. Well, signal
517 handler returns don't need relocation either, but we use the
518 value of %eip to recognize those; see below. */
519 if (! i386_absolute_jmp_p (insn
)
520 && ! i386_absolute_call_p (insn
)
521 && ! i386_ret_p (insn
))
526 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
528 /* A signal trampoline system call changes the %eip, resuming
529 execution of the main program after the signal handler has
530 returned. That makes them like 'return' instructions; we
531 shouldn't relocate %eip.
533 But most system calls don't, and we do need to relocate %eip.
535 Our heuristic for distinguishing these cases: if stepping
536 over the system call instruction left control directly after
537 the instruction, the we relocate --- control almost certainly
538 doesn't belong in the displaced copy. Otherwise, we assume
539 the instruction has put control where it belongs, and leave
540 it unrelocated. Goodness help us if there are PC-relative
542 if (i386_syscall_p (insn
, &insn_len
)
543 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
546 fprintf_unfiltered (gdb_stdlog
,
547 "displaced: syscall changed %%eip; "
552 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
554 /* If we just stepped over a breakpoint insn, we don't backup
555 the pc on purpose; this is to match behaviour without
558 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
561 fprintf_unfiltered (gdb_stdlog
,
563 "relocated %%eip from %s to %s\n",
564 paddress (gdbarch
, orig_eip
),
565 paddress (gdbarch
, eip
));
569 /* If the instruction was PUSHFL, then the TF bit will be set in the
570 pushed value, and should be cleared. We'll leave this for later,
571 since GDB already messes up the TF flag when stepping over a
574 /* If the instruction was a call, the return address now atop the
575 stack is the address following the copied instruction. We need
576 to make it the address following the original instruction. */
577 if (i386_call_p (insn
))
581 const ULONGEST retaddr_len
= 4;
583 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
584 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
585 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
586 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
589 fprintf_unfiltered (gdb_stdlog
,
590 "displaced: relocated return addr at %s to %s\n",
591 paddress (gdbarch
, esp
),
592 paddress (gdbarch
, retaddr
));
596 #ifdef I386_REGNO_TO_SYMMETRY
597 #error "The Sequent Symmetry is no longer supported."
600 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
601 and %esp "belong" to the calling function. Therefore these
602 registers should be saved if they're going to be modified. */
604 /* The maximum number of saved registers. This should include all
605 registers mentioned above, and %eip. */
606 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
608 struct i386_frame_cache
615 /* Saved registers. */
616 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
621 /* Stack space reserved for local variables. */
625 /* Allocate and initialize a frame cache. */
627 static struct i386_frame_cache
*
628 i386_alloc_frame_cache (void)
630 struct i386_frame_cache
*cache
;
633 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
637 cache
->sp_offset
= -4;
640 /* Saved registers. We initialize these to -1 since zero is a valid
641 offset (that's where %ebp is supposed to be stored). */
642 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
643 cache
->saved_regs
[i
] = -1;
645 cache
->saved_sp_reg
= -1;
646 cache
->pc_in_eax
= 0;
648 /* Frameless until proven otherwise. */
654 /* If the instruction at PC is a jump, return the address of its
655 target. Otherwise, return PC. */
658 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
660 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
665 target_read_memory (pc
, &op
, 1);
669 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
675 /* Relative jump: if data16 == 0, disp32, else disp16. */
678 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
680 /* Include the size of the jmp instruction (including the
686 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
688 /* Include the size of the jmp instruction. */
693 /* Relative jump, disp8 (ignore data16). */
694 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
703 /* Check whether PC points at a prologue for a function returning a
704 structure or union. If so, it updates CACHE and returns the
705 address of the first instruction after the code sequence that
706 removes the "hidden" argument from the stack or CURRENT_PC,
707 whichever is smaller. Otherwise, return PC. */
710 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
711 struct i386_frame_cache
*cache
)
713 /* Functions that return a structure or union start with:
716 xchgl %eax, (%esp) 0x87 0x04 0x24
717 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
719 (the System V compiler puts out the second `xchg' instruction,
720 and the assembler doesn't try to optimize it, so the 'sib' form
721 gets generated). This sequence is used to get the address of the
722 return buffer for a function that returns a structure. */
723 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
724 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
728 if (current_pc
<= pc
)
731 target_read_memory (pc
, &op
, 1);
733 if (op
!= 0x58) /* popl %eax */
736 target_read_memory (pc
+ 1, buf
, 4);
737 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
740 if (current_pc
== pc
)
742 cache
->sp_offset
+= 4;
746 if (current_pc
== pc
+ 1)
748 cache
->pc_in_eax
= 1;
752 if (buf
[1] == proto1
[1])
759 i386_skip_probe (CORE_ADDR pc
)
761 /* A function may start with
775 target_read_memory (pc
, &op
, 1);
777 if (op
== 0x68 || op
== 0x6a)
781 /* Skip past the `pushl' instruction; it has either a one-byte or a
782 four-byte operand, depending on the opcode. */
788 /* Read the following 8 bytes, which should be `call _probe' (6
789 bytes) followed by `addl $4,%esp' (2 bytes). */
790 read_memory (pc
+ delta
, buf
, sizeof (buf
));
791 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
792 pc
+= delta
+ sizeof (buf
);
798 /* GCC 4.1 and later, can put code in the prologue to realign the
799 stack pointer. Check whether PC points to such code, and update
800 CACHE accordingly. Return the first instruction after the code
801 sequence or CURRENT_PC, whichever is smaller. If we don't
802 recognize the code, return PC. */
805 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
806 struct i386_frame_cache
*cache
)
808 /* There are 2 code sequences to re-align stack before the frame
811 1. Use a caller-saved saved register:
817 2. Use a callee-saved saved register:
824 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
826 0x83 0xe4 0xf0 andl $-16, %esp
827 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
832 int offset
, offset_and
;
833 static int regnums
[8] = {
834 I386_EAX_REGNUM
, /* %eax */
835 I386_ECX_REGNUM
, /* %ecx */
836 I386_EDX_REGNUM
, /* %edx */
837 I386_EBX_REGNUM
, /* %ebx */
838 I386_ESP_REGNUM
, /* %esp */
839 I386_EBP_REGNUM
, /* %ebp */
840 I386_ESI_REGNUM
, /* %esi */
841 I386_EDI_REGNUM
/* %edi */
844 if (target_read_memory (pc
, buf
, sizeof buf
))
847 /* Check caller-saved saved register. The first instruction has
848 to be "leal 4(%esp), %reg". */
849 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
851 /* MOD must be binary 10 and R/M must be binary 100. */
852 if ((buf
[1] & 0xc7) != 0x44)
855 /* REG has register number. */
856 reg
= (buf
[1] >> 3) & 7;
861 /* Check callee-saved saved register. The first instruction
862 has to be "pushl %reg". */
863 if ((buf
[0] & 0xf8) != 0x50)
869 /* The next instruction has to be "leal 8(%esp), %reg". */
870 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
873 /* MOD must be binary 10 and R/M must be binary 100. */
874 if ((buf
[2] & 0xc7) != 0x44)
877 /* REG has register number. Registers in pushl and leal have to
879 if (reg
!= ((buf
[2] >> 3) & 7))
885 /* Rigister can't be %esp nor %ebp. */
886 if (reg
== 4 || reg
== 5)
889 /* The next instruction has to be "andl $-XXX, %esp". */
890 if (buf
[offset
+ 1] != 0xe4
891 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
895 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
897 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
898 0xfc. REG must be binary 110 and MOD must be binary 01. */
899 if (buf
[offset
] != 0xff
900 || buf
[offset
+ 2] != 0xfc
901 || (buf
[offset
+ 1] & 0xf8) != 0x70)
904 /* R/M has register. Registers in leal and pushl have to be the
906 if (reg
!= (buf
[offset
+ 1] & 7))
909 if (current_pc
> pc
+ offset_and
)
910 cache
->saved_sp_reg
= regnums
[reg
];
912 return min (pc
+ offset
+ 3, current_pc
);
915 /* Maximum instruction length we need to handle. */
916 #define I386_MAX_MATCHED_INSN_LEN 6
918 /* Instruction description. */
922 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
923 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
926 /* Search for the instruction at PC in the list SKIP_INSNS. Return
927 the first instruction description that matches. Otherwise, return
930 static struct i386_insn
*
931 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
933 struct i386_insn
*insn
;
936 target_read_memory (pc
, &op
, 1);
938 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
940 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
942 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
943 int insn_matched
= 1;
946 gdb_assert (insn
->len
> 1);
947 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
949 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
950 for (i
= 1; i
< insn
->len
; i
++)
952 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
964 /* Some special instructions that might be migrated by GCC into the
965 part of the prologue that sets up the new stack frame. Because the
966 stack frame hasn't been setup yet, no registers have been saved
967 yet, and only the scratch registers %eax, %ecx and %edx can be
970 struct i386_insn i386_frame_setup_skip_insns
[] =
972 /* Check for `movb imm8, r' and `movl imm32, r'.
974 ??? Should we handle 16-bit operand-sizes here? */
976 /* `movb imm8, %al' and `movb imm8, %ah' */
977 /* `movb imm8, %cl' and `movb imm8, %ch' */
978 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
979 /* `movb imm8, %dl' and `movb imm8, %dh' */
980 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
981 /* `movl imm32, %eax' and `movl imm32, %ecx' */
982 { 5, { 0xb8 }, { 0xfe } },
983 /* `movl imm32, %edx' */
984 { 5, { 0xba }, { 0xff } },
986 /* Check for `mov imm32, r32'. Note that there is an alternative
987 encoding for `mov m32, %eax'.
989 ??? Should we handle SIB adressing here?
990 ??? Should we handle 16-bit operand-sizes here? */
992 /* `movl m32, %eax' */
993 { 5, { 0xa1 }, { 0xff } },
994 /* `movl m32, %eax' and `mov; m32, %ecx' */
995 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
996 /* `movl m32, %edx' */
997 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
999 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1000 Because of the symmetry, there are actually two ways to encode
1001 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1002 opcode bytes 0x31 and 0x33 for `xorl'. */
1004 /* `subl %eax, %eax' */
1005 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1006 /* `subl %ecx, %ecx' */
1007 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1008 /* `subl %edx, %edx' */
1009 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1010 /* `xorl %eax, %eax' */
1011 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1012 /* `xorl %ecx, %ecx' */
1013 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1014 /* `xorl %edx, %edx' */
1015 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1020 /* Check whether PC points to a no-op instruction. */
1022 i386_skip_noop (CORE_ADDR pc
)
1027 target_read_memory (pc
, &op
, 1);
1032 /* Ignore `nop' instruction. */
1036 target_read_memory (pc
, &op
, 1);
1039 /* Ignore no-op instruction `mov %edi, %edi'.
1040 Microsoft system dlls often start with
1041 a `mov %edi,%edi' instruction.
1042 The 5 bytes before the function start are
1043 filled with `nop' instructions.
1044 This pattern can be used for hot-patching:
1045 The `mov %edi, %edi' instruction can be replaced by a
1046 near jump to the location of the 5 `nop' instructions
1047 which can be replaced by a 32-bit jump to anywhere
1048 in the 32-bit address space. */
1050 else if (op
== 0x8b)
1052 target_read_memory (pc
+ 1, &op
, 1);
1056 target_read_memory (pc
, &op
, 1);
1064 /* Check whether PC points at a code that sets up a new stack frame.
1065 If so, it updates CACHE and returns the address of the first
1066 instruction after the sequence that sets up the frame or LIMIT,
1067 whichever is smaller. If we don't recognize the code, return PC. */
1070 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1071 CORE_ADDR pc
, CORE_ADDR limit
,
1072 struct i386_frame_cache
*cache
)
1074 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1075 struct i386_insn
*insn
;
1082 target_read_memory (pc
, &op
, 1);
1084 if (op
== 0x55) /* pushl %ebp */
1086 /* Take into account that we've executed the `pushl %ebp' that
1087 starts this instruction sequence. */
1088 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1089 cache
->sp_offset
+= 4;
1092 /* If that's all, return now. */
1096 /* Check for some special instructions that might be migrated by
1097 GCC into the prologue and skip them. At this point in the
1098 prologue, code should only touch the scratch registers %eax,
1099 %ecx and %edx, so while the number of posibilities is sheer,
1102 Make sure we only skip these instructions if we later see the
1103 `movl %esp, %ebp' that actually sets up the frame. */
1104 while (pc
+ skip
< limit
)
1106 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1113 /* If that's all, return now. */
1114 if (limit
<= pc
+ skip
)
1117 target_read_memory (pc
+ skip
, &op
, 1);
1119 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1123 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1128 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1136 /* OK, we actually have a frame. We just don't know how large
1137 it is yet. Set its size to zero. We'll adjust it if
1138 necessary. We also now commit to skipping the special
1139 instructions mentioned before. */
1143 /* If that's all, return now. */
1147 /* Check for stack adjustment
1151 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1152 reg, so we don't have to worry about a data16 prefix. */
1153 target_read_memory (pc
, &op
, 1);
1156 /* `subl' with 8-bit immediate. */
1157 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1158 /* Some instruction starting with 0x83 other than `subl'. */
1161 /* `subl' with signed 8-bit immediate (though it wouldn't
1162 make sense to be negative). */
1163 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1166 else if (op
== 0x81)
1168 /* Maybe it is `subl' with a 32-bit immediate. */
1169 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1170 /* Some instruction starting with 0x81 other than `subl'. */
1173 /* It is `subl' with a 32-bit immediate. */
1174 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1179 /* Some instruction other than `subl'. */
1183 else if (op
== 0xc8) /* enter */
1185 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1192 /* Check whether PC points at code that saves registers on the stack.
1193 If so, it updates CACHE and returns the address of the first
1194 instruction after the register saves or CURRENT_PC, whichever is
1195 smaller. Otherwise, return PC. */
1198 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1199 struct i386_frame_cache
*cache
)
1201 CORE_ADDR offset
= 0;
1205 if (cache
->locals
> 0)
1206 offset
-= cache
->locals
;
1207 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1209 target_read_memory (pc
, &op
, 1);
1210 if (op
< 0x50 || op
> 0x57)
1214 cache
->saved_regs
[op
- 0x50] = offset
;
1215 cache
->sp_offset
+= 4;
1222 /* Do a full analysis of the prologue at PC and update CACHE
1223 accordingly. Bail out early if CURRENT_PC is reached. Return the
1224 address where the analysis stopped.
1226 We handle these cases:
1228 The startup sequence can be at the start of the function, or the
1229 function can start with a branch to startup code at the end.
1231 %ebp can be set up with either the 'enter' instruction, or "pushl
1232 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1233 once used in the System V compiler).
1235 Local space is allocated just below the saved %ebp by either the
1236 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1237 16-bit unsigned argument for space to allocate, and the 'addl'
1238 instruction could have either a signed byte, or 32-bit immediate.
1240 Next, the registers used by this function are pushed. With the
1241 System V compiler they will always be in the order: %edi, %esi,
1242 %ebx (and sometimes a harmless bug causes it to also save but not
1243 restore %eax); however, the code below is willing to see the pushes
1244 in any order, and will handle up to 8 of them.
1246 If the setup sequence is at the end of the function, then the next
1247 instruction will be a branch back to the start. */
1250 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1251 CORE_ADDR pc
, CORE_ADDR current_pc
,
1252 struct i386_frame_cache
*cache
)
1254 pc
= i386_skip_noop (pc
);
1255 pc
= i386_follow_jump (gdbarch
, pc
);
1256 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1257 pc
= i386_skip_probe (pc
);
1258 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1259 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1260 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1263 /* Return PC of first real instruction. */
1266 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1268 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1270 static gdb_byte pic_pat
[6] =
1272 0xe8, 0, 0, 0, 0, /* call 0x0 */
1273 0x5b, /* popl %ebx */
1275 struct i386_frame_cache cache
;
1281 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1282 if (cache
.locals
< 0)
1285 /* Found valid frame setup. */
1287 /* The native cc on SVR4 in -K PIC mode inserts the following code
1288 to get the address of the global offset table (GOT) into register
1293 movl %ebx,x(%ebp) (optional)
1296 This code is with the rest of the prologue (at the end of the
1297 function), so we have to skip it to get to the first real
1298 instruction at the start of the function. */
1300 for (i
= 0; i
< 6; i
++)
1302 target_read_memory (pc
+ i
, &op
, 1);
1303 if (pic_pat
[i
] != op
)
1310 target_read_memory (pc
+ delta
, &op
, 1);
1312 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1314 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1316 if (op
== 0x5d) /* One byte offset from %ebp. */
1318 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1320 else /* Unexpected instruction. */
1323 target_read_memory (pc
+ delta
, &op
, 1);
1327 if (delta
> 0 && op
== 0x81
1328 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1335 /* If the function starts with a branch (to startup code at the end)
1336 the last instruction should bring us back to the first
1337 instruction of the real code. */
1338 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1339 pc
= i386_follow_jump (gdbarch
, pc
);
1344 /* Check that the code pointed to by PC corresponds to a call to
1345 __main, skip it if so. Return PC otherwise. */
1348 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1350 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1353 target_read_memory (pc
, &op
, 1);
1358 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1360 /* Make sure address is computed correctly as a 32bit
1361 integer even if CORE_ADDR is 64 bit wide. */
1362 struct minimal_symbol
*s
;
1363 CORE_ADDR call_dest
;
1365 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1366 call_dest
= call_dest
& 0xffffffffU
;
1367 s
= lookup_minimal_symbol_by_pc (call_dest
);
1369 && SYMBOL_LINKAGE_NAME (s
) != NULL
1370 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1378 /* This function is 64-bit safe. */
1381 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1385 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1386 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1390 /* Normal frames. */
1392 static struct i386_frame_cache
*
1393 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1395 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1396 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1397 struct i386_frame_cache
*cache
;
1404 cache
= i386_alloc_frame_cache ();
1405 *this_cache
= cache
;
1407 /* In principle, for normal frames, %ebp holds the frame pointer,
1408 which holds the base address for the current stack frame.
1409 However, for functions that don't need it, the frame pointer is
1410 optional. For these "frameless" functions the frame pointer is
1411 actually the frame pointer of the calling frame. Signal
1412 trampolines are just a special case of a "frameless" function.
1413 They (usually) share their frame pointer with the frame that was
1414 in progress when the signal occurred. */
1416 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1417 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1418 if (cache
->base
== 0)
1421 /* For normal frames, %eip is stored at 4(%ebp). */
1422 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1424 cache
->pc
= get_frame_func (this_frame
);
1426 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1429 if (cache
->saved_sp_reg
!= -1)
1431 /* Saved stack pointer has been saved. */
1432 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1433 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1436 if (cache
->locals
< 0)
1438 /* We didn't find a valid frame, which means that CACHE->base
1439 currently holds the frame pointer for our calling frame. If
1440 we're at the start of a function, or somewhere half-way its
1441 prologue, the function's frame probably hasn't been fully
1442 setup yet. Try to reconstruct the base address for the stack
1443 frame by looking at the stack pointer. For truly "frameless"
1444 functions this might work too. */
1446 if (cache
->saved_sp_reg
!= -1)
1448 /* We're halfway aligning the stack. */
1449 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1450 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1452 /* This will be added back below. */
1453 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1455 else if (cache
->pc
!= 0
1456 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1458 /* We're in a known function, but did not find a frame
1459 setup. Assume that the function does not use %ebp.
1460 Alternatively, we may have jumped to an invalid
1461 address; in that case there is definitely no new
1463 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1464 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1468 /* We're in an unknown function. We could not find the start
1469 of the function to analyze the prologue; our best option is
1470 to assume a typical frame layout with the caller's %ebp
1472 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1475 /* Now that we have the base address for the stack frame we can
1476 calculate the value of %esp in the calling frame. */
1477 if (cache
->saved_sp
== 0)
1478 cache
->saved_sp
= cache
->base
+ 8;
1480 /* Adjust all the saved registers such that they contain addresses
1481 instead of offsets. */
1482 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1483 if (cache
->saved_regs
[i
] != -1)
1484 cache
->saved_regs
[i
] += cache
->base
;
1490 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1491 struct frame_id
*this_id
)
1493 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1495 /* This marks the outermost frame. */
1496 if (cache
->base
== 0)
1499 /* See the end of i386_push_dummy_call. */
1500 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1503 static struct value
*
1504 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1507 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1509 gdb_assert (regnum
>= 0);
1511 /* The System V ABI says that:
1513 "The flags register contains the system flags, such as the
1514 direction flag and the carry flag. The direction flag must be
1515 set to the forward (that is, zero) direction before entry and
1516 upon exit from a function. Other user flags have no specified
1517 role in the standard calling sequence and are not preserved."
1519 To guarantee the "upon exit" part of that statement we fake a
1520 saved flags register that has its direction flag cleared.
1522 Note that GCC doesn't seem to rely on the fact that the direction
1523 flag is cleared after a function return; it always explicitly
1524 clears the flag before operations where it matters.
1526 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1527 right thing to do. The way we fake the flags register here makes
1528 it impossible to change it. */
1530 if (regnum
== I386_EFLAGS_REGNUM
)
1534 val
= get_frame_register_unsigned (this_frame
, regnum
);
1536 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1539 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1540 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1542 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1543 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1545 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1546 return frame_unwind_got_memory (this_frame
, regnum
,
1547 cache
->saved_regs
[regnum
]);
1549 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1552 static const struct frame_unwind i386_frame_unwind
=
1556 i386_frame_prev_register
,
1558 default_frame_sniffer
1561 /* Normal frames, but in a function epilogue. */
1563 /* The epilogue is defined here as the 'ret' instruction, which will
1564 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1565 the function's stack frame. */
1568 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1572 if (target_read_memory (pc
, &insn
, 1))
1573 return 0; /* Can't read memory at pc. */
1575 if (insn
!= 0xc3) /* 'ret' instruction. */
1582 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1583 struct frame_info
*this_frame
,
1584 void **this_prologue_cache
)
1586 if (frame_relative_level (this_frame
) == 0)
1587 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1588 get_frame_pc (this_frame
));
1593 static struct i386_frame_cache
*
1594 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1596 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1597 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1598 struct i386_frame_cache
*cache
;
1604 cache
= i386_alloc_frame_cache ();
1605 *this_cache
= cache
;
1607 /* Cache base will be %esp plus cache->sp_offset (-4). */
1608 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1609 cache
->base
= extract_unsigned_integer (buf
, 4,
1610 byte_order
) + cache
->sp_offset
;
1612 /* Cache pc will be the frame func. */
1613 cache
->pc
= get_frame_pc (this_frame
);
1615 /* The saved %esp will be at cache->base plus 8. */
1616 cache
->saved_sp
= cache
->base
+ 8;
1618 /* The saved %eip will be at cache->base plus 4. */
1619 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1625 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1627 struct frame_id
*this_id
)
1629 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1632 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1635 static const struct frame_unwind i386_epilogue_frame_unwind
=
1638 i386_epilogue_frame_this_id
,
1639 i386_frame_prev_register
,
1641 i386_epilogue_frame_sniffer
1645 /* Signal trampolines. */
1647 static struct i386_frame_cache
*
1648 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1650 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1652 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1653 struct i386_frame_cache
*cache
;
1660 cache
= i386_alloc_frame_cache ();
1662 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1663 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1665 addr
= tdep
->sigcontext_addr (this_frame
);
1666 if (tdep
->sc_reg_offset
)
1670 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1672 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1673 if (tdep
->sc_reg_offset
[i
] != -1)
1674 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1678 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1679 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1682 *this_cache
= cache
;
1687 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1688 struct frame_id
*this_id
)
1690 struct i386_frame_cache
*cache
=
1691 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1693 /* See the end of i386_push_dummy_call. */
1694 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1697 static struct value
*
1698 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1699 void **this_cache
, int regnum
)
1701 /* Make sure we've initialized the cache. */
1702 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1704 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1708 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1709 struct frame_info
*this_frame
,
1710 void **this_prologue_cache
)
1712 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1714 /* We shouldn't even bother if we don't have a sigcontext_addr
1716 if (tdep
->sigcontext_addr
== NULL
)
1719 if (tdep
->sigtramp_p
!= NULL
)
1721 if (tdep
->sigtramp_p (this_frame
))
1725 if (tdep
->sigtramp_start
!= 0)
1727 CORE_ADDR pc
= get_frame_pc (this_frame
);
1729 gdb_assert (tdep
->sigtramp_end
!= 0);
1730 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1737 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1740 i386_sigtramp_frame_this_id
,
1741 i386_sigtramp_frame_prev_register
,
1743 i386_sigtramp_frame_sniffer
1748 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1750 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1755 static const struct frame_base i386_frame_base
=
1758 i386_frame_base_address
,
1759 i386_frame_base_address
,
1760 i386_frame_base_address
1763 static struct frame_id
1764 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1768 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1770 /* See the end of i386_push_dummy_call. */
1771 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1775 /* Figure out where the longjmp will land. Slurp the args out of the
1776 stack. We expect the first arg to be a pointer to the jmp_buf
1777 structure from which we extract the address that we will land at.
1778 This address is copied into PC. This routine returns non-zero on
1782 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1785 CORE_ADDR sp
, jb_addr
;
1786 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1787 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1788 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1790 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1791 longjmp will land. */
1792 if (jb_pc_offset
== -1)
1795 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1796 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1797 if (target_read_memory (sp
+ 4, buf
, 4))
1800 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1801 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1804 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1809 /* Check whether TYPE must be 16-byte-aligned when passed as a
1810 function argument. 16-byte vectors, _Decimal128 and structures or
1811 unions containing such types must be 16-byte-aligned; other
1812 arguments are 4-byte-aligned. */
1815 i386_16_byte_align_p (struct type
*type
)
1817 type
= check_typedef (type
);
1818 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1819 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1820 && TYPE_LENGTH (type
) == 16)
1822 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1823 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1824 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1825 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1828 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1830 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1838 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1839 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1840 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1841 CORE_ADDR struct_addr
)
1843 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1849 /* Determine the total space required for arguments and struct
1850 return address in a first pass (allowing for 16-byte-aligned
1851 arguments), then push arguments in a second pass. */
1853 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1855 int args_space_used
= 0;
1856 int have_16_byte_aligned_arg
= 0;
1862 /* Push value address. */
1863 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1864 write_memory (sp
, buf
, 4);
1865 args_space_used
+= 4;
1871 for (i
= 0; i
< nargs
; i
++)
1873 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1877 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1878 args_space_used
= align_up (args_space_used
, 16);
1880 write_memory (sp
+ args_space_used
,
1881 value_contents_all (args
[i
]), len
);
1882 /* The System V ABI says that:
1884 "An argument's size is increased, if necessary, to make it a
1885 multiple of [32-bit] words. This may require tail padding,
1886 depending on the size of the argument."
1888 This makes sure the stack stays word-aligned. */
1889 args_space_used
+= align_up (len
, 4);
1893 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1895 args_space
= align_up (args_space
, 16);
1896 have_16_byte_aligned_arg
= 1;
1898 args_space
+= align_up (len
, 4);
1904 if (have_16_byte_aligned_arg
)
1905 args_space
= align_up (args_space
, 16);
1910 /* Store return address. */
1912 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1913 write_memory (sp
, buf
, 4);
1915 /* Finally, update the stack pointer... */
1916 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1917 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1919 /* ...and fake a frame pointer. */
1920 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1922 /* MarkK wrote: This "+ 8" is all over the place:
1923 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1924 i386_dummy_id). It's there, since all frame unwinders for
1925 a given target have to agree (within a certain margin) on the
1926 definition of the stack address of a frame. Otherwise frame id
1927 comparison might not work correctly. Since DWARF2/GCC uses the
1928 stack address *before* the function call as a frame's CFA. On
1929 the i386, when %ebp is used as a frame pointer, the offset
1930 between the contents %ebp and the CFA as defined by GCC. */
1934 /* These registers are used for returning integers (and on some
1935 targets also for returning `struct' and `union' values when their
1936 size and alignment match an integer type). */
1937 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1938 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1940 /* Read, for architecture GDBARCH, a function return value of TYPE
1941 from REGCACHE, and copy that into VALBUF. */
1944 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1945 struct regcache
*regcache
, gdb_byte
*valbuf
)
1947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1948 int len
= TYPE_LENGTH (type
);
1949 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1951 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1953 if (tdep
->st0_regnum
< 0)
1955 warning (_("Cannot find floating-point return value."));
1956 memset (valbuf
, 0, len
);
1960 /* Floating-point return values can be found in %st(0). Convert
1961 its contents to the desired type. This is probably not
1962 exactly how it would happen on the target itself, but it is
1963 the best we can do. */
1964 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1965 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1969 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1970 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1972 if (len
<= low_size
)
1974 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1975 memcpy (valbuf
, buf
, len
);
1977 else if (len
<= (low_size
+ high_size
))
1979 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1980 memcpy (valbuf
, buf
, low_size
);
1981 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1982 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1985 internal_error (__FILE__
, __LINE__
,
1986 _("Cannot extract return value of %d bytes long."), len
);
1990 /* Write, for architecture GDBARCH, a function return value of TYPE
1991 from VALBUF into REGCACHE. */
1994 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1995 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1998 int len
= TYPE_LENGTH (type
);
2000 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2003 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2005 if (tdep
->st0_regnum
< 0)
2007 warning (_("Cannot set floating-point return value."));
2011 /* Returning floating-point values is a bit tricky. Apart from
2012 storing the return value in %st(0), we have to simulate the
2013 state of the FPU at function return point. */
2015 /* Convert the value found in VALBUF to the extended
2016 floating-point format used by the FPU. This is probably
2017 not exactly how it would happen on the target itself, but
2018 it is the best we can do. */
2019 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2020 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2022 /* Set the top of the floating-point register stack to 7. The
2023 actual value doesn't really matter, but 7 is what a normal
2024 function return would end up with if the program started out
2025 with a freshly initialized FPU. */
2026 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2028 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2030 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2031 the floating-point register stack to 7, the appropriate value
2032 for the tag word is 0x3fff. */
2033 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2037 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2038 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2040 if (len
<= low_size
)
2041 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2042 else if (len
<= (low_size
+ high_size
))
2044 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2045 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2046 len
- low_size
, valbuf
+ low_size
);
2049 internal_error (__FILE__
, __LINE__
,
2050 _("Cannot store return value of %d bytes long."), len
);
2055 /* This is the variable that is set with "set struct-convention", and
2056 its legitimate values. */
2057 static const char default_struct_convention
[] = "default";
2058 static const char pcc_struct_convention
[] = "pcc";
2059 static const char reg_struct_convention
[] = "reg";
2060 static const char *valid_conventions
[] =
2062 default_struct_convention
,
2063 pcc_struct_convention
,
2064 reg_struct_convention
,
2067 static const char *struct_convention
= default_struct_convention
;
2069 /* Return non-zero if TYPE, which is assumed to be a structure,
2070 a union type, or an array type, should be returned in registers
2071 for architecture GDBARCH. */
2074 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2076 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2077 enum type_code code
= TYPE_CODE (type
);
2078 int len
= TYPE_LENGTH (type
);
2080 gdb_assert (code
== TYPE_CODE_STRUCT
2081 || code
== TYPE_CODE_UNION
2082 || code
== TYPE_CODE_ARRAY
);
2084 if (struct_convention
== pcc_struct_convention
2085 || (struct_convention
== default_struct_convention
2086 && tdep
->struct_return
== pcc_struct_return
))
2089 /* Structures consisting of a single `float', `double' or 'long
2090 double' member are returned in %st(0). */
2091 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2093 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2094 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2095 return (len
== 4 || len
== 8 || len
== 12);
2098 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2101 /* Determine, for architecture GDBARCH, how a return value of TYPE
2102 should be returned. If it is supposed to be returned in registers,
2103 and READBUF is non-zero, read the appropriate value from REGCACHE,
2104 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2105 from WRITEBUF into REGCACHE. */
2107 static enum return_value_convention
2108 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2109 struct type
*type
, struct regcache
*regcache
,
2110 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2112 enum type_code code
= TYPE_CODE (type
);
2114 if (((code
== TYPE_CODE_STRUCT
2115 || code
== TYPE_CODE_UNION
2116 || code
== TYPE_CODE_ARRAY
)
2117 && !i386_reg_struct_return_p (gdbarch
, type
))
2118 /* 128-bit decimal float uses the struct return convention. */
2119 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2121 /* The System V ABI says that:
2123 "A function that returns a structure or union also sets %eax
2124 to the value of the original address of the caller's area
2125 before it returns. Thus when the caller receives control
2126 again, the address of the returned object resides in register
2127 %eax and can be used to access the object."
2129 So the ABI guarantees that we can always find the return
2130 value just after the function has returned. */
2132 /* Note that the ABI doesn't mention functions returning arrays,
2133 which is something possible in certain languages such as Ada.
2134 In this case, the value is returned as if it was wrapped in
2135 a record, so the convention applied to records also applies
2142 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2143 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2146 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2149 /* This special case is for structures consisting of a single
2150 `float', `double' or 'long double' member. These structures are
2151 returned in %st(0). For these structures, we call ourselves
2152 recursively, changing TYPE into the type of the first member of
2153 the structure. Since that should work for all structures that
2154 have only one member, we don't bother to check the member's type
2156 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2158 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2159 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2164 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2166 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2168 return RETURN_VALUE_REGISTER_CONVENTION
;
2173 i387_ext_type (struct gdbarch
*gdbarch
)
2175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2177 if (!tdep
->i387_ext_type
)
2179 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2180 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2183 return tdep
->i387_ext_type
;
2186 /* Construct vector type for MMX registers. */
2187 static struct type
*
2188 i386_mmx_type (struct gdbarch
*gdbarch
)
2190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2192 if (!tdep
->i386_mmx_type
)
2194 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2196 /* The type we're building is this: */
2198 union __gdb_builtin_type_vec64i
2201 int32_t v2_int32
[2];
2202 int16_t v4_int16
[4];
2209 t
= arch_composite_type (gdbarch
,
2210 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2212 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2213 append_composite_type_field (t
, "v2_int32",
2214 init_vector_type (bt
->builtin_int32
, 2));
2215 append_composite_type_field (t
, "v4_int16",
2216 init_vector_type (bt
->builtin_int16
, 4));
2217 append_composite_type_field (t
, "v8_int8",
2218 init_vector_type (bt
->builtin_int8
, 8));
2220 TYPE_VECTOR (t
) = 1;
2221 TYPE_NAME (t
) = "builtin_type_vec64i";
2222 tdep
->i386_mmx_type
= t
;
2225 return tdep
->i386_mmx_type
;
2228 /* Return the GDB type object for the "standard" data type of data in
2231 static struct type
*
2232 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2234 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2235 return i386_mmx_type (gdbarch
);
2238 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2239 if (i386_byte_regnum_p (gdbarch
, regnum
))
2240 return bt
->builtin_int8
;
2241 else if (i386_word_regnum_p (gdbarch
, regnum
))
2242 return bt
->builtin_int16
;
2243 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2244 return bt
->builtin_int32
;
2247 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2250 /* Map a cooked register onto a raw register or memory. For the i386,
2251 the MMX registers need to be mapped onto floating point registers. */
2254 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2261 mmxreg
= regnum
- tdep
->mm0_regnum
;
2262 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2263 tos
= (fstat
>> 11) & 0x7;
2264 fpreg
= (mmxreg
+ tos
) % 8;
2266 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2270 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2271 int regnum
, gdb_byte
*buf
)
2273 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2277 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2279 /* Extract (always little endian). */
2280 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2281 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2287 if (i386_word_regnum_p (gdbarch
, regnum
))
2289 int gpnum
= regnum
- tdep
->ax_regnum
;
2291 /* Extract (always little endian). */
2292 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2293 memcpy (buf
, raw_buf
, 2);
2295 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2297 /* Check byte pseudo registers last since this function will
2298 be called from amd64_pseudo_register_read, which handles
2299 byte pseudo registers differently. */
2300 int gpnum
= regnum
- tdep
->al_regnum
;
2302 /* Extract (always little endian). We read both lower and
2304 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2306 memcpy (buf
, raw_buf
+ 1, 1);
2308 memcpy (buf
, raw_buf
, 1);
2311 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2316 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2317 int regnum
, const gdb_byte
*buf
)
2319 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2321 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2323 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2326 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2327 /* ... Modify ... (always little endian). */
2328 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2330 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2336 if (i386_word_regnum_p (gdbarch
, regnum
))
2338 int gpnum
= regnum
- tdep
->ax_regnum
;
2341 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2342 /* ... Modify ... (always little endian). */
2343 memcpy (raw_buf
, buf
, 2);
2345 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2347 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2349 /* Check byte pseudo registers last since this function will
2350 be called from amd64_pseudo_register_read, which handles
2351 byte pseudo registers differently. */
2352 int gpnum
= regnum
- tdep
->al_regnum
;
2354 /* Read ... We read both lower and upper registers. */
2355 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2356 /* ... Modify ... (always little endian). */
2358 memcpy (raw_buf
+ 1, buf
, 1);
2360 memcpy (raw_buf
, buf
, 1);
2362 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2365 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2370 /* Return the register number of the register allocated by GCC after
2371 REGNUM, or -1 if there is no such register. */
2374 i386_next_regnum (int regnum
)
2376 /* GCC allocates the registers in the order:
2378 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2380 Since storing a variable in %esp doesn't make any sense we return
2381 -1 for %ebp and for %esp itself. */
2382 static int next_regnum
[] =
2384 I386_EDX_REGNUM
, /* Slot for %eax. */
2385 I386_EBX_REGNUM
, /* Slot for %ecx. */
2386 I386_ECX_REGNUM
, /* Slot for %edx. */
2387 I386_ESI_REGNUM
, /* Slot for %ebx. */
2388 -1, -1, /* Slots for %esp and %ebp. */
2389 I386_EDI_REGNUM
, /* Slot for %esi. */
2390 I386_EBP_REGNUM
/* Slot for %edi. */
2393 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2394 return next_regnum
[regnum
];
2399 /* Return nonzero if a value of type TYPE stored in register REGNUM
2400 needs any special handling. */
2403 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2405 int len
= TYPE_LENGTH (type
);
2407 /* Values may be spread across multiple registers. Most debugging
2408 formats aren't expressive enough to specify the locations, so
2409 some heuristics is involved. Right now we only handle types that
2410 have a length that is a multiple of the word size, since GCC
2411 doesn't seem to put any other types into registers. */
2412 if (len
> 4 && len
% 4 == 0)
2414 int last_regnum
= regnum
;
2418 last_regnum
= i386_next_regnum (last_regnum
);
2422 if (last_regnum
!= -1)
2426 return i387_convert_register_p (gdbarch
, regnum
, type
);
2429 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2430 return its contents in TO. */
2433 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2434 struct type
*type
, gdb_byte
*to
)
2436 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2437 int len
= TYPE_LENGTH (type
);
2439 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2440 available in FRAME (i.e. if it wasn't saved)? */
2442 if (i386_fp_regnum_p (gdbarch
, regnum
))
2444 i387_register_to_value (frame
, regnum
, type
, to
);
2448 /* Read a value spread across multiple registers. */
2450 gdb_assert (len
> 4 && len
% 4 == 0);
2454 gdb_assert (regnum
!= -1);
2455 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2457 get_frame_register (frame
, regnum
, to
);
2458 regnum
= i386_next_regnum (regnum
);
2464 /* Write the contents FROM of a value of type TYPE into register
2465 REGNUM in frame FRAME. */
2468 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2469 struct type
*type
, const gdb_byte
*from
)
2471 int len
= TYPE_LENGTH (type
);
2473 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2475 i387_value_to_register (frame
, regnum
, type
, from
);
2479 /* Write a value spread across multiple registers. */
2481 gdb_assert (len
> 4 && len
% 4 == 0);
2485 gdb_assert (regnum
!= -1);
2486 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2488 put_frame_register (frame
, regnum
, from
);
2489 regnum
= i386_next_regnum (regnum
);
2495 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2496 in the general-purpose register set REGSET to register cache
2497 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2500 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2501 int regnum
, const void *gregs
, size_t len
)
2503 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2504 const gdb_byte
*regs
= gregs
;
2507 gdb_assert (len
== tdep
->sizeof_gregset
);
2509 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2511 if ((regnum
== i
|| regnum
== -1)
2512 && tdep
->gregset_reg_offset
[i
] != -1)
2513 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2517 /* Collect register REGNUM from the register cache REGCACHE and store
2518 it in the buffer specified by GREGS and LEN as described by the
2519 general-purpose register set REGSET. If REGNUM is -1, do this for
2520 all registers in REGSET. */
2523 i386_collect_gregset (const struct regset
*regset
,
2524 const struct regcache
*regcache
,
2525 int regnum
, void *gregs
, size_t len
)
2527 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2528 gdb_byte
*regs
= gregs
;
2531 gdb_assert (len
== tdep
->sizeof_gregset
);
2533 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2535 if ((regnum
== i
|| regnum
== -1)
2536 && tdep
->gregset_reg_offset
[i
] != -1)
2537 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2541 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2542 in the floating-point register set REGSET to register cache
2543 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2546 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2547 int regnum
, const void *fpregs
, size_t len
)
2549 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2551 if (len
== I387_SIZEOF_FXSAVE
)
2553 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2557 gdb_assert (len
== tdep
->sizeof_fpregset
);
2558 i387_supply_fsave (regcache
, regnum
, fpregs
);
2561 /* Collect register REGNUM from the register cache REGCACHE and store
2562 it in the buffer specified by FPREGS and LEN as described by the
2563 floating-point register set REGSET. If REGNUM is -1, do this for
2564 all registers in REGSET. */
2567 i386_collect_fpregset (const struct regset
*regset
,
2568 const struct regcache
*regcache
,
2569 int regnum
, void *fpregs
, size_t len
)
2571 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2573 if (len
== I387_SIZEOF_FXSAVE
)
2575 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2579 gdb_assert (len
== tdep
->sizeof_fpregset
);
2580 i387_collect_fsave (regcache
, regnum
, fpregs
);
2583 /* Return the appropriate register set for the core section identified
2584 by SECT_NAME and SECT_SIZE. */
2586 const struct regset
*
2587 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2588 const char *sect_name
, size_t sect_size
)
2590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2592 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2594 if (tdep
->gregset
== NULL
)
2595 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2596 i386_collect_gregset
);
2597 return tdep
->gregset
;
2600 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2601 || (strcmp (sect_name
, ".reg-xfp") == 0
2602 && sect_size
== I387_SIZEOF_FXSAVE
))
2604 if (tdep
->fpregset
== NULL
)
2605 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2606 i386_collect_fpregset
);
2607 return tdep
->fpregset
;
2614 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2617 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2618 CORE_ADDR pc
, char *name
)
2620 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2621 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2624 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2626 unsigned long indirect
=
2627 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2628 struct minimal_symbol
*indsym
=
2629 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2630 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2634 if (strncmp (symname
, "__imp_", 6) == 0
2635 || strncmp (symname
, "_imp_", 5) == 0)
2637 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2640 return 0; /* Not a trampoline. */
2644 /* Return whether the THIS_FRAME corresponds to a sigtramp
2648 i386_sigtramp_p (struct frame_info
*this_frame
)
2650 CORE_ADDR pc
= get_frame_pc (this_frame
);
2653 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2654 return (name
&& strcmp ("_sigtramp", name
) == 0);
2658 /* We have two flavours of disassembly. The machinery on this page
2659 deals with switching between those. */
2662 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2664 gdb_assert (disassembly_flavor
== att_flavor
2665 || disassembly_flavor
== intel_flavor
);
2667 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2668 constified, cast to prevent a compiler warning. */
2669 info
->disassembler_options
= (char *) disassembly_flavor
;
2671 return print_insn_i386 (pc
, info
);
2675 /* There are a few i386 architecture variants that differ only
2676 slightly from the generic i386 target. For now, we don't give them
2677 their own source file, but include them here. As a consequence,
2678 they'll always be included. */
2680 /* System V Release 4 (SVR4). */
2682 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2686 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2688 CORE_ADDR pc
= get_frame_pc (this_frame
);
2691 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2692 currently unknown. */
2693 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2694 return (name
&& (strcmp ("_sigreturn", name
) == 0
2695 || strcmp ("_sigacthandler", name
) == 0
2696 || strcmp ("sigvechandler", name
) == 0));
2699 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2700 address of the associated sigcontext (ucontext) structure. */
2703 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2705 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2706 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2710 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2711 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2713 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2720 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2722 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2723 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2726 /* System V Release 4 (SVR4). */
2729 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2733 /* System V Release 4 uses ELF. */
2734 i386_elf_init_abi (info
, gdbarch
);
2736 /* System V Release 4 has shared libraries. */
2737 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2739 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2740 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2741 tdep
->sc_pc_offset
= 36 + 14 * 4;
2742 tdep
->sc_sp_offset
= 36 + 17 * 4;
2744 tdep
->jb_pc_offset
= 20;
2750 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2754 /* DJGPP doesn't have any special frames for signal handlers. */
2755 tdep
->sigtramp_p
= NULL
;
2757 tdep
->jb_pc_offset
= 36;
2759 /* DJGPP does not support the SSE registers. */
2760 tdep
->num_xmm_regs
= 0;
2761 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I387_NUM_REGS
);
2763 /* Native compiler is GCC, which uses the SVR4 register numbering
2764 even in COFF and STABS. See the comment in i386_gdbarch_init,
2765 before the calls to set_gdbarch_stab_reg_to_regnum and
2766 set_gdbarch_sdb_reg_to_regnum. */
2767 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2768 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2772 /* i386 register groups. In addition to the normal groups, add "mmx"
2775 static struct reggroup
*i386_sse_reggroup
;
2776 static struct reggroup
*i386_mmx_reggroup
;
2779 i386_init_reggroups (void)
2781 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2782 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2786 i386_add_reggroups (struct gdbarch
*gdbarch
)
2788 reggroup_add (gdbarch
, i386_sse_reggroup
);
2789 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2790 reggroup_add (gdbarch
, general_reggroup
);
2791 reggroup_add (gdbarch
, float_reggroup
);
2792 reggroup_add (gdbarch
, all_reggroup
);
2793 reggroup_add (gdbarch
, save_reggroup
);
2794 reggroup_add (gdbarch
, restore_reggroup
);
2795 reggroup_add (gdbarch
, vector_reggroup
);
2796 reggroup_add (gdbarch
, system_reggroup
);
2800 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2801 struct reggroup
*group
)
2803 int sse_regnum_p
, fp_regnum_p
, mmx_regnum_p
, byte_regnum_p
,
2804 word_regnum_p
, dword_regnum_p
;
2806 /* Don't include pseudo registers, except for MMX, in any register
2808 byte_regnum_p
= i386_byte_regnum_p (gdbarch
, regnum
);
2812 word_regnum_p
= i386_word_regnum_p (gdbarch
, regnum
);
2816 dword_regnum_p
= i386_dword_regnum_p (gdbarch
, regnum
);
2820 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
2821 if (group
== i386_mmx_reggroup
)
2822 return mmx_regnum_p
;
2824 sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2825 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2826 if (group
== i386_sse_reggroup
)
2827 return sse_regnum_p
;
2828 if (group
== vector_reggroup
)
2829 return mmx_regnum_p
|| sse_regnum_p
;
2831 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2832 || i386_fpc_regnum_p (gdbarch
, regnum
));
2833 if (group
== float_reggroup
)
2836 if (group
== general_reggroup
)
2837 return (!fp_regnum_p
2842 && !dword_regnum_p
);
2844 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2848 /* Get the ARGIth function argument for the current function. */
2851 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2854 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2855 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2856 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2857 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2861 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2863 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2865 /* On i386, breakpoint is exactly 1 byte long, so we just
2866 adjust the PC in the regcache. */
2868 regcache_write_pc (regcache
, current_pc
);
2872 #define PREFIX_REPZ 0x01
2873 #define PREFIX_REPNZ 0x02
2874 #define PREFIX_LOCK 0x04
2875 #define PREFIX_DATA 0x08
2876 #define PREFIX_ADDR 0x10
2887 /* i386 arith/logic operations */
2900 struct i386_record_s
2902 struct gdbarch
*gdbarch
;
2903 struct regcache
*regcache
;
2904 CORE_ADDR orig_addr
;
2910 uint8_t mod
, reg
, rm
;
2919 /* Parse "modrm" part in current memory address that irp->addr point to
2920 Return -1 if something wrong. */
2923 i386_record_modrm (struct i386_record_s
*irp
)
2925 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2927 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2930 printf_unfiltered (_("Process record: error reading memory at "
2931 "addr %s len = 1.\n"),
2932 paddress (gdbarch
, irp
->addr
));
2936 irp
->mod
= (irp
->modrm
>> 6) & 3;
2937 irp
->reg
= (irp
->modrm
>> 3) & 7;
2938 irp
->rm
= irp
->modrm
& 7;
2943 /* Get the memory address that current instruction write to and set it to
2944 the argument "addr".
2945 Return -1 if something wrong. */
2948 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2950 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2951 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2963 uint8_t base
= irp
->rm
;
2968 if (target_read_memory (irp
->addr
, &byte
, 1))
2971 printf_unfiltered (_("Process record: error reading memory "
2972 "at addr %s len = 1.\n"),
2973 paddress (gdbarch
, irp
->addr
));
2977 scale
= (byte
>> 6) & 3;
2978 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
2986 if ((base
& 7) == 5)
2989 if (target_read_memory (irp
->addr
, buf
, 4))
2992 printf_unfiltered (_("Process record: error reading "
2993 "memory at addr %s len = 4.\n"),
2994 paddress (gdbarch
, irp
->addr
));
2998 *addr
= extract_signed_integer (buf
, 4, byte_order
);
2999 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3000 *addr
+= irp
->addr
+ irp
->rip_offset
;
3008 if (target_read_memory (irp
->addr
, buf
, 1))
3011 printf_unfiltered (_("Process record: error reading memory "
3012 "at addr %s len = 1.\n"),
3013 paddress (gdbarch
, irp
->addr
));
3017 *addr
= (int8_t) buf
[0];
3020 if (target_read_memory (irp
->addr
, buf
, 4))
3023 printf_unfiltered (_("Process record: error reading memory "
3024 "at addr %s len = 4.\n"),
3025 paddress (gdbarch
, irp
->addr
));
3028 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3036 if (base
== 4 && irp
->popl_esp_hack
)
3037 *addr
+= irp
->popl_esp_hack
;
3038 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3041 if (irp
->aflag
== 2)
3046 *addr
= (uint32_t) (offset64
+ *addr
);
3048 if (havesib
&& (index
!= 4 || scale
!= 0))
3050 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3052 if (irp
->aflag
== 2)
3053 *addr
+= offset64
<< scale
;
3055 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3066 if (target_read_memory (irp
->addr
, buf
, 2))
3069 printf_unfiltered (_("Process record: error reading "
3070 "memory at addr %s len = 2.\n"),
3071 paddress (gdbarch
, irp
->addr
));
3075 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3085 if (target_read_memory (irp
->addr
, buf
, 1))
3088 printf_unfiltered (_("Process record: error reading memory "
3089 "at addr %s len = 1.\n"),
3090 paddress (gdbarch
, irp
->addr
));
3094 *addr
= (int8_t) buf
[0];
3097 if (target_read_memory (irp
->addr
, buf
, 2))
3100 printf_unfiltered (_("Process record: error reading memory "
3101 "at addr %s len = 2.\n"),
3102 paddress (gdbarch
, irp
->addr
));
3106 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3113 regcache_raw_read_unsigned (irp
->regcache
,
3114 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3116 *addr
= (uint32_t) (*addr
+ offset64
);
3117 regcache_raw_read_unsigned (irp
->regcache
,
3118 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3120 *addr
= (uint32_t) (*addr
+ offset64
);
3123 regcache_raw_read_unsigned (irp
->regcache
,
3124 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3126 *addr
= (uint32_t) (*addr
+ offset64
);
3127 regcache_raw_read_unsigned (irp
->regcache
,
3128 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3130 *addr
= (uint32_t) (*addr
+ offset64
);
3133 regcache_raw_read_unsigned (irp
->regcache
,
3134 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3136 *addr
= (uint32_t) (*addr
+ offset64
);
3137 regcache_raw_read_unsigned (irp
->regcache
,
3138 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3140 *addr
= (uint32_t) (*addr
+ offset64
);
3143 regcache_raw_read_unsigned (irp
->regcache
,
3144 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3146 *addr
= (uint32_t) (*addr
+ offset64
);
3147 regcache_raw_read_unsigned (irp
->regcache
,
3148 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3150 *addr
= (uint32_t) (*addr
+ offset64
);
3153 regcache_raw_read_unsigned (irp
->regcache
,
3154 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3156 *addr
= (uint32_t) (*addr
+ offset64
);
3159 regcache_raw_read_unsigned (irp
->regcache
,
3160 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3162 *addr
= (uint32_t) (*addr
+ offset64
);
3165 regcache_raw_read_unsigned (irp
->regcache
,
3166 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3168 *addr
= (uint32_t) (*addr
+ offset64
);
3171 regcache_raw_read_unsigned (irp
->regcache
,
3172 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3174 *addr
= (uint32_t) (*addr
+ offset64
);
3184 /* Record the value of the memory that willbe changed in current instruction
3185 to "record_arch_list".
3186 Return -1 if something wrong. */
3189 i386_record_lea_modrm (struct i386_record_s
*irp
)
3191 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3194 if (irp
->override
>= 0)
3196 warning (_("Process record ignores the memory change "
3197 "of instruction at address %s because it "
3198 "can't get the value of the segment register."),
3199 paddress (gdbarch
, irp
->orig_addr
));
3203 if (i386_record_lea_modrm_addr (irp
, &addr
))
3206 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3212 /* Record the push operation to "record_arch_list".
3213 Return -1 if something wrong. */
3216 i386_record_push (struct i386_record_s
*irp
, int size
)
3220 if (record_arch_list_add_reg (irp
->regcache
,
3221 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3223 regcache_raw_read_unsigned (irp
->regcache
,
3224 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3226 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3233 /* Defines contents to record. */
3234 #define I386_SAVE_FPU_REGS 0xfffd
3235 #define I386_SAVE_FPU_ENV 0xfffe
3236 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3238 /* Record the value of floating point registers which will be changed by the
3239 current instruction to "record_arch_list". Return -1 if something is wrong.
3242 static int i386_record_floats (struct gdbarch
*gdbarch
,
3243 struct i386_record_s
*ir
,
3246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3249 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3250 happen. Currently we store st0-st7 registers, but we need not store all
3251 registers all the time, in future we use ftag register and record only
3252 those who are not marked as an empty. */
3254 if (I386_SAVE_FPU_REGS
== iregnum
)
3256 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3258 if (record_arch_list_add_reg (ir
->regcache
, i
))
3262 else if (I386_SAVE_FPU_ENV
== iregnum
)
3264 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3266 if (record_arch_list_add_reg (ir
->regcache
, i
))
3270 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3272 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3274 if (record_arch_list_add_reg (ir
->regcache
, i
))
3278 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3279 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3281 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3286 /* Parameter error. */
3289 if(I386_SAVE_FPU_ENV
!= iregnum
)
3291 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3293 if (record_arch_list_add_reg (ir
->regcache
, i
))
3300 /* Parse the current instruction and record the values of the registers and
3301 memory that will be changed in current instruction to "record_arch_list".
3302 Return -1 if something wrong. */
3304 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3305 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3308 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3309 CORE_ADDR input_addr
)
3311 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3317 gdb_byte buf
[MAX_REGISTER_SIZE
];
3318 struct i386_record_s ir
;
3319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3324 memset (&ir
, 0, sizeof (struct i386_record_s
));
3325 ir
.regcache
= regcache
;
3326 ir
.addr
= input_addr
;
3327 ir
.orig_addr
= input_addr
;
3331 ir
.popl_esp_hack
= 0;
3332 ir
.regmap
= gdbarch_tdep (gdbarch
)->record_regmap
;
3333 ir
.gdbarch
= gdbarch
;
3335 if (record_debug
> 1)
3336 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3338 paddress (gdbarch
, ir
.addr
));
3343 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3346 printf_unfiltered (_("Process record: error reading memory at "
3347 "addr %s len = 1.\n"),
3348 paddress (gdbarch
, ir
.addr
));
3352 switch (opcode8
) /* Instruction prefixes */
3354 case REPE_PREFIX_OPCODE
:
3355 prefixes
|= PREFIX_REPZ
;
3357 case REPNE_PREFIX_OPCODE
:
3358 prefixes
|= PREFIX_REPNZ
;
3360 case LOCK_PREFIX_OPCODE
:
3361 prefixes
|= PREFIX_LOCK
;
3363 case CS_PREFIX_OPCODE
:
3364 ir
.override
= X86_RECORD_CS_REGNUM
;
3366 case SS_PREFIX_OPCODE
:
3367 ir
.override
= X86_RECORD_SS_REGNUM
;
3369 case DS_PREFIX_OPCODE
:
3370 ir
.override
= X86_RECORD_DS_REGNUM
;
3372 case ES_PREFIX_OPCODE
:
3373 ir
.override
= X86_RECORD_ES_REGNUM
;
3375 case FS_PREFIX_OPCODE
:
3376 ir
.override
= X86_RECORD_FS_REGNUM
;
3378 case GS_PREFIX_OPCODE
:
3379 ir
.override
= X86_RECORD_GS_REGNUM
;
3381 case DATA_PREFIX_OPCODE
:
3382 prefixes
|= PREFIX_DATA
;
3384 case ADDR_PREFIX_OPCODE
:
3385 prefixes
|= PREFIX_ADDR
;
3387 case 0x40: /* i386 inc %eax */
3388 case 0x41: /* i386 inc %ecx */
3389 case 0x42: /* i386 inc %edx */
3390 case 0x43: /* i386 inc %ebx */
3391 case 0x44: /* i386 inc %esp */
3392 case 0x45: /* i386 inc %ebp */
3393 case 0x46: /* i386 inc %esi */
3394 case 0x47: /* i386 inc %edi */
3395 case 0x48: /* i386 dec %eax */
3396 case 0x49: /* i386 dec %ecx */
3397 case 0x4a: /* i386 dec %edx */
3398 case 0x4b: /* i386 dec %ebx */
3399 case 0x4c: /* i386 dec %esp */
3400 case 0x4d: /* i386 dec %ebp */
3401 case 0x4e: /* i386 dec %esi */
3402 case 0x4f: /* i386 dec %edi */
3403 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3407 rex_w
= (opcode8
>> 3) & 1;
3408 rex_r
= (opcode8
& 0x4) << 1;
3409 ir
.rex_x
= (opcode8
& 0x2) << 2;
3410 ir
.rex_b
= (opcode8
& 0x1) << 3;
3412 else /* 32 bit target */
3421 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3427 if (prefixes
& PREFIX_DATA
)
3430 if (prefixes
& PREFIX_ADDR
)
3432 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3435 /* now check op code */
3436 opcode
= (uint32_t) opcode8
;
3441 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3444 printf_unfiltered (_("Process record: error reading memory at "
3445 "addr %s len = 1.\n"),
3446 paddress (gdbarch
, ir
.addr
));
3450 opcode
= (uint16_t) opcode8
| 0x0f00;
3454 case 0x00: /* arith & logic */
3502 if (((opcode
>> 3) & 7) != OP_CMPL
)
3504 if ((opcode
& 1) == 0)
3507 ir
.ot
= ir
.dflag
+ OT_WORD
;
3509 switch ((opcode
>> 1) & 3)
3511 case 0: /* OP Ev, Gv */
3512 if (i386_record_modrm (&ir
))
3516 if (i386_record_lea_modrm (&ir
))
3522 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3524 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3527 case 1: /* OP Gv, Ev */
3528 if (i386_record_modrm (&ir
))
3531 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3533 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3535 case 2: /* OP A, Iv */
3536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3543 case 0x80: /* GRP1 */
3547 if (i386_record_modrm (&ir
))
3550 if (ir
.reg
!= OP_CMPL
)
3552 if ((opcode
& 1) == 0)
3555 ir
.ot
= ir
.dflag
+ OT_WORD
;
3562 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3563 if (i386_record_lea_modrm (&ir
))
3567 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3572 case 0x40: /* inc */
3581 case 0x48: /* dec */
3590 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3591 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3594 case 0xf6: /* GRP3 */
3596 if ((opcode
& 1) == 0)
3599 ir
.ot
= ir
.dflag
+ OT_WORD
;
3600 if (i386_record_modrm (&ir
))
3603 if (ir
.mod
!= 3 && ir
.reg
== 0)
3604 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3609 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3615 if (i386_record_lea_modrm (&ir
))
3621 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3623 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3625 if (ir
.reg
== 3) /* neg */
3626 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3633 if (ir
.ot
!= OT_BYTE
)
3634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3639 opcode
= opcode
<< 8 | ir
.modrm
;
3645 case 0xfe: /* GRP4 */
3646 case 0xff: /* GRP5 */
3647 if (i386_record_modrm (&ir
))
3649 if (ir
.reg
>= 2 && opcode
== 0xfe)
3652 opcode
= opcode
<< 8 | ir
.modrm
;
3659 if ((opcode
& 1) == 0)
3662 ir
.ot
= ir
.dflag
+ OT_WORD
;
3665 if (i386_record_lea_modrm (&ir
))
3671 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3673 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3678 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3680 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3685 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3686 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3688 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3692 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3695 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3697 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3702 opcode
= opcode
<< 8 | ir
.modrm
;
3708 case 0x84: /* test */
3712 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3715 case 0x98: /* CWDE/CBW */
3716 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3719 case 0x99: /* CDQ/CWD */
3720 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3721 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3724 case 0x0faf: /* imul */
3727 ir
.ot
= ir
.dflag
+ OT_WORD
;
3728 if (i386_record_modrm (&ir
))
3731 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3732 else if (opcode
== 0x6b)
3735 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3737 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3738 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3741 case 0x0fc0: /* xadd */
3743 if ((opcode
& 1) == 0)
3746 ir
.ot
= ir
.dflag
+ OT_WORD
;
3747 if (i386_record_modrm (&ir
))
3752 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3754 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3755 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3757 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3761 if (i386_record_lea_modrm (&ir
))
3763 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3765 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3770 case 0x0fb0: /* cmpxchg */
3772 if ((opcode
& 1) == 0)
3775 ir
.ot
= ir
.dflag
+ OT_WORD
;
3776 if (i386_record_modrm (&ir
))
3781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3782 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3784 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3789 if (i386_record_lea_modrm (&ir
))
3792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3795 case 0x0fc7: /* cmpxchg8b */
3796 if (i386_record_modrm (&ir
))
3801 opcode
= opcode
<< 8 | ir
.modrm
;
3804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3806 if (i386_record_lea_modrm (&ir
))
3808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3811 case 0x50: /* push */
3821 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3823 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3827 case 0x06: /* push es */
3828 case 0x0e: /* push cs */
3829 case 0x16: /* push ss */
3830 case 0x1e: /* push ds */
3831 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3836 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3840 case 0x0fa0: /* push fs */
3841 case 0x0fa8: /* push gs */
3842 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3847 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3851 case 0x60: /* pusha */
3852 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3857 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3861 case 0x58: /* pop */
3869 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3870 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3873 case 0x61: /* popa */
3874 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3879 for (regnum
= X86_RECORD_REAX_REGNUM
;
3880 regnum
<= X86_RECORD_REDI_REGNUM
;
3882 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
3885 case 0x8f: /* pop */
3886 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3887 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3889 ir
.ot
= ir
.dflag
+ OT_WORD
;
3890 if (i386_record_modrm (&ir
))
3893 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3896 ir
.popl_esp_hack
= 1 << ir
.ot
;
3897 if (i386_record_lea_modrm (&ir
))
3900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3903 case 0xc8: /* enter */
3904 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3905 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3907 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3911 case 0xc9: /* leave */
3912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3913 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3916 case 0x07: /* pop es */
3917 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3927 case 0x17: /* pop ss */
3928 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3933 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3934 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3938 case 0x1f: /* pop ds */
3939 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3944 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3949 case 0x0fa1: /* pop fs */
3950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3955 case 0x0fa9: /* pop gs */
3956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3961 case 0x88: /* mov */
3965 if ((opcode
& 1) == 0)
3968 ir
.ot
= ir
.dflag
+ OT_WORD
;
3970 if (i386_record_modrm (&ir
))
3975 if (opcode
== 0xc6 || opcode
== 0xc7)
3976 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3977 if (i386_record_lea_modrm (&ir
))
3982 if (opcode
== 0xc6 || opcode
== 0xc7)
3984 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3986 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3990 case 0x8a: /* mov */
3992 if ((opcode
& 1) == 0)
3995 ir
.ot
= ir
.dflag
+ OT_WORD
;
3996 if (i386_record_modrm (&ir
))
3999 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4001 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4004 case 0x8c: /* mov seg */
4005 if (i386_record_modrm (&ir
))
4010 opcode
= opcode
<< 8 | ir
.modrm
;
4015 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4019 if (i386_record_lea_modrm (&ir
))
4024 case 0x8e: /* mov seg */
4025 if (i386_record_modrm (&ir
))
4030 regnum
= X86_RECORD_ES_REGNUM
;
4033 regnum
= X86_RECORD_SS_REGNUM
;
4036 regnum
= X86_RECORD_DS_REGNUM
;
4039 regnum
= X86_RECORD_FS_REGNUM
;
4042 regnum
= X86_RECORD_GS_REGNUM
;
4046 opcode
= opcode
<< 8 | ir
.modrm
;
4050 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4051 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4054 case 0x0fb6: /* movzbS */
4055 case 0x0fb7: /* movzwS */
4056 case 0x0fbe: /* movsbS */
4057 case 0x0fbf: /* movswS */
4058 if (i386_record_modrm (&ir
))
4060 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4063 case 0x8d: /* lea */
4064 if (i386_record_modrm (&ir
))
4069 opcode
= opcode
<< 8 | ir
.modrm
;
4074 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4076 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4079 case 0xa0: /* mov EAX */
4082 case 0xd7: /* xlat */
4083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4086 case 0xa2: /* mov EAX */
4088 if (ir
.override
>= 0)
4090 warning (_("Process record ignores the memory change "
4091 "of instruction at address %s because "
4092 "it can't get the value of the segment "
4094 paddress (gdbarch
, ir
.orig_addr
));
4098 if ((opcode
& 1) == 0)
4101 ir
.ot
= ir
.dflag
+ OT_WORD
;
4104 if (target_read_memory (ir
.addr
, buf
, 8))
4107 printf_unfiltered (_("Process record: error reading "
4108 "memory at addr 0x%s len = 8.\n"),
4109 paddress (gdbarch
, ir
.addr
));
4113 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4117 if (target_read_memory (ir
.addr
, buf
, 4))
4120 printf_unfiltered (_("Process record: error reading "
4121 "memory at addr 0x%s len = 4.\n"),
4122 paddress (gdbarch
, ir
.addr
));
4126 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4130 if (target_read_memory (ir
.addr
, buf
, 2))
4133 printf_unfiltered (_("Process record: error reading "
4134 "memory at addr 0x%s len = 2.\n"),
4135 paddress (gdbarch
, ir
.addr
));
4139 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4141 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4146 case 0xb0: /* mov R, Ib */
4154 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4155 ? ((opcode
& 0x7) | ir
.rex_b
)
4156 : ((opcode
& 0x7) & 0x3));
4159 case 0xb8: /* mov R, Iv */
4167 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4170 case 0x91: /* xchg R, EAX */
4177 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4178 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4181 case 0x86: /* xchg Ev, Gv */
4183 if ((opcode
& 1) == 0)
4186 ir
.ot
= ir
.dflag
+ OT_WORD
;
4187 if (i386_record_modrm (&ir
))
4192 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4194 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4198 if (i386_record_lea_modrm (&ir
))
4202 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4204 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4207 case 0xc4: /* les Gv */
4208 case 0xc5: /* lds Gv */
4209 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4214 case 0x0fb2: /* lss Gv */
4215 case 0x0fb4: /* lfs Gv */
4216 case 0x0fb5: /* lgs Gv */
4217 if (i386_record_modrm (&ir
))
4225 opcode
= opcode
<< 8 | ir
.modrm
;
4230 case 0xc4: /* les Gv */
4231 regnum
= X86_RECORD_ES_REGNUM
;
4233 case 0xc5: /* lds Gv */
4234 regnum
= X86_RECORD_DS_REGNUM
;
4236 case 0x0fb2: /* lss Gv */
4237 regnum
= X86_RECORD_SS_REGNUM
;
4239 case 0x0fb4: /* lfs Gv */
4240 regnum
= X86_RECORD_FS_REGNUM
;
4242 case 0x0fb5: /* lgs Gv */
4243 regnum
= X86_RECORD_GS_REGNUM
;
4246 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4247 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4248 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4251 case 0xc0: /* shifts */
4257 if ((opcode
& 1) == 0)
4260 ir
.ot
= ir
.dflag
+ OT_WORD
;
4261 if (i386_record_modrm (&ir
))
4263 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4265 if (i386_record_lea_modrm (&ir
))
4271 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4273 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4282 if (i386_record_modrm (&ir
))
4286 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4291 if (i386_record_lea_modrm (&ir
))
4296 case 0xd8: /* Floats. */
4304 if (i386_record_modrm (&ir
))
4306 ir
.reg
|= ((opcode
& 7) << 3);
4312 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4320 /* For fcom, ficom nothing to do. */
4326 /* For fcomp, ficomp pop FPU stack, store all. */
4327 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4354 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4355 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4356 of code, always affects st(0) register. */
4357 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4381 /* Handling fld, fild. */
4382 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4386 switch (ir
.reg
>> 4)
4389 if (record_arch_list_add_mem (addr64
, 4))
4393 if (record_arch_list_add_mem (addr64
, 8))
4399 if (record_arch_list_add_mem (addr64
, 2))
4405 switch (ir
.reg
>> 4)
4408 if (record_arch_list_add_mem (addr64
, 4))
4410 if (3 == (ir
.reg
& 7))
4412 /* For fstp m32fp. */
4413 if (i386_record_floats (gdbarch
, &ir
,
4414 I386_SAVE_FPU_REGS
))
4419 if (record_arch_list_add_mem (addr64
, 4))
4421 if ((3 == (ir
.reg
& 7))
4422 || (5 == (ir
.reg
& 7))
4423 || (7 == (ir
.reg
& 7)))
4425 /* For fstp insn. */
4426 if (i386_record_floats (gdbarch
, &ir
,
4427 I386_SAVE_FPU_REGS
))
4432 if (record_arch_list_add_mem (addr64
, 8))
4434 if (3 == (ir
.reg
& 7))
4436 /* For fstp m64fp. */
4437 if (i386_record_floats (gdbarch
, &ir
,
4438 I386_SAVE_FPU_REGS
))
4443 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4445 /* For fistp, fbld, fild, fbstp. */
4446 if (i386_record_floats (gdbarch
, &ir
,
4447 I386_SAVE_FPU_REGS
))
4452 if (record_arch_list_add_mem (addr64
, 2))
4461 if (i386_record_floats (gdbarch
, &ir
,
4462 I386_SAVE_FPU_ENV_REG_STACK
))
4467 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4472 if (i386_record_floats (gdbarch
, &ir
,
4473 I386_SAVE_FPU_ENV_REG_STACK
))
4479 if (record_arch_list_add_mem (addr64
, 28))
4484 if (record_arch_list_add_mem (addr64
, 14))
4490 if (record_arch_list_add_mem (addr64
, 2))
4492 /* Insn fstp, fbstp. */
4493 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4498 if (record_arch_list_add_mem (addr64
, 10))
4504 if (record_arch_list_add_mem (addr64
, 28))
4510 if (record_arch_list_add_mem (addr64
, 14))
4514 if (record_arch_list_add_mem (addr64
, 80))
4517 if (i386_record_floats (gdbarch
, &ir
,
4518 I386_SAVE_FPU_ENV_REG_STACK
))
4522 if (record_arch_list_add_mem (addr64
, 8))
4525 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4530 opcode
= opcode
<< 8 | ir
.modrm
;
4535 /* Opcode is an extension of modR/M byte. */
4541 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4545 if (0x0c == (ir
.modrm
>> 4))
4547 if ((ir
.modrm
& 0x0f) <= 7)
4549 if (i386_record_floats (gdbarch
, &ir
,
4550 I386_SAVE_FPU_REGS
))
4555 if (i386_record_floats (gdbarch
, &ir
,
4556 I387_ST0_REGNUM (tdep
)))
4558 /* If only st(0) is changing, then we have already
4560 if ((ir
.modrm
& 0x0f) - 0x08)
4562 if (i386_record_floats (gdbarch
, &ir
,
4563 I387_ST0_REGNUM (tdep
) +
4564 ((ir
.modrm
& 0x0f) - 0x08)))
4582 if (i386_record_floats (gdbarch
, &ir
,
4583 I387_ST0_REGNUM (tdep
)))
4601 if (i386_record_floats (gdbarch
, &ir
,
4602 I386_SAVE_FPU_REGS
))
4606 if (i386_record_floats (gdbarch
, &ir
,
4607 I387_ST0_REGNUM (tdep
)))
4609 if (i386_record_floats (gdbarch
, &ir
,
4610 I387_ST0_REGNUM (tdep
) + 1))
4617 if (0xe9 == ir
.modrm
)
4619 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4622 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4624 if (i386_record_floats (gdbarch
, &ir
,
4625 I387_ST0_REGNUM (tdep
)))
4627 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4629 if (i386_record_floats (gdbarch
, &ir
,
4630 I387_ST0_REGNUM (tdep
) +
4634 else if ((ir
.modrm
& 0x0f) - 0x08)
4636 if (i386_record_floats (gdbarch
, &ir
,
4637 I387_ST0_REGNUM (tdep
) +
4638 ((ir
.modrm
& 0x0f) - 0x08)))
4644 if (0xe3 == ir
.modrm
)
4646 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4649 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4651 if (i386_record_floats (gdbarch
, &ir
,
4652 I387_ST0_REGNUM (tdep
)))
4654 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4656 if (i386_record_floats (gdbarch
, &ir
,
4657 I387_ST0_REGNUM (tdep
) +
4661 else if ((ir
.modrm
& 0x0f) - 0x08)
4663 if (i386_record_floats (gdbarch
, &ir
,
4664 I387_ST0_REGNUM (tdep
) +
4665 ((ir
.modrm
& 0x0f) - 0x08)))
4671 if ((0x0c == ir
.modrm
>> 4)
4672 || (0x0d == ir
.modrm
>> 4)
4673 || (0x0f == ir
.modrm
>> 4))
4675 if ((ir
.modrm
& 0x0f) <= 7)
4677 if (i386_record_floats (gdbarch
, &ir
,
4678 I387_ST0_REGNUM (tdep
) +
4684 if (i386_record_floats (gdbarch
, &ir
,
4685 I387_ST0_REGNUM (tdep
) +
4686 ((ir
.modrm
& 0x0f) - 0x08)))
4692 if (0x0c == ir
.modrm
>> 4)
4694 if (i386_record_floats (gdbarch
, &ir
,
4695 I387_FTAG_REGNUM (tdep
)))
4698 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4700 if ((ir
.modrm
& 0x0f) <= 7)
4702 if (i386_record_floats (gdbarch
, &ir
,
4703 I387_ST0_REGNUM (tdep
) +
4709 if (i386_record_floats (gdbarch
, &ir
,
4710 I386_SAVE_FPU_REGS
))
4716 if ((0x0c == ir
.modrm
>> 4)
4717 || (0x0e == ir
.modrm
>> 4)
4718 || (0x0f == ir
.modrm
>> 4)
4719 || (0xd9 == ir
.modrm
))
4721 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4726 if (0xe0 == ir
.modrm
)
4728 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4731 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4733 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4741 case 0xa4: /* movsS */
4743 case 0xaa: /* stosS */
4745 case 0x6c: /* insS */
4747 regcache_raw_read_unsigned (ir
.regcache
,
4748 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4754 if ((opcode
& 1) == 0)
4757 ir
.ot
= ir
.dflag
+ OT_WORD
;
4758 regcache_raw_read_unsigned (ir
.regcache
,
4759 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4762 regcache_raw_read_unsigned (ir
.regcache
,
4763 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4765 regcache_raw_read_unsigned (ir
.regcache
,
4766 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4768 if (ir
.aflag
&& (es
!= ds
))
4770 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4771 warning (_("Process record ignores the memory "
4772 "change of instruction at address %s "
4773 "because it can't get the value of the "
4774 "ES segment register."),
4775 paddress (gdbarch
, ir
.orig_addr
));
4779 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4783 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4785 if (opcode
== 0xa4 || opcode
== 0xa5)
4786 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4792 case 0xa6: /* cmpsS */
4794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4796 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4797 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4798 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4801 case 0xac: /* lodsS */
4803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4805 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4806 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4810 case 0xae: /* scasS */
4812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4813 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4814 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4818 case 0x6e: /* outsS */
4820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4821 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4822 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4826 case 0xe4: /* port I/O */
4830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4831 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4841 case 0xc2: /* ret im */
4842 case 0xc3: /* ret */
4843 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4844 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4847 case 0xca: /* lret im */
4848 case 0xcb: /* lret */
4849 case 0xcf: /* iret */
4850 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4851 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4852 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4855 case 0xe8: /* call im */
4856 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4858 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4862 case 0x9a: /* lcall im */
4863 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4868 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4869 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4873 case 0xe9: /* jmp im */
4874 case 0xea: /* ljmp im */
4875 case 0xeb: /* jmp Jb */
4876 case 0x70: /* jcc Jb */
4892 case 0x0f80: /* jcc Jv */
4910 case 0x0f90: /* setcc Gv */
4926 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4928 if (i386_record_modrm (&ir
))
4931 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4935 if (i386_record_lea_modrm (&ir
))
4940 case 0x0f40: /* cmov Gv, Ev */
4956 if (i386_record_modrm (&ir
))
4959 if (ir
.dflag
== OT_BYTE
)
4961 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4965 case 0x9c: /* pushf */
4966 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4967 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4969 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4973 case 0x9d: /* popf */
4974 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4978 case 0x9e: /* sahf */
4979 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4984 case 0xf5: /* cmc */
4985 case 0xf8: /* clc */
4986 case 0xf9: /* stc */
4987 case 0xfc: /* cld */
4988 case 0xfd: /* std */
4989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4992 case 0x9f: /* lahf */
4993 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4999 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5002 /* bit operations */
5003 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5004 ir
.ot
= ir
.dflag
+ OT_WORD
;
5005 if (i386_record_modrm (&ir
))
5010 opcode
= opcode
<< 8 | ir
.modrm
;
5016 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5019 if (i386_record_lea_modrm (&ir
))
5023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5026 case 0x0fa3: /* bt Gv, Ev */
5027 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5030 case 0x0fab: /* bts */
5031 case 0x0fb3: /* btr */
5032 case 0x0fbb: /* btc */
5033 ir
.ot
= ir
.dflag
+ OT_WORD
;
5034 if (i386_record_modrm (&ir
))
5037 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5041 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5043 regcache_raw_read_unsigned (ir
.regcache
,
5044 ir
.regmap
[ir
.reg
| rex_r
],
5049 addr64
+= ((int16_t) addr
>> 4) << 4;
5052 addr64
+= ((int32_t) addr
>> 5) << 5;
5055 addr64
+= ((int64_t) addr
>> 6) << 6;
5058 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5060 if (i386_record_lea_modrm (&ir
))
5063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5066 case 0x0fbc: /* bsf */
5067 case 0x0fbd: /* bsr */
5068 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5069 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5073 case 0x27: /* daa */
5074 case 0x2f: /* das */
5075 case 0x37: /* aaa */
5076 case 0x3f: /* aas */
5077 case 0xd4: /* aam */
5078 case 0xd5: /* aad */
5079 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5084 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5089 case 0x90: /* nop */
5090 if (prefixes
& PREFIX_LOCK
)
5097 case 0x9b: /* fwait */
5098 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5101 printf_unfiltered (_("Process record: error reading memory at "
5102 "addr 0x%s len = 1.\n"),
5103 paddress (gdbarch
, ir
.addr
));
5106 opcode
= (uint32_t) opcode8
;
5112 case 0xcc: /* int3 */
5113 printf_unfiltered (_("Process record doesn't support instruction "
5120 case 0xcd: /* int */
5124 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5127 printf_unfiltered (_("Process record: error reading memory "
5128 "at addr %s len = 1.\n"),
5129 paddress (gdbarch
, ir
.addr
));
5133 if (interrupt
!= 0x80
5134 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
5136 printf_unfiltered (_("Process record doesn't support "
5137 "instruction int 0x%02x.\n"),
5142 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
5149 case 0xce: /* into */
5150 printf_unfiltered (_("Process record doesn't support "
5151 "instruction into.\n"));
5156 case 0xfa: /* cli */
5157 case 0xfb: /* sti */
5160 case 0x62: /* bound */
5161 printf_unfiltered (_("Process record doesn't support "
5162 "instruction bound.\n"));
5167 case 0x0fc8: /* bswap reg */
5175 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5178 case 0xd6: /* salc */
5179 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5184 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5185 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5188 case 0xe0: /* loopnz */
5189 case 0xe1: /* loopz */
5190 case 0xe2: /* loop */
5191 case 0xe3: /* jecxz */
5192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5196 case 0x0f30: /* wrmsr */
5197 printf_unfiltered (_("Process record doesn't support "
5198 "instruction wrmsr.\n"));
5203 case 0x0f32: /* rdmsr */
5204 printf_unfiltered (_("Process record doesn't support "
5205 "instruction rdmsr.\n"));
5210 case 0x0f31: /* rdtsc */
5211 printf_unfiltered (_("Process record doesn't support "
5212 "instruction rdtsc.\n"));
5217 case 0x0f34: /* sysenter */
5220 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5225 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
5227 printf_unfiltered (_("Process record doesn't support "
5228 "instruction sysenter.\n"));
5232 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
5238 case 0x0f35: /* sysexit */
5239 printf_unfiltered (_("Process record doesn't support "
5240 "instruction sysexit.\n"));
5245 case 0x0f05: /* syscall */
5248 if (gdbarch_tdep (gdbarch
)->i386_syscall_record
== NULL
)
5250 printf_unfiltered (_("Process record doesn't support "
5251 "instruction syscall.\n"));
5255 ret
= gdbarch_tdep (gdbarch
)->i386_syscall_record (ir
.regcache
);
5261 case 0x0f07: /* sysret */
5262 printf_unfiltered (_("Process record doesn't support "
5263 "instruction sysret.\n"));
5268 case 0x0fa2: /* cpuid */
5269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5275 case 0xf4: /* hlt */
5276 printf_unfiltered (_("Process record doesn't support "
5277 "instruction hlt.\n"));
5283 if (i386_record_modrm (&ir
))
5290 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5294 if (i386_record_lea_modrm (&ir
))
5303 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5307 opcode
= opcode
<< 8 | ir
.modrm
;
5314 if (i386_record_modrm (&ir
))
5325 opcode
= opcode
<< 8 | ir
.modrm
;
5328 if (ir
.override
>= 0)
5330 warning (_("Process record ignores the memory "
5331 "change of instruction at "
5332 "address %s because it can't get "
5333 "the value of the segment "
5335 paddress (gdbarch
, ir
.orig_addr
));
5339 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5341 if (record_arch_list_add_mem (addr64
, 2))
5344 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5346 if (record_arch_list_add_mem (addr64
, 8))
5351 if (record_arch_list_add_mem (addr64
, 4))
5362 case 0: /* monitor */
5365 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5369 opcode
= opcode
<< 8 | ir
.modrm
;
5377 if (ir
.override
>= 0)
5379 warning (_("Process record ignores the memory "
5380 "change of instruction at "
5381 "address %s because it can't get "
5382 "the value of the segment "
5384 paddress (gdbarch
, ir
.orig_addr
));
5390 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5392 if (record_arch_list_add_mem (addr64
, 2))
5395 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5397 if (record_arch_list_add_mem (addr64
, 8))
5402 if (record_arch_list_add_mem (addr64
, 4))
5414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5419 else if (ir
.rm
== 1)
5426 opcode
= opcode
<< 8 | ir
.modrm
;
5433 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5439 if (i386_record_lea_modrm (&ir
))
5442 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5445 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5447 case 7: /* invlpg */
5450 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5455 opcode
= opcode
<< 8 | ir
.modrm
;
5460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5464 opcode
= opcode
<< 8 | ir
.modrm
;
5470 case 0x0f08: /* invd */
5471 case 0x0f09: /* wbinvd */
5474 case 0x63: /* arpl */
5475 if (i386_record_modrm (&ir
))
5477 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5479 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5480 ? (ir
.reg
| rex_r
) : ir
.rm
);
5484 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5485 if (i386_record_lea_modrm (&ir
))
5488 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5492 case 0x0f02: /* lar */
5493 case 0x0f03: /* lsl */
5494 if (i386_record_modrm (&ir
))
5496 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5501 if (i386_record_modrm (&ir
))
5503 if (ir
.mod
== 3 && ir
.reg
== 3)
5506 opcode
= opcode
<< 8 | ir
.modrm
;
5518 /* nop (multi byte) */
5521 case 0x0f20: /* mov reg, crN */
5522 case 0x0f22: /* mov crN, reg */
5523 if (i386_record_modrm (&ir
))
5525 if ((ir
.modrm
& 0xc0) != 0xc0)
5528 opcode
= opcode
<< 8 | ir
.modrm
;
5539 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5541 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5545 opcode
= opcode
<< 8 | ir
.modrm
;
5551 case 0x0f21: /* mov reg, drN */
5552 case 0x0f23: /* mov drN, reg */
5553 if (i386_record_modrm (&ir
))
5555 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5556 || ir
.reg
== 5 || ir
.reg
>= 8)
5559 opcode
= opcode
<< 8 | ir
.modrm
;
5563 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5565 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5568 case 0x0f06: /* clts */
5569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5572 /* MMX/SSE/SSE2/PNI support */
5584 /* In the future, maybe still need to deal with need_dasm. */
5585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
5586 if (record_arch_list_add_end ())
5592 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5593 "at address %s.\n"),
5594 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5598 static const int i386_record_regmap
[] =
5600 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
5601 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
5602 0, 0, 0, 0, 0, 0, 0, 0,
5603 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
5604 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
5607 /* Check that the given address appears suitable for a fast
5608 tracepoint, which on x86 means that we need an instruction of at
5609 least 5 bytes, so that we can overwrite it with a 4-byte-offset
5610 jump and not have to worry about program jumps to an address in the
5611 middle of the tracepoint jump. Returns 1 if OK, and writes a size
5612 of instruction to replace, and 0 if not, plus an explanatory
5616 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
5617 CORE_ADDR addr
, int *isize
, char **msg
)
5620 static struct ui_file
*gdb_null
= NULL
;
5622 /* This is based on the target agent using a 4-byte relative jump.
5623 Alternate future possibilities include 8-byte offset for x86-84,
5624 or 3-byte jumps if the program has trampoline space close by. */
5627 /* Dummy file descriptor for the disassembler. */
5629 gdb_null
= ui_file_new ();
5631 /* Check for fit. */
5632 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
5635 /* Return a bit of target-specific detail to add to the caller's
5636 generic failure message. */
5638 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
5651 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
5652 struct tdesc_arch_data
*tdesc_data
)
5654 const struct target_desc
*tdesc
= tdep
->tdesc
;
5655 const struct tdesc_feature
*feature_core
, *feature_vector
;
5656 int i
, num_regs
, valid_p
;
5658 if (! tdesc_has_registers (tdesc
))
5661 /* Get core registers. */
5662 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
5664 /* Get SSE registers. */
5665 feature_vector
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
5667 if (feature_core
== NULL
|| feature_vector
== NULL
)
5672 num_regs
= tdep
->num_core_regs
;
5673 for (i
= 0; i
< num_regs
; i
++)
5674 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
5675 tdep
->register_names
[i
]);
5677 /* Need to include %mxcsr, so add one. */
5678 num_regs
+= tdep
->num_xmm_regs
+ 1;
5679 for (; i
< num_regs
; i
++)
5680 valid_p
&= tdesc_numbered_register (feature_vector
, tdesc_data
, i
,
5681 tdep
->register_names
[i
]);
5687 static struct gdbarch
*
5688 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5690 struct gdbarch_tdep
*tdep
;
5691 struct gdbarch
*gdbarch
;
5692 struct tdesc_arch_data
*tdesc_data
;
5693 const struct target_desc
*tdesc
;
5696 /* If there is already a candidate, use it. */
5697 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5699 return arches
->gdbarch
;
5701 /* Allocate space for the new architecture. */
5702 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5703 gdbarch
= gdbarch_alloc (&info
, tdep
);
5705 /* General-purpose registers. */
5706 tdep
->gregset
= NULL
;
5707 tdep
->gregset_reg_offset
= NULL
;
5708 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5709 tdep
->sizeof_gregset
= 0;
5711 /* Floating-point registers. */
5712 tdep
->fpregset
= NULL
;
5713 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5715 /* The default settings include the FPU registers, the MMX registers
5716 and the SSE registers. This can be overridden for a specific ABI
5717 by adjusting the members `st0_regnum', `mm0_regnum' and
5718 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5719 will show up in the output of "info all-registers". Ideally we
5720 should try to autodetect whether they are available, such that we
5721 can prevent "info all-registers" from displaying registers that
5724 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5725 [the SSE registers] always (even when they don't exist) or never
5726 showing them to the user (even when they do exist), I prefer the
5727 former over the latter. */
5729 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5731 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5732 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5734 tdep
->jb_pc_offset
= -1;
5735 tdep
->struct_return
= pcc_struct_return
;
5736 tdep
->sigtramp_start
= 0;
5737 tdep
->sigtramp_end
= 0;
5738 tdep
->sigtramp_p
= i386_sigtramp_p
;
5739 tdep
->sigcontext_addr
= NULL
;
5740 tdep
->sc_reg_offset
= NULL
;
5741 tdep
->sc_pc_offset
= -1;
5742 tdep
->sc_sp_offset
= -1;
5744 tdep
->record_regmap
= i386_record_regmap
;
5746 /* The format used for `long double' on almost all i386 targets is
5747 the i387 extended floating-point format. In fact, of all targets
5748 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5749 on having a `long double' that's not `long' at all. */
5750 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5752 /* Although the i387 extended floating-point has only 80 significant
5753 bits, a `long double' actually takes up 96, probably to enforce
5755 set_gdbarch_long_double_bit (gdbarch
, 96);
5757 /* Register numbers of various important registers. */
5758 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5759 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5760 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5761 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5763 /* NOTE: kettenis/20040418: GCC does have two possible register
5764 numbering schemes on the i386: dbx and SVR4. These schemes
5765 differ in how they number %ebp, %esp, %eflags, and the
5766 floating-point registers, and are implemented by the arrays
5767 dbx_register_map[] and svr4_dbx_register_map in
5768 gcc/config/i386.c. GCC also defines a third numbering scheme in
5769 gcc/config/i386.c, which it designates as the "default" register
5770 map used in 64bit mode. This last register numbering scheme is
5771 implemented in dbx64_register_map, and is used for AMD64; see
5774 Currently, each GCC i386 target always uses the same register
5775 numbering scheme across all its supported debugging formats
5776 i.e. SDB (COFF), stabs and DWARF 2. This is because
5777 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5778 DBX_REGISTER_NUMBER macro which is defined by each target's
5779 respective config header in a manner independent of the requested
5780 output debugging format.
5782 This does not match the arrangement below, which presumes that
5783 the SDB and stabs numbering schemes differ from the DWARF and
5784 DWARF 2 ones. The reason for this arrangement is that it is
5785 likely to get the numbering scheme for the target's
5786 default/native debug format right. For targets where GCC is the
5787 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5788 targets where the native toolchain uses a different numbering
5789 scheme for a particular debug format (stabs-in-ELF on Solaris)
5790 the defaults below will have to be overridden, like
5791 i386_elf_init_abi() does. */
5793 /* Use the dbx register numbering scheme for stabs and COFF. */
5794 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5795 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5797 /* Use the SVR4 register numbering scheme for DWARF 2. */
5798 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5800 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5801 be in use on any of the supported i386 targets. */
5803 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5805 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5807 /* Call dummy code. */
5808 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5810 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5811 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5812 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5814 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5816 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5818 /* Stack grows downward. */
5819 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5821 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5822 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5823 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5825 set_gdbarch_frame_args_skip (gdbarch
, 8);
5827 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5829 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5831 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5833 /* Add the i386 register groups. */
5834 i386_add_reggroups (gdbarch
);
5835 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
5837 /* Helper for function argument information. */
5838 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5840 /* Hook the function epilogue frame unwinder. This unwinder is
5841 appended to the list first, so that it supercedes the Dwarf
5842 unwinder in function epilogues (where the Dwarf unwinder
5843 currently fails). */
5844 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
5846 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5847 to the list before the prologue-based unwinders, so that Dwarf
5848 CFI info will be used if it is available. */
5849 dwarf2_append_unwinders (gdbarch
);
5851 frame_base_set_default (gdbarch
, &i386_frame_base
);
5853 /* Pseudo registers may be changed by amd64_init_abi. */
5854 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5855 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5857 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
5858 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
5860 /* The default ABI includes general-purpose registers,
5861 floating-point registers, and the SSE registers. */
5862 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5864 /* Get the x86 target description from INFO. */
5865 tdesc
= info
.target_desc
;
5866 if (! tdesc_has_registers (tdesc
))
5868 tdep
->tdesc
= tdesc
;
5870 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
5871 tdep
->register_names
= i386_register_names
;
5873 tdep
->num_byte_regs
= 8;
5874 tdep
->num_word_regs
= 8;
5875 tdep
->num_dword_regs
= 0;
5876 tdep
->num_mmx_regs
= 8;
5878 tdesc_data
= tdesc_data_alloc ();
5880 /* Hook in ABI-specific overrides, if they have been registered. */
5881 info
.tdep_info
= (void *) tdesc_data
;
5882 gdbarch_init_osabi (info
, gdbarch
);
5884 /* Wire in pseudo registers. Number of pseudo registers may be
5886 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
5887 + tdep
->num_word_regs
5888 + tdep
->num_dword_regs
5889 + tdep
->num_mmx_regs
));
5891 /* Target description may be changed. */
5892 tdesc
= tdep
->tdesc
;
5894 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
5896 tdesc_data_cleanup (tdesc_data
);
5898 gdbarch_free (gdbarch
);
5902 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
5904 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
5905 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
5907 /* Make %al the first pseudo-register. */
5908 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
5909 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
5911 mm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
5912 if (tdep
->num_dword_regs
)
5914 /* Support dword pseudo-registesr if it hasn't been disabled, */
5915 tdep
->eax_regnum
= mm0_regnum
;
5916 mm0_regnum
= tdep
->eax_regnum
+ tdep
->num_dword_regs
;
5919 tdep
->eax_regnum
= -1;
5921 if (tdep
->num_mmx_regs
!= 0)
5923 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
5924 tdep
->mm0_regnum
= mm0_regnum
;
5927 tdep
->mm0_regnum
= -1;
5929 /* Hook in the legacy prologue-based unwinders last (fallback). */
5930 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5931 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5933 /* If we have a register mapping, enable the generic core file
5934 support, unless it has already been enabled. */
5935 if (tdep
->gregset_reg_offset
5936 && !gdbarch_regset_from_core_section_p (gdbarch
))
5937 set_gdbarch_regset_from_core_section (gdbarch
,
5938 i386_regset_from_core_section
);
5940 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5941 i386_skip_permanent_breakpoint
);
5943 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
5944 i386_fast_tracepoint_valid_at
);
5949 static enum gdb_osabi
5950 i386_coff_osabi_sniffer (bfd
*abfd
)
5952 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5953 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5954 return GDB_OSABI_GO32
;
5956 return GDB_OSABI_UNKNOWN
;
5960 /* Provide a prototype to silence -Wmissing-prototypes. */
5961 void _initialize_i386_tdep (void);
5964 _initialize_i386_tdep (void)
5966 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5968 /* Add the variable that controls the disassembly flavor. */
5969 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5970 &disassembly_flavor
, _("\
5971 Set the disassembly flavor."), _("\
5972 Show the disassembly flavor."), _("\
5973 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5975 NULL
, /* FIXME: i18n: */
5976 &setlist
, &showlist
);
5978 /* Add the variable that controls the convention for returning
5980 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5981 &struct_convention
, _("\
5982 Set the convention for returning small structs."), _("\
5983 Show the convention for returning small structs."), _("\
5984 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5987 NULL
, /* FIXME: i18n: */
5988 &setlist
, &showlist
);
5990 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5991 i386_coff_osabi_sniffer
);
5993 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5994 i386_svr4_init_abi
);
5995 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5996 i386_go32_init_abi
);
5998 /* Initialize the i386-specific register groups. */
5999 i386_init_reggroups ();
6001 /* Initialize the standard target descriptions. */
6002 initialize_tdesc_i386 ();