1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "gdb_assert.h"
49 #include "gdb_string.h"
51 #include "i386-tdep.h"
52 #include "i387-tdep.h"
59 static char *i386_register_names
[] =
61 "eax", "ecx", "edx", "ebx",
62 "esp", "ebp", "esi", "edi",
63 "eip", "eflags", "cs", "ss",
64 "ds", "es", "fs", "gs",
65 "st0", "st1", "st2", "st3",
66 "st4", "st5", "st6", "st7",
67 "fctrl", "fstat", "ftag", "fiseg",
68 "fioff", "foseg", "fooff", "fop",
69 "xmm0", "xmm1", "xmm2", "xmm3",
70 "xmm4", "xmm5", "xmm6", "xmm7",
74 static const int i386_num_register_names
= ARRAY_SIZE (i386_register_names
);
76 /* Register names for MMX pseudo-registers. */
78 static char *i386_mmx_names
[] =
80 "mm0", "mm1", "mm2", "mm3",
81 "mm4", "mm5", "mm6", "mm7"
84 static const int i386_num_mmx_regs
= ARRAY_SIZE (i386_mmx_names
);
87 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
89 int mm0_regnum
= gdbarch_tdep (gdbarch
)->mm0_regnum
;
94 return (regnum
>= mm0_regnum
&& regnum
< mm0_regnum
+ i386_num_mmx_regs
);
100 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
102 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
104 if (I387_NUM_XMM_REGS (tdep
) == 0)
107 return (I387_XMM0_REGNUM (tdep
) <= regnum
108 && regnum
< I387_MXCSR_REGNUM (tdep
));
112 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
116 if (I387_NUM_XMM_REGS (tdep
) == 0)
119 return (regnum
== I387_MXCSR_REGNUM (tdep
));
125 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
129 if (I387_ST0_REGNUM (tdep
) < 0)
132 return (I387_ST0_REGNUM (tdep
) <= regnum
133 && regnum
< I387_FCTRL_REGNUM (tdep
));
137 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 if (I387_ST0_REGNUM (tdep
) < 0)
144 return (I387_FCTRL_REGNUM (tdep
) <= regnum
145 && regnum
< I387_XMM0_REGNUM (tdep
));
148 /* Return the name of register REGNUM. */
151 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
153 if (i386_mmx_regnum_p (gdbarch
, regnum
))
154 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (gdbarch_tdep (gdbarch
))];
156 if (regnum
>= 0 && regnum
< i386_num_register_names
)
157 return i386_register_names
[regnum
];
162 /* Convert a dbx register number REG to the appropriate register
163 number used by GDB. */
166 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
170 /* This implements what GCC calls the "default" register map
171 (dbx_register_map[]). */
173 if (reg
>= 0 && reg
<= 7)
175 /* General-purpose registers. The debug info calls %ebp
176 register 4, and %esp register 5. */
183 else if (reg
>= 12 && reg
<= 19)
185 /* Floating-point registers. */
186 return reg
- 12 + I387_ST0_REGNUM (tdep
);
188 else if (reg
>= 21 && reg
<= 28)
191 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
193 else if (reg
>= 29 && reg
<= 36)
196 return reg
- 29 + I387_MM0_REGNUM (tdep
);
199 /* This will hopefully provoke a warning. */
200 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
203 /* Convert SVR4 register number REG to the appropriate register number
207 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
211 /* This implements the GCC register map that tries to be compatible
212 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
214 /* The SVR4 register numbering includes %eip and %eflags, and
215 numbers the floating point registers differently. */
216 if (reg
>= 0 && reg
<= 9)
218 /* General-purpose registers. */
221 else if (reg
>= 11 && reg
<= 18)
223 /* Floating-point registers. */
224 return reg
- 11 + I387_ST0_REGNUM (tdep
);
226 else if (reg
>= 21 && reg
<= 36)
228 /* The SSE and MMX registers have the same numbers as with dbx. */
229 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
234 case 37: return I387_FCTRL_REGNUM (tdep
);
235 case 38: return I387_FSTAT_REGNUM (tdep
);
236 case 39: return I387_MXCSR_REGNUM (tdep
);
237 case 40: return I386_ES_REGNUM
;
238 case 41: return I386_CS_REGNUM
;
239 case 42: return I386_SS_REGNUM
;
240 case 43: return I386_DS_REGNUM
;
241 case 44: return I386_FS_REGNUM
;
242 case 45: return I386_GS_REGNUM
;
245 /* This will hopefully provoke a warning. */
246 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
251 /* This is the variable that is set with "set disassembly-flavor", and
252 its legitimate values. */
253 static const char att_flavor
[] = "att";
254 static const char intel_flavor
[] = "intel";
255 static const char *valid_flavors
[] =
261 static const char *disassembly_flavor
= att_flavor
;
264 /* Use the program counter to determine the contents and size of a
265 breakpoint instruction. Return a pointer to a string of bytes that
266 encode a breakpoint instruction, store the length of the string in
267 *LEN and optionally adjust *PC to point to the correct memory
268 location for inserting the breakpoint.
270 On the i386 we have a single breakpoint that fits in a single byte
271 and can be inserted anywhere.
273 This function is 64-bit safe. */
275 static const gdb_byte
*
276 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
278 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
280 *len
= sizeof (break_insn
);
284 /* Displaced instruction handling. */
286 /* Skip the legacy instruction prefixes in INSN.
287 Not all prefixes are valid for any particular insn
288 but we needn't care, the insn will fault if it's invalid.
289 The result is a pointer to the first opcode byte,
290 or NULL if we run off the end of the buffer. */
293 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
295 gdb_byte
*end
= insn
+ max_len
;
301 case DATA_PREFIX_OPCODE
:
302 case ADDR_PREFIX_OPCODE
:
303 case CS_PREFIX_OPCODE
:
304 case DS_PREFIX_OPCODE
:
305 case ES_PREFIX_OPCODE
:
306 case FS_PREFIX_OPCODE
:
307 case GS_PREFIX_OPCODE
:
308 case SS_PREFIX_OPCODE
:
309 case LOCK_PREFIX_OPCODE
:
310 case REPE_PREFIX_OPCODE
:
311 case REPNE_PREFIX_OPCODE
:
323 i386_absolute_jmp_p (const gdb_byte
*insn
)
325 /* jmp far (absolute address in operand) */
331 /* jump near, absolute indirect (/4) */
332 if ((insn
[1] & 0x38) == 0x20)
335 /* jump far, absolute indirect (/5) */
336 if ((insn
[1] & 0x38) == 0x28)
344 i386_absolute_call_p (const gdb_byte
*insn
)
346 /* call far, absolute */
352 /* Call near, absolute indirect (/2) */
353 if ((insn
[1] & 0x38) == 0x10)
356 /* Call far, absolute indirect (/3) */
357 if ((insn
[1] & 0x38) == 0x18)
365 i386_ret_p (const gdb_byte
*insn
)
369 case 0xc2: /* ret near, pop N bytes */
370 case 0xc3: /* ret near */
371 case 0xca: /* ret far, pop N bytes */
372 case 0xcb: /* ret far */
373 case 0xcf: /* iret */
382 i386_call_p (const gdb_byte
*insn
)
384 if (i386_absolute_call_p (insn
))
387 /* call near, relative */
394 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
395 length in bytes. Otherwise, return zero. */
398 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
409 /* Fix up the state of registers and memory after having single-stepped
410 a displaced instruction. */
413 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
414 struct displaced_step_closure
*closure
,
415 CORE_ADDR from
, CORE_ADDR to
,
416 struct regcache
*regs
)
418 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
420 /* The offset we applied to the instruction's address.
421 This could well be negative (when viewed as a signed 32-bit
422 value), but ULONGEST won't reflect that, so take care when
424 ULONGEST insn_offset
= to
- from
;
426 /* Since we use simple_displaced_step_copy_insn, our closure is a
427 copy of the instruction. */
428 gdb_byte
*insn
= (gdb_byte
*) closure
;
429 /* The start of the insn, needed in case we see some prefixes. */
430 gdb_byte
*insn_start
= insn
;
433 fprintf_unfiltered (gdb_stdlog
,
434 "displaced: fixup (%s, %s), "
435 "insn = 0x%02x 0x%02x ...\n",
436 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
439 /* The list of issues to contend with here is taken from
440 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
441 Yay for Free Software! */
443 /* Relocate the %eip, if necessary. */
445 /* The instruction recognizers we use assume any leading prefixes
446 have been skipped. */
448 /* This is the size of the buffer in closure. */
449 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
450 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
451 /* If there are too many prefixes, just ignore the insn.
452 It will fault when run. */
457 /* Except in the case of absolute or indirect jump or call
458 instructions, or a return instruction, the new eip is relative to
459 the displaced instruction; make it relative. Well, signal
460 handler returns don't need relocation either, but we use the
461 value of %eip to recognize those; see below. */
462 if (! i386_absolute_jmp_p (insn
)
463 && ! i386_absolute_call_p (insn
)
464 && ! i386_ret_p (insn
))
469 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
471 /* A signal trampoline system call changes the %eip, resuming
472 execution of the main program after the signal handler has
473 returned. That makes them like 'return' instructions; we
474 shouldn't relocate %eip.
476 But most system calls don't, and we do need to relocate %eip.
478 Our heuristic for distinguishing these cases: if stepping
479 over the system call instruction left control directly after
480 the instruction, the we relocate --- control almost certainly
481 doesn't belong in the displaced copy. Otherwise, we assume
482 the instruction has put control where it belongs, and leave
483 it unrelocated. Goodness help us if there are PC-relative
485 if (i386_syscall_p (insn
, &insn_len
)
486 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
489 fprintf_unfiltered (gdb_stdlog
,
490 "displaced: syscall changed %%eip; "
495 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
497 /* If we just stepped over a breakpoint insn, we don't backup
498 the pc on purpose; this is to match behaviour without
501 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
504 fprintf_unfiltered (gdb_stdlog
,
506 "relocated %%eip from %s to %s\n",
507 paddress (gdbarch
, orig_eip
),
508 paddress (gdbarch
, eip
));
512 /* If the instruction was PUSHFL, then the TF bit will be set in the
513 pushed value, and should be cleared. We'll leave this for later,
514 since GDB already messes up the TF flag when stepping over a
517 /* If the instruction was a call, the return address now atop the
518 stack is the address following the copied instruction. We need
519 to make it the address following the original instruction. */
520 if (i386_call_p (insn
))
524 const ULONGEST retaddr_len
= 4;
526 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
527 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
528 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
529 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
532 fprintf_unfiltered (gdb_stdlog
,
533 "displaced: relocated return addr at %s to %s\n",
534 paddress (gdbarch
, esp
),
535 paddress (gdbarch
, retaddr
));
539 #ifdef I386_REGNO_TO_SYMMETRY
540 #error "The Sequent Symmetry is no longer supported."
543 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
544 and %esp "belong" to the calling function. Therefore these
545 registers should be saved if they're going to be modified. */
547 /* The maximum number of saved registers. This should include all
548 registers mentioned above, and %eip. */
549 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
551 struct i386_frame_cache
558 /* Saved registers. */
559 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
564 /* Stack space reserved for local variables. */
568 /* Allocate and initialize a frame cache. */
570 static struct i386_frame_cache
*
571 i386_alloc_frame_cache (void)
573 struct i386_frame_cache
*cache
;
576 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
580 cache
->sp_offset
= -4;
583 /* Saved registers. We initialize these to -1 since zero is a valid
584 offset (that's where %ebp is supposed to be stored). */
585 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
586 cache
->saved_regs
[i
] = -1;
588 cache
->saved_sp_reg
= -1;
589 cache
->pc_in_eax
= 0;
591 /* Frameless until proven otherwise. */
597 /* If the instruction at PC is a jump, return the address of its
598 target. Otherwise, return PC. */
601 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
603 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
608 target_read_memory (pc
, &op
, 1);
612 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
618 /* Relative jump: if data16 == 0, disp32, else disp16. */
621 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
623 /* Include the size of the jmp instruction (including the
629 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
631 /* Include the size of the jmp instruction. */
636 /* Relative jump, disp8 (ignore data16). */
637 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
646 /* Check whether PC points at a prologue for a function returning a
647 structure or union. If so, it updates CACHE and returns the
648 address of the first instruction after the code sequence that
649 removes the "hidden" argument from the stack or CURRENT_PC,
650 whichever is smaller. Otherwise, return PC. */
653 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
654 struct i386_frame_cache
*cache
)
656 /* Functions that return a structure or union start with:
659 xchgl %eax, (%esp) 0x87 0x04 0x24
660 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
662 (the System V compiler puts out the second `xchg' instruction,
663 and the assembler doesn't try to optimize it, so the 'sib' form
664 gets generated). This sequence is used to get the address of the
665 return buffer for a function that returns a structure. */
666 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
667 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
671 if (current_pc
<= pc
)
674 target_read_memory (pc
, &op
, 1);
676 if (op
!= 0x58) /* popl %eax */
679 target_read_memory (pc
+ 1, buf
, 4);
680 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
683 if (current_pc
== pc
)
685 cache
->sp_offset
+= 4;
689 if (current_pc
== pc
+ 1)
691 cache
->pc_in_eax
= 1;
695 if (buf
[1] == proto1
[1])
702 i386_skip_probe (CORE_ADDR pc
)
704 /* A function may start with
718 target_read_memory (pc
, &op
, 1);
720 if (op
== 0x68 || op
== 0x6a)
724 /* Skip past the `pushl' instruction; it has either a one-byte or a
725 four-byte operand, depending on the opcode. */
731 /* Read the following 8 bytes, which should be `call _probe' (6
732 bytes) followed by `addl $4,%esp' (2 bytes). */
733 read_memory (pc
+ delta
, buf
, sizeof (buf
));
734 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
735 pc
+= delta
+ sizeof (buf
);
741 /* GCC 4.1 and later, can put code in the prologue to realign the
742 stack pointer. Check whether PC points to such code, and update
743 CACHE accordingly. Return the first instruction after the code
744 sequence or CURRENT_PC, whichever is smaller. If we don't
745 recognize the code, return PC. */
748 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
749 struct i386_frame_cache
*cache
)
751 /* There are 2 code sequences to re-align stack before the frame
754 1. Use a caller-saved saved register:
760 2. Use a callee-saved saved register:
767 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
769 0x83 0xe4 0xf0 andl $-16, %esp
770 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
775 int offset
, offset_and
;
776 static int regnums
[8] = {
777 I386_EAX_REGNUM
, /* %eax */
778 I386_ECX_REGNUM
, /* %ecx */
779 I386_EDX_REGNUM
, /* %edx */
780 I386_EBX_REGNUM
, /* %ebx */
781 I386_ESP_REGNUM
, /* %esp */
782 I386_EBP_REGNUM
, /* %ebp */
783 I386_ESI_REGNUM
, /* %esi */
784 I386_EDI_REGNUM
/* %edi */
787 if (target_read_memory (pc
, buf
, sizeof buf
))
790 /* Check caller-saved saved register. The first instruction has
791 to be "leal 4(%esp), %reg". */
792 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
794 /* MOD must be binary 10 and R/M must be binary 100. */
795 if ((buf
[1] & 0xc7) != 0x44)
798 /* REG has register number. */
799 reg
= (buf
[1] >> 3) & 7;
804 /* Check callee-saved saved register. The first instruction
805 has to be "pushl %reg". */
806 if ((buf
[0] & 0xf8) != 0x50)
812 /* The next instruction has to be "leal 8(%esp), %reg". */
813 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
816 /* MOD must be binary 10 and R/M must be binary 100. */
817 if ((buf
[2] & 0xc7) != 0x44)
820 /* REG has register number. Registers in pushl and leal have to
822 if (reg
!= ((buf
[2] >> 3) & 7))
828 /* Rigister can't be %esp nor %ebp. */
829 if (reg
== 4 || reg
== 5)
832 /* The next instruction has to be "andl $-XXX, %esp". */
833 if (buf
[offset
+ 1] != 0xe4
834 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
838 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
840 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
841 0xfc. REG must be binary 110 and MOD must be binary 01. */
842 if (buf
[offset
] != 0xff
843 || buf
[offset
+ 2] != 0xfc
844 || (buf
[offset
+ 1] & 0xf8) != 0x70)
847 /* R/M has register. Registers in leal and pushl have to be the
849 if (reg
!= (buf
[offset
+ 1] & 7))
852 if (current_pc
> pc
+ offset_and
)
853 cache
->saved_sp_reg
= regnums
[reg
];
855 return min (pc
+ offset
+ 3, current_pc
);
858 /* Maximum instruction length we need to handle. */
859 #define I386_MAX_MATCHED_INSN_LEN 6
861 /* Instruction description. */
865 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
866 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
869 /* Search for the instruction at PC in the list SKIP_INSNS. Return
870 the first instruction description that matches. Otherwise, return
873 static struct i386_insn
*
874 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
876 struct i386_insn
*insn
;
879 target_read_memory (pc
, &op
, 1);
881 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
883 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
885 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
886 int insn_matched
= 1;
889 gdb_assert (insn
->len
> 1);
890 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
892 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
893 for (i
= 1; i
< insn
->len
; i
++)
895 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
907 /* Some special instructions that might be migrated by GCC into the
908 part of the prologue that sets up the new stack frame. Because the
909 stack frame hasn't been setup yet, no registers have been saved
910 yet, and only the scratch registers %eax, %ecx and %edx can be
913 struct i386_insn i386_frame_setup_skip_insns
[] =
915 /* Check for `movb imm8, r' and `movl imm32, r'.
917 ??? Should we handle 16-bit operand-sizes here? */
919 /* `movb imm8, %al' and `movb imm8, %ah' */
920 /* `movb imm8, %cl' and `movb imm8, %ch' */
921 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
922 /* `movb imm8, %dl' and `movb imm8, %dh' */
923 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
924 /* `movl imm32, %eax' and `movl imm32, %ecx' */
925 { 5, { 0xb8 }, { 0xfe } },
926 /* `movl imm32, %edx' */
927 { 5, { 0xba }, { 0xff } },
929 /* Check for `mov imm32, r32'. Note that there is an alternative
930 encoding for `mov m32, %eax'.
932 ??? Should we handle SIB adressing here?
933 ??? Should we handle 16-bit operand-sizes here? */
935 /* `movl m32, %eax' */
936 { 5, { 0xa1 }, { 0xff } },
937 /* `movl m32, %eax' and `mov; m32, %ecx' */
938 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
939 /* `movl m32, %edx' */
940 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
942 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
943 Because of the symmetry, there are actually two ways to encode
944 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
945 opcode bytes 0x31 and 0x33 for `xorl'. */
947 /* `subl %eax, %eax' */
948 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
949 /* `subl %ecx, %ecx' */
950 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
951 /* `subl %edx, %edx' */
952 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
953 /* `xorl %eax, %eax' */
954 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
955 /* `xorl %ecx, %ecx' */
956 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
957 /* `xorl %edx, %edx' */
958 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
963 /* Check whether PC points to a no-op instruction. */
965 i386_skip_noop (CORE_ADDR pc
)
970 target_read_memory (pc
, &op
, 1);
975 /* Ignore `nop' instruction. */
979 target_read_memory (pc
, &op
, 1);
982 /* Ignore no-op instruction `mov %edi, %edi'.
983 Microsoft system dlls often start with
984 a `mov %edi,%edi' instruction.
985 The 5 bytes before the function start are
986 filled with `nop' instructions.
987 This pattern can be used for hot-patching:
988 The `mov %edi, %edi' instruction can be replaced by a
989 near jump to the location of the 5 `nop' instructions
990 which can be replaced by a 32-bit jump to anywhere
991 in the 32-bit address space. */
995 target_read_memory (pc
+ 1, &op
, 1);
999 target_read_memory (pc
, &op
, 1);
1007 /* Check whether PC points at a code that sets up a new stack frame.
1008 If so, it updates CACHE and returns the address of the first
1009 instruction after the sequence that sets up the frame or LIMIT,
1010 whichever is smaller. If we don't recognize the code, return PC. */
1013 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1014 CORE_ADDR pc
, CORE_ADDR limit
,
1015 struct i386_frame_cache
*cache
)
1017 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1018 struct i386_insn
*insn
;
1025 target_read_memory (pc
, &op
, 1);
1027 if (op
== 0x55) /* pushl %ebp */
1029 /* Take into account that we've executed the `pushl %ebp' that
1030 starts this instruction sequence. */
1031 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1032 cache
->sp_offset
+= 4;
1035 /* If that's all, return now. */
1039 /* Check for some special instructions that might be migrated by
1040 GCC into the prologue and skip them. At this point in the
1041 prologue, code should only touch the scratch registers %eax,
1042 %ecx and %edx, so while the number of posibilities is sheer,
1045 Make sure we only skip these instructions if we later see the
1046 `movl %esp, %ebp' that actually sets up the frame. */
1047 while (pc
+ skip
< limit
)
1049 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1056 /* If that's all, return now. */
1057 if (limit
<= pc
+ skip
)
1060 target_read_memory (pc
+ skip
, &op
, 1);
1062 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1066 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1071 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1079 /* OK, we actually have a frame. We just don't know how large
1080 it is yet. Set its size to zero. We'll adjust it if
1081 necessary. We also now commit to skipping the special
1082 instructions mentioned before. */
1086 /* If that's all, return now. */
1090 /* Check for stack adjustment
1094 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1095 reg, so we don't have to worry about a data16 prefix. */
1096 target_read_memory (pc
, &op
, 1);
1099 /* `subl' with 8-bit immediate. */
1100 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1101 /* Some instruction starting with 0x83 other than `subl'. */
1104 /* `subl' with signed 8-bit immediate (though it wouldn't
1105 make sense to be negative). */
1106 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1109 else if (op
== 0x81)
1111 /* Maybe it is `subl' with a 32-bit immediate. */
1112 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1113 /* Some instruction starting with 0x81 other than `subl'. */
1116 /* It is `subl' with a 32-bit immediate. */
1117 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1122 /* Some instruction other than `subl'. */
1126 else if (op
== 0xc8) /* enter */
1128 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1135 /* Check whether PC points at code that saves registers on the stack.
1136 If so, it updates CACHE and returns the address of the first
1137 instruction after the register saves or CURRENT_PC, whichever is
1138 smaller. Otherwise, return PC. */
1141 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1142 struct i386_frame_cache
*cache
)
1144 CORE_ADDR offset
= 0;
1148 if (cache
->locals
> 0)
1149 offset
-= cache
->locals
;
1150 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1152 target_read_memory (pc
, &op
, 1);
1153 if (op
< 0x50 || op
> 0x57)
1157 cache
->saved_regs
[op
- 0x50] = offset
;
1158 cache
->sp_offset
+= 4;
1165 /* Do a full analysis of the prologue at PC and update CACHE
1166 accordingly. Bail out early if CURRENT_PC is reached. Return the
1167 address where the analysis stopped.
1169 We handle these cases:
1171 The startup sequence can be at the start of the function, or the
1172 function can start with a branch to startup code at the end.
1174 %ebp can be set up with either the 'enter' instruction, or "pushl
1175 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1176 once used in the System V compiler).
1178 Local space is allocated just below the saved %ebp by either the
1179 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1180 16-bit unsigned argument for space to allocate, and the 'addl'
1181 instruction could have either a signed byte, or 32-bit immediate.
1183 Next, the registers used by this function are pushed. With the
1184 System V compiler they will always be in the order: %edi, %esi,
1185 %ebx (and sometimes a harmless bug causes it to also save but not
1186 restore %eax); however, the code below is willing to see the pushes
1187 in any order, and will handle up to 8 of them.
1189 If the setup sequence is at the end of the function, then the next
1190 instruction will be a branch back to the start. */
1193 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1194 CORE_ADDR pc
, CORE_ADDR current_pc
,
1195 struct i386_frame_cache
*cache
)
1197 pc
= i386_skip_noop (pc
);
1198 pc
= i386_follow_jump (gdbarch
, pc
);
1199 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1200 pc
= i386_skip_probe (pc
);
1201 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1202 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1203 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1206 /* Return PC of first real instruction. */
1209 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1211 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1213 static gdb_byte pic_pat
[6] =
1215 0xe8, 0, 0, 0, 0, /* call 0x0 */
1216 0x5b, /* popl %ebx */
1218 struct i386_frame_cache cache
;
1224 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1225 if (cache
.locals
< 0)
1228 /* Found valid frame setup. */
1230 /* The native cc on SVR4 in -K PIC mode inserts the following code
1231 to get the address of the global offset table (GOT) into register
1236 movl %ebx,x(%ebp) (optional)
1239 This code is with the rest of the prologue (at the end of the
1240 function), so we have to skip it to get to the first real
1241 instruction at the start of the function. */
1243 for (i
= 0; i
< 6; i
++)
1245 target_read_memory (pc
+ i
, &op
, 1);
1246 if (pic_pat
[i
] != op
)
1253 target_read_memory (pc
+ delta
, &op
, 1);
1255 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1257 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1259 if (op
== 0x5d) /* One byte offset from %ebp. */
1261 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1263 else /* Unexpected instruction. */
1266 target_read_memory (pc
+ delta
, &op
, 1);
1270 if (delta
> 0 && op
== 0x81
1271 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1278 /* If the function starts with a branch (to startup code at the end)
1279 the last instruction should bring us back to the first
1280 instruction of the real code. */
1281 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1282 pc
= i386_follow_jump (gdbarch
, pc
);
1287 /* Check that the code pointed to by PC corresponds to a call to
1288 __main, skip it if so. Return PC otherwise. */
1291 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1293 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1296 target_read_memory (pc
, &op
, 1);
1301 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1303 /* Make sure address is computed correctly as a 32bit
1304 integer even if CORE_ADDR is 64 bit wide. */
1305 struct minimal_symbol
*s
;
1306 CORE_ADDR call_dest
;
1308 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1309 call_dest
= call_dest
& 0xffffffffU
;
1310 s
= lookup_minimal_symbol_by_pc (call_dest
);
1312 && SYMBOL_LINKAGE_NAME (s
) != NULL
1313 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1321 /* This function is 64-bit safe. */
1324 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1328 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1329 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1333 /* Normal frames. */
1335 static struct i386_frame_cache
*
1336 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1338 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1339 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 struct i386_frame_cache
*cache
;
1347 cache
= i386_alloc_frame_cache ();
1348 *this_cache
= cache
;
1350 /* In principle, for normal frames, %ebp holds the frame pointer,
1351 which holds the base address for the current stack frame.
1352 However, for functions that don't need it, the frame pointer is
1353 optional. For these "frameless" functions the frame pointer is
1354 actually the frame pointer of the calling frame. Signal
1355 trampolines are just a special case of a "frameless" function.
1356 They (usually) share their frame pointer with the frame that was
1357 in progress when the signal occurred. */
1359 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1360 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1361 if (cache
->base
== 0)
1364 /* For normal frames, %eip is stored at 4(%ebp). */
1365 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1367 cache
->pc
= get_frame_func (this_frame
);
1369 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1372 if (cache
->saved_sp_reg
!= -1)
1374 /* Saved stack pointer has been saved. */
1375 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1376 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1379 if (cache
->locals
< 0)
1381 /* We didn't find a valid frame, which means that CACHE->base
1382 currently holds the frame pointer for our calling frame. If
1383 we're at the start of a function, or somewhere half-way its
1384 prologue, the function's frame probably hasn't been fully
1385 setup yet. Try to reconstruct the base address for the stack
1386 frame by looking at the stack pointer. For truly "frameless"
1387 functions this might work too. */
1389 if (cache
->saved_sp_reg
!= -1)
1391 /* We're halfway aligning the stack. */
1392 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1393 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1395 /* This will be added back below. */
1396 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1398 else if (cache
->pc
!= 0
1399 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1401 /* We're in a known function, but did not find a frame
1402 setup. Assume that the function does not use %ebp.
1403 Alternatively, we may have jumped to an invalid
1404 address; in that case there is definitely no new
1406 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1407 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1411 /* We're in an unknown function. We could not find the start
1412 of the function to analyze the prologue; our best option is
1413 to assume a typical frame layout with the caller's %ebp
1415 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1418 /* Now that we have the base address for the stack frame we can
1419 calculate the value of %esp in the calling frame. */
1420 if (cache
->saved_sp
== 0)
1421 cache
->saved_sp
= cache
->base
+ 8;
1423 /* Adjust all the saved registers such that they contain addresses
1424 instead of offsets. */
1425 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1426 if (cache
->saved_regs
[i
] != -1)
1427 cache
->saved_regs
[i
] += cache
->base
;
1433 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1434 struct frame_id
*this_id
)
1436 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1438 /* This marks the outermost frame. */
1439 if (cache
->base
== 0)
1442 /* See the end of i386_push_dummy_call. */
1443 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1446 static struct value
*
1447 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1450 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1452 gdb_assert (regnum
>= 0);
1454 /* The System V ABI says that:
1456 "The flags register contains the system flags, such as the
1457 direction flag and the carry flag. The direction flag must be
1458 set to the forward (that is, zero) direction before entry and
1459 upon exit from a function. Other user flags have no specified
1460 role in the standard calling sequence and are not preserved."
1462 To guarantee the "upon exit" part of that statement we fake a
1463 saved flags register that has its direction flag cleared.
1465 Note that GCC doesn't seem to rely on the fact that the direction
1466 flag is cleared after a function return; it always explicitly
1467 clears the flag before operations where it matters.
1469 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1470 right thing to do. The way we fake the flags register here makes
1471 it impossible to change it. */
1473 if (regnum
== I386_EFLAGS_REGNUM
)
1477 val
= get_frame_register_unsigned (this_frame
, regnum
);
1479 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1482 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1483 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1485 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1486 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1488 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1489 return frame_unwind_got_memory (this_frame
, regnum
,
1490 cache
->saved_regs
[regnum
]);
1492 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1495 static const struct frame_unwind i386_frame_unwind
=
1499 i386_frame_prev_register
,
1501 default_frame_sniffer
1504 /* Normal frames, but in a function epilogue. */
1506 /* The epilogue is defined here as the 'ret' instruction, which will
1507 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1508 the function's stack frame. */
1511 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1515 if (target_read_memory (pc
, &insn
, 1))
1516 return 0; /* Can't read memory at pc. */
1518 if (insn
!= 0xc3) /* 'ret' instruction. */
1525 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1526 struct frame_info
*this_frame
,
1527 void **this_prologue_cache
)
1529 if (frame_relative_level (this_frame
) == 0)
1530 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1531 get_frame_pc (this_frame
));
1536 static struct i386_frame_cache
*
1537 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1539 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1540 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1541 struct i386_frame_cache
*cache
;
1547 cache
= i386_alloc_frame_cache ();
1548 *this_cache
= cache
;
1550 /* Cache base will be %esp plus cache->sp_offset (-4). */
1551 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1552 cache
->base
= extract_unsigned_integer (buf
, 4,
1553 byte_order
) + cache
->sp_offset
;
1555 /* Cache pc will be the frame func. */
1556 cache
->pc
= get_frame_pc (this_frame
);
1558 /* The saved %esp will be at cache->base plus 8. */
1559 cache
->saved_sp
= cache
->base
+ 8;
1561 /* The saved %eip will be at cache->base plus 4. */
1562 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1568 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1570 struct frame_id
*this_id
)
1572 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1575 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1578 static const struct frame_unwind i386_epilogue_frame_unwind
=
1581 i386_epilogue_frame_this_id
,
1582 i386_frame_prev_register
,
1584 i386_epilogue_frame_sniffer
1588 /* Signal trampolines. */
1590 static struct i386_frame_cache
*
1591 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1593 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1594 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1595 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1596 struct i386_frame_cache
*cache
;
1603 cache
= i386_alloc_frame_cache ();
1605 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1606 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1608 addr
= tdep
->sigcontext_addr (this_frame
);
1609 if (tdep
->sc_reg_offset
)
1613 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1615 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1616 if (tdep
->sc_reg_offset
[i
] != -1)
1617 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1621 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1622 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1625 *this_cache
= cache
;
1630 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1631 struct frame_id
*this_id
)
1633 struct i386_frame_cache
*cache
=
1634 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1636 /* See the end of i386_push_dummy_call. */
1637 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1640 static struct value
*
1641 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1642 void **this_cache
, int regnum
)
1644 /* Make sure we've initialized the cache. */
1645 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1647 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1651 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1652 struct frame_info
*this_frame
,
1653 void **this_prologue_cache
)
1655 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1657 /* We shouldn't even bother if we don't have a sigcontext_addr
1659 if (tdep
->sigcontext_addr
== NULL
)
1662 if (tdep
->sigtramp_p
!= NULL
)
1664 if (tdep
->sigtramp_p (this_frame
))
1668 if (tdep
->sigtramp_start
!= 0)
1670 CORE_ADDR pc
= get_frame_pc (this_frame
);
1672 gdb_assert (tdep
->sigtramp_end
!= 0);
1673 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1680 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1683 i386_sigtramp_frame_this_id
,
1684 i386_sigtramp_frame_prev_register
,
1686 i386_sigtramp_frame_sniffer
1691 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1693 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1698 static const struct frame_base i386_frame_base
=
1701 i386_frame_base_address
,
1702 i386_frame_base_address
,
1703 i386_frame_base_address
1706 static struct frame_id
1707 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1711 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1713 /* See the end of i386_push_dummy_call. */
1714 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1718 /* Figure out where the longjmp will land. Slurp the args out of the
1719 stack. We expect the first arg to be a pointer to the jmp_buf
1720 structure from which we extract the address that we will land at.
1721 This address is copied into PC. This routine returns non-zero on
1725 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1728 CORE_ADDR sp
, jb_addr
;
1729 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1730 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1731 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1733 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1734 longjmp will land. */
1735 if (jb_pc_offset
== -1)
1738 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1739 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1740 if (target_read_memory (sp
+ 4, buf
, 4))
1743 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1744 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1747 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1752 /* Check whether TYPE must be 16-byte-aligned when passed as a
1753 function argument. 16-byte vectors, _Decimal128 and structures or
1754 unions containing such types must be 16-byte-aligned; other
1755 arguments are 4-byte-aligned. */
1758 i386_16_byte_align_p (struct type
*type
)
1760 type
= check_typedef (type
);
1761 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1762 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1763 && TYPE_LENGTH (type
) == 16)
1765 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1766 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1767 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1768 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1771 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1773 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1781 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1782 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1783 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1784 CORE_ADDR struct_addr
)
1786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1792 /* Determine the total space required for arguments and struct
1793 return address in a first pass (allowing for 16-byte-aligned
1794 arguments), then push arguments in a second pass. */
1796 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1798 int args_space_used
= 0;
1799 int have_16_byte_aligned_arg
= 0;
1805 /* Push value address. */
1806 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1807 write_memory (sp
, buf
, 4);
1808 args_space_used
+= 4;
1814 for (i
= 0; i
< nargs
; i
++)
1816 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1820 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1821 args_space_used
= align_up (args_space_used
, 16);
1823 write_memory (sp
+ args_space_used
,
1824 value_contents_all (args
[i
]), len
);
1825 /* The System V ABI says that:
1827 "An argument's size is increased, if necessary, to make it a
1828 multiple of [32-bit] words. This may require tail padding,
1829 depending on the size of the argument."
1831 This makes sure the stack stays word-aligned. */
1832 args_space_used
+= align_up (len
, 4);
1836 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1838 args_space
= align_up (args_space
, 16);
1839 have_16_byte_aligned_arg
= 1;
1841 args_space
+= align_up (len
, 4);
1847 if (have_16_byte_aligned_arg
)
1848 args_space
= align_up (args_space
, 16);
1853 /* Store return address. */
1855 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1856 write_memory (sp
, buf
, 4);
1858 /* Finally, update the stack pointer... */
1859 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1860 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1862 /* ...and fake a frame pointer. */
1863 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1865 /* MarkK wrote: This "+ 8" is all over the place:
1866 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1867 i386_dummy_id). It's there, since all frame unwinders for
1868 a given target have to agree (within a certain margin) on the
1869 definition of the stack address of a frame. Otherwise frame id
1870 comparison might not work correctly. Since DWARF2/GCC uses the
1871 stack address *before* the function call as a frame's CFA. On
1872 the i386, when %ebp is used as a frame pointer, the offset
1873 between the contents %ebp and the CFA as defined by GCC. */
1877 /* These registers are used for returning integers (and on some
1878 targets also for returning `struct' and `union' values when their
1879 size and alignment match an integer type). */
1880 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1881 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1883 /* Read, for architecture GDBARCH, a function return value of TYPE
1884 from REGCACHE, and copy that into VALBUF. */
1887 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1888 struct regcache
*regcache
, gdb_byte
*valbuf
)
1890 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1891 int len
= TYPE_LENGTH (type
);
1892 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1894 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1896 if (tdep
->st0_regnum
< 0)
1898 warning (_("Cannot find floating-point return value."));
1899 memset (valbuf
, 0, len
);
1903 /* Floating-point return values can be found in %st(0). Convert
1904 its contents to the desired type. This is probably not
1905 exactly how it would happen on the target itself, but it is
1906 the best we can do. */
1907 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1908 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1912 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1913 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1915 if (len
<= low_size
)
1917 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1918 memcpy (valbuf
, buf
, len
);
1920 else if (len
<= (low_size
+ high_size
))
1922 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1923 memcpy (valbuf
, buf
, low_size
);
1924 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1925 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1928 internal_error (__FILE__
, __LINE__
,
1929 _("Cannot extract return value of %d bytes long."), len
);
1933 /* Write, for architecture GDBARCH, a function return value of TYPE
1934 from VALBUF into REGCACHE. */
1937 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1938 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1941 int len
= TYPE_LENGTH (type
);
1943 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1946 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1948 if (tdep
->st0_regnum
< 0)
1950 warning (_("Cannot set floating-point return value."));
1954 /* Returning floating-point values is a bit tricky. Apart from
1955 storing the return value in %st(0), we have to simulate the
1956 state of the FPU at function return point. */
1958 /* Convert the value found in VALBUF to the extended
1959 floating-point format used by the FPU. This is probably
1960 not exactly how it would happen on the target itself, but
1961 it is the best we can do. */
1962 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
1963 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
1965 /* Set the top of the floating-point register stack to 7. The
1966 actual value doesn't really matter, but 7 is what a normal
1967 function return would end up with if the program started out
1968 with a freshly initialized FPU. */
1969 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1971 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1973 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1974 the floating-point register stack to 7, the appropriate value
1975 for the tag word is 0x3fff. */
1976 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
1980 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1981 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1983 if (len
<= low_size
)
1984 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
1985 else if (len
<= (low_size
+ high_size
))
1987 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
1988 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
1989 len
- low_size
, valbuf
+ low_size
);
1992 internal_error (__FILE__
, __LINE__
,
1993 _("Cannot store return value of %d bytes long."), len
);
1998 /* This is the variable that is set with "set struct-convention", and
1999 its legitimate values. */
2000 static const char default_struct_convention
[] = "default";
2001 static const char pcc_struct_convention
[] = "pcc";
2002 static const char reg_struct_convention
[] = "reg";
2003 static const char *valid_conventions
[] =
2005 default_struct_convention
,
2006 pcc_struct_convention
,
2007 reg_struct_convention
,
2010 static const char *struct_convention
= default_struct_convention
;
2012 /* Return non-zero if TYPE, which is assumed to be a structure,
2013 a union type, or an array type, should be returned in registers
2014 for architecture GDBARCH. */
2017 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2019 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2020 enum type_code code
= TYPE_CODE (type
);
2021 int len
= TYPE_LENGTH (type
);
2023 gdb_assert (code
== TYPE_CODE_STRUCT
2024 || code
== TYPE_CODE_UNION
2025 || code
== TYPE_CODE_ARRAY
);
2027 if (struct_convention
== pcc_struct_convention
2028 || (struct_convention
== default_struct_convention
2029 && tdep
->struct_return
== pcc_struct_return
))
2032 /* Structures consisting of a single `float', `double' or 'long
2033 double' member are returned in %st(0). */
2034 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2036 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2037 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2038 return (len
== 4 || len
== 8 || len
== 12);
2041 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2044 /* Determine, for architecture GDBARCH, how a return value of TYPE
2045 should be returned. If it is supposed to be returned in registers,
2046 and READBUF is non-zero, read the appropriate value from REGCACHE,
2047 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2048 from WRITEBUF into REGCACHE. */
2050 static enum return_value_convention
2051 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2052 struct type
*type
, struct regcache
*regcache
,
2053 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2055 enum type_code code
= TYPE_CODE (type
);
2057 if (((code
== TYPE_CODE_STRUCT
2058 || code
== TYPE_CODE_UNION
2059 || code
== TYPE_CODE_ARRAY
)
2060 && !i386_reg_struct_return_p (gdbarch
, type
))
2061 /* 128-bit decimal float uses the struct return convention. */
2062 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2064 /* The System V ABI says that:
2066 "A function that returns a structure or union also sets %eax
2067 to the value of the original address of the caller's area
2068 before it returns. Thus when the caller receives control
2069 again, the address of the returned object resides in register
2070 %eax and can be used to access the object."
2072 So the ABI guarantees that we can always find the return
2073 value just after the function has returned. */
2075 /* Note that the ABI doesn't mention functions returning arrays,
2076 which is something possible in certain languages such as Ada.
2077 In this case, the value is returned as if it was wrapped in
2078 a record, so the convention applied to records also applies
2085 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2086 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2089 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2092 /* This special case is for structures consisting of a single
2093 `float', `double' or 'long double' member. These structures are
2094 returned in %st(0). For these structures, we call ourselves
2095 recursively, changing TYPE into the type of the first member of
2096 the structure. Since that should work for all structures that
2097 have only one member, we don't bother to check the member's type
2099 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2101 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2102 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2107 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2109 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2111 return RETURN_VALUE_REGISTER_CONVENTION
;
2115 /* Construct types for ISA-specific registers. */
2117 i386_eflags_type (struct gdbarch
*gdbarch
)
2119 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2121 if (!tdep
->i386_eflags_type
)
2125 type
= arch_flags_type (gdbarch
, "builtin_type_i386_eflags", 4);
2126 append_flags_type_flag (type
, 0, "CF");
2127 append_flags_type_flag (type
, 1, NULL
);
2128 append_flags_type_flag (type
, 2, "PF");
2129 append_flags_type_flag (type
, 4, "AF");
2130 append_flags_type_flag (type
, 6, "ZF");
2131 append_flags_type_flag (type
, 7, "SF");
2132 append_flags_type_flag (type
, 8, "TF");
2133 append_flags_type_flag (type
, 9, "IF");
2134 append_flags_type_flag (type
, 10, "DF");
2135 append_flags_type_flag (type
, 11, "OF");
2136 append_flags_type_flag (type
, 14, "NT");
2137 append_flags_type_flag (type
, 16, "RF");
2138 append_flags_type_flag (type
, 17, "VM");
2139 append_flags_type_flag (type
, 18, "AC");
2140 append_flags_type_flag (type
, 19, "VIF");
2141 append_flags_type_flag (type
, 20, "VIP");
2142 append_flags_type_flag (type
, 21, "ID");
2144 tdep
->i386_eflags_type
= type
;
2147 return tdep
->i386_eflags_type
;
2151 i386_mxcsr_type (struct gdbarch
*gdbarch
)
2153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2155 if (!tdep
->i386_mxcsr_type
)
2159 type
= arch_flags_type (gdbarch
, "builtin_type_i386_mxcsr", 4);
2160 append_flags_type_flag (type
, 0, "IE");
2161 append_flags_type_flag (type
, 1, "DE");
2162 append_flags_type_flag (type
, 2, "ZE");
2163 append_flags_type_flag (type
, 3, "OE");
2164 append_flags_type_flag (type
, 4, "UE");
2165 append_flags_type_flag (type
, 5, "PE");
2166 append_flags_type_flag (type
, 6, "DAZ");
2167 append_flags_type_flag (type
, 7, "IM");
2168 append_flags_type_flag (type
, 8, "DM");
2169 append_flags_type_flag (type
, 9, "ZM");
2170 append_flags_type_flag (type
, 10, "OM");
2171 append_flags_type_flag (type
, 11, "UM");
2172 append_flags_type_flag (type
, 12, "PM");
2173 append_flags_type_flag (type
, 15, "FZ");
2175 tdep
->i386_mxcsr_type
= type
;
2178 return tdep
->i386_mxcsr_type
;
2182 i387_ext_type (struct gdbarch
*gdbarch
)
2184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2186 if (!tdep
->i387_ext_type
)
2188 = arch_float_type (gdbarch
, -1, "builtin_type_i387_ext",
2189 floatformats_i387_ext
);
2191 return tdep
->i387_ext_type
;
2194 /* Construct vector type for MMX registers. */
2196 i386_mmx_type (struct gdbarch
*gdbarch
)
2198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2200 if (!tdep
->i386_mmx_type
)
2202 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2204 /* The type we're building is this: */
2206 union __gdb_builtin_type_vec64i
2209 int32_t v2_int32
[2];
2210 int16_t v4_int16
[4];
2217 t
= arch_composite_type (gdbarch
,
2218 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2220 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2221 append_composite_type_field (t
, "v2_int32",
2222 init_vector_type (bt
->builtin_int32
, 2));
2223 append_composite_type_field (t
, "v4_int16",
2224 init_vector_type (bt
->builtin_int16
, 4));
2225 append_composite_type_field (t
, "v8_int8",
2226 init_vector_type (bt
->builtin_int8
, 8));
2228 TYPE_VECTOR (t
) = 1;
2229 TYPE_NAME (t
) = "builtin_type_vec64i";
2230 tdep
->i386_mmx_type
= t
;
2233 return tdep
->i386_mmx_type
;
2237 i386_sse_type (struct gdbarch
*gdbarch
)
2239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2241 if (!tdep
->i386_sse_type
)
2243 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2245 /* The type we're building is this: */
2247 union __gdb_builtin_type_vec128i
2250 int64_t v2_int64
[2];
2251 int32_t v4_int32
[4];
2252 int16_t v8_int16
[8];
2253 int8_t v16_int8
[16];
2254 double v2_double
[2];
2261 t
= arch_composite_type (gdbarch
,
2262 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION
);
2263 append_composite_type_field (t
, "v4_float",
2264 init_vector_type (bt
->builtin_float
, 4));
2265 append_composite_type_field (t
, "v2_double",
2266 init_vector_type (bt
->builtin_double
, 2));
2267 append_composite_type_field (t
, "v16_int8",
2268 init_vector_type (bt
->builtin_int8
, 16));
2269 append_composite_type_field (t
, "v8_int16",
2270 init_vector_type (bt
->builtin_int16
, 8));
2271 append_composite_type_field (t
, "v4_int32",
2272 init_vector_type (bt
->builtin_int32
, 4));
2273 append_composite_type_field (t
, "v2_int64",
2274 init_vector_type (bt
->builtin_int64
, 2));
2275 append_composite_type_field (t
, "uint128", bt
->builtin_int128
);
2277 TYPE_VECTOR (t
) = 1;
2278 TYPE_NAME (t
) = "builtin_type_vec128i";
2279 tdep
->i386_sse_type
= t
;
2282 return tdep
->i386_sse_type
;
2285 /* Return the GDB type object for the "standard" data type of data in
2286 register REGNUM. Perhaps %esi and %edi should go here, but
2287 potentially they could be used for things other than address. */
2289 static struct type
*
2290 i386_register_type (struct gdbarch
*gdbarch
, int regnum
)
2292 if (regnum
== I386_EIP_REGNUM
)
2293 return builtin_type (gdbarch
)->builtin_func_ptr
;
2295 if (regnum
== I386_EFLAGS_REGNUM
)
2296 return i386_eflags_type (gdbarch
);
2298 if (regnum
== I386_EBP_REGNUM
|| regnum
== I386_ESP_REGNUM
)
2299 return builtin_type (gdbarch
)->builtin_data_ptr
;
2301 if (i386_fp_regnum_p (gdbarch
, regnum
))
2302 return i387_ext_type (gdbarch
);
2304 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2305 return i386_mmx_type (gdbarch
);
2307 if (i386_sse_regnum_p (gdbarch
, regnum
))
2308 return i386_sse_type (gdbarch
);
2310 if (regnum
== I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch
)))
2311 return i386_mxcsr_type (gdbarch
);
2313 return builtin_type (gdbarch
)->builtin_int
;
2316 /* Map a cooked register onto a raw register or memory. For the i386,
2317 the MMX registers need to be mapped onto floating point registers. */
2320 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2322 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2327 mmxreg
= regnum
- tdep
->mm0_regnum
;
2328 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2329 tos
= (fstat
>> 11) & 0x7;
2330 fpreg
= (mmxreg
+ tos
) % 8;
2332 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2336 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2337 int regnum
, gdb_byte
*buf
)
2339 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2341 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2342 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2344 /* Extract (always little endian). */
2345 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2346 memcpy (buf
, mmx_buf
, register_size (gdbarch
, regnum
));
2349 regcache_raw_read (regcache
, regnum
, buf
);
2353 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2354 int regnum
, const gdb_byte
*buf
)
2356 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2358 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2359 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2362 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2363 /* ... Modify ... (always little endian). */
2364 memcpy (mmx_buf
, buf
, register_size (gdbarch
, regnum
));
2366 regcache_raw_write (regcache
, fpnum
, mmx_buf
);
2369 regcache_raw_write (regcache
, regnum
, buf
);
2373 /* Return the register number of the register allocated by GCC after
2374 REGNUM, or -1 if there is no such register. */
2377 i386_next_regnum (int regnum
)
2379 /* GCC allocates the registers in the order:
2381 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2383 Since storing a variable in %esp doesn't make any sense we return
2384 -1 for %ebp and for %esp itself. */
2385 static int next_regnum
[] =
2387 I386_EDX_REGNUM
, /* Slot for %eax. */
2388 I386_EBX_REGNUM
, /* Slot for %ecx. */
2389 I386_ECX_REGNUM
, /* Slot for %edx. */
2390 I386_ESI_REGNUM
, /* Slot for %ebx. */
2391 -1, -1, /* Slots for %esp and %ebp. */
2392 I386_EDI_REGNUM
, /* Slot for %esi. */
2393 I386_EBP_REGNUM
/* Slot for %edi. */
2396 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2397 return next_regnum
[regnum
];
2402 /* Return nonzero if a value of type TYPE stored in register REGNUM
2403 needs any special handling. */
2406 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2408 int len
= TYPE_LENGTH (type
);
2410 /* Values may be spread across multiple registers. Most debugging
2411 formats aren't expressive enough to specify the locations, so
2412 some heuristics is involved. Right now we only handle types that
2413 have a length that is a multiple of the word size, since GCC
2414 doesn't seem to put any other types into registers. */
2415 if (len
> 4 && len
% 4 == 0)
2417 int last_regnum
= regnum
;
2421 last_regnum
= i386_next_regnum (last_regnum
);
2425 if (last_regnum
!= -1)
2429 return i387_convert_register_p (gdbarch
, regnum
, type
);
2432 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2433 return its contents in TO. */
2436 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2437 struct type
*type
, gdb_byte
*to
)
2439 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2440 int len
= TYPE_LENGTH (type
);
2442 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2443 available in FRAME (i.e. if it wasn't saved)? */
2445 if (i386_fp_regnum_p (gdbarch
, regnum
))
2447 i387_register_to_value (frame
, regnum
, type
, to
);
2451 /* Read a value spread across multiple registers. */
2453 gdb_assert (len
> 4 && len
% 4 == 0);
2457 gdb_assert (regnum
!= -1);
2458 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2460 get_frame_register (frame
, regnum
, to
);
2461 regnum
= i386_next_regnum (regnum
);
2467 /* Write the contents FROM of a value of type TYPE into register
2468 REGNUM in frame FRAME. */
2471 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2472 struct type
*type
, const gdb_byte
*from
)
2474 int len
= TYPE_LENGTH (type
);
2476 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2478 i387_value_to_register (frame
, regnum
, type
, from
);
2482 /* Write a value spread across multiple registers. */
2484 gdb_assert (len
> 4 && len
% 4 == 0);
2488 gdb_assert (regnum
!= -1);
2489 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2491 put_frame_register (frame
, regnum
, from
);
2492 regnum
= i386_next_regnum (regnum
);
2498 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2499 in the general-purpose register set REGSET to register cache
2500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2503 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2504 int regnum
, const void *gregs
, size_t len
)
2506 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2507 const gdb_byte
*regs
= gregs
;
2510 gdb_assert (len
== tdep
->sizeof_gregset
);
2512 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2514 if ((regnum
== i
|| regnum
== -1)
2515 && tdep
->gregset_reg_offset
[i
] != -1)
2516 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2520 /* Collect register REGNUM from the register cache REGCACHE and store
2521 it in the buffer specified by GREGS and LEN as described by the
2522 general-purpose register set REGSET. If REGNUM is -1, do this for
2523 all registers in REGSET. */
2526 i386_collect_gregset (const struct regset
*regset
,
2527 const struct regcache
*regcache
,
2528 int regnum
, void *gregs
, size_t len
)
2530 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2531 gdb_byte
*regs
= gregs
;
2534 gdb_assert (len
== tdep
->sizeof_gregset
);
2536 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2538 if ((regnum
== i
|| regnum
== -1)
2539 && tdep
->gregset_reg_offset
[i
] != -1)
2540 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2544 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2545 in the floating-point register set REGSET to register cache
2546 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2549 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2550 int regnum
, const void *fpregs
, size_t len
)
2552 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2554 if (len
== I387_SIZEOF_FXSAVE
)
2556 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2560 gdb_assert (len
== tdep
->sizeof_fpregset
);
2561 i387_supply_fsave (regcache
, regnum
, fpregs
);
2564 /* Collect register REGNUM from the register cache REGCACHE and store
2565 it in the buffer specified by FPREGS and LEN as described by the
2566 floating-point register set REGSET. If REGNUM is -1, do this for
2567 all registers in REGSET. */
2570 i386_collect_fpregset (const struct regset
*regset
,
2571 const struct regcache
*regcache
,
2572 int regnum
, void *fpregs
, size_t len
)
2574 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2576 if (len
== I387_SIZEOF_FXSAVE
)
2578 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2582 gdb_assert (len
== tdep
->sizeof_fpregset
);
2583 i387_collect_fsave (regcache
, regnum
, fpregs
);
2586 /* Return the appropriate register set for the core section identified
2587 by SECT_NAME and SECT_SIZE. */
2589 const struct regset
*
2590 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2591 const char *sect_name
, size_t sect_size
)
2593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2595 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2597 if (tdep
->gregset
== NULL
)
2598 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2599 i386_collect_gregset
);
2600 return tdep
->gregset
;
2603 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2604 || (strcmp (sect_name
, ".reg-xfp") == 0
2605 && sect_size
== I387_SIZEOF_FXSAVE
))
2607 if (tdep
->fpregset
== NULL
)
2608 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2609 i386_collect_fpregset
);
2610 return tdep
->fpregset
;
2617 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2620 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2621 CORE_ADDR pc
, char *name
)
2623 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2624 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2627 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2629 unsigned long indirect
=
2630 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2631 struct minimal_symbol
*indsym
=
2632 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2633 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2637 if (strncmp (symname
, "__imp_", 6) == 0
2638 || strncmp (symname
, "_imp_", 5) == 0)
2640 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2643 return 0; /* Not a trampoline. */
2647 /* Return whether the THIS_FRAME corresponds to a sigtramp
2651 i386_sigtramp_p (struct frame_info
*this_frame
)
2653 CORE_ADDR pc
= get_frame_pc (this_frame
);
2656 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2657 return (name
&& strcmp ("_sigtramp", name
) == 0);
2661 /* We have two flavours of disassembly. The machinery on this page
2662 deals with switching between those. */
2665 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2667 gdb_assert (disassembly_flavor
== att_flavor
2668 || disassembly_flavor
== intel_flavor
);
2670 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2671 constified, cast to prevent a compiler warning. */
2672 info
->disassembler_options
= (char *) disassembly_flavor
;
2674 return print_insn_i386 (pc
, info
);
2678 /* There are a few i386 architecture variants that differ only
2679 slightly from the generic i386 target. For now, we don't give them
2680 their own source file, but include them here. As a consequence,
2681 they'll always be included. */
2683 /* System V Release 4 (SVR4). */
2685 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2689 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2691 CORE_ADDR pc
= get_frame_pc (this_frame
);
2694 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2695 currently unknown. */
2696 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2697 return (name
&& (strcmp ("_sigreturn", name
) == 0
2698 || strcmp ("_sigacthandler", name
) == 0
2699 || strcmp ("sigvechandler", name
) == 0));
2702 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2703 address of the associated sigcontext (ucontext) structure. */
2706 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2708 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2709 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2713 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2714 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2716 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2723 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2725 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2726 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2729 /* System V Release 4 (SVR4). */
2732 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2736 /* System V Release 4 uses ELF. */
2737 i386_elf_init_abi (info
, gdbarch
);
2739 /* System V Release 4 has shared libraries. */
2740 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2742 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2743 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2744 tdep
->sc_pc_offset
= 36 + 14 * 4;
2745 tdep
->sc_sp_offset
= 36 + 17 * 4;
2747 tdep
->jb_pc_offset
= 20;
2753 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2757 /* DJGPP doesn't have any special frames for signal handlers. */
2758 tdep
->sigtramp_p
= NULL
;
2760 tdep
->jb_pc_offset
= 36;
2762 /* DJGPP does not support the SSE registers. */
2763 tdep
->num_xmm_regs
= 0;
2764 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I386_NUM_FREGS
);
2766 /* Native compiler is GCC, which uses the SVR4 register numbering
2767 even in COFF and STABS. See the comment in i386_gdbarch_init,
2768 before the calls to set_gdbarch_stab_reg_to_regnum and
2769 set_gdbarch_sdb_reg_to_regnum. */
2770 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2771 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2775 /* i386 register groups. In addition to the normal groups, add "mmx"
2778 static struct reggroup
*i386_sse_reggroup
;
2779 static struct reggroup
*i386_mmx_reggroup
;
2782 i386_init_reggroups (void)
2784 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2785 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2789 i386_add_reggroups (struct gdbarch
*gdbarch
)
2791 reggroup_add (gdbarch
, i386_sse_reggroup
);
2792 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2793 reggroup_add (gdbarch
, general_reggroup
);
2794 reggroup_add (gdbarch
, float_reggroup
);
2795 reggroup_add (gdbarch
, all_reggroup
);
2796 reggroup_add (gdbarch
, save_reggroup
);
2797 reggroup_add (gdbarch
, restore_reggroup
);
2798 reggroup_add (gdbarch
, vector_reggroup
);
2799 reggroup_add (gdbarch
, system_reggroup
);
2803 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2804 struct reggroup
*group
)
2806 int sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2807 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2808 int fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2809 || i386_fpc_regnum_p (gdbarch
, regnum
));
2810 int mmx_regnum_p
= (i386_mmx_regnum_p (gdbarch
, regnum
));
2812 if (group
== i386_mmx_reggroup
)
2813 return mmx_regnum_p
;
2814 if (group
== i386_sse_reggroup
)
2815 return sse_regnum_p
;
2816 if (group
== vector_reggroup
)
2817 return (mmx_regnum_p
|| sse_regnum_p
);
2818 if (group
== float_reggroup
)
2820 if (group
== general_reggroup
)
2821 return (!fp_regnum_p
&& !mmx_regnum_p
&& !sse_regnum_p
);
2823 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2827 /* Get the ARGIth function argument for the current function. */
2830 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2833 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2834 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2835 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2836 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2840 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2842 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2844 /* On i386, breakpoint is exactly 1 byte long, so we just
2845 adjust the PC in the regcache. */
2847 regcache_write_pc (regcache
, current_pc
);
2851 #define PREFIX_REPZ 0x01
2852 #define PREFIX_REPNZ 0x02
2853 #define PREFIX_LOCK 0x04
2854 #define PREFIX_DATA 0x08
2855 #define PREFIX_ADDR 0x10
2866 /* i386 arith/logic operations */
2879 struct i386_record_s
2881 struct gdbarch
*gdbarch
;
2882 struct regcache
*regcache
;
2883 CORE_ADDR orig_addr
;
2889 uint8_t mod
, reg
, rm
;
2898 /* Parse "modrm" part in current memory address that irp->addr point to
2899 Return -1 if something wrong. */
2902 i386_record_modrm (struct i386_record_s
*irp
)
2904 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2906 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2909 printf_unfiltered (_("Process record: error reading memory at "
2910 "addr %s len = 1.\n"),
2911 paddress (gdbarch
, irp
->addr
));
2915 irp
->mod
= (irp
->modrm
>> 6) & 3;
2916 irp
->reg
= (irp
->modrm
>> 3) & 7;
2917 irp
->rm
= irp
->modrm
& 7;
2922 /* Get the memory address that current instruction write to and set it to
2923 the argument "addr".
2924 Return -1 if something wrong. */
2927 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2929 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2933 ULONGEST tmpulongest
;
2942 uint8_t base
= irp
->rm
;
2947 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2950 printf_unfiltered (_("Process record: error reading memory "
2951 "at addr %s len = 1.\n"),
2952 paddress (gdbarch
, irp
->addr
));
2956 scale
= (tmpu8
>> 6) & 3;
2957 index
= ((tmpu8
>> 3) & 7) | irp
->rex_x
;
2965 if ((base
& 7) == 5)
2968 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
2971 printf_unfiltered (_("Process record: error reading "
2972 "memory at addr %s len = 4.\n"),
2973 paddress (gdbarch
, irp
->addr
));
2978 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
2979 *addr
+= irp
->addr
+ irp
->rip_offset
;
2987 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2990 printf_unfiltered (_("Process record: error reading memory "
2991 "at addr %s len = 1.\n"),
2992 paddress (gdbarch
, irp
->addr
));
2996 *addr
= (int8_t) tmpu8
;
2999 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
3002 printf_unfiltered (_("Process record: error reading memory "
3003 "at addr %s len = 4.\n"),
3004 paddress (gdbarch
, irp
->addr
));
3015 if (base
== 4 && irp
->popl_esp_hack
)
3016 *addr
+= irp
->popl_esp_hack
;
3017 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3020 if (irp
->aflag
== 2)
3022 *addr
+= tmpulongest
;
3025 *addr
= (uint32_t) (tmpulongest
+ *addr
);
3027 if (havesib
&& (index
!= 4 || scale
!= 0))
3029 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3031 if (irp
->aflag
== 2)
3032 *addr
+= tmpulongest
<< scale
;
3034 *addr
= (uint32_t) (*addr
+ (tmpulongest
<< scale
));
3045 if (target_read_memory
3046 (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3049 printf_unfiltered (_("Process record: error reading "
3050 "memory at addr %s len = 2.\n"),
3051 paddress (gdbarch
, irp
->addr
));
3065 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
3068 printf_unfiltered (_("Process record: error reading memory "
3069 "at addr %s len = 1.\n"),
3070 paddress (gdbarch
, irp
->addr
));
3074 *addr
= (int8_t) tmpu8
;
3077 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3080 printf_unfiltered (_("Process record: error reading memory "
3081 "at addr %s len = 2.\n"),
3082 paddress (gdbarch
, irp
->addr
));
3093 regcache_raw_read_unsigned (irp
->regcache
,
3094 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3096 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3097 regcache_raw_read_unsigned (irp
->regcache
,
3098 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3100 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3103 regcache_raw_read_unsigned (irp
->regcache
,
3104 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3106 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3107 regcache_raw_read_unsigned (irp
->regcache
,
3108 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3110 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3113 regcache_raw_read_unsigned (irp
->regcache
,
3114 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3116 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3117 regcache_raw_read_unsigned (irp
->regcache
,
3118 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3120 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3123 regcache_raw_read_unsigned (irp
->regcache
,
3124 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3126 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3127 regcache_raw_read_unsigned (irp
->regcache
,
3128 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3130 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3133 regcache_raw_read_unsigned (irp
->regcache
,
3134 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3136 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3139 regcache_raw_read_unsigned (irp
->regcache
,
3140 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3142 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3145 regcache_raw_read_unsigned (irp
->regcache
,
3146 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3148 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3151 regcache_raw_read_unsigned (irp
->regcache
,
3152 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3154 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3164 /* Record the value of the memory that willbe changed in current instruction
3165 to "record_arch_list".
3166 Return -1 if something wrong. */
3169 i386_record_lea_modrm (struct i386_record_s
*irp
)
3171 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3174 if (irp
->override
>= 0)
3176 warning (_("Process record ignores the memory change "
3177 "of instruction at address %s because it "
3178 "can't get the value of the segment register."),
3179 paddress (gdbarch
, irp
->orig_addr
));
3183 if (i386_record_lea_modrm_addr (irp
, &addr
))
3186 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3192 /* Record the push operation to "record_arch_list".
3193 Return -1 if something wrong. */
3196 i386_record_push (struct i386_record_s
*irp
, int size
)
3198 ULONGEST tmpulongest
;
3200 if (record_arch_list_add_reg (irp
->regcache
,
3201 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3203 regcache_raw_read_unsigned (irp
->regcache
,
3204 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3206 if (record_arch_list_add_mem ((CORE_ADDR
) tmpulongest
- size
, size
))
3213 /* Defines contents to record. */
3214 #define I386_SAVE_FPU_REGS 0xfffd
3215 #define I386_SAVE_FPU_ENV 0xfffe
3216 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3218 /* Record the value of floating point registers which will be changed by the
3219 current instruction to "record_arch_list". Return -1 if something is wrong.
3222 static int i386_record_floats (struct gdbarch
*gdbarch
,
3223 struct i386_record_s
*ir
,
3226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3229 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3230 happen. Currently we store st0-st7 registers, but we need not store all
3231 registers all the time, in future we use ftag register and record only
3232 those who are not marked as an empty. */
3234 if (I386_SAVE_FPU_REGS
== iregnum
)
3236 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3238 if (record_arch_list_add_reg (ir
->regcache
, i
))
3242 else if (I386_SAVE_FPU_ENV
== iregnum
)
3244 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3246 if (record_arch_list_add_reg (ir
->regcache
, i
))
3250 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3252 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3254 if (record_arch_list_add_reg (ir
->regcache
, i
))
3258 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3259 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3261 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3266 /* Parameter error. */
3269 if(I386_SAVE_FPU_ENV
!= iregnum
)
3271 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3273 if (record_arch_list_add_reg (ir
->regcache
, i
))
3280 /* Parse the current instruction and record the values of the registers and
3281 memory that will be changed in current instruction to "record_arch_list".
3282 Return -1 if something wrong. */
3284 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3285 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3288 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3295 ULONGEST tmpulongest
;
3297 struct i386_record_s ir
;
3298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3303 memset (&ir
, 0, sizeof (struct i386_record_s
));
3304 ir
.regcache
= regcache
;
3306 ir
.orig_addr
= addr
;
3310 ir
.popl_esp_hack
= 0;
3311 ir
.regmap
= gdbarch_tdep (gdbarch
)->record_regmap
;
3312 ir
.gdbarch
= gdbarch
;
3314 if (record_debug
> 1)
3315 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3317 paddress (gdbarch
, ir
.addr
));
3322 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3325 printf_unfiltered (_("Process record: error reading memory at "
3326 "addr %s len = 1.\n"),
3327 paddress (gdbarch
, ir
.addr
));
3331 switch (tmpu8
) /* Instruction prefixes */
3333 case REPE_PREFIX_OPCODE
:
3334 prefixes
|= PREFIX_REPZ
;
3336 case REPNE_PREFIX_OPCODE
:
3337 prefixes
|= PREFIX_REPNZ
;
3339 case LOCK_PREFIX_OPCODE
:
3340 prefixes
|= PREFIX_LOCK
;
3342 case CS_PREFIX_OPCODE
:
3343 ir
.override
= X86_RECORD_CS_REGNUM
;
3345 case SS_PREFIX_OPCODE
:
3346 ir
.override
= X86_RECORD_SS_REGNUM
;
3348 case DS_PREFIX_OPCODE
:
3349 ir
.override
= X86_RECORD_DS_REGNUM
;
3351 case ES_PREFIX_OPCODE
:
3352 ir
.override
= X86_RECORD_ES_REGNUM
;
3354 case FS_PREFIX_OPCODE
:
3355 ir
.override
= X86_RECORD_FS_REGNUM
;
3357 case GS_PREFIX_OPCODE
:
3358 ir
.override
= X86_RECORD_GS_REGNUM
;
3360 case DATA_PREFIX_OPCODE
:
3361 prefixes
|= PREFIX_DATA
;
3363 case ADDR_PREFIX_OPCODE
:
3364 prefixes
|= PREFIX_ADDR
;
3366 case 0x40: /* i386 inc %eax */
3367 case 0x41: /* i386 inc %ecx */
3368 case 0x42: /* i386 inc %edx */
3369 case 0x43: /* i386 inc %ebx */
3370 case 0x44: /* i386 inc %esp */
3371 case 0x45: /* i386 inc %ebp */
3372 case 0x46: /* i386 inc %esi */
3373 case 0x47: /* i386 inc %edi */
3374 case 0x48: /* i386 dec %eax */
3375 case 0x49: /* i386 dec %ecx */
3376 case 0x4a: /* i386 dec %edx */
3377 case 0x4b: /* i386 dec %ebx */
3378 case 0x4c: /* i386 dec %esp */
3379 case 0x4d: /* i386 dec %ebp */
3380 case 0x4e: /* i386 dec %esi */
3381 case 0x4f: /* i386 dec %edi */
3382 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3386 rex_w
= (tmpu8
>> 3) & 1;
3387 rex_r
= (tmpu8
& 0x4) << 1;
3388 ir
.rex_x
= (tmpu8
& 0x2) << 2;
3389 ir
.rex_b
= (tmpu8
& 0x1) << 3;
3391 else /* 32 bit target */
3400 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3406 if (prefixes
& PREFIX_DATA
)
3409 if (prefixes
& PREFIX_ADDR
)
3411 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3414 /* now check op code */
3415 opcode
= (uint32_t) tmpu8
;
3420 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3423 printf_unfiltered (_("Process record: error reading memory at "
3424 "addr %s len = 1.\n"),
3425 paddress (gdbarch
, ir
.addr
));
3429 opcode
= (uint16_t) tmpu8
| 0x0f00;
3433 case 0x00: /* arith & logic */
3481 if (((opcode
>> 3) & 7) != OP_CMPL
)
3483 if ((opcode
& 1) == 0)
3486 ir
.ot
= ir
.dflag
+ OT_WORD
;
3488 switch ((opcode
>> 1) & 3)
3490 case 0: /* OP Ev, Gv */
3491 if (i386_record_modrm (&ir
))
3495 if (i386_record_lea_modrm (&ir
))
3501 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3503 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3506 case 1: /* OP Gv, Ev */
3507 if (i386_record_modrm (&ir
))
3510 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3512 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3514 case 2: /* OP A, Iv */
3515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3519 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3522 case 0x80: /* GRP1 */
3526 if (i386_record_modrm (&ir
))
3529 if (ir
.reg
!= OP_CMPL
)
3531 if ((opcode
& 1) == 0)
3534 ir
.ot
= ir
.dflag
+ OT_WORD
;
3541 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3542 if (i386_record_lea_modrm (&ir
))
3546 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3548 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3551 case 0x40: /* inc */
3560 case 0x48: /* dec */
3569 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3573 case 0xf6: /* GRP3 */
3575 if ((opcode
& 1) == 0)
3578 ir
.ot
= ir
.dflag
+ OT_WORD
;
3579 if (i386_record_modrm (&ir
))
3582 if (ir
.mod
!= 3 && ir
.reg
== 0)
3583 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3588 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3594 if (i386_record_lea_modrm (&ir
))
3600 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3602 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3604 if (ir
.reg
== 3) /* neg */
3605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3612 if (ir
.ot
!= OT_BYTE
)
3613 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3614 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3618 opcode
= opcode
<< 8 | ir
.modrm
;
3624 case 0xfe: /* GRP4 */
3625 case 0xff: /* GRP5 */
3626 if (i386_record_modrm (&ir
))
3628 if (ir
.reg
>= 2 && opcode
== 0xfe)
3631 opcode
= opcode
<< 8 | ir
.modrm
;
3638 if ((opcode
& 1) == 0)
3641 ir
.ot
= ir
.dflag
+ OT_WORD
;
3644 if (i386_record_lea_modrm (&ir
))
3650 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3652 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3654 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3657 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3659 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3661 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3664 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3665 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3667 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3671 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3674 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3676 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3681 opcode
= opcode
<< 8 | ir
.modrm
;
3687 case 0x84: /* test */
3691 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3694 case 0x98: /* CWDE/CBW */
3695 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3698 case 0x99: /* CDQ/CWD */
3699 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3700 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3703 case 0x0faf: /* imul */
3706 ir
.ot
= ir
.dflag
+ OT_WORD
;
3707 if (i386_record_modrm (&ir
))
3710 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3711 else if (opcode
== 0x6b)
3714 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3716 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3720 case 0x0fc0: /* xadd */
3722 if ((opcode
& 1) == 0)
3725 ir
.ot
= ir
.dflag
+ OT_WORD
;
3726 if (i386_record_modrm (&ir
))
3731 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3733 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3734 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3736 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3740 if (i386_record_lea_modrm (&ir
))
3742 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3744 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3746 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3749 case 0x0fb0: /* cmpxchg */
3751 if ((opcode
& 1) == 0)
3754 ir
.ot
= ir
.dflag
+ OT_WORD
;
3755 if (i386_record_modrm (&ir
))
3760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3761 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3763 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3768 if (i386_record_lea_modrm (&ir
))
3771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3774 case 0x0fc7: /* cmpxchg8b */
3775 if (i386_record_modrm (&ir
))
3780 opcode
= opcode
<< 8 | ir
.modrm
;
3783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3785 if (i386_record_lea_modrm (&ir
))
3787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3790 case 0x50: /* push */
3800 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3802 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3806 case 0x06: /* push es */
3807 case 0x0e: /* push cs */
3808 case 0x16: /* push ss */
3809 case 0x1e: /* push ds */
3810 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3815 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3819 case 0x0fa0: /* push fs */
3820 case 0x0fa8: /* push gs */
3821 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3826 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3830 case 0x60: /* pusha */
3831 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3836 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3840 case 0x58: /* pop */
3848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3849 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3852 case 0x61: /* popa */
3853 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3858 for (tmpu8
= X86_RECORD_REAX_REGNUM
; tmpu8
<= X86_RECORD_REDI_REGNUM
;
3860 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
3863 case 0x8f: /* pop */
3864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3865 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3867 ir
.ot
= ir
.dflag
+ OT_WORD
;
3868 if (i386_record_modrm (&ir
))
3871 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3874 ir
.popl_esp_hack
= 1 << ir
.ot
;
3875 if (i386_record_lea_modrm (&ir
))
3878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3881 case 0xc8: /* enter */
3882 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3883 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3885 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3889 case 0xc9: /* leave */
3890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3891 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3894 case 0x07: /* pop es */
3895 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3901 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3902 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3905 case 0x17: /* pop ss */
3906 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3911 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3913 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3916 case 0x1f: /* pop ds */
3917 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3927 case 0x0fa1: /* pop fs */
3928 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3933 case 0x0fa9: /* pop gs */
3934 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3939 case 0x88: /* mov */
3943 if ((opcode
& 1) == 0)
3946 ir
.ot
= ir
.dflag
+ OT_WORD
;
3948 if (i386_record_modrm (&ir
))
3953 if (opcode
== 0xc6 || opcode
== 0xc7)
3954 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3955 if (i386_record_lea_modrm (&ir
))
3960 if (opcode
== 0xc6 || opcode
== 0xc7)
3962 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3964 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3968 case 0x8a: /* mov */
3970 if ((opcode
& 1) == 0)
3973 ir
.ot
= ir
.dflag
+ OT_WORD
;
3974 if (i386_record_modrm (&ir
))
3977 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3979 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3982 case 0x8c: /* mov seg */
3983 if (i386_record_modrm (&ir
))
3988 opcode
= opcode
<< 8 | ir
.modrm
;
3993 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3997 if (i386_record_lea_modrm (&ir
))
4002 case 0x8e: /* mov seg */
4003 if (i386_record_modrm (&ir
))
4008 tmpu8
= X86_RECORD_ES_REGNUM
;
4011 tmpu8
= X86_RECORD_SS_REGNUM
;
4014 tmpu8
= X86_RECORD_DS_REGNUM
;
4017 tmpu8
= X86_RECORD_FS_REGNUM
;
4020 tmpu8
= X86_RECORD_GS_REGNUM
;
4024 opcode
= opcode
<< 8 | ir
.modrm
;
4028 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
4029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4032 case 0x0fb6: /* movzbS */
4033 case 0x0fb7: /* movzwS */
4034 case 0x0fbe: /* movsbS */
4035 case 0x0fbf: /* movswS */
4036 if (i386_record_modrm (&ir
))
4038 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4041 case 0x8d: /* lea */
4042 if (i386_record_modrm (&ir
))
4047 opcode
= opcode
<< 8 | ir
.modrm
;
4052 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4054 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4057 case 0xa0: /* mov EAX */
4060 case 0xd7: /* xlat */
4061 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4064 case 0xa2: /* mov EAX */
4066 if (ir
.override
>= 0)
4068 warning (_("Process record ignores the memory change "
4069 "of instruction at address %s because "
4070 "it can't get the value of the segment "
4072 paddress (gdbarch
, ir
.orig_addr
));
4076 if ((opcode
& 1) == 0)
4079 ir
.ot
= ir
.dflag
+ OT_WORD
;
4082 if (target_read_memory (ir
.addr
, (gdb_byte
*) &addr
, 8))
4085 printf_unfiltered (_("Process record: error reading "
4086 "memory at addr 0x%s len = 8.\n"),
4087 paddress (gdbarch
, ir
.addr
));
4094 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu32
, 4))
4097 printf_unfiltered (_("Process record: error reading "
4098 "memory at addr 0x%s len = 4.\n"),
4099 paddress (gdbarch
, ir
.addr
));
4107 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu16
, 2))
4110 printf_unfiltered (_("Process record: error reading "
4111 "memory at addr 0x%s len = 2.\n"),
4112 paddress (gdbarch
, ir
.addr
));
4118 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4123 case 0xb0: /* mov R, Ib */
4131 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4132 ? ((opcode
& 0x7) | ir
.rex_b
)
4133 : ((opcode
& 0x7) & 0x3));
4136 case 0xb8: /* mov R, Iv */
4144 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4147 case 0x91: /* xchg R, EAX */
4154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4155 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4158 case 0x86: /* xchg Ev, Gv */
4160 if ((opcode
& 1) == 0)
4163 ir
.ot
= ir
.dflag
+ OT_WORD
;
4164 if (i386_record_modrm (&ir
))
4169 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4171 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4175 if (i386_record_lea_modrm (&ir
))
4179 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4181 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4184 case 0xc4: /* les Gv */
4185 case 0xc5: /* lds Gv */
4186 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4191 case 0x0fb2: /* lss Gv */
4192 case 0x0fb4: /* lfs Gv */
4193 case 0x0fb5: /* lgs Gv */
4194 if (i386_record_modrm (&ir
))
4202 opcode
= opcode
<< 8 | ir
.modrm
;
4207 case 0xc4: /* les Gv */
4208 tmpu8
= X86_RECORD_ES_REGNUM
;
4210 case 0xc5: /* lds Gv */
4211 tmpu8
= X86_RECORD_DS_REGNUM
;
4213 case 0x0fb2: /* lss Gv */
4214 tmpu8
= X86_RECORD_SS_REGNUM
;
4216 case 0x0fb4: /* lfs Gv */
4217 tmpu8
= X86_RECORD_FS_REGNUM
;
4219 case 0x0fb5: /* lgs Gv */
4220 tmpu8
= X86_RECORD_GS_REGNUM
;
4223 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
4224 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4225 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4228 case 0xc0: /* shifts */
4234 if ((opcode
& 1) == 0)
4237 ir
.ot
= ir
.dflag
+ OT_WORD
;
4238 if (i386_record_modrm (&ir
))
4240 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4242 if (i386_record_lea_modrm (&ir
))
4248 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4250 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4252 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4259 if (i386_record_modrm (&ir
))
4263 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4268 if (i386_record_lea_modrm (&ir
))
4273 case 0xd8: /* Floats. */
4281 if (i386_record_modrm (&ir
))
4283 ir
.reg
|= ((opcode
& 7) << 3);
4289 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
4297 /* For fcom, ficom nothing to do. */
4303 /* For fcomp, ficomp pop FPU stack, store all. */
4304 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4331 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4332 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4333 of code, always affects st(0) register. */
4334 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4358 /* Handling fld, fild. */
4359 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4363 switch (ir
.reg
>> 4)
4366 if (record_arch_list_add_mem (tmpu64
, 4))
4370 if (record_arch_list_add_mem (tmpu64
, 8))
4376 if (record_arch_list_add_mem (tmpu64
, 2))
4382 switch (ir
.reg
>> 4)
4385 if (record_arch_list_add_mem (tmpu64
, 4))
4387 if (3 == (ir
.reg
& 7))
4389 /* For fstp m32fp. */
4390 if (i386_record_floats (gdbarch
, &ir
,
4391 I386_SAVE_FPU_REGS
))
4396 if (record_arch_list_add_mem (tmpu64
, 4))
4398 if ((3 == (ir
.reg
& 7))
4399 || (5 == (ir
.reg
& 7))
4400 || (7 == (ir
.reg
& 7)))
4402 /* For fstp insn. */
4403 if (i386_record_floats (gdbarch
, &ir
,
4404 I386_SAVE_FPU_REGS
))
4409 if (record_arch_list_add_mem (tmpu64
, 8))
4411 if (3 == (ir
.reg
& 7))
4413 /* For fstp m64fp. */
4414 if (i386_record_floats (gdbarch
, &ir
,
4415 I386_SAVE_FPU_REGS
))
4420 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4422 /* For fistp, fbld, fild, fbstp. */
4423 if (i386_record_floats (gdbarch
, &ir
,
4424 I386_SAVE_FPU_REGS
))
4429 if (record_arch_list_add_mem (tmpu64
, 2))
4438 if (i386_record_floats (gdbarch
, &ir
,
4439 I386_SAVE_FPU_ENV_REG_STACK
))
4444 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4449 if (i386_record_floats (gdbarch
, &ir
,
4450 I386_SAVE_FPU_ENV_REG_STACK
))
4456 if (record_arch_list_add_mem (tmpu64
, 28))
4461 if (record_arch_list_add_mem (tmpu64
, 14))
4467 if (record_arch_list_add_mem (tmpu64
, 2))
4469 /* Insn fstp, fbstp. */
4470 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4475 if (record_arch_list_add_mem (tmpu64
, 10))
4481 if (record_arch_list_add_mem (tmpu64
, 28))
4487 if (record_arch_list_add_mem (tmpu64
, 14))
4491 if (record_arch_list_add_mem (tmpu64
, 80))
4494 if (i386_record_floats (gdbarch
, &ir
,
4495 I386_SAVE_FPU_ENV_REG_STACK
))
4499 if (record_arch_list_add_mem (tmpu64
, 8))
4502 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4507 opcode
= opcode
<< 8 | ir
.modrm
;
4512 /* Opcode is an extension of modR/M byte. */
4518 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4522 if (0x0c == (ir
.modrm
>> 4))
4524 if ((ir
.modrm
& 0x0f) <= 7)
4526 if (i386_record_floats (gdbarch
, &ir
,
4527 I386_SAVE_FPU_REGS
))
4532 if (i386_record_floats (gdbarch
, &ir
,
4533 I387_ST0_REGNUM (tdep
)))
4535 /* If only st(0) is changing, then we have already
4537 if ((ir
.modrm
& 0x0f) - 0x08)
4539 if (i386_record_floats (gdbarch
, &ir
,
4540 I387_ST0_REGNUM (tdep
) +
4541 ((ir
.modrm
& 0x0f) - 0x08)))
4559 if (i386_record_floats (gdbarch
, &ir
,
4560 I387_ST0_REGNUM (tdep
)))
4578 if (i386_record_floats (gdbarch
, &ir
,
4579 I386_SAVE_FPU_REGS
))
4583 if (i386_record_floats (gdbarch
, &ir
,
4584 I387_ST0_REGNUM (tdep
)))
4586 if (i386_record_floats (gdbarch
, &ir
,
4587 I387_ST0_REGNUM (tdep
) + 1))
4594 if (0xe9 == ir
.modrm
)
4596 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4599 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4601 if (i386_record_floats (gdbarch
, &ir
,
4602 I387_ST0_REGNUM (tdep
)))
4604 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4606 if (i386_record_floats (gdbarch
, &ir
,
4607 I387_ST0_REGNUM (tdep
) +
4611 else if ((ir
.modrm
& 0x0f) - 0x08)
4613 if (i386_record_floats (gdbarch
, &ir
,
4614 I387_ST0_REGNUM (tdep
) +
4615 ((ir
.modrm
& 0x0f) - 0x08)))
4621 if (0xe3 == ir
.modrm
)
4623 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4626 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4628 if (i386_record_floats (gdbarch
, &ir
,
4629 I387_ST0_REGNUM (tdep
)))
4631 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4633 if (i386_record_floats (gdbarch
, &ir
,
4634 I387_ST0_REGNUM (tdep
) +
4638 else if ((ir
.modrm
& 0x0f) - 0x08)
4640 if (i386_record_floats (gdbarch
, &ir
,
4641 I387_ST0_REGNUM (tdep
) +
4642 ((ir
.modrm
& 0x0f) - 0x08)))
4648 if ((0x0c == ir
.modrm
>> 4)
4649 || (0x0d == ir
.modrm
>> 4)
4650 || (0x0f == ir
.modrm
>> 4))
4652 if ((ir
.modrm
& 0x0f) <= 7)
4654 if (i386_record_floats (gdbarch
, &ir
,
4655 I387_ST0_REGNUM (tdep
) +
4661 if (i386_record_floats (gdbarch
, &ir
,
4662 I387_ST0_REGNUM (tdep
) +
4663 ((ir
.modrm
& 0x0f) - 0x08)))
4669 if (0x0c == ir
.modrm
>> 4)
4671 if (i386_record_floats (gdbarch
, &ir
,
4672 I387_FTAG_REGNUM (tdep
)))
4675 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4677 if ((ir
.modrm
& 0x0f) <= 7)
4679 if (i386_record_floats (gdbarch
, &ir
,
4680 I387_ST0_REGNUM (tdep
) +
4686 if (i386_record_floats (gdbarch
, &ir
,
4687 I386_SAVE_FPU_REGS
))
4693 if ((0x0c == ir
.modrm
>> 4)
4694 || (0x0e == ir
.modrm
>> 4)
4695 || (0x0f == ir
.modrm
>> 4)
4696 || (0xd9 == ir
.modrm
))
4698 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4703 if (0xe0 == ir
.modrm
)
4705 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4708 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4710 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4718 case 0xa4: /* movsS */
4720 case 0xaa: /* stosS */
4722 case 0x6c: /* insS */
4724 regcache_raw_read_unsigned (ir
.regcache
,
4725 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4731 if ((opcode
& 1) == 0)
4734 ir
.ot
= ir
.dflag
+ OT_WORD
;
4735 regcache_raw_read_unsigned (ir
.regcache
,
4736 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4739 regcache_raw_read_unsigned (ir
.regcache
,
4740 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4742 regcache_raw_read_unsigned (ir
.regcache
,
4743 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4745 if (ir
.aflag
&& (es
!= ds
))
4747 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4748 warning (_("Process record ignores the memory "
4749 "change of instruction at address %s "
4750 "because it can't get the value of the "
4751 "ES segment register."),
4752 paddress (gdbarch
, ir
.orig_addr
));
4756 if (record_arch_list_add_mem (tmpulongest
, 1 << ir
.ot
))
4760 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4762 if (opcode
== 0xa4 || opcode
== 0xa5)
4763 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4764 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4765 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4769 case 0xa6: /* cmpsS */
4771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4772 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4773 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4774 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4775 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4778 case 0xac: /* lodsS */
4780 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4782 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4787 case 0xae: /* scasS */
4789 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4790 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4791 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4795 case 0x6e: /* outsS */
4797 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4798 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4803 case 0xe4: /* port I/O */
4807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4818 case 0xc2: /* ret im */
4819 case 0xc3: /* ret */
4820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4824 case 0xca: /* lret im */
4825 case 0xcb: /* lret */
4826 case 0xcf: /* iret */
4827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4828 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4832 case 0xe8: /* call im */
4833 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4835 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4839 case 0x9a: /* lcall im */
4840 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4845 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4846 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4850 case 0xe9: /* jmp im */
4851 case 0xea: /* ljmp im */
4852 case 0xeb: /* jmp Jb */
4853 case 0x70: /* jcc Jb */
4869 case 0x0f80: /* jcc Jv */
4887 case 0x0f90: /* setcc Gv */
4903 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4905 if (i386_record_modrm (&ir
))
4908 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4912 if (i386_record_lea_modrm (&ir
))
4917 case 0x0f40: /* cmov Gv, Ev */
4933 if (i386_record_modrm (&ir
))
4936 if (ir
.dflag
== OT_BYTE
)
4938 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4942 case 0x9c: /* pushf */
4943 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4944 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4946 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4950 case 0x9d: /* popf */
4951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4955 case 0x9e: /* sahf */
4956 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4961 case 0xf5: /* cmc */
4962 case 0xf8: /* clc */
4963 case 0xf9: /* stc */
4964 case 0xfc: /* cld */
4965 case 0xfd: /* std */
4966 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4969 case 0x9f: /* lahf */
4970 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4976 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4979 /* bit operations */
4980 case 0x0fba: /* bt/bts/btr/btc Gv, im */
4981 ir
.ot
= ir
.dflag
+ OT_WORD
;
4982 if (i386_record_modrm (&ir
))
4987 opcode
= opcode
<< 8 | ir
.modrm
;
4993 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4996 if (i386_record_lea_modrm (&ir
))
5000 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5003 case 0x0fa3: /* bt Gv, Ev */
5004 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5007 case 0x0fab: /* bts */
5008 case 0x0fb3: /* btr */
5009 case 0x0fbb: /* btc */
5010 ir
.ot
= ir
.dflag
+ OT_WORD
;
5011 if (i386_record_modrm (&ir
))
5014 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5018 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5020 regcache_raw_read_unsigned (ir
.regcache
,
5021 ir
.regmap
[ir
.reg
| rex_r
],
5026 tmpu64
+= ((int16_t) tmpulongest
>> 4) << 4;
5029 tmpu64
+= ((int32_t) tmpulongest
>> 5) << 5;
5032 tmpu64
+= ((int64_t) tmpulongest
>> 6) << 6;
5035 if (record_arch_list_add_mem (tmpu64
, 1 << ir
.ot
))
5037 if (i386_record_lea_modrm (&ir
))
5040 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5043 case 0x0fbc: /* bsf */
5044 case 0x0fbd: /* bsr */
5045 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5046 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5050 case 0x27: /* daa */
5051 case 0x2f: /* das */
5052 case 0x37: /* aaa */
5053 case 0x3f: /* aas */
5054 case 0xd4: /* aam */
5055 case 0xd5: /* aad */
5056 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5061 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5062 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5066 case 0x90: /* nop */
5067 if (prefixes
& PREFIX_LOCK
)
5074 case 0x9b: /* fwait */
5075 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
5078 printf_unfiltered (_("Process record: error reading memory at "
5079 "addr 0x%s len = 1.\n"),
5080 paddress (gdbarch
, ir
.addr
));
5083 opcode
= (uint32_t) tmpu8
;
5089 case 0xcc: /* int3 */
5090 printf_unfiltered (_("Process record doesn't support instruction "
5097 case 0xcd: /* int */
5100 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
5103 printf_unfiltered (_("Process record: error reading memory "
5104 "at addr %s len = 1.\n"),
5105 paddress (gdbarch
, ir
.addr
));
5110 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
5112 printf_unfiltered (_("Process record doesn't support "
5113 "instruction int 0x%02x.\n"),
5118 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
5125 case 0xce: /* into */
5126 printf_unfiltered (_("Process record doesn't support "
5127 "instruction into.\n"));
5132 case 0xfa: /* cli */
5133 case 0xfb: /* sti */
5136 case 0x62: /* bound */
5137 printf_unfiltered (_("Process record doesn't support "
5138 "instruction bound.\n"));
5143 case 0x0fc8: /* bswap reg */
5151 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5154 case 0xd6: /* salc */
5155 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5164 case 0xe0: /* loopnz */
5165 case 0xe1: /* loopz */
5166 case 0xe2: /* loop */
5167 case 0xe3: /* jecxz */
5168 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5172 case 0x0f30: /* wrmsr */
5173 printf_unfiltered (_("Process record doesn't support "
5174 "instruction wrmsr.\n"));
5179 case 0x0f32: /* rdmsr */
5180 printf_unfiltered (_("Process record doesn't support "
5181 "instruction rdmsr.\n"));
5186 case 0x0f31: /* rdtsc */
5187 printf_unfiltered (_("Process record doesn't support "
5188 "instruction rdtsc.\n"));
5193 case 0x0f34: /* sysenter */
5196 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5201 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
5203 printf_unfiltered (_("Process record doesn't support "
5204 "instruction sysenter.\n"));
5208 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
5214 case 0x0f35: /* sysexit */
5215 printf_unfiltered (_("Process record doesn't support "
5216 "instruction sysexit.\n"));
5221 case 0x0f05: /* syscall */
5224 if (gdbarch_tdep (gdbarch
)->i386_syscall_record
== NULL
)
5226 printf_unfiltered (_("Process record doesn't support "
5227 "instruction syscall.\n"));
5231 ret
= gdbarch_tdep (gdbarch
)->i386_syscall_record (ir
.regcache
);
5237 case 0x0f07: /* sysret */
5238 printf_unfiltered (_("Process record doesn't support "
5239 "instruction sysret.\n"));
5244 case 0x0fa2: /* cpuid */
5245 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5246 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5247 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5248 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5251 case 0xf4: /* hlt */
5252 printf_unfiltered (_("Process record doesn't support "
5253 "instruction hlt.\n"));
5259 if (i386_record_modrm (&ir
))
5266 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5270 if (i386_record_lea_modrm (&ir
))
5279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5283 opcode
= opcode
<< 8 | ir
.modrm
;
5290 if (i386_record_modrm (&ir
))
5301 opcode
= opcode
<< 8 | ir
.modrm
;
5304 if (ir
.override
>= 0)
5306 warning (_("Process record ignores the memory "
5307 "change of instruction at "
5308 "address %s because it can't get "
5309 "the value of the segment "
5311 paddress (gdbarch
, ir
.orig_addr
));
5315 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5317 if (record_arch_list_add_mem (tmpu64
, 2))
5320 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5322 if (record_arch_list_add_mem (tmpu64
, 8))
5327 if (record_arch_list_add_mem (tmpu64
, 4))
5338 case 0: /* monitor */
5341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5345 opcode
= opcode
<< 8 | ir
.modrm
;
5353 if (ir
.override
>= 0)
5355 warning (_("Process record ignores the memory "
5356 "change of instruction at "
5357 "address %s because it can't get "
5358 "the value of the segment "
5360 paddress (gdbarch
, ir
.orig_addr
));
5366 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5368 if (record_arch_list_add_mem (tmpu64
, 2))
5371 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5373 if (record_arch_list_add_mem (tmpu64
, 8))
5378 if (record_arch_list_add_mem (tmpu64
, 4))
5390 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5391 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5395 else if (ir
.rm
== 1)
5402 opcode
= opcode
<< 8 | ir
.modrm
;
5409 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5415 if (i386_record_lea_modrm (&ir
))
5418 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5421 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5423 case 7: /* invlpg */
5426 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5431 opcode
= opcode
<< 8 | ir
.modrm
;
5436 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5440 opcode
= opcode
<< 8 | ir
.modrm
;
5446 case 0x0f08: /* invd */
5447 case 0x0f09: /* wbinvd */
5450 case 0x63: /* arpl */
5451 if (i386_record_modrm (&ir
))
5453 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5455 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5456 ? (ir
.reg
| rex_r
) : ir
.rm
);
5460 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5461 if (i386_record_lea_modrm (&ir
))
5464 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5465 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5468 case 0x0f02: /* lar */
5469 case 0x0f03: /* lsl */
5470 if (i386_record_modrm (&ir
))
5472 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5477 if (i386_record_modrm (&ir
))
5479 if (ir
.mod
== 3 && ir
.reg
== 3)
5482 opcode
= opcode
<< 8 | ir
.modrm
;
5494 /* nop (multi byte) */
5497 case 0x0f20: /* mov reg, crN */
5498 case 0x0f22: /* mov crN, reg */
5499 if (i386_record_modrm (&ir
))
5501 if ((ir
.modrm
& 0xc0) != 0xc0)
5504 opcode
= opcode
<< 8 | ir
.modrm
;
5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5517 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5521 opcode
= opcode
<< 8 | ir
.modrm
;
5527 case 0x0f21: /* mov reg, drN */
5528 case 0x0f23: /* mov drN, reg */
5529 if (i386_record_modrm (&ir
))
5531 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5532 || ir
.reg
== 5 || ir
.reg
>= 8)
5535 opcode
= opcode
<< 8 | ir
.modrm
;
5539 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5541 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5544 case 0x0f06: /* clts */
5545 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5548 /* MMX/SSE/SSE2/PNI support */
5560 /* In the future, maybe still need to deal with need_dasm. */
5561 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
5562 if (record_arch_list_add_end ())
5568 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5569 "at address %s.\n"),
5570 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5574 static const int i386_record_regmap
[] =
5576 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
5577 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
5578 0, 0, 0, 0, 0, 0, 0, 0,
5579 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
5580 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
5583 /* Check that the given address appears suitable for a fast
5584 tracepoint, which on x86 means that we need an instruction of at
5585 least 5 bytes, so that we can overwrite it with a 4-byte-offset
5586 jump and not have to worry about program jumps to an address in the
5587 middle of the tracepoint jump. Returns 1 if OK, and writes a size
5588 of instruction to replace, and 0 if not, plus an explanatory
5592 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
5593 CORE_ADDR addr
, int *isize
, char **msg
)
5596 static struct ui_file
*gdb_null
= NULL
;
5598 /* This is based on the target agent using a 4-byte relative jump.
5599 Alternate future possibilities include 8-byte offset for x86-84,
5600 or 3-byte jumps if the program has trampoline space close by. */
5603 /* Dummy file descriptor for the disassembler. */
5605 gdb_null
= ui_file_new ();
5607 /* Check for fit. */
5608 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
5611 /* Return a bit of target-specific detail to add to the caller's
5612 generic failure message. */
5614 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
5627 static struct gdbarch
*
5628 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5630 struct gdbarch_tdep
*tdep
;
5631 struct gdbarch
*gdbarch
;
5633 /* If there is already a candidate, use it. */
5634 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5636 return arches
->gdbarch
;
5638 /* Allocate space for the new architecture. */
5639 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5640 gdbarch
= gdbarch_alloc (&info
, tdep
);
5642 /* General-purpose registers. */
5643 tdep
->gregset
= NULL
;
5644 tdep
->gregset_reg_offset
= NULL
;
5645 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5646 tdep
->sizeof_gregset
= 0;
5648 /* Floating-point registers. */
5649 tdep
->fpregset
= NULL
;
5650 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5652 /* The default settings include the FPU registers, the MMX registers
5653 and the SSE registers. This can be overridden for a specific ABI
5654 by adjusting the members `st0_regnum', `mm0_regnum' and
5655 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5656 will show up in the output of "info all-registers". Ideally we
5657 should try to autodetect whether they are available, such that we
5658 can prevent "info all-registers" from displaying registers that
5661 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5662 [the SSE registers] always (even when they don't exist) or never
5663 showing them to the user (even when they do exist), I prefer the
5664 former over the latter. */
5666 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5668 /* The MMX registers are implemented as pseudo-registers. Put off
5669 calculating the register number for %mm0 until we know the number
5670 of raw registers. */
5671 tdep
->mm0_regnum
= 0;
5673 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5674 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5676 tdep
->jb_pc_offset
= -1;
5677 tdep
->struct_return
= pcc_struct_return
;
5678 tdep
->sigtramp_start
= 0;
5679 tdep
->sigtramp_end
= 0;
5680 tdep
->sigtramp_p
= i386_sigtramp_p
;
5681 tdep
->sigcontext_addr
= NULL
;
5682 tdep
->sc_reg_offset
= NULL
;
5683 tdep
->sc_pc_offset
= -1;
5684 tdep
->sc_sp_offset
= -1;
5686 tdep
->record_regmap
= i386_record_regmap
;
5688 /* The format used for `long double' on almost all i386 targets is
5689 the i387 extended floating-point format. In fact, of all targets
5690 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5691 on having a `long double' that's not `long' at all. */
5692 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5694 /* Although the i387 extended floating-point has only 80 significant
5695 bits, a `long double' actually takes up 96, probably to enforce
5697 set_gdbarch_long_double_bit (gdbarch
, 96);
5699 /* The default ABI includes general-purpose registers,
5700 floating-point registers, and the SSE registers. */
5701 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5702 set_gdbarch_register_name (gdbarch
, i386_register_name
);
5703 set_gdbarch_register_type (gdbarch
, i386_register_type
);
5705 /* Register numbers of various important registers. */
5706 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5707 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5708 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5709 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5711 /* NOTE: kettenis/20040418: GCC does have two possible register
5712 numbering schemes on the i386: dbx and SVR4. These schemes
5713 differ in how they number %ebp, %esp, %eflags, and the
5714 floating-point registers, and are implemented by the arrays
5715 dbx_register_map[] and svr4_dbx_register_map in
5716 gcc/config/i386.c. GCC also defines a third numbering scheme in
5717 gcc/config/i386.c, which it designates as the "default" register
5718 map used in 64bit mode. This last register numbering scheme is
5719 implemented in dbx64_register_map, and is used for AMD64; see
5722 Currently, each GCC i386 target always uses the same register
5723 numbering scheme across all its supported debugging formats
5724 i.e. SDB (COFF), stabs and DWARF 2. This is because
5725 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5726 DBX_REGISTER_NUMBER macro which is defined by each target's
5727 respective config header in a manner independent of the requested
5728 output debugging format.
5730 This does not match the arrangement below, which presumes that
5731 the SDB and stabs numbering schemes differ from the DWARF and
5732 DWARF 2 ones. The reason for this arrangement is that it is
5733 likely to get the numbering scheme for the target's
5734 default/native debug format right. For targets where GCC is the
5735 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5736 targets where the native toolchain uses a different numbering
5737 scheme for a particular debug format (stabs-in-ELF on Solaris)
5738 the defaults below will have to be overridden, like
5739 i386_elf_init_abi() does. */
5741 /* Use the dbx register numbering scheme for stabs and COFF. */
5742 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5743 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5745 /* Use the SVR4 register numbering scheme for DWARF 2. */
5746 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5748 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5749 be in use on any of the supported i386 targets. */
5751 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5753 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5755 /* Call dummy code. */
5756 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5758 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5759 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5760 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5762 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5764 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5766 /* Stack grows downward. */
5767 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5769 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5770 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5771 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5773 set_gdbarch_frame_args_skip (gdbarch
, 8);
5775 /* Wire in the MMX registers. */
5776 set_gdbarch_num_pseudo_regs (gdbarch
, i386_num_mmx_regs
);
5777 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5778 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5780 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5782 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5784 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5786 /* Add the i386 register groups. */
5787 i386_add_reggroups (gdbarch
);
5788 set_gdbarch_register_reggroup_p (gdbarch
, i386_register_reggroup_p
);
5790 /* Helper for function argument information. */
5791 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5793 /* Hook the function epilogue frame unwinder. This unwinder is
5794 appended to the list first, so that it supercedes the Dwarf
5795 unwinder in function epilogues (where the Dwarf unwinder
5796 currently fails). */
5797 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
5799 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5800 to the list before the prologue-based unwinders, so that Dwarf
5801 CFI info will be used if it is available. */
5802 dwarf2_append_unwinders (gdbarch
);
5804 frame_base_set_default (gdbarch
, &i386_frame_base
);
5806 /* Hook in ABI-specific overrides, if they have been registered. */
5807 gdbarch_init_osabi (info
, gdbarch
);
5809 /* Hook in the legacy prologue-based unwinders last (fallback). */
5810 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5811 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5813 /* If we have a register mapping, enable the generic core file
5814 support, unless it has already been enabled. */
5815 if (tdep
->gregset_reg_offset
5816 && !gdbarch_regset_from_core_section_p (gdbarch
))
5817 set_gdbarch_regset_from_core_section (gdbarch
,
5818 i386_regset_from_core_section
);
5820 /* Unless support for MMX has been disabled, make %mm0 the first
5822 if (tdep
->mm0_regnum
== 0)
5823 tdep
->mm0_regnum
= gdbarch_num_regs (gdbarch
);
5825 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5826 i386_skip_permanent_breakpoint
);
5828 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
5829 i386_fast_tracepoint_valid_at
);
5834 static enum gdb_osabi
5835 i386_coff_osabi_sniffer (bfd
*abfd
)
5837 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5838 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5839 return GDB_OSABI_GO32
;
5841 return GDB_OSABI_UNKNOWN
;
5845 /* Provide a prototype to silence -Wmissing-prototypes. */
5846 void _initialize_i386_tdep (void);
5849 _initialize_i386_tdep (void)
5851 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5853 /* Add the variable that controls the disassembly flavor. */
5854 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5855 &disassembly_flavor
, _("\
5856 Set the disassembly flavor."), _("\
5857 Show the disassembly flavor."), _("\
5858 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5860 NULL
, /* FIXME: i18n: */
5861 &setlist
, &showlist
);
5863 /* Add the variable that controls the convention for returning
5865 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5866 &struct_convention
, _("\
5867 Set the convention for returning small structs."), _("\
5868 Show the convention for returning small structs."), _("\
5869 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5872 NULL
, /* FIXME: i18n: */
5873 &setlist
, &showlist
);
5875 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5876 i386_coff_osabi_sniffer
);
5878 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5879 i386_svr4_init_abi
);
5880 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5881 i386_go32_init_abi
);
5883 /* Initialize the i386-specific register groups. */
5884 i386_init_reggroups ();