1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
58 static char *i386_register_names
[] =
60 "eax", "ecx", "edx", "ebx",
61 "esp", "ebp", "esi", "edi",
62 "eip", "eflags", "cs", "ss",
63 "ds", "es", "fs", "gs",
64 "st0", "st1", "st2", "st3",
65 "st4", "st5", "st6", "st7",
66 "fctrl", "fstat", "ftag", "fiseg",
67 "fioff", "foseg", "fooff", "fop",
68 "xmm0", "xmm1", "xmm2", "xmm3",
69 "xmm4", "xmm5", "xmm6", "xmm7",
73 static const int i386_num_register_names
= ARRAY_SIZE (i386_register_names
);
75 /* Register names for MMX pseudo-registers. */
77 static char *i386_mmx_names
[] =
79 "mm0", "mm1", "mm2", "mm3",
80 "mm4", "mm5", "mm6", "mm7"
83 static const int i386_num_mmx_regs
= ARRAY_SIZE (i386_mmx_names
);
86 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
88 int mm0_regnum
= gdbarch_tdep (gdbarch
)->mm0_regnum
;
93 return (regnum
>= mm0_regnum
&& regnum
< mm0_regnum
+ i386_num_mmx_regs
);
99 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
103 if (I387_NUM_XMM_REGS (tdep
) == 0)
106 return (I387_XMM0_REGNUM (tdep
) <= regnum
107 && regnum
< I387_MXCSR_REGNUM (tdep
));
111 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
113 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
115 if (I387_NUM_XMM_REGS (tdep
) == 0)
118 return (regnum
== I387_MXCSR_REGNUM (tdep
));
124 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
128 if (I387_ST0_REGNUM (tdep
) < 0)
131 return (I387_ST0_REGNUM (tdep
) <= regnum
132 && regnum
< I387_FCTRL_REGNUM (tdep
));
136 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
140 if (I387_ST0_REGNUM (tdep
) < 0)
143 return (I387_FCTRL_REGNUM (tdep
) <= regnum
144 && regnum
< I387_XMM0_REGNUM (tdep
));
147 /* Return the name of register REGNUM. */
150 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
152 if (i386_mmx_regnum_p (gdbarch
, regnum
))
153 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (gdbarch_tdep (gdbarch
))];
155 if (regnum
>= 0 && regnum
< i386_num_register_names
)
156 return i386_register_names
[regnum
];
161 /* Convert a dbx register number REG to the appropriate register
162 number used by GDB. */
165 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
169 /* This implements what GCC calls the "default" register map
170 (dbx_register_map[]). */
172 if (reg
>= 0 && reg
<= 7)
174 /* General-purpose registers. The debug info calls %ebp
175 register 4, and %esp register 5. */
182 else if (reg
>= 12 && reg
<= 19)
184 /* Floating-point registers. */
185 return reg
- 12 + I387_ST0_REGNUM (tdep
);
187 else if (reg
>= 21 && reg
<= 28)
190 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
192 else if (reg
>= 29 && reg
<= 36)
195 return reg
- 29 + I387_MM0_REGNUM (tdep
);
198 /* This will hopefully provoke a warning. */
199 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
202 /* Convert SVR4 register number REG to the appropriate register number
206 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 /* This implements the GCC register map that tries to be compatible
211 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
213 /* The SVR4 register numbering includes %eip and %eflags, and
214 numbers the floating point registers differently. */
215 if (reg
>= 0 && reg
<= 9)
217 /* General-purpose registers. */
220 else if (reg
>= 11 && reg
<= 18)
222 /* Floating-point registers. */
223 return reg
- 11 + I387_ST0_REGNUM (tdep
);
225 else if (reg
>= 21 && reg
<= 36)
227 /* The SSE and MMX registers have the same numbers as with dbx. */
228 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
233 case 37: return I387_FCTRL_REGNUM (tdep
);
234 case 38: return I387_FSTAT_REGNUM (tdep
);
235 case 39: return I387_MXCSR_REGNUM (tdep
);
236 case 40: return I386_ES_REGNUM
;
237 case 41: return I386_CS_REGNUM
;
238 case 42: return I386_SS_REGNUM
;
239 case 43: return I386_DS_REGNUM
;
240 case 44: return I386_FS_REGNUM
;
241 case 45: return I386_GS_REGNUM
;
244 /* This will hopefully provoke a warning. */
245 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
250 /* This is the variable that is set with "set disassembly-flavor", and
251 its legitimate values. */
252 static const char att_flavor
[] = "att";
253 static const char intel_flavor
[] = "intel";
254 static const char *valid_flavors
[] =
260 static const char *disassembly_flavor
= att_flavor
;
263 /* Use the program counter to determine the contents and size of a
264 breakpoint instruction. Return a pointer to a string of bytes that
265 encode a breakpoint instruction, store the length of the string in
266 *LEN and optionally adjust *PC to point to the correct memory
267 location for inserting the breakpoint.
269 On the i386 we have a single breakpoint that fits in a single byte
270 and can be inserted anywhere.
272 This function is 64-bit safe. */
274 static const gdb_byte
*
275 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
277 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
279 *len
= sizeof (break_insn
);
283 /* Displaced instruction handling. */
285 /* Skip the legacy instruction prefixes in INSN.
286 Not all prefixes are valid for any particular insn
287 but we needn't care, the insn will fault if it's invalid.
288 The result is a pointer to the first opcode byte,
289 or NULL if we run off the end of the buffer. */
292 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
294 gdb_byte
*end
= insn
+ max_len
;
300 case DATA_PREFIX_OPCODE
:
301 case ADDR_PREFIX_OPCODE
:
302 case CS_PREFIX_OPCODE
:
303 case DS_PREFIX_OPCODE
:
304 case ES_PREFIX_OPCODE
:
305 case FS_PREFIX_OPCODE
:
306 case GS_PREFIX_OPCODE
:
307 case SS_PREFIX_OPCODE
:
308 case LOCK_PREFIX_OPCODE
:
309 case REPE_PREFIX_OPCODE
:
310 case REPNE_PREFIX_OPCODE
:
322 i386_absolute_jmp_p (const gdb_byte
*insn
)
324 /* jmp far (absolute address in operand) */
330 /* jump near, absolute indirect (/4) */
331 if ((insn
[1] & 0x38) == 0x20)
334 /* jump far, absolute indirect (/5) */
335 if ((insn
[1] & 0x38) == 0x28)
343 i386_absolute_call_p (const gdb_byte
*insn
)
345 /* call far, absolute */
351 /* Call near, absolute indirect (/2) */
352 if ((insn
[1] & 0x38) == 0x10)
355 /* Call far, absolute indirect (/3) */
356 if ((insn
[1] & 0x38) == 0x18)
364 i386_ret_p (const gdb_byte
*insn
)
368 case 0xc2: /* ret near, pop N bytes */
369 case 0xc3: /* ret near */
370 case 0xca: /* ret far, pop N bytes */
371 case 0xcb: /* ret far */
372 case 0xcf: /* iret */
381 i386_call_p (const gdb_byte
*insn
)
383 if (i386_absolute_call_p (insn
))
386 /* call near, relative */
393 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
394 length in bytes. Otherwise, return zero. */
397 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
408 /* Fix up the state of registers and memory after having single-stepped
409 a displaced instruction. */
412 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
413 struct displaced_step_closure
*closure
,
414 CORE_ADDR from
, CORE_ADDR to
,
415 struct regcache
*regs
)
417 /* The offset we applied to the instruction's address.
418 This could well be negative (when viewed as a signed 32-bit
419 value), but ULONGEST won't reflect that, so take care when
421 ULONGEST insn_offset
= to
- from
;
423 /* Since we use simple_displaced_step_copy_insn, our closure is a
424 copy of the instruction. */
425 gdb_byte
*insn
= (gdb_byte
*) closure
;
426 /* The start of the insn, needed in case we see some prefixes. */
427 gdb_byte
*insn_start
= insn
;
430 fprintf_unfiltered (gdb_stdlog
,
431 "displaced: fixup (%s, %s), "
432 "insn = 0x%02x 0x%02x ...\n",
433 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
436 /* The list of issues to contend with here is taken from
437 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
438 Yay for Free Software! */
440 /* Relocate the %eip, if necessary. */
442 /* The instruction recognizers we use assume any leading prefixes
443 have been skipped. */
445 /* This is the size of the buffer in closure. */
446 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
447 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
448 /* If there are too many prefixes, just ignore the insn.
449 It will fault when run. */
454 /* Except in the case of absolute or indirect jump or call
455 instructions, or a return instruction, the new eip is relative to
456 the displaced instruction; make it relative. Well, signal
457 handler returns don't need relocation either, but we use the
458 value of %eip to recognize those; see below. */
459 if (! i386_absolute_jmp_p (insn
)
460 && ! i386_absolute_call_p (insn
)
461 && ! i386_ret_p (insn
))
466 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
468 /* A signal trampoline system call changes the %eip, resuming
469 execution of the main program after the signal handler has
470 returned. That makes them like 'return' instructions; we
471 shouldn't relocate %eip.
473 But most system calls don't, and we do need to relocate %eip.
475 Our heuristic for distinguishing these cases: if stepping
476 over the system call instruction left control directly after
477 the instruction, the we relocate --- control almost certainly
478 doesn't belong in the displaced copy. Otherwise, we assume
479 the instruction has put control where it belongs, and leave
480 it unrelocated. Goodness help us if there are PC-relative
482 if (i386_syscall_p (insn
, &insn_len
)
483 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
486 fprintf_unfiltered (gdb_stdlog
,
487 "displaced: syscall changed %%eip; "
492 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
494 /* If we just stepped over a breakpoint insn, we don't backup
495 the pc on purpose; this is to match behaviour without
498 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
501 fprintf_unfiltered (gdb_stdlog
,
503 "relocated %%eip from %s to %s\n",
504 paddress (gdbarch
, orig_eip
),
505 paddress (gdbarch
, eip
));
509 /* If the instruction was PUSHFL, then the TF bit will be set in the
510 pushed value, and should be cleared. We'll leave this for later,
511 since GDB already messes up the TF flag when stepping over a
514 /* If the instruction was a call, the return address now atop the
515 stack is the address following the copied instruction. We need
516 to make it the address following the original instruction. */
517 if (i386_call_p (insn
))
521 const ULONGEST retaddr_len
= 4;
523 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
524 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
);
525 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
526 write_memory_unsigned_integer (esp
, retaddr_len
, retaddr
);
529 fprintf_unfiltered (gdb_stdlog
,
530 "displaced: relocated return addr at %s to %s\n",
531 paddress (gdbarch
, esp
),
532 paddress (gdbarch
, retaddr
));
536 #ifdef I386_REGNO_TO_SYMMETRY
537 #error "The Sequent Symmetry is no longer supported."
540 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
541 and %esp "belong" to the calling function. Therefore these
542 registers should be saved if they're going to be modified. */
544 /* The maximum number of saved registers. This should include all
545 registers mentioned above, and %eip. */
546 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
548 struct i386_frame_cache
555 /* Saved registers. */
556 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
561 /* Stack space reserved for local variables. */
565 /* Allocate and initialize a frame cache. */
567 static struct i386_frame_cache
*
568 i386_alloc_frame_cache (void)
570 struct i386_frame_cache
*cache
;
573 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
577 cache
->sp_offset
= -4;
580 /* Saved registers. We initialize these to -1 since zero is a valid
581 offset (that's where %ebp is supposed to be stored). */
582 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
583 cache
->saved_regs
[i
] = -1;
585 cache
->saved_sp_reg
= -1;
586 cache
->pc_in_eax
= 0;
588 /* Frameless until proven otherwise. */
594 /* If the instruction at PC is a jump, return the address of its
595 target. Otherwise, return PC. */
598 i386_follow_jump (CORE_ADDR pc
)
604 target_read_memory (pc
, &op
, 1);
608 op
= read_memory_unsigned_integer (pc
+ 1, 1);
614 /* Relative jump: if data16 == 0, disp32, else disp16. */
617 delta
= read_memory_integer (pc
+ 2, 2);
619 /* Include the size of the jmp instruction (including the
625 delta
= read_memory_integer (pc
+ 1, 4);
627 /* Include the size of the jmp instruction. */
632 /* Relative jump, disp8 (ignore data16). */
633 delta
= read_memory_integer (pc
+ data16
+ 1, 1);
642 /* Check whether PC points at a prologue for a function returning a
643 structure or union. If so, it updates CACHE and returns the
644 address of the first instruction after the code sequence that
645 removes the "hidden" argument from the stack or CURRENT_PC,
646 whichever is smaller. Otherwise, return PC. */
649 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
650 struct i386_frame_cache
*cache
)
652 /* Functions that return a structure or union start with:
655 xchgl %eax, (%esp) 0x87 0x04 0x24
656 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
658 (the System V compiler puts out the second `xchg' instruction,
659 and the assembler doesn't try to optimize it, so the 'sib' form
660 gets generated). This sequence is used to get the address of the
661 return buffer for a function that returns a structure. */
662 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
663 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
667 if (current_pc
<= pc
)
670 target_read_memory (pc
, &op
, 1);
672 if (op
!= 0x58) /* popl %eax */
675 target_read_memory (pc
+ 1, buf
, 4);
676 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
679 if (current_pc
== pc
)
681 cache
->sp_offset
+= 4;
685 if (current_pc
== pc
+ 1)
687 cache
->pc_in_eax
= 1;
691 if (buf
[1] == proto1
[1])
698 i386_skip_probe (CORE_ADDR pc
)
700 /* A function may start with
714 target_read_memory (pc
, &op
, 1);
716 if (op
== 0x68 || op
== 0x6a)
720 /* Skip past the `pushl' instruction; it has either a one-byte or a
721 four-byte operand, depending on the opcode. */
727 /* Read the following 8 bytes, which should be `call _probe' (6
728 bytes) followed by `addl $4,%esp' (2 bytes). */
729 read_memory (pc
+ delta
, buf
, sizeof (buf
));
730 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
731 pc
+= delta
+ sizeof (buf
);
737 /* GCC 4.1 and later, can put code in the prologue to realign the
738 stack pointer. Check whether PC points to such code, and update
739 CACHE accordingly. Return the first instruction after the code
740 sequence or CURRENT_PC, whichever is smaller. If we don't
741 recognize the code, return PC. */
744 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
745 struct i386_frame_cache
*cache
)
747 /* There are 2 code sequences to re-align stack before the frame
750 1. Use a caller-saved saved register:
756 2. Use a callee-saved saved register:
763 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
765 0x83 0xe4 0xf0 andl $-16, %esp
766 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
771 int offset
, offset_and
;
772 static int regnums
[8] = {
773 I386_EAX_REGNUM
, /* %eax */
774 I386_ECX_REGNUM
, /* %ecx */
775 I386_EDX_REGNUM
, /* %edx */
776 I386_EBX_REGNUM
, /* %ebx */
777 I386_ESP_REGNUM
, /* %esp */
778 I386_EBP_REGNUM
, /* %ebp */
779 I386_ESI_REGNUM
, /* %esi */
780 I386_EDI_REGNUM
/* %edi */
783 if (target_read_memory (pc
, buf
, sizeof buf
))
786 /* Check caller-saved saved register. The first instruction has
787 to be "leal 4(%esp), %reg". */
788 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
790 /* MOD must be binary 10 and R/M must be binary 100. */
791 if ((buf
[1] & 0xc7) != 0x44)
794 /* REG has register number. */
795 reg
= (buf
[1] >> 3) & 7;
800 /* Check callee-saved saved register. The first instruction
801 has to be "pushl %reg". */
802 if ((buf
[0] & 0xf8) != 0x50)
808 /* The next instruction has to be "leal 8(%esp), %reg". */
809 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
812 /* MOD must be binary 10 and R/M must be binary 100. */
813 if ((buf
[2] & 0xc7) != 0x44)
816 /* REG has register number. Registers in pushl and leal have to
818 if (reg
!= ((buf
[2] >> 3) & 7))
824 /* Rigister can't be %esp nor %ebp. */
825 if (reg
== 4 || reg
== 5)
828 /* The next instruction has to be "andl $-XXX, %esp". */
829 if (buf
[offset
+ 1] != 0xe4
830 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
834 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
836 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
837 0xfc. REG must be binary 110 and MOD must be binary 01. */
838 if (buf
[offset
] != 0xff
839 || buf
[offset
+ 2] != 0xfc
840 || (buf
[offset
+ 1] & 0xf8) != 0x70)
843 /* R/M has register. Registers in leal and pushl have to be the
845 if (reg
!= (buf
[offset
+ 1] & 7))
848 if (current_pc
> pc
+ offset_and
)
849 cache
->saved_sp_reg
= regnums
[reg
];
851 return min (pc
+ offset
+ 3, current_pc
);
854 /* Maximum instruction length we need to handle. */
855 #define I386_MAX_MATCHED_INSN_LEN 6
857 /* Instruction description. */
861 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
862 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
865 /* Search for the instruction at PC in the list SKIP_INSNS. Return
866 the first instruction description that matches. Otherwise, return
869 static struct i386_insn
*
870 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
872 struct i386_insn
*insn
;
875 target_read_memory (pc
, &op
, 1);
877 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
879 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
881 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
882 int insn_matched
= 1;
885 gdb_assert (insn
->len
> 1);
886 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
888 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
889 for (i
= 1; i
< insn
->len
; i
++)
891 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
903 /* Some special instructions that might be migrated by GCC into the
904 part of the prologue that sets up the new stack frame. Because the
905 stack frame hasn't been setup yet, no registers have been saved
906 yet, and only the scratch registers %eax, %ecx and %edx can be
909 struct i386_insn i386_frame_setup_skip_insns
[] =
911 /* Check for `movb imm8, r' and `movl imm32, r'.
913 ??? Should we handle 16-bit operand-sizes here? */
915 /* `movb imm8, %al' and `movb imm8, %ah' */
916 /* `movb imm8, %cl' and `movb imm8, %ch' */
917 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
918 /* `movb imm8, %dl' and `movb imm8, %dh' */
919 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
920 /* `movl imm32, %eax' and `movl imm32, %ecx' */
921 { 5, { 0xb8 }, { 0xfe } },
922 /* `movl imm32, %edx' */
923 { 5, { 0xba }, { 0xff } },
925 /* Check for `mov imm32, r32'. Note that there is an alternative
926 encoding for `mov m32, %eax'.
928 ??? Should we handle SIB adressing here?
929 ??? Should we handle 16-bit operand-sizes here? */
931 /* `movl m32, %eax' */
932 { 5, { 0xa1 }, { 0xff } },
933 /* `movl m32, %eax' and `mov; m32, %ecx' */
934 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
935 /* `movl m32, %edx' */
936 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
938 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
939 Because of the symmetry, there are actually two ways to encode
940 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
941 opcode bytes 0x31 and 0x33 for `xorl'. */
943 /* `subl %eax, %eax' */
944 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
945 /* `subl %ecx, %ecx' */
946 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
947 /* `subl %edx, %edx' */
948 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
949 /* `xorl %eax, %eax' */
950 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
951 /* `xorl %ecx, %ecx' */
952 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
953 /* `xorl %edx, %edx' */
954 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
959 /* Check whether PC points to a no-op instruction. */
961 i386_skip_noop (CORE_ADDR pc
)
966 target_read_memory (pc
, &op
, 1);
971 /* Ignore `nop' instruction. */
975 target_read_memory (pc
, &op
, 1);
978 /* Ignore no-op instruction `mov %edi, %edi'.
979 Microsoft system dlls often start with
980 a `mov %edi,%edi' instruction.
981 The 5 bytes before the function start are
982 filled with `nop' instructions.
983 This pattern can be used for hot-patching:
984 The `mov %edi, %edi' instruction can be replaced by a
985 near jump to the location of the 5 `nop' instructions
986 which can be replaced by a 32-bit jump to anywhere
987 in the 32-bit address space. */
991 target_read_memory (pc
+ 1, &op
, 1);
995 target_read_memory (pc
, &op
, 1);
1003 /* Check whether PC points at a code that sets up a new stack frame.
1004 If so, it updates CACHE and returns the address of the first
1005 instruction after the sequence that sets up the frame or LIMIT,
1006 whichever is smaller. If we don't recognize the code, return PC. */
1009 i386_analyze_frame_setup (CORE_ADDR pc
, CORE_ADDR limit
,
1010 struct i386_frame_cache
*cache
)
1012 struct i386_insn
*insn
;
1019 target_read_memory (pc
, &op
, 1);
1021 if (op
== 0x55) /* pushl %ebp */
1023 /* Take into account that we've executed the `pushl %ebp' that
1024 starts this instruction sequence. */
1025 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1026 cache
->sp_offset
+= 4;
1029 /* If that's all, return now. */
1033 /* Check for some special instructions that might be migrated by
1034 GCC into the prologue and skip them. At this point in the
1035 prologue, code should only touch the scratch registers %eax,
1036 %ecx and %edx, so while the number of posibilities is sheer,
1039 Make sure we only skip these instructions if we later see the
1040 `movl %esp, %ebp' that actually sets up the frame. */
1041 while (pc
+ skip
< limit
)
1043 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1050 /* If that's all, return now. */
1051 if (limit
<= pc
+ skip
)
1054 target_read_memory (pc
+ skip
, &op
, 1);
1056 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1060 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1) != 0xec)
1064 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1) != 0xe5)
1071 /* OK, we actually have a frame. We just don't know how large
1072 it is yet. Set its size to zero. We'll adjust it if
1073 necessary. We also now commit to skipping the special
1074 instructions mentioned before. */
1078 /* If that's all, return now. */
1082 /* Check for stack adjustment
1086 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1087 reg, so we don't have to worry about a data16 prefix. */
1088 target_read_memory (pc
, &op
, 1);
1091 /* `subl' with 8-bit immediate. */
1092 if (read_memory_unsigned_integer (pc
+ 1, 1) != 0xec)
1093 /* Some instruction starting with 0x83 other than `subl'. */
1096 /* `subl' with signed 8-bit immediate (though it wouldn't
1097 make sense to be negative). */
1098 cache
->locals
= read_memory_integer (pc
+ 2, 1);
1101 else if (op
== 0x81)
1103 /* Maybe it is `subl' with a 32-bit immediate. */
1104 if (read_memory_unsigned_integer (pc
+ 1, 1) != 0xec)
1105 /* Some instruction starting with 0x81 other than `subl'. */
1108 /* It is `subl' with a 32-bit immediate. */
1109 cache
->locals
= read_memory_integer (pc
+ 2, 4);
1114 /* Some instruction other than `subl'. */
1118 else if (op
== 0xc8) /* enter */
1120 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2);
1127 /* Check whether PC points at code that saves registers on the stack.
1128 If so, it updates CACHE and returns the address of the first
1129 instruction after the register saves or CURRENT_PC, whichever is
1130 smaller. Otherwise, return PC. */
1133 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1134 struct i386_frame_cache
*cache
)
1136 CORE_ADDR offset
= 0;
1140 if (cache
->locals
> 0)
1141 offset
-= cache
->locals
;
1142 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1144 target_read_memory (pc
, &op
, 1);
1145 if (op
< 0x50 || op
> 0x57)
1149 cache
->saved_regs
[op
- 0x50] = offset
;
1150 cache
->sp_offset
+= 4;
1157 /* Do a full analysis of the prologue at PC and update CACHE
1158 accordingly. Bail out early if CURRENT_PC is reached. Return the
1159 address where the analysis stopped.
1161 We handle these cases:
1163 The startup sequence can be at the start of the function, or the
1164 function can start with a branch to startup code at the end.
1166 %ebp can be set up with either the 'enter' instruction, or "pushl
1167 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1168 once used in the System V compiler).
1170 Local space is allocated just below the saved %ebp by either the
1171 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1172 16-bit unsigned argument for space to allocate, and the 'addl'
1173 instruction could have either a signed byte, or 32-bit immediate.
1175 Next, the registers used by this function are pushed. With the
1176 System V compiler they will always be in the order: %edi, %esi,
1177 %ebx (and sometimes a harmless bug causes it to also save but not
1178 restore %eax); however, the code below is willing to see the pushes
1179 in any order, and will handle up to 8 of them.
1181 If the setup sequence is at the end of the function, then the next
1182 instruction will be a branch back to the start. */
1185 i386_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
1186 struct i386_frame_cache
*cache
)
1188 pc
= i386_skip_noop (pc
);
1189 pc
= i386_follow_jump (pc
);
1190 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1191 pc
= i386_skip_probe (pc
);
1192 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1193 pc
= i386_analyze_frame_setup (pc
, current_pc
, cache
);
1194 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1197 /* Return PC of first real instruction. */
1200 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1202 static gdb_byte pic_pat
[6] =
1204 0xe8, 0, 0, 0, 0, /* call 0x0 */
1205 0x5b, /* popl %ebx */
1207 struct i386_frame_cache cache
;
1213 pc
= i386_analyze_prologue (start_pc
, 0xffffffff, &cache
);
1214 if (cache
.locals
< 0)
1217 /* Found valid frame setup. */
1219 /* The native cc on SVR4 in -K PIC mode inserts the following code
1220 to get the address of the global offset table (GOT) into register
1225 movl %ebx,x(%ebp) (optional)
1228 This code is with the rest of the prologue (at the end of the
1229 function), so we have to skip it to get to the first real
1230 instruction at the start of the function. */
1232 for (i
= 0; i
< 6; i
++)
1234 target_read_memory (pc
+ i
, &op
, 1);
1235 if (pic_pat
[i
] != op
)
1242 target_read_memory (pc
+ delta
, &op
, 1);
1244 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1246 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1);
1248 if (op
== 0x5d) /* One byte offset from %ebp. */
1250 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1252 else /* Unexpected instruction. */
1255 target_read_memory (pc
+ delta
, &op
, 1);
1259 if (delta
> 0 && op
== 0x81
1260 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1) == 0xc3)
1266 /* If the function starts with a branch (to startup code at the end)
1267 the last instruction should bring us back to the first
1268 instruction of the real code. */
1269 if (i386_follow_jump (start_pc
) != start_pc
)
1270 pc
= i386_follow_jump (pc
);
1275 /* Check that the code pointed to by PC corresponds to a call to
1276 __main, skip it if so. Return PC otherwise. */
1279 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1283 target_read_memory (pc
, &op
, 1);
1288 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1290 /* Make sure address is computed correctly as a 32bit
1291 integer even if CORE_ADDR is 64 bit wide. */
1292 struct minimal_symbol
*s
;
1293 CORE_ADDR call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4);
1295 call_dest
= call_dest
& 0xffffffffU
;
1296 s
= lookup_minimal_symbol_by_pc (call_dest
);
1298 && SYMBOL_LINKAGE_NAME (s
) != NULL
1299 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1307 /* This function is 64-bit safe. */
1310 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1314 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1315 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1319 /* Normal frames. */
1321 static struct i386_frame_cache
*
1322 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1324 struct i386_frame_cache
*cache
;
1331 cache
= i386_alloc_frame_cache ();
1332 *this_cache
= cache
;
1334 /* In principle, for normal frames, %ebp holds the frame pointer,
1335 which holds the base address for the current stack frame.
1336 However, for functions that don't need it, the frame pointer is
1337 optional. For these "frameless" functions the frame pointer is
1338 actually the frame pointer of the calling frame. Signal
1339 trampolines are just a special case of a "frameless" function.
1340 They (usually) share their frame pointer with the frame that was
1341 in progress when the signal occurred. */
1343 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1344 cache
->base
= extract_unsigned_integer (buf
, 4);
1345 if (cache
->base
== 0)
1348 /* For normal frames, %eip is stored at 4(%ebp). */
1349 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1351 cache
->pc
= get_frame_func (this_frame
);
1353 i386_analyze_prologue (cache
->pc
, get_frame_pc (this_frame
), cache
);
1355 if (cache
->saved_sp_reg
!= -1)
1357 /* Saved stack pointer has been saved. */
1358 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1359 cache
->saved_sp
= extract_unsigned_integer(buf
, 4);
1362 if (cache
->locals
< 0)
1364 /* We didn't find a valid frame, which means that CACHE->base
1365 currently holds the frame pointer for our calling frame. If
1366 we're at the start of a function, or somewhere half-way its
1367 prologue, the function's frame probably hasn't been fully
1368 setup yet. Try to reconstruct the base address for the stack
1369 frame by looking at the stack pointer. For truly "frameless"
1370 functions this might work too. */
1372 if (cache
->saved_sp_reg
!= -1)
1374 /* We're halfway aligning the stack. */
1375 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1376 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1378 /* This will be added back below. */
1379 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1383 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1384 cache
->base
= extract_unsigned_integer (buf
, 4) + cache
->sp_offset
;
1388 /* Now that we have the base address for the stack frame we can
1389 calculate the value of %esp in the calling frame. */
1390 if (cache
->saved_sp
== 0)
1391 cache
->saved_sp
= cache
->base
+ 8;
1393 /* Adjust all the saved registers such that they contain addresses
1394 instead of offsets. */
1395 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1396 if (cache
->saved_regs
[i
] != -1)
1397 cache
->saved_regs
[i
] += cache
->base
;
1403 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1404 struct frame_id
*this_id
)
1406 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1408 /* This marks the outermost frame. */
1409 if (cache
->base
== 0)
1412 /* See the end of i386_push_dummy_call. */
1413 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1416 static struct value
*
1417 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1420 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1422 gdb_assert (regnum
>= 0);
1424 /* The System V ABI says that:
1426 "The flags register contains the system flags, such as the
1427 direction flag and the carry flag. The direction flag must be
1428 set to the forward (that is, zero) direction before entry and
1429 upon exit from a function. Other user flags have no specified
1430 role in the standard calling sequence and are not preserved."
1432 To guarantee the "upon exit" part of that statement we fake a
1433 saved flags register that has its direction flag cleared.
1435 Note that GCC doesn't seem to rely on the fact that the direction
1436 flag is cleared after a function return; it always explicitly
1437 clears the flag before operations where it matters.
1439 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1440 right thing to do. The way we fake the flags register here makes
1441 it impossible to change it. */
1443 if (regnum
== I386_EFLAGS_REGNUM
)
1447 val
= get_frame_register_unsigned (this_frame
, regnum
);
1449 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1452 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1453 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1455 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1456 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1458 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1459 return frame_unwind_got_memory (this_frame
, regnum
,
1460 cache
->saved_regs
[regnum
]);
1462 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1465 static const struct frame_unwind i386_frame_unwind
=
1469 i386_frame_prev_register
,
1471 default_frame_sniffer
1475 /* Signal trampolines. */
1477 static struct i386_frame_cache
*
1478 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1480 struct i386_frame_cache
*cache
;
1481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1488 cache
= i386_alloc_frame_cache ();
1490 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1491 cache
->base
= extract_unsigned_integer (buf
, 4) - 4;
1493 addr
= tdep
->sigcontext_addr (this_frame
);
1494 if (tdep
->sc_reg_offset
)
1498 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1500 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1501 if (tdep
->sc_reg_offset
[i
] != -1)
1502 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1506 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1507 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1510 *this_cache
= cache
;
1515 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1516 struct frame_id
*this_id
)
1518 struct i386_frame_cache
*cache
=
1519 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1521 /* See the end of i386_push_dummy_call. */
1522 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1525 static struct value
*
1526 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1527 void **this_cache
, int regnum
)
1529 /* Make sure we've initialized the cache. */
1530 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1532 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1536 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1537 struct frame_info
*this_frame
,
1538 void **this_prologue_cache
)
1540 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1542 /* We shouldn't even bother if we don't have a sigcontext_addr
1544 if (tdep
->sigcontext_addr
== NULL
)
1547 if (tdep
->sigtramp_p
!= NULL
)
1549 if (tdep
->sigtramp_p (this_frame
))
1553 if (tdep
->sigtramp_start
!= 0)
1555 CORE_ADDR pc
= get_frame_pc (this_frame
);
1557 gdb_assert (tdep
->sigtramp_end
!= 0);
1558 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1565 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1568 i386_sigtramp_frame_this_id
,
1569 i386_sigtramp_frame_prev_register
,
1571 i386_sigtramp_frame_sniffer
1576 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1578 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1583 static const struct frame_base i386_frame_base
=
1586 i386_frame_base_address
,
1587 i386_frame_base_address
,
1588 i386_frame_base_address
1591 static struct frame_id
1592 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1596 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1598 /* See the end of i386_push_dummy_call. */
1599 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1603 /* Figure out where the longjmp will land. Slurp the args out of the
1604 stack. We expect the first arg to be a pointer to the jmp_buf
1605 structure from which we extract the address that we will land at.
1606 This address is copied into PC. This routine returns non-zero on
1610 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1613 CORE_ADDR sp
, jb_addr
;
1614 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1615 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1617 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1618 longjmp will land. */
1619 if (jb_pc_offset
== -1)
1622 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1623 sp
= extract_unsigned_integer (buf
, 4);
1624 if (target_read_memory (sp
+ 4, buf
, 4))
1627 jb_addr
= extract_unsigned_integer (buf
, 4);
1628 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1631 *pc
= extract_unsigned_integer (buf
, 4);
1636 /* Check whether TYPE must be 16-byte-aligned when passed as a
1637 function argument. 16-byte vectors, _Decimal128 and structures or
1638 unions containing such types must be 16-byte-aligned; other
1639 arguments are 4-byte-aligned. */
1642 i386_16_byte_align_p (struct type
*type
)
1644 type
= check_typedef (type
);
1645 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1646 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1647 && TYPE_LENGTH (type
) == 16)
1649 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1650 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1651 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1652 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1655 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1657 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1665 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1666 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1667 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1668 CORE_ADDR struct_addr
)
1675 /* Determine the total space required for arguments and struct
1676 return address in a first pass (allowing for 16-byte-aligned
1677 arguments), then push arguments in a second pass. */
1679 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1681 int args_space_used
= 0;
1682 int have_16_byte_aligned_arg
= 0;
1688 /* Push value address. */
1689 store_unsigned_integer (buf
, 4, struct_addr
);
1690 write_memory (sp
, buf
, 4);
1691 args_space_used
+= 4;
1697 for (i
= 0; i
< nargs
; i
++)
1699 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1703 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1704 args_space_used
= align_up (args_space_used
, 16);
1706 write_memory (sp
+ args_space_used
,
1707 value_contents_all (args
[i
]), len
);
1708 /* The System V ABI says that:
1710 "An argument's size is increased, if necessary, to make it a
1711 multiple of [32-bit] words. This may require tail padding,
1712 depending on the size of the argument."
1714 This makes sure the stack stays word-aligned. */
1715 args_space_used
+= align_up (len
, 4);
1719 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1721 args_space
= align_up (args_space
, 16);
1722 have_16_byte_aligned_arg
= 1;
1724 args_space
+= align_up (len
, 4);
1730 if (have_16_byte_aligned_arg
)
1731 args_space
= align_up (args_space
, 16);
1736 /* Store return address. */
1738 store_unsigned_integer (buf
, 4, bp_addr
);
1739 write_memory (sp
, buf
, 4);
1741 /* Finally, update the stack pointer... */
1742 store_unsigned_integer (buf
, 4, sp
);
1743 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1745 /* ...and fake a frame pointer. */
1746 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1748 /* MarkK wrote: This "+ 8" is all over the place:
1749 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1750 i386_dummy_id). It's there, since all frame unwinders for
1751 a given target have to agree (within a certain margin) on the
1752 definition of the stack address of a frame. Otherwise frame id
1753 comparison might not work correctly. Since DWARF2/GCC uses the
1754 stack address *before* the function call as a frame's CFA. On
1755 the i386, when %ebp is used as a frame pointer, the offset
1756 between the contents %ebp and the CFA as defined by GCC. */
1760 /* These registers are used for returning integers (and on some
1761 targets also for returning `struct' and `union' values when their
1762 size and alignment match an integer type). */
1763 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1764 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1766 /* Read, for architecture GDBARCH, a function return value of TYPE
1767 from REGCACHE, and copy that into VALBUF. */
1770 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1771 struct regcache
*regcache
, gdb_byte
*valbuf
)
1773 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1774 int len
= TYPE_LENGTH (type
);
1775 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1777 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1779 if (tdep
->st0_regnum
< 0)
1781 warning (_("Cannot find floating-point return value."));
1782 memset (valbuf
, 0, len
);
1786 /* Floating-point return values can be found in %st(0). Convert
1787 its contents to the desired type. This is probably not
1788 exactly how it would happen on the target itself, but it is
1789 the best we can do. */
1790 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1791 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1795 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1796 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1798 if (len
<= low_size
)
1800 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1801 memcpy (valbuf
, buf
, len
);
1803 else if (len
<= (low_size
+ high_size
))
1805 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1806 memcpy (valbuf
, buf
, low_size
);
1807 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1808 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1811 internal_error (__FILE__
, __LINE__
,
1812 _("Cannot extract return value of %d bytes long."), len
);
1816 /* Write, for architecture GDBARCH, a function return value of TYPE
1817 from VALBUF into REGCACHE. */
1820 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1821 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1823 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1824 int len
= TYPE_LENGTH (type
);
1826 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1829 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1831 if (tdep
->st0_regnum
< 0)
1833 warning (_("Cannot set floating-point return value."));
1837 /* Returning floating-point values is a bit tricky. Apart from
1838 storing the return value in %st(0), we have to simulate the
1839 state of the FPU at function return point. */
1841 /* Convert the value found in VALBUF to the extended
1842 floating-point format used by the FPU. This is probably
1843 not exactly how it would happen on the target itself, but
1844 it is the best we can do. */
1845 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
1846 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
1848 /* Set the top of the floating-point register stack to 7. The
1849 actual value doesn't really matter, but 7 is what a normal
1850 function return would end up with if the program started out
1851 with a freshly initialized FPU. */
1852 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1854 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1856 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1857 the floating-point register stack to 7, the appropriate value
1858 for the tag word is 0x3fff. */
1859 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
1863 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1864 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1866 if (len
<= low_size
)
1867 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
1868 else if (len
<= (low_size
+ high_size
))
1870 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
1871 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
1872 len
- low_size
, valbuf
+ low_size
);
1875 internal_error (__FILE__
, __LINE__
,
1876 _("Cannot store return value of %d bytes long."), len
);
1881 /* This is the variable that is set with "set struct-convention", and
1882 its legitimate values. */
1883 static const char default_struct_convention
[] = "default";
1884 static const char pcc_struct_convention
[] = "pcc";
1885 static const char reg_struct_convention
[] = "reg";
1886 static const char *valid_conventions
[] =
1888 default_struct_convention
,
1889 pcc_struct_convention
,
1890 reg_struct_convention
,
1893 static const char *struct_convention
= default_struct_convention
;
1895 /* Return non-zero if TYPE, which is assumed to be a structure,
1896 a union type, or an array type, should be returned in registers
1897 for architecture GDBARCH. */
1900 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
1902 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1903 enum type_code code
= TYPE_CODE (type
);
1904 int len
= TYPE_LENGTH (type
);
1906 gdb_assert (code
== TYPE_CODE_STRUCT
1907 || code
== TYPE_CODE_UNION
1908 || code
== TYPE_CODE_ARRAY
);
1910 if (struct_convention
== pcc_struct_convention
1911 || (struct_convention
== default_struct_convention
1912 && tdep
->struct_return
== pcc_struct_return
))
1915 /* Structures consisting of a single `float', `double' or 'long
1916 double' member are returned in %st(0). */
1917 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
1919 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
1920 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1921 return (len
== 4 || len
== 8 || len
== 12);
1924 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
1927 /* Determine, for architecture GDBARCH, how a return value of TYPE
1928 should be returned. If it is supposed to be returned in registers,
1929 and READBUF is non-zero, read the appropriate value from REGCACHE,
1930 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1931 from WRITEBUF into REGCACHE. */
1933 static enum return_value_convention
1934 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1935 struct type
*type
, struct regcache
*regcache
,
1936 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1938 enum type_code code
= TYPE_CODE (type
);
1940 if (((code
== TYPE_CODE_STRUCT
1941 || code
== TYPE_CODE_UNION
1942 || code
== TYPE_CODE_ARRAY
)
1943 && !i386_reg_struct_return_p (gdbarch
, type
))
1944 /* 128-bit decimal float uses the struct return convention. */
1945 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
1947 /* The System V ABI says that:
1949 "A function that returns a structure or union also sets %eax
1950 to the value of the original address of the caller's area
1951 before it returns. Thus when the caller receives control
1952 again, the address of the returned object resides in register
1953 %eax and can be used to access the object."
1955 So the ABI guarantees that we can always find the return
1956 value just after the function has returned. */
1958 /* Note that the ABI doesn't mention functions returning arrays,
1959 which is something possible in certain languages such as Ada.
1960 In this case, the value is returned as if it was wrapped in
1961 a record, so the convention applied to records also applies
1968 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
1969 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1972 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
1975 /* This special case is for structures consisting of a single
1976 `float', `double' or 'long double' member. These structures are
1977 returned in %st(0). For these structures, we call ourselves
1978 recursively, changing TYPE into the type of the first member of
1979 the structure. Since that should work for all structures that
1980 have only one member, we don't bother to check the member's type
1982 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
1984 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
1985 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
1990 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
1992 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
1994 return RETURN_VALUE_REGISTER_CONVENTION
;
1998 /* Construct types for ISA-specific registers. */
2000 i386_eflags_type (struct gdbarch
*gdbarch
)
2002 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2004 if (!tdep
->i386_eflags_type
)
2008 type
= arch_flags_type (gdbarch
, "builtin_type_i386_eflags", 4);
2009 append_flags_type_flag (type
, 0, "CF");
2010 append_flags_type_flag (type
, 1, NULL
);
2011 append_flags_type_flag (type
, 2, "PF");
2012 append_flags_type_flag (type
, 4, "AF");
2013 append_flags_type_flag (type
, 6, "ZF");
2014 append_flags_type_flag (type
, 7, "SF");
2015 append_flags_type_flag (type
, 8, "TF");
2016 append_flags_type_flag (type
, 9, "IF");
2017 append_flags_type_flag (type
, 10, "DF");
2018 append_flags_type_flag (type
, 11, "OF");
2019 append_flags_type_flag (type
, 14, "NT");
2020 append_flags_type_flag (type
, 16, "RF");
2021 append_flags_type_flag (type
, 17, "VM");
2022 append_flags_type_flag (type
, 18, "AC");
2023 append_flags_type_flag (type
, 19, "VIF");
2024 append_flags_type_flag (type
, 20, "VIP");
2025 append_flags_type_flag (type
, 21, "ID");
2027 tdep
->i386_eflags_type
= type
;
2030 return tdep
->i386_eflags_type
;
2034 i386_mxcsr_type (struct gdbarch
*gdbarch
)
2036 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2038 if (!tdep
->i386_mxcsr_type
)
2042 type
= arch_flags_type (gdbarch
, "builtin_type_i386_mxcsr", 4);
2043 append_flags_type_flag (type
, 0, "IE");
2044 append_flags_type_flag (type
, 1, "DE");
2045 append_flags_type_flag (type
, 2, "ZE");
2046 append_flags_type_flag (type
, 3, "OE");
2047 append_flags_type_flag (type
, 4, "UE");
2048 append_flags_type_flag (type
, 5, "PE");
2049 append_flags_type_flag (type
, 6, "DAZ");
2050 append_flags_type_flag (type
, 7, "IM");
2051 append_flags_type_flag (type
, 8, "DM");
2052 append_flags_type_flag (type
, 9, "ZM");
2053 append_flags_type_flag (type
, 10, "OM");
2054 append_flags_type_flag (type
, 11, "UM");
2055 append_flags_type_flag (type
, 12, "PM");
2056 append_flags_type_flag (type
, 15, "FZ");
2058 tdep
->i386_mxcsr_type
= type
;
2061 return tdep
->i386_mxcsr_type
;
2065 i387_ext_type (struct gdbarch
*gdbarch
)
2067 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2069 if (!tdep
->i387_ext_type
)
2071 = arch_float_type (gdbarch
, -1, "builtin_type_i387_ext",
2072 floatformats_i387_ext
);
2074 return tdep
->i387_ext_type
;
2077 /* Construct vector type for MMX registers. */
2079 i386_mmx_type (struct gdbarch
*gdbarch
)
2081 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2083 if (!tdep
->i386_mmx_type
)
2085 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2087 /* The type we're building is this: */
2089 union __gdb_builtin_type_vec64i
2092 int32_t v2_int32
[2];
2093 int16_t v4_int16
[4];
2100 t
= arch_composite_type (gdbarch
,
2101 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2103 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2104 append_composite_type_field (t
, "v2_int32",
2105 init_vector_type (bt
->builtin_int32
, 2));
2106 append_composite_type_field (t
, "v4_int16",
2107 init_vector_type (bt
->builtin_int16
, 4));
2108 append_composite_type_field (t
, "v8_int8",
2109 init_vector_type (bt
->builtin_int8
, 8));
2111 TYPE_VECTOR (t
) = 1;
2112 TYPE_NAME (t
) = "builtin_type_vec64i";
2113 tdep
->i386_mmx_type
= t
;
2116 return tdep
->i386_mmx_type
;
2120 i386_sse_type (struct gdbarch
*gdbarch
)
2122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2124 if (!tdep
->i386_sse_type
)
2126 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2128 /* The type we're building is this: */
2130 union __gdb_builtin_type_vec128i
2133 int64_t v2_int64
[2];
2134 int32_t v4_int32
[4];
2135 int16_t v8_int16
[8];
2136 int8_t v16_int8
[16];
2137 double v2_double
[2];
2144 t
= arch_composite_type (gdbarch
,
2145 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION
);
2146 append_composite_type_field (t
, "v4_float",
2147 init_vector_type (bt
->builtin_float
, 4));
2148 append_composite_type_field (t
, "v2_double",
2149 init_vector_type (bt
->builtin_double
, 2));
2150 append_composite_type_field (t
, "v16_int8",
2151 init_vector_type (bt
->builtin_int8
, 16));
2152 append_composite_type_field (t
, "v8_int16",
2153 init_vector_type (bt
->builtin_int16
, 8));
2154 append_composite_type_field (t
, "v4_int32",
2155 init_vector_type (bt
->builtin_int32
, 4));
2156 append_composite_type_field (t
, "v2_int64",
2157 init_vector_type (bt
->builtin_int64
, 2));
2158 append_composite_type_field (t
, "uint128", bt
->builtin_int128
);
2160 TYPE_VECTOR (t
) = 1;
2161 TYPE_NAME (t
) = "builtin_type_vec128i";
2162 tdep
->i386_sse_type
= t
;
2165 return tdep
->i386_sse_type
;
2168 /* Return the GDB type object for the "standard" data type of data in
2169 register REGNUM. Perhaps %esi and %edi should go here, but
2170 potentially they could be used for things other than address. */
2172 static struct type
*
2173 i386_register_type (struct gdbarch
*gdbarch
, int regnum
)
2175 if (regnum
== I386_EIP_REGNUM
)
2176 return builtin_type (gdbarch
)->builtin_func_ptr
;
2178 if (regnum
== I386_EFLAGS_REGNUM
)
2179 return i386_eflags_type (gdbarch
);
2181 if (regnum
== I386_EBP_REGNUM
|| regnum
== I386_ESP_REGNUM
)
2182 return builtin_type (gdbarch
)->builtin_data_ptr
;
2184 if (i386_fp_regnum_p (gdbarch
, regnum
))
2185 return i387_ext_type (gdbarch
);
2187 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2188 return i386_mmx_type (gdbarch
);
2190 if (i386_sse_regnum_p (gdbarch
, regnum
))
2191 return i386_sse_type (gdbarch
);
2193 if (regnum
== I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch
)))
2194 return i386_mxcsr_type (gdbarch
);
2196 return builtin_type (gdbarch
)->builtin_int
;
2199 /* Map a cooked register onto a raw register or memory. For the i386,
2200 the MMX registers need to be mapped onto floating point registers. */
2203 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2205 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2210 mmxreg
= regnum
- tdep
->mm0_regnum
;
2211 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2212 tos
= (fstat
>> 11) & 0x7;
2213 fpreg
= (mmxreg
+ tos
) % 8;
2215 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2219 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2220 int regnum
, gdb_byte
*buf
)
2222 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2224 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2225 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2227 /* Extract (always little endian). */
2228 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2229 memcpy (buf
, mmx_buf
, register_size (gdbarch
, regnum
));
2232 regcache_raw_read (regcache
, regnum
, buf
);
2236 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2237 int regnum
, const gdb_byte
*buf
)
2239 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2241 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2242 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2245 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2246 /* ... Modify ... (always little endian). */
2247 memcpy (mmx_buf
, buf
, register_size (gdbarch
, regnum
));
2249 regcache_raw_write (regcache
, fpnum
, mmx_buf
);
2252 regcache_raw_write (regcache
, regnum
, buf
);
2256 /* Return the register number of the register allocated by GCC after
2257 REGNUM, or -1 if there is no such register. */
2260 i386_next_regnum (int regnum
)
2262 /* GCC allocates the registers in the order:
2264 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2266 Since storing a variable in %esp doesn't make any sense we return
2267 -1 for %ebp and for %esp itself. */
2268 static int next_regnum
[] =
2270 I386_EDX_REGNUM
, /* Slot for %eax. */
2271 I386_EBX_REGNUM
, /* Slot for %ecx. */
2272 I386_ECX_REGNUM
, /* Slot for %edx. */
2273 I386_ESI_REGNUM
, /* Slot for %ebx. */
2274 -1, -1, /* Slots for %esp and %ebp. */
2275 I386_EDI_REGNUM
, /* Slot for %esi. */
2276 I386_EBP_REGNUM
/* Slot for %edi. */
2279 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2280 return next_regnum
[regnum
];
2285 /* Return nonzero if a value of type TYPE stored in register REGNUM
2286 needs any special handling. */
2289 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2291 int len
= TYPE_LENGTH (type
);
2293 /* Values may be spread across multiple registers. Most debugging
2294 formats aren't expressive enough to specify the locations, so
2295 some heuristics is involved. Right now we only handle types that
2296 have a length that is a multiple of the word size, since GCC
2297 doesn't seem to put any other types into registers. */
2298 if (len
> 4 && len
% 4 == 0)
2300 int last_regnum
= regnum
;
2304 last_regnum
= i386_next_regnum (last_regnum
);
2308 if (last_regnum
!= -1)
2312 return i387_convert_register_p (gdbarch
, regnum
, type
);
2315 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2316 return its contents in TO. */
2319 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2320 struct type
*type
, gdb_byte
*to
)
2322 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2323 int len
= TYPE_LENGTH (type
);
2325 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2326 available in FRAME (i.e. if it wasn't saved)? */
2328 if (i386_fp_regnum_p (gdbarch
, regnum
))
2330 i387_register_to_value (frame
, regnum
, type
, to
);
2334 /* Read a value spread across multiple registers. */
2336 gdb_assert (len
> 4 && len
% 4 == 0);
2340 gdb_assert (regnum
!= -1);
2341 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2343 get_frame_register (frame
, regnum
, to
);
2344 regnum
= i386_next_regnum (regnum
);
2350 /* Write the contents FROM of a value of type TYPE into register
2351 REGNUM in frame FRAME. */
2354 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2355 struct type
*type
, const gdb_byte
*from
)
2357 int len
= TYPE_LENGTH (type
);
2359 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2361 i387_value_to_register (frame
, regnum
, type
, from
);
2365 /* Write a value spread across multiple registers. */
2367 gdb_assert (len
> 4 && len
% 4 == 0);
2371 gdb_assert (regnum
!= -1);
2372 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2374 put_frame_register (frame
, regnum
, from
);
2375 regnum
= i386_next_regnum (regnum
);
2381 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2382 in the general-purpose register set REGSET to register cache
2383 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2386 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2387 int regnum
, const void *gregs
, size_t len
)
2389 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2390 const gdb_byte
*regs
= gregs
;
2393 gdb_assert (len
== tdep
->sizeof_gregset
);
2395 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2397 if ((regnum
== i
|| regnum
== -1)
2398 && tdep
->gregset_reg_offset
[i
] != -1)
2399 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2403 /* Collect register REGNUM from the register cache REGCACHE and store
2404 it in the buffer specified by GREGS and LEN as described by the
2405 general-purpose register set REGSET. If REGNUM is -1, do this for
2406 all registers in REGSET. */
2409 i386_collect_gregset (const struct regset
*regset
,
2410 const struct regcache
*regcache
,
2411 int regnum
, void *gregs
, size_t len
)
2413 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2414 gdb_byte
*regs
= gregs
;
2417 gdb_assert (len
== tdep
->sizeof_gregset
);
2419 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2421 if ((regnum
== i
|| regnum
== -1)
2422 && tdep
->gregset_reg_offset
[i
] != -1)
2423 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2427 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2428 in the floating-point register set REGSET to register cache
2429 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2432 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2433 int regnum
, const void *fpregs
, size_t len
)
2435 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2437 if (len
== I387_SIZEOF_FXSAVE
)
2439 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2443 gdb_assert (len
== tdep
->sizeof_fpregset
);
2444 i387_supply_fsave (regcache
, regnum
, fpregs
);
2447 /* Collect register REGNUM from the register cache REGCACHE and store
2448 it in the buffer specified by FPREGS and LEN as described by the
2449 floating-point register set REGSET. If REGNUM is -1, do this for
2450 all registers in REGSET. */
2453 i386_collect_fpregset (const struct regset
*regset
,
2454 const struct regcache
*regcache
,
2455 int regnum
, void *fpregs
, size_t len
)
2457 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2459 if (len
== I387_SIZEOF_FXSAVE
)
2461 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2465 gdb_assert (len
== tdep
->sizeof_fpregset
);
2466 i387_collect_fsave (regcache
, regnum
, fpregs
);
2469 /* Return the appropriate register set for the core section identified
2470 by SECT_NAME and SECT_SIZE. */
2472 const struct regset
*
2473 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2474 const char *sect_name
, size_t sect_size
)
2476 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2478 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2480 if (tdep
->gregset
== NULL
)
2481 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2482 i386_collect_gregset
);
2483 return tdep
->gregset
;
2486 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2487 || (strcmp (sect_name
, ".reg-xfp") == 0
2488 && sect_size
== I387_SIZEOF_FXSAVE
))
2490 if (tdep
->fpregset
== NULL
)
2491 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2492 i386_collect_fpregset
);
2493 return tdep
->fpregset
;
2500 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2503 i386_pe_skip_trampoline_code (CORE_ADDR pc
, char *name
)
2505 if (pc
&& read_memory_unsigned_integer (pc
, 2) == 0x25ff) /* jmp *(dest) */
2507 unsigned long indirect
= read_memory_unsigned_integer (pc
+ 2, 4);
2508 struct minimal_symbol
*indsym
=
2509 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2510 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2514 if (strncmp (symname
, "__imp_", 6) == 0
2515 || strncmp (symname
, "_imp_", 5) == 0)
2516 return name
? 1 : read_memory_unsigned_integer (indirect
, 4);
2519 return 0; /* Not a trampoline. */
2523 /* Return whether the THIS_FRAME corresponds to a sigtramp
2527 i386_sigtramp_p (struct frame_info
*this_frame
)
2529 CORE_ADDR pc
= get_frame_pc (this_frame
);
2532 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2533 return (name
&& strcmp ("_sigtramp", name
) == 0);
2537 /* We have two flavours of disassembly. The machinery on this page
2538 deals with switching between those. */
2541 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2543 gdb_assert (disassembly_flavor
== att_flavor
2544 || disassembly_flavor
== intel_flavor
);
2546 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2547 constified, cast to prevent a compiler warning. */
2548 info
->disassembler_options
= (char *) disassembly_flavor
;
2550 return print_insn_i386 (pc
, info
);
2554 /* There are a few i386 architecture variants that differ only
2555 slightly from the generic i386 target. For now, we don't give them
2556 their own source file, but include them here. As a consequence,
2557 they'll always be included. */
2559 /* System V Release 4 (SVR4). */
2561 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2565 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2567 CORE_ADDR pc
= get_frame_pc (this_frame
);
2570 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2571 currently unknown. */
2572 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2573 return (name
&& (strcmp ("_sigreturn", name
) == 0
2574 || strcmp ("_sigacthandler", name
) == 0
2575 || strcmp ("sigvechandler", name
) == 0));
2578 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2579 address of the associated sigcontext (ucontext) structure. */
2582 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2587 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2588 sp
= extract_unsigned_integer (buf
, 4);
2590 return read_memory_unsigned_integer (sp
+ 8, 4);
2597 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2599 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2600 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2603 /* System V Release 4 (SVR4). */
2606 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2608 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2610 /* System V Release 4 uses ELF. */
2611 i386_elf_init_abi (info
, gdbarch
);
2613 /* System V Release 4 has shared libraries. */
2614 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2616 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2617 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2618 tdep
->sc_pc_offset
= 36 + 14 * 4;
2619 tdep
->sc_sp_offset
= 36 + 17 * 4;
2621 tdep
->jb_pc_offset
= 20;
2627 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2629 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2631 /* DJGPP doesn't have any special frames for signal handlers. */
2632 tdep
->sigtramp_p
= NULL
;
2634 tdep
->jb_pc_offset
= 36;
2636 /* DJGPP does not support the SSE registers. */
2637 tdep
->num_xmm_regs
= 0;
2638 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I386_NUM_FREGS
);
2640 /* Native compiler is GCC, which uses the SVR4 register numbering
2641 even in COFF and STABS. See the comment in i386_gdbarch_init,
2642 before the calls to set_gdbarch_stab_reg_to_regnum and
2643 set_gdbarch_sdb_reg_to_regnum. */
2644 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2645 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2649 /* i386 register groups. In addition to the normal groups, add "mmx"
2652 static struct reggroup
*i386_sse_reggroup
;
2653 static struct reggroup
*i386_mmx_reggroup
;
2656 i386_init_reggroups (void)
2658 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2659 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2663 i386_add_reggroups (struct gdbarch
*gdbarch
)
2665 reggroup_add (gdbarch
, i386_sse_reggroup
);
2666 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2667 reggroup_add (gdbarch
, general_reggroup
);
2668 reggroup_add (gdbarch
, float_reggroup
);
2669 reggroup_add (gdbarch
, all_reggroup
);
2670 reggroup_add (gdbarch
, save_reggroup
);
2671 reggroup_add (gdbarch
, restore_reggroup
);
2672 reggroup_add (gdbarch
, vector_reggroup
);
2673 reggroup_add (gdbarch
, system_reggroup
);
2677 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2678 struct reggroup
*group
)
2680 int sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2681 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2682 int fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2683 || i386_fpc_regnum_p (gdbarch
, regnum
));
2684 int mmx_regnum_p
= (i386_mmx_regnum_p (gdbarch
, regnum
));
2686 if (group
== i386_mmx_reggroup
)
2687 return mmx_regnum_p
;
2688 if (group
== i386_sse_reggroup
)
2689 return sse_regnum_p
;
2690 if (group
== vector_reggroup
)
2691 return (mmx_regnum_p
|| sse_regnum_p
);
2692 if (group
== float_reggroup
)
2694 if (group
== general_reggroup
)
2695 return (!fp_regnum_p
&& !mmx_regnum_p
&& !sse_regnum_p
);
2697 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2701 /* Get the ARGIth function argument for the current function. */
2704 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2707 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2708 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4);
2712 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2714 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2716 /* On i386, breakpoint is exactly 1 byte long, so we just
2717 adjust the PC in the regcache. */
2719 regcache_write_pc (regcache
, current_pc
);
2723 #define PREFIX_REPZ 0x01
2724 #define PREFIX_REPNZ 0x02
2725 #define PREFIX_LOCK 0x04
2726 #define PREFIX_DATA 0x08
2727 #define PREFIX_ADDR 0x10
2737 /* i386 arith/logic operations */
2750 struct i386_record_s
2752 struct regcache
*regcache
;
2758 uint8_t mod
, reg
, rm
;
2762 /* Parse "modrm" part in current memory address that irp->addr point to
2763 Return -1 if something wrong. */
2766 i386_record_modrm (struct i386_record_s
*irp
)
2768 struct gdbarch
*gdbarch
= get_regcache_arch (irp
->regcache
);
2770 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2773 printf_unfiltered (_("Process record: error reading memory at "
2774 "addr %s len = 1.\n"),
2775 paddress (gdbarch
, irp
->addr
));
2779 irp
->mod
= (irp
->modrm
>> 6) & 3;
2780 irp
->reg
= (irp
->modrm
>> 3) & 7;
2781 irp
->rm
= irp
->modrm
& 7;
2786 /* Get the memory address that current instruction write to and set it to
2787 the argument "addr".
2788 Return -1 if something wrong. */
2791 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint32_t * addr
)
2793 struct gdbarch
*gdbarch
= get_regcache_arch (irp
->regcache
);
2805 uint8_t base
= irp
->rm
;
2810 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2813 printf_unfiltered (_("Process record: error reading memory "
2814 "at addr %s len = 1.\n"),
2815 paddress (gdbarch
, irp
->addr
));
2819 scale
= (tmpu8
>> 6) & 3;
2820 index
= ((tmpu8
>> 3) & 7);
2827 if ((base
& 7) == 5)
2830 if (target_read_memory (irp
->addr
, (gdb_byte
*) addr
, 4))
2833 printf_unfiltered (_("Process record: error reading "
2834 "memory at addr %s len = 4.\n"),
2835 paddress (gdbarch
, irp
->addr
));
2846 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2849 printf_unfiltered (_("Process record: error reading memory "
2850 "at addr %s len = 1.\n"),
2851 paddress (gdbarch
, irp
->addr
));
2855 *addr
= (int8_t) tmpu8
;
2858 if (target_read_memory (irp
->addr
, (gdb_byte
*) addr
, 4))
2861 printf_unfiltered (_("Process record: error reading memory "
2862 "at addr %s len = 4.\n"),
2863 paddress (gdbarch
, irp
->addr
));
2872 regcache_raw_read (irp
->regcache
, base
, (gdb_byte
*) & tmpu32
);
2876 /* XXX: index == 4 is always invalid */
2877 if (havesib
&& (index
!= 4 || scale
!= 0))
2879 regcache_raw_read (irp
->regcache
, index
, (gdb_byte
*) & tmpu32
);
2880 *addr
+= tmpu32
<< scale
;
2891 if (target_read_memory
2892 (irp
->addr
, (gdb_byte
*) & tmpu16
, 2))
2895 printf_unfiltered (_("Process record: error reading "
2896 "memory at addr %s len = 2.\n"),
2897 paddress (gdbarch
, irp
->addr
));
2901 *addr
= (int16_t) tmpu16
;
2911 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2914 printf_unfiltered (_("Process record: error reading memory "
2915 "at addr %s len = 1.\n"),
2916 paddress (gdbarch
, irp
->addr
));
2920 *addr
= (int8_t) tmpu8
;
2923 if (target_read_memory (irp
->addr
, (gdb_byte
*) & tmpu16
, 2))
2926 printf_unfiltered (_("Process record: error reading memory "
2927 "at addr %s len = 2.\n"),
2928 paddress (gdbarch
, irp
->addr
));
2932 *addr
= (int16_t) tmpu16
;
2939 regcache_raw_read (irp
->regcache
, I386_EBX_REGNUM
,
2940 (gdb_byte
*) & tmpu32
);
2942 regcache_raw_read (irp
->regcache
, I386_ESI_REGNUM
,
2943 (gdb_byte
*) & tmpu32
);
2947 regcache_raw_read (irp
->regcache
, I386_EBX_REGNUM
,
2948 (gdb_byte
*) & tmpu32
);
2950 regcache_raw_read (irp
->regcache
, I386_EDI_REGNUM
,
2951 (gdb_byte
*) & tmpu32
);
2955 regcache_raw_read (irp
->regcache
, I386_EBP_REGNUM
,
2956 (gdb_byte
*) & tmpu32
);
2958 regcache_raw_read (irp
->regcache
, I386_ESI_REGNUM
,
2959 (gdb_byte
*) & tmpu32
);
2963 regcache_raw_read (irp
->regcache
, I386_EBP_REGNUM
,
2964 (gdb_byte
*) & tmpu32
);
2966 regcache_raw_read (irp
->regcache
, I386_EDI_REGNUM
,
2967 (gdb_byte
*) & tmpu32
);
2971 regcache_raw_read (irp
->regcache
, I386_ESI_REGNUM
,
2972 (gdb_byte
*) & tmpu32
);
2976 regcache_raw_read (irp
->regcache
, I386_EDI_REGNUM
,
2977 (gdb_byte
*) & tmpu32
);
2981 regcache_raw_read (irp
->regcache
, I386_EBP_REGNUM
,
2982 (gdb_byte
*) & tmpu32
);
2986 regcache_raw_read (irp
->regcache
, I386_EBX_REGNUM
,
2987 (gdb_byte
*) & tmpu32
);
2998 /* Record the value of the memory that willbe changed in current instruction
2999 to "record_arch_list".
3000 Return -1 if something wrong. */
3003 i386_record_lea_modrm (struct i386_record_s
*irp
)
3005 struct gdbarch
*gdbarch
= get_regcache_arch (irp
->regcache
);
3011 printf_unfiltered (_("Process record ignores the memory change "
3012 "of instruction at address %s because it "
3013 "can't get the value of the segment register.\n"),
3014 paddress (gdbarch
, irp
->addr
));
3018 if (i386_record_lea_modrm_addr (irp
, &addr
))
3021 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3027 /* Parse the current instruction and record the values of the registers and
3028 memory that will be changed in current instruction to "record_arch_list".
3029 Return -1 if something wrong. */
3032 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3040 struct i386_record_s ir
;
3042 memset (&ir
, 0, sizeof (struct i386_record_s
));
3043 ir
.regcache
= regcache
;
3048 if (record_debug
> 1)
3049 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3051 paddress (gdbarch
, ir
.addr
));
3056 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3059 printf_unfiltered (_("Process record: error reading memory at "
3060 "addr %s len = 1.\n"),
3061 paddress (gdbarch
, ir
.addr
));
3068 prefixes
|= PREFIX_REPZ
;
3071 prefixes
|= PREFIX_REPNZ
;
3074 prefixes
|= PREFIX_LOCK
;
3077 ir
.override
= I386_CS_REGNUM
;
3080 ir
.override
= I386_SS_REGNUM
;
3083 ir
.override
= I386_DS_REGNUM
;
3086 ir
.override
= I386_ES_REGNUM
;
3089 ir
.override
= I386_FS_REGNUM
;
3092 ir
.override
= I386_GS_REGNUM
;
3095 prefixes
|= PREFIX_DATA
;
3098 prefixes
|= PREFIX_ADDR
;
3106 if (prefixes
& PREFIX_DATA
)
3108 if (prefixes
& PREFIX_ADDR
)
3111 /* now check op code */
3112 opcode
= (uint32_t) tmpu8
;
3117 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3120 printf_unfiltered (_("Process record: error reading memory at "
3121 "addr %s len = 1.\n"),
3122 paddress (gdbarch
, ir
.addr
));
3126 opcode
= (uint16_t) tmpu8
| 0x0f00;
3179 if (((opcode
>> 3) & 7) != OP_CMPL
)
3181 if ((opcode
& 1) == 0)
3184 ir
.ot
= ir
.dflag
+ OT_WORD
;
3186 switch ((opcode
>> 1) & 3)
3190 if (i386_record_modrm (&ir
))
3194 if (i386_record_lea_modrm (&ir
))
3199 if (ir
.ot
== OT_BYTE
)
3201 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3207 if (i386_record_modrm (&ir
))
3209 if (ir
.ot
== OT_BYTE
)
3211 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3216 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3221 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3230 if (i386_record_modrm (&ir
))
3233 if (ir
.reg
!= OP_CMPL
)
3235 if ((opcode
& 1) == 0)
3238 ir
.ot
= ir
.dflag
+ OT_WORD
;
3242 if (i386_record_lea_modrm (&ir
))
3247 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3251 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3273 if (record_arch_list_add_reg (ir
.regcache
, opcode
& 7))
3275 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3282 if ((opcode
& 1) == 0)
3285 ir
.ot
= ir
.dflag
+ OT_WORD
;
3286 if (i386_record_modrm (&ir
))
3293 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3300 if (i386_record_lea_modrm (&ir
))
3305 if (ir
.ot
== OT_BYTE
)
3307 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3315 if (i386_record_lea_modrm (&ir
))
3320 if (ir
.ot
== OT_BYTE
)
3322 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3325 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3336 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3338 if (ir
.ot
!= OT_BYTE
)
3340 if (record_arch_list_add_reg (ir
.regcache
, I386_EDX_REGNUM
))
3343 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3348 opcode
= opcode
<< 8 | ir
.modrm
;
3358 if ((opcode
& 1) == 0)
3361 ir
.ot
= ir
.dflag
+ OT_WORD
;
3362 if (i386_record_modrm (&ir
))
3364 if (ir
.reg
>= 2 && opcode
== 0xfe)
3367 opcode
= opcode
<< 8 | ir
.modrm
;
3379 if (i386_record_lea_modrm (&ir
))
3384 if (ir
.ot
== OT_BYTE
)
3386 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3389 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3396 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3398 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
3399 (gdb_byte
*) & tmpu32
);
3400 if (record_arch_list_add_mem
3401 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 1)), (1 << (ir
.dflag
+ 1))))
3406 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3408 if (record_arch_list_add_reg (ir
.regcache
, I386_CS_REGNUM
))
3410 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
3411 (gdb_byte
*) & tmpu32
);
3412 if (record_arch_list_add_mem
3413 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 2)), (1 << (ir
.dflag
+ 2))))
3423 opcode
= opcode
<< 8 | ir
.modrm
;
3434 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3440 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3446 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3448 if (record_arch_list_add_reg (ir
.regcache
, I386_EDX_REGNUM
))
3456 ir
.ot
= ir
.dflag
+ OT_WORD
;
3457 if (i386_record_modrm (&ir
))
3459 if (ir
.ot
== OT_BYTE
)
3461 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3463 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3470 if ((opcode
& 1) == 0)
3473 ir
.ot
= ir
.dflag
+ OT_WORD
;
3474 if (i386_record_modrm (&ir
))
3478 if (ir
.ot
== OT_BYTE
)
3480 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3482 if (ir
.ot
== OT_BYTE
)
3484 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3489 if (i386_record_lea_modrm (&ir
))
3491 if (ir
.ot
== OT_BYTE
)
3493 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3496 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3503 if ((opcode
& 1) == 0)
3506 ir
.ot
= ir
.dflag
+ OT_WORD
;
3507 if (i386_record_modrm (&ir
))
3511 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3513 if (ir
.ot
== OT_BYTE
)
3515 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3520 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3522 if (i386_record_lea_modrm (&ir
))
3525 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3531 if (i386_record_modrm (&ir
))
3536 opcode
= opcode
<< 8 | ir
.modrm
;
3539 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3541 if (record_arch_list_add_reg (ir
.regcache
, I386_EDX_REGNUM
))
3543 if (i386_record_lea_modrm (&ir
))
3545 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3572 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3574 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
3575 (gdb_byte
*) & tmpu32
);
3576 if (record_arch_list_add_mem
3577 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 1)), (1 << (ir
.dflag
+ 1))))
3590 ir
.ot
= ir
.dflag
+ OT_WORD
;
3591 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3593 if (ir
.ot
== OT_BYTE
)
3595 if (record_arch_list_add_reg (ir
.regcache
, opcode
& 0x7))
3601 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3603 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
3604 (gdb_byte
*) & tmpu32
);
3605 if (record_arch_list_add_mem
3606 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 4)), (1 << (ir
.dflag
+ 4))))
3612 for (tmpu8
= I386_EAX_REGNUM
; tmpu8
<= I386_EDI_REGNUM
; tmpu8
++)
3614 if (record_arch_list_add_reg (ir
.regcache
, tmpu8
))
3621 ir
.ot
= ir
.dflag
+ OT_WORD
;
3622 if (i386_record_modrm (&ir
))
3626 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3631 if (i386_record_lea_modrm (&ir
))
3634 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3640 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3642 if (record_arch_list_add_reg (ir
.regcache
, I386_EBP_REGNUM
))
3644 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
3645 (gdb_byte
*) & tmpu32
);
3646 if (record_arch_list_add_mem
3647 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 1)), (1 << (ir
.dflag
+ 1))))
3653 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3655 if (record_arch_list_add_reg (ir
.regcache
, I386_EBP_REGNUM
))
3661 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3663 if (record_arch_list_add_reg (ir
.regcache
, I386_ES_REGNUM
))
3669 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3671 if (record_arch_list_add_reg (ir
.regcache
, I386_SS_REGNUM
))
3677 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3679 if (record_arch_list_add_reg (ir
.regcache
, I386_DS_REGNUM
))
3685 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3687 if (record_arch_list_add_reg (ir
.regcache
, I386_FS_REGNUM
))
3693 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
3695 if (record_arch_list_add_reg (ir
.regcache
, I386_GS_REGNUM
))
3704 if ((opcode
& 1) == 0)
3707 ir
.ot
= ir
.dflag
+ OT_WORD
;
3709 if (i386_record_modrm (&ir
))
3714 if (i386_record_lea_modrm (&ir
))
3719 if (ir
.ot
== OT_BYTE
)
3721 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3724 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3730 if ((opcode
& 1) == 0)
3733 ir
.ot
= ir
.dflag
+ OT_WORD
;
3735 if (i386_record_modrm (&ir
))
3738 if (ir
.ot
== OT_BYTE
)
3740 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3743 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3749 if (i386_record_modrm (&ir
))
3755 tmpu8
= I386_ES_REGNUM
;
3758 tmpu8
= I386_SS_REGNUM
;
3761 tmpu8
= I386_DS_REGNUM
;
3764 tmpu8
= I386_FS_REGNUM
;
3767 tmpu8
= I386_GS_REGNUM
;
3771 opcode
= opcode
<< 8 | ir
.modrm
;
3775 if (record_arch_list_add_reg (ir
.regcache
, tmpu8
))
3778 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3784 if (i386_record_modrm (&ir
))
3789 opcode
= opcode
<< 8 | ir
.modrm
;
3795 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3801 if (i386_record_lea_modrm (&ir
))
3805 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
3817 if (i386_record_modrm (&ir
))
3819 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3825 if (i386_record_modrm (&ir
))
3830 opcode
= opcode
<< 8 | ir
.modrm
;
3835 if (ir
.ot
== OT_BYTE
)
3837 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3846 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3859 printf_unfiltered (_("Process record ignores the memory change "
3860 "of instruction at address %s because "
3861 "it can't get the value of the segment "
3863 paddress (gdbarch
, ir
.addr
));
3867 if ((opcode
& 1) == 0)
3870 ir
.ot
= ir
.dflag
+ OT_WORD
;
3873 if (target_read_memory
3874 (ir
.addr
, (gdb_byte
*) & addr
, 4))
3877 printf_unfiltered (_("Process record: error reading "
3878 "memory at addr %s len = 4.\n"),
3879 paddress (gdbarch
, ir
.addr
));
3886 if (target_read_memory
3887 (ir
.addr
, (gdb_byte
*) & tmpu16
, 4))
3890 printf_unfiltered (_("Process record: error reading "
3891 "memory at addr %s len = 4.\n"),
3892 paddress (gdbarch
, ir
.addr
));
3898 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
3913 if (record_arch_list_add_reg (ir
.regcache
, (opcode
& 0x7) & 0x3))
3926 if (record_arch_list_add_reg (ir
.regcache
, opcode
& 0x7))
3938 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
3940 if (record_arch_list_add_reg (ir
.regcache
, opcode
& 0x7))
3947 if ((opcode
& 1) == 0)
3950 ir
.ot
= ir
.dflag
+ OT_WORD
;
3952 if (i386_record_modrm (&ir
))
3957 if (ir
.ot
== OT_BYTE
)
3959 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
3964 if (i386_record_lea_modrm (&ir
))
3968 if (ir
.ot
== OT_BYTE
)
3970 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
3984 if (i386_record_modrm (&ir
))
3992 opcode
= opcode
<< 8 | ir
.modrm
;
4000 tmpu8
= I386_ES_REGNUM
;
4004 tmpu8
= I386_DS_REGNUM
;
4008 tmpu8
= I386_SS_REGNUM
;
4012 tmpu8
= I386_FS_REGNUM
;
4016 tmpu8
= I386_GS_REGNUM
;
4019 if (record_arch_list_add_reg (ir
.regcache
, tmpu8
))
4022 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
4033 if ((opcode
& 1) == 0)
4036 ir
.ot
= ir
.dflag
+ OT_WORD
;
4038 if (i386_record_modrm (&ir
))
4041 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4043 if (i386_record_lea_modrm (&ir
))
4048 if (ir
.ot
== OT_BYTE
)
4050 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4054 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4062 if (i386_record_modrm (&ir
))
4066 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4071 if (i386_record_lea_modrm (&ir
))
4077 /* It just record the memory change of instrcution. */
4086 if (i386_record_modrm (&ir
))
4088 ir
.reg
|= ((opcode
& 7) << 3);
4094 if (i386_record_lea_modrm_addr (&ir
, &addr
))
4151 switch (ir
.reg
>> 4)
4154 if (record_arch_list_add_mem (addr
, 4))
4158 if (record_arch_list_add_mem (addr
, 8))
4163 if (record_arch_list_add_mem (addr
, 2))
4169 switch (ir
.reg
>> 4)
4173 if (record_arch_list_add_mem (addr
, 4))
4177 if (record_arch_list_add_mem (addr
, 8))
4182 if (record_arch_list_add_mem (addr
, 2))
4199 if (record_arch_list_add_mem (addr
, 28))
4204 if (record_arch_list_add_mem (addr
, 14))
4210 if (record_arch_list_add_mem (addr
, 2))
4215 if (record_arch_list_add_mem (addr
, 10))
4221 if (record_arch_list_add_mem (addr
, 28))
4227 if (record_arch_list_add_mem (addr
, 14))
4231 if (record_arch_list_add_mem (addr
, 80))
4235 if (record_arch_list_add_mem (addr
, 8))
4240 opcode
= opcode
<< 8 | ir
.modrm
;
4260 if ((opcode
& 1) == 0)
4263 ir
.ot
= ir
.dflag
+ OT_WORD
;
4264 if (opcode
== 0xa4 || opcode
== 0xa5)
4266 if (record_arch_list_add_reg (ir
.regcache
, I386_ESI_REGNUM
))
4269 if (record_arch_list_add_reg (ir
.regcache
, I386_EDI_REGNUM
))
4272 regcache_raw_read (ir
.regcache
, I386_EDI_REGNUM
,
4273 (gdb_byte
*) & addr
);
4277 /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */
4279 printf_unfiltered (_("Process record ignores the memory change "
4280 "of instruction at address %s because "
4281 "it can't get the value of the segment "
4283 paddress (gdbarch
, ir
.addr
));
4286 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4290 regcache_raw_read (ir
.regcache
, I386_ECX_REGNUM
,
4291 (gdb_byte
*) & count
);
4295 regcache_raw_read (ir
.regcache
, I386_EFLAGS_REGNUM
,
4296 (gdb_byte
*) & tmpu32
);
4297 if ((tmpu32
>> 10) & 0x1)
4298 addr
-= (count
- 1) * (1 << ir
.ot
);
4302 if (record_arch_list_add_mem (addr
, count
* (1 << ir
.ot
)))
4306 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4313 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4323 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4325 if (record_arch_list_add_reg (ir
.regcache
, I386_ESI_REGNUM
))
4327 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4329 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4337 if (record_arch_list_add_reg (ir
.regcache
, I386_ESI_REGNUM
))
4339 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4341 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4349 if (record_arch_list_add_reg (ir
.regcache
, I386_EDI_REGNUM
))
4351 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4353 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4356 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4363 if (record_arch_list_add_reg (ir
.regcache
, I386_EDI_REGNUM
))
4365 if (record_arch_list_add_reg (ir
.regcache
, I386_ESI_REGNUM
))
4367 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4369 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4372 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4381 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4400 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4402 if (record_arch_list_add_reg (ir
.regcache
, I386_CS_REGNUM
))
4408 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4410 if (record_arch_list_add_reg (ir
.regcache
, I386_CS_REGNUM
))
4412 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4418 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4420 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
4421 (gdb_byte
*) & tmpu32
);
4422 if (record_arch_list_add_mem
4423 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 1)), (1 << (ir
.dflag
+ 1))))
4429 if (record_arch_list_add_reg (ir
.regcache
, I386_CS_REGNUM
))
4431 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4433 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
4434 (gdb_byte
*) & tmpu32
);
4435 if (record_arch_list_add_mem
4436 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 2)), (1 << (ir
.dflag
+ 2))))
4500 if (i386_record_modrm (&ir
))
4504 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
& 0x3))
4509 if (i386_record_lea_modrm (&ir
))
4531 if (i386_record_modrm (&ir
))
4533 if (ir
.dflag
== OT_BYTE
)
4535 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
& 0x3))
4542 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4544 regcache_raw_read (ir
.regcache
, I386_ESP_REGNUM
,
4545 (gdb_byte
*) & tmpu32
);
4546 if (record_arch_list_add_mem
4547 ((CORE_ADDR
) tmpu32
- (1 << (ir
.dflag
+ 1)), (1 << (ir
.dflag
+ 1))))
4553 if (record_arch_list_add_reg (ir
.regcache
, I386_ESP_REGNUM
))
4555 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4571 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4577 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4581 /* bit operations */
4582 /* bt/bts/btr/btc Gv, im */
4590 ir
.ot
= ir
.dflag
+ OT_WORD
;
4591 if (i386_record_modrm (&ir
))
4596 opcode
= opcode
<< 8 | ir
.modrm
;
4604 if (i386_record_lea_modrm (&ir
))
4609 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4613 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4619 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4627 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
4629 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4646 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4648 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4655 if (prefixes
& PREFIX_LOCK
)
4665 printf_unfiltered (_("Process record doesn't support instruction "
4674 printf_unfiltered (_("Process record doesn't support instruction "
4685 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
4688 printf_unfiltered (_("Process record: error reading memory "
4689 "at addr %s len = 1.\n"),
4690 paddress (gdbarch
, ir
.addr
));
4695 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
4697 printf_unfiltered (_("Process record doesn't support "
4698 "instruction int 0x%02x.\n"),
4703 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
4712 printf_unfiltered (_("Process record doesn't support "
4713 "instruction into.\n"));
4726 printf_unfiltered (_("Process record doesn't support "
4727 "instruction bound.\n"));
4741 if (record_arch_list_add_reg (ir
.regcache
, opcode
& 7))
4747 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4749 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4761 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4767 printf_unfiltered (_("Process record doesn't support "
4768 "instruction wrmsr.\n"));
4775 printf_unfiltered (_("Process record doesn't support "
4776 "instruction rdmsr.\n"));
4783 printf_unfiltered (_("Process record doesn't support "
4784 "instruction rdtsc.\n"));
4793 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
4795 printf_unfiltered (_("Process record doesn't support "
4796 "instruction sysenter.\n"));
4800 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
4808 printf_unfiltered (_("Process record doesn't support "
4809 "instruction sysexit.\n"));
4816 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4818 if (record_arch_list_add_reg (ir
.regcache
, I386_ECX_REGNUM
))
4820 if (record_arch_list_add_reg (ir
.regcache
, I386_EDX_REGNUM
))
4822 if (record_arch_list_add_reg (ir
.regcache
, I386_EBX_REGNUM
))
4828 printf_unfiltered (_("Process record doesn't support "
4829 "instruction hlt.\n"));
4835 if (i386_record_modrm (&ir
))
4845 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4851 if (i386_record_lea_modrm (&ir
))
4864 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4869 opcode
= opcode
<< 8 | ir
.modrm
;
4876 if (i386_record_modrm (&ir
))
4888 opcode
= opcode
<< 8 | ir
.modrm
;
4895 printf_unfiltered (_("Process record ignores the memory "
4896 "change of instruction at "
4897 "address %s because it can't get "
4898 "the value of the segment "
4900 paddress (gdbarch
, ir
.addr
));
4904 if (i386_record_lea_modrm_addr (&ir
, &addr
))
4906 if (record_arch_list_add_mem (addr
, 2))
4909 if (record_arch_list_add_mem (addr
, 4))
4924 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
4929 opcode
= opcode
<< 8 | ir
.modrm
;
4940 printf_unfiltered (_("Process record ignores the memory "
4941 "change of instruction at "
4942 "address %s because it can't get "
4943 "the value of the segment "
4945 paddress (gdbarch
, ir
.addr
));
4951 if (i386_record_lea_modrm_addr (&ir
, &addr
))
4953 if (record_arch_list_add_mem (addr
, 2))
4956 if (record_arch_list_add_mem (addr
, 4))
4971 opcode
= opcode
<< 8 | ir
.modrm
;
4979 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4985 if (i386_record_lea_modrm (&ir
))
5003 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5004 if (i386_record_modrm (&ir
))
5008 if (i386_record_lea_modrm (&ir
))
5013 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5016 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
5024 if (i386_record_modrm (&ir
))
5026 if (record_arch_list_add_reg (ir
.regcache
, ir
.reg
))
5028 if (record_arch_list_add_reg (ir
.regcache
, I386_EFLAGS_REGNUM
))
5035 /* nop (multi byte) */
5049 if (i386_record_modrm (&ir
))
5051 if ((ir
.modrm
& 0xc0) != 0xc0)
5054 opcode
= opcode
<< 8 | ir
.modrm
;
5069 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5075 opcode
= opcode
<< 8 | ir
.modrm
;
5085 if (i386_record_modrm (&ir
))
5087 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5088 || ir
.reg
== 5 || ir
.reg
>= 8)
5091 opcode
= opcode
<< 8 | ir
.modrm
;
5099 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5108 /* MMX/SSE/SSE2/PNI support */
5120 /* In the future, Maybe still need to deal with need_dasm */
5121 if (record_arch_list_add_reg (ir
.regcache
, I386_EIP_REGNUM
))
5123 if (record_arch_list_add_end ())
5129 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5130 "at address %s.\n"),
5131 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5136 static struct gdbarch
*
5137 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5139 struct gdbarch_tdep
*tdep
;
5140 struct gdbarch
*gdbarch
;
5142 /* If there is already a candidate, use it. */
5143 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5145 return arches
->gdbarch
;
5147 /* Allocate space for the new architecture. */
5148 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5149 gdbarch
= gdbarch_alloc (&info
, tdep
);
5151 /* General-purpose registers. */
5152 tdep
->gregset
= NULL
;
5153 tdep
->gregset_reg_offset
= NULL
;
5154 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5155 tdep
->sizeof_gregset
= 0;
5157 /* Floating-point registers. */
5158 tdep
->fpregset
= NULL
;
5159 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5161 /* The default settings include the FPU registers, the MMX registers
5162 and the SSE registers. This can be overridden for a specific ABI
5163 by adjusting the members `st0_regnum', `mm0_regnum' and
5164 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5165 will show up in the output of "info all-registers". Ideally we
5166 should try to autodetect whether they are available, such that we
5167 can prevent "info all-registers" from displaying registers that
5170 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5171 [the SSE registers] always (even when they don't exist) or never
5172 showing them to the user (even when they do exist), I prefer the
5173 former over the latter. */
5175 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5177 /* The MMX registers are implemented as pseudo-registers. Put off
5178 calculating the register number for %mm0 until we know the number
5179 of raw registers. */
5180 tdep
->mm0_regnum
= 0;
5182 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5183 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5185 tdep
->jb_pc_offset
= -1;
5186 tdep
->struct_return
= pcc_struct_return
;
5187 tdep
->sigtramp_start
= 0;
5188 tdep
->sigtramp_end
= 0;
5189 tdep
->sigtramp_p
= i386_sigtramp_p
;
5190 tdep
->sigcontext_addr
= NULL
;
5191 tdep
->sc_reg_offset
= NULL
;
5192 tdep
->sc_pc_offset
= -1;
5193 tdep
->sc_sp_offset
= -1;
5195 /* The format used for `long double' on almost all i386 targets is
5196 the i387 extended floating-point format. In fact, of all targets
5197 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5198 on having a `long double' that's not `long' at all. */
5199 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5201 /* Although the i387 extended floating-point has only 80 significant
5202 bits, a `long double' actually takes up 96, probably to enforce
5204 set_gdbarch_long_double_bit (gdbarch
, 96);
5206 /* The default ABI includes general-purpose registers,
5207 floating-point registers, and the SSE registers. */
5208 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5209 set_gdbarch_register_name (gdbarch
, i386_register_name
);
5210 set_gdbarch_register_type (gdbarch
, i386_register_type
);
5212 /* Register numbers of various important registers. */
5213 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5214 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5215 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5216 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5218 /* NOTE: kettenis/20040418: GCC does have two possible register
5219 numbering schemes on the i386: dbx and SVR4. These schemes
5220 differ in how they number %ebp, %esp, %eflags, and the
5221 floating-point registers, and are implemented by the arrays
5222 dbx_register_map[] and svr4_dbx_register_map in
5223 gcc/config/i386.c. GCC also defines a third numbering scheme in
5224 gcc/config/i386.c, which it designates as the "default" register
5225 map used in 64bit mode. This last register numbering scheme is
5226 implemented in dbx64_register_map, and is used for AMD64; see
5229 Currently, each GCC i386 target always uses the same register
5230 numbering scheme across all its supported debugging formats
5231 i.e. SDB (COFF), stabs and DWARF 2. This is because
5232 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5233 DBX_REGISTER_NUMBER macro which is defined by each target's
5234 respective config header in a manner independent of the requested
5235 output debugging format.
5237 This does not match the arrangement below, which presumes that
5238 the SDB and stabs numbering schemes differ from the DWARF and
5239 DWARF 2 ones. The reason for this arrangement is that it is
5240 likely to get the numbering scheme for the target's
5241 default/native debug format right. For targets where GCC is the
5242 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5243 targets where the native toolchain uses a different numbering
5244 scheme for a particular debug format (stabs-in-ELF on Solaris)
5245 the defaults below will have to be overridden, like
5246 i386_elf_init_abi() does. */
5248 /* Use the dbx register numbering scheme for stabs and COFF. */
5249 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5250 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5252 /* Use the SVR4 register numbering scheme for DWARF 2. */
5253 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5255 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5256 be in use on any of the supported i386 targets. */
5258 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5260 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5262 /* Call dummy code. */
5263 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5265 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5266 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5267 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5269 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5271 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5273 /* Stack grows downward. */
5274 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5276 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5277 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5278 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5280 set_gdbarch_frame_args_skip (gdbarch
, 8);
5282 /* Wire in the MMX registers. */
5283 set_gdbarch_num_pseudo_regs (gdbarch
, i386_num_mmx_regs
);
5284 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5285 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5287 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5289 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5291 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5293 /* Add the i386 register groups. */
5294 i386_add_reggroups (gdbarch
);
5295 set_gdbarch_register_reggroup_p (gdbarch
, i386_register_reggroup_p
);
5297 /* Helper for function argument information. */
5298 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5300 /* Hook in the DWARF CFI frame unwinder. */
5301 dwarf2_append_unwinders (gdbarch
);
5303 frame_base_set_default (gdbarch
, &i386_frame_base
);
5305 /* Hook in ABI-specific overrides, if they have been registered. */
5306 gdbarch_init_osabi (info
, gdbarch
);
5308 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5309 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5311 /* If we have a register mapping, enable the generic core file
5312 support, unless it has already been enabled. */
5313 if (tdep
->gregset_reg_offset
5314 && !gdbarch_regset_from_core_section_p (gdbarch
))
5315 set_gdbarch_regset_from_core_section (gdbarch
,
5316 i386_regset_from_core_section
);
5318 /* Unless support for MMX has been disabled, make %mm0 the first
5320 if (tdep
->mm0_regnum
== 0)
5321 tdep
->mm0_regnum
= gdbarch_num_regs (gdbarch
);
5323 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5324 i386_skip_permanent_breakpoint
);
5329 static enum gdb_osabi
5330 i386_coff_osabi_sniffer (bfd
*abfd
)
5332 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5333 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5334 return GDB_OSABI_GO32
;
5336 return GDB_OSABI_UNKNOWN
;
5340 /* Provide a prototype to silence -Wmissing-prototypes. */
5341 void _initialize_i386_tdep (void);
5344 _initialize_i386_tdep (void)
5346 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5348 /* Add the variable that controls the disassembly flavor. */
5349 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5350 &disassembly_flavor
, _("\
5351 Set the disassembly flavor."), _("\
5352 Show the disassembly flavor."), _("\
5353 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5355 NULL
, /* FIXME: i18n: */
5356 &setlist
, &showlist
);
5358 /* Add the variable that controls the convention for returning
5360 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5361 &struct_convention
, _("\
5362 Set the convention for returning small structs."), _("\
5363 Show the convention for returning small structs."), _("\
5364 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5367 NULL
, /* FIXME: i18n: */
5368 &setlist
, &showlist
);
5370 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5371 i386_coff_osabi_sniffer
);
5373 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5374 i386_svr4_init_abi
);
5375 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5376 i386_go32_init_abi
);
5378 /* Initialize the i386-specific register groups. */
5379 i386_init_reggroups ();