1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mpx.c"
61 #include "features/i386/i386-mmx.c"
66 #include "stap-probe.h"
67 #include "user-regs.h"
68 #include "cli/cli-utils.h"
69 #include "expression.h"
70 #include "parser-defs.h"
75 static const char *i386_register_names
[] =
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
90 static const char *i386_ymm_names
[] =
92 "ymm0", "ymm1", "ymm2", "ymm3",
93 "ymm4", "ymm5", "ymm6", "ymm7",
96 static const char *i386_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
102 static const char *i386_mpx_names
[] =
104 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
107 /* Register names for MPX pseudo-registers. */
109 static const char *i386_bnd_names
[] =
111 "bnd0", "bnd1", "bnd2", "bnd3"
114 /* Register names for MMX pseudo-registers. */
116 static const char *i386_mmx_names
[] =
118 "mm0", "mm1", "mm2", "mm3",
119 "mm4", "mm5", "mm6", "mm7"
122 /* Register names for byte pseudo-registers. */
124 static const char *i386_byte_names
[] =
126 "al", "cl", "dl", "bl",
127 "ah", "ch", "dh", "bh"
130 /* Register names for word pseudo-registers. */
132 static const char *i386_word_names
[] =
134 "ax", "cx", "dx", "bx",
141 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
144 int mm0_regnum
= tdep
->mm0_regnum
;
149 regnum
-= mm0_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
156 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 regnum
-= tdep
->al_regnum
;
161 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
167 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 regnum
-= tdep
->ax_regnum
;
172 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
175 /* Dword register? */
178 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int eax_regnum
= tdep
->eax_regnum
;
186 regnum
-= eax_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
191 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
196 if (ymm0h_regnum
< 0)
199 regnum
-= ymm0h_regnum
;
200 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
206 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
209 int ymm0_regnum
= tdep
->ymm0_regnum
;
214 regnum
-= ymm0_regnum
;
215 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
221 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 int bnd0_regnum
= tdep
->bnd0_regnum
;
229 regnum
-= bnd0_regnum
;
230 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
236 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
239 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
241 if (num_xmm_regs
== 0)
244 regnum
-= I387_XMM0_REGNUM (tdep
);
245 return regnum
>= 0 && regnum
< num_xmm_regs
;
249 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
253 if (I387_NUM_XMM_REGS (tdep
) == 0)
256 return (regnum
== I387_MXCSR_REGNUM (tdep
));
262 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
266 if (I387_ST0_REGNUM (tdep
) < 0)
269 return (I387_ST0_REGNUM (tdep
) <= regnum
270 && regnum
< I387_FCTRL_REGNUM (tdep
));
274 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
278 if (I387_ST0_REGNUM (tdep
) < 0)
281 return (I387_FCTRL_REGNUM (tdep
) <= regnum
282 && regnum
< I387_XMM0_REGNUM (tdep
));
285 /* BNDr (raw) register? */
288 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
292 if (I387_BND0R_REGNUM (tdep
) < 0)
295 regnum
-= tdep
->bnd0r_regnum
;
296 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
299 /* BND control register? */
302 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
306 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
309 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
310 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
313 /* Return the name of register REGNUM, or the empty string if it is
314 an anonymous register. */
317 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
319 /* Hide the upper YMM registers. */
320 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
323 return tdesc_register_name (gdbarch
, regnum
);
326 /* Return the name of register REGNUM. */
329 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 if (i386_bnd_regnum_p (gdbarch
, regnum
))
333 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
334 if (i386_mmx_regnum_p (gdbarch
, regnum
))
335 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
336 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
337 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
338 else if (i386_byte_regnum_p (gdbarch
, regnum
))
339 return i386_byte_names
[regnum
- tdep
->al_regnum
];
340 else if (i386_word_regnum_p (gdbarch
, regnum
))
341 return i386_word_names
[regnum
- tdep
->ax_regnum
];
343 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
346 /* Convert a dbx register number REG to the appropriate register
347 number used by GDB. */
350 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
354 /* This implements what GCC calls the "default" register map
355 (dbx_register_map[]). */
357 if (reg
>= 0 && reg
<= 7)
359 /* General-purpose registers. The debug info calls %ebp
360 register 4, and %esp register 5. */
367 else if (reg
>= 12 && reg
<= 19)
369 /* Floating-point registers. */
370 return reg
- 12 + I387_ST0_REGNUM (tdep
);
372 else if (reg
>= 21 && reg
<= 28)
375 int ymm0_regnum
= tdep
->ymm0_regnum
;
378 && i386_xmm_regnum_p (gdbarch
, reg
))
379 return reg
- 21 + ymm0_regnum
;
381 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
383 else if (reg
>= 29 && reg
<= 36)
386 return reg
- 29 + I387_MM0_REGNUM (tdep
);
389 /* This will hopefully provoke a warning. */
390 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
393 /* Convert SVR4 register number REG to the appropriate register number
397 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
401 /* This implements the GCC register map that tries to be compatible
402 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
404 /* The SVR4 register numbering includes %eip and %eflags, and
405 numbers the floating point registers differently. */
406 if (reg
>= 0 && reg
<= 9)
408 /* General-purpose registers. */
411 else if (reg
>= 11 && reg
<= 18)
413 /* Floating-point registers. */
414 return reg
- 11 + I387_ST0_REGNUM (tdep
);
416 else if (reg
>= 21 && reg
<= 36)
418 /* The SSE and MMX registers have the same numbers as with dbx. */
419 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
424 case 37: return I387_FCTRL_REGNUM (tdep
);
425 case 38: return I387_FSTAT_REGNUM (tdep
);
426 case 39: return I387_MXCSR_REGNUM (tdep
);
427 case 40: return I386_ES_REGNUM
;
428 case 41: return I386_CS_REGNUM
;
429 case 42: return I386_SS_REGNUM
;
430 case 43: return I386_DS_REGNUM
;
431 case 44: return I386_FS_REGNUM
;
432 case 45: return I386_GS_REGNUM
;
435 /* This will hopefully provoke a warning. */
436 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
441 /* This is the variable that is set with "set disassembly-flavor", and
442 its legitimate values. */
443 static const char att_flavor
[] = "att";
444 static const char intel_flavor
[] = "intel";
445 static const char *const valid_flavors
[] =
451 static const char *disassembly_flavor
= att_flavor
;
454 /* Use the program counter to determine the contents and size of a
455 breakpoint instruction. Return a pointer to a string of bytes that
456 encode a breakpoint instruction, store the length of the string in
457 *LEN and optionally adjust *PC to point to the correct memory
458 location for inserting the breakpoint.
460 On the i386 we have a single breakpoint that fits in a single byte
461 and can be inserted anywhere.
463 This function is 64-bit safe. */
465 static const gdb_byte
*
466 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
468 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
470 *len
= sizeof (break_insn
);
474 /* Displaced instruction handling. */
476 /* Skip the legacy instruction prefixes in INSN.
477 Not all prefixes are valid for any particular insn
478 but we needn't care, the insn will fault if it's invalid.
479 The result is a pointer to the first opcode byte,
480 or NULL if we run off the end of the buffer. */
483 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
485 gdb_byte
*end
= insn
+ max_len
;
491 case DATA_PREFIX_OPCODE
:
492 case ADDR_PREFIX_OPCODE
:
493 case CS_PREFIX_OPCODE
:
494 case DS_PREFIX_OPCODE
:
495 case ES_PREFIX_OPCODE
:
496 case FS_PREFIX_OPCODE
:
497 case GS_PREFIX_OPCODE
:
498 case SS_PREFIX_OPCODE
:
499 case LOCK_PREFIX_OPCODE
:
500 case REPE_PREFIX_OPCODE
:
501 case REPNE_PREFIX_OPCODE
:
513 i386_absolute_jmp_p (const gdb_byte
*insn
)
515 /* jmp far (absolute address in operand). */
521 /* jump near, absolute indirect (/4). */
522 if ((insn
[1] & 0x38) == 0x20)
525 /* jump far, absolute indirect (/5). */
526 if ((insn
[1] & 0x38) == 0x28)
534 i386_absolute_call_p (const gdb_byte
*insn
)
536 /* call far, absolute. */
542 /* Call near, absolute indirect (/2). */
543 if ((insn
[1] & 0x38) == 0x10)
546 /* Call far, absolute indirect (/3). */
547 if ((insn
[1] & 0x38) == 0x18)
555 i386_ret_p (const gdb_byte
*insn
)
559 case 0xc2: /* ret near, pop N bytes. */
560 case 0xc3: /* ret near */
561 case 0xca: /* ret far, pop N bytes. */
562 case 0xcb: /* ret far */
563 case 0xcf: /* iret */
572 i386_call_p (const gdb_byte
*insn
)
574 if (i386_absolute_call_p (insn
))
577 /* call near, relative. */
584 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
585 length in bytes. Otherwise, return zero. */
588 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
590 /* Is it 'int $0x80'? */
591 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
592 /* Or is it 'sysenter'? */
593 || (insn
[0] == 0x0f && insn
[1] == 0x34)
594 /* Or is it 'syscall'? */
595 || (insn
[0] == 0x0f && insn
[1] == 0x05))
604 /* Some kernels may run one past a syscall insn, so we have to cope.
605 Otherwise this is just simple_displaced_step_copy_insn. */
607 struct displaced_step_closure
*
608 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
609 CORE_ADDR from
, CORE_ADDR to
,
610 struct regcache
*regs
)
612 size_t len
= gdbarch_max_insn_length (gdbarch
);
613 gdb_byte
*buf
= xmalloc (len
);
615 read_memory (from
, buf
, len
);
617 /* GDB may get control back after the insn after the syscall.
618 Presumably this is a kernel bug.
619 If this is a syscall, make sure there's a nop afterwards. */
624 insn
= i386_skip_prefixes (buf
, len
);
625 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
626 insn
[syscall_length
] = NOP_OPCODE
;
629 write_memory (to
, buf
, len
);
633 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
634 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
635 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
638 return (struct displaced_step_closure
*) buf
;
641 /* Fix up the state of registers and memory after having single-stepped
642 a displaced instruction. */
645 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
646 struct displaced_step_closure
*closure
,
647 CORE_ADDR from
, CORE_ADDR to
,
648 struct regcache
*regs
)
650 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
652 /* The offset we applied to the instruction's address.
653 This could well be negative (when viewed as a signed 32-bit
654 value), but ULONGEST won't reflect that, so take care when
656 ULONGEST insn_offset
= to
- from
;
658 /* Since we use simple_displaced_step_copy_insn, our closure is a
659 copy of the instruction. */
660 gdb_byte
*insn
= (gdb_byte
*) closure
;
661 /* The start of the insn, needed in case we see some prefixes. */
662 gdb_byte
*insn_start
= insn
;
665 fprintf_unfiltered (gdb_stdlog
,
666 "displaced: fixup (%s, %s), "
667 "insn = 0x%02x 0x%02x ...\n",
668 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
671 /* The list of issues to contend with here is taken from
672 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
673 Yay for Free Software! */
675 /* Relocate the %eip, if necessary. */
677 /* The instruction recognizers we use assume any leading prefixes
678 have been skipped. */
680 /* This is the size of the buffer in closure. */
681 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
682 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
683 /* If there are too many prefixes, just ignore the insn.
684 It will fault when run. */
689 /* Except in the case of absolute or indirect jump or call
690 instructions, or a return instruction, the new eip is relative to
691 the displaced instruction; make it relative. Well, signal
692 handler returns don't need relocation either, but we use the
693 value of %eip to recognize those; see below. */
694 if (! i386_absolute_jmp_p (insn
)
695 && ! i386_absolute_call_p (insn
)
696 && ! i386_ret_p (insn
))
701 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
703 /* A signal trampoline system call changes the %eip, resuming
704 execution of the main program after the signal handler has
705 returned. That makes them like 'return' instructions; we
706 shouldn't relocate %eip.
708 But most system calls don't, and we do need to relocate %eip.
710 Our heuristic for distinguishing these cases: if stepping
711 over the system call instruction left control directly after
712 the instruction, the we relocate --- control almost certainly
713 doesn't belong in the displaced copy. Otherwise, we assume
714 the instruction has put control where it belongs, and leave
715 it unrelocated. Goodness help us if there are PC-relative
717 if (i386_syscall_p (insn
, &insn_len
)
718 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
719 /* GDB can get control back after the insn after the syscall.
720 Presumably this is a kernel bug.
721 i386_displaced_step_copy_insn ensures its a nop,
722 we add one to the length for it. */
723 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
726 fprintf_unfiltered (gdb_stdlog
,
727 "displaced: syscall changed %%eip; "
732 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
734 /* If we just stepped over a breakpoint insn, we don't backup
735 the pc on purpose; this is to match behaviour without
738 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
741 fprintf_unfiltered (gdb_stdlog
,
743 "relocated %%eip from %s to %s\n",
744 paddress (gdbarch
, orig_eip
),
745 paddress (gdbarch
, eip
));
749 /* If the instruction was PUSHFL, then the TF bit will be set in the
750 pushed value, and should be cleared. We'll leave this for later,
751 since GDB already messes up the TF flag when stepping over a
754 /* If the instruction was a call, the return address now atop the
755 stack is the address following the copied instruction. We need
756 to make it the address following the original instruction. */
757 if (i386_call_p (insn
))
761 const ULONGEST retaddr_len
= 4;
763 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
764 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
765 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
766 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
769 fprintf_unfiltered (gdb_stdlog
,
770 "displaced: relocated return addr at %s to %s\n",
771 paddress (gdbarch
, esp
),
772 paddress (gdbarch
, retaddr
));
777 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
779 target_write_memory (*to
, buf
, len
);
784 i386_relocate_instruction (struct gdbarch
*gdbarch
,
785 CORE_ADDR
*to
, CORE_ADDR oldloc
)
787 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 gdb_byte buf
[I386_MAX_INSN_LEN
];
789 int offset
= 0, rel32
, newrel
;
791 gdb_byte
*insn
= buf
;
793 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
795 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
796 I386_MAX_INSN_LEN
, oldloc
);
798 /* Get past the prefixes. */
799 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
801 /* Adjust calls with 32-bit relative addresses as push/jump, with
802 the address pushed being the location where the original call in
803 the user program would return to. */
806 gdb_byte push_buf
[16];
807 unsigned int ret_addr
;
809 /* Where "ret" in the original code will return to. */
810 ret_addr
= oldloc
+ insn_length
;
811 push_buf
[0] = 0x68; /* pushq $... */
812 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
814 append_insns (to
, 5, push_buf
);
816 /* Convert the relative call to a relative jump. */
819 /* Adjust the destination offset. */
820 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
821 newrel
= (oldloc
- *to
) + rel32
;
822 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
825 fprintf_unfiltered (gdb_stdlog
,
826 "Adjusted insn rel32=%s at %s to"
828 hex_string (rel32
), paddress (gdbarch
, oldloc
),
829 hex_string (newrel
), paddress (gdbarch
, *to
));
831 /* Write the adjusted jump into its displaced location. */
832 append_insns (to
, 5, insn
);
836 /* Adjust jumps with 32-bit relative addresses. Calls are already
840 /* Adjust conditional jumps. */
841 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
846 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
847 newrel
= (oldloc
- *to
) + rel32
;
848 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
850 fprintf_unfiltered (gdb_stdlog
,
851 "Adjusted insn rel32=%s at %s to"
853 hex_string (rel32
), paddress (gdbarch
, oldloc
),
854 hex_string (newrel
), paddress (gdbarch
, *to
));
857 /* Write the adjusted instructions into their displaced
859 append_insns (to
, insn_length
, buf
);
863 #ifdef I386_REGNO_TO_SYMMETRY
864 #error "The Sequent Symmetry is no longer supported."
867 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
868 and %esp "belong" to the calling function. Therefore these
869 registers should be saved if they're going to be modified. */
871 /* The maximum number of saved registers. This should include all
872 registers mentioned above, and %eip. */
873 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
875 struct i386_frame_cache
883 /* Saved registers. */
884 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
889 /* Stack space reserved for local variables. */
893 /* Allocate and initialize a frame cache. */
895 static struct i386_frame_cache
*
896 i386_alloc_frame_cache (void)
898 struct i386_frame_cache
*cache
;
901 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
906 cache
->sp_offset
= -4;
909 /* Saved registers. We initialize these to -1 since zero is a valid
910 offset (that's where %ebp is supposed to be stored). */
911 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
912 cache
->saved_regs
[i
] = -1;
914 cache
->saved_sp_reg
= -1;
915 cache
->pc_in_eax
= 0;
917 /* Frameless until proven otherwise. */
923 /* If the instruction at PC is a jump, return the address of its
924 target. Otherwise, return PC. */
927 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
934 if (target_read_code (pc
, &op
, 1))
941 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
947 /* Relative jump: if data16 == 0, disp32, else disp16. */
950 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
952 /* Include the size of the jmp instruction (including the
958 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
960 /* Include the size of the jmp instruction. */
965 /* Relative jump, disp8 (ignore data16). */
966 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
975 /* Check whether PC points at a prologue for a function returning a
976 structure or union. If so, it updates CACHE and returns the
977 address of the first instruction after the code sequence that
978 removes the "hidden" argument from the stack or CURRENT_PC,
979 whichever is smaller. Otherwise, return PC. */
982 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
983 struct i386_frame_cache
*cache
)
985 /* Functions that return a structure or union start with:
988 xchgl %eax, (%esp) 0x87 0x04 0x24
989 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
991 (the System V compiler puts out the second `xchg' instruction,
992 and the assembler doesn't try to optimize it, so the 'sib' form
993 gets generated). This sequence is used to get the address of the
994 return buffer for a function that returns a structure. */
995 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
996 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1000 if (current_pc
<= pc
)
1003 if (target_read_code (pc
, &op
, 1))
1006 if (op
!= 0x58) /* popl %eax */
1009 if (target_read_code (pc
+ 1, buf
, 4))
1012 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1015 if (current_pc
== pc
)
1017 cache
->sp_offset
+= 4;
1021 if (current_pc
== pc
+ 1)
1023 cache
->pc_in_eax
= 1;
1027 if (buf
[1] == proto1
[1])
1034 i386_skip_probe (CORE_ADDR pc
)
1036 /* A function may start with
1050 if (target_read_code (pc
, &op
, 1))
1053 if (op
== 0x68 || op
== 0x6a)
1057 /* Skip past the `pushl' instruction; it has either a one-byte or a
1058 four-byte operand, depending on the opcode. */
1064 /* Read the following 8 bytes, which should be `call _probe' (6
1065 bytes) followed by `addl $4,%esp' (2 bytes). */
1066 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1067 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1068 pc
+= delta
+ sizeof (buf
);
1074 /* GCC 4.1 and later, can put code in the prologue to realign the
1075 stack pointer. Check whether PC points to such code, and update
1076 CACHE accordingly. Return the first instruction after the code
1077 sequence or CURRENT_PC, whichever is smaller. If we don't
1078 recognize the code, return PC. */
1081 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1082 struct i386_frame_cache
*cache
)
1084 /* There are 2 code sequences to re-align stack before the frame
1087 1. Use a caller-saved saved register:
1093 2. Use a callee-saved saved register:
1100 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1102 0x83 0xe4 0xf0 andl $-16, %esp
1103 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1108 int offset
, offset_and
;
1109 static int regnums
[8] = {
1110 I386_EAX_REGNUM
, /* %eax */
1111 I386_ECX_REGNUM
, /* %ecx */
1112 I386_EDX_REGNUM
, /* %edx */
1113 I386_EBX_REGNUM
, /* %ebx */
1114 I386_ESP_REGNUM
, /* %esp */
1115 I386_EBP_REGNUM
, /* %ebp */
1116 I386_ESI_REGNUM
, /* %esi */
1117 I386_EDI_REGNUM
/* %edi */
1120 if (target_read_code (pc
, buf
, sizeof buf
))
1123 /* Check caller-saved saved register. The first instruction has
1124 to be "leal 4(%esp), %reg". */
1125 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1127 /* MOD must be binary 10 and R/M must be binary 100. */
1128 if ((buf
[1] & 0xc7) != 0x44)
1131 /* REG has register number. */
1132 reg
= (buf
[1] >> 3) & 7;
1137 /* Check callee-saved saved register. The first instruction
1138 has to be "pushl %reg". */
1139 if ((buf
[0] & 0xf8) != 0x50)
1145 /* The next instruction has to be "leal 8(%esp), %reg". */
1146 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1149 /* MOD must be binary 10 and R/M must be binary 100. */
1150 if ((buf
[2] & 0xc7) != 0x44)
1153 /* REG has register number. Registers in pushl and leal have to
1155 if (reg
!= ((buf
[2] >> 3) & 7))
1161 /* Rigister can't be %esp nor %ebp. */
1162 if (reg
== 4 || reg
== 5)
1165 /* The next instruction has to be "andl $-XXX, %esp". */
1166 if (buf
[offset
+ 1] != 0xe4
1167 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1170 offset_and
= offset
;
1171 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1173 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1174 0xfc. REG must be binary 110 and MOD must be binary 01. */
1175 if (buf
[offset
] != 0xff
1176 || buf
[offset
+ 2] != 0xfc
1177 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1180 /* R/M has register. Registers in leal and pushl have to be the
1182 if (reg
!= (buf
[offset
+ 1] & 7))
1185 if (current_pc
> pc
+ offset_and
)
1186 cache
->saved_sp_reg
= regnums
[reg
];
1188 return min (pc
+ offset
+ 3, current_pc
);
1191 /* Maximum instruction length we need to handle. */
1192 #define I386_MAX_MATCHED_INSN_LEN 6
1194 /* Instruction description. */
1198 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1199 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1202 /* Return whether instruction at PC matches PATTERN. */
1205 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1209 if (target_read_code (pc
, &op
, 1))
1212 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1214 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1215 int insn_matched
= 1;
1218 gdb_assert (pattern
.len
> 1);
1219 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1221 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1224 for (i
= 1; i
< pattern
.len
; i
++)
1226 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1229 return insn_matched
;
1234 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1235 the first instruction description that matches. Otherwise, return
1238 static struct i386_insn
*
1239 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1241 struct i386_insn
*pattern
;
1243 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1245 if (i386_match_pattern (pc
, *pattern
))
1252 /* Return whether PC points inside a sequence of instructions that
1253 matches INSN_PATTERNS. */
1256 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1258 CORE_ADDR current_pc
;
1260 struct i386_insn
*insn
;
1262 insn
= i386_match_insn (pc
, insn_patterns
);
1267 ix
= insn
- insn_patterns
;
1268 for (i
= ix
- 1; i
>= 0; i
--)
1270 current_pc
-= insn_patterns
[i
].len
;
1272 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1276 current_pc
= pc
+ insn
->len
;
1277 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1279 if (!i386_match_pattern (current_pc
, *insn
))
1282 current_pc
+= insn
->len
;
1288 /* Some special instructions that might be migrated by GCC into the
1289 part of the prologue that sets up the new stack frame. Because the
1290 stack frame hasn't been setup yet, no registers have been saved
1291 yet, and only the scratch registers %eax, %ecx and %edx can be
1294 struct i386_insn i386_frame_setup_skip_insns
[] =
1296 /* Check for `movb imm8, r' and `movl imm32, r'.
1298 ??? Should we handle 16-bit operand-sizes here? */
1300 /* `movb imm8, %al' and `movb imm8, %ah' */
1301 /* `movb imm8, %cl' and `movb imm8, %ch' */
1302 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1303 /* `movb imm8, %dl' and `movb imm8, %dh' */
1304 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1305 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1306 { 5, { 0xb8 }, { 0xfe } },
1307 /* `movl imm32, %edx' */
1308 { 5, { 0xba }, { 0xff } },
1310 /* Check for `mov imm32, r32'. Note that there is an alternative
1311 encoding for `mov m32, %eax'.
1313 ??? Should we handle SIB adressing here?
1314 ??? Should we handle 16-bit operand-sizes here? */
1316 /* `movl m32, %eax' */
1317 { 5, { 0xa1 }, { 0xff } },
1318 /* `movl m32, %eax' and `mov; m32, %ecx' */
1319 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1320 /* `movl m32, %edx' */
1321 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1323 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1324 Because of the symmetry, there are actually two ways to encode
1325 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1326 opcode bytes 0x31 and 0x33 for `xorl'. */
1328 /* `subl %eax, %eax' */
1329 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1330 /* `subl %ecx, %ecx' */
1331 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1332 /* `subl %edx, %edx' */
1333 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1334 /* `xorl %eax, %eax' */
1335 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1336 /* `xorl %ecx, %ecx' */
1337 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1338 /* `xorl %edx, %edx' */
1339 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1344 /* Check whether PC points to a no-op instruction. */
1346 i386_skip_noop (CORE_ADDR pc
)
1351 if (target_read_code (pc
, &op
, 1))
1357 /* Ignore `nop' instruction. */
1361 if (target_read_code (pc
, &op
, 1))
1365 /* Ignore no-op instruction `mov %edi, %edi'.
1366 Microsoft system dlls often start with
1367 a `mov %edi,%edi' instruction.
1368 The 5 bytes before the function start are
1369 filled with `nop' instructions.
1370 This pattern can be used for hot-patching:
1371 The `mov %edi, %edi' instruction can be replaced by a
1372 near jump to the location of the 5 `nop' instructions
1373 which can be replaced by a 32-bit jump to anywhere
1374 in the 32-bit address space. */
1376 else if (op
== 0x8b)
1378 if (target_read_code (pc
+ 1, &op
, 1))
1384 if (target_read_code (pc
, &op
, 1))
1394 /* Check whether PC points at a code that sets up a new stack frame.
1395 If so, it updates CACHE and returns the address of the first
1396 instruction after the sequence that sets up the frame or LIMIT,
1397 whichever is smaller. If we don't recognize the code, return PC. */
1400 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1401 CORE_ADDR pc
, CORE_ADDR limit
,
1402 struct i386_frame_cache
*cache
)
1404 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1405 struct i386_insn
*insn
;
1412 if (target_read_code (pc
, &op
, 1))
1415 if (op
== 0x55) /* pushl %ebp */
1417 /* Take into account that we've executed the `pushl %ebp' that
1418 starts this instruction sequence. */
1419 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1420 cache
->sp_offset
+= 4;
1423 /* If that's all, return now. */
1427 /* Check for some special instructions that might be migrated by
1428 GCC into the prologue and skip them. At this point in the
1429 prologue, code should only touch the scratch registers %eax,
1430 %ecx and %edx, so while the number of posibilities is sheer,
1433 Make sure we only skip these instructions if we later see the
1434 `movl %esp, %ebp' that actually sets up the frame. */
1435 while (pc
+ skip
< limit
)
1437 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1444 /* If that's all, return now. */
1445 if (limit
<= pc
+ skip
)
1448 if (target_read_code (pc
+ skip
, &op
, 1))
1451 /* The i386 prologue looks like
1457 and a different prologue can be generated for atom.
1461 lea -0x10(%esp),%esp
1463 We handle both of them here. */
1467 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1469 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1475 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1480 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1481 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1490 /* OK, we actually have a frame. We just don't know how large
1491 it is yet. Set its size to zero. We'll adjust it if
1492 necessary. We also now commit to skipping the special
1493 instructions mentioned before. */
1496 /* If that's all, return now. */
1500 /* Check for stack adjustment
1506 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1507 reg, so we don't have to worry about a data16 prefix. */
1508 if (target_read_code (pc
, &op
, 1))
1512 /* `subl' with 8-bit immediate. */
1513 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1514 /* Some instruction starting with 0x83 other than `subl'. */
1517 /* `subl' with signed 8-bit immediate (though it wouldn't
1518 make sense to be negative). */
1519 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1522 else if (op
== 0x81)
1524 /* Maybe it is `subl' with a 32-bit immediate. */
1525 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1526 /* Some instruction starting with 0x81 other than `subl'. */
1529 /* It is `subl' with a 32-bit immediate. */
1530 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1533 else if (op
== 0x8d)
1535 /* The ModR/M byte is 0x64. */
1536 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1538 /* 'lea' with 8-bit displacement. */
1539 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1544 /* Some instruction other than `subl' nor 'lea'. */
1548 else if (op
== 0xc8) /* enter */
1550 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1557 /* Check whether PC points at code that saves registers on the stack.
1558 If so, it updates CACHE and returns the address of the first
1559 instruction after the register saves or CURRENT_PC, whichever is
1560 smaller. Otherwise, return PC. */
1563 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1564 struct i386_frame_cache
*cache
)
1566 CORE_ADDR offset
= 0;
1570 if (cache
->locals
> 0)
1571 offset
-= cache
->locals
;
1572 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1574 if (target_read_code (pc
, &op
, 1))
1576 if (op
< 0x50 || op
> 0x57)
1580 cache
->saved_regs
[op
- 0x50] = offset
;
1581 cache
->sp_offset
+= 4;
1588 /* Do a full analysis of the prologue at PC and update CACHE
1589 accordingly. Bail out early if CURRENT_PC is reached. Return the
1590 address where the analysis stopped.
1592 We handle these cases:
1594 The startup sequence can be at the start of the function, or the
1595 function can start with a branch to startup code at the end.
1597 %ebp can be set up with either the 'enter' instruction, or "pushl
1598 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1599 once used in the System V compiler).
1601 Local space is allocated just below the saved %ebp by either the
1602 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1603 16-bit unsigned argument for space to allocate, and the 'addl'
1604 instruction could have either a signed byte, or 32-bit immediate.
1606 Next, the registers used by this function are pushed. With the
1607 System V compiler they will always be in the order: %edi, %esi,
1608 %ebx (and sometimes a harmless bug causes it to also save but not
1609 restore %eax); however, the code below is willing to see the pushes
1610 in any order, and will handle up to 8 of them.
1612 If the setup sequence is at the end of the function, then the next
1613 instruction will be a branch back to the start. */
1616 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1617 CORE_ADDR pc
, CORE_ADDR current_pc
,
1618 struct i386_frame_cache
*cache
)
1620 pc
= i386_skip_noop (pc
);
1621 pc
= i386_follow_jump (gdbarch
, pc
);
1622 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1623 pc
= i386_skip_probe (pc
);
1624 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1625 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1626 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1629 /* Return PC of first real instruction. */
1632 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1634 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1636 static gdb_byte pic_pat
[6] =
1638 0xe8, 0, 0, 0, 0, /* call 0x0 */
1639 0x5b, /* popl %ebx */
1641 struct i386_frame_cache cache
;
1645 CORE_ADDR func_addr
;
1647 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1649 CORE_ADDR post_prologue_pc
1650 = skip_prologue_using_sal (gdbarch
, func_addr
);
1651 struct symtab
*s
= find_pc_symtab (func_addr
);
1653 /* Clang always emits a line note before the prologue and another
1654 one after. We trust clang to emit usable line notes. */
1655 if (post_prologue_pc
1657 && s
->producer
!= NULL
1658 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1659 return max (start_pc
, post_prologue_pc
);
1663 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1664 if (cache
.locals
< 0)
1667 /* Found valid frame setup. */
1669 /* The native cc on SVR4 in -K PIC mode inserts the following code
1670 to get the address of the global offset table (GOT) into register
1675 movl %ebx,x(%ebp) (optional)
1678 This code is with the rest of the prologue (at the end of the
1679 function), so we have to skip it to get to the first real
1680 instruction at the start of the function. */
1682 for (i
= 0; i
< 6; i
++)
1684 if (target_read_code (pc
+ i
, &op
, 1))
1687 if (pic_pat
[i
] != op
)
1694 if (target_read_code (pc
+ delta
, &op
, 1))
1697 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1699 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1701 if (op
== 0x5d) /* One byte offset from %ebp. */
1703 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1705 else /* Unexpected instruction. */
1708 if (target_read_code (pc
+ delta
, &op
, 1))
1713 if (delta
> 0 && op
== 0x81
1714 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1721 /* If the function starts with a branch (to startup code at the end)
1722 the last instruction should bring us back to the first
1723 instruction of the real code. */
1724 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1725 pc
= i386_follow_jump (gdbarch
, pc
);
1730 /* Check that the code pointed to by PC corresponds to a call to
1731 __main, skip it if so. Return PC otherwise. */
1734 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1736 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1739 if (target_read_code (pc
, &op
, 1))
1745 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1747 /* Make sure address is computed correctly as a 32bit
1748 integer even if CORE_ADDR is 64 bit wide. */
1749 struct bound_minimal_symbol s
;
1750 CORE_ADDR call_dest
;
1752 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1753 call_dest
= call_dest
& 0xffffffffU
;
1754 s
= lookup_minimal_symbol_by_pc (call_dest
);
1755 if (s
.minsym
!= NULL
1756 && SYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1757 && strcmp (SYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1765 /* This function is 64-bit safe. */
1768 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1772 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1773 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1777 /* Normal frames. */
1780 i386_frame_cache_1 (struct frame_info
*this_frame
,
1781 struct i386_frame_cache
*cache
)
1783 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1784 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1788 cache
->pc
= get_frame_func (this_frame
);
1790 /* In principle, for normal frames, %ebp holds the frame pointer,
1791 which holds the base address for the current stack frame.
1792 However, for functions that don't need it, the frame pointer is
1793 optional. For these "frameless" functions the frame pointer is
1794 actually the frame pointer of the calling frame. Signal
1795 trampolines are just a special case of a "frameless" function.
1796 They (usually) share their frame pointer with the frame that was
1797 in progress when the signal occurred. */
1799 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1800 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1801 if (cache
->base
== 0)
1807 /* For normal frames, %eip is stored at 4(%ebp). */
1808 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1811 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1814 if (cache
->locals
< 0)
1816 /* We didn't find a valid frame, which means that CACHE->base
1817 currently holds the frame pointer for our calling frame. If
1818 we're at the start of a function, or somewhere half-way its
1819 prologue, the function's frame probably hasn't been fully
1820 setup yet. Try to reconstruct the base address for the stack
1821 frame by looking at the stack pointer. For truly "frameless"
1822 functions this might work too. */
1824 if (cache
->saved_sp_reg
!= -1)
1826 /* Saved stack pointer has been saved. */
1827 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1828 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1830 /* We're halfway aligning the stack. */
1831 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1832 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1834 /* This will be added back below. */
1835 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1837 else if (cache
->pc
!= 0
1838 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
1840 /* We're in a known function, but did not find a frame
1841 setup. Assume that the function does not use %ebp.
1842 Alternatively, we may have jumped to an invalid
1843 address; in that case there is definitely no new
1845 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1846 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1850 /* We're in an unknown function. We could not find the start
1851 of the function to analyze the prologue; our best option is
1852 to assume a typical frame layout with the caller's %ebp
1854 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1857 if (cache
->saved_sp_reg
!= -1)
1859 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1860 register may be unavailable). */
1861 if (cache
->saved_sp
== 0
1862 && deprecated_frame_register_read (this_frame
,
1863 cache
->saved_sp_reg
, buf
))
1864 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1866 /* Now that we have the base address for the stack frame we can
1867 calculate the value of %esp in the calling frame. */
1868 else if (cache
->saved_sp
== 0)
1869 cache
->saved_sp
= cache
->base
+ 8;
1871 /* Adjust all the saved registers such that they contain addresses
1872 instead of offsets. */
1873 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1874 if (cache
->saved_regs
[i
] != -1)
1875 cache
->saved_regs
[i
] += cache
->base
;
1880 static struct i386_frame_cache
*
1881 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1883 volatile struct gdb_exception ex
;
1884 struct i386_frame_cache
*cache
;
1889 cache
= i386_alloc_frame_cache ();
1890 *this_cache
= cache
;
1892 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1894 i386_frame_cache_1 (this_frame
, cache
);
1896 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1897 throw_exception (ex
);
1903 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1904 struct frame_id
*this_id
)
1906 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1908 /* This marks the outermost frame. */
1909 if (cache
->base
== 0)
1912 /* See the end of i386_push_dummy_call. */
1913 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1916 static enum unwind_stop_reason
1917 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1920 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1923 return UNWIND_UNAVAILABLE
;
1925 /* This marks the outermost frame. */
1926 if (cache
->base
== 0)
1927 return UNWIND_OUTERMOST
;
1929 return UNWIND_NO_REASON
;
1932 static struct value
*
1933 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1936 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1938 gdb_assert (regnum
>= 0);
1940 /* The System V ABI says that:
1942 "The flags register contains the system flags, such as the
1943 direction flag and the carry flag. The direction flag must be
1944 set to the forward (that is, zero) direction before entry and
1945 upon exit from a function. Other user flags have no specified
1946 role in the standard calling sequence and are not preserved."
1948 To guarantee the "upon exit" part of that statement we fake a
1949 saved flags register that has its direction flag cleared.
1951 Note that GCC doesn't seem to rely on the fact that the direction
1952 flag is cleared after a function return; it always explicitly
1953 clears the flag before operations where it matters.
1955 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1956 right thing to do. The way we fake the flags register here makes
1957 it impossible to change it. */
1959 if (regnum
== I386_EFLAGS_REGNUM
)
1963 val
= get_frame_register_unsigned (this_frame
, regnum
);
1965 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1968 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1969 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1971 if (regnum
== I386_ESP_REGNUM
1972 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1974 /* If the SP has been saved, but we don't know where, then this
1975 means that SAVED_SP_REG register was found unavailable back
1976 when we built the cache. */
1977 if (cache
->saved_sp
== 0)
1978 return frame_unwind_got_register (this_frame
, regnum
,
1979 cache
->saved_sp_reg
);
1981 return frame_unwind_got_constant (this_frame
, regnum
,
1985 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1986 return frame_unwind_got_memory (this_frame
, regnum
,
1987 cache
->saved_regs
[regnum
]);
1989 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1992 static const struct frame_unwind i386_frame_unwind
=
1995 i386_frame_unwind_stop_reason
,
1997 i386_frame_prev_register
,
1999 default_frame_sniffer
2002 /* Normal frames, but in a function epilogue. */
2004 /* The epilogue is defined here as the 'ret' instruction, which will
2005 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2006 the function's stack frame. */
2009 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2012 struct symtab
*symtab
;
2014 symtab
= find_pc_symtab (pc
);
2015 if (symtab
&& symtab
->epilogue_unwind_valid
)
2018 if (target_read_memory (pc
, &insn
, 1))
2019 return 0; /* Can't read memory at pc. */
2021 if (insn
!= 0xc3) /* 'ret' instruction. */
2028 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2029 struct frame_info
*this_frame
,
2030 void **this_prologue_cache
)
2032 if (frame_relative_level (this_frame
) == 0)
2033 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
2034 get_frame_pc (this_frame
));
2039 static struct i386_frame_cache
*
2040 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2042 volatile struct gdb_exception ex
;
2043 struct i386_frame_cache
*cache
;
2049 cache
= i386_alloc_frame_cache ();
2050 *this_cache
= cache
;
2052 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2054 cache
->pc
= get_frame_func (this_frame
);
2056 /* At this point the stack looks as if we just entered the
2057 function, with the return address at the top of the
2059 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2060 cache
->base
= sp
+ cache
->sp_offset
;
2061 cache
->saved_sp
= cache
->base
+ 8;
2062 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2066 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2067 throw_exception (ex
);
2072 static enum unwind_stop_reason
2073 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2076 struct i386_frame_cache
*cache
=
2077 i386_epilogue_frame_cache (this_frame
, this_cache
);
2080 return UNWIND_UNAVAILABLE
;
2082 return UNWIND_NO_REASON
;
2086 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2088 struct frame_id
*this_id
)
2090 struct i386_frame_cache
*cache
=
2091 i386_epilogue_frame_cache (this_frame
, this_cache
);
2096 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2099 static struct value
*
2100 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2101 void **this_cache
, int regnum
)
2103 /* Make sure we've initialized the cache. */
2104 i386_epilogue_frame_cache (this_frame
, this_cache
);
2106 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2109 static const struct frame_unwind i386_epilogue_frame_unwind
=
2112 i386_epilogue_frame_unwind_stop_reason
,
2113 i386_epilogue_frame_this_id
,
2114 i386_epilogue_frame_prev_register
,
2116 i386_epilogue_frame_sniffer
2120 /* Stack-based trampolines. */
2122 /* These trampolines are used on cross x86 targets, when taking the
2123 address of a nested function. When executing these trampolines,
2124 no stack frame is set up, so we are in a similar situation as in
2125 epilogues and i386_epilogue_frame_this_id can be re-used. */
2127 /* Static chain passed in register. */
2129 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2131 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2132 { 5, { 0xb8 }, { 0xfe } },
2135 { 5, { 0xe9 }, { 0xff } },
2140 /* Static chain passed on stack (when regparm=3). */
2142 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2145 { 5, { 0x68 }, { 0xff } },
2148 { 5, { 0xe9 }, { 0xff } },
2153 /* Return whether PC points inside a stack trampoline. */
2156 i386_in_stack_tramp_p (CORE_ADDR pc
)
2161 /* A stack trampoline is detected if no name is associated
2162 to the current pc and if it points inside a trampoline
2165 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2169 if (target_read_memory (pc
, &insn
, 1))
2172 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2173 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2180 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2181 struct frame_info
*this_frame
,
2184 if (frame_relative_level (this_frame
) == 0)
2185 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2190 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2193 i386_epilogue_frame_unwind_stop_reason
,
2194 i386_epilogue_frame_this_id
,
2195 i386_epilogue_frame_prev_register
,
2197 i386_stack_tramp_frame_sniffer
2200 /* Generate a bytecode expression to get the value of the saved PC. */
2203 i386_gen_return_address (struct gdbarch
*gdbarch
,
2204 struct agent_expr
*ax
, struct axs_value
*value
,
2207 /* The following sequence assumes the traditional use of the base
2209 ax_reg (ax
, I386_EBP_REGNUM
);
2211 ax_simple (ax
, aop_add
);
2212 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2213 value
->kind
= axs_lvalue_memory
;
2217 /* Signal trampolines. */
2219 static struct i386_frame_cache
*
2220 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2222 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2224 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2225 volatile struct gdb_exception ex
;
2226 struct i386_frame_cache
*cache
;
2233 cache
= i386_alloc_frame_cache ();
2235 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2237 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2238 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2240 addr
= tdep
->sigcontext_addr (this_frame
);
2241 if (tdep
->sc_reg_offset
)
2245 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2247 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2248 if (tdep
->sc_reg_offset
[i
] != -1)
2249 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2253 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2254 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2259 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2260 throw_exception (ex
);
2262 *this_cache
= cache
;
2266 static enum unwind_stop_reason
2267 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2270 struct i386_frame_cache
*cache
=
2271 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2274 return UNWIND_UNAVAILABLE
;
2276 return UNWIND_NO_REASON
;
2280 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2281 struct frame_id
*this_id
)
2283 struct i386_frame_cache
*cache
=
2284 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2289 /* See the end of i386_push_dummy_call. */
2290 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2293 static struct value
*
2294 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2295 void **this_cache
, int regnum
)
2297 /* Make sure we've initialized the cache. */
2298 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2300 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2304 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2305 struct frame_info
*this_frame
,
2306 void **this_prologue_cache
)
2308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2310 /* We shouldn't even bother if we don't have a sigcontext_addr
2312 if (tdep
->sigcontext_addr
== NULL
)
2315 if (tdep
->sigtramp_p
!= NULL
)
2317 if (tdep
->sigtramp_p (this_frame
))
2321 if (tdep
->sigtramp_start
!= 0)
2323 CORE_ADDR pc
= get_frame_pc (this_frame
);
2325 gdb_assert (tdep
->sigtramp_end
!= 0);
2326 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2333 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2336 i386_sigtramp_frame_unwind_stop_reason
,
2337 i386_sigtramp_frame_this_id
,
2338 i386_sigtramp_frame_prev_register
,
2340 i386_sigtramp_frame_sniffer
2345 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2347 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2352 static const struct frame_base i386_frame_base
=
2355 i386_frame_base_address
,
2356 i386_frame_base_address
,
2357 i386_frame_base_address
2360 static struct frame_id
2361 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2365 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2367 /* See the end of i386_push_dummy_call. */
2368 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2371 /* _Decimal128 function return values need 16-byte alignment on the
2375 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2377 return sp
& -(CORE_ADDR
)16;
2381 /* Figure out where the longjmp will land. Slurp the args out of the
2382 stack. We expect the first arg to be a pointer to the jmp_buf
2383 structure from which we extract the address that we will land at.
2384 This address is copied into PC. This routine returns non-zero on
2388 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2391 CORE_ADDR sp
, jb_addr
;
2392 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2393 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2394 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2396 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2397 longjmp will land. */
2398 if (jb_pc_offset
== -1)
2401 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2402 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2403 if (target_read_memory (sp
+ 4, buf
, 4))
2406 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2407 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2410 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2415 /* Check whether TYPE must be 16-byte-aligned when passed as a
2416 function argument. 16-byte vectors, _Decimal128 and structures or
2417 unions containing such types must be 16-byte-aligned; other
2418 arguments are 4-byte-aligned. */
2421 i386_16_byte_align_p (struct type
*type
)
2423 type
= check_typedef (type
);
2424 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2425 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2426 && TYPE_LENGTH (type
) == 16)
2428 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2429 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2430 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2431 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2434 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2436 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2443 /* Implementation for set_gdbarch_push_dummy_code. */
2446 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2447 struct value
**args
, int nargs
, struct type
*value_type
,
2448 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2449 struct regcache
*regcache
)
2451 /* Use 0xcc breakpoint - 1 byte. */
2455 /* Keep the stack aligned. */
2460 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2461 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2462 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2463 CORE_ADDR struct_addr
)
2465 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2471 /* Determine the total space required for arguments and struct
2472 return address in a first pass (allowing for 16-byte-aligned
2473 arguments), then push arguments in a second pass. */
2475 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2477 int args_space_used
= 0;
2483 /* Push value address. */
2484 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2485 write_memory (sp
, buf
, 4);
2486 args_space_used
+= 4;
2492 for (i
= 0; i
< nargs
; i
++)
2494 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2498 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2499 args_space_used
= align_up (args_space_used
, 16);
2501 write_memory (sp
+ args_space_used
,
2502 value_contents_all (args
[i
]), len
);
2503 /* The System V ABI says that:
2505 "An argument's size is increased, if necessary, to make it a
2506 multiple of [32-bit] words. This may require tail padding,
2507 depending on the size of the argument."
2509 This makes sure the stack stays word-aligned. */
2510 args_space_used
+= align_up (len
, 4);
2514 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2515 args_space
= align_up (args_space
, 16);
2516 args_space
+= align_up (len
, 4);
2524 /* The original System V ABI only requires word alignment,
2525 but modern incarnations need 16-byte alignment in order
2526 to support SSE. Since wasting a few bytes here isn't
2527 harmful we unconditionally enforce 16-byte alignment. */
2532 /* Store return address. */
2534 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2535 write_memory (sp
, buf
, 4);
2537 /* Finally, update the stack pointer... */
2538 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2539 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2541 /* ...and fake a frame pointer. */
2542 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2544 /* MarkK wrote: This "+ 8" is all over the place:
2545 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2546 i386_dummy_id). It's there, since all frame unwinders for
2547 a given target have to agree (within a certain margin) on the
2548 definition of the stack address of a frame. Otherwise frame id
2549 comparison might not work correctly. Since DWARF2/GCC uses the
2550 stack address *before* the function call as a frame's CFA. On
2551 the i386, when %ebp is used as a frame pointer, the offset
2552 between the contents %ebp and the CFA as defined by GCC. */
2556 /* These registers are used for returning integers (and on some
2557 targets also for returning `struct' and `union' values when their
2558 size and alignment match an integer type). */
2559 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2560 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2562 /* Read, for architecture GDBARCH, a function return value of TYPE
2563 from REGCACHE, and copy that into VALBUF. */
2566 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2567 struct regcache
*regcache
, gdb_byte
*valbuf
)
2569 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2570 int len
= TYPE_LENGTH (type
);
2571 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2573 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2575 if (tdep
->st0_regnum
< 0)
2577 warning (_("Cannot find floating-point return value."));
2578 memset (valbuf
, 0, len
);
2582 /* Floating-point return values can be found in %st(0). Convert
2583 its contents to the desired type. This is probably not
2584 exactly how it would happen on the target itself, but it is
2585 the best we can do. */
2586 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2587 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2591 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2592 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2594 if (len
<= low_size
)
2596 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2597 memcpy (valbuf
, buf
, len
);
2599 else if (len
<= (low_size
+ high_size
))
2601 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2602 memcpy (valbuf
, buf
, low_size
);
2603 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2604 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2607 internal_error (__FILE__
, __LINE__
,
2608 _("Cannot extract return value of %d bytes long."),
2613 /* Write, for architecture GDBARCH, a function return value of TYPE
2614 from VALBUF into REGCACHE. */
2617 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2618 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2620 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2621 int len
= TYPE_LENGTH (type
);
2623 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2626 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2628 if (tdep
->st0_regnum
< 0)
2630 warning (_("Cannot set floating-point return value."));
2634 /* Returning floating-point values is a bit tricky. Apart from
2635 storing the return value in %st(0), we have to simulate the
2636 state of the FPU at function return point. */
2638 /* Convert the value found in VALBUF to the extended
2639 floating-point format used by the FPU. This is probably
2640 not exactly how it would happen on the target itself, but
2641 it is the best we can do. */
2642 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2643 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2645 /* Set the top of the floating-point register stack to 7. The
2646 actual value doesn't really matter, but 7 is what a normal
2647 function return would end up with if the program started out
2648 with a freshly initialized FPU. */
2649 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2651 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2653 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2654 the floating-point register stack to 7, the appropriate value
2655 for the tag word is 0x3fff. */
2656 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2660 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2661 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2663 if (len
<= low_size
)
2664 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2665 else if (len
<= (low_size
+ high_size
))
2667 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2668 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2669 len
- low_size
, valbuf
+ low_size
);
2672 internal_error (__FILE__
, __LINE__
,
2673 _("Cannot store return value of %d bytes long."), len
);
2678 /* This is the variable that is set with "set struct-convention", and
2679 its legitimate values. */
2680 static const char default_struct_convention
[] = "default";
2681 static const char pcc_struct_convention
[] = "pcc";
2682 static const char reg_struct_convention
[] = "reg";
2683 static const char *const valid_conventions
[] =
2685 default_struct_convention
,
2686 pcc_struct_convention
,
2687 reg_struct_convention
,
2690 static const char *struct_convention
= default_struct_convention
;
2692 /* Return non-zero if TYPE, which is assumed to be a structure,
2693 a union type, or an array type, should be returned in registers
2694 for architecture GDBARCH. */
2697 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2699 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2700 enum type_code code
= TYPE_CODE (type
);
2701 int len
= TYPE_LENGTH (type
);
2703 gdb_assert (code
== TYPE_CODE_STRUCT
2704 || code
== TYPE_CODE_UNION
2705 || code
== TYPE_CODE_ARRAY
);
2707 if (struct_convention
== pcc_struct_convention
2708 || (struct_convention
== default_struct_convention
2709 && tdep
->struct_return
== pcc_struct_return
))
2712 /* Structures consisting of a single `float', `double' or 'long
2713 double' member are returned in %st(0). */
2714 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2716 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2717 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2718 return (len
== 4 || len
== 8 || len
== 12);
2721 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2724 /* Determine, for architecture GDBARCH, how a return value of TYPE
2725 should be returned. If it is supposed to be returned in registers,
2726 and READBUF is non-zero, read the appropriate value from REGCACHE,
2727 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2728 from WRITEBUF into REGCACHE. */
2730 static enum return_value_convention
2731 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2732 struct type
*type
, struct regcache
*regcache
,
2733 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2735 enum type_code code
= TYPE_CODE (type
);
2737 if (((code
== TYPE_CODE_STRUCT
2738 || code
== TYPE_CODE_UNION
2739 || code
== TYPE_CODE_ARRAY
)
2740 && !i386_reg_struct_return_p (gdbarch
, type
))
2741 /* Complex double and long double uses the struct return covention. */
2742 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2743 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2744 /* 128-bit decimal float uses the struct return convention. */
2745 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2747 /* The System V ABI says that:
2749 "A function that returns a structure or union also sets %eax
2750 to the value of the original address of the caller's area
2751 before it returns. Thus when the caller receives control
2752 again, the address of the returned object resides in register
2753 %eax and can be used to access the object."
2755 So the ABI guarantees that we can always find the return
2756 value just after the function has returned. */
2758 /* Note that the ABI doesn't mention functions returning arrays,
2759 which is something possible in certain languages such as Ada.
2760 In this case, the value is returned as if it was wrapped in
2761 a record, so the convention applied to records also applies
2768 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2769 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2772 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2775 /* This special case is for structures consisting of a single
2776 `float', `double' or 'long double' member. These structures are
2777 returned in %st(0). For these structures, we call ourselves
2778 recursively, changing TYPE into the type of the first member of
2779 the structure. Since that should work for all structures that
2780 have only one member, we don't bother to check the member's type
2782 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2784 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2785 return i386_return_value (gdbarch
, function
, type
, regcache
,
2790 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2792 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2794 return RETURN_VALUE_REGISTER_CONVENTION
;
2799 i387_ext_type (struct gdbarch
*gdbarch
)
2801 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2803 if (!tdep
->i387_ext_type
)
2805 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2806 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2809 return tdep
->i387_ext_type
;
2812 /* Construct type for pseudo BND registers. We can't use
2813 tdesc_find_type since a complement of one value has to be used
2814 to describe the upper bound. */
2816 static struct type
*
2817 i386_bnd_type (struct gdbarch
*gdbarch
)
2819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2822 if (!tdep
->i386_bnd_type
)
2824 struct type
*t
, *bound_t
;
2825 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2827 /* The type we're building is described bellow: */
2832 void *ubound
; /* One complement of raw ubound field. */
2836 t
= arch_composite_type (gdbarch
,
2837 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
2839 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
2840 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
2842 TYPE_NAME (t
) = "builtin_type_bound128";
2843 tdep
->i386_bnd_type
= t
;
2846 return tdep
->i386_bnd_type
;
2849 /* Construct vector type for pseudo YMM registers. We can't use
2850 tdesc_find_type since YMM isn't described in target description. */
2852 static struct type
*
2853 i386_ymm_type (struct gdbarch
*gdbarch
)
2855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2857 if (!tdep
->i386_ymm_type
)
2859 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2861 /* The type we're building is this: */
2863 union __gdb_builtin_type_vec256i
2865 int128_t uint128
[2];
2866 int64_t v2_int64
[4];
2867 int32_t v4_int32
[8];
2868 int16_t v8_int16
[16];
2869 int8_t v16_int8
[32];
2870 double v2_double
[4];
2877 t
= arch_composite_type (gdbarch
,
2878 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2879 append_composite_type_field (t
, "v8_float",
2880 init_vector_type (bt
->builtin_float
, 8));
2881 append_composite_type_field (t
, "v4_double",
2882 init_vector_type (bt
->builtin_double
, 4));
2883 append_composite_type_field (t
, "v32_int8",
2884 init_vector_type (bt
->builtin_int8
, 32));
2885 append_composite_type_field (t
, "v16_int16",
2886 init_vector_type (bt
->builtin_int16
, 16));
2887 append_composite_type_field (t
, "v8_int32",
2888 init_vector_type (bt
->builtin_int32
, 8));
2889 append_composite_type_field (t
, "v4_int64",
2890 init_vector_type (bt
->builtin_int64
, 4));
2891 append_composite_type_field (t
, "v2_int128",
2892 init_vector_type (bt
->builtin_int128
, 2));
2894 TYPE_VECTOR (t
) = 1;
2895 TYPE_NAME (t
) = "builtin_type_vec256i";
2896 tdep
->i386_ymm_type
= t
;
2899 return tdep
->i386_ymm_type
;
2902 /* Construct vector type for MMX registers. */
2903 static struct type
*
2904 i386_mmx_type (struct gdbarch
*gdbarch
)
2906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2908 if (!tdep
->i386_mmx_type
)
2910 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2912 /* The type we're building is this: */
2914 union __gdb_builtin_type_vec64i
2917 int32_t v2_int32
[2];
2918 int16_t v4_int16
[4];
2925 t
= arch_composite_type (gdbarch
,
2926 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2928 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2929 append_composite_type_field (t
, "v2_int32",
2930 init_vector_type (bt
->builtin_int32
, 2));
2931 append_composite_type_field (t
, "v4_int16",
2932 init_vector_type (bt
->builtin_int16
, 4));
2933 append_composite_type_field (t
, "v8_int8",
2934 init_vector_type (bt
->builtin_int8
, 8));
2936 TYPE_VECTOR (t
) = 1;
2937 TYPE_NAME (t
) = "builtin_type_vec64i";
2938 tdep
->i386_mmx_type
= t
;
2941 return tdep
->i386_mmx_type
;
2944 /* Return the GDB type object for the "standard" data type of data in
2948 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2950 if (i386_bnd_regnum_p (gdbarch
, regnum
))
2951 return i386_bnd_type (gdbarch
);
2952 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2953 return i386_mmx_type (gdbarch
);
2954 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2955 return i386_ymm_type (gdbarch
);
2958 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2959 if (i386_byte_regnum_p (gdbarch
, regnum
))
2960 return bt
->builtin_int8
;
2961 else if (i386_word_regnum_p (gdbarch
, regnum
))
2962 return bt
->builtin_int16
;
2963 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2964 return bt
->builtin_int32
;
2967 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2970 /* Map a cooked register onto a raw register or memory. For the i386,
2971 the MMX registers need to be mapped onto floating point registers. */
2974 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2976 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2981 mmxreg
= regnum
- tdep
->mm0_regnum
;
2982 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2983 tos
= (fstat
>> 11) & 0x7;
2984 fpreg
= (mmxreg
+ tos
) % 8;
2986 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2989 /* A helper function for us by i386_pseudo_register_read_value and
2990 amd64_pseudo_register_read_value. It does all the work but reads
2991 the data into an already-allocated value. */
2994 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2995 struct regcache
*regcache
,
2997 struct value
*result_value
)
2999 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3000 enum register_status status
;
3001 gdb_byte
*buf
= value_contents_raw (result_value
);
3003 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3005 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3007 /* Extract (always little endian). */
3008 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3009 if (status
!= REG_VALID
)
3010 mark_value_bytes_unavailable (result_value
, 0,
3011 TYPE_LENGTH (value_type (result_value
)));
3013 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3018 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3020 regnum
-= tdep
->bnd0_regnum
;
3022 /* Extract (always little endian). Read lower 128bits. */
3023 status
= regcache_raw_read (regcache
,
3024 I387_BND0R_REGNUM (tdep
) + regnum
,
3026 if (status
!= REG_VALID
)
3027 mark_value_bytes_unavailable (result_value
, 0, 16);
3030 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3031 LONGEST upper
, lower
;
3032 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3034 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3035 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3038 memcpy (buf
, &lower
, size
);
3039 memcpy (buf
+ size
, &upper
, size
);
3042 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3044 regnum
-= tdep
->ymm0_regnum
;
3046 /* Extract (always little endian). Read lower 128bits. */
3047 status
= regcache_raw_read (regcache
,
3048 I387_XMM0_REGNUM (tdep
) + regnum
,
3050 if (status
!= REG_VALID
)
3051 mark_value_bytes_unavailable (result_value
, 0, 16);
3053 memcpy (buf
, raw_buf
, 16);
3054 /* Read upper 128bits. */
3055 status
= regcache_raw_read (regcache
,
3056 tdep
->ymm0h_regnum
+ regnum
,
3058 if (status
!= REG_VALID
)
3059 mark_value_bytes_unavailable (result_value
, 16, 32);
3061 memcpy (buf
+ 16, raw_buf
, 16);
3063 else if (i386_word_regnum_p (gdbarch
, regnum
))
3065 int gpnum
= regnum
- tdep
->ax_regnum
;
3067 /* Extract (always little endian). */
3068 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3069 if (status
!= REG_VALID
)
3070 mark_value_bytes_unavailable (result_value
, 0,
3071 TYPE_LENGTH (value_type (result_value
)));
3073 memcpy (buf
, raw_buf
, 2);
3075 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3077 /* Check byte pseudo registers last since this function will
3078 be called from amd64_pseudo_register_read, which handles
3079 byte pseudo registers differently. */
3080 int gpnum
= regnum
- tdep
->al_regnum
;
3082 /* Extract (always little endian). We read both lower and
3084 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3085 if (status
!= REG_VALID
)
3086 mark_value_bytes_unavailable (result_value
, 0,
3087 TYPE_LENGTH (value_type (result_value
)));
3088 else if (gpnum
>= 4)
3089 memcpy (buf
, raw_buf
+ 1, 1);
3091 memcpy (buf
, raw_buf
, 1);
3094 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3098 static struct value
*
3099 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3100 struct regcache
*regcache
,
3103 struct value
*result
;
3105 result
= allocate_value (register_type (gdbarch
, regnum
));
3106 VALUE_LVAL (result
) = lval_register
;
3107 VALUE_REGNUM (result
) = regnum
;
3109 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3115 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3116 int regnum
, const gdb_byte
*buf
)
3118 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3120 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3122 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3125 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3126 /* ... Modify ... (always little endian). */
3127 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3129 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3133 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3135 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3137 ULONGEST upper
, lower
;
3138 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3139 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3141 /* New values from input value. */
3142 regnum
-= tdep
->bnd0_regnum
;
3143 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3144 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3146 /* Fetching register buffer. */
3147 regcache_raw_read (regcache
,
3148 I387_BND0R_REGNUM (tdep
) + regnum
,
3153 /* Set register bits. */
3154 memcpy (raw_buf
, &lower
, 8);
3155 memcpy (raw_buf
+ 8, &upper
, 8);
3158 regcache_raw_write (regcache
,
3159 I387_BND0R_REGNUM (tdep
) + regnum
,
3162 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3164 regnum
-= tdep
->ymm0_regnum
;
3166 /* ... Write lower 128bits. */
3167 regcache_raw_write (regcache
,
3168 I387_XMM0_REGNUM (tdep
) + regnum
,
3170 /* ... Write upper 128bits. */
3171 regcache_raw_write (regcache
,
3172 tdep
->ymm0h_regnum
+ regnum
,
3175 else if (i386_word_regnum_p (gdbarch
, regnum
))
3177 int gpnum
= regnum
- tdep
->ax_regnum
;
3180 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3181 /* ... Modify ... (always little endian). */
3182 memcpy (raw_buf
, buf
, 2);
3184 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3186 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3188 /* Check byte pseudo registers last since this function will
3189 be called from amd64_pseudo_register_read, which handles
3190 byte pseudo registers differently. */
3191 int gpnum
= regnum
- tdep
->al_regnum
;
3193 /* Read ... We read both lower and upper registers. */
3194 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3195 /* ... Modify ... (always little endian). */
3197 memcpy (raw_buf
+ 1, buf
, 1);
3199 memcpy (raw_buf
, buf
, 1);
3201 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3204 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3209 /* Return the register number of the register allocated by GCC after
3210 REGNUM, or -1 if there is no such register. */
3213 i386_next_regnum (int regnum
)
3215 /* GCC allocates the registers in the order:
3217 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3219 Since storing a variable in %esp doesn't make any sense we return
3220 -1 for %ebp and for %esp itself. */
3221 static int next_regnum
[] =
3223 I386_EDX_REGNUM
, /* Slot for %eax. */
3224 I386_EBX_REGNUM
, /* Slot for %ecx. */
3225 I386_ECX_REGNUM
, /* Slot for %edx. */
3226 I386_ESI_REGNUM
, /* Slot for %ebx. */
3227 -1, -1, /* Slots for %esp and %ebp. */
3228 I386_EDI_REGNUM
, /* Slot for %esi. */
3229 I386_EBP_REGNUM
/* Slot for %edi. */
3232 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3233 return next_regnum
[regnum
];
3238 /* Return nonzero if a value of type TYPE stored in register REGNUM
3239 needs any special handling. */
3242 i386_convert_register_p (struct gdbarch
*gdbarch
,
3243 int regnum
, struct type
*type
)
3245 int len
= TYPE_LENGTH (type
);
3247 /* Values may be spread across multiple registers. Most debugging
3248 formats aren't expressive enough to specify the locations, so
3249 some heuristics is involved. Right now we only handle types that
3250 have a length that is a multiple of the word size, since GCC
3251 doesn't seem to put any other types into registers. */
3252 if (len
> 4 && len
% 4 == 0)
3254 int last_regnum
= regnum
;
3258 last_regnum
= i386_next_regnum (last_regnum
);
3262 if (last_regnum
!= -1)
3266 return i387_convert_register_p (gdbarch
, regnum
, type
);
3269 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3270 return its contents in TO. */
3273 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3274 struct type
*type
, gdb_byte
*to
,
3275 int *optimizedp
, int *unavailablep
)
3277 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3278 int len
= TYPE_LENGTH (type
);
3280 if (i386_fp_regnum_p (gdbarch
, regnum
))
3281 return i387_register_to_value (frame
, regnum
, type
, to
,
3282 optimizedp
, unavailablep
);
3284 /* Read a value spread across multiple registers. */
3286 gdb_assert (len
> 4 && len
% 4 == 0);
3290 gdb_assert (regnum
!= -1);
3291 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3293 if (!get_frame_register_bytes (frame
, regnum
, 0,
3294 register_size (gdbarch
, regnum
),
3295 to
, optimizedp
, unavailablep
))
3298 regnum
= i386_next_regnum (regnum
);
3303 *optimizedp
= *unavailablep
= 0;
3307 /* Write the contents FROM of a value of type TYPE into register
3308 REGNUM in frame FRAME. */
3311 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3312 struct type
*type
, const gdb_byte
*from
)
3314 int len
= TYPE_LENGTH (type
);
3316 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3318 i387_value_to_register (frame
, regnum
, type
, from
);
3322 /* Write a value spread across multiple registers. */
3324 gdb_assert (len
> 4 && len
% 4 == 0);
3328 gdb_assert (regnum
!= -1);
3329 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3331 put_frame_register (frame
, regnum
, from
);
3332 regnum
= i386_next_regnum (regnum
);
3338 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3339 in the general-purpose register set REGSET to register cache
3340 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3343 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3344 int regnum
, const void *gregs
, size_t len
)
3346 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3347 const gdb_byte
*regs
= gregs
;
3350 gdb_assert (len
== tdep
->sizeof_gregset
);
3352 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3354 if ((regnum
== i
|| regnum
== -1)
3355 && tdep
->gregset_reg_offset
[i
] != -1)
3356 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3360 /* Collect register REGNUM from the register cache REGCACHE and store
3361 it in the buffer specified by GREGS and LEN as described by the
3362 general-purpose register set REGSET. If REGNUM is -1, do this for
3363 all registers in REGSET. */
3366 i386_collect_gregset (const struct regset
*regset
,
3367 const struct regcache
*regcache
,
3368 int regnum
, void *gregs
, size_t len
)
3370 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3371 gdb_byte
*regs
= gregs
;
3374 gdb_assert (len
== tdep
->sizeof_gregset
);
3376 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3378 if ((regnum
== i
|| regnum
== -1)
3379 && tdep
->gregset_reg_offset
[i
] != -1)
3380 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3384 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3385 in the floating-point register set REGSET to register cache
3386 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3389 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3390 int regnum
, const void *fpregs
, size_t len
)
3392 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3394 if (len
== I387_SIZEOF_FXSAVE
)
3396 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3400 gdb_assert (len
== tdep
->sizeof_fpregset
);
3401 i387_supply_fsave (regcache
, regnum
, fpregs
);
3404 /* Collect register REGNUM from the register cache REGCACHE and store
3405 it in the buffer specified by FPREGS and LEN as described by the
3406 floating-point register set REGSET. If REGNUM is -1, do this for
3407 all registers in REGSET. */
3410 i386_collect_fpregset (const struct regset
*regset
,
3411 const struct regcache
*regcache
,
3412 int regnum
, void *fpregs
, size_t len
)
3414 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3416 if (len
== I387_SIZEOF_FXSAVE
)
3418 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3422 gdb_assert (len
== tdep
->sizeof_fpregset
);
3423 i387_collect_fsave (regcache
, regnum
, fpregs
);
3426 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3429 i386_supply_xstateregset (const struct regset
*regset
,
3430 struct regcache
*regcache
, int regnum
,
3431 const void *xstateregs
, size_t len
)
3433 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3436 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3439 i386_collect_xstateregset (const struct regset
*regset
,
3440 const struct regcache
*regcache
,
3441 int regnum
, void *xstateregs
, size_t len
)
3443 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3446 /* Return the appropriate register set for the core section identified
3447 by SECT_NAME and SECT_SIZE. */
3449 const struct regset
*
3450 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3451 const char *sect_name
, size_t sect_size
)
3453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3455 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3457 if (tdep
->gregset
== NULL
)
3458 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3459 i386_collect_gregset
);
3460 return tdep
->gregset
;
3463 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3464 || (strcmp (sect_name
, ".reg-xfp") == 0
3465 && sect_size
== I387_SIZEOF_FXSAVE
))
3467 if (tdep
->fpregset
== NULL
)
3468 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3469 i386_collect_fpregset
);
3470 return tdep
->fpregset
;
3473 if (strcmp (sect_name
, ".reg-xstate") == 0)
3475 if (tdep
->xstateregset
== NULL
)
3476 tdep
->xstateregset
= regset_alloc (gdbarch
,
3477 i386_supply_xstateregset
,
3478 i386_collect_xstateregset
);
3480 return tdep
->xstateregset
;
3487 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3490 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3491 CORE_ADDR pc
, char *name
)
3493 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3494 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3497 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3499 unsigned long indirect
=
3500 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3501 struct minimal_symbol
*indsym
=
3502 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3503 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3507 if (strncmp (symname
, "__imp_", 6) == 0
3508 || strncmp (symname
, "_imp_", 5) == 0)
3510 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3513 return 0; /* Not a trampoline. */
3517 /* Return whether the THIS_FRAME corresponds to a sigtramp
3521 i386_sigtramp_p (struct frame_info
*this_frame
)
3523 CORE_ADDR pc
= get_frame_pc (this_frame
);
3526 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3527 return (name
&& strcmp ("_sigtramp", name
) == 0);
3531 /* We have two flavours of disassembly. The machinery on this page
3532 deals with switching between those. */
3535 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3537 gdb_assert (disassembly_flavor
== att_flavor
3538 || disassembly_flavor
== intel_flavor
);
3540 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3541 constified, cast to prevent a compiler warning. */
3542 info
->disassembler_options
= (char *) disassembly_flavor
;
3544 return print_insn_i386 (pc
, info
);
3548 /* There are a few i386 architecture variants that differ only
3549 slightly from the generic i386 target. For now, we don't give them
3550 their own source file, but include them here. As a consequence,
3551 they'll always be included. */
3553 /* System V Release 4 (SVR4). */
3555 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3559 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3561 CORE_ADDR pc
= get_frame_pc (this_frame
);
3564 /* The origin of these symbols is currently unknown. */
3565 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3566 return (name
&& (strcmp ("_sigreturn", name
) == 0
3567 || strcmp ("sigvechandler", name
) == 0));
3570 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3571 address of the associated sigcontext (ucontext) structure. */
3574 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3576 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3577 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3581 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3582 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3584 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3589 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3593 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3595 return (*s
== '$' /* Literal number. */
3596 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3597 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3598 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3601 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3605 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3606 struct stap_parse_info
*p
)
3608 /* In order to parse special tokens, we use a state-machine that go
3609 through every known token and try to get a match. */
3613 THREE_ARG_DISPLACEMENT
,
3617 current_state
= TRIPLET
;
3619 /* The special tokens to be parsed here are:
3621 - `register base + (register index * size) + offset', as represented
3622 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3624 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3625 `*(-8 + 3 - 1 + (void *) $eax)'. */
3627 while (current_state
!= DONE
)
3629 const char *s
= p
->arg
;
3631 switch (current_state
)
3635 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3639 long displacements
[3];
3655 displacements
[0] = strtol (s
, &endp
, 10);
3658 if (*s
!= '+' && *s
!= '-')
3660 /* We are not dealing with a triplet. */
3673 displacements
[1] = strtol (s
, &endp
, 10);
3676 if (*s
!= '+' && *s
!= '-')
3678 /* We are not dealing with a triplet. */
3691 displacements
[2] = strtol (s
, &endp
, 10);
3694 if (*s
!= '(' || s
[1] != '%')
3700 while (isalnum (*s
))
3707 regname
= alloca (len
+ 1);
3709 strncpy (regname
, start
, len
);
3710 regname
[len
] = '\0';
3712 if (user_reg_map_name_to_regnum (gdbarch
,
3713 regname
, len
) == -1)
3714 error (_("Invalid register name `%s' "
3715 "on expression `%s'."),
3716 regname
, p
->saved_arg
);
3718 for (i
= 0; i
< 3; i
++)
3720 write_exp_elt_opcode (OP_LONG
);
3722 (builtin_type (gdbarch
)->builtin_long
);
3723 write_exp_elt_longcst (displacements
[i
]);
3724 write_exp_elt_opcode (OP_LONG
);
3726 write_exp_elt_opcode (UNOP_NEG
);
3729 write_exp_elt_opcode (OP_REGISTER
);
3732 write_exp_string (str
);
3733 write_exp_elt_opcode (OP_REGISTER
);
3735 write_exp_elt_opcode (UNOP_CAST
);
3736 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3737 write_exp_elt_opcode (UNOP_CAST
);
3739 write_exp_elt_opcode (BINOP_ADD
);
3740 write_exp_elt_opcode (BINOP_ADD
);
3741 write_exp_elt_opcode (BINOP_ADD
);
3743 write_exp_elt_opcode (UNOP_CAST
);
3744 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3745 write_exp_elt_opcode (UNOP_CAST
);
3747 write_exp_elt_opcode (UNOP_IND
);
3755 case THREE_ARG_DISPLACEMENT
:
3757 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3759 int offset_minus
= 0;
3768 struct stoken base_token
, index_token
;
3778 if (offset_minus
&& !isdigit (*s
))
3785 offset
= strtol (s
, &endp
, 10);
3789 if (*s
!= '(' || s
[1] != '%')
3795 while (isalnum (*s
))
3798 if (*s
!= ',' || s
[1] != '%')
3801 len_base
= s
- start
;
3802 base
= alloca (len_base
+ 1);
3803 strncpy (base
, start
, len_base
);
3804 base
[len_base
] = '\0';
3806 if (user_reg_map_name_to_regnum (gdbarch
,
3807 base
, len_base
) == -1)
3808 error (_("Invalid register name `%s' "
3809 "on expression `%s'."),
3810 base
, p
->saved_arg
);
3815 while (isalnum (*s
))
3818 len_index
= s
- start
;
3819 index
= alloca (len_index
+ 1);
3820 strncpy (index
, start
, len_index
);
3821 index
[len_index
] = '\0';
3823 if (user_reg_map_name_to_regnum (gdbarch
,
3824 index
, len_index
) == -1)
3825 error (_("Invalid register name `%s' "
3826 "on expression `%s'."),
3827 index
, p
->saved_arg
);
3829 if (*s
!= ',' && *s
!= ')')
3845 size
= strtol (s
, &endp
, 10);
3856 write_exp_elt_opcode (OP_LONG
);
3858 (builtin_type (gdbarch
)->builtin_long
);
3859 write_exp_elt_longcst (offset
);
3860 write_exp_elt_opcode (OP_LONG
);
3862 write_exp_elt_opcode (UNOP_NEG
);
3865 write_exp_elt_opcode (OP_REGISTER
);
3866 base_token
.ptr
= base
;
3867 base_token
.length
= len_base
;
3868 write_exp_string (base_token
);
3869 write_exp_elt_opcode (OP_REGISTER
);
3872 write_exp_elt_opcode (BINOP_ADD
);
3874 write_exp_elt_opcode (OP_REGISTER
);
3875 index_token
.ptr
= index
;
3876 index_token
.length
= len_index
;
3877 write_exp_string (index_token
);
3878 write_exp_elt_opcode (OP_REGISTER
);
3882 write_exp_elt_opcode (OP_LONG
);
3884 (builtin_type (gdbarch
)->builtin_long
);
3885 write_exp_elt_longcst (size
);
3886 write_exp_elt_opcode (OP_LONG
);
3888 write_exp_elt_opcode (UNOP_NEG
);
3889 write_exp_elt_opcode (BINOP_MUL
);
3892 write_exp_elt_opcode (BINOP_ADD
);
3894 write_exp_elt_opcode (UNOP_CAST
);
3895 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3896 write_exp_elt_opcode (UNOP_CAST
);
3898 write_exp_elt_opcode (UNOP_IND
);
3908 /* Advancing to the next state. */
3920 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3922 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3923 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3925 /* Registering SystemTap handlers. */
3926 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3927 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3928 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3929 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3930 set_gdbarch_stap_is_single_operand (gdbarch
,
3931 i386_stap_is_single_operand
);
3932 set_gdbarch_stap_parse_special_token (gdbarch
,
3933 i386_stap_parse_special_token
);
3936 /* System V Release 4 (SVR4). */
3939 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3943 /* System V Release 4 uses ELF. */
3944 i386_elf_init_abi (info
, gdbarch
);
3946 /* System V Release 4 has shared libraries. */
3947 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3949 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3950 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3951 tdep
->sc_pc_offset
= 36 + 14 * 4;
3952 tdep
->sc_sp_offset
= 36 + 17 * 4;
3954 tdep
->jb_pc_offset
= 20;
3960 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3964 /* DJGPP doesn't have any special frames for signal handlers. */
3965 tdep
->sigtramp_p
= NULL
;
3967 tdep
->jb_pc_offset
= 36;
3969 /* DJGPP does not support the SSE registers. */
3970 if (! tdesc_has_registers (info
.target_desc
))
3971 tdep
->tdesc
= tdesc_i386_mmx
;
3973 /* Native compiler is GCC, which uses the SVR4 register numbering
3974 even in COFF and STABS. See the comment in i386_gdbarch_init,
3975 before the calls to set_gdbarch_stab_reg_to_regnum and
3976 set_gdbarch_sdb_reg_to_regnum. */
3977 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3978 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3980 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3984 /* i386 register groups. In addition to the normal groups, add "mmx"
3987 static struct reggroup
*i386_sse_reggroup
;
3988 static struct reggroup
*i386_mmx_reggroup
;
3991 i386_init_reggroups (void)
3993 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3994 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3998 i386_add_reggroups (struct gdbarch
*gdbarch
)
4000 reggroup_add (gdbarch
, i386_sse_reggroup
);
4001 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4002 reggroup_add (gdbarch
, general_reggroup
);
4003 reggroup_add (gdbarch
, float_reggroup
);
4004 reggroup_add (gdbarch
, all_reggroup
);
4005 reggroup_add (gdbarch
, save_reggroup
);
4006 reggroup_add (gdbarch
, restore_reggroup
);
4007 reggroup_add (gdbarch
, vector_reggroup
);
4008 reggroup_add (gdbarch
, system_reggroup
);
4012 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4013 struct reggroup
*group
)
4015 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4016 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4017 ymm_regnum_p
, ymmh_regnum_p
, bndr_regnum_p
, bnd_regnum_p
,
4020 /* Don't include pseudo registers, except for MMX, in any register
4022 if (i386_byte_regnum_p (gdbarch
, regnum
))
4025 if (i386_word_regnum_p (gdbarch
, regnum
))
4028 if (i386_dword_regnum_p (gdbarch
, regnum
))
4031 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4032 if (group
== i386_mmx_reggroup
)
4033 return mmx_regnum_p
;
4035 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4036 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4037 if (group
== i386_sse_reggroup
)
4038 return xmm_regnum_p
|| mxcsr_regnum_p
;
4040 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4041 if (group
== vector_reggroup
)
4042 return (mmx_regnum_p
4046 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
4047 == I386_XSTATE_SSE_MASK
)));
4049 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4050 || i386_fpc_regnum_p (gdbarch
, regnum
));
4051 if (group
== float_reggroup
)
4054 /* For "info reg all", don't include upper YMM registers nor XMM
4055 registers when AVX is supported. */
4056 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4057 if (group
== all_reggroup
4059 && (tdep
->xcr0
& I386_XSTATE_AVX
))
4063 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4064 if (group
== all_reggroup
4065 && ((bnd_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4066 return bnd_regnum_p
;
4068 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4069 if (group
== all_reggroup
4070 && ((bndr_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4073 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4074 if (group
== all_reggroup
4075 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4076 return mpx_ctrl_regnum_p
;
4078 if (group
== general_reggroup
)
4079 return (!fp_regnum_p
4087 && !mpx_ctrl_regnum_p
);
4089 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4093 /* Get the ARGIth function argument for the current function. */
4096 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4099 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4100 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4101 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4102 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4106 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
4108 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
4110 /* On i386, breakpoint is exactly 1 byte long, so we just
4111 adjust the PC in the regcache. */
4113 regcache_write_pc (regcache
, current_pc
);
4117 #define PREFIX_REPZ 0x01
4118 #define PREFIX_REPNZ 0x02
4119 #define PREFIX_LOCK 0x04
4120 #define PREFIX_DATA 0x08
4121 #define PREFIX_ADDR 0x10
4133 /* i386 arith/logic operations */
4146 struct i386_record_s
4148 struct gdbarch
*gdbarch
;
4149 struct regcache
*regcache
;
4150 CORE_ADDR orig_addr
;
4156 uint8_t mod
, reg
, rm
;
4165 /* Parse the "modrm" part of the memory address irp->addr points at.
4166 Returns -1 if something goes wrong, 0 otherwise. */
4169 i386_record_modrm (struct i386_record_s
*irp
)
4171 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4173 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4177 irp
->mod
= (irp
->modrm
>> 6) & 3;
4178 irp
->reg
= (irp
->modrm
>> 3) & 7;
4179 irp
->rm
= irp
->modrm
& 7;
4184 /* Extract the memory address that the current instruction writes to,
4185 and return it in *ADDR. Return -1 if something goes wrong. */
4188 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4190 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4203 uint8_t base
= irp
->rm
;
4208 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4211 scale
= (byte
>> 6) & 3;
4212 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4220 if ((base
& 7) == 5)
4223 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4226 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4227 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4228 *addr
+= irp
->addr
+ irp
->rip_offset
;
4232 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4235 *addr
= (int8_t) buf
[0];
4238 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4240 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4248 if (base
== 4 && irp
->popl_esp_hack
)
4249 *addr
+= irp
->popl_esp_hack
;
4250 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4253 if (irp
->aflag
== 2)
4258 *addr
= (uint32_t) (offset64
+ *addr
);
4260 if (havesib
&& (index
!= 4 || scale
!= 0))
4262 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4264 if (irp
->aflag
== 2)
4265 *addr
+= offset64
<< scale
;
4267 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4278 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4281 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4287 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4290 *addr
= (int8_t) buf
[0];
4293 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4296 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4303 regcache_raw_read_unsigned (irp
->regcache
,
4304 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4306 *addr
= (uint32_t) (*addr
+ offset64
);
4307 regcache_raw_read_unsigned (irp
->regcache
,
4308 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4310 *addr
= (uint32_t) (*addr
+ offset64
);
4313 regcache_raw_read_unsigned (irp
->regcache
,
4314 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4316 *addr
= (uint32_t) (*addr
+ offset64
);
4317 regcache_raw_read_unsigned (irp
->regcache
,
4318 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4320 *addr
= (uint32_t) (*addr
+ offset64
);
4323 regcache_raw_read_unsigned (irp
->regcache
,
4324 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4326 *addr
= (uint32_t) (*addr
+ offset64
);
4327 regcache_raw_read_unsigned (irp
->regcache
,
4328 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4330 *addr
= (uint32_t) (*addr
+ offset64
);
4333 regcache_raw_read_unsigned (irp
->regcache
,
4334 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4336 *addr
= (uint32_t) (*addr
+ offset64
);
4337 regcache_raw_read_unsigned (irp
->regcache
,
4338 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4340 *addr
= (uint32_t) (*addr
+ offset64
);
4343 regcache_raw_read_unsigned (irp
->regcache
,
4344 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4346 *addr
= (uint32_t) (*addr
+ offset64
);
4349 regcache_raw_read_unsigned (irp
->regcache
,
4350 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4352 *addr
= (uint32_t) (*addr
+ offset64
);
4355 regcache_raw_read_unsigned (irp
->regcache
,
4356 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4358 *addr
= (uint32_t) (*addr
+ offset64
);
4361 regcache_raw_read_unsigned (irp
->regcache
,
4362 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4364 *addr
= (uint32_t) (*addr
+ offset64
);
4374 /* Record the address and contents of the memory that will be changed
4375 by the current instruction. Return -1 if something goes wrong, 0
4379 i386_record_lea_modrm (struct i386_record_s
*irp
)
4381 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4384 if (irp
->override
>= 0)
4386 if (record_full_memory_query
)
4390 target_terminal_ours ();
4392 Process record ignores the memory change of instruction at address %s\n\
4393 because it can't get the value of the segment register.\n\
4394 Do you want to stop the program?"),
4395 paddress (gdbarch
, irp
->orig_addr
));
4396 target_terminal_inferior ();
4404 if (i386_record_lea_modrm_addr (irp
, &addr
))
4407 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4413 /* Record the effects of a push operation. Return -1 if something
4414 goes wrong, 0 otherwise. */
4417 i386_record_push (struct i386_record_s
*irp
, int size
)
4421 if (record_full_arch_list_add_reg (irp
->regcache
,
4422 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4424 regcache_raw_read_unsigned (irp
->regcache
,
4425 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4427 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4434 /* Defines contents to record. */
4435 #define I386_SAVE_FPU_REGS 0xfffd
4436 #define I386_SAVE_FPU_ENV 0xfffe
4437 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4439 /* Record the values of the floating point registers which will be
4440 changed by the current instruction. Returns -1 if something is
4441 wrong, 0 otherwise. */
4443 static int i386_record_floats (struct gdbarch
*gdbarch
,
4444 struct i386_record_s
*ir
,
4447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4450 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4451 happen. Currently we store st0-st7 registers, but we need not store all
4452 registers all the time, in future we use ftag register and record only
4453 those who are not marked as an empty. */
4455 if (I386_SAVE_FPU_REGS
== iregnum
)
4457 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4459 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4463 else if (I386_SAVE_FPU_ENV
== iregnum
)
4465 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4467 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4471 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4473 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4475 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4479 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4480 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4482 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4487 /* Parameter error. */
4490 if(I386_SAVE_FPU_ENV
!= iregnum
)
4492 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4494 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4501 /* Parse the current instruction, and record the values of the
4502 registers and memory that will be changed by the current
4503 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4505 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4506 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4509 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4510 CORE_ADDR input_addr
)
4512 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4518 gdb_byte buf
[MAX_REGISTER_SIZE
];
4519 struct i386_record_s ir
;
4520 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4524 memset (&ir
, 0, sizeof (struct i386_record_s
));
4525 ir
.regcache
= regcache
;
4526 ir
.addr
= input_addr
;
4527 ir
.orig_addr
= input_addr
;
4531 ir
.popl_esp_hack
= 0;
4532 ir
.regmap
= tdep
->record_regmap
;
4533 ir
.gdbarch
= gdbarch
;
4535 if (record_debug
> 1)
4536 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4538 paddress (gdbarch
, ir
.addr
));
4543 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4546 switch (opcode8
) /* Instruction prefixes */
4548 case REPE_PREFIX_OPCODE
:
4549 prefixes
|= PREFIX_REPZ
;
4551 case REPNE_PREFIX_OPCODE
:
4552 prefixes
|= PREFIX_REPNZ
;
4554 case LOCK_PREFIX_OPCODE
:
4555 prefixes
|= PREFIX_LOCK
;
4557 case CS_PREFIX_OPCODE
:
4558 ir
.override
= X86_RECORD_CS_REGNUM
;
4560 case SS_PREFIX_OPCODE
:
4561 ir
.override
= X86_RECORD_SS_REGNUM
;
4563 case DS_PREFIX_OPCODE
:
4564 ir
.override
= X86_RECORD_DS_REGNUM
;
4566 case ES_PREFIX_OPCODE
:
4567 ir
.override
= X86_RECORD_ES_REGNUM
;
4569 case FS_PREFIX_OPCODE
:
4570 ir
.override
= X86_RECORD_FS_REGNUM
;
4572 case GS_PREFIX_OPCODE
:
4573 ir
.override
= X86_RECORD_GS_REGNUM
;
4575 case DATA_PREFIX_OPCODE
:
4576 prefixes
|= PREFIX_DATA
;
4578 case ADDR_PREFIX_OPCODE
:
4579 prefixes
|= PREFIX_ADDR
;
4581 case 0x40: /* i386 inc %eax */
4582 case 0x41: /* i386 inc %ecx */
4583 case 0x42: /* i386 inc %edx */
4584 case 0x43: /* i386 inc %ebx */
4585 case 0x44: /* i386 inc %esp */
4586 case 0x45: /* i386 inc %ebp */
4587 case 0x46: /* i386 inc %esi */
4588 case 0x47: /* i386 inc %edi */
4589 case 0x48: /* i386 dec %eax */
4590 case 0x49: /* i386 dec %ecx */
4591 case 0x4a: /* i386 dec %edx */
4592 case 0x4b: /* i386 dec %ebx */
4593 case 0x4c: /* i386 dec %esp */
4594 case 0x4d: /* i386 dec %ebp */
4595 case 0x4e: /* i386 dec %esi */
4596 case 0x4f: /* i386 dec %edi */
4597 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4600 rex_w
= (opcode8
>> 3) & 1;
4601 rex_r
= (opcode8
& 0x4) << 1;
4602 ir
.rex_x
= (opcode8
& 0x2) << 2;
4603 ir
.rex_b
= (opcode8
& 0x1) << 3;
4605 else /* 32 bit target */
4614 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4620 if (prefixes
& PREFIX_DATA
)
4623 if (prefixes
& PREFIX_ADDR
)
4625 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4628 /* Now check op code. */
4629 opcode
= (uint32_t) opcode8
;
4634 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4637 opcode
= (uint32_t) opcode8
| 0x0f00;
4641 case 0x00: /* arith & logic */
4689 if (((opcode
>> 3) & 7) != OP_CMPL
)
4691 if ((opcode
& 1) == 0)
4694 ir
.ot
= ir
.dflag
+ OT_WORD
;
4696 switch ((opcode
>> 1) & 3)
4698 case 0: /* OP Ev, Gv */
4699 if (i386_record_modrm (&ir
))
4703 if (i386_record_lea_modrm (&ir
))
4709 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4714 case 1: /* OP Gv, Ev */
4715 if (i386_record_modrm (&ir
))
4718 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4720 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4722 case 2: /* OP A, Iv */
4723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4730 case 0x80: /* GRP1 */
4734 if (i386_record_modrm (&ir
))
4737 if (ir
.reg
!= OP_CMPL
)
4739 if ((opcode
& 1) == 0)
4742 ir
.ot
= ir
.dflag
+ OT_WORD
;
4749 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4750 if (i386_record_lea_modrm (&ir
))
4754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4756 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4759 case 0x40: /* inc */
4768 case 0x48: /* dec */
4777 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
4778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4781 case 0xf6: /* GRP3 */
4783 if ((opcode
& 1) == 0)
4786 ir
.ot
= ir
.dflag
+ OT_WORD
;
4787 if (i386_record_modrm (&ir
))
4790 if (ir
.mod
!= 3 && ir
.reg
== 0)
4791 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4796 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4802 if (i386_record_lea_modrm (&ir
))
4808 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4812 if (ir
.reg
== 3) /* neg */
4813 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4820 if (ir
.ot
!= OT_BYTE
)
4821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4822 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4826 opcode
= opcode
<< 8 | ir
.modrm
;
4832 case 0xfe: /* GRP4 */
4833 case 0xff: /* GRP5 */
4834 if (i386_record_modrm (&ir
))
4836 if (ir
.reg
>= 2 && opcode
== 0xfe)
4839 opcode
= opcode
<< 8 | ir
.modrm
;
4846 if ((opcode
& 1) == 0)
4849 ir
.ot
= ir
.dflag
+ OT_WORD
;
4852 if (i386_record_lea_modrm (&ir
))
4858 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4860 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4862 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4865 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4867 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4869 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4872 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4873 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4879 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4882 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4884 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4889 opcode
= opcode
<< 8 | ir
.modrm
;
4895 case 0x84: /* test */
4899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4902 case 0x98: /* CWDE/CBW */
4903 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4906 case 0x99: /* CDQ/CWD */
4907 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4908 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4911 case 0x0faf: /* imul */
4914 ir
.ot
= ir
.dflag
+ OT_WORD
;
4915 if (i386_record_modrm (&ir
))
4918 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4919 else if (opcode
== 0x6b)
4922 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4925 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4928 case 0x0fc0: /* xadd */
4930 if ((opcode
& 1) == 0)
4933 ir
.ot
= ir
.dflag
+ OT_WORD
;
4934 if (i386_record_modrm (&ir
))
4939 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4941 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4942 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4944 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4948 if (i386_record_lea_modrm (&ir
))
4950 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4952 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4957 case 0x0fb0: /* cmpxchg */
4959 if ((opcode
& 1) == 0)
4962 ir
.ot
= ir
.dflag
+ OT_WORD
;
4963 if (i386_record_modrm (&ir
))
4968 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4969 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4976 if (i386_record_lea_modrm (&ir
))
4979 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4982 case 0x0fc7: /* cmpxchg8b */
4983 if (i386_record_modrm (&ir
))
4988 opcode
= opcode
<< 8 | ir
.modrm
;
4991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4993 if (i386_record_lea_modrm (&ir
))
4995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4998 case 0x50: /* push */
5008 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5010 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5014 case 0x06: /* push es */
5015 case 0x0e: /* push cs */
5016 case 0x16: /* push ss */
5017 case 0x1e: /* push ds */
5018 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5023 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5027 case 0x0fa0: /* push fs */
5028 case 0x0fa8: /* push gs */
5029 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5034 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5038 case 0x60: /* pusha */
5039 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5044 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5048 case 0x58: /* pop */
5056 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5057 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5060 case 0x61: /* popa */
5061 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5066 for (regnum
= X86_RECORD_REAX_REGNUM
;
5067 regnum
<= X86_RECORD_REDI_REGNUM
;
5069 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5072 case 0x8f: /* pop */
5073 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5074 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5076 ir
.ot
= ir
.dflag
+ OT_WORD
;
5077 if (i386_record_modrm (&ir
))
5080 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5083 ir
.popl_esp_hack
= 1 << ir
.ot
;
5084 if (i386_record_lea_modrm (&ir
))
5087 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5090 case 0xc8: /* enter */
5091 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5092 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5094 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5098 case 0xc9: /* leave */
5099 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5100 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5103 case 0x07: /* pop es */
5104 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5109 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5110 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5111 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5114 case 0x17: /* pop ss */
5115 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5121 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5122 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5125 case 0x1f: /* pop ds */
5126 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5131 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5132 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5133 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5136 case 0x0fa1: /* pop fs */
5137 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5138 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5139 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5142 case 0x0fa9: /* pop gs */
5143 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5145 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5148 case 0x88: /* mov */
5152 if ((opcode
& 1) == 0)
5155 ir
.ot
= ir
.dflag
+ OT_WORD
;
5157 if (i386_record_modrm (&ir
))
5162 if (opcode
== 0xc6 || opcode
== 0xc7)
5163 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5164 if (i386_record_lea_modrm (&ir
))
5169 if (opcode
== 0xc6 || opcode
== 0xc7)
5171 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5173 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5177 case 0x8a: /* mov */
5179 if ((opcode
& 1) == 0)
5182 ir
.ot
= ir
.dflag
+ OT_WORD
;
5183 if (i386_record_modrm (&ir
))
5186 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5188 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5191 case 0x8c: /* mov seg */
5192 if (i386_record_modrm (&ir
))
5197 opcode
= opcode
<< 8 | ir
.modrm
;
5202 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5206 if (i386_record_lea_modrm (&ir
))
5211 case 0x8e: /* mov seg */
5212 if (i386_record_modrm (&ir
))
5217 regnum
= X86_RECORD_ES_REGNUM
;
5220 regnum
= X86_RECORD_SS_REGNUM
;
5223 regnum
= X86_RECORD_DS_REGNUM
;
5226 regnum
= X86_RECORD_FS_REGNUM
;
5229 regnum
= X86_RECORD_GS_REGNUM
;
5233 opcode
= opcode
<< 8 | ir
.modrm
;
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5241 case 0x0fb6: /* movzbS */
5242 case 0x0fb7: /* movzwS */
5243 case 0x0fbe: /* movsbS */
5244 case 0x0fbf: /* movswS */
5245 if (i386_record_modrm (&ir
))
5247 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5250 case 0x8d: /* lea */
5251 if (i386_record_modrm (&ir
))
5256 opcode
= opcode
<< 8 | ir
.modrm
;
5261 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5263 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5266 case 0xa0: /* mov EAX */
5269 case 0xd7: /* xlat */
5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5273 case 0xa2: /* mov EAX */
5275 if (ir
.override
>= 0)
5277 if (record_full_memory_query
)
5281 target_terminal_ours ();
5283 Process record ignores the memory change of instruction at address %s\n\
5284 because it can't get the value of the segment register.\n\
5285 Do you want to stop the program?"),
5286 paddress (gdbarch
, ir
.orig_addr
));
5287 target_terminal_inferior ();
5294 if ((opcode
& 1) == 0)
5297 ir
.ot
= ir
.dflag
+ OT_WORD
;
5300 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5303 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5307 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5310 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5314 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5317 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5319 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5324 case 0xb0: /* mov R, Ib */
5332 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5333 ? ((opcode
& 0x7) | ir
.rex_b
)
5334 : ((opcode
& 0x7) & 0x3));
5337 case 0xb8: /* mov R, Iv */
5345 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5348 case 0x91: /* xchg R, EAX */
5355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5356 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5359 case 0x86: /* xchg Ev, Gv */
5361 if ((opcode
& 1) == 0)
5364 ir
.ot
= ir
.dflag
+ OT_WORD
;
5365 if (i386_record_modrm (&ir
))
5370 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5376 if (i386_record_lea_modrm (&ir
))
5380 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5385 case 0xc4: /* les Gv */
5386 case 0xc5: /* lds Gv */
5387 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5393 case 0x0fb2: /* lss Gv */
5394 case 0x0fb4: /* lfs Gv */
5395 case 0x0fb5: /* lgs Gv */
5396 if (i386_record_modrm (&ir
))
5404 opcode
= opcode
<< 8 | ir
.modrm
;
5409 case 0xc4: /* les Gv */
5410 regnum
= X86_RECORD_ES_REGNUM
;
5412 case 0xc5: /* lds Gv */
5413 regnum
= X86_RECORD_DS_REGNUM
;
5415 case 0x0fb2: /* lss Gv */
5416 regnum
= X86_RECORD_SS_REGNUM
;
5418 case 0x0fb4: /* lfs Gv */
5419 regnum
= X86_RECORD_FS_REGNUM
;
5421 case 0x0fb5: /* lgs Gv */
5422 regnum
= X86_RECORD_GS_REGNUM
;
5425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5430 case 0xc0: /* shifts */
5436 if ((opcode
& 1) == 0)
5439 ir
.ot
= ir
.dflag
+ OT_WORD
;
5440 if (i386_record_modrm (&ir
))
5442 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5444 if (i386_record_lea_modrm (&ir
))
5450 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5454 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5461 if (i386_record_modrm (&ir
))
5465 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5470 if (i386_record_lea_modrm (&ir
))
5475 case 0xd8: /* Floats. */
5483 if (i386_record_modrm (&ir
))
5485 ir
.reg
|= ((opcode
& 7) << 3);
5491 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5499 /* For fcom, ficom nothing to do. */
5505 /* For fcomp, ficomp pop FPU stack, store all. */
5506 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5533 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5534 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5535 of code, always affects st(0) register. */
5536 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5560 /* Handling fld, fild. */
5561 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5565 switch (ir
.reg
>> 4)
5568 if (record_full_arch_list_add_mem (addr64
, 4))
5572 if (record_full_arch_list_add_mem (addr64
, 8))
5578 if (record_full_arch_list_add_mem (addr64
, 2))
5584 switch (ir
.reg
>> 4)
5587 if (record_full_arch_list_add_mem (addr64
, 4))
5589 if (3 == (ir
.reg
& 7))
5591 /* For fstp m32fp. */
5592 if (i386_record_floats (gdbarch
, &ir
,
5593 I386_SAVE_FPU_REGS
))
5598 if (record_full_arch_list_add_mem (addr64
, 4))
5600 if ((3 == (ir
.reg
& 7))
5601 || (5 == (ir
.reg
& 7))
5602 || (7 == (ir
.reg
& 7)))
5604 /* For fstp insn. */
5605 if (i386_record_floats (gdbarch
, &ir
,
5606 I386_SAVE_FPU_REGS
))
5611 if (record_full_arch_list_add_mem (addr64
, 8))
5613 if (3 == (ir
.reg
& 7))
5615 /* For fstp m64fp. */
5616 if (i386_record_floats (gdbarch
, &ir
,
5617 I386_SAVE_FPU_REGS
))
5622 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5624 /* For fistp, fbld, fild, fbstp. */
5625 if (i386_record_floats (gdbarch
, &ir
,
5626 I386_SAVE_FPU_REGS
))
5631 if (record_full_arch_list_add_mem (addr64
, 2))
5640 if (i386_record_floats (gdbarch
, &ir
,
5641 I386_SAVE_FPU_ENV_REG_STACK
))
5646 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5651 if (i386_record_floats (gdbarch
, &ir
,
5652 I386_SAVE_FPU_ENV_REG_STACK
))
5658 if (record_full_arch_list_add_mem (addr64
, 28))
5663 if (record_full_arch_list_add_mem (addr64
, 14))
5669 if (record_full_arch_list_add_mem (addr64
, 2))
5671 /* Insn fstp, fbstp. */
5672 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5677 if (record_full_arch_list_add_mem (addr64
, 10))
5683 if (record_full_arch_list_add_mem (addr64
, 28))
5689 if (record_full_arch_list_add_mem (addr64
, 14))
5693 if (record_full_arch_list_add_mem (addr64
, 80))
5696 if (i386_record_floats (gdbarch
, &ir
,
5697 I386_SAVE_FPU_ENV_REG_STACK
))
5701 if (record_full_arch_list_add_mem (addr64
, 8))
5704 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5709 opcode
= opcode
<< 8 | ir
.modrm
;
5714 /* Opcode is an extension of modR/M byte. */
5720 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5724 if (0x0c == (ir
.modrm
>> 4))
5726 if ((ir
.modrm
& 0x0f) <= 7)
5728 if (i386_record_floats (gdbarch
, &ir
,
5729 I386_SAVE_FPU_REGS
))
5734 if (i386_record_floats (gdbarch
, &ir
,
5735 I387_ST0_REGNUM (tdep
)))
5737 /* If only st(0) is changing, then we have already
5739 if ((ir
.modrm
& 0x0f) - 0x08)
5741 if (i386_record_floats (gdbarch
, &ir
,
5742 I387_ST0_REGNUM (tdep
) +
5743 ((ir
.modrm
& 0x0f) - 0x08)))
5761 if (i386_record_floats (gdbarch
, &ir
,
5762 I387_ST0_REGNUM (tdep
)))
5780 if (i386_record_floats (gdbarch
, &ir
,
5781 I386_SAVE_FPU_REGS
))
5785 if (i386_record_floats (gdbarch
, &ir
,
5786 I387_ST0_REGNUM (tdep
)))
5788 if (i386_record_floats (gdbarch
, &ir
,
5789 I387_ST0_REGNUM (tdep
) + 1))
5796 if (0xe9 == ir
.modrm
)
5798 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5801 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5803 if (i386_record_floats (gdbarch
, &ir
,
5804 I387_ST0_REGNUM (tdep
)))
5806 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5808 if (i386_record_floats (gdbarch
, &ir
,
5809 I387_ST0_REGNUM (tdep
) +
5813 else if ((ir
.modrm
& 0x0f) - 0x08)
5815 if (i386_record_floats (gdbarch
, &ir
,
5816 I387_ST0_REGNUM (tdep
) +
5817 ((ir
.modrm
& 0x0f) - 0x08)))
5823 if (0xe3 == ir
.modrm
)
5825 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5828 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5830 if (i386_record_floats (gdbarch
, &ir
,
5831 I387_ST0_REGNUM (tdep
)))
5833 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5835 if (i386_record_floats (gdbarch
, &ir
,
5836 I387_ST0_REGNUM (tdep
) +
5840 else if ((ir
.modrm
& 0x0f) - 0x08)
5842 if (i386_record_floats (gdbarch
, &ir
,
5843 I387_ST0_REGNUM (tdep
) +
5844 ((ir
.modrm
& 0x0f) - 0x08)))
5850 if ((0x0c == ir
.modrm
>> 4)
5851 || (0x0d == ir
.modrm
>> 4)
5852 || (0x0f == ir
.modrm
>> 4))
5854 if ((ir
.modrm
& 0x0f) <= 7)
5856 if (i386_record_floats (gdbarch
, &ir
,
5857 I387_ST0_REGNUM (tdep
) +
5863 if (i386_record_floats (gdbarch
, &ir
,
5864 I387_ST0_REGNUM (tdep
) +
5865 ((ir
.modrm
& 0x0f) - 0x08)))
5871 if (0x0c == ir
.modrm
>> 4)
5873 if (i386_record_floats (gdbarch
, &ir
,
5874 I387_FTAG_REGNUM (tdep
)))
5877 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5879 if ((ir
.modrm
& 0x0f) <= 7)
5881 if (i386_record_floats (gdbarch
, &ir
,
5882 I387_ST0_REGNUM (tdep
) +
5888 if (i386_record_floats (gdbarch
, &ir
,
5889 I386_SAVE_FPU_REGS
))
5895 if ((0x0c == ir
.modrm
>> 4)
5896 || (0x0e == ir
.modrm
>> 4)
5897 || (0x0f == ir
.modrm
>> 4)
5898 || (0xd9 == ir
.modrm
))
5900 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5905 if (0xe0 == ir
.modrm
)
5907 if (record_full_arch_list_add_reg (ir
.regcache
,
5911 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5913 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5921 case 0xa4: /* movsS */
5923 case 0xaa: /* stosS */
5925 case 0x6c: /* insS */
5927 regcache_raw_read_unsigned (ir
.regcache
,
5928 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5934 if ((opcode
& 1) == 0)
5937 ir
.ot
= ir
.dflag
+ OT_WORD
;
5938 regcache_raw_read_unsigned (ir
.regcache
,
5939 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5942 regcache_raw_read_unsigned (ir
.regcache
,
5943 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5945 regcache_raw_read_unsigned (ir
.regcache
,
5946 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5948 if (ir
.aflag
&& (es
!= ds
))
5950 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5951 if (record_full_memory_query
)
5955 target_terminal_ours ();
5957 Process record ignores the memory change of instruction at address %s\n\
5958 because it can't get the value of the segment register.\n\
5959 Do you want to stop the program?"),
5960 paddress (gdbarch
, ir
.orig_addr
));
5961 target_terminal_inferior ();
5968 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5972 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5974 if (opcode
== 0xa4 || opcode
== 0xa5)
5975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5976 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5981 case 0xa6: /* cmpsS */
5983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5985 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5987 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 case 0xac: /* lodsS */
5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5994 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5996 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5999 case 0xae: /* scasS */
6001 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6002 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6007 case 0x6e: /* outsS */
6009 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6010 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6011 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6012 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6015 case 0xe4: /* port I/O */
6019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6020 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6030 case 0xc2: /* ret im */
6031 case 0xc3: /* ret */
6032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6033 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6036 case 0xca: /* lret im */
6037 case 0xcb: /* lret */
6038 case 0xcf: /* iret */
6039 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6041 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6044 case 0xe8: /* call im */
6045 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6047 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6051 case 0x9a: /* lcall im */
6052 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6057 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6058 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6062 case 0xe9: /* jmp im */
6063 case 0xea: /* ljmp im */
6064 case 0xeb: /* jmp Jb */
6065 case 0x70: /* jcc Jb */
6081 case 0x0f80: /* jcc Jv */
6099 case 0x0f90: /* setcc Gv */
6115 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6117 if (i386_record_modrm (&ir
))
6120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6124 if (i386_record_lea_modrm (&ir
))
6129 case 0x0f40: /* cmov Gv, Ev */
6145 if (i386_record_modrm (&ir
))
6148 if (ir
.dflag
== OT_BYTE
)
6150 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6154 case 0x9c: /* pushf */
6155 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6156 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6158 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6162 case 0x9d: /* popf */
6163 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6164 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6167 case 0x9e: /* sahf */
6168 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6174 case 0xf5: /* cmc */
6175 case 0xf8: /* clc */
6176 case 0xf9: /* stc */
6177 case 0xfc: /* cld */
6178 case 0xfd: /* std */
6179 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6182 case 0x9f: /* lahf */
6183 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6188 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6192 /* bit operations */
6193 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6194 ir
.ot
= ir
.dflag
+ OT_WORD
;
6195 if (i386_record_modrm (&ir
))
6200 opcode
= opcode
<< 8 | ir
.modrm
;
6206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6209 if (i386_record_lea_modrm (&ir
))
6213 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6216 case 0x0fa3: /* bt Gv, Ev */
6217 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6220 case 0x0fab: /* bts */
6221 case 0x0fb3: /* btr */
6222 case 0x0fbb: /* btc */
6223 ir
.ot
= ir
.dflag
+ OT_WORD
;
6224 if (i386_record_modrm (&ir
))
6227 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6231 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6233 regcache_raw_read_unsigned (ir
.regcache
,
6234 ir
.regmap
[ir
.reg
| rex_r
],
6239 addr64
+= ((int16_t) addr
>> 4) << 4;
6242 addr64
+= ((int32_t) addr
>> 5) << 5;
6245 addr64
+= ((int64_t) addr
>> 6) << 6;
6248 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6250 if (i386_record_lea_modrm (&ir
))
6253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6256 case 0x0fbc: /* bsf */
6257 case 0x0fbd: /* bsr */
6258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6263 case 0x27: /* daa */
6264 case 0x2f: /* das */
6265 case 0x37: /* aaa */
6266 case 0x3f: /* aas */
6267 case 0xd4: /* aam */
6268 case 0xd5: /* aad */
6269 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6274 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6279 case 0x90: /* nop */
6280 if (prefixes
& PREFIX_LOCK
)
6287 case 0x9b: /* fwait */
6288 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6290 opcode
= (uint32_t) opcode8
;
6296 case 0xcc: /* int3 */
6297 printf_unfiltered (_("Process record does not support instruction "
6304 case 0xcd: /* int */
6308 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6311 if (interrupt
!= 0x80
6312 || tdep
->i386_intx80_record
== NULL
)
6314 printf_unfiltered (_("Process record does not support "
6315 "instruction int 0x%02x.\n"),
6320 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6327 case 0xce: /* into */
6328 printf_unfiltered (_("Process record does not support "
6329 "instruction into.\n"));
6334 case 0xfa: /* cli */
6335 case 0xfb: /* sti */
6338 case 0x62: /* bound */
6339 printf_unfiltered (_("Process record does not support "
6340 "instruction bound.\n"));
6345 case 0x0fc8: /* bswap reg */
6353 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6356 case 0xd6: /* salc */
6357 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6362 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6366 case 0xe0: /* loopnz */
6367 case 0xe1: /* loopz */
6368 case 0xe2: /* loop */
6369 case 0xe3: /* jecxz */
6370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6374 case 0x0f30: /* wrmsr */
6375 printf_unfiltered (_("Process record does not support "
6376 "instruction wrmsr.\n"));
6381 case 0x0f32: /* rdmsr */
6382 printf_unfiltered (_("Process record does not support "
6383 "instruction rdmsr.\n"));
6388 case 0x0f31: /* rdtsc */
6389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6390 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6393 case 0x0f34: /* sysenter */
6396 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6401 if (tdep
->i386_sysenter_record
== NULL
)
6403 printf_unfiltered (_("Process record does not support "
6404 "instruction sysenter.\n"));
6408 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6414 case 0x0f35: /* sysexit */
6415 printf_unfiltered (_("Process record does not support "
6416 "instruction sysexit.\n"));
6421 case 0x0f05: /* syscall */
6424 if (tdep
->i386_syscall_record
== NULL
)
6426 printf_unfiltered (_("Process record does not support "
6427 "instruction syscall.\n"));
6431 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6437 case 0x0f07: /* sysret */
6438 printf_unfiltered (_("Process record does not support "
6439 "instruction sysret.\n"));
6444 case 0x0fa2: /* cpuid */
6445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6451 case 0xf4: /* hlt */
6452 printf_unfiltered (_("Process record does not support "
6453 "instruction hlt.\n"));
6459 if (i386_record_modrm (&ir
))
6466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6470 if (i386_record_lea_modrm (&ir
))
6479 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6483 opcode
= opcode
<< 8 | ir
.modrm
;
6490 if (i386_record_modrm (&ir
))
6501 opcode
= opcode
<< 8 | ir
.modrm
;
6504 if (ir
.override
>= 0)
6506 if (record_full_memory_query
)
6510 target_terminal_ours ();
6512 Process record ignores the memory change of instruction at address %s\n\
6513 because it can't get the value of the segment register.\n\
6514 Do you want to stop the program?"),
6515 paddress (gdbarch
, ir
.orig_addr
));
6516 target_terminal_inferior ();
6523 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6525 if (record_full_arch_list_add_mem (addr64
, 2))
6528 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6530 if (record_full_arch_list_add_mem (addr64
, 8))
6535 if (record_full_arch_list_add_mem (addr64
, 4))
6546 case 0: /* monitor */
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6553 opcode
= opcode
<< 8 | ir
.modrm
;
6561 if (ir
.override
>= 0)
6563 if (record_full_memory_query
)
6567 target_terminal_ours ();
6569 Process record ignores the memory change of instruction at address %s\n\
6570 because it can't get the value of the segment register.\n\
6571 Do you want to stop the program?"),
6572 paddress (gdbarch
, ir
.orig_addr
));
6573 target_terminal_inferior ();
6582 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6584 if (record_full_arch_list_add_mem (addr64
, 2))
6587 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6589 if (record_full_arch_list_add_mem (addr64
, 8))
6594 if (record_full_arch_list_add_mem (addr64
, 4))
6606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6611 else if (ir
.rm
== 1)
6618 opcode
= opcode
<< 8 | ir
.modrm
;
6625 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6631 if (i386_record_lea_modrm (&ir
))
6634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6639 case 7: /* invlpg */
6642 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6647 opcode
= opcode
<< 8 | ir
.modrm
;
6652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6656 opcode
= opcode
<< 8 | ir
.modrm
;
6662 case 0x0f08: /* invd */
6663 case 0x0f09: /* wbinvd */
6666 case 0x63: /* arpl */
6667 if (i386_record_modrm (&ir
))
6669 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6672 ? (ir
.reg
| rex_r
) : ir
.rm
);
6676 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6677 if (i386_record_lea_modrm (&ir
))
6680 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6684 case 0x0f02: /* lar */
6685 case 0x0f03: /* lsl */
6686 if (i386_record_modrm (&ir
))
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6693 if (i386_record_modrm (&ir
))
6695 if (ir
.mod
== 3 && ir
.reg
== 3)
6698 opcode
= opcode
<< 8 | ir
.modrm
;
6710 /* nop (multi byte) */
6713 case 0x0f20: /* mov reg, crN */
6714 case 0x0f22: /* mov crN, reg */
6715 if (i386_record_modrm (&ir
))
6717 if ((ir
.modrm
& 0xc0) != 0xc0)
6720 opcode
= opcode
<< 8 | ir
.modrm
;
6731 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6733 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6737 opcode
= opcode
<< 8 | ir
.modrm
;
6743 case 0x0f21: /* mov reg, drN */
6744 case 0x0f23: /* mov drN, reg */
6745 if (i386_record_modrm (&ir
))
6747 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6748 || ir
.reg
== 5 || ir
.reg
>= 8)
6751 opcode
= opcode
<< 8 | ir
.modrm
;
6755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6757 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6760 case 0x0f06: /* clts */
6761 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6764 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6766 case 0x0f0d: /* 3DNow! prefetch */
6769 case 0x0f0e: /* 3DNow! femms */
6770 case 0x0f77: /* emms */
6771 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6773 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6776 case 0x0f0f: /* 3DNow! data */
6777 if (i386_record_modrm (&ir
))
6779 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6784 case 0x0c: /* 3DNow! pi2fw */
6785 case 0x0d: /* 3DNow! pi2fd */
6786 case 0x1c: /* 3DNow! pf2iw */
6787 case 0x1d: /* 3DNow! pf2id */
6788 case 0x8a: /* 3DNow! pfnacc */
6789 case 0x8e: /* 3DNow! pfpnacc */
6790 case 0x90: /* 3DNow! pfcmpge */
6791 case 0x94: /* 3DNow! pfmin */
6792 case 0x96: /* 3DNow! pfrcp */
6793 case 0x97: /* 3DNow! pfrsqrt */
6794 case 0x9a: /* 3DNow! pfsub */
6795 case 0x9e: /* 3DNow! pfadd */
6796 case 0xa0: /* 3DNow! pfcmpgt */
6797 case 0xa4: /* 3DNow! pfmax */
6798 case 0xa6: /* 3DNow! pfrcpit1 */
6799 case 0xa7: /* 3DNow! pfrsqit1 */
6800 case 0xaa: /* 3DNow! pfsubr */
6801 case 0xae: /* 3DNow! pfacc */
6802 case 0xb0: /* 3DNow! pfcmpeq */
6803 case 0xb4: /* 3DNow! pfmul */
6804 case 0xb6: /* 3DNow! pfrcpit2 */
6805 case 0xb7: /* 3DNow! pmulhrw */
6806 case 0xbb: /* 3DNow! pswapd */
6807 case 0xbf: /* 3DNow! pavgusb */
6808 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6809 goto no_support_3dnow_data
;
6810 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6814 no_support_3dnow_data
:
6815 opcode
= (opcode
<< 8) | opcode8
;
6821 case 0x0faa: /* rsm */
6822 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6823 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6824 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6827 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6828 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6834 if (i386_record_modrm (&ir
))
6838 case 0: /* fxsave */
6842 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6843 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6845 if (record_full_arch_list_add_mem (tmpu64
, 512))
6850 case 1: /* fxrstor */
6854 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6856 for (i
= I387_MM0_REGNUM (tdep
);
6857 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6858 record_full_arch_list_add_reg (ir
.regcache
, i
);
6860 for (i
= I387_XMM0_REGNUM (tdep
);
6861 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6862 record_full_arch_list_add_reg (ir
.regcache
, i
);
6864 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6865 record_full_arch_list_add_reg (ir
.regcache
,
6866 I387_MXCSR_REGNUM(tdep
));
6868 for (i
= I387_ST0_REGNUM (tdep
);
6869 i386_fp_regnum_p (gdbarch
, i
); i
++)
6870 record_full_arch_list_add_reg (ir
.regcache
, i
);
6872 for (i
= I387_FCTRL_REGNUM (tdep
);
6873 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6874 record_full_arch_list_add_reg (ir
.regcache
, i
);
6878 case 2: /* ldmxcsr */
6879 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6881 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6884 case 3: /* stmxcsr */
6886 if (i386_record_lea_modrm (&ir
))
6890 case 5: /* lfence */
6891 case 6: /* mfence */
6892 case 7: /* sfence clflush */
6896 opcode
= (opcode
<< 8) | ir
.modrm
;
6902 case 0x0fc3: /* movnti */
6903 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6904 if (i386_record_modrm (&ir
))
6909 if (i386_record_lea_modrm (&ir
))
6913 /* Add prefix to opcode. */
7040 reswitch_prefix_add
:
7048 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7051 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7052 goto reswitch_prefix_add
;
7055 case 0x0f10: /* movups */
7056 case 0x660f10: /* movupd */
7057 case 0xf30f10: /* movss */
7058 case 0xf20f10: /* movsd */
7059 case 0x0f12: /* movlps */
7060 case 0x660f12: /* movlpd */
7061 case 0xf30f12: /* movsldup */
7062 case 0xf20f12: /* movddup */
7063 case 0x0f14: /* unpcklps */
7064 case 0x660f14: /* unpcklpd */
7065 case 0x0f15: /* unpckhps */
7066 case 0x660f15: /* unpckhpd */
7067 case 0x0f16: /* movhps */
7068 case 0x660f16: /* movhpd */
7069 case 0xf30f16: /* movshdup */
7070 case 0x0f28: /* movaps */
7071 case 0x660f28: /* movapd */
7072 case 0x0f2a: /* cvtpi2ps */
7073 case 0x660f2a: /* cvtpi2pd */
7074 case 0xf30f2a: /* cvtsi2ss */
7075 case 0xf20f2a: /* cvtsi2sd */
7076 case 0x0f2c: /* cvttps2pi */
7077 case 0x660f2c: /* cvttpd2pi */
7078 case 0x0f2d: /* cvtps2pi */
7079 case 0x660f2d: /* cvtpd2pi */
7080 case 0x660f3800: /* pshufb */
7081 case 0x660f3801: /* phaddw */
7082 case 0x660f3802: /* phaddd */
7083 case 0x660f3803: /* phaddsw */
7084 case 0x660f3804: /* pmaddubsw */
7085 case 0x660f3805: /* phsubw */
7086 case 0x660f3806: /* phsubd */
7087 case 0x660f3807: /* phsubsw */
7088 case 0x660f3808: /* psignb */
7089 case 0x660f3809: /* psignw */
7090 case 0x660f380a: /* psignd */
7091 case 0x660f380b: /* pmulhrsw */
7092 case 0x660f3810: /* pblendvb */
7093 case 0x660f3814: /* blendvps */
7094 case 0x660f3815: /* blendvpd */
7095 case 0x660f381c: /* pabsb */
7096 case 0x660f381d: /* pabsw */
7097 case 0x660f381e: /* pabsd */
7098 case 0x660f3820: /* pmovsxbw */
7099 case 0x660f3821: /* pmovsxbd */
7100 case 0x660f3822: /* pmovsxbq */
7101 case 0x660f3823: /* pmovsxwd */
7102 case 0x660f3824: /* pmovsxwq */
7103 case 0x660f3825: /* pmovsxdq */
7104 case 0x660f3828: /* pmuldq */
7105 case 0x660f3829: /* pcmpeqq */
7106 case 0x660f382a: /* movntdqa */
7107 case 0x660f3a08: /* roundps */
7108 case 0x660f3a09: /* roundpd */
7109 case 0x660f3a0a: /* roundss */
7110 case 0x660f3a0b: /* roundsd */
7111 case 0x660f3a0c: /* blendps */
7112 case 0x660f3a0d: /* blendpd */
7113 case 0x660f3a0e: /* pblendw */
7114 case 0x660f3a0f: /* palignr */
7115 case 0x660f3a20: /* pinsrb */
7116 case 0x660f3a21: /* insertps */
7117 case 0x660f3a22: /* pinsrd pinsrq */
7118 case 0x660f3a40: /* dpps */
7119 case 0x660f3a41: /* dppd */
7120 case 0x660f3a42: /* mpsadbw */
7121 case 0x660f3a60: /* pcmpestrm */
7122 case 0x660f3a61: /* pcmpestri */
7123 case 0x660f3a62: /* pcmpistrm */
7124 case 0x660f3a63: /* pcmpistri */
7125 case 0x0f51: /* sqrtps */
7126 case 0x660f51: /* sqrtpd */
7127 case 0xf20f51: /* sqrtsd */
7128 case 0xf30f51: /* sqrtss */
7129 case 0x0f52: /* rsqrtps */
7130 case 0xf30f52: /* rsqrtss */
7131 case 0x0f53: /* rcpps */
7132 case 0xf30f53: /* rcpss */
7133 case 0x0f54: /* andps */
7134 case 0x660f54: /* andpd */
7135 case 0x0f55: /* andnps */
7136 case 0x660f55: /* andnpd */
7137 case 0x0f56: /* orps */
7138 case 0x660f56: /* orpd */
7139 case 0x0f57: /* xorps */
7140 case 0x660f57: /* xorpd */
7141 case 0x0f58: /* addps */
7142 case 0x660f58: /* addpd */
7143 case 0xf20f58: /* addsd */
7144 case 0xf30f58: /* addss */
7145 case 0x0f59: /* mulps */
7146 case 0x660f59: /* mulpd */
7147 case 0xf20f59: /* mulsd */
7148 case 0xf30f59: /* mulss */
7149 case 0x0f5a: /* cvtps2pd */
7150 case 0x660f5a: /* cvtpd2ps */
7151 case 0xf20f5a: /* cvtsd2ss */
7152 case 0xf30f5a: /* cvtss2sd */
7153 case 0x0f5b: /* cvtdq2ps */
7154 case 0x660f5b: /* cvtps2dq */
7155 case 0xf30f5b: /* cvttps2dq */
7156 case 0x0f5c: /* subps */
7157 case 0x660f5c: /* subpd */
7158 case 0xf20f5c: /* subsd */
7159 case 0xf30f5c: /* subss */
7160 case 0x0f5d: /* minps */
7161 case 0x660f5d: /* minpd */
7162 case 0xf20f5d: /* minsd */
7163 case 0xf30f5d: /* minss */
7164 case 0x0f5e: /* divps */
7165 case 0x660f5e: /* divpd */
7166 case 0xf20f5e: /* divsd */
7167 case 0xf30f5e: /* divss */
7168 case 0x0f5f: /* maxps */
7169 case 0x660f5f: /* maxpd */
7170 case 0xf20f5f: /* maxsd */
7171 case 0xf30f5f: /* maxss */
7172 case 0x660f60: /* punpcklbw */
7173 case 0x660f61: /* punpcklwd */
7174 case 0x660f62: /* punpckldq */
7175 case 0x660f63: /* packsswb */
7176 case 0x660f64: /* pcmpgtb */
7177 case 0x660f65: /* pcmpgtw */
7178 case 0x660f66: /* pcmpgtd */
7179 case 0x660f67: /* packuswb */
7180 case 0x660f68: /* punpckhbw */
7181 case 0x660f69: /* punpckhwd */
7182 case 0x660f6a: /* punpckhdq */
7183 case 0x660f6b: /* packssdw */
7184 case 0x660f6c: /* punpcklqdq */
7185 case 0x660f6d: /* punpckhqdq */
7186 case 0x660f6e: /* movd */
7187 case 0x660f6f: /* movdqa */
7188 case 0xf30f6f: /* movdqu */
7189 case 0x660f70: /* pshufd */
7190 case 0xf20f70: /* pshuflw */
7191 case 0xf30f70: /* pshufhw */
7192 case 0x660f74: /* pcmpeqb */
7193 case 0x660f75: /* pcmpeqw */
7194 case 0x660f76: /* pcmpeqd */
7195 case 0x660f7c: /* haddpd */
7196 case 0xf20f7c: /* haddps */
7197 case 0x660f7d: /* hsubpd */
7198 case 0xf20f7d: /* hsubps */
7199 case 0xf30f7e: /* movq */
7200 case 0x0fc2: /* cmpps */
7201 case 0x660fc2: /* cmppd */
7202 case 0xf20fc2: /* cmpsd */
7203 case 0xf30fc2: /* cmpss */
7204 case 0x660fc4: /* pinsrw */
7205 case 0x0fc6: /* shufps */
7206 case 0x660fc6: /* shufpd */
7207 case 0x660fd0: /* addsubpd */
7208 case 0xf20fd0: /* addsubps */
7209 case 0x660fd1: /* psrlw */
7210 case 0x660fd2: /* psrld */
7211 case 0x660fd3: /* psrlq */
7212 case 0x660fd4: /* paddq */
7213 case 0x660fd5: /* pmullw */
7214 case 0xf30fd6: /* movq2dq */
7215 case 0x660fd8: /* psubusb */
7216 case 0x660fd9: /* psubusw */
7217 case 0x660fda: /* pminub */
7218 case 0x660fdb: /* pand */
7219 case 0x660fdc: /* paddusb */
7220 case 0x660fdd: /* paddusw */
7221 case 0x660fde: /* pmaxub */
7222 case 0x660fdf: /* pandn */
7223 case 0x660fe0: /* pavgb */
7224 case 0x660fe1: /* psraw */
7225 case 0x660fe2: /* psrad */
7226 case 0x660fe3: /* pavgw */
7227 case 0x660fe4: /* pmulhuw */
7228 case 0x660fe5: /* pmulhw */
7229 case 0x660fe6: /* cvttpd2dq */
7230 case 0xf20fe6: /* cvtpd2dq */
7231 case 0xf30fe6: /* cvtdq2pd */
7232 case 0x660fe8: /* psubsb */
7233 case 0x660fe9: /* psubsw */
7234 case 0x660fea: /* pminsw */
7235 case 0x660feb: /* por */
7236 case 0x660fec: /* paddsb */
7237 case 0x660fed: /* paddsw */
7238 case 0x660fee: /* pmaxsw */
7239 case 0x660fef: /* pxor */
7240 case 0xf20ff0: /* lddqu */
7241 case 0x660ff1: /* psllw */
7242 case 0x660ff2: /* pslld */
7243 case 0x660ff3: /* psllq */
7244 case 0x660ff4: /* pmuludq */
7245 case 0x660ff5: /* pmaddwd */
7246 case 0x660ff6: /* psadbw */
7247 case 0x660ff8: /* psubb */
7248 case 0x660ff9: /* psubw */
7249 case 0x660ffa: /* psubd */
7250 case 0x660ffb: /* psubq */
7251 case 0x660ffc: /* paddb */
7252 case 0x660ffd: /* paddw */
7253 case 0x660ffe: /* paddd */
7254 if (i386_record_modrm (&ir
))
7257 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7259 record_full_arch_list_add_reg (ir
.regcache
,
7260 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7261 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7265 case 0x0f11: /* movups */
7266 case 0x660f11: /* movupd */
7267 case 0xf30f11: /* movss */
7268 case 0xf20f11: /* movsd */
7269 case 0x0f13: /* movlps */
7270 case 0x660f13: /* movlpd */
7271 case 0x0f17: /* movhps */
7272 case 0x660f17: /* movhpd */
7273 case 0x0f29: /* movaps */
7274 case 0x660f29: /* movapd */
7275 case 0x660f3a14: /* pextrb */
7276 case 0x660f3a15: /* pextrw */
7277 case 0x660f3a16: /* pextrd pextrq */
7278 case 0x660f3a17: /* extractps */
7279 case 0x660f7f: /* movdqa */
7280 case 0xf30f7f: /* movdqu */
7281 if (i386_record_modrm (&ir
))
7285 if (opcode
== 0x0f13 || opcode
== 0x660f13
7286 || opcode
== 0x0f17 || opcode
== 0x660f17)
7289 if (!i386_xmm_regnum_p (gdbarch
,
7290 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7292 record_full_arch_list_add_reg (ir
.regcache
,
7293 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7315 if (i386_record_lea_modrm (&ir
))
7320 case 0x0f2b: /* movntps */
7321 case 0x660f2b: /* movntpd */
7322 case 0x0fe7: /* movntq */
7323 case 0x660fe7: /* movntdq */
7326 if (opcode
== 0x0fe7)
7330 if (i386_record_lea_modrm (&ir
))
7334 case 0xf30f2c: /* cvttss2si */
7335 case 0xf20f2c: /* cvttsd2si */
7336 case 0xf30f2d: /* cvtss2si */
7337 case 0xf20f2d: /* cvtsd2si */
7338 case 0xf20f38f0: /* crc32 */
7339 case 0xf20f38f1: /* crc32 */
7340 case 0x0f50: /* movmskps */
7341 case 0x660f50: /* movmskpd */
7342 case 0x0fc5: /* pextrw */
7343 case 0x660fc5: /* pextrw */
7344 case 0x0fd7: /* pmovmskb */
7345 case 0x660fd7: /* pmovmskb */
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7349 case 0x0f3800: /* pshufb */
7350 case 0x0f3801: /* phaddw */
7351 case 0x0f3802: /* phaddd */
7352 case 0x0f3803: /* phaddsw */
7353 case 0x0f3804: /* pmaddubsw */
7354 case 0x0f3805: /* phsubw */
7355 case 0x0f3806: /* phsubd */
7356 case 0x0f3807: /* phsubsw */
7357 case 0x0f3808: /* psignb */
7358 case 0x0f3809: /* psignw */
7359 case 0x0f380a: /* psignd */
7360 case 0x0f380b: /* pmulhrsw */
7361 case 0x0f381c: /* pabsb */
7362 case 0x0f381d: /* pabsw */
7363 case 0x0f381e: /* pabsd */
7364 case 0x0f382b: /* packusdw */
7365 case 0x0f3830: /* pmovzxbw */
7366 case 0x0f3831: /* pmovzxbd */
7367 case 0x0f3832: /* pmovzxbq */
7368 case 0x0f3833: /* pmovzxwd */
7369 case 0x0f3834: /* pmovzxwq */
7370 case 0x0f3835: /* pmovzxdq */
7371 case 0x0f3837: /* pcmpgtq */
7372 case 0x0f3838: /* pminsb */
7373 case 0x0f3839: /* pminsd */
7374 case 0x0f383a: /* pminuw */
7375 case 0x0f383b: /* pminud */
7376 case 0x0f383c: /* pmaxsb */
7377 case 0x0f383d: /* pmaxsd */
7378 case 0x0f383e: /* pmaxuw */
7379 case 0x0f383f: /* pmaxud */
7380 case 0x0f3840: /* pmulld */
7381 case 0x0f3841: /* phminposuw */
7382 case 0x0f3a0f: /* palignr */
7383 case 0x0f60: /* punpcklbw */
7384 case 0x0f61: /* punpcklwd */
7385 case 0x0f62: /* punpckldq */
7386 case 0x0f63: /* packsswb */
7387 case 0x0f64: /* pcmpgtb */
7388 case 0x0f65: /* pcmpgtw */
7389 case 0x0f66: /* pcmpgtd */
7390 case 0x0f67: /* packuswb */
7391 case 0x0f68: /* punpckhbw */
7392 case 0x0f69: /* punpckhwd */
7393 case 0x0f6a: /* punpckhdq */
7394 case 0x0f6b: /* packssdw */
7395 case 0x0f6e: /* movd */
7396 case 0x0f6f: /* movq */
7397 case 0x0f70: /* pshufw */
7398 case 0x0f74: /* pcmpeqb */
7399 case 0x0f75: /* pcmpeqw */
7400 case 0x0f76: /* pcmpeqd */
7401 case 0x0fc4: /* pinsrw */
7402 case 0x0fd1: /* psrlw */
7403 case 0x0fd2: /* psrld */
7404 case 0x0fd3: /* psrlq */
7405 case 0x0fd4: /* paddq */
7406 case 0x0fd5: /* pmullw */
7407 case 0xf20fd6: /* movdq2q */
7408 case 0x0fd8: /* psubusb */
7409 case 0x0fd9: /* psubusw */
7410 case 0x0fda: /* pminub */
7411 case 0x0fdb: /* pand */
7412 case 0x0fdc: /* paddusb */
7413 case 0x0fdd: /* paddusw */
7414 case 0x0fde: /* pmaxub */
7415 case 0x0fdf: /* pandn */
7416 case 0x0fe0: /* pavgb */
7417 case 0x0fe1: /* psraw */
7418 case 0x0fe2: /* psrad */
7419 case 0x0fe3: /* pavgw */
7420 case 0x0fe4: /* pmulhuw */
7421 case 0x0fe5: /* pmulhw */
7422 case 0x0fe8: /* psubsb */
7423 case 0x0fe9: /* psubsw */
7424 case 0x0fea: /* pminsw */
7425 case 0x0feb: /* por */
7426 case 0x0fec: /* paddsb */
7427 case 0x0fed: /* paddsw */
7428 case 0x0fee: /* pmaxsw */
7429 case 0x0fef: /* pxor */
7430 case 0x0ff1: /* psllw */
7431 case 0x0ff2: /* pslld */
7432 case 0x0ff3: /* psllq */
7433 case 0x0ff4: /* pmuludq */
7434 case 0x0ff5: /* pmaddwd */
7435 case 0x0ff6: /* psadbw */
7436 case 0x0ff8: /* psubb */
7437 case 0x0ff9: /* psubw */
7438 case 0x0ffa: /* psubd */
7439 case 0x0ffb: /* psubq */
7440 case 0x0ffc: /* paddb */
7441 case 0x0ffd: /* paddw */
7442 case 0x0ffe: /* paddd */
7443 if (i386_record_modrm (&ir
))
7445 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7447 record_full_arch_list_add_reg (ir
.regcache
,
7448 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7451 case 0x0f71: /* psllw */
7452 case 0x0f72: /* pslld */
7453 case 0x0f73: /* psllq */
7454 if (i386_record_modrm (&ir
))
7456 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7458 record_full_arch_list_add_reg (ir
.regcache
,
7459 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7462 case 0x660f71: /* psllw */
7463 case 0x660f72: /* pslld */
7464 case 0x660f73: /* psllq */
7465 if (i386_record_modrm (&ir
))
7468 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7470 record_full_arch_list_add_reg (ir
.regcache
,
7471 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7474 case 0x0f7e: /* movd */
7475 case 0x660f7e: /* movd */
7476 if (i386_record_modrm (&ir
))
7479 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7486 if (i386_record_lea_modrm (&ir
))
7491 case 0x0f7f: /* movq */
7492 if (i386_record_modrm (&ir
))
7496 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7498 record_full_arch_list_add_reg (ir
.regcache
,
7499 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7504 if (i386_record_lea_modrm (&ir
))
7509 case 0xf30fb8: /* popcnt */
7510 if (i386_record_modrm (&ir
))
7512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7516 case 0x660fd6: /* movq */
7517 if (i386_record_modrm (&ir
))
7522 if (!i386_xmm_regnum_p (gdbarch
,
7523 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7525 record_full_arch_list_add_reg (ir
.regcache
,
7526 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7531 if (i386_record_lea_modrm (&ir
))
7536 case 0x660f3817: /* ptest */
7537 case 0x0f2e: /* ucomiss */
7538 case 0x660f2e: /* ucomisd */
7539 case 0x0f2f: /* comiss */
7540 case 0x660f2f: /* comisd */
7541 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7544 case 0x0ff7: /* maskmovq */
7545 regcache_raw_read_unsigned (ir
.regcache
,
7546 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7548 if (record_full_arch_list_add_mem (addr
, 64))
7552 case 0x660ff7: /* maskmovdqu */
7553 regcache_raw_read_unsigned (ir
.regcache
,
7554 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7556 if (record_full_arch_list_add_mem (addr
, 128))
7571 /* In the future, maybe still need to deal with need_dasm. */
7572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7573 if (record_full_arch_list_add_end ())
7579 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7580 "at address %s.\n"),
7581 (unsigned int) (opcode
),
7582 paddress (gdbarch
, ir
.orig_addr
));
7586 static const int i386_record_regmap
[] =
7588 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7589 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7590 0, 0, 0, 0, 0, 0, 0, 0,
7591 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7592 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7595 /* Check that the given address appears suitable for a fast
7596 tracepoint, which on x86-64 means that we need an instruction of at
7597 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7598 jump and not have to worry about program jumps to an address in the
7599 middle of the tracepoint jump. On x86, it may be possible to use
7600 4-byte jumps with a 2-byte offset to a trampoline located in the
7601 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7602 of instruction to replace, and 0 if not, plus an explanatory
7606 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7607 CORE_ADDR addr
, int *isize
, char **msg
)
7610 static struct ui_file
*gdb_null
= NULL
;
7612 /* Ask the target for the minimum instruction length supported. */
7613 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7617 /* If the target does not support the get_min_fast_tracepoint_insn_len
7618 operation, assume that fast tracepoints will always be implemented
7619 using 4-byte relative jumps on both x86 and x86-64. */
7622 else if (jumplen
== 0)
7624 /* If the target does support get_min_fast_tracepoint_insn_len but
7625 returns zero, then the IPA has not loaded yet. In this case,
7626 we optimistically assume that truncated 2-byte relative jumps
7627 will be available on x86, and compensate later if this assumption
7628 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7629 jumps will always be used. */
7630 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7633 /* Dummy file descriptor for the disassembler. */
7635 gdb_null
= ui_file_new ();
7637 /* Check for fit. */
7638 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7644 /* Return a bit of target-specific detail to add to the caller's
7645 generic failure message. */
7647 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7648 "need at least %d bytes for the jump"),
7661 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7662 struct tdesc_arch_data
*tdesc_data
)
7664 const struct target_desc
*tdesc
= tdep
->tdesc
;
7665 const struct tdesc_feature
*feature_core
;
7666 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
;
7667 int i
, num_regs
, valid_p
;
7669 if (! tdesc_has_registers (tdesc
))
7672 /* Get core registers. */
7673 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7674 if (feature_core
== NULL
)
7677 /* Get SSE registers. */
7678 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7680 /* Try AVX registers. */
7681 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7683 /* Try MPX registers. */
7684 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
7688 /* The XCR0 bits. */
7691 /* AVX register description requires SSE register description. */
7695 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7697 /* It may have been set by OSABI initialization function. */
7698 if (tdep
->num_ymm_regs
== 0)
7700 tdep
->ymmh_register_names
= i386_ymmh_names
;
7701 tdep
->num_ymm_regs
= 8;
7702 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7705 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7706 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7707 tdep
->ymm0h_regnum
+ i
,
7708 tdep
->ymmh_register_names
[i
]);
7710 else if (feature_sse
)
7711 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7714 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7715 tdep
->num_xmm_regs
= 0;
7718 num_regs
= tdep
->num_core_regs
;
7719 for (i
= 0; i
< num_regs
; i
++)
7720 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7721 tdep
->register_names
[i
]);
7725 /* Need to include %mxcsr, so add one. */
7726 num_regs
+= tdep
->num_xmm_regs
+ 1;
7727 for (; i
< num_regs
; i
++)
7728 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7729 tdep
->register_names
[i
]);
7734 tdep
->xcr0
= I386_XSTATE_MPX_MASK
;
7736 if (tdep
->bnd0r_regnum
< 0)
7738 tdep
->mpx_register_names
= i386_mpx_names
;
7739 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
7740 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
7743 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
7744 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
7745 I387_BND0R_REGNUM (tdep
) + i
,
7746 tdep
->mpx_register_names
[i
]);
7753 static struct gdbarch
*
7754 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7756 struct gdbarch_tdep
*tdep
;
7757 struct gdbarch
*gdbarch
;
7758 struct tdesc_arch_data
*tdesc_data
;
7759 const struct target_desc
*tdesc
;
7765 /* If there is already a candidate, use it. */
7766 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7768 return arches
->gdbarch
;
7770 /* Allocate space for the new architecture. */
7771 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7772 gdbarch
= gdbarch_alloc (&info
, tdep
);
7774 /* General-purpose registers. */
7775 tdep
->gregset
= NULL
;
7776 tdep
->gregset_reg_offset
= NULL
;
7777 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7778 tdep
->sizeof_gregset
= 0;
7780 /* Floating-point registers. */
7781 tdep
->fpregset
= NULL
;
7782 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7784 tdep
->xstateregset
= NULL
;
7786 /* The default settings include the FPU registers, the MMX registers
7787 and the SSE registers. This can be overridden for a specific ABI
7788 by adjusting the members `st0_regnum', `mm0_regnum' and
7789 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7790 will show up in the output of "info all-registers". */
7792 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7794 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7795 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7797 tdep
->jb_pc_offset
= -1;
7798 tdep
->struct_return
= pcc_struct_return
;
7799 tdep
->sigtramp_start
= 0;
7800 tdep
->sigtramp_end
= 0;
7801 tdep
->sigtramp_p
= i386_sigtramp_p
;
7802 tdep
->sigcontext_addr
= NULL
;
7803 tdep
->sc_reg_offset
= NULL
;
7804 tdep
->sc_pc_offset
= -1;
7805 tdep
->sc_sp_offset
= -1;
7807 tdep
->xsave_xcr0_offset
= -1;
7809 tdep
->record_regmap
= i386_record_regmap
;
7811 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7813 /* The format used for `long double' on almost all i386 targets is
7814 the i387 extended floating-point format. In fact, of all targets
7815 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7816 on having a `long double' that's not `long' at all. */
7817 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7819 /* Although the i387 extended floating-point has only 80 significant
7820 bits, a `long double' actually takes up 96, probably to enforce
7822 set_gdbarch_long_double_bit (gdbarch
, 96);
7824 /* Register numbers of various important registers. */
7825 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7826 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7827 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7828 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7830 /* NOTE: kettenis/20040418: GCC does have two possible register
7831 numbering schemes on the i386: dbx and SVR4. These schemes
7832 differ in how they number %ebp, %esp, %eflags, and the
7833 floating-point registers, and are implemented by the arrays
7834 dbx_register_map[] and svr4_dbx_register_map in
7835 gcc/config/i386.c. GCC also defines a third numbering scheme in
7836 gcc/config/i386.c, which it designates as the "default" register
7837 map used in 64bit mode. This last register numbering scheme is
7838 implemented in dbx64_register_map, and is used for AMD64; see
7841 Currently, each GCC i386 target always uses the same register
7842 numbering scheme across all its supported debugging formats
7843 i.e. SDB (COFF), stabs and DWARF 2. This is because
7844 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7845 DBX_REGISTER_NUMBER macro which is defined by each target's
7846 respective config header in a manner independent of the requested
7847 output debugging format.
7849 This does not match the arrangement below, which presumes that
7850 the SDB and stabs numbering schemes differ from the DWARF and
7851 DWARF 2 ones. The reason for this arrangement is that it is
7852 likely to get the numbering scheme for the target's
7853 default/native debug format right. For targets where GCC is the
7854 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7855 targets where the native toolchain uses a different numbering
7856 scheme for a particular debug format (stabs-in-ELF on Solaris)
7857 the defaults below will have to be overridden, like
7858 i386_elf_init_abi() does. */
7860 /* Use the dbx register numbering scheme for stabs and COFF. */
7861 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7862 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7864 /* Use the SVR4 register numbering scheme for DWARF 2. */
7865 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7867 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7868 be in use on any of the supported i386 targets. */
7870 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7872 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7874 /* Call dummy code. */
7875 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7876 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7877 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7878 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7880 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7881 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7882 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7884 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7886 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7888 /* Stack grows downward. */
7889 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7891 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7892 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7893 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7895 set_gdbarch_frame_args_skip (gdbarch
, 8);
7897 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7899 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7901 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7903 /* Add the i386 register groups. */
7904 i386_add_reggroups (gdbarch
);
7905 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7907 /* Helper for function argument information. */
7908 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7910 /* Hook the function epilogue frame unwinder. This unwinder is
7911 appended to the list first, so that it supercedes the DWARF
7912 unwinder in function epilogues (where the DWARF unwinder
7913 currently fails). */
7914 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7916 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7917 to the list before the prologue-based unwinders, so that DWARF
7918 CFI info will be used if it is available. */
7919 dwarf2_append_unwinders (gdbarch
);
7921 frame_base_set_default (gdbarch
, &i386_frame_base
);
7923 /* Pseudo registers may be changed by amd64_init_abi. */
7924 set_gdbarch_pseudo_register_read_value (gdbarch
,
7925 i386_pseudo_register_read_value
);
7926 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7928 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7929 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7931 /* Override the normal target description method to make the AVX
7932 upper halves anonymous. */
7933 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7935 /* Even though the default ABI only includes general-purpose registers,
7936 floating-point registers and the SSE registers, we have to leave a
7937 gap for the upper AVX registers and the MPX registers. */
7938 set_gdbarch_num_regs (gdbarch
, I386_MPX_NUM_REGS
);
7940 /* Get the x86 target description from INFO. */
7941 tdesc
= info
.target_desc
;
7942 if (! tdesc_has_registers (tdesc
))
7944 tdep
->tdesc
= tdesc
;
7946 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7947 tdep
->register_names
= i386_register_names
;
7949 /* No upper YMM registers. */
7950 tdep
->ymmh_register_names
= NULL
;
7951 tdep
->ymm0h_regnum
= -1;
7953 tdep
->num_byte_regs
= 8;
7954 tdep
->num_word_regs
= 8;
7955 tdep
->num_dword_regs
= 0;
7956 tdep
->num_mmx_regs
= 8;
7957 tdep
->num_ymm_regs
= 0;
7959 /* No MPX registers. */
7960 tdep
->bnd0r_regnum
= -1;
7961 tdep
->bndcfgu_regnum
= -1;
7963 tdesc_data
= tdesc_data_alloc ();
7965 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7967 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7969 /* Hook in ABI-specific overrides, if they have been registered. */
7970 info
.tdep_info
= (void *) tdesc_data
;
7971 gdbarch_init_osabi (info
, gdbarch
);
7973 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7975 tdesc_data_cleanup (tdesc_data
);
7977 gdbarch_free (gdbarch
);
7981 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
7983 /* Wire in pseudo registers. Number of pseudo registers may be
7985 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7986 + tdep
->num_word_regs
7987 + tdep
->num_dword_regs
7988 + tdep
->num_mmx_regs
7989 + tdep
->num_ymm_regs
7992 /* Target description may be changed. */
7993 tdesc
= tdep
->tdesc
;
7995 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7997 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7998 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8000 /* Make %al the first pseudo-register. */
8001 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8002 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8004 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8005 if (tdep
->num_dword_regs
)
8007 /* Support dword pseudo-register if it hasn't been disabled. */
8008 tdep
->eax_regnum
= ymm0_regnum
;
8009 ymm0_regnum
+= tdep
->num_dword_regs
;
8012 tdep
->eax_regnum
= -1;
8014 mm0_regnum
= ymm0_regnum
;
8015 if (tdep
->num_ymm_regs
)
8017 /* Support YMM pseudo-register if it is available. */
8018 tdep
->ymm0_regnum
= ymm0_regnum
;
8019 mm0_regnum
+= tdep
->num_ymm_regs
;
8022 tdep
->ymm0_regnum
= -1;
8024 bnd0_regnum
= mm0_regnum
;
8025 if (tdep
->num_mmx_regs
!= 0)
8027 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8028 tdep
->mm0_regnum
= mm0_regnum
;
8029 bnd0_regnum
+= tdep
->num_mmx_regs
;
8032 tdep
->mm0_regnum
= -1;
8034 if (tdep
->bnd0r_regnum
> 0)
8035 tdep
->bnd0_regnum
= bnd0_regnum
;
8037 tdep
-> bnd0_regnum
= -1;
8039 /* Hook in the legacy prologue-based unwinders last (fallback). */
8040 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8041 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8042 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8044 /* If we have a register mapping, enable the generic core file
8045 support, unless it has already been enabled. */
8046 if (tdep
->gregset_reg_offset
8047 && !gdbarch_regset_from_core_section_p (gdbarch
))
8048 set_gdbarch_regset_from_core_section (gdbarch
,
8049 i386_regset_from_core_section
);
8051 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
8052 i386_skip_permanent_breakpoint
);
8054 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8055 i386_fast_tracepoint_valid_at
);
8060 static enum gdb_osabi
8061 i386_coff_osabi_sniffer (bfd
*abfd
)
8063 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8064 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8065 return GDB_OSABI_GO32
;
8067 return GDB_OSABI_UNKNOWN
;
8071 /* Provide a prototype to silence -Wmissing-prototypes. */
8072 void _initialize_i386_tdep (void);
8075 _initialize_i386_tdep (void)
8077 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8079 /* Add the variable that controls the disassembly flavor. */
8080 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8081 &disassembly_flavor
, _("\
8082 Set the disassembly flavor."), _("\
8083 Show the disassembly flavor."), _("\
8084 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8086 NULL
, /* FIXME: i18n: */
8087 &setlist
, &showlist
);
8089 /* Add the variable that controls the convention for returning
8091 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
8092 &struct_convention
, _("\
8093 Set the convention for returning small structs."), _("\
8094 Show the convention for returning small structs."), _("\
8095 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8098 NULL
, /* FIXME: i18n: */
8099 &setlist
, &showlist
);
8101 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
8102 i386_coff_osabi_sniffer
);
8104 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
8105 i386_svr4_init_abi
);
8106 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
8107 i386_go32_init_abi
);
8109 /* Initialize the i386-specific register groups. */
8110 i386_init_reggroups ();
8112 /* Initialize the standard target descriptions. */
8113 initialize_tdesc_i386 ();
8114 initialize_tdesc_i386_mmx ();
8115 initialize_tdesc_i386_avx ();
8116 initialize_tdesc_i386_mpx ();
8118 /* Tell remote stub that we support XML target description. */
8119 register_remote_support_xml ("i386");