1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
68 static const char *i386_register_names
[] =
70 "eax", "ecx", "edx", "ebx",
71 "esp", "ebp", "esi", "edi",
72 "eip", "eflags", "cs", "ss",
73 "ds", "es", "fs", "gs",
74 "st0", "st1", "st2", "st3",
75 "st4", "st5", "st6", "st7",
76 "fctrl", "fstat", "ftag", "fiseg",
77 "fioff", "foseg", "fooff", "fop",
78 "xmm0", "xmm1", "xmm2", "xmm3",
79 "xmm4", "xmm5", "xmm6", "xmm7",
83 static const char *i386_ymm_names
[] =
85 "ymm0", "ymm1", "ymm2", "ymm3",
86 "ymm4", "ymm5", "ymm6", "ymm7",
89 static const char *i386_ymmh_names
[] =
91 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
92 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
95 /* Register names for MMX pseudo-registers. */
97 static const char *i386_mmx_names
[] =
99 "mm0", "mm1", "mm2", "mm3",
100 "mm4", "mm5", "mm6", "mm7"
103 /* Register names for byte pseudo-registers. */
105 static const char *i386_byte_names
[] =
107 "al", "cl", "dl", "bl",
108 "ah", "ch", "dh", "bh"
111 /* Register names for word pseudo-registers. */
113 static const char *i386_word_names
[] =
115 "ax", "cx", "dx", "bx",
122 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
125 int mm0_regnum
= tdep
->mm0_regnum
;
130 regnum
-= mm0_regnum
;
131 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
137 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 regnum
-= tdep
->al_regnum
;
142 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
148 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
152 regnum
-= tdep
->ax_regnum
;
153 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
156 /* Dword register? */
159 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
162 int eax_regnum
= tdep
->eax_regnum
;
167 regnum
-= eax_regnum
;
168 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
172 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
175 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
177 if (ymm0h_regnum
< 0)
180 regnum
-= ymm0h_regnum
;
181 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
187 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
189 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 int ymm0_regnum
= tdep
->ymm0_regnum
;
195 regnum
-= ymm0_regnum
;
196 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
202 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
204 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
205 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
207 if (num_xmm_regs
== 0)
210 regnum
-= I387_XMM0_REGNUM (tdep
);
211 return regnum
>= 0 && regnum
< num_xmm_regs
;
215 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
219 if (I387_NUM_XMM_REGS (tdep
) == 0)
222 return (regnum
== I387_MXCSR_REGNUM (tdep
));
228 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
232 if (I387_ST0_REGNUM (tdep
) < 0)
235 return (I387_ST0_REGNUM (tdep
) <= regnum
236 && regnum
< I387_FCTRL_REGNUM (tdep
));
240 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
242 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
244 if (I387_ST0_REGNUM (tdep
) < 0)
247 return (I387_FCTRL_REGNUM (tdep
) <= regnum
248 && regnum
< I387_XMM0_REGNUM (tdep
));
251 /* Return the name of register REGNUM, or the empty string if it is
252 an anonymous register. */
255 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
257 /* Hide the upper YMM registers. */
258 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
261 return tdesc_register_name (gdbarch
, regnum
);
264 /* Return the name of register REGNUM. */
267 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 if (i386_mmx_regnum_p (gdbarch
, regnum
))
271 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
272 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
273 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
274 else if (i386_byte_regnum_p (gdbarch
, regnum
))
275 return i386_byte_names
[regnum
- tdep
->al_regnum
];
276 else if (i386_word_regnum_p (gdbarch
, regnum
))
277 return i386_word_names
[regnum
- tdep
->ax_regnum
];
279 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
282 /* Convert a dbx register number REG to the appropriate register
283 number used by GDB. */
286 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
290 /* This implements what GCC calls the "default" register map
291 (dbx_register_map[]). */
293 if (reg
>= 0 && reg
<= 7)
295 /* General-purpose registers. The debug info calls %ebp
296 register 4, and %esp register 5. */
303 else if (reg
>= 12 && reg
<= 19)
305 /* Floating-point registers. */
306 return reg
- 12 + I387_ST0_REGNUM (tdep
);
308 else if (reg
>= 21 && reg
<= 28)
311 int ymm0_regnum
= tdep
->ymm0_regnum
;
314 && i386_xmm_regnum_p (gdbarch
, reg
))
315 return reg
- 21 + ymm0_regnum
;
317 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
319 else if (reg
>= 29 && reg
<= 36)
322 return reg
- 29 + I387_MM0_REGNUM (tdep
);
325 /* This will hopefully provoke a warning. */
326 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
329 /* Convert SVR4 register number REG to the appropriate register number
333 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
337 /* This implements the GCC register map that tries to be compatible
338 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
340 /* The SVR4 register numbering includes %eip and %eflags, and
341 numbers the floating point registers differently. */
342 if (reg
>= 0 && reg
<= 9)
344 /* General-purpose registers. */
347 else if (reg
>= 11 && reg
<= 18)
349 /* Floating-point registers. */
350 return reg
- 11 + I387_ST0_REGNUM (tdep
);
352 else if (reg
>= 21 && reg
<= 36)
354 /* The SSE and MMX registers have the same numbers as with dbx. */
355 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
360 case 37: return I387_FCTRL_REGNUM (tdep
);
361 case 38: return I387_FSTAT_REGNUM (tdep
);
362 case 39: return I387_MXCSR_REGNUM (tdep
);
363 case 40: return I386_ES_REGNUM
;
364 case 41: return I386_CS_REGNUM
;
365 case 42: return I386_SS_REGNUM
;
366 case 43: return I386_DS_REGNUM
;
367 case 44: return I386_FS_REGNUM
;
368 case 45: return I386_GS_REGNUM
;
371 /* This will hopefully provoke a warning. */
372 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
377 /* This is the variable that is set with "set disassembly-flavor", and
378 its legitimate values. */
379 static const char att_flavor
[] = "att";
380 static const char intel_flavor
[] = "intel";
381 static const char *valid_flavors
[] =
387 static const char *disassembly_flavor
= att_flavor
;
390 /* Use the program counter to determine the contents and size of a
391 breakpoint instruction. Return a pointer to a string of bytes that
392 encode a breakpoint instruction, store the length of the string in
393 *LEN and optionally adjust *PC to point to the correct memory
394 location for inserting the breakpoint.
396 On the i386 we have a single breakpoint that fits in a single byte
397 and can be inserted anywhere.
399 This function is 64-bit safe. */
401 static const gdb_byte
*
402 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
404 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
406 *len
= sizeof (break_insn
);
410 /* Displaced instruction handling. */
412 /* Skip the legacy instruction prefixes in INSN.
413 Not all prefixes are valid for any particular insn
414 but we needn't care, the insn will fault if it's invalid.
415 The result is a pointer to the first opcode byte,
416 or NULL if we run off the end of the buffer. */
419 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
421 gdb_byte
*end
= insn
+ max_len
;
427 case DATA_PREFIX_OPCODE
:
428 case ADDR_PREFIX_OPCODE
:
429 case CS_PREFIX_OPCODE
:
430 case DS_PREFIX_OPCODE
:
431 case ES_PREFIX_OPCODE
:
432 case FS_PREFIX_OPCODE
:
433 case GS_PREFIX_OPCODE
:
434 case SS_PREFIX_OPCODE
:
435 case LOCK_PREFIX_OPCODE
:
436 case REPE_PREFIX_OPCODE
:
437 case REPNE_PREFIX_OPCODE
:
449 i386_absolute_jmp_p (const gdb_byte
*insn
)
451 /* jmp far (absolute address in operand). */
457 /* jump near, absolute indirect (/4). */
458 if ((insn
[1] & 0x38) == 0x20)
461 /* jump far, absolute indirect (/5). */
462 if ((insn
[1] & 0x38) == 0x28)
470 i386_absolute_call_p (const gdb_byte
*insn
)
472 /* call far, absolute. */
478 /* Call near, absolute indirect (/2). */
479 if ((insn
[1] & 0x38) == 0x10)
482 /* Call far, absolute indirect (/3). */
483 if ((insn
[1] & 0x38) == 0x18)
491 i386_ret_p (const gdb_byte
*insn
)
495 case 0xc2: /* ret near, pop N bytes. */
496 case 0xc3: /* ret near */
497 case 0xca: /* ret far, pop N bytes. */
498 case 0xcb: /* ret far */
499 case 0xcf: /* iret */
508 i386_call_p (const gdb_byte
*insn
)
510 if (i386_absolute_call_p (insn
))
513 /* call near, relative. */
520 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
521 length in bytes. Otherwise, return zero. */
524 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
535 /* Some kernels may run one past a syscall insn, so we have to cope.
536 Otherwise this is just simple_displaced_step_copy_insn. */
538 struct displaced_step_closure
*
539 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
540 CORE_ADDR from
, CORE_ADDR to
,
541 struct regcache
*regs
)
543 size_t len
= gdbarch_max_insn_length (gdbarch
);
544 gdb_byte
*buf
= xmalloc (len
);
546 read_memory (from
, buf
, len
);
548 /* GDB may get control back after the insn after the syscall.
549 Presumably this is a kernel bug.
550 If this is a syscall, make sure there's a nop afterwards. */
555 insn
= i386_skip_prefixes (buf
, len
);
556 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
557 insn
[syscall_length
] = NOP_OPCODE
;
560 write_memory (to
, buf
, len
);
564 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
565 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
566 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
569 return (struct displaced_step_closure
*) buf
;
572 /* Fix up the state of registers and memory after having single-stepped
573 a displaced instruction. */
576 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
577 struct displaced_step_closure
*closure
,
578 CORE_ADDR from
, CORE_ADDR to
,
579 struct regcache
*regs
)
581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
583 /* The offset we applied to the instruction's address.
584 This could well be negative (when viewed as a signed 32-bit
585 value), but ULONGEST won't reflect that, so take care when
587 ULONGEST insn_offset
= to
- from
;
589 /* Since we use simple_displaced_step_copy_insn, our closure is a
590 copy of the instruction. */
591 gdb_byte
*insn
= (gdb_byte
*) closure
;
592 /* The start of the insn, needed in case we see some prefixes. */
593 gdb_byte
*insn_start
= insn
;
596 fprintf_unfiltered (gdb_stdlog
,
597 "displaced: fixup (%s, %s), "
598 "insn = 0x%02x 0x%02x ...\n",
599 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
602 /* The list of issues to contend with here is taken from
603 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
604 Yay for Free Software! */
606 /* Relocate the %eip, if necessary. */
608 /* The instruction recognizers we use assume any leading prefixes
609 have been skipped. */
611 /* This is the size of the buffer in closure. */
612 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
613 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
614 /* If there are too many prefixes, just ignore the insn.
615 It will fault when run. */
620 /* Except in the case of absolute or indirect jump or call
621 instructions, or a return instruction, the new eip is relative to
622 the displaced instruction; make it relative. Well, signal
623 handler returns don't need relocation either, but we use the
624 value of %eip to recognize those; see below. */
625 if (! i386_absolute_jmp_p (insn
)
626 && ! i386_absolute_call_p (insn
)
627 && ! i386_ret_p (insn
))
632 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
634 /* A signal trampoline system call changes the %eip, resuming
635 execution of the main program after the signal handler has
636 returned. That makes them like 'return' instructions; we
637 shouldn't relocate %eip.
639 But most system calls don't, and we do need to relocate %eip.
641 Our heuristic for distinguishing these cases: if stepping
642 over the system call instruction left control directly after
643 the instruction, the we relocate --- control almost certainly
644 doesn't belong in the displaced copy. Otherwise, we assume
645 the instruction has put control where it belongs, and leave
646 it unrelocated. Goodness help us if there are PC-relative
648 if (i386_syscall_p (insn
, &insn_len
)
649 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
650 /* GDB can get control back after the insn after the syscall.
651 Presumably this is a kernel bug.
652 i386_displaced_step_copy_insn ensures its a nop,
653 we add one to the length for it. */
654 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
657 fprintf_unfiltered (gdb_stdlog
,
658 "displaced: syscall changed %%eip; "
663 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
665 /* If we just stepped over a breakpoint insn, we don't backup
666 the pc on purpose; this is to match behaviour without
669 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
672 fprintf_unfiltered (gdb_stdlog
,
674 "relocated %%eip from %s to %s\n",
675 paddress (gdbarch
, orig_eip
),
676 paddress (gdbarch
, eip
));
680 /* If the instruction was PUSHFL, then the TF bit will be set in the
681 pushed value, and should be cleared. We'll leave this for later,
682 since GDB already messes up the TF flag when stepping over a
685 /* If the instruction was a call, the return address now atop the
686 stack is the address following the copied instruction. We need
687 to make it the address following the original instruction. */
688 if (i386_call_p (insn
))
692 const ULONGEST retaddr_len
= 4;
694 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
695 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
696 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
697 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
700 fprintf_unfiltered (gdb_stdlog
,
701 "displaced: relocated return addr at %s to %s\n",
702 paddress (gdbarch
, esp
),
703 paddress (gdbarch
, retaddr
));
708 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
710 target_write_memory (*to
, buf
, len
);
715 i386_relocate_instruction (struct gdbarch
*gdbarch
,
716 CORE_ADDR
*to
, CORE_ADDR oldloc
)
718 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
719 gdb_byte buf
[I386_MAX_INSN_LEN
];
720 int offset
= 0, rel32
, newrel
;
722 gdb_byte
*insn
= buf
;
724 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
726 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
727 I386_MAX_INSN_LEN
, oldloc
);
729 /* Get past the prefixes. */
730 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
732 /* Adjust calls with 32-bit relative addresses as push/jump, with
733 the address pushed being the location where the original call in
734 the user program would return to. */
737 gdb_byte push_buf
[16];
738 unsigned int ret_addr
;
740 /* Where "ret" in the original code will return to. */
741 ret_addr
= oldloc
+ insn_length
;
742 push_buf
[0] = 0x68; /* pushq $... */
743 memcpy (&push_buf
[1], &ret_addr
, 4);
745 append_insns (to
, 5, push_buf
);
747 /* Convert the relative call to a relative jump. */
750 /* Adjust the destination offset. */
751 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
752 newrel
= (oldloc
- *to
) + rel32
;
753 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
756 fprintf_unfiltered (gdb_stdlog
,
757 "Adjusted insn rel32=%s at %s to"
759 hex_string (rel32
), paddress (gdbarch
, oldloc
),
760 hex_string (newrel
), paddress (gdbarch
, *to
));
762 /* Write the adjusted jump into its displaced location. */
763 append_insns (to
, 5, insn
);
767 /* Adjust jumps with 32-bit relative addresses. Calls are already
771 /* Adjust conditional jumps. */
772 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
777 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
778 newrel
= (oldloc
- *to
) + rel32
;
779 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
781 fprintf_unfiltered (gdb_stdlog
,
782 "Adjusted insn rel32=%s at %s to"
784 hex_string (rel32
), paddress (gdbarch
, oldloc
),
785 hex_string (newrel
), paddress (gdbarch
, *to
));
788 /* Write the adjusted instructions into their displaced
790 append_insns (to
, insn_length
, buf
);
794 #ifdef I386_REGNO_TO_SYMMETRY
795 #error "The Sequent Symmetry is no longer supported."
798 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
799 and %esp "belong" to the calling function. Therefore these
800 registers should be saved if they're going to be modified. */
802 /* The maximum number of saved registers. This should include all
803 registers mentioned above, and %eip. */
804 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
806 struct i386_frame_cache
814 /* Saved registers. */
815 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
820 /* Stack space reserved for local variables. */
824 /* Allocate and initialize a frame cache. */
826 static struct i386_frame_cache
*
827 i386_alloc_frame_cache (void)
829 struct i386_frame_cache
*cache
;
832 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
837 cache
->sp_offset
= -4;
840 /* Saved registers. We initialize these to -1 since zero is a valid
841 offset (that's where %ebp is supposed to be stored). */
842 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
843 cache
->saved_regs
[i
] = -1;
845 cache
->saved_sp_reg
= -1;
846 cache
->pc_in_eax
= 0;
848 /* Frameless until proven otherwise. */
854 /* If the instruction at PC is a jump, return the address of its
855 target. Otherwise, return PC. */
858 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
860 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
865 if (target_read_memory (pc
, &op
, 1))
871 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
877 /* Relative jump: if data16 == 0, disp32, else disp16. */
880 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
882 /* Include the size of the jmp instruction (including the
888 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
890 /* Include the size of the jmp instruction. */
895 /* Relative jump, disp8 (ignore data16). */
896 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
905 /* Check whether PC points at a prologue for a function returning a
906 structure or union. If so, it updates CACHE and returns the
907 address of the first instruction after the code sequence that
908 removes the "hidden" argument from the stack or CURRENT_PC,
909 whichever is smaller. Otherwise, return PC. */
912 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
913 struct i386_frame_cache
*cache
)
915 /* Functions that return a structure or union start with:
918 xchgl %eax, (%esp) 0x87 0x04 0x24
919 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
921 (the System V compiler puts out the second `xchg' instruction,
922 and the assembler doesn't try to optimize it, so the 'sib' form
923 gets generated). This sequence is used to get the address of the
924 return buffer for a function that returns a structure. */
925 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
926 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
930 if (current_pc
<= pc
)
933 if (target_read_memory (pc
, &op
, 1))
936 if (op
!= 0x58) /* popl %eax */
939 if (target_read_memory (pc
+ 1, buf
, 4))
942 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
945 if (current_pc
== pc
)
947 cache
->sp_offset
+= 4;
951 if (current_pc
== pc
+ 1)
953 cache
->pc_in_eax
= 1;
957 if (buf
[1] == proto1
[1])
964 i386_skip_probe (CORE_ADDR pc
)
966 /* A function may start with
980 if (target_read_memory (pc
, &op
, 1))
983 if (op
== 0x68 || op
== 0x6a)
987 /* Skip past the `pushl' instruction; it has either a one-byte or a
988 four-byte operand, depending on the opcode. */
994 /* Read the following 8 bytes, which should be `call _probe' (6
995 bytes) followed by `addl $4,%esp' (2 bytes). */
996 read_memory (pc
+ delta
, buf
, sizeof (buf
));
997 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
998 pc
+= delta
+ sizeof (buf
);
1004 /* GCC 4.1 and later, can put code in the prologue to realign the
1005 stack pointer. Check whether PC points to such code, and update
1006 CACHE accordingly. Return the first instruction after the code
1007 sequence or CURRENT_PC, whichever is smaller. If we don't
1008 recognize the code, return PC. */
1011 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1012 struct i386_frame_cache
*cache
)
1014 /* There are 2 code sequences to re-align stack before the frame
1017 1. Use a caller-saved saved register:
1023 2. Use a callee-saved saved register:
1030 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1032 0x83 0xe4 0xf0 andl $-16, %esp
1033 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1038 int offset
, offset_and
;
1039 static int regnums
[8] = {
1040 I386_EAX_REGNUM
, /* %eax */
1041 I386_ECX_REGNUM
, /* %ecx */
1042 I386_EDX_REGNUM
, /* %edx */
1043 I386_EBX_REGNUM
, /* %ebx */
1044 I386_ESP_REGNUM
, /* %esp */
1045 I386_EBP_REGNUM
, /* %ebp */
1046 I386_ESI_REGNUM
, /* %esi */
1047 I386_EDI_REGNUM
/* %edi */
1050 if (target_read_memory (pc
, buf
, sizeof buf
))
1053 /* Check caller-saved saved register. The first instruction has
1054 to be "leal 4(%esp), %reg". */
1055 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1057 /* MOD must be binary 10 and R/M must be binary 100. */
1058 if ((buf
[1] & 0xc7) != 0x44)
1061 /* REG has register number. */
1062 reg
= (buf
[1] >> 3) & 7;
1067 /* Check callee-saved saved register. The first instruction
1068 has to be "pushl %reg". */
1069 if ((buf
[0] & 0xf8) != 0x50)
1075 /* The next instruction has to be "leal 8(%esp), %reg". */
1076 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1079 /* MOD must be binary 10 and R/M must be binary 100. */
1080 if ((buf
[2] & 0xc7) != 0x44)
1083 /* REG has register number. Registers in pushl and leal have to
1085 if (reg
!= ((buf
[2] >> 3) & 7))
1091 /* Rigister can't be %esp nor %ebp. */
1092 if (reg
== 4 || reg
== 5)
1095 /* The next instruction has to be "andl $-XXX, %esp". */
1096 if (buf
[offset
+ 1] != 0xe4
1097 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1100 offset_and
= offset
;
1101 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1103 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1104 0xfc. REG must be binary 110 and MOD must be binary 01. */
1105 if (buf
[offset
] != 0xff
1106 || buf
[offset
+ 2] != 0xfc
1107 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1110 /* R/M has register. Registers in leal and pushl have to be the
1112 if (reg
!= (buf
[offset
+ 1] & 7))
1115 if (current_pc
> pc
+ offset_and
)
1116 cache
->saved_sp_reg
= regnums
[reg
];
1118 return min (pc
+ offset
+ 3, current_pc
);
1121 /* Maximum instruction length we need to handle. */
1122 #define I386_MAX_MATCHED_INSN_LEN 6
1124 /* Instruction description. */
1128 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1129 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1132 /* Return whether instruction at PC matches PATTERN. */
1135 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1139 if (target_read_memory (pc
, &op
, 1))
1142 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1144 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1145 int insn_matched
= 1;
1148 gdb_assert (pattern
.len
> 1);
1149 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1151 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1154 for (i
= 1; i
< pattern
.len
; i
++)
1156 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1159 return insn_matched
;
1164 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1165 the first instruction description that matches. Otherwise, return
1168 static struct i386_insn
*
1169 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1171 struct i386_insn
*pattern
;
1173 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1175 if (i386_match_pattern (pc
, *pattern
))
1182 /* Return whether PC points inside a sequence of instructions that
1183 matches INSN_PATTERNS. */
1186 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1188 CORE_ADDR current_pc
;
1191 struct i386_insn
*insn
;
1193 insn
= i386_match_insn (pc
, insn_patterns
);
1198 ix
= insn
- insn_patterns
;
1199 for (i
= ix
- 1; i
>= 0; i
--)
1201 current_pc
-= insn_patterns
[i
].len
;
1203 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1207 current_pc
= pc
+ insn
->len
;
1208 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1210 if (!i386_match_pattern (current_pc
, *insn
))
1213 current_pc
+= insn
->len
;
1219 /* Some special instructions that might be migrated by GCC into the
1220 part of the prologue that sets up the new stack frame. Because the
1221 stack frame hasn't been setup yet, no registers have been saved
1222 yet, and only the scratch registers %eax, %ecx and %edx can be
1225 struct i386_insn i386_frame_setup_skip_insns
[] =
1227 /* Check for `movb imm8, r' and `movl imm32, r'.
1229 ??? Should we handle 16-bit operand-sizes here? */
1231 /* `movb imm8, %al' and `movb imm8, %ah' */
1232 /* `movb imm8, %cl' and `movb imm8, %ch' */
1233 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1234 /* `movb imm8, %dl' and `movb imm8, %dh' */
1235 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1236 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1237 { 5, { 0xb8 }, { 0xfe } },
1238 /* `movl imm32, %edx' */
1239 { 5, { 0xba }, { 0xff } },
1241 /* Check for `mov imm32, r32'. Note that there is an alternative
1242 encoding for `mov m32, %eax'.
1244 ??? Should we handle SIB adressing here?
1245 ??? Should we handle 16-bit operand-sizes here? */
1247 /* `movl m32, %eax' */
1248 { 5, { 0xa1 }, { 0xff } },
1249 /* `movl m32, %eax' and `mov; m32, %ecx' */
1250 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1251 /* `movl m32, %edx' */
1252 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1254 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1255 Because of the symmetry, there are actually two ways to encode
1256 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1257 opcode bytes 0x31 and 0x33 for `xorl'. */
1259 /* `subl %eax, %eax' */
1260 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1261 /* `subl %ecx, %ecx' */
1262 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1263 /* `subl %edx, %edx' */
1264 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1265 /* `xorl %eax, %eax' */
1266 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1267 /* `xorl %ecx, %ecx' */
1268 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1269 /* `xorl %edx, %edx' */
1270 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1275 /* Check whether PC points to a no-op instruction. */
1277 i386_skip_noop (CORE_ADDR pc
)
1282 if (target_read_memory (pc
, &op
, 1))
1288 /* Ignore `nop' instruction. */
1292 if (target_read_memory (pc
, &op
, 1))
1296 /* Ignore no-op instruction `mov %edi, %edi'.
1297 Microsoft system dlls often start with
1298 a `mov %edi,%edi' instruction.
1299 The 5 bytes before the function start are
1300 filled with `nop' instructions.
1301 This pattern can be used for hot-patching:
1302 The `mov %edi, %edi' instruction can be replaced by a
1303 near jump to the location of the 5 `nop' instructions
1304 which can be replaced by a 32-bit jump to anywhere
1305 in the 32-bit address space. */
1307 else if (op
== 0x8b)
1309 if (target_read_memory (pc
+ 1, &op
, 1))
1315 if (target_read_memory (pc
, &op
, 1))
1325 /* Check whether PC points at a code that sets up a new stack frame.
1326 If so, it updates CACHE and returns the address of the first
1327 instruction after the sequence that sets up the frame or LIMIT,
1328 whichever is smaller. If we don't recognize the code, return PC. */
1331 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1332 CORE_ADDR pc
, CORE_ADDR limit
,
1333 struct i386_frame_cache
*cache
)
1335 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1336 struct i386_insn
*insn
;
1343 if (target_read_memory (pc
, &op
, 1))
1346 if (op
== 0x55) /* pushl %ebp */
1348 /* Take into account that we've executed the `pushl %ebp' that
1349 starts this instruction sequence. */
1350 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1351 cache
->sp_offset
+= 4;
1354 /* If that's all, return now. */
1358 /* Check for some special instructions that might be migrated by
1359 GCC into the prologue and skip them. At this point in the
1360 prologue, code should only touch the scratch registers %eax,
1361 %ecx and %edx, so while the number of posibilities is sheer,
1364 Make sure we only skip these instructions if we later see the
1365 `movl %esp, %ebp' that actually sets up the frame. */
1366 while (pc
+ skip
< limit
)
1368 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1375 /* If that's all, return now. */
1376 if (limit
<= pc
+ skip
)
1379 if (target_read_memory (pc
+ skip
, &op
, 1))
1382 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1386 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1391 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1399 /* OK, we actually have a frame. We just don't know how large
1400 it is yet. Set its size to zero. We'll adjust it if
1401 necessary. We also now commit to skipping the special
1402 instructions mentioned before. */
1406 /* If that's all, return now. */
1410 /* Check for stack adjustment
1414 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1415 reg, so we don't have to worry about a data16 prefix. */
1416 if (target_read_memory (pc
, &op
, 1))
1420 /* `subl' with 8-bit immediate. */
1421 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1422 /* Some instruction starting with 0x83 other than `subl'. */
1425 /* `subl' with signed 8-bit immediate (though it wouldn't
1426 make sense to be negative). */
1427 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1430 else if (op
== 0x81)
1432 /* Maybe it is `subl' with a 32-bit immediate. */
1433 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1434 /* Some instruction starting with 0x81 other than `subl'. */
1437 /* It is `subl' with a 32-bit immediate. */
1438 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1443 /* Some instruction other than `subl'. */
1447 else if (op
== 0xc8) /* enter */
1449 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1456 /* Check whether PC points at code that saves registers on the stack.
1457 If so, it updates CACHE and returns the address of the first
1458 instruction after the register saves or CURRENT_PC, whichever is
1459 smaller. Otherwise, return PC. */
1462 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1463 struct i386_frame_cache
*cache
)
1465 CORE_ADDR offset
= 0;
1469 if (cache
->locals
> 0)
1470 offset
-= cache
->locals
;
1471 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1473 if (target_read_memory (pc
, &op
, 1))
1475 if (op
< 0x50 || op
> 0x57)
1479 cache
->saved_regs
[op
- 0x50] = offset
;
1480 cache
->sp_offset
+= 4;
1487 /* Do a full analysis of the prologue at PC and update CACHE
1488 accordingly. Bail out early if CURRENT_PC is reached. Return the
1489 address where the analysis stopped.
1491 We handle these cases:
1493 The startup sequence can be at the start of the function, or the
1494 function can start with a branch to startup code at the end.
1496 %ebp can be set up with either the 'enter' instruction, or "pushl
1497 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1498 once used in the System V compiler).
1500 Local space is allocated just below the saved %ebp by either the
1501 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1502 16-bit unsigned argument for space to allocate, and the 'addl'
1503 instruction could have either a signed byte, or 32-bit immediate.
1505 Next, the registers used by this function are pushed. With the
1506 System V compiler they will always be in the order: %edi, %esi,
1507 %ebx (and sometimes a harmless bug causes it to also save but not
1508 restore %eax); however, the code below is willing to see the pushes
1509 in any order, and will handle up to 8 of them.
1511 If the setup sequence is at the end of the function, then the next
1512 instruction will be a branch back to the start. */
1515 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1516 CORE_ADDR pc
, CORE_ADDR current_pc
,
1517 struct i386_frame_cache
*cache
)
1519 pc
= i386_skip_noop (pc
);
1520 pc
= i386_follow_jump (gdbarch
, pc
);
1521 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1522 pc
= i386_skip_probe (pc
);
1523 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1524 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1525 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1528 /* Return PC of first real instruction. */
1531 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1533 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1535 static gdb_byte pic_pat
[6] =
1537 0xe8, 0, 0, 0, 0, /* call 0x0 */
1538 0x5b, /* popl %ebx */
1540 struct i386_frame_cache cache
;
1546 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1547 if (cache
.locals
< 0)
1550 /* Found valid frame setup. */
1552 /* The native cc on SVR4 in -K PIC mode inserts the following code
1553 to get the address of the global offset table (GOT) into register
1558 movl %ebx,x(%ebp) (optional)
1561 This code is with the rest of the prologue (at the end of the
1562 function), so we have to skip it to get to the first real
1563 instruction at the start of the function. */
1565 for (i
= 0; i
< 6; i
++)
1567 if (target_read_memory (pc
+ i
, &op
, 1))
1570 if (pic_pat
[i
] != op
)
1577 if (target_read_memory (pc
+ delta
, &op
, 1))
1580 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1582 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1584 if (op
== 0x5d) /* One byte offset from %ebp. */
1586 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1588 else /* Unexpected instruction. */
1591 if (target_read_memory (pc
+ delta
, &op
, 1))
1596 if (delta
> 0 && op
== 0x81
1597 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1604 /* If the function starts with a branch (to startup code at the end)
1605 the last instruction should bring us back to the first
1606 instruction of the real code. */
1607 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1608 pc
= i386_follow_jump (gdbarch
, pc
);
1613 /* Check that the code pointed to by PC corresponds to a call to
1614 __main, skip it if so. Return PC otherwise. */
1617 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1619 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1622 if (target_read_memory (pc
, &op
, 1))
1628 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1630 /* Make sure address is computed correctly as a 32bit
1631 integer even if CORE_ADDR is 64 bit wide. */
1632 struct minimal_symbol
*s
;
1633 CORE_ADDR call_dest
;
1635 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1636 call_dest
= call_dest
& 0xffffffffU
;
1637 s
= lookup_minimal_symbol_by_pc (call_dest
);
1639 && SYMBOL_LINKAGE_NAME (s
) != NULL
1640 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1648 /* This function is 64-bit safe. */
1651 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1655 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1656 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1660 /* Normal frames. */
1663 i386_frame_cache_1 (struct frame_info
*this_frame
,
1664 struct i386_frame_cache
*cache
)
1666 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1667 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1671 cache
->pc
= get_frame_func (this_frame
);
1673 /* In principle, for normal frames, %ebp holds the frame pointer,
1674 which holds the base address for the current stack frame.
1675 However, for functions that don't need it, the frame pointer is
1676 optional. For these "frameless" functions the frame pointer is
1677 actually the frame pointer of the calling frame. Signal
1678 trampolines are just a special case of a "frameless" function.
1679 They (usually) share their frame pointer with the frame that was
1680 in progress when the signal occurred. */
1682 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1683 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1684 if (cache
->base
== 0)
1687 /* For normal frames, %eip is stored at 4(%ebp). */
1688 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1691 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1694 if (cache
->locals
< 0)
1696 /* We didn't find a valid frame, which means that CACHE->base
1697 currently holds the frame pointer for our calling frame. If
1698 we're at the start of a function, or somewhere half-way its
1699 prologue, the function's frame probably hasn't been fully
1700 setup yet. Try to reconstruct the base address for the stack
1701 frame by looking at the stack pointer. For truly "frameless"
1702 functions this might work too. */
1704 if (cache
->saved_sp_reg
!= -1)
1706 /* Saved stack pointer has been saved. */
1707 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1708 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1710 /* We're halfway aligning the stack. */
1711 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1712 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1714 /* This will be added back below. */
1715 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1717 else if (cache
->pc
!= 0
1718 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1720 /* We're in a known function, but did not find a frame
1721 setup. Assume that the function does not use %ebp.
1722 Alternatively, we may have jumped to an invalid
1723 address; in that case there is definitely no new
1725 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1726 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1730 /* We're in an unknown function. We could not find the start
1731 of the function to analyze the prologue; our best option is
1732 to assume a typical frame layout with the caller's %ebp
1734 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1737 if (cache
->saved_sp_reg
!= -1)
1739 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1740 register may be unavailable). */
1741 if (cache
->saved_sp
== 0
1742 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1743 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1745 /* Now that we have the base address for the stack frame we can
1746 calculate the value of %esp in the calling frame. */
1747 else if (cache
->saved_sp
== 0)
1748 cache
->saved_sp
= cache
->base
+ 8;
1750 /* Adjust all the saved registers such that they contain addresses
1751 instead of offsets. */
1752 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1753 if (cache
->saved_regs
[i
] != -1)
1754 cache
->saved_regs
[i
] += cache
->base
;
1759 static struct i386_frame_cache
*
1760 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1762 volatile struct gdb_exception ex
;
1763 struct i386_frame_cache
*cache
;
1768 cache
= i386_alloc_frame_cache ();
1769 *this_cache
= cache
;
1771 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1773 i386_frame_cache_1 (this_frame
, cache
);
1775 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1776 throw_exception (ex
);
1782 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1783 struct frame_id
*this_id
)
1785 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1787 /* This marks the outermost frame. */
1788 if (cache
->base
== 0)
1791 /* See the end of i386_push_dummy_call. */
1792 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1795 static enum unwind_stop_reason
1796 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1799 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1802 return UNWIND_UNAVAILABLE
;
1804 /* This marks the outermost frame. */
1805 if (cache
->base
== 0)
1806 return UNWIND_OUTERMOST
;
1808 return UNWIND_NO_REASON
;
1811 static struct value
*
1812 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1815 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1817 gdb_assert (regnum
>= 0);
1819 /* The System V ABI says that:
1821 "The flags register contains the system flags, such as the
1822 direction flag and the carry flag. The direction flag must be
1823 set to the forward (that is, zero) direction before entry and
1824 upon exit from a function. Other user flags have no specified
1825 role in the standard calling sequence and are not preserved."
1827 To guarantee the "upon exit" part of that statement we fake a
1828 saved flags register that has its direction flag cleared.
1830 Note that GCC doesn't seem to rely on the fact that the direction
1831 flag is cleared after a function return; it always explicitly
1832 clears the flag before operations where it matters.
1834 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1835 right thing to do. The way we fake the flags register here makes
1836 it impossible to change it. */
1838 if (regnum
== I386_EFLAGS_REGNUM
)
1842 val
= get_frame_register_unsigned (this_frame
, regnum
);
1844 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1847 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1848 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1850 if (regnum
== I386_ESP_REGNUM
1851 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1853 /* If the SP has been saved, but we don't know where, then this
1854 means that SAVED_SP_REG register was found unavailable back
1855 when we built the cache. */
1856 if (cache
->saved_sp
== 0)
1857 return frame_unwind_got_register (this_frame
, regnum
,
1858 cache
->saved_sp_reg
);
1860 return frame_unwind_got_constant (this_frame
, regnum
,
1864 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1865 return frame_unwind_got_memory (this_frame
, regnum
,
1866 cache
->saved_regs
[regnum
]);
1868 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1871 static const struct frame_unwind i386_frame_unwind
=
1874 i386_frame_unwind_stop_reason
,
1876 i386_frame_prev_register
,
1878 default_frame_sniffer
1881 /* Normal frames, but in a function epilogue. */
1883 /* The epilogue is defined here as the 'ret' instruction, which will
1884 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1885 the function's stack frame. */
1888 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1891 struct symtab
*symtab
;
1893 symtab
= find_pc_symtab (pc
);
1894 if (symtab
&& symtab
->epilogue_unwind_valid
)
1897 if (target_read_memory (pc
, &insn
, 1))
1898 return 0; /* Can't read memory at pc. */
1900 if (insn
!= 0xc3) /* 'ret' instruction. */
1907 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1908 struct frame_info
*this_frame
,
1909 void **this_prologue_cache
)
1911 if (frame_relative_level (this_frame
) == 0)
1912 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1913 get_frame_pc (this_frame
));
1918 static struct i386_frame_cache
*
1919 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1921 volatile struct gdb_exception ex
;
1922 struct i386_frame_cache
*cache
;
1928 cache
= i386_alloc_frame_cache ();
1929 *this_cache
= cache
;
1931 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1933 cache
->pc
= get_frame_func (this_frame
);
1935 /* At this point the stack looks as if we just entered the
1936 function, with the return address at the top of the
1938 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1939 cache
->base
= sp
+ cache
->sp_offset
;
1940 cache
->saved_sp
= cache
->base
+ 8;
1941 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1945 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1946 throw_exception (ex
);
1951 static enum unwind_stop_reason
1952 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1955 struct i386_frame_cache
*cache
=
1956 i386_epilogue_frame_cache (this_frame
, this_cache
);
1959 return UNWIND_UNAVAILABLE
;
1961 return UNWIND_NO_REASON
;
1965 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1967 struct frame_id
*this_id
)
1969 struct i386_frame_cache
*cache
=
1970 i386_epilogue_frame_cache (this_frame
, this_cache
);
1975 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1978 static struct value
*
1979 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1980 void **this_cache
, int regnum
)
1982 /* Make sure we've initialized the cache. */
1983 i386_epilogue_frame_cache (this_frame
, this_cache
);
1985 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1988 static const struct frame_unwind i386_epilogue_frame_unwind
=
1991 i386_epilogue_frame_unwind_stop_reason
,
1992 i386_epilogue_frame_this_id
,
1993 i386_epilogue_frame_prev_register
,
1995 i386_epilogue_frame_sniffer
1999 /* Stack-based trampolines. */
2001 /* These trampolines are used on cross x86 targets, when taking the
2002 address of a nested function. When executing these trampolines,
2003 no stack frame is set up, so we are in a similar situation as in
2004 epilogues and i386_epilogue_frame_this_id can be re-used. */
2006 /* Static chain passed in register. */
2008 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2010 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2011 { 5, { 0xb8 }, { 0xfe } },
2014 { 5, { 0xe9 }, { 0xff } },
2019 /* Static chain passed on stack (when regparm=3). */
2021 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2024 { 5, { 0x68 }, { 0xff } },
2027 { 5, { 0xe9 }, { 0xff } },
2032 /* Return whether PC points inside a stack trampoline. */
2035 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2040 /* A stack trampoline is detected if no name is associated
2041 to the current pc and if it points inside a trampoline
2044 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2048 if (target_read_memory (pc
, &insn
, 1))
2051 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2052 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2059 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2060 struct frame_info
*this_frame
,
2063 if (frame_relative_level (this_frame
) == 0)
2064 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2065 get_frame_pc (this_frame
));
2070 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2073 i386_epilogue_frame_unwind_stop_reason
,
2074 i386_epilogue_frame_this_id
,
2075 i386_epilogue_frame_prev_register
,
2077 i386_stack_tramp_frame_sniffer
2080 /* Generate a bytecode expression to get the value of the saved PC. */
2083 i386_gen_return_address (struct gdbarch
*gdbarch
,
2084 struct agent_expr
*ax
, struct axs_value
*value
,
2087 /* The following sequence assumes the traditional use of the base
2089 ax_reg (ax
, I386_EBP_REGNUM
);
2091 ax_simple (ax
, aop_add
);
2092 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2093 value
->kind
= axs_lvalue_memory
;
2097 /* Signal trampolines. */
2099 static struct i386_frame_cache
*
2100 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2102 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2103 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2104 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2105 volatile struct gdb_exception ex
;
2106 struct i386_frame_cache
*cache
;
2113 cache
= i386_alloc_frame_cache ();
2115 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2117 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2118 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2120 addr
= tdep
->sigcontext_addr (this_frame
);
2121 if (tdep
->sc_reg_offset
)
2125 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2127 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2128 if (tdep
->sc_reg_offset
[i
] != -1)
2129 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2133 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2134 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2139 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2140 throw_exception (ex
);
2142 *this_cache
= cache
;
2146 static enum unwind_stop_reason
2147 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2150 struct i386_frame_cache
*cache
=
2151 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2154 return UNWIND_UNAVAILABLE
;
2156 return UNWIND_NO_REASON
;
2160 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2161 struct frame_id
*this_id
)
2163 struct i386_frame_cache
*cache
=
2164 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2169 /* See the end of i386_push_dummy_call. */
2170 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2173 static struct value
*
2174 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2175 void **this_cache
, int regnum
)
2177 /* Make sure we've initialized the cache. */
2178 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2180 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2184 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2185 struct frame_info
*this_frame
,
2186 void **this_prologue_cache
)
2188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2190 /* We shouldn't even bother if we don't have a sigcontext_addr
2192 if (tdep
->sigcontext_addr
== NULL
)
2195 if (tdep
->sigtramp_p
!= NULL
)
2197 if (tdep
->sigtramp_p (this_frame
))
2201 if (tdep
->sigtramp_start
!= 0)
2203 CORE_ADDR pc
= get_frame_pc (this_frame
);
2205 gdb_assert (tdep
->sigtramp_end
!= 0);
2206 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2213 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2216 i386_sigtramp_frame_unwind_stop_reason
,
2217 i386_sigtramp_frame_this_id
,
2218 i386_sigtramp_frame_prev_register
,
2220 i386_sigtramp_frame_sniffer
2225 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2227 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2232 static const struct frame_base i386_frame_base
=
2235 i386_frame_base_address
,
2236 i386_frame_base_address
,
2237 i386_frame_base_address
2240 static struct frame_id
2241 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2245 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2247 /* See the end of i386_push_dummy_call. */
2248 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2251 /* _Decimal128 function return values need 16-byte alignment on the
2255 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2257 return sp
& -(CORE_ADDR
)16;
2261 /* Figure out where the longjmp will land. Slurp the args out of the
2262 stack. We expect the first arg to be a pointer to the jmp_buf
2263 structure from which we extract the address that we will land at.
2264 This address is copied into PC. This routine returns non-zero on
2268 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2271 CORE_ADDR sp
, jb_addr
;
2272 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2273 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2274 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2276 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2277 longjmp will land. */
2278 if (jb_pc_offset
== -1)
2281 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2282 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2283 if (target_read_memory (sp
+ 4, buf
, 4))
2286 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2287 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2290 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2295 /* Check whether TYPE must be 16-byte-aligned when passed as a
2296 function argument. 16-byte vectors, _Decimal128 and structures or
2297 unions containing such types must be 16-byte-aligned; other
2298 arguments are 4-byte-aligned. */
2301 i386_16_byte_align_p (struct type
*type
)
2303 type
= check_typedef (type
);
2304 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2305 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2306 && TYPE_LENGTH (type
) == 16)
2308 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2309 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2310 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2311 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2314 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2316 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2324 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2325 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2326 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2327 CORE_ADDR struct_addr
)
2329 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2335 /* Determine the total space required for arguments and struct
2336 return address in a first pass (allowing for 16-byte-aligned
2337 arguments), then push arguments in a second pass. */
2339 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2341 int args_space_used
= 0;
2342 int have_16_byte_aligned_arg
= 0;
2348 /* Push value address. */
2349 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2350 write_memory (sp
, buf
, 4);
2351 args_space_used
+= 4;
2357 for (i
= 0; i
< nargs
; i
++)
2359 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2363 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2364 args_space_used
= align_up (args_space_used
, 16);
2366 write_memory (sp
+ args_space_used
,
2367 value_contents_all (args
[i
]), len
);
2368 /* The System V ABI says that:
2370 "An argument's size is increased, if necessary, to make it a
2371 multiple of [32-bit] words. This may require tail padding,
2372 depending on the size of the argument."
2374 This makes sure the stack stays word-aligned. */
2375 args_space_used
+= align_up (len
, 4);
2379 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2381 args_space
= align_up (args_space
, 16);
2382 have_16_byte_aligned_arg
= 1;
2384 args_space
+= align_up (len
, 4);
2390 if (have_16_byte_aligned_arg
)
2391 args_space
= align_up (args_space
, 16);
2396 /* Store return address. */
2398 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2399 write_memory (sp
, buf
, 4);
2401 /* Finally, update the stack pointer... */
2402 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2403 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2405 /* ...and fake a frame pointer. */
2406 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2408 /* MarkK wrote: This "+ 8" is all over the place:
2409 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2410 i386_dummy_id). It's there, since all frame unwinders for
2411 a given target have to agree (within a certain margin) on the
2412 definition of the stack address of a frame. Otherwise frame id
2413 comparison might not work correctly. Since DWARF2/GCC uses the
2414 stack address *before* the function call as a frame's CFA. On
2415 the i386, when %ebp is used as a frame pointer, the offset
2416 between the contents %ebp and the CFA as defined by GCC. */
2420 /* These registers are used for returning integers (and on some
2421 targets also for returning `struct' and `union' values when their
2422 size and alignment match an integer type). */
2423 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2424 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2426 /* Read, for architecture GDBARCH, a function return value of TYPE
2427 from REGCACHE, and copy that into VALBUF. */
2430 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2431 struct regcache
*regcache
, gdb_byte
*valbuf
)
2433 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2434 int len
= TYPE_LENGTH (type
);
2435 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2437 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2439 if (tdep
->st0_regnum
< 0)
2441 warning (_("Cannot find floating-point return value."));
2442 memset (valbuf
, 0, len
);
2446 /* Floating-point return values can be found in %st(0). Convert
2447 its contents to the desired type. This is probably not
2448 exactly how it would happen on the target itself, but it is
2449 the best we can do. */
2450 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2451 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2455 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2456 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2458 if (len
<= low_size
)
2460 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2461 memcpy (valbuf
, buf
, len
);
2463 else if (len
<= (low_size
+ high_size
))
2465 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2466 memcpy (valbuf
, buf
, low_size
);
2467 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2468 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2471 internal_error (__FILE__
, __LINE__
,
2472 _("Cannot extract return value of %d bytes long."),
2477 /* Write, for architecture GDBARCH, a function return value of TYPE
2478 from VALBUF into REGCACHE. */
2481 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2482 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2485 int len
= TYPE_LENGTH (type
);
2487 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2490 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2492 if (tdep
->st0_regnum
< 0)
2494 warning (_("Cannot set floating-point return value."));
2498 /* Returning floating-point values is a bit tricky. Apart from
2499 storing the return value in %st(0), we have to simulate the
2500 state of the FPU at function return point. */
2502 /* Convert the value found in VALBUF to the extended
2503 floating-point format used by the FPU. This is probably
2504 not exactly how it would happen on the target itself, but
2505 it is the best we can do. */
2506 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2507 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2509 /* Set the top of the floating-point register stack to 7. The
2510 actual value doesn't really matter, but 7 is what a normal
2511 function return would end up with if the program started out
2512 with a freshly initialized FPU. */
2513 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2515 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2517 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2518 the floating-point register stack to 7, the appropriate value
2519 for the tag word is 0x3fff. */
2520 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2524 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2525 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2527 if (len
<= low_size
)
2528 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2529 else if (len
<= (low_size
+ high_size
))
2531 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2532 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2533 len
- low_size
, valbuf
+ low_size
);
2536 internal_error (__FILE__
, __LINE__
,
2537 _("Cannot store return value of %d bytes long."), len
);
2542 /* This is the variable that is set with "set struct-convention", and
2543 its legitimate values. */
2544 static const char default_struct_convention
[] = "default";
2545 static const char pcc_struct_convention
[] = "pcc";
2546 static const char reg_struct_convention
[] = "reg";
2547 static const char *valid_conventions
[] =
2549 default_struct_convention
,
2550 pcc_struct_convention
,
2551 reg_struct_convention
,
2554 static const char *struct_convention
= default_struct_convention
;
2556 /* Return non-zero if TYPE, which is assumed to be a structure,
2557 a union type, or an array type, should be returned in registers
2558 for architecture GDBARCH. */
2561 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2564 enum type_code code
= TYPE_CODE (type
);
2565 int len
= TYPE_LENGTH (type
);
2567 gdb_assert (code
== TYPE_CODE_STRUCT
2568 || code
== TYPE_CODE_UNION
2569 || code
== TYPE_CODE_ARRAY
);
2571 if (struct_convention
== pcc_struct_convention
2572 || (struct_convention
== default_struct_convention
2573 && tdep
->struct_return
== pcc_struct_return
))
2576 /* Structures consisting of a single `float', `double' or 'long
2577 double' member are returned in %st(0). */
2578 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2580 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2581 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2582 return (len
== 4 || len
== 8 || len
== 12);
2585 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2588 /* Determine, for architecture GDBARCH, how a return value of TYPE
2589 should be returned. If it is supposed to be returned in registers,
2590 and READBUF is non-zero, read the appropriate value from REGCACHE,
2591 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2592 from WRITEBUF into REGCACHE. */
2594 static enum return_value_convention
2595 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2596 struct type
*type
, struct regcache
*regcache
,
2597 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2599 enum type_code code
= TYPE_CODE (type
);
2601 if (((code
== TYPE_CODE_STRUCT
2602 || code
== TYPE_CODE_UNION
2603 || code
== TYPE_CODE_ARRAY
)
2604 && !i386_reg_struct_return_p (gdbarch
, type
))
2605 /* 128-bit decimal float uses the struct return convention. */
2606 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2608 /* The System V ABI says that:
2610 "A function that returns a structure or union also sets %eax
2611 to the value of the original address of the caller's area
2612 before it returns. Thus when the caller receives control
2613 again, the address of the returned object resides in register
2614 %eax and can be used to access the object."
2616 So the ABI guarantees that we can always find the return
2617 value just after the function has returned. */
2619 /* Note that the ABI doesn't mention functions returning arrays,
2620 which is something possible in certain languages such as Ada.
2621 In this case, the value is returned as if it was wrapped in
2622 a record, so the convention applied to records also applies
2629 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2630 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2633 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2636 /* This special case is for structures consisting of a single
2637 `float', `double' or 'long double' member. These structures are
2638 returned in %st(0). For these structures, we call ourselves
2639 recursively, changing TYPE into the type of the first member of
2640 the structure. Since that should work for all structures that
2641 have only one member, we don't bother to check the member's type
2643 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2645 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2646 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2651 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2653 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2655 return RETURN_VALUE_REGISTER_CONVENTION
;
2660 i387_ext_type (struct gdbarch
*gdbarch
)
2662 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2664 if (!tdep
->i387_ext_type
)
2666 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2667 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2670 return tdep
->i387_ext_type
;
2673 /* Construct vector type for pseudo YMM registers. We can't use
2674 tdesc_find_type since YMM isn't described in target description. */
2676 static struct type
*
2677 i386_ymm_type (struct gdbarch
*gdbarch
)
2679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2681 if (!tdep
->i386_ymm_type
)
2683 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2685 /* The type we're building is this: */
2687 union __gdb_builtin_type_vec256i
2689 int128_t uint128
[2];
2690 int64_t v2_int64
[4];
2691 int32_t v4_int32
[8];
2692 int16_t v8_int16
[16];
2693 int8_t v16_int8
[32];
2694 double v2_double
[4];
2701 t
= arch_composite_type (gdbarch
,
2702 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2703 append_composite_type_field (t
, "v8_float",
2704 init_vector_type (bt
->builtin_float
, 8));
2705 append_composite_type_field (t
, "v4_double",
2706 init_vector_type (bt
->builtin_double
, 4));
2707 append_composite_type_field (t
, "v32_int8",
2708 init_vector_type (bt
->builtin_int8
, 32));
2709 append_composite_type_field (t
, "v16_int16",
2710 init_vector_type (bt
->builtin_int16
, 16));
2711 append_composite_type_field (t
, "v8_int32",
2712 init_vector_type (bt
->builtin_int32
, 8));
2713 append_composite_type_field (t
, "v4_int64",
2714 init_vector_type (bt
->builtin_int64
, 4));
2715 append_composite_type_field (t
, "v2_int128",
2716 init_vector_type (bt
->builtin_int128
, 2));
2718 TYPE_VECTOR (t
) = 1;
2719 TYPE_NAME (t
) = "builtin_type_vec256i";
2720 tdep
->i386_ymm_type
= t
;
2723 return tdep
->i386_ymm_type
;
2726 /* Construct vector type for MMX registers. */
2727 static struct type
*
2728 i386_mmx_type (struct gdbarch
*gdbarch
)
2730 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2732 if (!tdep
->i386_mmx_type
)
2734 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2736 /* The type we're building is this: */
2738 union __gdb_builtin_type_vec64i
2741 int32_t v2_int32
[2];
2742 int16_t v4_int16
[4];
2749 t
= arch_composite_type (gdbarch
,
2750 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2752 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2753 append_composite_type_field (t
, "v2_int32",
2754 init_vector_type (bt
->builtin_int32
, 2));
2755 append_composite_type_field (t
, "v4_int16",
2756 init_vector_type (bt
->builtin_int16
, 4));
2757 append_composite_type_field (t
, "v8_int8",
2758 init_vector_type (bt
->builtin_int8
, 8));
2760 TYPE_VECTOR (t
) = 1;
2761 TYPE_NAME (t
) = "builtin_type_vec64i";
2762 tdep
->i386_mmx_type
= t
;
2765 return tdep
->i386_mmx_type
;
2768 /* Return the GDB type object for the "standard" data type of data in
2771 static struct type
*
2772 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2774 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2775 return i386_mmx_type (gdbarch
);
2776 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2777 return i386_ymm_type (gdbarch
);
2780 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2781 if (i386_byte_regnum_p (gdbarch
, regnum
))
2782 return bt
->builtin_int8
;
2783 else if (i386_word_regnum_p (gdbarch
, regnum
))
2784 return bt
->builtin_int16
;
2785 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2786 return bt
->builtin_int32
;
2789 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2792 /* Map a cooked register onto a raw register or memory. For the i386,
2793 the MMX registers need to be mapped onto floating point registers. */
2796 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2803 mmxreg
= regnum
- tdep
->mm0_regnum
;
2804 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2805 tos
= (fstat
>> 11) & 0x7;
2806 fpreg
= (mmxreg
+ tos
) % 8;
2808 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2811 /* A helper function for us by i386_pseudo_register_read_value and
2812 amd64_pseudo_register_read_value. It does all the work but reads
2813 the data into an already-allocated value. */
2816 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2817 struct regcache
*regcache
,
2819 struct value
*result_value
)
2821 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2822 enum register_status status
;
2823 gdb_byte
*buf
= value_contents_raw (result_value
);
2825 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2827 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2829 /* Extract (always little endian). */
2830 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2831 if (status
!= REG_VALID
)
2832 mark_value_bytes_unavailable (result_value
, 0,
2833 TYPE_LENGTH (value_type (result_value
)));
2835 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2839 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2841 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2843 regnum
-= tdep
->ymm0_regnum
;
2845 /* Extract (always little endian). Read lower 128bits. */
2846 status
= regcache_raw_read (regcache
,
2847 I387_XMM0_REGNUM (tdep
) + regnum
,
2849 if (status
!= REG_VALID
)
2850 mark_value_bytes_unavailable (result_value
, 0, 16);
2852 memcpy (buf
, raw_buf
, 16);
2853 /* Read upper 128bits. */
2854 status
= regcache_raw_read (regcache
,
2855 tdep
->ymm0h_regnum
+ regnum
,
2857 if (status
!= REG_VALID
)
2858 mark_value_bytes_unavailable (result_value
, 16, 32);
2860 memcpy (buf
+ 16, raw_buf
, 16);
2862 else if (i386_word_regnum_p (gdbarch
, regnum
))
2864 int gpnum
= regnum
- tdep
->ax_regnum
;
2866 /* Extract (always little endian). */
2867 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2868 if (status
!= REG_VALID
)
2869 mark_value_bytes_unavailable (result_value
, 0,
2870 TYPE_LENGTH (value_type (result_value
)));
2872 memcpy (buf
, raw_buf
, 2);
2874 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2876 /* Check byte pseudo registers last since this function will
2877 be called from amd64_pseudo_register_read, which handles
2878 byte pseudo registers differently. */
2879 int gpnum
= regnum
- tdep
->al_regnum
;
2881 /* Extract (always little endian). We read both lower and
2883 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2884 if (status
!= REG_VALID
)
2885 mark_value_bytes_unavailable (result_value
, 0,
2886 TYPE_LENGTH (value_type (result_value
)));
2887 else if (gpnum
>= 4)
2888 memcpy (buf
, raw_buf
+ 1, 1);
2890 memcpy (buf
, raw_buf
, 1);
2893 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2897 static struct value
*
2898 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2899 struct regcache
*regcache
,
2902 struct value
*result
;
2904 result
= allocate_value (register_type (gdbarch
, regnum
));
2905 VALUE_LVAL (result
) = lval_register
;
2906 VALUE_REGNUM (result
) = regnum
;
2908 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2914 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2915 int regnum
, const gdb_byte
*buf
)
2917 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2919 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2921 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2924 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2925 /* ... Modify ... (always little endian). */
2926 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2928 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2932 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2934 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2936 regnum
-= tdep
->ymm0_regnum
;
2938 /* ... Write lower 128bits. */
2939 regcache_raw_write (regcache
,
2940 I387_XMM0_REGNUM (tdep
) + regnum
,
2942 /* ... Write upper 128bits. */
2943 regcache_raw_write (regcache
,
2944 tdep
->ymm0h_regnum
+ regnum
,
2947 else if (i386_word_regnum_p (gdbarch
, regnum
))
2949 int gpnum
= regnum
- tdep
->ax_regnum
;
2952 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2953 /* ... Modify ... (always little endian). */
2954 memcpy (raw_buf
, buf
, 2);
2956 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2958 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2960 /* Check byte pseudo registers last since this function will
2961 be called from amd64_pseudo_register_read, which handles
2962 byte pseudo registers differently. */
2963 int gpnum
= regnum
- tdep
->al_regnum
;
2965 /* Read ... We read both lower and upper registers. */
2966 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2967 /* ... Modify ... (always little endian). */
2969 memcpy (raw_buf
+ 1, buf
, 1);
2971 memcpy (raw_buf
, buf
, 1);
2973 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2976 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2981 /* Return the register number of the register allocated by GCC after
2982 REGNUM, or -1 if there is no such register. */
2985 i386_next_regnum (int regnum
)
2987 /* GCC allocates the registers in the order:
2989 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2991 Since storing a variable in %esp doesn't make any sense we return
2992 -1 for %ebp and for %esp itself. */
2993 static int next_regnum
[] =
2995 I386_EDX_REGNUM
, /* Slot for %eax. */
2996 I386_EBX_REGNUM
, /* Slot for %ecx. */
2997 I386_ECX_REGNUM
, /* Slot for %edx. */
2998 I386_ESI_REGNUM
, /* Slot for %ebx. */
2999 -1, -1, /* Slots for %esp and %ebp. */
3000 I386_EDI_REGNUM
, /* Slot for %esi. */
3001 I386_EBP_REGNUM
/* Slot for %edi. */
3004 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3005 return next_regnum
[regnum
];
3010 /* Return nonzero if a value of type TYPE stored in register REGNUM
3011 needs any special handling. */
3014 i386_convert_register_p (struct gdbarch
*gdbarch
,
3015 int regnum
, struct type
*type
)
3017 int len
= TYPE_LENGTH (type
);
3019 /* Values may be spread across multiple registers. Most debugging
3020 formats aren't expressive enough to specify the locations, so
3021 some heuristics is involved. Right now we only handle types that
3022 have a length that is a multiple of the word size, since GCC
3023 doesn't seem to put any other types into registers. */
3024 if (len
> 4 && len
% 4 == 0)
3026 int last_regnum
= regnum
;
3030 last_regnum
= i386_next_regnum (last_regnum
);
3034 if (last_regnum
!= -1)
3038 return i387_convert_register_p (gdbarch
, regnum
, type
);
3041 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3042 return its contents in TO. */
3045 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3046 struct type
*type
, gdb_byte
*to
,
3047 int *optimizedp
, int *unavailablep
)
3049 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3050 int len
= TYPE_LENGTH (type
);
3052 if (i386_fp_regnum_p (gdbarch
, regnum
))
3053 return i387_register_to_value (frame
, regnum
, type
, to
,
3054 optimizedp
, unavailablep
);
3056 /* Read a value spread across multiple registers. */
3058 gdb_assert (len
> 4 && len
% 4 == 0);
3062 gdb_assert (regnum
!= -1);
3063 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3065 if (!get_frame_register_bytes (frame
, regnum
, 0,
3066 register_size (gdbarch
, regnum
),
3067 to
, optimizedp
, unavailablep
))
3070 regnum
= i386_next_regnum (regnum
);
3075 *optimizedp
= *unavailablep
= 0;
3079 /* Write the contents FROM of a value of type TYPE into register
3080 REGNUM in frame FRAME. */
3083 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3084 struct type
*type
, const gdb_byte
*from
)
3086 int len
= TYPE_LENGTH (type
);
3088 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3090 i387_value_to_register (frame
, regnum
, type
, from
);
3094 /* Write a value spread across multiple registers. */
3096 gdb_assert (len
> 4 && len
% 4 == 0);
3100 gdb_assert (regnum
!= -1);
3101 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3103 put_frame_register (frame
, regnum
, from
);
3104 regnum
= i386_next_regnum (regnum
);
3110 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3111 in the general-purpose register set REGSET to register cache
3112 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3115 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3116 int regnum
, const void *gregs
, size_t len
)
3118 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3119 const gdb_byte
*regs
= gregs
;
3122 gdb_assert (len
== tdep
->sizeof_gregset
);
3124 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3126 if ((regnum
== i
|| regnum
== -1)
3127 && tdep
->gregset_reg_offset
[i
] != -1)
3128 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3132 /* Collect register REGNUM from the register cache REGCACHE and store
3133 it in the buffer specified by GREGS and LEN as described by the
3134 general-purpose register set REGSET. If REGNUM is -1, do this for
3135 all registers in REGSET. */
3138 i386_collect_gregset (const struct regset
*regset
,
3139 const struct regcache
*regcache
,
3140 int regnum
, void *gregs
, size_t len
)
3142 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3143 gdb_byte
*regs
= gregs
;
3146 gdb_assert (len
== tdep
->sizeof_gregset
);
3148 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3150 if ((regnum
== i
|| regnum
== -1)
3151 && tdep
->gregset_reg_offset
[i
] != -1)
3152 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3156 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3157 in the floating-point register set REGSET to register cache
3158 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3161 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3162 int regnum
, const void *fpregs
, size_t len
)
3164 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3166 if (len
== I387_SIZEOF_FXSAVE
)
3168 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3172 gdb_assert (len
== tdep
->sizeof_fpregset
);
3173 i387_supply_fsave (regcache
, regnum
, fpregs
);
3176 /* Collect register REGNUM from the register cache REGCACHE and store
3177 it in the buffer specified by FPREGS and LEN as described by the
3178 floating-point register set REGSET. If REGNUM is -1, do this for
3179 all registers in REGSET. */
3182 i386_collect_fpregset (const struct regset
*regset
,
3183 const struct regcache
*regcache
,
3184 int regnum
, void *fpregs
, size_t len
)
3186 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3188 if (len
== I387_SIZEOF_FXSAVE
)
3190 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3194 gdb_assert (len
== tdep
->sizeof_fpregset
);
3195 i387_collect_fsave (regcache
, regnum
, fpregs
);
3198 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3201 i386_supply_xstateregset (const struct regset
*regset
,
3202 struct regcache
*regcache
, int regnum
,
3203 const void *xstateregs
, size_t len
)
3205 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3208 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3211 i386_collect_xstateregset (const struct regset
*regset
,
3212 const struct regcache
*regcache
,
3213 int regnum
, void *xstateregs
, size_t len
)
3215 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3218 /* Return the appropriate register set for the core section identified
3219 by SECT_NAME and SECT_SIZE. */
3221 const struct regset
*
3222 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3223 const char *sect_name
, size_t sect_size
)
3225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3227 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3229 if (tdep
->gregset
== NULL
)
3230 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3231 i386_collect_gregset
);
3232 return tdep
->gregset
;
3235 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3236 || (strcmp (sect_name
, ".reg-xfp") == 0
3237 && sect_size
== I387_SIZEOF_FXSAVE
))
3239 if (tdep
->fpregset
== NULL
)
3240 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3241 i386_collect_fpregset
);
3242 return tdep
->fpregset
;
3245 if (strcmp (sect_name
, ".reg-xstate") == 0)
3247 if (tdep
->xstateregset
== NULL
)
3248 tdep
->xstateregset
= regset_alloc (gdbarch
,
3249 i386_supply_xstateregset
,
3250 i386_collect_xstateregset
);
3252 return tdep
->xstateregset
;
3259 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3262 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3263 CORE_ADDR pc
, char *name
)
3265 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3266 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3269 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3271 unsigned long indirect
=
3272 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3273 struct minimal_symbol
*indsym
=
3274 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3275 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3279 if (strncmp (symname
, "__imp_", 6) == 0
3280 || strncmp (symname
, "_imp_", 5) == 0)
3282 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3285 return 0; /* Not a trampoline. */
3289 /* Return whether the THIS_FRAME corresponds to a sigtramp
3293 i386_sigtramp_p (struct frame_info
*this_frame
)
3295 CORE_ADDR pc
= get_frame_pc (this_frame
);
3298 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3299 return (name
&& strcmp ("_sigtramp", name
) == 0);
3303 /* We have two flavours of disassembly. The machinery on this page
3304 deals with switching between those. */
3307 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3309 gdb_assert (disassembly_flavor
== att_flavor
3310 || disassembly_flavor
== intel_flavor
);
3312 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3313 constified, cast to prevent a compiler warning. */
3314 info
->disassembler_options
= (char *) disassembly_flavor
;
3316 return print_insn_i386 (pc
, info
);
3320 /* There are a few i386 architecture variants that differ only
3321 slightly from the generic i386 target. For now, we don't give them
3322 their own source file, but include them here. As a consequence,
3323 they'll always be included. */
3325 /* System V Release 4 (SVR4). */
3327 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3331 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3333 CORE_ADDR pc
= get_frame_pc (this_frame
);
3336 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3337 currently unknown. */
3338 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3339 return (name
&& (strcmp ("_sigreturn", name
) == 0
3340 || strcmp ("_sigacthandler", name
) == 0
3341 || strcmp ("sigvechandler", name
) == 0));
3344 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3345 address of the associated sigcontext (ucontext) structure. */
3348 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3350 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3351 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3355 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3356 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3358 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3365 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3367 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3368 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3371 /* System V Release 4 (SVR4). */
3374 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3376 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3378 /* System V Release 4 uses ELF. */
3379 i386_elf_init_abi (info
, gdbarch
);
3381 /* System V Release 4 has shared libraries. */
3382 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3384 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3385 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3386 tdep
->sc_pc_offset
= 36 + 14 * 4;
3387 tdep
->sc_sp_offset
= 36 + 17 * 4;
3389 tdep
->jb_pc_offset
= 20;
3395 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3399 /* DJGPP doesn't have any special frames for signal handlers. */
3400 tdep
->sigtramp_p
= NULL
;
3402 tdep
->jb_pc_offset
= 36;
3404 /* DJGPP does not support the SSE registers. */
3405 if (! tdesc_has_registers (info
.target_desc
))
3406 tdep
->tdesc
= tdesc_i386_mmx
;
3408 /* Native compiler is GCC, which uses the SVR4 register numbering
3409 even in COFF and STABS. See the comment in i386_gdbarch_init,
3410 before the calls to set_gdbarch_stab_reg_to_regnum and
3411 set_gdbarch_sdb_reg_to_regnum. */
3412 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3413 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3415 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3419 /* i386 register groups. In addition to the normal groups, add "mmx"
3422 static struct reggroup
*i386_sse_reggroup
;
3423 static struct reggroup
*i386_mmx_reggroup
;
3426 i386_init_reggroups (void)
3428 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3429 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3433 i386_add_reggroups (struct gdbarch
*gdbarch
)
3435 reggroup_add (gdbarch
, i386_sse_reggroup
);
3436 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3437 reggroup_add (gdbarch
, general_reggroup
);
3438 reggroup_add (gdbarch
, float_reggroup
);
3439 reggroup_add (gdbarch
, all_reggroup
);
3440 reggroup_add (gdbarch
, save_reggroup
);
3441 reggroup_add (gdbarch
, restore_reggroup
);
3442 reggroup_add (gdbarch
, vector_reggroup
);
3443 reggroup_add (gdbarch
, system_reggroup
);
3447 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3448 struct reggroup
*group
)
3450 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3451 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3452 ymm_regnum_p
, ymmh_regnum_p
;
3454 /* Don't include pseudo registers, except for MMX, in any register
3456 if (i386_byte_regnum_p (gdbarch
, regnum
))
3459 if (i386_word_regnum_p (gdbarch
, regnum
))
3462 if (i386_dword_regnum_p (gdbarch
, regnum
))
3465 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3466 if (group
== i386_mmx_reggroup
)
3467 return mmx_regnum_p
;
3469 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3470 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3471 if (group
== i386_sse_reggroup
)
3472 return xmm_regnum_p
|| mxcsr_regnum_p
;
3474 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3475 if (group
== vector_reggroup
)
3476 return (mmx_regnum_p
3480 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3481 == I386_XSTATE_SSE_MASK
)));
3483 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3484 || i386_fpc_regnum_p (gdbarch
, regnum
));
3485 if (group
== float_reggroup
)
3488 /* For "info reg all", don't include upper YMM registers nor XMM
3489 registers when AVX is supported. */
3490 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3491 if (group
== all_reggroup
3493 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3497 if (group
== general_reggroup
)
3498 return (!fp_regnum_p
3505 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3509 /* Get the ARGIth function argument for the current function. */
3512 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3516 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3517 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3518 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3522 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3524 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3526 /* On i386, breakpoint is exactly 1 byte long, so we just
3527 adjust the PC in the regcache. */
3529 regcache_write_pc (regcache
, current_pc
);
3533 #define PREFIX_REPZ 0x01
3534 #define PREFIX_REPNZ 0x02
3535 #define PREFIX_LOCK 0x04
3536 #define PREFIX_DATA 0x08
3537 #define PREFIX_ADDR 0x10
3549 /* i386 arith/logic operations */
3562 struct i386_record_s
3564 struct gdbarch
*gdbarch
;
3565 struct regcache
*regcache
;
3566 CORE_ADDR orig_addr
;
3572 uint8_t mod
, reg
, rm
;
3581 /* Parse "modrm" part in current memory address that irp->addr point to
3582 Return -1 if something wrong. */
3585 i386_record_modrm (struct i386_record_s
*irp
)
3587 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3589 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3592 printf_unfiltered (_("Process record: error reading memory at "
3593 "addr %s len = 1.\n"),
3594 paddress (gdbarch
, irp
->addr
));
3598 irp
->mod
= (irp
->modrm
>> 6) & 3;
3599 irp
->reg
= (irp
->modrm
>> 3) & 7;
3600 irp
->rm
= irp
->modrm
& 7;
3605 /* Get the memory address that current instruction write to and set it to
3606 the argument "addr".
3607 Return -1 if something wrong. */
3610 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3612 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3613 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3625 uint8_t base
= irp
->rm
;
3630 if (target_read_memory (irp
->addr
, &byte
, 1))
3633 printf_unfiltered (_("Process record: error reading memory "
3634 "at addr %s len = 1.\n"),
3635 paddress (gdbarch
, irp
->addr
));
3639 scale
= (byte
>> 6) & 3;
3640 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3648 if ((base
& 7) == 5)
3651 if (target_read_memory (irp
->addr
, buf
, 4))
3654 printf_unfiltered (_("Process record: error reading "
3655 "memory at addr %s len = 4.\n"),
3656 paddress (gdbarch
, irp
->addr
));
3660 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3661 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3662 *addr
+= irp
->addr
+ irp
->rip_offset
;
3666 if (target_read_memory (irp
->addr
, buf
, 1))
3669 printf_unfiltered (_("Process record: error reading memory "
3670 "at addr %s len = 1.\n"),
3671 paddress (gdbarch
, irp
->addr
));
3675 *addr
= (int8_t) buf
[0];
3678 if (target_read_memory (irp
->addr
, buf
, 4))
3681 printf_unfiltered (_("Process record: error reading memory "
3682 "at addr %s len = 4.\n"),
3683 paddress (gdbarch
, irp
->addr
));
3686 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3694 if (base
== 4 && irp
->popl_esp_hack
)
3695 *addr
+= irp
->popl_esp_hack
;
3696 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3699 if (irp
->aflag
== 2)
3704 *addr
= (uint32_t) (offset64
+ *addr
);
3706 if (havesib
&& (index
!= 4 || scale
!= 0))
3708 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3710 if (irp
->aflag
== 2)
3711 *addr
+= offset64
<< scale
;
3713 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3724 if (target_read_memory (irp
->addr
, buf
, 2))
3727 printf_unfiltered (_("Process record: error reading "
3728 "memory at addr %s len = 2.\n"),
3729 paddress (gdbarch
, irp
->addr
));
3733 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3739 if (target_read_memory (irp
->addr
, buf
, 1))
3742 printf_unfiltered (_("Process record: error reading memory "
3743 "at addr %s len = 1.\n"),
3744 paddress (gdbarch
, irp
->addr
));
3748 *addr
= (int8_t) buf
[0];
3751 if (target_read_memory (irp
->addr
, buf
, 2))
3754 printf_unfiltered (_("Process record: error reading memory "
3755 "at addr %s len = 2.\n"),
3756 paddress (gdbarch
, irp
->addr
));
3760 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3767 regcache_raw_read_unsigned (irp
->regcache
,
3768 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3770 *addr
= (uint32_t) (*addr
+ offset64
);
3771 regcache_raw_read_unsigned (irp
->regcache
,
3772 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3774 *addr
= (uint32_t) (*addr
+ offset64
);
3777 regcache_raw_read_unsigned (irp
->regcache
,
3778 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3780 *addr
= (uint32_t) (*addr
+ offset64
);
3781 regcache_raw_read_unsigned (irp
->regcache
,
3782 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3784 *addr
= (uint32_t) (*addr
+ offset64
);
3787 regcache_raw_read_unsigned (irp
->regcache
,
3788 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3790 *addr
= (uint32_t) (*addr
+ offset64
);
3791 regcache_raw_read_unsigned (irp
->regcache
,
3792 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3794 *addr
= (uint32_t) (*addr
+ offset64
);
3797 regcache_raw_read_unsigned (irp
->regcache
,
3798 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3800 *addr
= (uint32_t) (*addr
+ offset64
);
3801 regcache_raw_read_unsigned (irp
->regcache
,
3802 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3804 *addr
= (uint32_t) (*addr
+ offset64
);
3807 regcache_raw_read_unsigned (irp
->regcache
,
3808 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3810 *addr
= (uint32_t) (*addr
+ offset64
);
3813 regcache_raw_read_unsigned (irp
->regcache
,
3814 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3816 *addr
= (uint32_t) (*addr
+ offset64
);
3819 regcache_raw_read_unsigned (irp
->regcache
,
3820 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3822 *addr
= (uint32_t) (*addr
+ offset64
);
3825 regcache_raw_read_unsigned (irp
->regcache
,
3826 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3828 *addr
= (uint32_t) (*addr
+ offset64
);
3838 /* Record the value of the memory that willbe changed in current instruction
3839 to "record_arch_list".
3840 Return -1 if something wrong. */
3843 i386_record_lea_modrm (struct i386_record_s
*irp
)
3845 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3848 if (irp
->override
>= 0)
3850 if (record_memory_query
)
3854 target_terminal_ours ();
3856 Process record ignores the memory change of instruction at address %s\n\
3857 because it can't get the value of the segment register.\n\
3858 Do you want to stop the program?"),
3859 paddress (gdbarch
, irp
->orig_addr
));
3860 target_terminal_inferior ();
3868 if (i386_record_lea_modrm_addr (irp
, &addr
))
3871 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3877 /* Record the push operation to "record_arch_list".
3878 Return -1 if something wrong. */
3881 i386_record_push (struct i386_record_s
*irp
, int size
)
3885 if (record_arch_list_add_reg (irp
->regcache
,
3886 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3888 regcache_raw_read_unsigned (irp
->regcache
,
3889 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3891 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3898 /* Defines contents to record. */
3899 #define I386_SAVE_FPU_REGS 0xfffd
3900 #define I386_SAVE_FPU_ENV 0xfffe
3901 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3903 /* Record the value of floating point registers which will be changed
3904 by the current instruction to "record_arch_list". Return -1 if
3905 something is wrong. */
3907 static int i386_record_floats (struct gdbarch
*gdbarch
,
3908 struct i386_record_s
*ir
,
3911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3914 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3915 happen. Currently we store st0-st7 registers, but we need not store all
3916 registers all the time, in future we use ftag register and record only
3917 those who are not marked as an empty. */
3919 if (I386_SAVE_FPU_REGS
== iregnum
)
3921 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3923 if (record_arch_list_add_reg (ir
->regcache
, i
))
3927 else if (I386_SAVE_FPU_ENV
== iregnum
)
3929 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3931 if (record_arch_list_add_reg (ir
->regcache
, i
))
3935 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3937 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3939 if (record_arch_list_add_reg (ir
->regcache
, i
))
3943 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3944 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3946 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3951 /* Parameter error. */
3954 if(I386_SAVE_FPU_ENV
!= iregnum
)
3956 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3958 if (record_arch_list_add_reg (ir
->regcache
, i
))
3965 /* Parse the current instruction and record the values of the registers and
3966 memory that will be changed in current instruction to "record_arch_list".
3967 Return -1 if something wrong. */
3969 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3970 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3973 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3974 CORE_ADDR input_addr
)
3976 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3982 gdb_byte buf
[MAX_REGISTER_SIZE
];
3983 struct i386_record_s ir
;
3984 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3989 memset (&ir
, 0, sizeof (struct i386_record_s
));
3990 ir
.regcache
= regcache
;
3991 ir
.addr
= input_addr
;
3992 ir
.orig_addr
= input_addr
;
3996 ir
.popl_esp_hack
= 0;
3997 ir
.regmap
= tdep
->record_regmap
;
3998 ir
.gdbarch
= gdbarch
;
4000 if (record_debug
> 1)
4001 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4003 paddress (gdbarch
, ir
.addr
));
4008 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4011 printf_unfiltered (_("Process record: error reading memory at "
4012 "addr %s len = 1.\n"),
4013 paddress (gdbarch
, ir
.addr
));
4017 switch (opcode8
) /* Instruction prefixes */
4019 case REPE_PREFIX_OPCODE
:
4020 prefixes
|= PREFIX_REPZ
;
4022 case REPNE_PREFIX_OPCODE
:
4023 prefixes
|= PREFIX_REPNZ
;
4025 case LOCK_PREFIX_OPCODE
:
4026 prefixes
|= PREFIX_LOCK
;
4028 case CS_PREFIX_OPCODE
:
4029 ir
.override
= X86_RECORD_CS_REGNUM
;
4031 case SS_PREFIX_OPCODE
:
4032 ir
.override
= X86_RECORD_SS_REGNUM
;
4034 case DS_PREFIX_OPCODE
:
4035 ir
.override
= X86_RECORD_DS_REGNUM
;
4037 case ES_PREFIX_OPCODE
:
4038 ir
.override
= X86_RECORD_ES_REGNUM
;
4040 case FS_PREFIX_OPCODE
:
4041 ir
.override
= X86_RECORD_FS_REGNUM
;
4043 case GS_PREFIX_OPCODE
:
4044 ir
.override
= X86_RECORD_GS_REGNUM
;
4046 case DATA_PREFIX_OPCODE
:
4047 prefixes
|= PREFIX_DATA
;
4049 case ADDR_PREFIX_OPCODE
:
4050 prefixes
|= PREFIX_ADDR
;
4052 case 0x40: /* i386 inc %eax */
4053 case 0x41: /* i386 inc %ecx */
4054 case 0x42: /* i386 inc %edx */
4055 case 0x43: /* i386 inc %ebx */
4056 case 0x44: /* i386 inc %esp */
4057 case 0x45: /* i386 inc %ebp */
4058 case 0x46: /* i386 inc %esi */
4059 case 0x47: /* i386 inc %edi */
4060 case 0x48: /* i386 dec %eax */
4061 case 0x49: /* i386 dec %ecx */
4062 case 0x4a: /* i386 dec %edx */
4063 case 0x4b: /* i386 dec %ebx */
4064 case 0x4c: /* i386 dec %esp */
4065 case 0x4d: /* i386 dec %ebp */
4066 case 0x4e: /* i386 dec %esi */
4067 case 0x4f: /* i386 dec %edi */
4068 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4072 rex_w
= (opcode8
>> 3) & 1;
4073 rex_r
= (opcode8
& 0x4) << 1;
4074 ir
.rex_x
= (opcode8
& 0x2) << 2;
4075 ir
.rex_b
= (opcode8
& 0x1) << 3;
4077 else /* 32 bit target */
4086 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4092 if (prefixes
& PREFIX_DATA
)
4095 if (prefixes
& PREFIX_ADDR
)
4097 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4100 /* Now check op code. */
4101 opcode
= (uint32_t) opcode8
;
4106 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4109 printf_unfiltered (_("Process record: error reading memory at "
4110 "addr %s len = 1.\n"),
4111 paddress (gdbarch
, ir
.addr
));
4115 opcode
= (uint32_t) opcode8
| 0x0f00;
4119 case 0x00: /* arith & logic */
4167 if (((opcode
>> 3) & 7) != OP_CMPL
)
4169 if ((opcode
& 1) == 0)
4172 ir
.ot
= ir
.dflag
+ OT_WORD
;
4174 switch ((opcode
>> 1) & 3)
4176 case 0: /* OP Ev, Gv */
4177 if (i386_record_modrm (&ir
))
4181 if (i386_record_lea_modrm (&ir
))
4187 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4189 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4192 case 1: /* OP Gv, Ev */
4193 if (i386_record_modrm (&ir
))
4196 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4198 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4200 case 2: /* OP A, Iv */
4201 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4205 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4208 case 0x80: /* GRP1 */
4212 if (i386_record_modrm (&ir
))
4215 if (ir
.reg
!= OP_CMPL
)
4217 if ((opcode
& 1) == 0)
4220 ir
.ot
= ir
.dflag
+ OT_WORD
;
4227 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4228 if (i386_record_lea_modrm (&ir
))
4232 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4237 case 0x40: /* inc */
4246 case 0x48: /* dec */
4255 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4259 case 0xf6: /* GRP3 */
4261 if ((opcode
& 1) == 0)
4264 ir
.ot
= ir
.dflag
+ OT_WORD
;
4265 if (i386_record_modrm (&ir
))
4268 if (ir
.mod
!= 3 && ir
.reg
== 0)
4269 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4280 if (i386_record_lea_modrm (&ir
))
4286 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4288 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4290 if (ir
.reg
== 3) /* neg */
4291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4298 if (ir
.ot
!= OT_BYTE
)
4299 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4300 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4304 opcode
= opcode
<< 8 | ir
.modrm
;
4310 case 0xfe: /* GRP4 */
4311 case 0xff: /* GRP5 */
4312 if (i386_record_modrm (&ir
))
4314 if (ir
.reg
>= 2 && opcode
== 0xfe)
4317 opcode
= opcode
<< 8 | ir
.modrm
;
4324 if ((opcode
& 1) == 0)
4327 ir
.ot
= ir
.dflag
+ OT_WORD
;
4330 if (i386_record_lea_modrm (&ir
))
4336 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4338 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4343 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4345 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4350 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4351 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4353 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4357 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4360 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4362 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4367 opcode
= opcode
<< 8 | ir
.modrm
;
4373 case 0x84: /* test */
4377 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4380 case 0x98: /* CWDE/CBW */
4381 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4384 case 0x99: /* CDQ/CWD */
4385 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4386 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4389 case 0x0faf: /* imul */
4392 ir
.ot
= ir
.dflag
+ OT_WORD
;
4393 if (i386_record_modrm (&ir
))
4396 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4397 else if (opcode
== 0x6b)
4400 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4402 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4403 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4406 case 0x0fc0: /* xadd */
4408 if ((opcode
& 1) == 0)
4411 ir
.ot
= ir
.dflag
+ OT_WORD
;
4412 if (i386_record_modrm (&ir
))
4417 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4419 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4420 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4422 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4426 if (i386_record_lea_modrm (&ir
))
4428 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4430 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4432 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4435 case 0x0fb0: /* cmpxchg */
4437 if ((opcode
& 1) == 0)
4440 ir
.ot
= ir
.dflag
+ OT_WORD
;
4441 if (i386_record_modrm (&ir
))
4446 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4447 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4449 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4454 if (i386_record_lea_modrm (&ir
))
4457 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4460 case 0x0fc7: /* cmpxchg8b */
4461 if (i386_record_modrm (&ir
))
4466 opcode
= opcode
<< 8 | ir
.modrm
;
4469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4471 if (i386_record_lea_modrm (&ir
))
4473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4476 case 0x50: /* push */
4486 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4488 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4492 case 0x06: /* push es */
4493 case 0x0e: /* push cs */
4494 case 0x16: /* push ss */
4495 case 0x1e: /* push ds */
4496 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4501 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4505 case 0x0fa0: /* push fs */
4506 case 0x0fa8: /* push gs */
4507 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4512 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4516 case 0x60: /* pusha */
4517 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4522 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4526 case 0x58: /* pop */
4534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4535 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4538 case 0x61: /* popa */
4539 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4544 for (regnum
= X86_RECORD_REAX_REGNUM
;
4545 regnum
<= X86_RECORD_REDI_REGNUM
;
4547 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4550 case 0x8f: /* pop */
4551 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4552 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4554 ir
.ot
= ir
.dflag
+ OT_WORD
;
4555 if (i386_record_modrm (&ir
))
4558 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4561 ir
.popl_esp_hack
= 1 << ir
.ot
;
4562 if (i386_record_lea_modrm (&ir
))
4565 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4568 case 0xc8: /* enter */
4569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4570 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4572 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4576 case 0xc9: /* leave */
4577 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4581 case 0x07: /* pop es */
4582 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4587 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4588 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4589 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4592 case 0x17: /* pop ss */
4593 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4600 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4603 case 0x1f: /* pop ds */
4604 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4609 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4614 case 0x0fa1: /* pop fs */
4615 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4617 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4620 case 0x0fa9: /* pop gs */
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4626 case 0x88: /* mov */
4630 if ((opcode
& 1) == 0)
4633 ir
.ot
= ir
.dflag
+ OT_WORD
;
4635 if (i386_record_modrm (&ir
))
4640 if (opcode
== 0xc6 || opcode
== 0xc7)
4641 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4642 if (i386_record_lea_modrm (&ir
))
4647 if (opcode
== 0xc6 || opcode
== 0xc7)
4649 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4651 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4655 case 0x8a: /* mov */
4657 if ((opcode
& 1) == 0)
4660 ir
.ot
= ir
.dflag
+ OT_WORD
;
4661 if (i386_record_modrm (&ir
))
4664 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4666 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4669 case 0x8c: /* mov seg */
4670 if (i386_record_modrm (&ir
))
4675 opcode
= opcode
<< 8 | ir
.modrm
;
4680 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4684 if (i386_record_lea_modrm (&ir
))
4689 case 0x8e: /* mov seg */
4690 if (i386_record_modrm (&ir
))
4695 regnum
= X86_RECORD_ES_REGNUM
;
4698 regnum
= X86_RECORD_SS_REGNUM
;
4701 regnum
= X86_RECORD_DS_REGNUM
;
4704 regnum
= X86_RECORD_FS_REGNUM
;
4707 regnum
= X86_RECORD_GS_REGNUM
;
4711 opcode
= opcode
<< 8 | ir
.modrm
;
4715 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4716 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4719 case 0x0fb6: /* movzbS */
4720 case 0x0fb7: /* movzwS */
4721 case 0x0fbe: /* movsbS */
4722 case 0x0fbf: /* movswS */
4723 if (i386_record_modrm (&ir
))
4725 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4728 case 0x8d: /* lea */
4729 if (i386_record_modrm (&ir
))
4734 opcode
= opcode
<< 8 | ir
.modrm
;
4739 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4741 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4744 case 0xa0: /* mov EAX */
4747 case 0xd7: /* xlat */
4748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4751 case 0xa2: /* mov EAX */
4753 if (ir
.override
>= 0)
4755 if (record_memory_query
)
4759 target_terminal_ours ();
4761 Process record ignores the memory change of instruction at address %s\n\
4762 because it can't get the value of the segment register.\n\
4763 Do you want to stop the program?"),
4764 paddress (gdbarch
, ir
.orig_addr
));
4765 target_terminal_inferior ();
4772 if ((opcode
& 1) == 0)
4775 ir
.ot
= ir
.dflag
+ OT_WORD
;
4778 if (target_read_memory (ir
.addr
, buf
, 8))
4781 printf_unfiltered (_("Process record: error reading "
4782 "memory at addr 0x%s len = 8.\n"),
4783 paddress (gdbarch
, ir
.addr
));
4787 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4791 if (target_read_memory (ir
.addr
, buf
, 4))
4794 printf_unfiltered (_("Process record: error reading "
4795 "memory at addr 0x%s len = 4.\n"),
4796 paddress (gdbarch
, ir
.addr
));
4800 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4804 if (target_read_memory (ir
.addr
, buf
, 2))
4807 printf_unfiltered (_("Process record: error reading "
4808 "memory at addr 0x%s len = 2.\n"),
4809 paddress (gdbarch
, ir
.addr
));
4813 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4815 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4820 case 0xb0: /* mov R, Ib */
4828 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4829 ? ((opcode
& 0x7) | ir
.rex_b
)
4830 : ((opcode
& 0x7) & 0x3));
4833 case 0xb8: /* mov R, Iv */
4841 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4844 case 0x91: /* xchg R, EAX */
4851 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4852 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4855 case 0x86: /* xchg Ev, Gv */
4857 if ((opcode
& 1) == 0)
4860 ir
.ot
= ir
.dflag
+ OT_WORD
;
4861 if (i386_record_modrm (&ir
))
4866 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4868 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4872 if (i386_record_lea_modrm (&ir
))
4876 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4878 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4881 case 0xc4: /* les Gv */
4882 case 0xc5: /* lds Gv */
4883 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4889 case 0x0fb2: /* lss Gv */
4890 case 0x0fb4: /* lfs Gv */
4891 case 0x0fb5: /* lgs Gv */
4892 if (i386_record_modrm (&ir
))
4900 opcode
= opcode
<< 8 | ir
.modrm
;
4905 case 0xc4: /* les Gv */
4906 regnum
= X86_RECORD_ES_REGNUM
;
4908 case 0xc5: /* lds Gv */
4909 regnum
= X86_RECORD_DS_REGNUM
;
4911 case 0x0fb2: /* lss Gv */
4912 regnum
= X86_RECORD_SS_REGNUM
;
4914 case 0x0fb4: /* lfs Gv */
4915 regnum
= X86_RECORD_FS_REGNUM
;
4917 case 0x0fb5: /* lgs Gv */
4918 regnum
= X86_RECORD_GS_REGNUM
;
4921 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4922 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4926 case 0xc0: /* shifts */
4932 if ((opcode
& 1) == 0)
4935 ir
.ot
= ir
.dflag
+ OT_WORD
;
4936 if (i386_record_modrm (&ir
))
4938 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4940 if (i386_record_lea_modrm (&ir
))
4946 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4948 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4957 if (i386_record_modrm (&ir
))
4961 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4966 if (i386_record_lea_modrm (&ir
))
4971 case 0xd8: /* Floats. */
4979 if (i386_record_modrm (&ir
))
4981 ir
.reg
|= ((opcode
& 7) << 3);
4987 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4995 /* For fcom, ficom nothing to do. */
5001 /* For fcomp, ficomp pop FPU stack, store all. */
5002 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5029 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5030 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5031 of code, always affects st(0) register. */
5032 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5056 /* Handling fld, fild. */
5057 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5061 switch (ir
.reg
>> 4)
5064 if (record_arch_list_add_mem (addr64
, 4))
5068 if (record_arch_list_add_mem (addr64
, 8))
5074 if (record_arch_list_add_mem (addr64
, 2))
5080 switch (ir
.reg
>> 4)
5083 if (record_arch_list_add_mem (addr64
, 4))
5085 if (3 == (ir
.reg
& 7))
5087 /* For fstp m32fp. */
5088 if (i386_record_floats (gdbarch
, &ir
,
5089 I386_SAVE_FPU_REGS
))
5094 if (record_arch_list_add_mem (addr64
, 4))
5096 if ((3 == (ir
.reg
& 7))
5097 || (5 == (ir
.reg
& 7))
5098 || (7 == (ir
.reg
& 7)))
5100 /* For fstp insn. */
5101 if (i386_record_floats (gdbarch
, &ir
,
5102 I386_SAVE_FPU_REGS
))
5107 if (record_arch_list_add_mem (addr64
, 8))
5109 if (3 == (ir
.reg
& 7))
5111 /* For fstp m64fp. */
5112 if (i386_record_floats (gdbarch
, &ir
,
5113 I386_SAVE_FPU_REGS
))
5118 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5120 /* For fistp, fbld, fild, fbstp. */
5121 if (i386_record_floats (gdbarch
, &ir
,
5122 I386_SAVE_FPU_REGS
))
5127 if (record_arch_list_add_mem (addr64
, 2))
5136 if (i386_record_floats (gdbarch
, &ir
,
5137 I386_SAVE_FPU_ENV_REG_STACK
))
5142 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5147 if (i386_record_floats (gdbarch
, &ir
,
5148 I386_SAVE_FPU_ENV_REG_STACK
))
5154 if (record_arch_list_add_mem (addr64
, 28))
5159 if (record_arch_list_add_mem (addr64
, 14))
5165 if (record_arch_list_add_mem (addr64
, 2))
5167 /* Insn fstp, fbstp. */
5168 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5173 if (record_arch_list_add_mem (addr64
, 10))
5179 if (record_arch_list_add_mem (addr64
, 28))
5185 if (record_arch_list_add_mem (addr64
, 14))
5189 if (record_arch_list_add_mem (addr64
, 80))
5192 if (i386_record_floats (gdbarch
, &ir
,
5193 I386_SAVE_FPU_ENV_REG_STACK
))
5197 if (record_arch_list_add_mem (addr64
, 8))
5200 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5205 opcode
= opcode
<< 8 | ir
.modrm
;
5210 /* Opcode is an extension of modR/M byte. */
5216 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5220 if (0x0c == (ir
.modrm
>> 4))
5222 if ((ir
.modrm
& 0x0f) <= 7)
5224 if (i386_record_floats (gdbarch
, &ir
,
5225 I386_SAVE_FPU_REGS
))
5230 if (i386_record_floats (gdbarch
, &ir
,
5231 I387_ST0_REGNUM (tdep
)))
5233 /* If only st(0) is changing, then we have already
5235 if ((ir
.modrm
& 0x0f) - 0x08)
5237 if (i386_record_floats (gdbarch
, &ir
,
5238 I387_ST0_REGNUM (tdep
) +
5239 ((ir
.modrm
& 0x0f) - 0x08)))
5257 if (i386_record_floats (gdbarch
, &ir
,
5258 I387_ST0_REGNUM (tdep
)))
5276 if (i386_record_floats (gdbarch
, &ir
,
5277 I386_SAVE_FPU_REGS
))
5281 if (i386_record_floats (gdbarch
, &ir
,
5282 I387_ST0_REGNUM (tdep
)))
5284 if (i386_record_floats (gdbarch
, &ir
,
5285 I387_ST0_REGNUM (tdep
) + 1))
5292 if (0xe9 == ir
.modrm
)
5294 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5297 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5299 if (i386_record_floats (gdbarch
, &ir
,
5300 I387_ST0_REGNUM (tdep
)))
5302 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5304 if (i386_record_floats (gdbarch
, &ir
,
5305 I387_ST0_REGNUM (tdep
) +
5309 else if ((ir
.modrm
& 0x0f) - 0x08)
5311 if (i386_record_floats (gdbarch
, &ir
,
5312 I387_ST0_REGNUM (tdep
) +
5313 ((ir
.modrm
& 0x0f) - 0x08)))
5319 if (0xe3 == ir
.modrm
)
5321 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5324 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5326 if (i386_record_floats (gdbarch
, &ir
,
5327 I387_ST0_REGNUM (tdep
)))
5329 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5331 if (i386_record_floats (gdbarch
, &ir
,
5332 I387_ST0_REGNUM (tdep
) +
5336 else if ((ir
.modrm
& 0x0f) - 0x08)
5338 if (i386_record_floats (gdbarch
, &ir
,
5339 I387_ST0_REGNUM (tdep
) +
5340 ((ir
.modrm
& 0x0f) - 0x08)))
5346 if ((0x0c == ir
.modrm
>> 4)
5347 || (0x0d == ir
.modrm
>> 4)
5348 || (0x0f == ir
.modrm
>> 4))
5350 if ((ir
.modrm
& 0x0f) <= 7)
5352 if (i386_record_floats (gdbarch
, &ir
,
5353 I387_ST0_REGNUM (tdep
) +
5359 if (i386_record_floats (gdbarch
, &ir
,
5360 I387_ST0_REGNUM (tdep
) +
5361 ((ir
.modrm
& 0x0f) - 0x08)))
5367 if (0x0c == ir
.modrm
>> 4)
5369 if (i386_record_floats (gdbarch
, &ir
,
5370 I387_FTAG_REGNUM (tdep
)))
5373 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5375 if ((ir
.modrm
& 0x0f) <= 7)
5377 if (i386_record_floats (gdbarch
, &ir
,
5378 I387_ST0_REGNUM (tdep
) +
5384 if (i386_record_floats (gdbarch
, &ir
,
5385 I386_SAVE_FPU_REGS
))
5391 if ((0x0c == ir
.modrm
>> 4)
5392 || (0x0e == ir
.modrm
>> 4)
5393 || (0x0f == ir
.modrm
>> 4)
5394 || (0xd9 == ir
.modrm
))
5396 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5401 if (0xe0 == ir
.modrm
)
5403 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5406 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5408 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5416 case 0xa4: /* movsS */
5418 case 0xaa: /* stosS */
5420 case 0x6c: /* insS */
5422 regcache_raw_read_unsigned (ir
.regcache
,
5423 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5429 if ((opcode
& 1) == 0)
5432 ir
.ot
= ir
.dflag
+ OT_WORD
;
5433 regcache_raw_read_unsigned (ir
.regcache
,
5434 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5437 regcache_raw_read_unsigned (ir
.regcache
,
5438 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5440 regcache_raw_read_unsigned (ir
.regcache
,
5441 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5443 if (ir
.aflag
&& (es
!= ds
))
5445 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5446 if (record_memory_query
)
5450 target_terminal_ours ();
5452 Process record ignores the memory change of instruction at address %s\n\
5453 because it can't get the value of the segment register.\n\
5454 Do you want to stop the program?"),
5455 paddress (gdbarch
, ir
.orig_addr
));
5456 target_terminal_inferior ();
5463 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5467 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5468 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5469 if (opcode
== 0xa4 || opcode
== 0xa5)
5470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5476 case 0xa6: /* cmpsS */
5478 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5480 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5481 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5482 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5485 case 0xac: /* lodsS */
5487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5489 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5494 case 0xae: /* scasS */
5496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5497 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5498 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5499 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5502 case 0x6e: /* outsS */
5504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5505 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5506 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5510 case 0xe4: /* port I/O */
5514 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5525 case 0xc2: /* ret im */
5526 case 0xc3: /* ret */
5527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5528 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5531 case 0xca: /* lret im */
5532 case 0xcb: /* lret */
5533 case 0xcf: /* iret */
5534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5539 case 0xe8: /* call im */
5540 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5542 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5546 case 0x9a: /* lcall im */
5547 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5552 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5553 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5557 case 0xe9: /* jmp im */
5558 case 0xea: /* ljmp im */
5559 case 0xeb: /* jmp Jb */
5560 case 0x70: /* jcc Jb */
5576 case 0x0f80: /* jcc Jv */
5594 case 0x0f90: /* setcc Gv */
5610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5612 if (i386_record_modrm (&ir
))
5615 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5619 if (i386_record_lea_modrm (&ir
))
5624 case 0x0f40: /* cmov Gv, Ev */
5640 if (i386_record_modrm (&ir
))
5643 if (ir
.dflag
== OT_BYTE
)
5645 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5649 case 0x9c: /* pushf */
5650 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5651 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5653 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5657 case 0x9d: /* popf */
5658 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5662 case 0x9e: /* sahf */
5663 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5669 case 0xf5: /* cmc */
5670 case 0xf8: /* clc */
5671 case 0xf9: /* stc */
5672 case 0xfc: /* cld */
5673 case 0xfd: /* std */
5674 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5677 case 0x9f: /* lahf */
5678 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5687 /* bit operations */
5688 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5689 ir
.ot
= ir
.dflag
+ OT_WORD
;
5690 if (i386_record_modrm (&ir
))
5695 opcode
= opcode
<< 8 | ir
.modrm
;
5701 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5704 if (i386_record_lea_modrm (&ir
))
5708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5711 case 0x0fa3: /* bt Gv, Ev */
5712 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5715 case 0x0fab: /* bts */
5716 case 0x0fb3: /* btr */
5717 case 0x0fbb: /* btc */
5718 ir
.ot
= ir
.dflag
+ OT_WORD
;
5719 if (i386_record_modrm (&ir
))
5722 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5726 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5728 regcache_raw_read_unsigned (ir
.regcache
,
5729 ir
.regmap
[ir
.reg
| rex_r
],
5734 addr64
+= ((int16_t) addr
>> 4) << 4;
5737 addr64
+= ((int32_t) addr
>> 5) << 5;
5740 addr64
+= ((int64_t) addr
>> 6) << 6;
5743 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5745 if (i386_record_lea_modrm (&ir
))
5748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5751 case 0x0fbc: /* bsf */
5752 case 0x0fbd: /* bsr */
5753 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5754 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5758 case 0x27: /* daa */
5759 case 0x2f: /* das */
5760 case 0x37: /* aaa */
5761 case 0x3f: /* aas */
5762 case 0xd4: /* aam */
5763 case 0xd5: /* aad */
5764 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5769 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5770 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5774 case 0x90: /* nop */
5775 if (prefixes
& PREFIX_LOCK
)
5782 case 0x9b: /* fwait */
5783 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5786 printf_unfiltered (_("Process record: error reading memory at "
5787 "addr 0x%s len = 1.\n"),
5788 paddress (gdbarch
, ir
.addr
));
5791 opcode
= (uint32_t) opcode8
;
5797 case 0xcc: /* int3 */
5798 printf_unfiltered (_("Process record does not support instruction "
5805 case 0xcd: /* int */
5809 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5812 printf_unfiltered (_("Process record: error reading memory "
5813 "at addr %s len = 1.\n"),
5814 paddress (gdbarch
, ir
.addr
));
5818 if (interrupt
!= 0x80
5819 || tdep
->i386_intx80_record
== NULL
)
5821 printf_unfiltered (_("Process record does not support "
5822 "instruction int 0x%02x.\n"),
5827 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5834 case 0xce: /* into */
5835 printf_unfiltered (_("Process record does not support "
5836 "instruction into.\n"));
5841 case 0xfa: /* cli */
5842 case 0xfb: /* sti */
5845 case 0x62: /* bound */
5846 printf_unfiltered (_("Process record does not support "
5847 "instruction bound.\n"));
5852 case 0x0fc8: /* bswap reg */
5860 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5863 case 0xd6: /* salc */
5864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5869 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5873 case 0xe0: /* loopnz */
5874 case 0xe1: /* loopz */
5875 case 0xe2: /* loop */
5876 case 0xe3: /* jecxz */
5877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5881 case 0x0f30: /* wrmsr */
5882 printf_unfiltered (_("Process record does not support "
5883 "instruction wrmsr.\n"));
5888 case 0x0f32: /* rdmsr */
5889 printf_unfiltered (_("Process record does not support "
5890 "instruction rdmsr.\n"));
5895 case 0x0f31: /* rdtsc */
5896 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5900 case 0x0f34: /* sysenter */
5903 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5908 if (tdep
->i386_sysenter_record
== NULL
)
5910 printf_unfiltered (_("Process record does not support "
5911 "instruction sysenter.\n"));
5915 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5921 case 0x0f35: /* sysexit */
5922 printf_unfiltered (_("Process record does not support "
5923 "instruction sysexit.\n"));
5928 case 0x0f05: /* syscall */
5931 if (tdep
->i386_syscall_record
== NULL
)
5933 printf_unfiltered (_("Process record does not support "
5934 "instruction syscall.\n"));
5938 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5944 case 0x0f07: /* sysret */
5945 printf_unfiltered (_("Process record does not support "
5946 "instruction sysret.\n"));
5951 case 0x0fa2: /* cpuid */
5952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5958 case 0xf4: /* hlt */
5959 printf_unfiltered (_("Process record does not support "
5960 "instruction hlt.\n"));
5966 if (i386_record_modrm (&ir
))
5973 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5977 if (i386_record_lea_modrm (&ir
))
5986 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 opcode
= opcode
<< 8 | ir
.modrm
;
5997 if (i386_record_modrm (&ir
))
6008 opcode
= opcode
<< 8 | ir
.modrm
;
6011 if (ir
.override
>= 0)
6013 if (record_memory_query
)
6017 target_terminal_ours ();
6019 Process record ignores the memory change of instruction at address %s\n\
6020 because it can't get the value of the segment register.\n\
6021 Do you want to stop the program?"),
6022 paddress (gdbarch
, ir
.orig_addr
));
6023 target_terminal_inferior ();
6030 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6032 if (record_arch_list_add_mem (addr64
, 2))
6035 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6037 if (record_arch_list_add_mem (addr64
, 8))
6042 if (record_arch_list_add_mem (addr64
, 4))
6053 case 0: /* monitor */
6056 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6060 opcode
= opcode
<< 8 | ir
.modrm
;
6068 if (ir
.override
>= 0)
6070 if (record_memory_query
)
6074 target_terminal_ours ();
6076 Process record ignores the memory change of instruction at address %s\n\
6077 because it can't get the value of the segment register.\n\
6078 Do you want to stop the program?"),
6079 paddress (gdbarch
, ir
.orig_addr
));
6080 target_terminal_inferior ();
6089 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6091 if (record_arch_list_add_mem (addr64
, 2))
6094 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6096 if (record_arch_list_add_mem (addr64
, 8))
6101 if (record_arch_list_add_mem (addr64
, 4))
6113 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6118 else if (ir
.rm
== 1)
6125 opcode
= opcode
<< 8 | ir
.modrm
;
6132 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6138 if (i386_record_lea_modrm (&ir
))
6141 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6144 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6146 case 7: /* invlpg */
6149 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6150 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6154 opcode
= opcode
<< 8 | ir
.modrm
;
6159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6163 opcode
= opcode
<< 8 | ir
.modrm
;
6169 case 0x0f08: /* invd */
6170 case 0x0f09: /* wbinvd */
6173 case 0x63: /* arpl */
6174 if (i386_record_modrm (&ir
))
6176 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6178 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6179 ? (ir
.reg
| rex_r
) : ir
.rm
);
6183 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6184 if (i386_record_lea_modrm (&ir
))
6187 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6188 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6191 case 0x0f02: /* lar */
6192 case 0x0f03: /* lsl */
6193 if (i386_record_modrm (&ir
))
6195 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6196 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6200 if (i386_record_modrm (&ir
))
6202 if (ir
.mod
== 3 && ir
.reg
== 3)
6205 opcode
= opcode
<< 8 | ir
.modrm
;
6217 /* nop (multi byte) */
6220 case 0x0f20: /* mov reg, crN */
6221 case 0x0f22: /* mov crN, reg */
6222 if (i386_record_modrm (&ir
))
6224 if ((ir
.modrm
& 0xc0) != 0xc0)
6227 opcode
= opcode
<< 8 | ir
.modrm
;
6238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6240 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6244 opcode
= opcode
<< 8 | ir
.modrm
;
6250 case 0x0f21: /* mov reg, drN */
6251 case 0x0f23: /* mov drN, reg */
6252 if (i386_record_modrm (&ir
))
6254 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6255 || ir
.reg
== 5 || ir
.reg
>= 8)
6258 opcode
= opcode
<< 8 | ir
.modrm
;
6262 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6264 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6267 case 0x0f06: /* clts */
6268 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6271 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6273 case 0x0f0d: /* 3DNow! prefetch */
6276 case 0x0f0e: /* 3DNow! femms */
6277 case 0x0f77: /* emms */
6278 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6280 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6283 case 0x0f0f: /* 3DNow! data */
6284 if (i386_record_modrm (&ir
))
6286 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6288 printf_unfiltered (_("Process record: error reading memory at "
6289 "addr %s len = 1.\n"),
6290 paddress (gdbarch
, ir
.addr
));
6296 case 0x0c: /* 3DNow! pi2fw */
6297 case 0x0d: /* 3DNow! pi2fd */
6298 case 0x1c: /* 3DNow! pf2iw */
6299 case 0x1d: /* 3DNow! pf2id */
6300 case 0x8a: /* 3DNow! pfnacc */
6301 case 0x8e: /* 3DNow! pfpnacc */
6302 case 0x90: /* 3DNow! pfcmpge */
6303 case 0x94: /* 3DNow! pfmin */
6304 case 0x96: /* 3DNow! pfrcp */
6305 case 0x97: /* 3DNow! pfrsqrt */
6306 case 0x9a: /* 3DNow! pfsub */
6307 case 0x9e: /* 3DNow! pfadd */
6308 case 0xa0: /* 3DNow! pfcmpgt */
6309 case 0xa4: /* 3DNow! pfmax */
6310 case 0xa6: /* 3DNow! pfrcpit1 */
6311 case 0xa7: /* 3DNow! pfrsqit1 */
6312 case 0xaa: /* 3DNow! pfsubr */
6313 case 0xae: /* 3DNow! pfacc */
6314 case 0xb0: /* 3DNow! pfcmpeq */
6315 case 0xb4: /* 3DNow! pfmul */
6316 case 0xb6: /* 3DNow! pfrcpit2 */
6317 case 0xb7: /* 3DNow! pmulhrw */
6318 case 0xbb: /* 3DNow! pswapd */
6319 case 0xbf: /* 3DNow! pavgusb */
6320 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6321 goto no_support_3dnow_data
;
6322 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6326 no_support_3dnow_data
:
6327 opcode
= (opcode
<< 8) | opcode8
;
6333 case 0x0faa: /* rsm */
6334 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6336 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6339 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6346 if (i386_record_modrm (&ir
))
6350 case 0: /* fxsave */
6354 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6355 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6357 if (record_arch_list_add_mem (tmpu64
, 512))
6362 case 1: /* fxrstor */
6366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6368 for (i
= I387_MM0_REGNUM (tdep
);
6369 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6370 record_arch_list_add_reg (ir
.regcache
, i
);
6372 for (i
= I387_XMM0_REGNUM (tdep
);
6373 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6374 record_arch_list_add_reg (ir
.regcache
, i
);
6376 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6377 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6379 for (i
= I387_ST0_REGNUM (tdep
);
6380 i386_fp_regnum_p (gdbarch
, i
); i
++)
6381 record_arch_list_add_reg (ir
.regcache
, i
);
6383 for (i
= I387_FCTRL_REGNUM (tdep
);
6384 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6385 record_arch_list_add_reg (ir
.regcache
, i
);
6389 case 2: /* ldmxcsr */
6390 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6392 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6395 case 3: /* stmxcsr */
6397 if (i386_record_lea_modrm (&ir
))
6401 case 5: /* lfence */
6402 case 6: /* mfence */
6403 case 7: /* sfence clflush */
6407 opcode
= (opcode
<< 8) | ir
.modrm
;
6413 case 0x0fc3: /* movnti */
6414 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6415 if (i386_record_modrm (&ir
))
6420 if (i386_record_lea_modrm (&ir
))
6424 /* Add prefix to opcode. */
6551 reswitch_prefix_add
:
6559 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6561 printf_unfiltered (_("Process record: error reading memory at "
6562 "addr %s len = 1.\n"),
6563 paddress (gdbarch
, ir
.addr
));
6567 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6568 goto reswitch_prefix_add
;
6571 case 0x0f10: /* movups */
6572 case 0x660f10: /* movupd */
6573 case 0xf30f10: /* movss */
6574 case 0xf20f10: /* movsd */
6575 case 0x0f12: /* movlps */
6576 case 0x660f12: /* movlpd */
6577 case 0xf30f12: /* movsldup */
6578 case 0xf20f12: /* movddup */
6579 case 0x0f14: /* unpcklps */
6580 case 0x660f14: /* unpcklpd */
6581 case 0x0f15: /* unpckhps */
6582 case 0x660f15: /* unpckhpd */
6583 case 0x0f16: /* movhps */
6584 case 0x660f16: /* movhpd */
6585 case 0xf30f16: /* movshdup */
6586 case 0x0f28: /* movaps */
6587 case 0x660f28: /* movapd */
6588 case 0x0f2a: /* cvtpi2ps */
6589 case 0x660f2a: /* cvtpi2pd */
6590 case 0xf30f2a: /* cvtsi2ss */
6591 case 0xf20f2a: /* cvtsi2sd */
6592 case 0x0f2c: /* cvttps2pi */
6593 case 0x660f2c: /* cvttpd2pi */
6594 case 0x0f2d: /* cvtps2pi */
6595 case 0x660f2d: /* cvtpd2pi */
6596 case 0x660f3800: /* pshufb */
6597 case 0x660f3801: /* phaddw */
6598 case 0x660f3802: /* phaddd */
6599 case 0x660f3803: /* phaddsw */
6600 case 0x660f3804: /* pmaddubsw */
6601 case 0x660f3805: /* phsubw */
6602 case 0x660f3806: /* phsubd */
6603 case 0x660f3807: /* phsubsw */
6604 case 0x660f3808: /* psignb */
6605 case 0x660f3809: /* psignw */
6606 case 0x660f380a: /* psignd */
6607 case 0x660f380b: /* pmulhrsw */
6608 case 0x660f3810: /* pblendvb */
6609 case 0x660f3814: /* blendvps */
6610 case 0x660f3815: /* blendvpd */
6611 case 0x660f381c: /* pabsb */
6612 case 0x660f381d: /* pabsw */
6613 case 0x660f381e: /* pabsd */
6614 case 0x660f3820: /* pmovsxbw */
6615 case 0x660f3821: /* pmovsxbd */
6616 case 0x660f3822: /* pmovsxbq */
6617 case 0x660f3823: /* pmovsxwd */
6618 case 0x660f3824: /* pmovsxwq */
6619 case 0x660f3825: /* pmovsxdq */
6620 case 0x660f3828: /* pmuldq */
6621 case 0x660f3829: /* pcmpeqq */
6622 case 0x660f382a: /* movntdqa */
6623 case 0x660f3a08: /* roundps */
6624 case 0x660f3a09: /* roundpd */
6625 case 0x660f3a0a: /* roundss */
6626 case 0x660f3a0b: /* roundsd */
6627 case 0x660f3a0c: /* blendps */
6628 case 0x660f3a0d: /* blendpd */
6629 case 0x660f3a0e: /* pblendw */
6630 case 0x660f3a0f: /* palignr */
6631 case 0x660f3a20: /* pinsrb */
6632 case 0x660f3a21: /* insertps */
6633 case 0x660f3a22: /* pinsrd pinsrq */
6634 case 0x660f3a40: /* dpps */
6635 case 0x660f3a41: /* dppd */
6636 case 0x660f3a42: /* mpsadbw */
6637 case 0x660f3a60: /* pcmpestrm */
6638 case 0x660f3a61: /* pcmpestri */
6639 case 0x660f3a62: /* pcmpistrm */
6640 case 0x660f3a63: /* pcmpistri */
6641 case 0x0f51: /* sqrtps */
6642 case 0x660f51: /* sqrtpd */
6643 case 0xf20f51: /* sqrtsd */
6644 case 0xf30f51: /* sqrtss */
6645 case 0x0f52: /* rsqrtps */
6646 case 0xf30f52: /* rsqrtss */
6647 case 0x0f53: /* rcpps */
6648 case 0xf30f53: /* rcpss */
6649 case 0x0f54: /* andps */
6650 case 0x660f54: /* andpd */
6651 case 0x0f55: /* andnps */
6652 case 0x660f55: /* andnpd */
6653 case 0x0f56: /* orps */
6654 case 0x660f56: /* orpd */
6655 case 0x0f57: /* xorps */
6656 case 0x660f57: /* xorpd */
6657 case 0x0f58: /* addps */
6658 case 0x660f58: /* addpd */
6659 case 0xf20f58: /* addsd */
6660 case 0xf30f58: /* addss */
6661 case 0x0f59: /* mulps */
6662 case 0x660f59: /* mulpd */
6663 case 0xf20f59: /* mulsd */
6664 case 0xf30f59: /* mulss */
6665 case 0x0f5a: /* cvtps2pd */
6666 case 0x660f5a: /* cvtpd2ps */
6667 case 0xf20f5a: /* cvtsd2ss */
6668 case 0xf30f5a: /* cvtss2sd */
6669 case 0x0f5b: /* cvtdq2ps */
6670 case 0x660f5b: /* cvtps2dq */
6671 case 0xf30f5b: /* cvttps2dq */
6672 case 0x0f5c: /* subps */
6673 case 0x660f5c: /* subpd */
6674 case 0xf20f5c: /* subsd */
6675 case 0xf30f5c: /* subss */
6676 case 0x0f5d: /* minps */
6677 case 0x660f5d: /* minpd */
6678 case 0xf20f5d: /* minsd */
6679 case 0xf30f5d: /* minss */
6680 case 0x0f5e: /* divps */
6681 case 0x660f5e: /* divpd */
6682 case 0xf20f5e: /* divsd */
6683 case 0xf30f5e: /* divss */
6684 case 0x0f5f: /* maxps */
6685 case 0x660f5f: /* maxpd */
6686 case 0xf20f5f: /* maxsd */
6687 case 0xf30f5f: /* maxss */
6688 case 0x660f60: /* punpcklbw */
6689 case 0x660f61: /* punpcklwd */
6690 case 0x660f62: /* punpckldq */
6691 case 0x660f63: /* packsswb */
6692 case 0x660f64: /* pcmpgtb */
6693 case 0x660f65: /* pcmpgtw */
6694 case 0x660f66: /* pcmpgtd */
6695 case 0x660f67: /* packuswb */
6696 case 0x660f68: /* punpckhbw */
6697 case 0x660f69: /* punpckhwd */
6698 case 0x660f6a: /* punpckhdq */
6699 case 0x660f6b: /* packssdw */
6700 case 0x660f6c: /* punpcklqdq */
6701 case 0x660f6d: /* punpckhqdq */
6702 case 0x660f6e: /* movd */
6703 case 0x660f6f: /* movdqa */
6704 case 0xf30f6f: /* movdqu */
6705 case 0x660f70: /* pshufd */
6706 case 0xf20f70: /* pshuflw */
6707 case 0xf30f70: /* pshufhw */
6708 case 0x660f74: /* pcmpeqb */
6709 case 0x660f75: /* pcmpeqw */
6710 case 0x660f76: /* pcmpeqd */
6711 case 0x660f7c: /* haddpd */
6712 case 0xf20f7c: /* haddps */
6713 case 0x660f7d: /* hsubpd */
6714 case 0xf20f7d: /* hsubps */
6715 case 0xf30f7e: /* movq */
6716 case 0x0fc2: /* cmpps */
6717 case 0x660fc2: /* cmppd */
6718 case 0xf20fc2: /* cmpsd */
6719 case 0xf30fc2: /* cmpss */
6720 case 0x660fc4: /* pinsrw */
6721 case 0x0fc6: /* shufps */
6722 case 0x660fc6: /* shufpd */
6723 case 0x660fd0: /* addsubpd */
6724 case 0xf20fd0: /* addsubps */
6725 case 0x660fd1: /* psrlw */
6726 case 0x660fd2: /* psrld */
6727 case 0x660fd3: /* psrlq */
6728 case 0x660fd4: /* paddq */
6729 case 0x660fd5: /* pmullw */
6730 case 0xf30fd6: /* movq2dq */
6731 case 0x660fd8: /* psubusb */
6732 case 0x660fd9: /* psubusw */
6733 case 0x660fda: /* pminub */
6734 case 0x660fdb: /* pand */
6735 case 0x660fdc: /* paddusb */
6736 case 0x660fdd: /* paddusw */
6737 case 0x660fde: /* pmaxub */
6738 case 0x660fdf: /* pandn */
6739 case 0x660fe0: /* pavgb */
6740 case 0x660fe1: /* psraw */
6741 case 0x660fe2: /* psrad */
6742 case 0x660fe3: /* pavgw */
6743 case 0x660fe4: /* pmulhuw */
6744 case 0x660fe5: /* pmulhw */
6745 case 0x660fe6: /* cvttpd2dq */
6746 case 0xf20fe6: /* cvtpd2dq */
6747 case 0xf30fe6: /* cvtdq2pd */
6748 case 0x660fe8: /* psubsb */
6749 case 0x660fe9: /* psubsw */
6750 case 0x660fea: /* pminsw */
6751 case 0x660feb: /* por */
6752 case 0x660fec: /* paddsb */
6753 case 0x660fed: /* paddsw */
6754 case 0x660fee: /* pmaxsw */
6755 case 0x660fef: /* pxor */
6756 case 0xf20ff0: /* lddqu */
6757 case 0x660ff1: /* psllw */
6758 case 0x660ff2: /* pslld */
6759 case 0x660ff3: /* psllq */
6760 case 0x660ff4: /* pmuludq */
6761 case 0x660ff5: /* pmaddwd */
6762 case 0x660ff6: /* psadbw */
6763 case 0x660ff8: /* psubb */
6764 case 0x660ff9: /* psubw */
6765 case 0x660ffa: /* psubd */
6766 case 0x660ffb: /* psubq */
6767 case 0x660ffc: /* paddb */
6768 case 0x660ffd: /* paddw */
6769 case 0x660ffe: /* paddd */
6770 if (i386_record_modrm (&ir
))
6773 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6775 record_arch_list_add_reg (ir
.regcache
,
6776 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6777 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6778 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6781 case 0x0f11: /* movups */
6782 case 0x660f11: /* movupd */
6783 case 0xf30f11: /* movss */
6784 case 0xf20f11: /* movsd */
6785 case 0x0f13: /* movlps */
6786 case 0x660f13: /* movlpd */
6787 case 0x0f17: /* movhps */
6788 case 0x660f17: /* movhpd */
6789 case 0x0f29: /* movaps */
6790 case 0x660f29: /* movapd */
6791 case 0x660f3a14: /* pextrb */
6792 case 0x660f3a15: /* pextrw */
6793 case 0x660f3a16: /* pextrd pextrq */
6794 case 0x660f3a17: /* extractps */
6795 case 0x660f7f: /* movdqa */
6796 case 0xf30f7f: /* movdqu */
6797 if (i386_record_modrm (&ir
))
6801 if (opcode
== 0x0f13 || opcode
== 0x660f13
6802 || opcode
== 0x0f17 || opcode
== 0x660f17)
6805 if (!i386_xmm_regnum_p (gdbarch
,
6806 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6808 record_arch_list_add_reg (ir
.regcache
,
6809 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6831 if (i386_record_lea_modrm (&ir
))
6836 case 0x0f2b: /* movntps */
6837 case 0x660f2b: /* movntpd */
6838 case 0x0fe7: /* movntq */
6839 case 0x660fe7: /* movntdq */
6842 if (opcode
== 0x0fe7)
6846 if (i386_record_lea_modrm (&ir
))
6850 case 0xf30f2c: /* cvttss2si */
6851 case 0xf20f2c: /* cvttsd2si */
6852 case 0xf30f2d: /* cvtss2si */
6853 case 0xf20f2d: /* cvtsd2si */
6854 case 0xf20f38f0: /* crc32 */
6855 case 0xf20f38f1: /* crc32 */
6856 case 0x0f50: /* movmskps */
6857 case 0x660f50: /* movmskpd */
6858 case 0x0fc5: /* pextrw */
6859 case 0x660fc5: /* pextrw */
6860 case 0x0fd7: /* pmovmskb */
6861 case 0x660fd7: /* pmovmskb */
6862 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6865 case 0x0f3800: /* pshufb */
6866 case 0x0f3801: /* phaddw */
6867 case 0x0f3802: /* phaddd */
6868 case 0x0f3803: /* phaddsw */
6869 case 0x0f3804: /* pmaddubsw */
6870 case 0x0f3805: /* phsubw */
6871 case 0x0f3806: /* phsubd */
6872 case 0x0f3807: /* phsubsw */
6873 case 0x0f3808: /* psignb */
6874 case 0x0f3809: /* psignw */
6875 case 0x0f380a: /* psignd */
6876 case 0x0f380b: /* pmulhrsw */
6877 case 0x0f381c: /* pabsb */
6878 case 0x0f381d: /* pabsw */
6879 case 0x0f381e: /* pabsd */
6880 case 0x0f382b: /* packusdw */
6881 case 0x0f3830: /* pmovzxbw */
6882 case 0x0f3831: /* pmovzxbd */
6883 case 0x0f3832: /* pmovzxbq */
6884 case 0x0f3833: /* pmovzxwd */
6885 case 0x0f3834: /* pmovzxwq */
6886 case 0x0f3835: /* pmovzxdq */
6887 case 0x0f3837: /* pcmpgtq */
6888 case 0x0f3838: /* pminsb */
6889 case 0x0f3839: /* pminsd */
6890 case 0x0f383a: /* pminuw */
6891 case 0x0f383b: /* pminud */
6892 case 0x0f383c: /* pmaxsb */
6893 case 0x0f383d: /* pmaxsd */
6894 case 0x0f383e: /* pmaxuw */
6895 case 0x0f383f: /* pmaxud */
6896 case 0x0f3840: /* pmulld */
6897 case 0x0f3841: /* phminposuw */
6898 case 0x0f3a0f: /* palignr */
6899 case 0x0f60: /* punpcklbw */
6900 case 0x0f61: /* punpcklwd */
6901 case 0x0f62: /* punpckldq */
6902 case 0x0f63: /* packsswb */
6903 case 0x0f64: /* pcmpgtb */
6904 case 0x0f65: /* pcmpgtw */
6905 case 0x0f66: /* pcmpgtd */
6906 case 0x0f67: /* packuswb */
6907 case 0x0f68: /* punpckhbw */
6908 case 0x0f69: /* punpckhwd */
6909 case 0x0f6a: /* punpckhdq */
6910 case 0x0f6b: /* packssdw */
6911 case 0x0f6e: /* movd */
6912 case 0x0f6f: /* movq */
6913 case 0x0f70: /* pshufw */
6914 case 0x0f74: /* pcmpeqb */
6915 case 0x0f75: /* pcmpeqw */
6916 case 0x0f76: /* pcmpeqd */
6917 case 0x0fc4: /* pinsrw */
6918 case 0x0fd1: /* psrlw */
6919 case 0x0fd2: /* psrld */
6920 case 0x0fd3: /* psrlq */
6921 case 0x0fd4: /* paddq */
6922 case 0x0fd5: /* pmullw */
6923 case 0xf20fd6: /* movdq2q */
6924 case 0x0fd8: /* psubusb */
6925 case 0x0fd9: /* psubusw */
6926 case 0x0fda: /* pminub */
6927 case 0x0fdb: /* pand */
6928 case 0x0fdc: /* paddusb */
6929 case 0x0fdd: /* paddusw */
6930 case 0x0fde: /* pmaxub */
6931 case 0x0fdf: /* pandn */
6932 case 0x0fe0: /* pavgb */
6933 case 0x0fe1: /* psraw */
6934 case 0x0fe2: /* psrad */
6935 case 0x0fe3: /* pavgw */
6936 case 0x0fe4: /* pmulhuw */
6937 case 0x0fe5: /* pmulhw */
6938 case 0x0fe8: /* psubsb */
6939 case 0x0fe9: /* psubsw */
6940 case 0x0fea: /* pminsw */
6941 case 0x0feb: /* por */
6942 case 0x0fec: /* paddsb */
6943 case 0x0fed: /* paddsw */
6944 case 0x0fee: /* pmaxsw */
6945 case 0x0fef: /* pxor */
6946 case 0x0ff1: /* psllw */
6947 case 0x0ff2: /* pslld */
6948 case 0x0ff3: /* psllq */
6949 case 0x0ff4: /* pmuludq */
6950 case 0x0ff5: /* pmaddwd */
6951 case 0x0ff6: /* psadbw */
6952 case 0x0ff8: /* psubb */
6953 case 0x0ff9: /* psubw */
6954 case 0x0ffa: /* psubd */
6955 case 0x0ffb: /* psubq */
6956 case 0x0ffc: /* paddb */
6957 case 0x0ffd: /* paddw */
6958 case 0x0ffe: /* paddd */
6959 if (i386_record_modrm (&ir
))
6961 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6963 record_arch_list_add_reg (ir
.regcache
,
6964 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6967 case 0x0f71: /* psllw */
6968 case 0x0f72: /* pslld */
6969 case 0x0f73: /* psllq */
6970 if (i386_record_modrm (&ir
))
6972 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6974 record_arch_list_add_reg (ir
.regcache
,
6975 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6978 case 0x660f71: /* psllw */
6979 case 0x660f72: /* pslld */
6980 case 0x660f73: /* psllq */
6981 if (i386_record_modrm (&ir
))
6984 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6986 record_arch_list_add_reg (ir
.regcache
,
6987 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6990 case 0x0f7e: /* movd */
6991 case 0x660f7e: /* movd */
6992 if (i386_record_modrm (&ir
))
6995 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7002 if (i386_record_lea_modrm (&ir
))
7007 case 0x0f7f: /* movq */
7008 if (i386_record_modrm (&ir
))
7012 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7014 record_arch_list_add_reg (ir
.regcache
,
7015 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7020 if (i386_record_lea_modrm (&ir
))
7025 case 0xf30fb8: /* popcnt */
7026 if (i386_record_modrm (&ir
))
7028 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7032 case 0x660fd6: /* movq */
7033 if (i386_record_modrm (&ir
))
7038 if (!i386_xmm_regnum_p (gdbarch
,
7039 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7041 record_arch_list_add_reg (ir
.regcache
,
7042 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7047 if (i386_record_lea_modrm (&ir
))
7052 case 0x660f3817: /* ptest */
7053 case 0x0f2e: /* ucomiss */
7054 case 0x660f2e: /* ucomisd */
7055 case 0x0f2f: /* comiss */
7056 case 0x660f2f: /* comisd */
7057 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7060 case 0x0ff7: /* maskmovq */
7061 regcache_raw_read_unsigned (ir
.regcache
,
7062 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7064 if (record_arch_list_add_mem (addr
, 64))
7068 case 0x660ff7: /* maskmovdqu */
7069 regcache_raw_read_unsigned (ir
.regcache
,
7070 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7072 if (record_arch_list_add_mem (addr
, 128))
7087 /* In the future, maybe still need to deal with need_dasm. */
7088 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7089 if (record_arch_list_add_end ())
7095 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7096 "at address %s.\n"),
7097 (unsigned int) (opcode
),
7098 paddress (gdbarch
, ir
.orig_addr
));
7102 static const int i386_record_regmap
[] =
7104 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7105 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7106 0, 0, 0, 0, 0, 0, 0, 0,
7107 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7108 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7111 /* Check that the given address appears suitable for a fast
7112 tracepoint, which on x86-64 means that we need an instruction of at
7113 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7114 jump and not have to worry about program jumps to an address in the
7115 middle of the tracepoint jump. On x86, it may be possible to use
7116 4-byte jumps with a 2-byte offset to a trampoline located in the
7117 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7118 of instruction to replace, and 0 if not, plus an explanatory
7122 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7123 CORE_ADDR addr
, int *isize
, char **msg
)
7126 static struct ui_file
*gdb_null
= NULL
;
7128 /* Ask the target for the minimum instruction length supported. */
7129 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7133 /* If the target does not support the get_min_fast_tracepoint_insn_len
7134 operation, assume that fast tracepoints will always be implemented
7135 using 4-byte relative jumps on both x86 and x86-64. */
7138 else if (jumplen
== 0)
7140 /* If the target does support get_min_fast_tracepoint_insn_len but
7141 returns zero, then the IPA has not loaded yet. In this case,
7142 we optimistically assume that truncated 2-byte relative jumps
7143 will be available on x86, and compensate later if this assumption
7144 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7145 jumps will always be used. */
7146 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7149 /* Dummy file descriptor for the disassembler. */
7151 gdb_null
= ui_file_new ();
7153 /* Check for fit. */
7154 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7160 /* Return a bit of target-specific detail to add to the caller's
7161 generic failure message. */
7163 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7164 "need at least %d bytes for the jump"),
7177 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7178 struct tdesc_arch_data
*tdesc_data
)
7180 const struct target_desc
*tdesc
= tdep
->tdesc
;
7181 const struct tdesc_feature
*feature_core
;
7182 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7183 int i
, num_regs
, valid_p
;
7185 if (! tdesc_has_registers (tdesc
))
7188 /* Get core registers. */
7189 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7190 if (feature_core
== NULL
)
7193 /* Get SSE registers. */
7194 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7196 /* Try AVX registers. */
7197 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7201 /* The XCR0 bits. */
7204 /* AVX register description requires SSE register description. */
7208 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7210 /* It may have been set by OSABI initialization function. */
7211 if (tdep
->num_ymm_regs
== 0)
7213 tdep
->ymmh_register_names
= i386_ymmh_names
;
7214 tdep
->num_ymm_regs
= 8;
7215 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7218 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7219 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7220 tdep
->ymm0h_regnum
+ i
,
7221 tdep
->ymmh_register_names
[i
]);
7223 else if (feature_sse
)
7224 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7227 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7228 tdep
->num_xmm_regs
= 0;
7231 num_regs
= tdep
->num_core_regs
;
7232 for (i
= 0; i
< num_regs
; i
++)
7233 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7234 tdep
->register_names
[i
]);
7238 /* Need to include %mxcsr, so add one. */
7239 num_regs
+= tdep
->num_xmm_regs
+ 1;
7240 for (; i
< num_regs
; i
++)
7241 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7242 tdep
->register_names
[i
]);
7249 static struct gdbarch
*
7250 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7252 struct gdbarch_tdep
*tdep
;
7253 struct gdbarch
*gdbarch
;
7254 struct tdesc_arch_data
*tdesc_data
;
7255 const struct target_desc
*tdesc
;
7259 /* If there is already a candidate, use it. */
7260 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7262 return arches
->gdbarch
;
7264 /* Allocate space for the new architecture. */
7265 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7266 gdbarch
= gdbarch_alloc (&info
, tdep
);
7268 /* General-purpose registers. */
7269 tdep
->gregset
= NULL
;
7270 tdep
->gregset_reg_offset
= NULL
;
7271 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7272 tdep
->sizeof_gregset
= 0;
7274 /* Floating-point registers. */
7275 tdep
->fpregset
= NULL
;
7276 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7278 tdep
->xstateregset
= NULL
;
7280 /* The default settings include the FPU registers, the MMX registers
7281 and the SSE registers. This can be overridden for a specific ABI
7282 by adjusting the members `st0_regnum', `mm0_regnum' and
7283 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7284 will show up in the output of "info all-registers". */
7286 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7288 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7289 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7291 tdep
->jb_pc_offset
= -1;
7292 tdep
->struct_return
= pcc_struct_return
;
7293 tdep
->sigtramp_start
= 0;
7294 tdep
->sigtramp_end
= 0;
7295 tdep
->sigtramp_p
= i386_sigtramp_p
;
7296 tdep
->sigcontext_addr
= NULL
;
7297 tdep
->sc_reg_offset
= NULL
;
7298 tdep
->sc_pc_offset
= -1;
7299 tdep
->sc_sp_offset
= -1;
7301 tdep
->xsave_xcr0_offset
= -1;
7303 tdep
->record_regmap
= i386_record_regmap
;
7305 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7307 /* The format used for `long double' on almost all i386 targets is
7308 the i387 extended floating-point format. In fact, of all targets
7309 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7310 on having a `long double' that's not `long' at all. */
7311 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7313 /* Although the i387 extended floating-point has only 80 significant
7314 bits, a `long double' actually takes up 96, probably to enforce
7316 set_gdbarch_long_double_bit (gdbarch
, 96);
7318 /* Register numbers of various important registers. */
7319 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7320 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7321 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7322 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7324 /* NOTE: kettenis/20040418: GCC does have two possible register
7325 numbering schemes on the i386: dbx and SVR4. These schemes
7326 differ in how they number %ebp, %esp, %eflags, and the
7327 floating-point registers, and are implemented by the arrays
7328 dbx_register_map[] and svr4_dbx_register_map in
7329 gcc/config/i386.c. GCC also defines a third numbering scheme in
7330 gcc/config/i386.c, which it designates as the "default" register
7331 map used in 64bit mode. This last register numbering scheme is
7332 implemented in dbx64_register_map, and is used for AMD64; see
7335 Currently, each GCC i386 target always uses the same register
7336 numbering scheme across all its supported debugging formats
7337 i.e. SDB (COFF), stabs and DWARF 2. This is because
7338 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7339 DBX_REGISTER_NUMBER macro which is defined by each target's
7340 respective config header in a manner independent of the requested
7341 output debugging format.
7343 This does not match the arrangement below, which presumes that
7344 the SDB and stabs numbering schemes differ from the DWARF and
7345 DWARF 2 ones. The reason for this arrangement is that it is
7346 likely to get the numbering scheme for the target's
7347 default/native debug format right. For targets where GCC is the
7348 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7349 targets where the native toolchain uses a different numbering
7350 scheme for a particular debug format (stabs-in-ELF on Solaris)
7351 the defaults below will have to be overridden, like
7352 i386_elf_init_abi() does. */
7354 /* Use the dbx register numbering scheme for stabs and COFF. */
7355 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7356 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7358 /* Use the SVR4 register numbering scheme for DWARF 2. */
7359 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7361 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7362 be in use on any of the supported i386 targets. */
7364 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7366 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7368 /* Call dummy code. */
7369 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7370 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7372 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7373 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7374 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7376 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7378 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7380 /* Stack grows downward. */
7381 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7383 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7384 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7385 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7387 set_gdbarch_frame_args_skip (gdbarch
, 8);
7389 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7391 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7393 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7395 /* Add the i386 register groups. */
7396 i386_add_reggroups (gdbarch
);
7397 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7399 /* Helper for function argument information. */
7400 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7402 /* Hook the function epilogue frame unwinder. This unwinder is
7403 appended to the list first, so that it supercedes the DWARF
7404 unwinder in function epilogues (where the DWARF unwinder
7405 currently fails). */
7406 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7408 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7409 to the list before the prologue-based unwinders, so that DWARF
7410 CFI info will be used if it is available. */
7411 dwarf2_append_unwinders (gdbarch
);
7413 frame_base_set_default (gdbarch
, &i386_frame_base
);
7415 /* Pseudo registers may be changed by amd64_init_abi. */
7416 set_gdbarch_pseudo_register_read_value (gdbarch
,
7417 i386_pseudo_register_read_value
);
7418 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7420 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7421 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7423 /* Override the normal target description method to make the AVX
7424 upper halves anonymous. */
7425 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7427 /* Even though the default ABI only includes general-purpose registers,
7428 floating-point registers and the SSE registers, we have to leave a
7429 gap for the upper AVX registers. */
7430 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7432 /* Get the x86 target description from INFO. */
7433 tdesc
= info
.target_desc
;
7434 if (! tdesc_has_registers (tdesc
))
7436 tdep
->tdesc
= tdesc
;
7438 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7439 tdep
->register_names
= i386_register_names
;
7441 /* No upper YMM registers. */
7442 tdep
->ymmh_register_names
= NULL
;
7443 tdep
->ymm0h_regnum
= -1;
7445 tdep
->num_byte_regs
= 8;
7446 tdep
->num_word_regs
= 8;
7447 tdep
->num_dword_regs
= 0;
7448 tdep
->num_mmx_regs
= 8;
7449 tdep
->num_ymm_regs
= 0;
7451 tdesc_data
= tdesc_data_alloc ();
7453 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7455 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7457 /* Hook in ABI-specific overrides, if they have been registered. */
7458 info
.tdep_info
= (void *) tdesc_data
;
7459 gdbarch_init_osabi (info
, gdbarch
);
7461 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7463 tdesc_data_cleanup (tdesc_data
);
7465 gdbarch_free (gdbarch
);
7469 /* Wire in pseudo registers. Number of pseudo registers may be
7471 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7472 + tdep
->num_word_regs
7473 + tdep
->num_dword_regs
7474 + tdep
->num_mmx_regs
7475 + tdep
->num_ymm_regs
));
7477 /* Target description may be changed. */
7478 tdesc
= tdep
->tdesc
;
7480 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7482 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7483 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7485 /* Make %al the first pseudo-register. */
7486 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7487 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7489 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7490 if (tdep
->num_dword_regs
)
7492 /* Support dword pseudo-register if it hasn't been disabled. */
7493 tdep
->eax_regnum
= ymm0_regnum
;
7494 ymm0_regnum
+= tdep
->num_dword_regs
;
7497 tdep
->eax_regnum
= -1;
7499 mm0_regnum
= ymm0_regnum
;
7500 if (tdep
->num_ymm_regs
)
7502 /* Support YMM pseudo-register if it is available. */
7503 tdep
->ymm0_regnum
= ymm0_regnum
;
7504 mm0_regnum
+= tdep
->num_ymm_regs
;
7507 tdep
->ymm0_regnum
= -1;
7509 if (tdep
->num_mmx_regs
!= 0)
7511 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7512 tdep
->mm0_regnum
= mm0_regnum
;
7515 tdep
->mm0_regnum
= -1;
7517 /* Hook in the legacy prologue-based unwinders last (fallback). */
7518 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7519 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7520 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7522 /* If we have a register mapping, enable the generic core file
7523 support, unless it has already been enabled. */
7524 if (tdep
->gregset_reg_offset
7525 && !gdbarch_regset_from_core_section_p (gdbarch
))
7526 set_gdbarch_regset_from_core_section (gdbarch
,
7527 i386_regset_from_core_section
);
7529 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7530 i386_skip_permanent_breakpoint
);
7532 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7533 i386_fast_tracepoint_valid_at
);
7538 static enum gdb_osabi
7539 i386_coff_osabi_sniffer (bfd
*abfd
)
7541 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7542 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7543 return GDB_OSABI_GO32
;
7545 return GDB_OSABI_UNKNOWN
;
7549 /* Provide a prototype to silence -Wmissing-prototypes. */
7550 void _initialize_i386_tdep (void);
7553 _initialize_i386_tdep (void)
7555 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7557 /* Add the variable that controls the disassembly flavor. */
7558 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7559 &disassembly_flavor
, _("\
7560 Set the disassembly flavor."), _("\
7561 Show the disassembly flavor."), _("\
7562 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7564 NULL
, /* FIXME: i18n: */
7565 &setlist
, &showlist
);
7567 /* Add the variable that controls the convention for returning
7569 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7570 &struct_convention
, _("\
7571 Set the convention for returning small structs."), _("\
7572 Show the convention for returning small structs."), _("\
7573 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7576 NULL
, /* FIXME: i18n: */
7577 &setlist
, &showlist
);
7579 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7580 i386_coff_osabi_sniffer
);
7582 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7583 i386_svr4_init_abi
);
7584 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7585 i386_go32_init_abi
);
7587 /* Initialize the i386-specific register groups. */
7588 i386_init_reggroups ();
7590 /* Initialize the standard target descriptions. */
7591 initialize_tdesc_i386 ();
7592 initialize_tdesc_i386_mmx ();
7593 initialize_tdesc_i386_avx ();
7595 /* Tell remote stub that we support XML target description. */
7596 register_remote_support_xml ("i386");