1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
66 static const char *i386_register_names
[] =
68 "eax", "ecx", "edx", "ebx",
69 "esp", "ebp", "esi", "edi",
70 "eip", "eflags", "cs", "ss",
71 "ds", "es", "fs", "gs",
72 "st0", "st1", "st2", "st3",
73 "st4", "st5", "st6", "st7",
74 "fctrl", "fstat", "ftag", "fiseg",
75 "fioff", "foseg", "fooff", "fop",
76 "xmm0", "xmm1", "xmm2", "xmm3",
77 "xmm4", "xmm5", "xmm6", "xmm7",
81 static const char *i386_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
87 static const char *i386_ymmh_names
[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
93 /* Register names for MMX pseudo-registers. */
95 static const char *i386_mmx_names
[] =
97 "mm0", "mm1", "mm2", "mm3",
98 "mm4", "mm5", "mm6", "mm7"
101 /* Register names for byte pseudo-registers. */
103 static const char *i386_byte_names
[] =
105 "al", "cl", "dl", "bl",
106 "ah", "ch", "dh", "bh"
109 /* Register names for word pseudo-registers. */
111 static const char *i386_word_names
[] =
113 "ax", "cx", "dx", "bx",
120 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
123 int mm0_regnum
= tdep
->mm0_regnum
;
128 regnum
-= mm0_regnum
;
129 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
135 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
137 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
139 regnum
-= tdep
->al_regnum
;
140 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
146 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
150 regnum
-= tdep
->ax_regnum
;
151 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
154 /* Dword register? */
157 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 int eax_regnum
= tdep
->eax_regnum
;
165 regnum
-= eax_regnum
;
166 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
170 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
173 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
175 if (ymm0h_regnum
< 0)
178 regnum
-= ymm0h_regnum
;
179 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
185 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
188 int ymm0_regnum
= tdep
->ymm0_regnum
;
193 regnum
-= ymm0_regnum
;
194 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
200 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
203 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
205 if (num_xmm_regs
== 0)
208 regnum
-= I387_XMM0_REGNUM (tdep
);
209 return regnum
>= 0 && regnum
< num_xmm_regs
;
213 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
217 if (I387_NUM_XMM_REGS (tdep
) == 0)
220 return (regnum
== I387_MXCSR_REGNUM (tdep
));
226 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
230 if (I387_ST0_REGNUM (tdep
) < 0)
233 return (I387_ST0_REGNUM (tdep
) <= regnum
234 && regnum
< I387_FCTRL_REGNUM (tdep
));
238 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
240 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
242 if (I387_ST0_REGNUM (tdep
) < 0)
245 return (I387_FCTRL_REGNUM (tdep
) <= regnum
246 && regnum
< I387_XMM0_REGNUM (tdep
));
249 /* Return the name of register REGNUM, or the empty string if it is
250 an anonymous register. */
253 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
255 /* Hide the upper YMM registers. */
256 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
259 return tdesc_register_name (gdbarch
, regnum
);
262 /* Return the name of register REGNUM. */
265 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
268 if (i386_mmx_regnum_p (gdbarch
, regnum
))
269 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
270 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
271 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
272 else if (i386_byte_regnum_p (gdbarch
, regnum
))
273 return i386_byte_names
[regnum
- tdep
->al_regnum
];
274 else if (i386_word_regnum_p (gdbarch
, regnum
))
275 return i386_word_names
[regnum
- tdep
->ax_regnum
];
277 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
280 /* Convert a dbx register number REG to the appropriate register
281 number used by GDB. */
284 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
288 /* This implements what GCC calls the "default" register map
289 (dbx_register_map[]). */
291 if (reg
>= 0 && reg
<= 7)
293 /* General-purpose registers. The debug info calls %ebp
294 register 4, and %esp register 5. */
301 else if (reg
>= 12 && reg
<= 19)
303 /* Floating-point registers. */
304 return reg
- 12 + I387_ST0_REGNUM (tdep
);
306 else if (reg
>= 21 && reg
<= 28)
309 int ymm0_regnum
= tdep
->ymm0_regnum
;
312 && i386_xmm_regnum_p (gdbarch
, reg
))
313 return reg
- 21 + ymm0_regnum
;
315 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
317 else if (reg
>= 29 && reg
<= 36)
320 return reg
- 29 + I387_MM0_REGNUM (tdep
);
323 /* This will hopefully provoke a warning. */
324 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
327 /* Convert SVR4 register number REG to the appropriate register number
331 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 /* This implements the GCC register map that tries to be compatible
336 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
338 /* The SVR4 register numbering includes %eip and %eflags, and
339 numbers the floating point registers differently. */
340 if (reg
>= 0 && reg
<= 9)
342 /* General-purpose registers. */
345 else if (reg
>= 11 && reg
<= 18)
347 /* Floating-point registers. */
348 return reg
- 11 + I387_ST0_REGNUM (tdep
);
350 else if (reg
>= 21 && reg
<= 36)
352 /* The SSE and MMX registers have the same numbers as with dbx. */
353 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
358 case 37: return I387_FCTRL_REGNUM (tdep
);
359 case 38: return I387_FSTAT_REGNUM (tdep
);
360 case 39: return I387_MXCSR_REGNUM (tdep
);
361 case 40: return I386_ES_REGNUM
;
362 case 41: return I386_CS_REGNUM
;
363 case 42: return I386_SS_REGNUM
;
364 case 43: return I386_DS_REGNUM
;
365 case 44: return I386_FS_REGNUM
;
366 case 45: return I386_GS_REGNUM
;
369 /* This will hopefully provoke a warning. */
370 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
375 /* This is the variable that is set with "set disassembly-flavor", and
376 its legitimate values. */
377 static const char att_flavor
[] = "att";
378 static const char intel_flavor
[] = "intel";
379 static const char *valid_flavors
[] =
385 static const char *disassembly_flavor
= att_flavor
;
388 /* Use the program counter to determine the contents and size of a
389 breakpoint instruction. Return a pointer to a string of bytes that
390 encode a breakpoint instruction, store the length of the string in
391 *LEN and optionally adjust *PC to point to the correct memory
392 location for inserting the breakpoint.
394 On the i386 we have a single breakpoint that fits in a single byte
395 and can be inserted anywhere.
397 This function is 64-bit safe. */
399 static const gdb_byte
*
400 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
402 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
404 *len
= sizeof (break_insn
);
408 /* Displaced instruction handling. */
410 /* Skip the legacy instruction prefixes in INSN.
411 Not all prefixes are valid for any particular insn
412 but we needn't care, the insn will fault if it's invalid.
413 The result is a pointer to the first opcode byte,
414 or NULL if we run off the end of the buffer. */
417 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
419 gdb_byte
*end
= insn
+ max_len
;
425 case DATA_PREFIX_OPCODE
:
426 case ADDR_PREFIX_OPCODE
:
427 case CS_PREFIX_OPCODE
:
428 case DS_PREFIX_OPCODE
:
429 case ES_PREFIX_OPCODE
:
430 case FS_PREFIX_OPCODE
:
431 case GS_PREFIX_OPCODE
:
432 case SS_PREFIX_OPCODE
:
433 case LOCK_PREFIX_OPCODE
:
434 case REPE_PREFIX_OPCODE
:
435 case REPNE_PREFIX_OPCODE
:
447 i386_absolute_jmp_p (const gdb_byte
*insn
)
449 /* jmp far (absolute address in operand). */
455 /* jump near, absolute indirect (/4). */
456 if ((insn
[1] & 0x38) == 0x20)
459 /* jump far, absolute indirect (/5). */
460 if ((insn
[1] & 0x38) == 0x28)
468 i386_absolute_call_p (const gdb_byte
*insn
)
470 /* call far, absolute. */
476 /* Call near, absolute indirect (/2). */
477 if ((insn
[1] & 0x38) == 0x10)
480 /* Call far, absolute indirect (/3). */
481 if ((insn
[1] & 0x38) == 0x18)
489 i386_ret_p (const gdb_byte
*insn
)
493 case 0xc2: /* ret near, pop N bytes. */
494 case 0xc3: /* ret near */
495 case 0xca: /* ret far, pop N bytes. */
496 case 0xcb: /* ret far */
497 case 0xcf: /* iret */
506 i386_call_p (const gdb_byte
*insn
)
508 if (i386_absolute_call_p (insn
))
511 /* call near, relative. */
518 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
519 length in bytes. Otherwise, return zero. */
522 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
533 /* Some kernels may run one past a syscall insn, so we have to cope.
534 Otherwise this is just simple_displaced_step_copy_insn. */
536 struct displaced_step_closure
*
537 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
538 CORE_ADDR from
, CORE_ADDR to
,
539 struct regcache
*regs
)
541 size_t len
= gdbarch_max_insn_length (gdbarch
);
542 gdb_byte
*buf
= xmalloc (len
);
544 read_memory (from
, buf
, len
);
546 /* GDB may get control back after the insn after the syscall.
547 Presumably this is a kernel bug.
548 If this is a syscall, make sure there's a nop afterwards. */
553 insn
= i386_skip_prefixes (buf
, len
);
554 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
555 insn
[syscall_length
] = NOP_OPCODE
;
558 write_memory (to
, buf
, len
);
562 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
563 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
564 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
567 return (struct displaced_step_closure
*) buf
;
570 /* Fix up the state of registers and memory after having single-stepped
571 a displaced instruction. */
574 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
575 struct displaced_step_closure
*closure
,
576 CORE_ADDR from
, CORE_ADDR to
,
577 struct regcache
*regs
)
579 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
581 /* The offset we applied to the instruction's address.
582 This could well be negative (when viewed as a signed 32-bit
583 value), but ULONGEST won't reflect that, so take care when
585 ULONGEST insn_offset
= to
- from
;
587 /* Since we use simple_displaced_step_copy_insn, our closure is a
588 copy of the instruction. */
589 gdb_byte
*insn
= (gdb_byte
*) closure
;
590 /* The start of the insn, needed in case we see some prefixes. */
591 gdb_byte
*insn_start
= insn
;
594 fprintf_unfiltered (gdb_stdlog
,
595 "displaced: fixup (%s, %s), "
596 "insn = 0x%02x 0x%02x ...\n",
597 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
600 /* The list of issues to contend with here is taken from
601 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
602 Yay for Free Software! */
604 /* Relocate the %eip, if necessary. */
606 /* The instruction recognizers we use assume any leading prefixes
607 have been skipped. */
609 /* This is the size of the buffer in closure. */
610 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
611 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
612 /* If there are too many prefixes, just ignore the insn.
613 It will fault when run. */
618 /* Except in the case of absolute or indirect jump or call
619 instructions, or a return instruction, the new eip is relative to
620 the displaced instruction; make it relative. Well, signal
621 handler returns don't need relocation either, but we use the
622 value of %eip to recognize those; see below. */
623 if (! i386_absolute_jmp_p (insn
)
624 && ! i386_absolute_call_p (insn
)
625 && ! i386_ret_p (insn
))
630 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
632 /* A signal trampoline system call changes the %eip, resuming
633 execution of the main program after the signal handler has
634 returned. That makes them like 'return' instructions; we
635 shouldn't relocate %eip.
637 But most system calls don't, and we do need to relocate %eip.
639 Our heuristic for distinguishing these cases: if stepping
640 over the system call instruction left control directly after
641 the instruction, the we relocate --- control almost certainly
642 doesn't belong in the displaced copy. Otherwise, we assume
643 the instruction has put control where it belongs, and leave
644 it unrelocated. Goodness help us if there are PC-relative
646 if (i386_syscall_p (insn
, &insn_len
)
647 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
648 /* GDB can get control back after the insn after the syscall.
649 Presumably this is a kernel bug.
650 i386_displaced_step_copy_insn ensures its a nop,
651 we add one to the length for it. */
652 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
655 fprintf_unfiltered (gdb_stdlog
,
656 "displaced: syscall changed %%eip; "
661 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
663 /* If we just stepped over a breakpoint insn, we don't backup
664 the pc on purpose; this is to match behaviour without
667 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
670 fprintf_unfiltered (gdb_stdlog
,
672 "relocated %%eip from %s to %s\n",
673 paddress (gdbarch
, orig_eip
),
674 paddress (gdbarch
, eip
));
678 /* If the instruction was PUSHFL, then the TF bit will be set in the
679 pushed value, and should be cleared. We'll leave this for later,
680 since GDB already messes up the TF flag when stepping over a
683 /* If the instruction was a call, the return address now atop the
684 stack is the address following the copied instruction. We need
685 to make it the address following the original instruction. */
686 if (i386_call_p (insn
))
690 const ULONGEST retaddr_len
= 4;
692 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
693 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
694 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
695 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
698 fprintf_unfiltered (gdb_stdlog
,
699 "displaced: relocated return addr at %s to %s\n",
700 paddress (gdbarch
, esp
),
701 paddress (gdbarch
, retaddr
));
706 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
708 target_write_memory (*to
, buf
, len
);
713 i386_relocate_instruction (struct gdbarch
*gdbarch
,
714 CORE_ADDR
*to
, CORE_ADDR oldloc
)
716 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
717 gdb_byte buf
[I386_MAX_INSN_LEN
];
718 int offset
= 0, rel32
, newrel
;
720 gdb_byte
*insn
= buf
;
722 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
724 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
725 I386_MAX_INSN_LEN
, oldloc
);
727 /* Get past the prefixes. */
728 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
730 /* Adjust calls with 32-bit relative addresses as push/jump, with
731 the address pushed being the location where the original call in
732 the user program would return to. */
735 gdb_byte push_buf
[16];
736 unsigned int ret_addr
;
738 /* Where "ret" in the original code will return to. */
739 ret_addr
= oldloc
+ insn_length
;
740 push_buf
[0] = 0x68; /* pushq $... */
741 memcpy (&push_buf
[1], &ret_addr
, 4);
743 append_insns (to
, 5, push_buf
);
745 /* Convert the relative call to a relative jump. */
748 /* Adjust the destination offset. */
749 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
750 newrel
= (oldloc
- *to
) + rel32
;
751 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
754 fprintf_unfiltered (gdb_stdlog
,
755 "Adjusted insn rel32=%s at %s to"
757 hex_string (rel32
), paddress (gdbarch
, oldloc
),
758 hex_string (newrel
), paddress (gdbarch
, *to
));
760 /* Write the adjusted jump into its displaced location. */
761 append_insns (to
, 5, insn
);
765 /* Adjust jumps with 32-bit relative addresses. Calls are already
769 /* Adjust conditional jumps. */
770 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
775 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
776 newrel
= (oldloc
- *to
) + rel32
;
777 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
779 fprintf_unfiltered (gdb_stdlog
,
780 "Adjusted insn rel32=%s at %s to"
782 hex_string (rel32
), paddress (gdbarch
, oldloc
),
783 hex_string (newrel
), paddress (gdbarch
, *to
));
786 /* Write the adjusted instructions into their displaced
788 append_insns (to
, insn_length
, buf
);
792 #ifdef I386_REGNO_TO_SYMMETRY
793 #error "The Sequent Symmetry is no longer supported."
796 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
797 and %esp "belong" to the calling function. Therefore these
798 registers should be saved if they're going to be modified. */
800 /* The maximum number of saved registers. This should include all
801 registers mentioned above, and %eip. */
802 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
804 struct i386_frame_cache
812 /* Saved registers. */
813 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
818 /* Stack space reserved for local variables. */
822 /* Allocate and initialize a frame cache. */
824 static struct i386_frame_cache
*
825 i386_alloc_frame_cache (void)
827 struct i386_frame_cache
*cache
;
830 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
835 cache
->sp_offset
= -4;
838 /* Saved registers. We initialize these to -1 since zero is a valid
839 offset (that's where %ebp is supposed to be stored). */
840 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
841 cache
->saved_regs
[i
] = -1;
843 cache
->saved_sp_reg
= -1;
844 cache
->pc_in_eax
= 0;
846 /* Frameless until proven otherwise. */
852 /* If the instruction at PC is a jump, return the address of its
853 target. Otherwise, return PC. */
856 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
858 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
863 if (target_read_memory (pc
, &op
, 1))
869 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
875 /* Relative jump: if data16 == 0, disp32, else disp16. */
878 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
880 /* Include the size of the jmp instruction (including the
886 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
888 /* Include the size of the jmp instruction. */
893 /* Relative jump, disp8 (ignore data16). */
894 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
903 /* Check whether PC points at a prologue for a function returning a
904 structure or union. If so, it updates CACHE and returns the
905 address of the first instruction after the code sequence that
906 removes the "hidden" argument from the stack or CURRENT_PC,
907 whichever is smaller. Otherwise, return PC. */
910 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
911 struct i386_frame_cache
*cache
)
913 /* Functions that return a structure or union start with:
916 xchgl %eax, (%esp) 0x87 0x04 0x24
917 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
919 (the System V compiler puts out the second `xchg' instruction,
920 and the assembler doesn't try to optimize it, so the 'sib' form
921 gets generated). This sequence is used to get the address of the
922 return buffer for a function that returns a structure. */
923 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
924 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
928 if (current_pc
<= pc
)
931 if (target_read_memory (pc
, &op
, 1))
934 if (op
!= 0x58) /* popl %eax */
937 if (target_read_memory (pc
+ 1, buf
, 4))
940 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
943 if (current_pc
== pc
)
945 cache
->sp_offset
+= 4;
949 if (current_pc
== pc
+ 1)
951 cache
->pc_in_eax
= 1;
955 if (buf
[1] == proto1
[1])
962 i386_skip_probe (CORE_ADDR pc
)
964 /* A function may start with
978 if (target_read_memory (pc
, &op
, 1))
981 if (op
== 0x68 || op
== 0x6a)
985 /* Skip past the `pushl' instruction; it has either a one-byte or a
986 four-byte operand, depending on the opcode. */
992 /* Read the following 8 bytes, which should be `call _probe' (6
993 bytes) followed by `addl $4,%esp' (2 bytes). */
994 read_memory (pc
+ delta
, buf
, sizeof (buf
));
995 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
996 pc
+= delta
+ sizeof (buf
);
1002 /* GCC 4.1 and later, can put code in the prologue to realign the
1003 stack pointer. Check whether PC points to such code, and update
1004 CACHE accordingly. Return the first instruction after the code
1005 sequence or CURRENT_PC, whichever is smaller. If we don't
1006 recognize the code, return PC. */
1009 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1010 struct i386_frame_cache
*cache
)
1012 /* There are 2 code sequences to re-align stack before the frame
1015 1. Use a caller-saved saved register:
1021 2. Use a callee-saved saved register:
1028 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1030 0x83 0xe4 0xf0 andl $-16, %esp
1031 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1036 int offset
, offset_and
;
1037 static int regnums
[8] = {
1038 I386_EAX_REGNUM
, /* %eax */
1039 I386_ECX_REGNUM
, /* %ecx */
1040 I386_EDX_REGNUM
, /* %edx */
1041 I386_EBX_REGNUM
, /* %ebx */
1042 I386_ESP_REGNUM
, /* %esp */
1043 I386_EBP_REGNUM
, /* %ebp */
1044 I386_ESI_REGNUM
, /* %esi */
1045 I386_EDI_REGNUM
/* %edi */
1048 if (target_read_memory (pc
, buf
, sizeof buf
))
1051 /* Check caller-saved saved register. The first instruction has
1052 to be "leal 4(%esp), %reg". */
1053 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1055 /* MOD must be binary 10 and R/M must be binary 100. */
1056 if ((buf
[1] & 0xc7) != 0x44)
1059 /* REG has register number. */
1060 reg
= (buf
[1] >> 3) & 7;
1065 /* Check callee-saved saved register. The first instruction
1066 has to be "pushl %reg". */
1067 if ((buf
[0] & 0xf8) != 0x50)
1073 /* The next instruction has to be "leal 8(%esp), %reg". */
1074 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1077 /* MOD must be binary 10 and R/M must be binary 100. */
1078 if ((buf
[2] & 0xc7) != 0x44)
1081 /* REG has register number. Registers in pushl and leal have to
1083 if (reg
!= ((buf
[2] >> 3) & 7))
1089 /* Rigister can't be %esp nor %ebp. */
1090 if (reg
== 4 || reg
== 5)
1093 /* The next instruction has to be "andl $-XXX, %esp". */
1094 if (buf
[offset
+ 1] != 0xe4
1095 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1098 offset_and
= offset
;
1099 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1101 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1102 0xfc. REG must be binary 110 and MOD must be binary 01. */
1103 if (buf
[offset
] != 0xff
1104 || buf
[offset
+ 2] != 0xfc
1105 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1108 /* R/M has register. Registers in leal and pushl have to be the
1110 if (reg
!= (buf
[offset
+ 1] & 7))
1113 if (current_pc
> pc
+ offset_and
)
1114 cache
->saved_sp_reg
= regnums
[reg
];
1116 return min (pc
+ offset
+ 3, current_pc
);
1119 /* Maximum instruction length we need to handle. */
1120 #define I386_MAX_MATCHED_INSN_LEN 6
1122 /* Instruction description. */
1126 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1127 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1130 /* Return whether instruction at PC matches PATTERN. */
1133 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1137 if (target_read_memory (pc
, &op
, 1))
1140 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1142 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1143 int insn_matched
= 1;
1146 gdb_assert (pattern
.len
> 1);
1147 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1149 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1152 for (i
= 1; i
< pattern
.len
; i
++)
1154 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1157 return insn_matched
;
1162 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1163 the first instruction description that matches. Otherwise, return
1166 static struct i386_insn
*
1167 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1169 struct i386_insn
*pattern
;
1171 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1173 if (i386_match_pattern (pc
, *pattern
))
1180 /* Return whether PC points inside a sequence of instructions that
1181 matches INSN_PATTERNS. */
1184 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1186 CORE_ADDR current_pc
;
1189 struct i386_insn
*insn
;
1191 insn
= i386_match_insn (pc
, insn_patterns
);
1196 ix
= insn
- insn_patterns
;
1197 for (i
= ix
- 1; i
>= 0; i
--)
1199 current_pc
-= insn_patterns
[i
].len
;
1201 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1205 current_pc
= pc
+ insn
->len
;
1206 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1208 if (!i386_match_pattern (current_pc
, *insn
))
1211 current_pc
+= insn
->len
;
1217 /* Some special instructions that might be migrated by GCC into the
1218 part of the prologue that sets up the new stack frame. Because the
1219 stack frame hasn't been setup yet, no registers have been saved
1220 yet, and only the scratch registers %eax, %ecx and %edx can be
1223 struct i386_insn i386_frame_setup_skip_insns
[] =
1225 /* Check for `movb imm8, r' and `movl imm32, r'.
1227 ??? Should we handle 16-bit operand-sizes here? */
1229 /* `movb imm8, %al' and `movb imm8, %ah' */
1230 /* `movb imm8, %cl' and `movb imm8, %ch' */
1231 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1232 /* `movb imm8, %dl' and `movb imm8, %dh' */
1233 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1234 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1235 { 5, { 0xb8 }, { 0xfe } },
1236 /* `movl imm32, %edx' */
1237 { 5, { 0xba }, { 0xff } },
1239 /* Check for `mov imm32, r32'. Note that there is an alternative
1240 encoding for `mov m32, %eax'.
1242 ??? Should we handle SIB adressing here?
1243 ??? Should we handle 16-bit operand-sizes here? */
1245 /* `movl m32, %eax' */
1246 { 5, { 0xa1 }, { 0xff } },
1247 /* `movl m32, %eax' and `mov; m32, %ecx' */
1248 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1249 /* `movl m32, %edx' */
1250 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1252 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1253 Because of the symmetry, there are actually two ways to encode
1254 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1255 opcode bytes 0x31 and 0x33 for `xorl'. */
1257 /* `subl %eax, %eax' */
1258 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1259 /* `subl %ecx, %ecx' */
1260 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1261 /* `subl %edx, %edx' */
1262 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1263 /* `xorl %eax, %eax' */
1264 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1265 /* `xorl %ecx, %ecx' */
1266 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1267 /* `xorl %edx, %edx' */
1268 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1273 /* Check whether PC points to a no-op instruction. */
1275 i386_skip_noop (CORE_ADDR pc
)
1280 if (target_read_memory (pc
, &op
, 1))
1286 /* Ignore `nop' instruction. */
1290 if (target_read_memory (pc
, &op
, 1))
1294 /* Ignore no-op instruction `mov %edi, %edi'.
1295 Microsoft system dlls often start with
1296 a `mov %edi,%edi' instruction.
1297 The 5 bytes before the function start are
1298 filled with `nop' instructions.
1299 This pattern can be used for hot-patching:
1300 The `mov %edi, %edi' instruction can be replaced by a
1301 near jump to the location of the 5 `nop' instructions
1302 which can be replaced by a 32-bit jump to anywhere
1303 in the 32-bit address space. */
1305 else if (op
== 0x8b)
1307 if (target_read_memory (pc
+ 1, &op
, 1))
1313 if (target_read_memory (pc
, &op
, 1))
1323 /* Check whether PC points at a code that sets up a new stack frame.
1324 If so, it updates CACHE and returns the address of the first
1325 instruction after the sequence that sets up the frame or LIMIT,
1326 whichever is smaller. If we don't recognize the code, return PC. */
1329 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1330 CORE_ADDR pc
, CORE_ADDR limit
,
1331 struct i386_frame_cache
*cache
)
1333 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1334 struct i386_insn
*insn
;
1341 if (target_read_memory (pc
, &op
, 1))
1344 if (op
== 0x55) /* pushl %ebp */
1346 /* Take into account that we've executed the `pushl %ebp' that
1347 starts this instruction sequence. */
1348 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1349 cache
->sp_offset
+= 4;
1352 /* If that's all, return now. */
1356 /* Check for some special instructions that might be migrated by
1357 GCC into the prologue and skip them. At this point in the
1358 prologue, code should only touch the scratch registers %eax,
1359 %ecx and %edx, so while the number of posibilities is sheer,
1362 Make sure we only skip these instructions if we later see the
1363 `movl %esp, %ebp' that actually sets up the frame. */
1364 while (pc
+ skip
< limit
)
1366 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1373 /* If that's all, return now. */
1374 if (limit
<= pc
+ skip
)
1377 if (target_read_memory (pc
+ skip
, &op
, 1))
1380 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1384 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1389 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1397 /* OK, we actually have a frame. We just don't know how large
1398 it is yet. Set its size to zero. We'll adjust it if
1399 necessary. We also now commit to skipping the special
1400 instructions mentioned before. */
1404 /* If that's all, return now. */
1408 /* Check for stack adjustment
1412 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1413 reg, so we don't have to worry about a data16 prefix. */
1414 if (target_read_memory (pc
, &op
, 1))
1418 /* `subl' with 8-bit immediate. */
1419 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1420 /* Some instruction starting with 0x83 other than `subl'. */
1423 /* `subl' with signed 8-bit immediate (though it wouldn't
1424 make sense to be negative). */
1425 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1428 else if (op
== 0x81)
1430 /* Maybe it is `subl' with a 32-bit immediate. */
1431 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1432 /* Some instruction starting with 0x81 other than `subl'. */
1435 /* It is `subl' with a 32-bit immediate. */
1436 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1441 /* Some instruction other than `subl'. */
1445 else if (op
== 0xc8) /* enter */
1447 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1454 /* Check whether PC points at code that saves registers on the stack.
1455 If so, it updates CACHE and returns the address of the first
1456 instruction after the register saves or CURRENT_PC, whichever is
1457 smaller. Otherwise, return PC. */
1460 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1461 struct i386_frame_cache
*cache
)
1463 CORE_ADDR offset
= 0;
1467 if (cache
->locals
> 0)
1468 offset
-= cache
->locals
;
1469 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1471 if (target_read_memory (pc
, &op
, 1))
1473 if (op
< 0x50 || op
> 0x57)
1477 cache
->saved_regs
[op
- 0x50] = offset
;
1478 cache
->sp_offset
+= 4;
1485 /* Do a full analysis of the prologue at PC and update CACHE
1486 accordingly. Bail out early if CURRENT_PC is reached. Return the
1487 address where the analysis stopped.
1489 We handle these cases:
1491 The startup sequence can be at the start of the function, or the
1492 function can start with a branch to startup code at the end.
1494 %ebp can be set up with either the 'enter' instruction, or "pushl
1495 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1496 once used in the System V compiler).
1498 Local space is allocated just below the saved %ebp by either the
1499 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1500 16-bit unsigned argument for space to allocate, and the 'addl'
1501 instruction could have either a signed byte, or 32-bit immediate.
1503 Next, the registers used by this function are pushed. With the
1504 System V compiler they will always be in the order: %edi, %esi,
1505 %ebx (and sometimes a harmless bug causes it to also save but not
1506 restore %eax); however, the code below is willing to see the pushes
1507 in any order, and will handle up to 8 of them.
1509 If the setup sequence is at the end of the function, then the next
1510 instruction will be a branch back to the start. */
1513 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1514 CORE_ADDR pc
, CORE_ADDR current_pc
,
1515 struct i386_frame_cache
*cache
)
1517 pc
= i386_skip_noop (pc
);
1518 pc
= i386_follow_jump (gdbarch
, pc
);
1519 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1520 pc
= i386_skip_probe (pc
);
1521 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1522 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1523 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1526 /* Return PC of first real instruction. */
1529 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1531 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1533 static gdb_byte pic_pat
[6] =
1535 0xe8, 0, 0, 0, 0, /* call 0x0 */
1536 0x5b, /* popl %ebx */
1538 struct i386_frame_cache cache
;
1544 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1545 if (cache
.locals
< 0)
1548 /* Found valid frame setup. */
1550 /* The native cc on SVR4 in -K PIC mode inserts the following code
1551 to get the address of the global offset table (GOT) into register
1556 movl %ebx,x(%ebp) (optional)
1559 This code is with the rest of the prologue (at the end of the
1560 function), so we have to skip it to get to the first real
1561 instruction at the start of the function. */
1563 for (i
= 0; i
< 6; i
++)
1565 if (target_read_memory (pc
+ i
, &op
, 1))
1568 if (pic_pat
[i
] != op
)
1575 if (target_read_memory (pc
+ delta
, &op
, 1))
1578 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1580 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1582 if (op
== 0x5d) /* One byte offset from %ebp. */
1584 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1586 else /* Unexpected instruction. */
1589 if (target_read_memory (pc
+ delta
, &op
, 1))
1594 if (delta
> 0 && op
== 0x81
1595 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1602 /* If the function starts with a branch (to startup code at the end)
1603 the last instruction should bring us back to the first
1604 instruction of the real code. */
1605 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1606 pc
= i386_follow_jump (gdbarch
, pc
);
1611 /* Check that the code pointed to by PC corresponds to a call to
1612 __main, skip it if so. Return PC otherwise. */
1615 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1620 if (target_read_memory (pc
, &op
, 1))
1626 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1628 /* Make sure address is computed correctly as a 32bit
1629 integer even if CORE_ADDR is 64 bit wide. */
1630 struct minimal_symbol
*s
;
1631 CORE_ADDR call_dest
;
1633 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1634 call_dest
= call_dest
& 0xffffffffU
;
1635 s
= lookup_minimal_symbol_by_pc (call_dest
);
1637 && SYMBOL_LINKAGE_NAME (s
) != NULL
1638 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1646 /* This function is 64-bit safe. */
1649 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1653 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1654 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1658 /* Normal frames. */
1661 i386_frame_cache_1 (struct frame_info
*this_frame
,
1662 struct i386_frame_cache
*cache
)
1664 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1665 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1669 cache
->pc
= get_frame_func (this_frame
);
1671 /* In principle, for normal frames, %ebp holds the frame pointer,
1672 which holds the base address for the current stack frame.
1673 However, for functions that don't need it, the frame pointer is
1674 optional. For these "frameless" functions the frame pointer is
1675 actually the frame pointer of the calling frame. Signal
1676 trampolines are just a special case of a "frameless" function.
1677 They (usually) share their frame pointer with the frame that was
1678 in progress when the signal occurred. */
1680 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1681 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1682 if (cache
->base
== 0)
1685 /* For normal frames, %eip is stored at 4(%ebp). */
1686 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1689 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1692 if (cache
->locals
< 0)
1694 /* We didn't find a valid frame, which means that CACHE->base
1695 currently holds the frame pointer for our calling frame. If
1696 we're at the start of a function, or somewhere half-way its
1697 prologue, the function's frame probably hasn't been fully
1698 setup yet. Try to reconstruct the base address for the stack
1699 frame by looking at the stack pointer. For truly "frameless"
1700 functions this might work too. */
1702 if (cache
->saved_sp_reg
!= -1)
1704 /* Saved stack pointer has been saved. */
1705 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1706 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1708 /* We're halfway aligning the stack. */
1709 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1710 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1712 /* This will be added back below. */
1713 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1715 else if (cache
->pc
!= 0
1716 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1718 /* We're in a known function, but did not find a frame
1719 setup. Assume that the function does not use %ebp.
1720 Alternatively, we may have jumped to an invalid
1721 address; in that case there is definitely no new
1723 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1724 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1728 /* We're in an unknown function. We could not find the start
1729 of the function to analyze the prologue; our best option is
1730 to assume a typical frame layout with the caller's %ebp
1732 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1735 if (cache
->saved_sp_reg
!= -1)
1737 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1738 register may be unavailable). */
1739 if (cache
->saved_sp
== 0
1740 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1741 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1743 /* Now that we have the base address for the stack frame we can
1744 calculate the value of %esp in the calling frame. */
1745 else if (cache
->saved_sp
== 0)
1746 cache
->saved_sp
= cache
->base
+ 8;
1748 /* Adjust all the saved registers such that they contain addresses
1749 instead of offsets. */
1750 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1751 if (cache
->saved_regs
[i
] != -1)
1752 cache
->saved_regs
[i
] += cache
->base
;
1757 static struct i386_frame_cache
*
1758 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1760 volatile struct gdb_exception ex
;
1761 struct i386_frame_cache
*cache
;
1766 cache
= i386_alloc_frame_cache ();
1767 *this_cache
= cache
;
1769 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1771 i386_frame_cache_1 (this_frame
, cache
);
1773 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1774 throw_exception (ex
);
1780 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1781 struct frame_id
*this_id
)
1783 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1785 /* This marks the outermost frame. */
1786 if (cache
->base
== 0)
1789 /* See the end of i386_push_dummy_call. */
1790 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1793 static enum unwind_stop_reason
1794 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1797 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1800 return UNWIND_UNAVAILABLE
;
1802 /* This marks the outermost frame. */
1803 if (cache
->base
== 0)
1804 return UNWIND_OUTERMOST
;
1806 return UNWIND_NO_REASON
;
1809 static struct value
*
1810 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1813 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1815 gdb_assert (regnum
>= 0);
1817 /* The System V ABI says that:
1819 "The flags register contains the system flags, such as the
1820 direction flag and the carry flag. The direction flag must be
1821 set to the forward (that is, zero) direction before entry and
1822 upon exit from a function. Other user flags have no specified
1823 role in the standard calling sequence and are not preserved."
1825 To guarantee the "upon exit" part of that statement we fake a
1826 saved flags register that has its direction flag cleared.
1828 Note that GCC doesn't seem to rely on the fact that the direction
1829 flag is cleared after a function return; it always explicitly
1830 clears the flag before operations where it matters.
1832 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1833 right thing to do. The way we fake the flags register here makes
1834 it impossible to change it. */
1836 if (regnum
== I386_EFLAGS_REGNUM
)
1840 val
= get_frame_register_unsigned (this_frame
, regnum
);
1842 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1845 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1846 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1848 if (regnum
== I386_ESP_REGNUM
1849 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1851 /* If the SP has been saved, but we don't know where, then this
1852 means that SAVED_SP_REG register was found unavailable back
1853 when we built the cache. */
1854 if (cache
->saved_sp
== 0)
1855 return frame_unwind_got_register (this_frame
, regnum
,
1856 cache
->saved_sp_reg
);
1858 return frame_unwind_got_constant (this_frame
, regnum
,
1862 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1863 return frame_unwind_got_memory (this_frame
, regnum
,
1864 cache
->saved_regs
[regnum
]);
1866 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1869 static const struct frame_unwind i386_frame_unwind
=
1872 i386_frame_unwind_stop_reason
,
1874 i386_frame_prev_register
,
1876 default_frame_sniffer
1879 /* Normal frames, but in a function epilogue. */
1881 /* The epilogue is defined here as the 'ret' instruction, which will
1882 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1883 the function's stack frame. */
1886 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1889 struct symtab
*symtab
;
1891 symtab
= find_pc_symtab (pc
);
1892 if (symtab
&& symtab
->epilogue_unwind_valid
)
1895 if (target_read_memory (pc
, &insn
, 1))
1896 return 0; /* Can't read memory at pc. */
1898 if (insn
!= 0xc3) /* 'ret' instruction. */
1905 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1906 struct frame_info
*this_frame
,
1907 void **this_prologue_cache
)
1909 if (frame_relative_level (this_frame
) == 0)
1910 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1911 get_frame_pc (this_frame
));
1916 static struct i386_frame_cache
*
1917 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1919 volatile struct gdb_exception ex
;
1920 struct i386_frame_cache
*cache
;
1926 cache
= i386_alloc_frame_cache ();
1927 *this_cache
= cache
;
1929 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1931 cache
->pc
= get_frame_func (this_frame
);
1933 /* At this point the stack looks as if we just entered the
1934 function, with the return address at the top of the
1936 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1937 cache
->base
= sp
+ cache
->sp_offset
;
1938 cache
->saved_sp
= cache
->base
+ 8;
1939 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1943 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1944 throw_exception (ex
);
1949 static enum unwind_stop_reason
1950 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1953 struct i386_frame_cache
*cache
=
1954 i386_epilogue_frame_cache (this_frame
, this_cache
);
1957 return UNWIND_UNAVAILABLE
;
1959 return UNWIND_NO_REASON
;
1963 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1965 struct frame_id
*this_id
)
1967 struct i386_frame_cache
*cache
=
1968 i386_epilogue_frame_cache (this_frame
, this_cache
);
1973 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1976 static struct value
*
1977 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1978 void **this_cache
, int regnum
)
1980 /* Make sure we've initialized the cache. */
1981 i386_epilogue_frame_cache (this_frame
, this_cache
);
1983 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1986 static const struct frame_unwind i386_epilogue_frame_unwind
=
1989 i386_epilogue_frame_unwind_stop_reason
,
1990 i386_epilogue_frame_this_id
,
1991 i386_epilogue_frame_prev_register
,
1993 i386_epilogue_frame_sniffer
1997 /* Stack-based trampolines. */
1999 /* These trampolines are used on cross x86 targets, when taking the
2000 address of a nested function. When executing these trampolines,
2001 no stack frame is set up, so we are in a similar situation as in
2002 epilogues and i386_epilogue_frame_this_id can be re-used. */
2004 /* Static chain passed in register. */
2006 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2008 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2009 { 5, { 0xb8 }, { 0xfe } },
2012 { 5, { 0xe9 }, { 0xff } },
2017 /* Static chain passed on stack (when regparm=3). */
2019 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2022 { 5, { 0x68 }, { 0xff } },
2025 { 5, { 0xe9 }, { 0xff } },
2030 /* Return whether PC points inside a stack trampoline. */
2033 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2038 /* A stack trampoline is detected if no name is associated
2039 to the current pc and if it points inside a trampoline
2042 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2046 if (target_read_memory (pc
, &insn
, 1))
2049 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2050 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2057 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2058 struct frame_info
*this_frame
,
2061 if (frame_relative_level (this_frame
) == 0)
2062 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2063 get_frame_pc (this_frame
));
2068 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2071 i386_epilogue_frame_unwind_stop_reason
,
2072 i386_epilogue_frame_this_id
,
2073 i386_epilogue_frame_prev_register
,
2075 i386_stack_tramp_frame_sniffer
2078 /* Generate a bytecode expression to get the value of the saved PC. */
2081 i386_gen_return_address (struct gdbarch
*gdbarch
,
2082 struct agent_expr
*ax
, struct axs_value
*value
,
2085 /* The following sequence assumes the traditional use of the base
2087 ax_reg (ax
, I386_EBP_REGNUM
);
2089 ax_simple (ax
, aop_add
);
2090 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2091 value
->kind
= axs_lvalue_memory
;
2095 /* Signal trampolines. */
2097 static struct i386_frame_cache
*
2098 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2100 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2102 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2103 volatile struct gdb_exception ex
;
2104 struct i386_frame_cache
*cache
;
2111 cache
= i386_alloc_frame_cache ();
2113 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2115 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2116 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2118 addr
= tdep
->sigcontext_addr (this_frame
);
2119 if (tdep
->sc_reg_offset
)
2123 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2125 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2126 if (tdep
->sc_reg_offset
[i
] != -1)
2127 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2131 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2132 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2137 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2138 throw_exception (ex
);
2140 *this_cache
= cache
;
2144 static enum unwind_stop_reason
2145 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2148 struct i386_frame_cache
*cache
=
2149 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2152 return UNWIND_UNAVAILABLE
;
2154 return UNWIND_NO_REASON
;
2158 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2159 struct frame_id
*this_id
)
2161 struct i386_frame_cache
*cache
=
2162 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2167 /* See the end of i386_push_dummy_call. */
2168 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2171 static struct value
*
2172 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2173 void **this_cache
, int regnum
)
2175 /* Make sure we've initialized the cache. */
2176 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2178 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2182 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2183 struct frame_info
*this_frame
,
2184 void **this_prologue_cache
)
2186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2188 /* We shouldn't even bother if we don't have a sigcontext_addr
2190 if (tdep
->sigcontext_addr
== NULL
)
2193 if (tdep
->sigtramp_p
!= NULL
)
2195 if (tdep
->sigtramp_p (this_frame
))
2199 if (tdep
->sigtramp_start
!= 0)
2201 CORE_ADDR pc
= get_frame_pc (this_frame
);
2203 gdb_assert (tdep
->sigtramp_end
!= 0);
2204 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2211 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2214 i386_sigtramp_frame_unwind_stop_reason
,
2215 i386_sigtramp_frame_this_id
,
2216 i386_sigtramp_frame_prev_register
,
2218 i386_sigtramp_frame_sniffer
2223 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2225 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2230 static const struct frame_base i386_frame_base
=
2233 i386_frame_base_address
,
2234 i386_frame_base_address
,
2235 i386_frame_base_address
2238 static struct frame_id
2239 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2243 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2245 /* See the end of i386_push_dummy_call. */
2246 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2249 /* _Decimal128 function return values need 16-byte alignment on the
2253 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2255 return sp
& -(CORE_ADDR
)16;
2259 /* Figure out where the longjmp will land. Slurp the args out of the
2260 stack. We expect the first arg to be a pointer to the jmp_buf
2261 structure from which we extract the address that we will land at.
2262 This address is copied into PC. This routine returns non-zero on
2266 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2269 CORE_ADDR sp
, jb_addr
;
2270 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2271 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2272 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2274 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2275 longjmp will land. */
2276 if (jb_pc_offset
== -1)
2279 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2280 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2281 if (target_read_memory (sp
+ 4, buf
, 4))
2284 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2285 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2288 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2293 /* Check whether TYPE must be 16-byte-aligned when passed as a
2294 function argument. 16-byte vectors, _Decimal128 and structures or
2295 unions containing such types must be 16-byte-aligned; other
2296 arguments are 4-byte-aligned. */
2299 i386_16_byte_align_p (struct type
*type
)
2301 type
= check_typedef (type
);
2302 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2303 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2304 && TYPE_LENGTH (type
) == 16)
2306 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2307 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2308 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2309 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2312 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2314 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2322 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2323 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2324 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2325 CORE_ADDR struct_addr
)
2327 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2333 /* Determine the total space required for arguments and struct
2334 return address in a first pass (allowing for 16-byte-aligned
2335 arguments), then push arguments in a second pass. */
2337 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2339 int args_space_used
= 0;
2340 int have_16_byte_aligned_arg
= 0;
2346 /* Push value address. */
2347 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2348 write_memory (sp
, buf
, 4);
2349 args_space_used
+= 4;
2355 for (i
= 0; i
< nargs
; i
++)
2357 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2361 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2362 args_space_used
= align_up (args_space_used
, 16);
2364 write_memory (sp
+ args_space_used
,
2365 value_contents_all (args
[i
]), len
);
2366 /* The System V ABI says that:
2368 "An argument's size is increased, if necessary, to make it a
2369 multiple of [32-bit] words. This may require tail padding,
2370 depending on the size of the argument."
2372 This makes sure the stack stays word-aligned. */
2373 args_space_used
+= align_up (len
, 4);
2377 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2379 args_space
= align_up (args_space
, 16);
2380 have_16_byte_aligned_arg
= 1;
2382 args_space
+= align_up (len
, 4);
2388 if (have_16_byte_aligned_arg
)
2389 args_space
= align_up (args_space
, 16);
2394 /* Store return address. */
2396 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2397 write_memory (sp
, buf
, 4);
2399 /* Finally, update the stack pointer... */
2400 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2401 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2403 /* ...and fake a frame pointer. */
2404 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2406 /* MarkK wrote: This "+ 8" is all over the place:
2407 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2408 i386_dummy_id). It's there, since all frame unwinders for
2409 a given target have to agree (within a certain margin) on the
2410 definition of the stack address of a frame. Otherwise frame id
2411 comparison might not work correctly. Since DWARF2/GCC uses the
2412 stack address *before* the function call as a frame's CFA. On
2413 the i386, when %ebp is used as a frame pointer, the offset
2414 between the contents %ebp and the CFA as defined by GCC. */
2418 /* These registers are used for returning integers (and on some
2419 targets also for returning `struct' and `union' values when their
2420 size and alignment match an integer type). */
2421 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2422 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2424 /* Read, for architecture GDBARCH, a function return value of TYPE
2425 from REGCACHE, and copy that into VALBUF. */
2428 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2429 struct regcache
*regcache
, gdb_byte
*valbuf
)
2431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2432 int len
= TYPE_LENGTH (type
);
2433 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2435 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2437 if (tdep
->st0_regnum
< 0)
2439 warning (_("Cannot find floating-point return value."));
2440 memset (valbuf
, 0, len
);
2444 /* Floating-point return values can be found in %st(0). Convert
2445 its contents to the desired type. This is probably not
2446 exactly how it would happen on the target itself, but it is
2447 the best we can do. */
2448 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2449 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2453 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2454 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2456 if (len
<= low_size
)
2458 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2459 memcpy (valbuf
, buf
, len
);
2461 else if (len
<= (low_size
+ high_size
))
2463 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2464 memcpy (valbuf
, buf
, low_size
);
2465 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2466 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2469 internal_error (__FILE__
, __LINE__
,
2470 _("Cannot extract return value of %d bytes long."),
2475 /* Write, for architecture GDBARCH, a function return value of TYPE
2476 from VALBUF into REGCACHE. */
2479 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2480 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2483 int len
= TYPE_LENGTH (type
);
2485 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2488 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2490 if (tdep
->st0_regnum
< 0)
2492 warning (_("Cannot set floating-point return value."));
2496 /* Returning floating-point values is a bit tricky. Apart from
2497 storing the return value in %st(0), we have to simulate the
2498 state of the FPU at function return point. */
2500 /* Convert the value found in VALBUF to the extended
2501 floating-point format used by the FPU. This is probably
2502 not exactly how it would happen on the target itself, but
2503 it is the best we can do. */
2504 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2505 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2507 /* Set the top of the floating-point register stack to 7. The
2508 actual value doesn't really matter, but 7 is what a normal
2509 function return would end up with if the program started out
2510 with a freshly initialized FPU. */
2511 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2513 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2515 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2516 the floating-point register stack to 7, the appropriate value
2517 for the tag word is 0x3fff. */
2518 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2522 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2523 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2525 if (len
<= low_size
)
2526 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2527 else if (len
<= (low_size
+ high_size
))
2529 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2530 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2531 len
- low_size
, valbuf
+ low_size
);
2534 internal_error (__FILE__
, __LINE__
,
2535 _("Cannot store return value of %d bytes long."), len
);
2540 /* This is the variable that is set with "set struct-convention", and
2541 its legitimate values. */
2542 static const char default_struct_convention
[] = "default";
2543 static const char pcc_struct_convention
[] = "pcc";
2544 static const char reg_struct_convention
[] = "reg";
2545 static const char *valid_conventions
[] =
2547 default_struct_convention
,
2548 pcc_struct_convention
,
2549 reg_struct_convention
,
2552 static const char *struct_convention
= default_struct_convention
;
2554 /* Return non-zero if TYPE, which is assumed to be a structure,
2555 a union type, or an array type, should be returned in registers
2556 for architecture GDBARCH. */
2559 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2561 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2562 enum type_code code
= TYPE_CODE (type
);
2563 int len
= TYPE_LENGTH (type
);
2565 gdb_assert (code
== TYPE_CODE_STRUCT
2566 || code
== TYPE_CODE_UNION
2567 || code
== TYPE_CODE_ARRAY
);
2569 if (struct_convention
== pcc_struct_convention
2570 || (struct_convention
== default_struct_convention
2571 && tdep
->struct_return
== pcc_struct_return
))
2574 /* Structures consisting of a single `float', `double' or 'long
2575 double' member are returned in %st(0). */
2576 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2578 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2579 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2580 return (len
== 4 || len
== 8 || len
== 12);
2583 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2586 /* Determine, for architecture GDBARCH, how a return value of TYPE
2587 should be returned. If it is supposed to be returned in registers,
2588 and READBUF is non-zero, read the appropriate value from REGCACHE,
2589 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2590 from WRITEBUF into REGCACHE. */
2592 static enum return_value_convention
2593 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2594 struct type
*type
, struct regcache
*regcache
,
2595 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2597 enum type_code code
= TYPE_CODE (type
);
2599 if (((code
== TYPE_CODE_STRUCT
2600 || code
== TYPE_CODE_UNION
2601 || code
== TYPE_CODE_ARRAY
)
2602 && !i386_reg_struct_return_p (gdbarch
, type
))
2603 /* 128-bit decimal float uses the struct return convention. */
2604 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2606 /* The System V ABI says that:
2608 "A function that returns a structure or union also sets %eax
2609 to the value of the original address of the caller's area
2610 before it returns. Thus when the caller receives control
2611 again, the address of the returned object resides in register
2612 %eax and can be used to access the object."
2614 So the ABI guarantees that we can always find the return
2615 value just after the function has returned. */
2617 /* Note that the ABI doesn't mention functions returning arrays,
2618 which is something possible in certain languages such as Ada.
2619 In this case, the value is returned as if it was wrapped in
2620 a record, so the convention applied to records also applies
2627 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2628 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2631 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2634 /* This special case is for structures consisting of a single
2635 `float', `double' or 'long double' member. These structures are
2636 returned in %st(0). For these structures, we call ourselves
2637 recursively, changing TYPE into the type of the first member of
2638 the structure. Since that should work for all structures that
2639 have only one member, we don't bother to check the member's type
2641 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2643 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2644 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2649 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2651 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2653 return RETURN_VALUE_REGISTER_CONVENTION
;
2658 i387_ext_type (struct gdbarch
*gdbarch
)
2660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2662 if (!tdep
->i387_ext_type
)
2664 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2665 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2668 return tdep
->i387_ext_type
;
2671 /* Construct vector type for pseudo YMM registers. We can't use
2672 tdesc_find_type since YMM isn't described in target description. */
2674 static struct type
*
2675 i386_ymm_type (struct gdbarch
*gdbarch
)
2677 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2679 if (!tdep
->i386_ymm_type
)
2681 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2683 /* The type we're building is this: */
2685 union __gdb_builtin_type_vec256i
2687 int128_t uint128
[2];
2688 int64_t v2_int64
[4];
2689 int32_t v4_int32
[8];
2690 int16_t v8_int16
[16];
2691 int8_t v16_int8
[32];
2692 double v2_double
[4];
2699 t
= arch_composite_type (gdbarch
,
2700 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2701 append_composite_type_field (t
, "v8_float",
2702 init_vector_type (bt
->builtin_float
, 8));
2703 append_composite_type_field (t
, "v4_double",
2704 init_vector_type (bt
->builtin_double
, 4));
2705 append_composite_type_field (t
, "v32_int8",
2706 init_vector_type (bt
->builtin_int8
, 32));
2707 append_composite_type_field (t
, "v16_int16",
2708 init_vector_type (bt
->builtin_int16
, 16));
2709 append_composite_type_field (t
, "v8_int32",
2710 init_vector_type (bt
->builtin_int32
, 8));
2711 append_composite_type_field (t
, "v4_int64",
2712 init_vector_type (bt
->builtin_int64
, 4));
2713 append_composite_type_field (t
, "v2_int128",
2714 init_vector_type (bt
->builtin_int128
, 2));
2716 TYPE_VECTOR (t
) = 1;
2717 TYPE_NAME (t
) = "builtin_type_vec256i";
2718 tdep
->i386_ymm_type
= t
;
2721 return tdep
->i386_ymm_type
;
2724 /* Construct vector type for MMX registers. */
2725 static struct type
*
2726 i386_mmx_type (struct gdbarch
*gdbarch
)
2728 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2730 if (!tdep
->i386_mmx_type
)
2732 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2734 /* The type we're building is this: */
2736 union __gdb_builtin_type_vec64i
2739 int32_t v2_int32
[2];
2740 int16_t v4_int16
[4];
2747 t
= arch_composite_type (gdbarch
,
2748 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2750 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2751 append_composite_type_field (t
, "v2_int32",
2752 init_vector_type (bt
->builtin_int32
, 2));
2753 append_composite_type_field (t
, "v4_int16",
2754 init_vector_type (bt
->builtin_int16
, 4));
2755 append_composite_type_field (t
, "v8_int8",
2756 init_vector_type (bt
->builtin_int8
, 8));
2758 TYPE_VECTOR (t
) = 1;
2759 TYPE_NAME (t
) = "builtin_type_vec64i";
2760 tdep
->i386_mmx_type
= t
;
2763 return tdep
->i386_mmx_type
;
2766 /* Return the GDB type object for the "standard" data type of data in
2769 static struct type
*
2770 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2772 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2773 return i386_mmx_type (gdbarch
);
2774 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2775 return i386_ymm_type (gdbarch
);
2778 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2779 if (i386_byte_regnum_p (gdbarch
, regnum
))
2780 return bt
->builtin_int8
;
2781 else if (i386_word_regnum_p (gdbarch
, regnum
))
2782 return bt
->builtin_int16
;
2783 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2784 return bt
->builtin_int32
;
2787 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2790 /* Map a cooked register onto a raw register or memory. For the i386,
2791 the MMX registers need to be mapped onto floating point registers. */
2794 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2801 mmxreg
= regnum
- tdep
->mm0_regnum
;
2802 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2803 tos
= (fstat
>> 11) & 0x7;
2804 fpreg
= (mmxreg
+ tos
) % 8;
2806 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2809 /* A helper function for us by i386_pseudo_register_read_value and
2810 amd64_pseudo_register_read_value. It does all the work but reads
2811 the data into an already-allocated value. */
2814 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2815 struct regcache
*regcache
,
2817 struct value
*result_value
)
2819 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2820 enum register_status status
;
2821 gdb_byte
*buf
= value_contents_raw (result_value
);
2823 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2825 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2827 /* Extract (always little endian). */
2828 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2829 if (status
!= REG_VALID
)
2830 mark_value_bytes_unavailable (result_value
, 0,
2831 TYPE_LENGTH (value_type (result_value
)));
2833 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2839 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2841 regnum
-= tdep
->ymm0_regnum
;
2843 /* Extract (always little endian). Read lower 128bits. */
2844 status
= regcache_raw_read (regcache
,
2845 I387_XMM0_REGNUM (tdep
) + regnum
,
2847 if (status
!= REG_VALID
)
2848 mark_value_bytes_unavailable (result_value
, 0, 16);
2850 memcpy (buf
, raw_buf
, 16);
2851 /* Read upper 128bits. */
2852 status
= regcache_raw_read (regcache
,
2853 tdep
->ymm0h_regnum
+ regnum
,
2855 if (status
!= REG_VALID
)
2856 mark_value_bytes_unavailable (result_value
, 16, 32);
2858 memcpy (buf
+ 16, raw_buf
, 16);
2860 else if (i386_word_regnum_p (gdbarch
, regnum
))
2862 int gpnum
= regnum
- tdep
->ax_regnum
;
2864 /* Extract (always little endian). */
2865 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2866 if (status
!= REG_VALID
)
2867 mark_value_bytes_unavailable (result_value
, 0,
2868 TYPE_LENGTH (value_type (result_value
)));
2870 memcpy (buf
, raw_buf
, 2);
2872 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2874 /* Check byte pseudo registers last since this function will
2875 be called from amd64_pseudo_register_read, which handles
2876 byte pseudo registers differently. */
2877 int gpnum
= regnum
- tdep
->al_regnum
;
2879 /* Extract (always little endian). We read both lower and
2881 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2882 if (status
!= REG_VALID
)
2883 mark_value_bytes_unavailable (result_value
, 0,
2884 TYPE_LENGTH (value_type (result_value
)));
2885 else if (gpnum
>= 4)
2886 memcpy (buf
, raw_buf
+ 1, 1);
2888 memcpy (buf
, raw_buf
, 1);
2891 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2895 static struct value
*
2896 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2897 struct regcache
*regcache
,
2900 struct value
*result
;
2902 result
= allocate_value (register_type (gdbarch
, regnum
));
2903 VALUE_LVAL (result
) = lval_register
;
2904 VALUE_REGNUM (result
) = regnum
;
2906 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2912 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2913 int regnum
, const gdb_byte
*buf
)
2915 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2917 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2919 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2922 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2923 /* ... Modify ... (always little endian). */
2924 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2926 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2930 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2932 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2934 regnum
-= tdep
->ymm0_regnum
;
2936 /* ... Write lower 128bits. */
2937 regcache_raw_write (regcache
,
2938 I387_XMM0_REGNUM (tdep
) + regnum
,
2940 /* ... Write upper 128bits. */
2941 regcache_raw_write (regcache
,
2942 tdep
->ymm0h_regnum
+ regnum
,
2945 else if (i386_word_regnum_p (gdbarch
, regnum
))
2947 int gpnum
= regnum
- tdep
->ax_regnum
;
2950 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2951 /* ... Modify ... (always little endian). */
2952 memcpy (raw_buf
, buf
, 2);
2954 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2956 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2958 /* Check byte pseudo registers last since this function will
2959 be called from amd64_pseudo_register_read, which handles
2960 byte pseudo registers differently. */
2961 int gpnum
= regnum
- tdep
->al_regnum
;
2963 /* Read ... We read both lower and upper registers. */
2964 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2965 /* ... Modify ... (always little endian). */
2967 memcpy (raw_buf
+ 1, buf
, 1);
2969 memcpy (raw_buf
, buf
, 1);
2971 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2974 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2979 /* Return the register number of the register allocated by GCC after
2980 REGNUM, or -1 if there is no such register. */
2983 i386_next_regnum (int regnum
)
2985 /* GCC allocates the registers in the order:
2987 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2989 Since storing a variable in %esp doesn't make any sense we return
2990 -1 for %ebp and for %esp itself. */
2991 static int next_regnum
[] =
2993 I386_EDX_REGNUM
, /* Slot for %eax. */
2994 I386_EBX_REGNUM
, /* Slot for %ecx. */
2995 I386_ECX_REGNUM
, /* Slot for %edx. */
2996 I386_ESI_REGNUM
, /* Slot for %ebx. */
2997 -1, -1, /* Slots for %esp and %ebp. */
2998 I386_EDI_REGNUM
, /* Slot for %esi. */
2999 I386_EBP_REGNUM
/* Slot for %edi. */
3002 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3003 return next_regnum
[regnum
];
3008 /* Return nonzero if a value of type TYPE stored in register REGNUM
3009 needs any special handling. */
3012 i386_convert_register_p (struct gdbarch
*gdbarch
,
3013 int regnum
, struct type
*type
)
3015 int len
= TYPE_LENGTH (type
);
3017 /* Values may be spread across multiple registers. Most debugging
3018 formats aren't expressive enough to specify the locations, so
3019 some heuristics is involved. Right now we only handle types that
3020 have a length that is a multiple of the word size, since GCC
3021 doesn't seem to put any other types into registers. */
3022 if (len
> 4 && len
% 4 == 0)
3024 int last_regnum
= regnum
;
3028 last_regnum
= i386_next_regnum (last_regnum
);
3032 if (last_regnum
!= -1)
3036 return i387_convert_register_p (gdbarch
, regnum
, type
);
3039 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3040 return its contents in TO. */
3043 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3044 struct type
*type
, gdb_byte
*to
,
3045 int *optimizedp
, int *unavailablep
)
3047 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3048 int len
= TYPE_LENGTH (type
);
3050 if (i386_fp_regnum_p (gdbarch
, regnum
))
3051 return i387_register_to_value (frame
, regnum
, type
, to
,
3052 optimizedp
, unavailablep
);
3054 /* Read a value spread across multiple registers. */
3056 gdb_assert (len
> 4 && len
% 4 == 0);
3060 gdb_assert (regnum
!= -1);
3061 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3063 if (!get_frame_register_bytes (frame
, regnum
, 0,
3064 register_size (gdbarch
, regnum
),
3065 to
, optimizedp
, unavailablep
))
3068 regnum
= i386_next_regnum (regnum
);
3073 *optimizedp
= *unavailablep
= 0;
3077 /* Write the contents FROM of a value of type TYPE into register
3078 REGNUM in frame FRAME. */
3081 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3082 struct type
*type
, const gdb_byte
*from
)
3084 int len
= TYPE_LENGTH (type
);
3086 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3088 i387_value_to_register (frame
, regnum
, type
, from
);
3092 /* Write a value spread across multiple registers. */
3094 gdb_assert (len
> 4 && len
% 4 == 0);
3098 gdb_assert (regnum
!= -1);
3099 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3101 put_frame_register (frame
, regnum
, from
);
3102 regnum
= i386_next_regnum (regnum
);
3108 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3109 in the general-purpose register set REGSET to register cache
3110 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3113 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3114 int regnum
, const void *gregs
, size_t len
)
3116 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3117 const gdb_byte
*regs
= gregs
;
3120 gdb_assert (len
== tdep
->sizeof_gregset
);
3122 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3124 if ((regnum
== i
|| regnum
== -1)
3125 && tdep
->gregset_reg_offset
[i
] != -1)
3126 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3130 /* Collect register REGNUM from the register cache REGCACHE and store
3131 it in the buffer specified by GREGS and LEN as described by the
3132 general-purpose register set REGSET. If REGNUM is -1, do this for
3133 all registers in REGSET. */
3136 i386_collect_gregset (const struct regset
*regset
,
3137 const struct regcache
*regcache
,
3138 int regnum
, void *gregs
, size_t len
)
3140 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3141 gdb_byte
*regs
= gregs
;
3144 gdb_assert (len
== tdep
->sizeof_gregset
);
3146 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3148 if ((regnum
== i
|| regnum
== -1)
3149 && tdep
->gregset_reg_offset
[i
] != -1)
3150 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3154 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3155 in the floating-point register set REGSET to register cache
3156 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3159 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3160 int regnum
, const void *fpregs
, size_t len
)
3162 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3164 if (len
== I387_SIZEOF_FXSAVE
)
3166 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3170 gdb_assert (len
== tdep
->sizeof_fpregset
);
3171 i387_supply_fsave (regcache
, regnum
, fpregs
);
3174 /* Collect register REGNUM from the register cache REGCACHE and store
3175 it in the buffer specified by FPREGS and LEN as described by the
3176 floating-point register set REGSET. If REGNUM is -1, do this for
3177 all registers in REGSET. */
3180 i386_collect_fpregset (const struct regset
*regset
,
3181 const struct regcache
*regcache
,
3182 int regnum
, void *fpregs
, size_t len
)
3184 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3186 if (len
== I387_SIZEOF_FXSAVE
)
3188 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3192 gdb_assert (len
== tdep
->sizeof_fpregset
);
3193 i387_collect_fsave (regcache
, regnum
, fpregs
);
3196 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3199 i386_supply_xstateregset (const struct regset
*regset
,
3200 struct regcache
*regcache
, int regnum
,
3201 const void *xstateregs
, size_t len
)
3203 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3206 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3209 i386_collect_xstateregset (const struct regset
*regset
,
3210 const struct regcache
*regcache
,
3211 int regnum
, void *xstateregs
, size_t len
)
3213 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3216 /* Return the appropriate register set for the core section identified
3217 by SECT_NAME and SECT_SIZE. */
3219 const struct regset
*
3220 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3221 const char *sect_name
, size_t sect_size
)
3223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3225 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3227 if (tdep
->gregset
== NULL
)
3228 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3229 i386_collect_gregset
);
3230 return tdep
->gregset
;
3233 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3234 || (strcmp (sect_name
, ".reg-xfp") == 0
3235 && sect_size
== I387_SIZEOF_FXSAVE
))
3237 if (tdep
->fpregset
== NULL
)
3238 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3239 i386_collect_fpregset
);
3240 return tdep
->fpregset
;
3243 if (strcmp (sect_name
, ".reg-xstate") == 0)
3245 if (tdep
->xstateregset
== NULL
)
3246 tdep
->xstateregset
= regset_alloc (gdbarch
,
3247 i386_supply_xstateregset
,
3248 i386_collect_xstateregset
);
3250 return tdep
->xstateregset
;
3257 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3260 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3261 CORE_ADDR pc
, char *name
)
3263 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3264 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3267 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3269 unsigned long indirect
=
3270 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3271 struct minimal_symbol
*indsym
=
3272 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3273 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3277 if (strncmp (symname
, "__imp_", 6) == 0
3278 || strncmp (symname
, "_imp_", 5) == 0)
3280 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3283 return 0; /* Not a trampoline. */
3287 /* Return whether the THIS_FRAME corresponds to a sigtramp
3291 i386_sigtramp_p (struct frame_info
*this_frame
)
3293 CORE_ADDR pc
= get_frame_pc (this_frame
);
3296 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3297 return (name
&& strcmp ("_sigtramp", name
) == 0);
3301 /* We have two flavours of disassembly. The machinery on this page
3302 deals with switching between those. */
3305 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3307 gdb_assert (disassembly_flavor
== att_flavor
3308 || disassembly_flavor
== intel_flavor
);
3310 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3311 constified, cast to prevent a compiler warning. */
3312 info
->disassembler_options
= (char *) disassembly_flavor
;
3314 return print_insn_i386 (pc
, info
);
3318 /* There are a few i386 architecture variants that differ only
3319 slightly from the generic i386 target. For now, we don't give them
3320 their own source file, but include them here. As a consequence,
3321 they'll always be included. */
3323 /* System V Release 4 (SVR4). */
3325 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3329 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3331 CORE_ADDR pc
= get_frame_pc (this_frame
);
3334 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3335 currently unknown. */
3336 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3337 return (name
&& (strcmp ("_sigreturn", name
) == 0
3338 || strcmp ("_sigacthandler", name
) == 0
3339 || strcmp ("sigvechandler", name
) == 0));
3342 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3343 address of the associated sigcontext (ucontext) structure. */
3346 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3348 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3349 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3353 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3354 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3356 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3363 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3365 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3366 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3369 /* System V Release 4 (SVR4). */
3372 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3374 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3376 /* System V Release 4 uses ELF. */
3377 i386_elf_init_abi (info
, gdbarch
);
3379 /* System V Release 4 has shared libraries. */
3380 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3382 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3383 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3384 tdep
->sc_pc_offset
= 36 + 14 * 4;
3385 tdep
->sc_sp_offset
= 36 + 17 * 4;
3387 tdep
->jb_pc_offset
= 20;
3393 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3397 /* DJGPP doesn't have any special frames for signal handlers. */
3398 tdep
->sigtramp_p
= NULL
;
3400 tdep
->jb_pc_offset
= 36;
3402 /* DJGPP does not support the SSE registers. */
3403 if (! tdesc_has_registers (info
.target_desc
))
3404 tdep
->tdesc
= tdesc_i386_mmx
;
3406 /* Native compiler is GCC, which uses the SVR4 register numbering
3407 even in COFF and STABS. See the comment in i386_gdbarch_init,
3408 before the calls to set_gdbarch_stab_reg_to_regnum and
3409 set_gdbarch_sdb_reg_to_regnum. */
3410 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3411 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3413 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3417 /* i386 register groups. In addition to the normal groups, add "mmx"
3420 static struct reggroup
*i386_sse_reggroup
;
3421 static struct reggroup
*i386_mmx_reggroup
;
3424 i386_init_reggroups (void)
3426 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3427 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3431 i386_add_reggroups (struct gdbarch
*gdbarch
)
3433 reggroup_add (gdbarch
, i386_sse_reggroup
);
3434 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3435 reggroup_add (gdbarch
, general_reggroup
);
3436 reggroup_add (gdbarch
, float_reggroup
);
3437 reggroup_add (gdbarch
, all_reggroup
);
3438 reggroup_add (gdbarch
, save_reggroup
);
3439 reggroup_add (gdbarch
, restore_reggroup
);
3440 reggroup_add (gdbarch
, vector_reggroup
);
3441 reggroup_add (gdbarch
, system_reggroup
);
3445 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3446 struct reggroup
*group
)
3448 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3449 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3450 ymm_regnum_p
, ymmh_regnum_p
;
3452 /* Don't include pseudo registers, except for MMX, in any register
3454 if (i386_byte_regnum_p (gdbarch
, regnum
))
3457 if (i386_word_regnum_p (gdbarch
, regnum
))
3460 if (i386_dword_regnum_p (gdbarch
, regnum
))
3463 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3464 if (group
== i386_mmx_reggroup
)
3465 return mmx_regnum_p
;
3467 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3468 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3469 if (group
== i386_sse_reggroup
)
3470 return xmm_regnum_p
|| mxcsr_regnum_p
;
3472 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3473 if (group
== vector_reggroup
)
3474 return (mmx_regnum_p
3478 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3479 == I386_XSTATE_SSE_MASK
)));
3481 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3482 || i386_fpc_regnum_p (gdbarch
, regnum
));
3483 if (group
== float_reggroup
)
3486 /* For "info reg all", don't include upper YMM registers nor XMM
3487 registers when AVX is supported. */
3488 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3489 if (group
== all_reggroup
3491 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3495 if (group
== general_reggroup
)
3496 return (!fp_regnum_p
3503 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3507 /* Get the ARGIth function argument for the current function. */
3510 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3513 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3514 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3515 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3516 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3520 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3522 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3524 /* On i386, breakpoint is exactly 1 byte long, so we just
3525 adjust the PC in the regcache. */
3527 regcache_write_pc (regcache
, current_pc
);
3531 #define PREFIX_REPZ 0x01
3532 #define PREFIX_REPNZ 0x02
3533 #define PREFIX_LOCK 0x04
3534 #define PREFIX_DATA 0x08
3535 #define PREFIX_ADDR 0x10
3547 /* i386 arith/logic operations */
3560 struct i386_record_s
3562 struct gdbarch
*gdbarch
;
3563 struct regcache
*regcache
;
3564 CORE_ADDR orig_addr
;
3570 uint8_t mod
, reg
, rm
;
3579 /* Parse "modrm" part in current memory address that irp->addr point to
3580 Return -1 if something wrong. */
3583 i386_record_modrm (struct i386_record_s
*irp
)
3585 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3587 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3590 printf_unfiltered (_("Process record: error reading memory at "
3591 "addr %s len = 1.\n"),
3592 paddress (gdbarch
, irp
->addr
));
3596 irp
->mod
= (irp
->modrm
>> 6) & 3;
3597 irp
->reg
= (irp
->modrm
>> 3) & 7;
3598 irp
->rm
= irp
->modrm
& 7;
3603 /* Get the memory address that current instruction write to and set it to
3604 the argument "addr".
3605 Return -1 if something wrong. */
3608 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3610 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3611 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3623 uint8_t base
= irp
->rm
;
3628 if (target_read_memory (irp
->addr
, &byte
, 1))
3631 printf_unfiltered (_("Process record: error reading memory "
3632 "at addr %s len = 1.\n"),
3633 paddress (gdbarch
, irp
->addr
));
3637 scale
= (byte
>> 6) & 3;
3638 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3646 if ((base
& 7) == 5)
3649 if (target_read_memory (irp
->addr
, buf
, 4))
3652 printf_unfiltered (_("Process record: error reading "
3653 "memory at addr %s len = 4.\n"),
3654 paddress (gdbarch
, irp
->addr
));
3658 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3659 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3660 *addr
+= irp
->addr
+ irp
->rip_offset
;
3664 if (target_read_memory (irp
->addr
, buf
, 1))
3667 printf_unfiltered (_("Process record: error reading memory "
3668 "at addr %s len = 1.\n"),
3669 paddress (gdbarch
, irp
->addr
));
3673 *addr
= (int8_t) buf
[0];
3676 if (target_read_memory (irp
->addr
, buf
, 4))
3679 printf_unfiltered (_("Process record: error reading memory "
3680 "at addr %s len = 4.\n"),
3681 paddress (gdbarch
, irp
->addr
));
3684 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3692 if (base
== 4 && irp
->popl_esp_hack
)
3693 *addr
+= irp
->popl_esp_hack
;
3694 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3697 if (irp
->aflag
== 2)
3702 *addr
= (uint32_t) (offset64
+ *addr
);
3704 if (havesib
&& (index
!= 4 || scale
!= 0))
3706 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3708 if (irp
->aflag
== 2)
3709 *addr
+= offset64
<< scale
;
3711 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3722 if (target_read_memory (irp
->addr
, buf
, 2))
3725 printf_unfiltered (_("Process record: error reading "
3726 "memory at addr %s len = 2.\n"),
3727 paddress (gdbarch
, irp
->addr
));
3731 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3737 if (target_read_memory (irp
->addr
, buf
, 1))
3740 printf_unfiltered (_("Process record: error reading memory "
3741 "at addr %s len = 1.\n"),
3742 paddress (gdbarch
, irp
->addr
));
3746 *addr
= (int8_t) buf
[0];
3749 if (target_read_memory (irp
->addr
, buf
, 2))
3752 printf_unfiltered (_("Process record: error reading memory "
3753 "at addr %s len = 2.\n"),
3754 paddress (gdbarch
, irp
->addr
));
3758 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3765 regcache_raw_read_unsigned (irp
->regcache
,
3766 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3768 *addr
= (uint32_t) (*addr
+ offset64
);
3769 regcache_raw_read_unsigned (irp
->regcache
,
3770 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3772 *addr
= (uint32_t) (*addr
+ offset64
);
3775 regcache_raw_read_unsigned (irp
->regcache
,
3776 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3778 *addr
= (uint32_t) (*addr
+ offset64
);
3779 regcache_raw_read_unsigned (irp
->regcache
,
3780 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3782 *addr
= (uint32_t) (*addr
+ offset64
);
3785 regcache_raw_read_unsigned (irp
->regcache
,
3786 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3788 *addr
= (uint32_t) (*addr
+ offset64
);
3789 regcache_raw_read_unsigned (irp
->regcache
,
3790 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3792 *addr
= (uint32_t) (*addr
+ offset64
);
3795 regcache_raw_read_unsigned (irp
->regcache
,
3796 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3798 *addr
= (uint32_t) (*addr
+ offset64
);
3799 regcache_raw_read_unsigned (irp
->regcache
,
3800 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3802 *addr
= (uint32_t) (*addr
+ offset64
);
3805 regcache_raw_read_unsigned (irp
->regcache
,
3806 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3808 *addr
= (uint32_t) (*addr
+ offset64
);
3811 regcache_raw_read_unsigned (irp
->regcache
,
3812 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3814 *addr
= (uint32_t) (*addr
+ offset64
);
3817 regcache_raw_read_unsigned (irp
->regcache
,
3818 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3820 *addr
= (uint32_t) (*addr
+ offset64
);
3823 regcache_raw_read_unsigned (irp
->regcache
,
3824 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3826 *addr
= (uint32_t) (*addr
+ offset64
);
3836 /* Record the value of the memory that willbe changed in current instruction
3837 to "record_arch_list".
3838 Return -1 if something wrong. */
3841 i386_record_lea_modrm (struct i386_record_s
*irp
)
3843 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3846 if (irp
->override
>= 0)
3848 if (record_memory_query
)
3852 target_terminal_ours ();
3854 Process record ignores the memory change of instruction at address %s\n\
3855 because it can't get the value of the segment register.\n\
3856 Do you want to stop the program?"),
3857 paddress (gdbarch
, irp
->orig_addr
));
3858 target_terminal_inferior ();
3866 if (i386_record_lea_modrm_addr (irp
, &addr
))
3869 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3875 /* Record the push operation to "record_arch_list".
3876 Return -1 if something wrong. */
3879 i386_record_push (struct i386_record_s
*irp
, int size
)
3883 if (record_arch_list_add_reg (irp
->regcache
,
3884 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3886 regcache_raw_read_unsigned (irp
->regcache
,
3887 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3889 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3896 /* Defines contents to record. */
3897 #define I386_SAVE_FPU_REGS 0xfffd
3898 #define I386_SAVE_FPU_ENV 0xfffe
3899 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3901 /* Record the value of floating point registers which will be changed
3902 by the current instruction to "record_arch_list". Return -1 if
3903 something is wrong. */
3905 static int i386_record_floats (struct gdbarch
*gdbarch
,
3906 struct i386_record_s
*ir
,
3909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3912 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3913 happen. Currently we store st0-st7 registers, but we need not store all
3914 registers all the time, in future we use ftag register and record only
3915 those who are not marked as an empty. */
3917 if (I386_SAVE_FPU_REGS
== iregnum
)
3919 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3921 if (record_arch_list_add_reg (ir
->regcache
, i
))
3925 else if (I386_SAVE_FPU_ENV
== iregnum
)
3927 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3929 if (record_arch_list_add_reg (ir
->regcache
, i
))
3933 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3935 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3937 if (record_arch_list_add_reg (ir
->regcache
, i
))
3941 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3942 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3944 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3949 /* Parameter error. */
3952 if(I386_SAVE_FPU_ENV
!= iregnum
)
3954 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3956 if (record_arch_list_add_reg (ir
->regcache
, i
))
3963 /* Parse the current instruction and record the values of the registers and
3964 memory that will be changed in current instruction to "record_arch_list".
3965 Return -1 if something wrong. */
3967 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3968 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3971 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3972 CORE_ADDR input_addr
)
3974 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3980 gdb_byte buf
[MAX_REGISTER_SIZE
];
3981 struct i386_record_s ir
;
3982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3987 memset (&ir
, 0, sizeof (struct i386_record_s
));
3988 ir
.regcache
= regcache
;
3989 ir
.addr
= input_addr
;
3990 ir
.orig_addr
= input_addr
;
3994 ir
.popl_esp_hack
= 0;
3995 ir
.regmap
= tdep
->record_regmap
;
3996 ir
.gdbarch
= gdbarch
;
3998 if (record_debug
> 1)
3999 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4001 paddress (gdbarch
, ir
.addr
));
4006 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4009 printf_unfiltered (_("Process record: error reading memory at "
4010 "addr %s len = 1.\n"),
4011 paddress (gdbarch
, ir
.addr
));
4015 switch (opcode8
) /* Instruction prefixes */
4017 case REPE_PREFIX_OPCODE
:
4018 prefixes
|= PREFIX_REPZ
;
4020 case REPNE_PREFIX_OPCODE
:
4021 prefixes
|= PREFIX_REPNZ
;
4023 case LOCK_PREFIX_OPCODE
:
4024 prefixes
|= PREFIX_LOCK
;
4026 case CS_PREFIX_OPCODE
:
4027 ir
.override
= X86_RECORD_CS_REGNUM
;
4029 case SS_PREFIX_OPCODE
:
4030 ir
.override
= X86_RECORD_SS_REGNUM
;
4032 case DS_PREFIX_OPCODE
:
4033 ir
.override
= X86_RECORD_DS_REGNUM
;
4035 case ES_PREFIX_OPCODE
:
4036 ir
.override
= X86_RECORD_ES_REGNUM
;
4038 case FS_PREFIX_OPCODE
:
4039 ir
.override
= X86_RECORD_FS_REGNUM
;
4041 case GS_PREFIX_OPCODE
:
4042 ir
.override
= X86_RECORD_GS_REGNUM
;
4044 case DATA_PREFIX_OPCODE
:
4045 prefixes
|= PREFIX_DATA
;
4047 case ADDR_PREFIX_OPCODE
:
4048 prefixes
|= PREFIX_ADDR
;
4050 case 0x40: /* i386 inc %eax */
4051 case 0x41: /* i386 inc %ecx */
4052 case 0x42: /* i386 inc %edx */
4053 case 0x43: /* i386 inc %ebx */
4054 case 0x44: /* i386 inc %esp */
4055 case 0x45: /* i386 inc %ebp */
4056 case 0x46: /* i386 inc %esi */
4057 case 0x47: /* i386 inc %edi */
4058 case 0x48: /* i386 dec %eax */
4059 case 0x49: /* i386 dec %ecx */
4060 case 0x4a: /* i386 dec %edx */
4061 case 0x4b: /* i386 dec %ebx */
4062 case 0x4c: /* i386 dec %esp */
4063 case 0x4d: /* i386 dec %ebp */
4064 case 0x4e: /* i386 dec %esi */
4065 case 0x4f: /* i386 dec %edi */
4066 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4070 rex_w
= (opcode8
>> 3) & 1;
4071 rex_r
= (opcode8
& 0x4) << 1;
4072 ir
.rex_x
= (opcode8
& 0x2) << 2;
4073 ir
.rex_b
= (opcode8
& 0x1) << 3;
4075 else /* 32 bit target */
4084 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4090 if (prefixes
& PREFIX_DATA
)
4093 if (prefixes
& PREFIX_ADDR
)
4095 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4098 /* Now check op code. */
4099 opcode
= (uint32_t) opcode8
;
4104 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4107 printf_unfiltered (_("Process record: error reading memory at "
4108 "addr %s len = 1.\n"),
4109 paddress (gdbarch
, ir
.addr
));
4113 opcode
= (uint32_t) opcode8
| 0x0f00;
4117 case 0x00: /* arith & logic */
4165 if (((opcode
>> 3) & 7) != OP_CMPL
)
4167 if ((opcode
& 1) == 0)
4170 ir
.ot
= ir
.dflag
+ OT_WORD
;
4172 switch ((opcode
>> 1) & 3)
4174 case 0: /* OP Ev, Gv */
4175 if (i386_record_modrm (&ir
))
4179 if (i386_record_lea_modrm (&ir
))
4185 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4187 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4190 case 1: /* OP Gv, Ev */
4191 if (i386_record_modrm (&ir
))
4194 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4196 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4198 case 2: /* OP A, Iv */
4199 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4203 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4206 case 0x80: /* GRP1 */
4210 if (i386_record_modrm (&ir
))
4213 if (ir
.reg
!= OP_CMPL
)
4215 if ((opcode
& 1) == 0)
4218 ir
.ot
= ir
.dflag
+ OT_WORD
;
4225 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4226 if (i386_record_lea_modrm (&ir
))
4230 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4232 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4235 case 0x40: /* inc */
4244 case 0x48: /* dec */
4253 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4257 case 0xf6: /* GRP3 */
4259 if ((opcode
& 1) == 0)
4262 ir
.ot
= ir
.dflag
+ OT_WORD
;
4263 if (i386_record_modrm (&ir
))
4266 if (ir
.mod
!= 3 && ir
.reg
== 0)
4267 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4278 if (i386_record_lea_modrm (&ir
))
4284 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4286 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4288 if (ir
.reg
== 3) /* neg */
4289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4295 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4296 if (ir
.ot
!= OT_BYTE
)
4297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4302 opcode
= opcode
<< 8 | ir
.modrm
;
4308 case 0xfe: /* GRP4 */
4309 case 0xff: /* GRP5 */
4310 if (i386_record_modrm (&ir
))
4312 if (ir
.reg
>= 2 && opcode
== 0xfe)
4315 opcode
= opcode
<< 8 | ir
.modrm
;
4322 if ((opcode
& 1) == 0)
4325 ir
.ot
= ir
.dflag
+ OT_WORD
;
4328 if (i386_record_lea_modrm (&ir
))
4334 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4336 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4341 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4343 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4345 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4349 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4351 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4355 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4358 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4360 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4365 opcode
= opcode
<< 8 | ir
.modrm
;
4371 case 0x84: /* test */
4375 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4378 case 0x98: /* CWDE/CBW */
4379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4382 case 0x99: /* CDQ/CWD */
4383 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4384 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4387 case 0x0faf: /* imul */
4390 ir
.ot
= ir
.dflag
+ OT_WORD
;
4391 if (i386_record_modrm (&ir
))
4394 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4395 else if (opcode
== 0x6b)
4398 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4400 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4401 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4404 case 0x0fc0: /* xadd */
4406 if ((opcode
& 1) == 0)
4409 ir
.ot
= ir
.dflag
+ OT_WORD
;
4410 if (i386_record_modrm (&ir
))
4415 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4417 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4418 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4420 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4424 if (i386_record_lea_modrm (&ir
))
4426 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4428 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4433 case 0x0fb0: /* cmpxchg */
4435 if ((opcode
& 1) == 0)
4438 ir
.ot
= ir
.dflag
+ OT_WORD
;
4439 if (i386_record_modrm (&ir
))
4444 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4445 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4447 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4452 if (i386_record_lea_modrm (&ir
))
4455 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4458 case 0x0fc7: /* cmpxchg8b */
4459 if (i386_record_modrm (&ir
))
4464 opcode
= opcode
<< 8 | ir
.modrm
;
4467 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4468 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4469 if (i386_record_lea_modrm (&ir
))
4471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4474 case 0x50: /* push */
4484 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4486 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4490 case 0x06: /* push es */
4491 case 0x0e: /* push cs */
4492 case 0x16: /* push ss */
4493 case 0x1e: /* push ds */
4494 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4499 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4503 case 0x0fa0: /* push fs */
4504 case 0x0fa8: /* push gs */
4505 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4510 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4514 case 0x60: /* pusha */
4515 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4520 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4524 case 0x58: /* pop */
4532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4533 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4536 case 0x61: /* popa */
4537 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4542 for (regnum
= X86_RECORD_REAX_REGNUM
;
4543 regnum
<= X86_RECORD_REDI_REGNUM
;
4545 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4548 case 0x8f: /* pop */
4549 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4550 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4552 ir
.ot
= ir
.dflag
+ OT_WORD
;
4553 if (i386_record_modrm (&ir
))
4556 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4559 ir
.popl_esp_hack
= 1 << ir
.ot
;
4560 if (i386_record_lea_modrm (&ir
))
4563 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4566 case 0xc8: /* enter */
4567 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4568 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4570 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4574 case 0xc9: /* leave */
4575 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4576 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4579 case 0x07: /* pop es */
4580 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4586 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4587 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4590 case 0x17: /* pop ss */
4591 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4596 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4601 case 0x1f: /* pop ds */
4602 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4607 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4608 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4609 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4612 case 0x0fa1: /* pop fs */
4613 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4614 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4615 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4618 case 0x0fa9: /* pop gs */
4619 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4620 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4624 case 0x88: /* mov */
4628 if ((opcode
& 1) == 0)
4631 ir
.ot
= ir
.dflag
+ OT_WORD
;
4633 if (i386_record_modrm (&ir
))
4638 if (opcode
== 0xc6 || opcode
== 0xc7)
4639 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4640 if (i386_record_lea_modrm (&ir
))
4645 if (opcode
== 0xc6 || opcode
== 0xc7)
4647 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4649 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4653 case 0x8a: /* mov */
4655 if ((opcode
& 1) == 0)
4658 ir
.ot
= ir
.dflag
+ OT_WORD
;
4659 if (i386_record_modrm (&ir
))
4662 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4664 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4667 case 0x8c: /* mov seg */
4668 if (i386_record_modrm (&ir
))
4673 opcode
= opcode
<< 8 | ir
.modrm
;
4678 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4682 if (i386_record_lea_modrm (&ir
))
4687 case 0x8e: /* mov seg */
4688 if (i386_record_modrm (&ir
))
4693 regnum
= X86_RECORD_ES_REGNUM
;
4696 regnum
= X86_RECORD_SS_REGNUM
;
4699 regnum
= X86_RECORD_DS_REGNUM
;
4702 regnum
= X86_RECORD_FS_REGNUM
;
4705 regnum
= X86_RECORD_GS_REGNUM
;
4709 opcode
= opcode
<< 8 | ir
.modrm
;
4713 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4717 case 0x0fb6: /* movzbS */
4718 case 0x0fb7: /* movzwS */
4719 case 0x0fbe: /* movsbS */
4720 case 0x0fbf: /* movswS */
4721 if (i386_record_modrm (&ir
))
4723 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4726 case 0x8d: /* lea */
4727 if (i386_record_modrm (&ir
))
4732 opcode
= opcode
<< 8 | ir
.modrm
;
4737 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4739 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4742 case 0xa0: /* mov EAX */
4745 case 0xd7: /* xlat */
4746 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4749 case 0xa2: /* mov EAX */
4751 if (ir
.override
>= 0)
4753 if (record_memory_query
)
4757 target_terminal_ours ();
4759 Process record ignores the memory change of instruction at address %s\n\
4760 because it can't get the value of the segment register.\n\
4761 Do you want to stop the program?"),
4762 paddress (gdbarch
, ir
.orig_addr
));
4763 target_terminal_inferior ();
4770 if ((opcode
& 1) == 0)
4773 ir
.ot
= ir
.dflag
+ OT_WORD
;
4776 if (target_read_memory (ir
.addr
, buf
, 8))
4779 printf_unfiltered (_("Process record: error reading "
4780 "memory at addr 0x%s len = 8.\n"),
4781 paddress (gdbarch
, ir
.addr
));
4785 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4789 if (target_read_memory (ir
.addr
, buf
, 4))
4792 printf_unfiltered (_("Process record: error reading "
4793 "memory at addr 0x%s len = 4.\n"),
4794 paddress (gdbarch
, ir
.addr
));
4798 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4802 if (target_read_memory (ir
.addr
, buf
, 2))
4805 printf_unfiltered (_("Process record: error reading "
4806 "memory at addr 0x%s len = 2.\n"),
4807 paddress (gdbarch
, ir
.addr
));
4811 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4813 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4818 case 0xb0: /* mov R, Ib */
4826 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4827 ? ((opcode
& 0x7) | ir
.rex_b
)
4828 : ((opcode
& 0x7) & 0x3));
4831 case 0xb8: /* mov R, Iv */
4839 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4842 case 0x91: /* xchg R, EAX */
4849 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4850 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4853 case 0x86: /* xchg Ev, Gv */
4855 if ((opcode
& 1) == 0)
4858 ir
.ot
= ir
.dflag
+ OT_WORD
;
4859 if (i386_record_modrm (&ir
))
4864 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4866 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4870 if (i386_record_lea_modrm (&ir
))
4874 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4876 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4879 case 0xc4: /* les Gv */
4880 case 0xc5: /* lds Gv */
4881 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4887 case 0x0fb2: /* lss Gv */
4888 case 0x0fb4: /* lfs Gv */
4889 case 0x0fb5: /* lgs Gv */
4890 if (i386_record_modrm (&ir
))
4898 opcode
= opcode
<< 8 | ir
.modrm
;
4903 case 0xc4: /* les Gv */
4904 regnum
= X86_RECORD_ES_REGNUM
;
4906 case 0xc5: /* lds Gv */
4907 regnum
= X86_RECORD_DS_REGNUM
;
4909 case 0x0fb2: /* lss Gv */
4910 regnum
= X86_RECORD_SS_REGNUM
;
4912 case 0x0fb4: /* lfs Gv */
4913 regnum
= X86_RECORD_FS_REGNUM
;
4915 case 0x0fb5: /* lgs Gv */
4916 regnum
= X86_RECORD_GS_REGNUM
;
4919 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4920 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4924 case 0xc0: /* shifts */
4930 if ((opcode
& 1) == 0)
4933 ir
.ot
= ir
.dflag
+ OT_WORD
;
4934 if (i386_record_modrm (&ir
))
4936 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4938 if (i386_record_lea_modrm (&ir
))
4944 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4946 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4948 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4955 if (i386_record_modrm (&ir
))
4959 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4964 if (i386_record_lea_modrm (&ir
))
4969 case 0xd8: /* Floats. */
4977 if (i386_record_modrm (&ir
))
4979 ir
.reg
|= ((opcode
& 7) << 3);
4985 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4993 /* For fcom, ficom nothing to do. */
4999 /* For fcomp, ficomp pop FPU stack, store all. */
5000 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5027 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5028 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5029 of code, always affects st(0) register. */
5030 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5054 /* Handling fld, fild. */
5055 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5059 switch (ir
.reg
>> 4)
5062 if (record_arch_list_add_mem (addr64
, 4))
5066 if (record_arch_list_add_mem (addr64
, 8))
5072 if (record_arch_list_add_mem (addr64
, 2))
5078 switch (ir
.reg
>> 4)
5081 if (record_arch_list_add_mem (addr64
, 4))
5083 if (3 == (ir
.reg
& 7))
5085 /* For fstp m32fp. */
5086 if (i386_record_floats (gdbarch
, &ir
,
5087 I386_SAVE_FPU_REGS
))
5092 if (record_arch_list_add_mem (addr64
, 4))
5094 if ((3 == (ir
.reg
& 7))
5095 || (5 == (ir
.reg
& 7))
5096 || (7 == (ir
.reg
& 7)))
5098 /* For fstp insn. */
5099 if (i386_record_floats (gdbarch
, &ir
,
5100 I386_SAVE_FPU_REGS
))
5105 if (record_arch_list_add_mem (addr64
, 8))
5107 if (3 == (ir
.reg
& 7))
5109 /* For fstp m64fp. */
5110 if (i386_record_floats (gdbarch
, &ir
,
5111 I386_SAVE_FPU_REGS
))
5116 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5118 /* For fistp, fbld, fild, fbstp. */
5119 if (i386_record_floats (gdbarch
, &ir
,
5120 I386_SAVE_FPU_REGS
))
5125 if (record_arch_list_add_mem (addr64
, 2))
5134 if (i386_record_floats (gdbarch
, &ir
,
5135 I386_SAVE_FPU_ENV_REG_STACK
))
5140 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5145 if (i386_record_floats (gdbarch
, &ir
,
5146 I386_SAVE_FPU_ENV_REG_STACK
))
5152 if (record_arch_list_add_mem (addr64
, 28))
5157 if (record_arch_list_add_mem (addr64
, 14))
5163 if (record_arch_list_add_mem (addr64
, 2))
5165 /* Insn fstp, fbstp. */
5166 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5171 if (record_arch_list_add_mem (addr64
, 10))
5177 if (record_arch_list_add_mem (addr64
, 28))
5183 if (record_arch_list_add_mem (addr64
, 14))
5187 if (record_arch_list_add_mem (addr64
, 80))
5190 if (i386_record_floats (gdbarch
, &ir
,
5191 I386_SAVE_FPU_ENV_REG_STACK
))
5195 if (record_arch_list_add_mem (addr64
, 8))
5198 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5203 opcode
= opcode
<< 8 | ir
.modrm
;
5208 /* Opcode is an extension of modR/M byte. */
5214 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5218 if (0x0c == (ir
.modrm
>> 4))
5220 if ((ir
.modrm
& 0x0f) <= 7)
5222 if (i386_record_floats (gdbarch
, &ir
,
5223 I386_SAVE_FPU_REGS
))
5228 if (i386_record_floats (gdbarch
, &ir
,
5229 I387_ST0_REGNUM (tdep
)))
5231 /* If only st(0) is changing, then we have already
5233 if ((ir
.modrm
& 0x0f) - 0x08)
5235 if (i386_record_floats (gdbarch
, &ir
,
5236 I387_ST0_REGNUM (tdep
) +
5237 ((ir
.modrm
& 0x0f) - 0x08)))
5255 if (i386_record_floats (gdbarch
, &ir
,
5256 I387_ST0_REGNUM (tdep
)))
5274 if (i386_record_floats (gdbarch
, &ir
,
5275 I386_SAVE_FPU_REGS
))
5279 if (i386_record_floats (gdbarch
, &ir
,
5280 I387_ST0_REGNUM (tdep
)))
5282 if (i386_record_floats (gdbarch
, &ir
,
5283 I387_ST0_REGNUM (tdep
) + 1))
5290 if (0xe9 == ir
.modrm
)
5292 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5295 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5297 if (i386_record_floats (gdbarch
, &ir
,
5298 I387_ST0_REGNUM (tdep
)))
5300 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5302 if (i386_record_floats (gdbarch
, &ir
,
5303 I387_ST0_REGNUM (tdep
) +
5307 else if ((ir
.modrm
& 0x0f) - 0x08)
5309 if (i386_record_floats (gdbarch
, &ir
,
5310 I387_ST0_REGNUM (tdep
) +
5311 ((ir
.modrm
& 0x0f) - 0x08)))
5317 if (0xe3 == ir
.modrm
)
5319 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5322 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5324 if (i386_record_floats (gdbarch
, &ir
,
5325 I387_ST0_REGNUM (tdep
)))
5327 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5329 if (i386_record_floats (gdbarch
, &ir
,
5330 I387_ST0_REGNUM (tdep
) +
5334 else if ((ir
.modrm
& 0x0f) - 0x08)
5336 if (i386_record_floats (gdbarch
, &ir
,
5337 I387_ST0_REGNUM (tdep
) +
5338 ((ir
.modrm
& 0x0f) - 0x08)))
5344 if ((0x0c == ir
.modrm
>> 4)
5345 || (0x0d == ir
.modrm
>> 4)
5346 || (0x0f == ir
.modrm
>> 4))
5348 if ((ir
.modrm
& 0x0f) <= 7)
5350 if (i386_record_floats (gdbarch
, &ir
,
5351 I387_ST0_REGNUM (tdep
) +
5357 if (i386_record_floats (gdbarch
, &ir
,
5358 I387_ST0_REGNUM (tdep
) +
5359 ((ir
.modrm
& 0x0f) - 0x08)))
5365 if (0x0c == ir
.modrm
>> 4)
5367 if (i386_record_floats (gdbarch
, &ir
,
5368 I387_FTAG_REGNUM (tdep
)))
5371 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5373 if ((ir
.modrm
& 0x0f) <= 7)
5375 if (i386_record_floats (gdbarch
, &ir
,
5376 I387_ST0_REGNUM (tdep
) +
5382 if (i386_record_floats (gdbarch
, &ir
,
5383 I386_SAVE_FPU_REGS
))
5389 if ((0x0c == ir
.modrm
>> 4)
5390 || (0x0e == ir
.modrm
>> 4)
5391 || (0x0f == ir
.modrm
>> 4)
5392 || (0xd9 == ir
.modrm
))
5394 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5399 if (0xe0 == ir
.modrm
)
5401 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5404 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5406 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5414 case 0xa4: /* movsS */
5416 case 0xaa: /* stosS */
5418 case 0x6c: /* insS */
5420 regcache_raw_read_unsigned (ir
.regcache
,
5421 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5427 if ((opcode
& 1) == 0)
5430 ir
.ot
= ir
.dflag
+ OT_WORD
;
5431 regcache_raw_read_unsigned (ir
.regcache
,
5432 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5435 regcache_raw_read_unsigned (ir
.regcache
,
5436 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5438 regcache_raw_read_unsigned (ir
.regcache
,
5439 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5441 if (ir
.aflag
&& (es
!= ds
))
5443 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5444 if (record_memory_query
)
5448 target_terminal_ours ();
5450 Process record ignores the memory change of instruction at address %s\n\
5451 because it can't get the value of the segment register.\n\
5452 Do you want to stop the program?"),
5453 paddress (gdbarch
, ir
.orig_addr
));
5454 target_terminal_inferior ();
5461 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5465 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5466 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5467 if (opcode
== 0xa4 || opcode
== 0xa5)
5468 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5474 case 0xa6: /* cmpsS */
5476 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5477 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5478 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5483 case 0xac: /* lodsS */
5485 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5486 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5487 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5492 case 0xae: /* scasS */
5494 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5495 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5500 case 0x6e: /* outsS */
5502 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5503 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5505 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5508 case 0xe4: /* port I/O */
5512 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5523 case 0xc2: /* ret im */
5524 case 0xc3: /* ret */
5525 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5526 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5529 case 0xca: /* lret im */
5530 case 0xcb: /* lret */
5531 case 0xcf: /* iret */
5532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5537 case 0xe8: /* call im */
5538 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5540 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5544 case 0x9a: /* lcall im */
5545 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5550 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5551 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5555 case 0xe9: /* jmp im */
5556 case 0xea: /* ljmp im */
5557 case 0xeb: /* jmp Jb */
5558 case 0x70: /* jcc Jb */
5574 case 0x0f80: /* jcc Jv */
5592 case 0x0f90: /* setcc Gv */
5608 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5610 if (i386_record_modrm (&ir
))
5613 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5617 if (i386_record_lea_modrm (&ir
))
5622 case 0x0f40: /* cmov Gv, Ev */
5638 if (i386_record_modrm (&ir
))
5641 if (ir
.dflag
== OT_BYTE
)
5643 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5647 case 0x9c: /* pushf */
5648 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5649 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5651 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5655 case 0x9d: /* popf */
5656 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5657 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5660 case 0x9e: /* sahf */
5661 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5667 case 0xf5: /* cmc */
5668 case 0xf8: /* clc */
5669 case 0xf9: /* stc */
5670 case 0xfc: /* cld */
5671 case 0xfd: /* std */
5672 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5675 case 0x9f: /* lahf */
5676 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5685 /* bit operations */
5686 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5687 ir
.ot
= ir
.dflag
+ OT_WORD
;
5688 if (i386_record_modrm (&ir
))
5693 opcode
= opcode
<< 8 | ir
.modrm
;
5699 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5702 if (i386_record_lea_modrm (&ir
))
5706 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5709 case 0x0fa3: /* bt Gv, Ev */
5710 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5713 case 0x0fab: /* bts */
5714 case 0x0fb3: /* btr */
5715 case 0x0fbb: /* btc */
5716 ir
.ot
= ir
.dflag
+ OT_WORD
;
5717 if (i386_record_modrm (&ir
))
5720 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5724 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5726 regcache_raw_read_unsigned (ir
.regcache
,
5727 ir
.regmap
[ir
.reg
| rex_r
],
5732 addr64
+= ((int16_t) addr
>> 4) << 4;
5735 addr64
+= ((int32_t) addr
>> 5) << 5;
5738 addr64
+= ((int64_t) addr
>> 6) << 6;
5741 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5743 if (i386_record_lea_modrm (&ir
))
5746 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5749 case 0x0fbc: /* bsf */
5750 case 0x0fbd: /* bsr */
5751 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5752 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5756 case 0x27: /* daa */
5757 case 0x2f: /* das */
5758 case 0x37: /* aaa */
5759 case 0x3f: /* aas */
5760 case 0xd4: /* aam */
5761 case 0xd5: /* aad */
5762 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5772 case 0x90: /* nop */
5773 if (prefixes
& PREFIX_LOCK
)
5780 case 0x9b: /* fwait */
5781 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5784 printf_unfiltered (_("Process record: error reading memory at "
5785 "addr 0x%s len = 1.\n"),
5786 paddress (gdbarch
, ir
.addr
));
5789 opcode
= (uint32_t) opcode8
;
5795 case 0xcc: /* int3 */
5796 printf_unfiltered (_("Process record does not support instruction "
5803 case 0xcd: /* int */
5807 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5810 printf_unfiltered (_("Process record: error reading memory "
5811 "at addr %s len = 1.\n"),
5812 paddress (gdbarch
, ir
.addr
));
5816 if (interrupt
!= 0x80
5817 || tdep
->i386_intx80_record
== NULL
)
5819 printf_unfiltered (_("Process record does not support "
5820 "instruction int 0x%02x.\n"),
5825 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5832 case 0xce: /* into */
5833 printf_unfiltered (_("Process record does not support "
5834 "instruction into.\n"));
5839 case 0xfa: /* cli */
5840 case 0xfb: /* sti */
5843 case 0x62: /* bound */
5844 printf_unfiltered (_("Process record does not support "
5845 "instruction bound.\n"));
5850 case 0x0fc8: /* bswap reg */
5858 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5861 case 0xd6: /* salc */
5862 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5867 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5868 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5871 case 0xe0: /* loopnz */
5872 case 0xe1: /* loopz */
5873 case 0xe2: /* loop */
5874 case 0xe3: /* jecxz */
5875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5876 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5879 case 0x0f30: /* wrmsr */
5880 printf_unfiltered (_("Process record does not support "
5881 "instruction wrmsr.\n"));
5886 case 0x0f32: /* rdmsr */
5887 printf_unfiltered (_("Process record does not support "
5888 "instruction rdmsr.\n"));
5893 case 0x0f31: /* rdtsc */
5894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5895 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5898 case 0x0f34: /* sysenter */
5901 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5906 if (tdep
->i386_sysenter_record
== NULL
)
5908 printf_unfiltered (_("Process record does not support "
5909 "instruction sysenter.\n"));
5913 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5919 case 0x0f35: /* sysexit */
5920 printf_unfiltered (_("Process record does not support "
5921 "instruction sysexit.\n"));
5926 case 0x0f05: /* syscall */
5929 if (tdep
->i386_syscall_record
== NULL
)
5931 printf_unfiltered (_("Process record does not support "
5932 "instruction syscall.\n"));
5936 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5942 case 0x0f07: /* sysret */
5943 printf_unfiltered (_("Process record does not support "
5944 "instruction sysret.\n"));
5949 case 0x0fa2: /* cpuid */
5950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5956 case 0xf4: /* hlt */
5957 printf_unfiltered (_("Process record does not support "
5958 "instruction hlt.\n"));
5964 if (i386_record_modrm (&ir
))
5971 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5975 if (i386_record_lea_modrm (&ir
))
5984 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5988 opcode
= opcode
<< 8 | ir
.modrm
;
5995 if (i386_record_modrm (&ir
))
6006 opcode
= opcode
<< 8 | ir
.modrm
;
6009 if (ir
.override
>= 0)
6011 if (record_memory_query
)
6015 target_terminal_ours ();
6017 Process record ignores the memory change of instruction at address %s\n\
6018 because it can't get the value of the segment register.\n\
6019 Do you want to stop the program?"),
6020 paddress (gdbarch
, ir
.orig_addr
));
6021 target_terminal_inferior ();
6028 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6030 if (record_arch_list_add_mem (addr64
, 2))
6033 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6035 if (record_arch_list_add_mem (addr64
, 8))
6040 if (record_arch_list_add_mem (addr64
, 4))
6051 case 0: /* monitor */
6054 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6058 opcode
= opcode
<< 8 | ir
.modrm
;
6066 if (ir
.override
>= 0)
6068 if (record_memory_query
)
6072 target_terminal_ours ();
6074 Process record ignores the memory change of instruction at address %s\n\
6075 because it can't get the value of the segment register.\n\
6076 Do you want to stop the program?"),
6077 paddress (gdbarch
, ir
.orig_addr
));
6078 target_terminal_inferior ();
6087 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6089 if (record_arch_list_add_mem (addr64
, 2))
6092 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6094 if (record_arch_list_add_mem (addr64
, 8))
6099 if (record_arch_list_add_mem (addr64
, 4))
6111 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6112 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6116 else if (ir
.rm
== 1)
6123 opcode
= opcode
<< 8 | ir
.modrm
;
6130 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6136 if (i386_record_lea_modrm (&ir
))
6139 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6144 case 7: /* invlpg */
6147 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6152 opcode
= opcode
<< 8 | ir
.modrm
;
6157 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6161 opcode
= opcode
<< 8 | ir
.modrm
;
6167 case 0x0f08: /* invd */
6168 case 0x0f09: /* wbinvd */
6171 case 0x63: /* arpl */
6172 if (i386_record_modrm (&ir
))
6174 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6176 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6177 ? (ir
.reg
| rex_r
) : ir
.rm
);
6181 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6182 if (i386_record_lea_modrm (&ir
))
6185 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6189 case 0x0f02: /* lar */
6190 case 0x0f03: /* lsl */
6191 if (i386_record_modrm (&ir
))
6193 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6198 if (i386_record_modrm (&ir
))
6200 if (ir
.mod
== 3 && ir
.reg
== 3)
6203 opcode
= opcode
<< 8 | ir
.modrm
;
6215 /* nop (multi byte) */
6218 case 0x0f20: /* mov reg, crN */
6219 case 0x0f22: /* mov crN, reg */
6220 if (i386_record_modrm (&ir
))
6222 if ((ir
.modrm
& 0xc0) != 0xc0)
6225 opcode
= opcode
<< 8 | ir
.modrm
;
6236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6238 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6242 opcode
= opcode
<< 8 | ir
.modrm
;
6248 case 0x0f21: /* mov reg, drN */
6249 case 0x0f23: /* mov drN, reg */
6250 if (i386_record_modrm (&ir
))
6252 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6253 || ir
.reg
== 5 || ir
.reg
>= 8)
6256 opcode
= opcode
<< 8 | ir
.modrm
;
6260 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6262 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6265 case 0x0f06: /* clts */
6266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6269 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6271 case 0x0f0d: /* 3DNow! prefetch */
6274 case 0x0f0e: /* 3DNow! femms */
6275 case 0x0f77: /* emms */
6276 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6278 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6281 case 0x0f0f: /* 3DNow! data */
6282 if (i386_record_modrm (&ir
))
6284 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6286 printf_unfiltered (_("Process record: error reading memory at "
6287 "addr %s len = 1.\n"),
6288 paddress (gdbarch
, ir
.addr
));
6294 case 0x0c: /* 3DNow! pi2fw */
6295 case 0x0d: /* 3DNow! pi2fd */
6296 case 0x1c: /* 3DNow! pf2iw */
6297 case 0x1d: /* 3DNow! pf2id */
6298 case 0x8a: /* 3DNow! pfnacc */
6299 case 0x8e: /* 3DNow! pfpnacc */
6300 case 0x90: /* 3DNow! pfcmpge */
6301 case 0x94: /* 3DNow! pfmin */
6302 case 0x96: /* 3DNow! pfrcp */
6303 case 0x97: /* 3DNow! pfrsqrt */
6304 case 0x9a: /* 3DNow! pfsub */
6305 case 0x9e: /* 3DNow! pfadd */
6306 case 0xa0: /* 3DNow! pfcmpgt */
6307 case 0xa4: /* 3DNow! pfmax */
6308 case 0xa6: /* 3DNow! pfrcpit1 */
6309 case 0xa7: /* 3DNow! pfrsqit1 */
6310 case 0xaa: /* 3DNow! pfsubr */
6311 case 0xae: /* 3DNow! pfacc */
6312 case 0xb0: /* 3DNow! pfcmpeq */
6313 case 0xb4: /* 3DNow! pfmul */
6314 case 0xb6: /* 3DNow! pfrcpit2 */
6315 case 0xb7: /* 3DNow! pmulhrw */
6316 case 0xbb: /* 3DNow! pswapd */
6317 case 0xbf: /* 3DNow! pavgusb */
6318 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6319 goto no_support_3dnow_data
;
6320 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6324 no_support_3dnow_data
:
6325 opcode
= (opcode
<< 8) | opcode8
;
6331 case 0x0faa: /* rsm */
6332 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6333 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6334 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6336 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6339 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6344 if (i386_record_modrm (&ir
))
6348 case 0: /* fxsave */
6352 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6353 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6355 if (record_arch_list_add_mem (tmpu64
, 512))
6360 case 1: /* fxrstor */
6364 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6366 for (i
= I387_MM0_REGNUM (tdep
);
6367 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6368 record_arch_list_add_reg (ir
.regcache
, i
);
6370 for (i
= I387_XMM0_REGNUM (tdep
);
6371 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6372 record_arch_list_add_reg (ir
.regcache
, i
);
6374 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6375 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6377 for (i
= I387_ST0_REGNUM (tdep
);
6378 i386_fp_regnum_p (gdbarch
, i
); i
++)
6379 record_arch_list_add_reg (ir
.regcache
, i
);
6381 for (i
= I387_FCTRL_REGNUM (tdep
);
6382 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6383 record_arch_list_add_reg (ir
.regcache
, i
);
6387 case 2: /* ldmxcsr */
6388 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6390 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6393 case 3: /* stmxcsr */
6395 if (i386_record_lea_modrm (&ir
))
6399 case 5: /* lfence */
6400 case 6: /* mfence */
6401 case 7: /* sfence clflush */
6405 opcode
= (opcode
<< 8) | ir
.modrm
;
6411 case 0x0fc3: /* movnti */
6412 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6413 if (i386_record_modrm (&ir
))
6418 if (i386_record_lea_modrm (&ir
))
6422 /* Add prefix to opcode. */
6549 reswitch_prefix_add
:
6557 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6559 printf_unfiltered (_("Process record: error reading memory at "
6560 "addr %s len = 1.\n"),
6561 paddress (gdbarch
, ir
.addr
));
6565 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6566 goto reswitch_prefix_add
;
6569 case 0x0f10: /* movups */
6570 case 0x660f10: /* movupd */
6571 case 0xf30f10: /* movss */
6572 case 0xf20f10: /* movsd */
6573 case 0x0f12: /* movlps */
6574 case 0x660f12: /* movlpd */
6575 case 0xf30f12: /* movsldup */
6576 case 0xf20f12: /* movddup */
6577 case 0x0f14: /* unpcklps */
6578 case 0x660f14: /* unpcklpd */
6579 case 0x0f15: /* unpckhps */
6580 case 0x660f15: /* unpckhpd */
6581 case 0x0f16: /* movhps */
6582 case 0x660f16: /* movhpd */
6583 case 0xf30f16: /* movshdup */
6584 case 0x0f28: /* movaps */
6585 case 0x660f28: /* movapd */
6586 case 0x0f2a: /* cvtpi2ps */
6587 case 0x660f2a: /* cvtpi2pd */
6588 case 0xf30f2a: /* cvtsi2ss */
6589 case 0xf20f2a: /* cvtsi2sd */
6590 case 0x0f2c: /* cvttps2pi */
6591 case 0x660f2c: /* cvttpd2pi */
6592 case 0x0f2d: /* cvtps2pi */
6593 case 0x660f2d: /* cvtpd2pi */
6594 case 0x660f3800: /* pshufb */
6595 case 0x660f3801: /* phaddw */
6596 case 0x660f3802: /* phaddd */
6597 case 0x660f3803: /* phaddsw */
6598 case 0x660f3804: /* pmaddubsw */
6599 case 0x660f3805: /* phsubw */
6600 case 0x660f3806: /* phsubd */
6601 case 0x660f3807: /* phsubsw */
6602 case 0x660f3808: /* psignb */
6603 case 0x660f3809: /* psignw */
6604 case 0x660f380a: /* psignd */
6605 case 0x660f380b: /* pmulhrsw */
6606 case 0x660f3810: /* pblendvb */
6607 case 0x660f3814: /* blendvps */
6608 case 0x660f3815: /* blendvpd */
6609 case 0x660f381c: /* pabsb */
6610 case 0x660f381d: /* pabsw */
6611 case 0x660f381e: /* pabsd */
6612 case 0x660f3820: /* pmovsxbw */
6613 case 0x660f3821: /* pmovsxbd */
6614 case 0x660f3822: /* pmovsxbq */
6615 case 0x660f3823: /* pmovsxwd */
6616 case 0x660f3824: /* pmovsxwq */
6617 case 0x660f3825: /* pmovsxdq */
6618 case 0x660f3828: /* pmuldq */
6619 case 0x660f3829: /* pcmpeqq */
6620 case 0x660f382a: /* movntdqa */
6621 case 0x660f3a08: /* roundps */
6622 case 0x660f3a09: /* roundpd */
6623 case 0x660f3a0a: /* roundss */
6624 case 0x660f3a0b: /* roundsd */
6625 case 0x660f3a0c: /* blendps */
6626 case 0x660f3a0d: /* blendpd */
6627 case 0x660f3a0e: /* pblendw */
6628 case 0x660f3a0f: /* palignr */
6629 case 0x660f3a20: /* pinsrb */
6630 case 0x660f3a21: /* insertps */
6631 case 0x660f3a22: /* pinsrd pinsrq */
6632 case 0x660f3a40: /* dpps */
6633 case 0x660f3a41: /* dppd */
6634 case 0x660f3a42: /* mpsadbw */
6635 case 0x660f3a60: /* pcmpestrm */
6636 case 0x660f3a61: /* pcmpestri */
6637 case 0x660f3a62: /* pcmpistrm */
6638 case 0x660f3a63: /* pcmpistri */
6639 case 0x0f51: /* sqrtps */
6640 case 0x660f51: /* sqrtpd */
6641 case 0xf20f51: /* sqrtsd */
6642 case 0xf30f51: /* sqrtss */
6643 case 0x0f52: /* rsqrtps */
6644 case 0xf30f52: /* rsqrtss */
6645 case 0x0f53: /* rcpps */
6646 case 0xf30f53: /* rcpss */
6647 case 0x0f54: /* andps */
6648 case 0x660f54: /* andpd */
6649 case 0x0f55: /* andnps */
6650 case 0x660f55: /* andnpd */
6651 case 0x0f56: /* orps */
6652 case 0x660f56: /* orpd */
6653 case 0x0f57: /* xorps */
6654 case 0x660f57: /* xorpd */
6655 case 0x0f58: /* addps */
6656 case 0x660f58: /* addpd */
6657 case 0xf20f58: /* addsd */
6658 case 0xf30f58: /* addss */
6659 case 0x0f59: /* mulps */
6660 case 0x660f59: /* mulpd */
6661 case 0xf20f59: /* mulsd */
6662 case 0xf30f59: /* mulss */
6663 case 0x0f5a: /* cvtps2pd */
6664 case 0x660f5a: /* cvtpd2ps */
6665 case 0xf20f5a: /* cvtsd2ss */
6666 case 0xf30f5a: /* cvtss2sd */
6667 case 0x0f5b: /* cvtdq2ps */
6668 case 0x660f5b: /* cvtps2dq */
6669 case 0xf30f5b: /* cvttps2dq */
6670 case 0x0f5c: /* subps */
6671 case 0x660f5c: /* subpd */
6672 case 0xf20f5c: /* subsd */
6673 case 0xf30f5c: /* subss */
6674 case 0x0f5d: /* minps */
6675 case 0x660f5d: /* minpd */
6676 case 0xf20f5d: /* minsd */
6677 case 0xf30f5d: /* minss */
6678 case 0x0f5e: /* divps */
6679 case 0x660f5e: /* divpd */
6680 case 0xf20f5e: /* divsd */
6681 case 0xf30f5e: /* divss */
6682 case 0x0f5f: /* maxps */
6683 case 0x660f5f: /* maxpd */
6684 case 0xf20f5f: /* maxsd */
6685 case 0xf30f5f: /* maxss */
6686 case 0x660f60: /* punpcklbw */
6687 case 0x660f61: /* punpcklwd */
6688 case 0x660f62: /* punpckldq */
6689 case 0x660f63: /* packsswb */
6690 case 0x660f64: /* pcmpgtb */
6691 case 0x660f65: /* pcmpgtw */
6692 case 0x660f66: /* pcmpgtd */
6693 case 0x660f67: /* packuswb */
6694 case 0x660f68: /* punpckhbw */
6695 case 0x660f69: /* punpckhwd */
6696 case 0x660f6a: /* punpckhdq */
6697 case 0x660f6b: /* packssdw */
6698 case 0x660f6c: /* punpcklqdq */
6699 case 0x660f6d: /* punpckhqdq */
6700 case 0x660f6e: /* movd */
6701 case 0x660f6f: /* movdqa */
6702 case 0xf30f6f: /* movdqu */
6703 case 0x660f70: /* pshufd */
6704 case 0xf20f70: /* pshuflw */
6705 case 0xf30f70: /* pshufhw */
6706 case 0x660f74: /* pcmpeqb */
6707 case 0x660f75: /* pcmpeqw */
6708 case 0x660f76: /* pcmpeqd */
6709 case 0x660f7c: /* haddpd */
6710 case 0xf20f7c: /* haddps */
6711 case 0x660f7d: /* hsubpd */
6712 case 0xf20f7d: /* hsubps */
6713 case 0xf30f7e: /* movq */
6714 case 0x0fc2: /* cmpps */
6715 case 0x660fc2: /* cmppd */
6716 case 0xf20fc2: /* cmpsd */
6717 case 0xf30fc2: /* cmpss */
6718 case 0x660fc4: /* pinsrw */
6719 case 0x0fc6: /* shufps */
6720 case 0x660fc6: /* shufpd */
6721 case 0x660fd0: /* addsubpd */
6722 case 0xf20fd0: /* addsubps */
6723 case 0x660fd1: /* psrlw */
6724 case 0x660fd2: /* psrld */
6725 case 0x660fd3: /* psrlq */
6726 case 0x660fd4: /* paddq */
6727 case 0x660fd5: /* pmullw */
6728 case 0xf30fd6: /* movq2dq */
6729 case 0x660fd8: /* psubusb */
6730 case 0x660fd9: /* psubusw */
6731 case 0x660fda: /* pminub */
6732 case 0x660fdb: /* pand */
6733 case 0x660fdc: /* paddusb */
6734 case 0x660fdd: /* paddusw */
6735 case 0x660fde: /* pmaxub */
6736 case 0x660fdf: /* pandn */
6737 case 0x660fe0: /* pavgb */
6738 case 0x660fe1: /* psraw */
6739 case 0x660fe2: /* psrad */
6740 case 0x660fe3: /* pavgw */
6741 case 0x660fe4: /* pmulhuw */
6742 case 0x660fe5: /* pmulhw */
6743 case 0x660fe6: /* cvttpd2dq */
6744 case 0xf20fe6: /* cvtpd2dq */
6745 case 0xf30fe6: /* cvtdq2pd */
6746 case 0x660fe8: /* psubsb */
6747 case 0x660fe9: /* psubsw */
6748 case 0x660fea: /* pminsw */
6749 case 0x660feb: /* por */
6750 case 0x660fec: /* paddsb */
6751 case 0x660fed: /* paddsw */
6752 case 0x660fee: /* pmaxsw */
6753 case 0x660fef: /* pxor */
6754 case 0xf20ff0: /* lddqu */
6755 case 0x660ff1: /* psllw */
6756 case 0x660ff2: /* pslld */
6757 case 0x660ff3: /* psllq */
6758 case 0x660ff4: /* pmuludq */
6759 case 0x660ff5: /* pmaddwd */
6760 case 0x660ff6: /* psadbw */
6761 case 0x660ff8: /* psubb */
6762 case 0x660ff9: /* psubw */
6763 case 0x660ffa: /* psubd */
6764 case 0x660ffb: /* psubq */
6765 case 0x660ffc: /* paddb */
6766 case 0x660ffd: /* paddw */
6767 case 0x660ffe: /* paddd */
6768 if (i386_record_modrm (&ir
))
6771 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6773 record_arch_list_add_reg (ir
.regcache
,
6774 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6775 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6776 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6779 case 0x0f11: /* movups */
6780 case 0x660f11: /* movupd */
6781 case 0xf30f11: /* movss */
6782 case 0xf20f11: /* movsd */
6783 case 0x0f13: /* movlps */
6784 case 0x660f13: /* movlpd */
6785 case 0x0f17: /* movhps */
6786 case 0x660f17: /* movhpd */
6787 case 0x0f29: /* movaps */
6788 case 0x660f29: /* movapd */
6789 case 0x660f3a14: /* pextrb */
6790 case 0x660f3a15: /* pextrw */
6791 case 0x660f3a16: /* pextrd pextrq */
6792 case 0x660f3a17: /* extractps */
6793 case 0x660f7f: /* movdqa */
6794 case 0xf30f7f: /* movdqu */
6795 if (i386_record_modrm (&ir
))
6799 if (opcode
== 0x0f13 || opcode
== 0x660f13
6800 || opcode
== 0x0f17 || opcode
== 0x660f17)
6803 if (!i386_xmm_regnum_p (gdbarch
,
6804 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6806 record_arch_list_add_reg (ir
.regcache
,
6807 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6829 if (i386_record_lea_modrm (&ir
))
6834 case 0x0f2b: /* movntps */
6835 case 0x660f2b: /* movntpd */
6836 case 0x0fe7: /* movntq */
6837 case 0x660fe7: /* movntdq */
6840 if (opcode
== 0x0fe7)
6844 if (i386_record_lea_modrm (&ir
))
6848 case 0xf30f2c: /* cvttss2si */
6849 case 0xf20f2c: /* cvttsd2si */
6850 case 0xf30f2d: /* cvtss2si */
6851 case 0xf20f2d: /* cvtsd2si */
6852 case 0xf20f38f0: /* crc32 */
6853 case 0xf20f38f1: /* crc32 */
6854 case 0x0f50: /* movmskps */
6855 case 0x660f50: /* movmskpd */
6856 case 0x0fc5: /* pextrw */
6857 case 0x660fc5: /* pextrw */
6858 case 0x0fd7: /* pmovmskb */
6859 case 0x660fd7: /* pmovmskb */
6860 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6863 case 0x0f3800: /* pshufb */
6864 case 0x0f3801: /* phaddw */
6865 case 0x0f3802: /* phaddd */
6866 case 0x0f3803: /* phaddsw */
6867 case 0x0f3804: /* pmaddubsw */
6868 case 0x0f3805: /* phsubw */
6869 case 0x0f3806: /* phsubd */
6870 case 0x0f3807: /* phsubsw */
6871 case 0x0f3808: /* psignb */
6872 case 0x0f3809: /* psignw */
6873 case 0x0f380a: /* psignd */
6874 case 0x0f380b: /* pmulhrsw */
6875 case 0x0f381c: /* pabsb */
6876 case 0x0f381d: /* pabsw */
6877 case 0x0f381e: /* pabsd */
6878 case 0x0f382b: /* packusdw */
6879 case 0x0f3830: /* pmovzxbw */
6880 case 0x0f3831: /* pmovzxbd */
6881 case 0x0f3832: /* pmovzxbq */
6882 case 0x0f3833: /* pmovzxwd */
6883 case 0x0f3834: /* pmovzxwq */
6884 case 0x0f3835: /* pmovzxdq */
6885 case 0x0f3837: /* pcmpgtq */
6886 case 0x0f3838: /* pminsb */
6887 case 0x0f3839: /* pminsd */
6888 case 0x0f383a: /* pminuw */
6889 case 0x0f383b: /* pminud */
6890 case 0x0f383c: /* pmaxsb */
6891 case 0x0f383d: /* pmaxsd */
6892 case 0x0f383e: /* pmaxuw */
6893 case 0x0f383f: /* pmaxud */
6894 case 0x0f3840: /* pmulld */
6895 case 0x0f3841: /* phminposuw */
6896 case 0x0f3a0f: /* palignr */
6897 case 0x0f60: /* punpcklbw */
6898 case 0x0f61: /* punpcklwd */
6899 case 0x0f62: /* punpckldq */
6900 case 0x0f63: /* packsswb */
6901 case 0x0f64: /* pcmpgtb */
6902 case 0x0f65: /* pcmpgtw */
6903 case 0x0f66: /* pcmpgtd */
6904 case 0x0f67: /* packuswb */
6905 case 0x0f68: /* punpckhbw */
6906 case 0x0f69: /* punpckhwd */
6907 case 0x0f6a: /* punpckhdq */
6908 case 0x0f6b: /* packssdw */
6909 case 0x0f6e: /* movd */
6910 case 0x0f6f: /* movq */
6911 case 0x0f70: /* pshufw */
6912 case 0x0f74: /* pcmpeqb */
6913 case 0x0f75: /* pcmpeqw */
6914 case 0x0f76: /* pcmpeqd */
6915 case 0x0fc4: /* pinsrw */
6916 case 0x0fd1: /* psrlw */
6917 case 0x0fd2: /* psrld */
6918 case 0x0fd3: /* psrlq */
6919 case 0x0fd4: /* paddq */
6920 case 0x0fd5: /* pmullw */
6921 case 0xf20fd6: /* movdq2q */
6922 case 0x0fd8: /* psubusb */
6923 case 0x0fd9: /* psubusw */
6924 case 0x0fda: /* pminub */
6925 case 0x0fdb: /* pand */
6926 case 0x0fdc: /* paddusb */
6927 case 0x0fdd: /* paddusw */
6928 case 0x0fde: /* pmaxub */
6929 case 0x0fdf: /* pandn */
6930 case 0x0fe0: /* pavgb */
6931 case 0x0fe1: /* psraw */
6932 case 0x0fe2: /* psrad */
6933 case 0x0fe3: /* pavgw */
6934 case 0x0fe4: /* pmulhuw */
6935 case 0x0fe5: /* pmulhw */
6936 case 0x0fe8: /* psubsb */
6937 case 0x0fe9: /* psubsw */
6938 case 0x0fea: /* pminsw */
6939 case 0x0feb: /* por */
6940 case 0x0fec: /* paddsb */
6941 case 0x0fed: /* paddsw */
6942 case 0x0fee: /* pmaxsw */
6943 case 0x0fef: /* pxor */
6944 case 0x0ff1: /* psllw */
6945 case 0x0ff2: /* pslld */
6946 case 0x0ff3: /* psllq */
6947 case 0x0ff4: /* pmuludq */
6948 case 0x0ff5: /* pmaddwd */
6949 case 0x0ff6: /* psadbw */
6950 case 0x0ff8: /* psubb */
6951 case 0x0ff9: /* psubw */
6952 case 0x0ffa: /* psubd */
6953 case 0x0ffb: /* psubq */
6954 case 0x0ffc: /* paddb */
6955 case 0x0ffd: /* paddw */
6956 case 0x0ffe: /* paddd */
6957 if (i386_record_modrm (&ir
))
6959 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6961 record_arch_list_add_reg (ir
.regcache
,
6962 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6965 case 0x0f71: /* psllw */
6966 case 0x0f72: /* pslld */
6967 case 0x0f73: /* psllq */
6968 if (i386_record_modrm (&ir
))
6970 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6972 record_arch_list_add_reg (ir
.regcache
,
6973 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6976 case 0x660f71: /* psllw */
6977 case 0x660f72: /* pslld */
6978 case 0x660f73: /* psllq */
6979 if (i386_record_modrm (&ir
))
6982 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6984 record_arch_list_add_reg (ir
.regcache
,
6985 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6988 case 0x0f7e: /* movd */
6989 case 0x660f7e: /* movd */
6990 if (i386_record_modrm (&ir
))
6993 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7000 if (i386_record_lea_modrm (&ir
))
7005 case 0x0f7f: /* movq */
7006 if (i386_record_modrm (&ir
))
7010 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7012 record_arch_list_add_reg (ir
.regcache
,
7013 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7018 if (i386_record_lea_modrm (&ir
))
7023 case 0xf30fb8: /* popcnt */
7024 if (i386_record_modrm (&ir
))
7026 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7027 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7030 case 0x660fd6: /* movq */
7031 if (i386_record_modrm (&ir
))
7036 if (!i386_xmm_regnum_p (gdbarch
,
7037 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7039 record_arch_list_add_reg (ir
.regcache
,
7040 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7045 if (i386_record_lea_modrm (&ir
))
7050 case 0x660f3817: /* ptest */
7051 case 0x0f2e: /* ucomiss */
7052 case 0x660f2e: /* ucomisd */
7053 case 0x0f2f: /* comiss */
7054 case 0x660f2f: /* comisd */
7055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7058 case 0x0ff7: /* maskmovq */
7059 regcache_raw_read_unsigned (ir
.regcache
,
7060 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7062 if (record_arch_list_add_mem (addr
, 64))
7066 case 0x660ff7: /* maskmovdqu */
7067 regcache_raw_read_unsigned (ir
.regcache
,
7068 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7070 if (record_arch_list_add_mem (addr
, 128))
7085 /* In the future, maybe still need to deal with need_dasm. */
7086 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7087 if (record_arch_list_add_end ())
7093 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7094 "at address %s.\n"),
7095 (unsigned int) (opcode
),
7096 paddress (gdbarch
, ir
.orig_addr
));
7100 static const int i386_record_regmap
[] =
7102 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7103 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7104 0, 0, 0, 0, 0, 0, 0, 0,
7105 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7106 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7109 /* Check that the given address appears suitable for a fast
7110 tracepoint, which on x86-64 means that we need an instruction of at
7111 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7112 jump and not have to worry about program jumps to an address in the
7113 middle of the tracepoint jump. On x86, it may be possible to use
7114 4-byte jumps with a 2-byte offset to a trampoline located in the
7115 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7116 of instruction to replace, and 0 if not, plus an explanatory
7120 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7121 CORE_ADDR addr
, int *isize
, char **msg
)
7124 static struct ui_file
*gdb_null
= NULL
;
7126 /* Ask the target for the minimum instruction length supported. */
7127 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7131 /* If the target does not support the get_min_fast_tracepoint_insn_len
7132 operation, assume that fast tracepoints will always be implemented
7133 using 4-byte relative jumps on both x86 and x86-64. */
7136 else if (jumplen
== 0)
7138 /* If the target does support get_min_fast_tracepoint_insn_len but
7139 returns zero, then the IPA has not loaded yet. In this case,
7140 we optimistically assume that truncated 2-byte relative jumps
7141 will be available on x86, and compensate later if this assumption
7142 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7143 jumps will always be used. */
7144 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7147 /* Dummy file descriptor for the disassembler. */
7149 gdb_null
= ui_file_new ();
7151 /* Check for fit. */
7152 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7158 /* Return a bit of target-specific detail to add to the caller's
7159 generic failure message. */
7161 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7162 "need at least %d bytes for the jump"),
7175 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7176 struct tdesc_arch_data
*tdesc_data
)
7178 const struct target_desc
*tdesc
= tdep
->tdesc
;
7179 const struct tdesc_feature
*feature_core
;
7180 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7181 int i
, num_regs
, valid_p
;
7183 if (! tdesc_has_registers (tdesc
))
7186 /* Get core registers. */
7187 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7188 if (feature_core
== NULL
)
7191 /* Get SSE registers. */
7192 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7194 /* Try AVX registers. */
7195 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7199 /* The XCR0 bits. */
7202 /* AVX register description requires SSE register description. */
7206 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7208 /* It may have been set by OSABI initialization function. */
7209 if (tdep
->num_ymm_regs
== 0)
7211 tdep
->ymmh_register_names
= i386_ymmh_names
;
7212 tdep
->num_ymm_regs
= 8;
7213 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7216 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7217 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7218 tdep
->ymm0h_regnum
+ i
,
7219 tdep
->ymmh_register_names
[i
]);
7221 else if (feature_sse
)
7222 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7225 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7226 tdep
->num_xmm_regs
= 0;
7229 num_regs
= tdep
->num_core_regs
;
7230 for (i
= 0; i
< num_regs
; i
++)
7231 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7232 tdep
->register_names
[i
]);
7236 /* Need to include %mxcsr, so add one. */
7237 num_regs
+= tdep
->num_xmm_regs
+ 1;
7238 for (; i
< num_regs
; i
++)
7239 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7240 tdep
->register_names
[i
]);
7247 static struct gdbarch
*
7248 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7250 struct gdbarch_tdep
*tdep
;
7251 struct gdbarch
*gdbarch
;
7252 struct tdesc_arch_data
*tdesc_data
;
7253 const struct target_desc
*tdesc
;
7257 /* If there is already a candidate, use it. */
7258 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7260 return arches
->gdbarch
;
7262 /* Allocate space for the new architecture. */
7263 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7264 gdbarch
= gdbarch_alloc (&info
, tdep
);
7266 /* General-purpose registers. */
7267 tdep
->gregset
= NULL
;
7268 tdep
->gregset_reg_offset
= NULL
;
7269 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7270 tdep
->sizeof_gregset
= 0;
7272 /* Floating-point registers. */
7273 tdep
->fpregset
= NULL
;
7274 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7276 tdep
->xstateregset
= NULL
;
7278 /* The default settings include the FPU registers, the MMX registers
7279 and the SSE registers. This can be overridden for a specific ABI
7280 by adjusting the members `st0_regnum', `mm0_regnum' and
7281 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7282 will show up in the output of "info all-registers". */
7284 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7286 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7287 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7289 tdep
->jb_pc_offset
= -1;
7290 tdep
->struct_return
= pcc_struct_return
;
7291 tdep
->sigtramp_start
= 0;
7292 tdep
->sigtramp_end
= 0;
7293 tdep
->sigtramp_p
= i386_sigtramp_p
;
7294 tdep
->sigcontext_addr
= NULL
;
7295 tdep
->sc_reg_offset
= NULL
;
7296 tdep
->sc_pc_offset
= -1;
7297 tdep
->sc_sp_offset
= -1;
7299 tdep
->xsave_xcr0_offset
= -1;
7301 tdep
->record_regmap
= i386_record_regmap
;
7303 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7305 /* The format used for `long double' on almost all i386 targets is
7306 the i387 extended floating-point format. In fact, of all targets
7307 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7308 on having a `long double' that's not `long' at all. */
7309 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7311 /* Although the i387 extended floating-point has only 80 significant
7312 bits, a `long double' actually takes up 96, probably to enforce
7314 set_gdbarch_long_double_bit (gdbarch
, 96);
7316 /* Register numbers of various important registers. */
7317 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7318 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7319 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7320 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7322 /* NOTE: kettenis/20040418: GCC does have two possible register
7323 numbering schemes on the i386: dbx and SVR4. These schemes
7324 differ in how they number %ebp, %esp, %eflags, and the
7325 floating-point registers, and are implemented by the arrays
7326 dbx_register_map[] and svr4_dbx_register_map in
7327 gcc/config/i386.c. GCC also defines a third numbering scheme in
7328 gcc/config/i386.c, which it designates as the "default" register
7329 map used in 64bit mode. This last register numbering scheme is
7330 implemented in dbx64_register_map, and is used for AMD64; see
7333 Currently, each GCC i386 target always uses the same register
7334 numbering scheme across all its supported debugging formats
7335 i.e. SDB (COFF), stabs and DWARF 2. This is because
7336 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7337 DBX_REGISTER_NUMBER macro which is defined by each target's
7338 respective config header in a manner independent of the requested
7339 output debugging format.
7341 This does not match the arrangement below, which presumes that
7342 the SDB and stabs numbering schemes differ from the DWARF and
7343 DWARF 2 ones. The reason for this arrangement is that it is
7344 likely to get the numbering scheme for the target's
7345 default/native debug format right. For targets where GCC is the
7346 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7347 targets where the native toolchain uses a different numbering
7348 scheme for a particular debug format (stabs-in-ELF on Solaris)
7349 the defaults below will have to be overridden, like
7350 i386_elf_init_abi() does. */
7352 /* Use the dbx register numbering scheme for stabs and COFF. */
7353 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7354 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7356 /* Use the SVR4 register numbering scheme for DWARF 2. */
7357 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7359 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7360 be in use on any of the supported i386 targets. */
7362 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7364 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7366 /* Call dummy code. */
7367 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7368 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7370 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7371 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7372 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7374 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7376 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7378 /* Stack grows downward. */
7379 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7381 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7382 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7383 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7385 set_gdbarch_frame_args_skip (gdbarch
, 8);
7387 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7389 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7391 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7393 /* Add the i386 register groups. */
7394 i386_add_reggroups (gdbarch
);
7395 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7397 /* Helper for function argument information. */
7398 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7400 /* Hook the function epilogue frame unwinder. This unwinder is
7401 appended to the list first, so that it supercedes the DWARF
7402 unwinder in function epilogues (where the DWARF unwinder
7403 currently fails). */
7404 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7406 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7407 to the list before the prologue-based unwinders, so that DWARF
7408 CFI info will be used if it is available. */
7409 dwarf2_append_unwinders (gdbarch
);
7411 frame_base_set_default (gdbarch
, &i386_frame_base
);
7413 /* Pseudo registers may be changed by amd64_init_abi. */
7414 set_gdbarch_pseudo_register_read_value (gdbarch
,
7415 i386_pseudo_register_read_value
);
7416 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7418 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7419 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7421 /* Override the normal target description method to make the AVX
7422 upper halves anonymous. */
7423 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7425 /* Even though the default ABI only includes general-purpose registers,
7426 floating-point registers and the SSE registers, we have to leave a
7427 gap for the upper AVX registers. */
7428 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7430 /* Get the x86 target description from INFO. */
7431 tdesc
= info
.target_desc
;
7432 if (! tdesc_has_registers (tdesc
))
7434 tdep
->tdesc
= tdesc
;
7436 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7437 tdep
->register_names
= i386_register_names
;
7439 /* No upper YMM registers. */
7440 tdep
->ymmh_register_names
= NULL
;
7441 tdep
->ymm0h_regnum
= -1;
7443 tdep
->num_byte_regs
= 8;
7444 tdep
->num_word_regs
= 8;
7445 tdep
->num_dword_regs
= 0;
7446 tdep
->num_mmx_regs
= 8;
7447 tdep
->num_ymm_regs
= 0;
7449 tdesc_data
= tdesc_data_alloc ();
7451 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7453 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7455 /* Hook in ABI-specific overrides, if they have been registered. */
7456 info
.tdep_info
= (void *) tdesc_data
;
7457 gdbarch_init_osabi (info
, gdbarch
);
7459 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7461 tdesc_data_cleanup (tdesc_data
);
7463 gdbarch_free (gdbarch
);
7467 /* Wire in pseudo registers. Number of pseudo registers may be
7469 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7470 + tdep
->num_word_regs
7471 + tdep
->num_dword_regs
7472 + tdep
->num_mmx_regs
7473 + tdep
->num_ymm_regs
));
7475 /* Target description may be changed. */
7476 tdesc
= tdep
->tdesc
;
7478 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7480 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7481 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7483 /* Make %al the first pseudo-register. */
7484 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7485 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7487 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7488 if (tdep
->num_dword_regs
)
7490 /* Support dword pseudo-register if it hasn't been disabled. */
7491 tdep
->eax_regnum
= ymm0_regnum
;
7492 ymm0_regnum
+= tdep
->num_dword_regs
;
7495 tdep
->eax_regnum
= -1;
7497 mm0_regnum
= ymm0_regnum
;
7498 if (tdep
->num_ymm_regs
)
7500 /* Support YMM pseudo-register if it is available. */
7501 tdep
->ymm0_regnum
= ymm0_regnum
;
7502 mm0_regnum
+= tdep
->num_ymm_regs
;
7505 tdep
->ymm0_regnum
= -1;
7507 if (tdep
->num_mmx_regs
!= 0)
7509 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7510 tdep
->mm0_regnum
= mm0_regnum
;
7513 tdep
->mm0_regnum
= -1;
7515 /* Hook in the legacy prologue-based unwinders last (fallback). */
7516 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7517 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7518 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7520 /* If we have a register mapping, enable the generic core file
7521 support, unless it has already been enabled. */
7522 if (tdep
->gregset_reg_offset
7523 && !gdbarch_regset_from_core_section_p (gdbarch
))
7524 set_gdbarch_regset_from_core_section (gdbarch
,
7525 i386_regset_from_core_section
);
7527 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7528 i386_skip_permanent_breakpoint
);
7530 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7531 i386_fast_tracepoint_valid_at
);
7536 static enum gdb_osabi
7537 i386_coff_osabi_sniffer (bfd
*abfd
)
7539 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7540 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7541 return GDB_OSABI_GO32
;
7543 return GDB_OSABI_UNKNOWN
;
7547 /* Provide a prototype to silence -Wmissing-prototypes. */
7548 void _initialize_i386_tdep (void);
7551 _initialize_i386_tdep (void)
7553 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7555 /* Add the variable that controls the disassembly flavor. */
7556 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7557 &disassembly_flavor
, _("\
7558 Set the disassembly flavor."), _("\
7559 Show the disassembly flavor."), _("\
7560 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7562 NULL
, /* FIXME: i18n: */
7563 &setlist
, &showlist
);
7565 /* Add the variable that controls the convention for returning
7567 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7568 &struct_convention
, _("\
7569 Set the convention for returning small structs."), _("\
7570 Show the convention for returning small structs."), _("\
7571 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7574 NULL
, /* FIXME: i18n: */
7575 &setlist
, &showlist
);
7577 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7578 i386_coff_osabi_sniffer
);
7580 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7581 i386_svr4_init_abi
);
7582 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7583 i386_go32_init_abi
);
7585 /* Initialize the i386-specific register groups. */
7586 i386_init_reggroups ();
7588 /* Initialize the standard target descriptions. */
7589 initialize_tdesc_i386 ();
7590 initialize_tdesc_i386_mmx ();
7591 initialize_tdesc_i386_avx ();
7593 /* Tell remote stub that we support XML target description. */
7594 register_remote_support_xml ("i386");