1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
753 fprintf_unfiltered (gdb_stdlog
,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32
), paddress (gdbarch
, oldloc
),
757 hex_string (newrel
), paddress (gdbarch
, *to
));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to
, 5, insn
);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
774 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
775 newrel
= (oldloc
- *to
) + rel32
;
776 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
778 fprintf_unfiltered (gdb_stdlog
,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32
), paddress (gdbarch
, oldloc
),
782 hex_string (newrel
), paddress (gdbarch
, *to
));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to
, insn_length
, buf
);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
810 /* Saved registers. */
811 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
816 /* Stack space reserved for local variables. */
820 /* Allocate and initialize a frame cache. */
822 static struct i386_frame_cache
*
823 i386_alloc_frame_cache (void)
825 struct i386_frame_cache
*cache
;
828 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
832 cache
->sp_offset
= -4;
835 /* Saved registers. We initialize these to -1 since zero is a valid
836 offset (that's where %ebp is supposed to be stored). */
837 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
838 cache
->saved_regs
[i
] = -1;
840 cache
->saved_sp_reg
= -1;
841 cache
->pc_in_eax
= 0;
843 /* Frameless until proven otherwise. */
849 /* If the instruction at PC is a jump, return the address of its
850 target. Otherwise, return PC. */
853 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
855 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
860 if (target_read_memory (pc
, &op
, 1))
866 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
872 /* Relative jump: if data16 == 0, disp32, else disp16. */
875 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
877 /* Include the size of the jmp instruction (including the
883 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
885 /* Include the size of the jmp instruction. */
890 /* Relative jump, disp8 (ignore data16). */
891 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
900 /* Check whether PC points at a prologue for a function returning a
901 structure or union. If so, it updates CACHE and returns the
902 address of the first instruction after the code sequence that
903 removes the "hidden" argument from the stack or CURRENT_PC,
904 whichever is smaller. Otherwise, return PC. */
907 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
908 struct i386_frame_cache
*cache
)
910 /* Functions that return a structure or union start with:
913 xchgl %eax, (%esp) 0x87 0x04 0x24
914 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
916 (the System V compiler puts out the second `xchg' instruction,
917 and the assembler doesn't try to optimize it, so the 'sib' form
918 gets generated). This sequence is used to get the address of the
919 return buffer for a function that returns a structure. */
920 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
921 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
925 if (current_pc
<= pc
)
928 if (target_read_memory (pc
, &op
, 1))
931 if (op
!= 0x58) /* popl %eax */
934 if (target_read_memory (pc
+ 1, buf
, 4))
937 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
940 if (current_pc
== pc
)
942 cache
->sp_offset
+= 4;
946 if (current_pc
== pc
+ 1)
948 cache
->pc_in_eax
= 1;
952 if (buf
[1] == proto1
[1])
959 i386_skip_probe (CORE_ADDR pc
)
961 /* A function may start with
975 if (target_read_memory (pc
, &op
, 1))
978 if (op
== 0x68 || op
== 0x6a)
982 /* Skip past the `pushl' instruction; it has either a one-byte or a
983 four-byte operand, depending on the opcode. */
989 /* Read the following 8 bytes, which should be `call _probe' (6
990 bytes) followed by `addl $4,%esp' (2 bytes). */
991 read_memory (pc
+ delta
, buf
, sizeof (buf
));
992 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
993 pc
+= delta
+ sizeof (buf
);
999 /* GCC 4.1 and later, can put code in the prologue to realign the
1000 stack pointer. Check whether PC points to such code, and update
1001 CACHE accordingly. Return the first instruction after the code
1002 sequence or CURRENT_PC, whichever is smaller. If we don't
1003 recognize the code, return PC. */
1006 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1007 struct i386_frame_cache
*cache
)
1009 /* There are 2 code sequences to re-align stack before the frame
1012 1. Use a caller-saved saved register:
1018 2. Use a callee-saved saved register:
1025 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1027 0x83 0xe4 0xf0 andl $-16, %esp
1028 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1033 int offset
, offset_and
;
1034 static int regnums
[8] = {
1035 I386_EAX_REGNUM
, /* %eax */
1036 I386_ECX_REGNUM
, /* %ecx */
1037 I386_EDX_REGNUM
, /* %edx */
1038 I386_EBX_REGNUM
, /* %ebx */
1039 I386_ESP_REGNUM
, /* %esp */
1040 I386_EBP_REGNUM
, /* %ebp */
1041 I386_ESI_REGNUM
, /* %esi */
1042 I386_EDI_REGNUM
/* %edi */
1045 if (target_read_memory (pc
, buf
, sizeof buf
))
1048 /* Check caller-saved saved register. The first instruction has
1049 to be "leal 4(%esp), %reg". */
1050 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1052 /* MOD must be binary 10 and R/M must be binary 100. */
1053 if ((buf
[1] & 0xc7) != 0x44)
1056 /* REG has register number. */
1057 reg
= (buf
[1] >> 3) & 7;
1062 /* Check callee-saved saved register. The first instruction
1063 has to be "pushl %reg". */
1064 if ((buf
[0] & 0xf8) != 0x50)
1070 /* The next instruction has to be "leal 8(%esp), %reg". */
1071 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1074 /* MOD must be binary 10 and R/M must be binary 100. */
1075 if ((buf
[2] & 0xc7) != 0x44)
1078 /* REG has register number. Registers in pushl and leal have to
1080 if (reg
!= ((buf
[2] >> 3) & 7))
1086 /* Rigister can't be %esp nor %ebp. */
1087 if (reg
== 4 || reg
== 5)
1090 /* The next instruction has to be "andl $-XXX, %esp". */
1091 if (buf
[offset
+ 1] != 0xe4
1092 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1095 offset_and
= offset
;
1096 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1098 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1099 0xfc. REG must be binary 110 and MOD must be binary 01. */
1100 if (buf
[offset
] != 0xff
1101 || buf
[offset
+ 2] != 0xfc
1102 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1105 /* R/M has register. Registers in leal and pushl have to be the
1107 if (reg
!= (buf
[offset
+ 1] & 7))
1110 if (current_pc
> pc
+ offset_and
)
1111 cache
->saved_sp_reg
= regnums
[reg
];
1113 return min (pc
+ offset
+ 3, current_pc
);
1116 /* Maximum instruction length we need to handle. */
1117 #define I386_MAX_MATCHED_INSN_LEN 6
1119 /* Instruction description. */
1123 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1124 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1127 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1128 the first instruction description that matches. Otherwise, return
1131 static struct i386_insn
*
1132 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
1134 struct i386_insn
*insn
;
1137 if (target_read_memory (pc
, &op
, 1))
1140 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1142 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1144 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1145 int insn_matched
= 1;
1148 gdb_assert (insn
->len
> 1);
1149 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1151 if (target_read_memory (pc
+ 1, buf
, insn
->len
- 1))
1154 for (i
= 1; i
< insn
->len
; i
++)
1156 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1168 /* Some special instructions that might be migrated by GCC into the
1169 part of the prologue that sets up the new stack frame. Because the
1170 stack frame hasn't been setup yet, no registers have been saved
1171 yet, and only the scratch registers %eax, %ecx and %edx can be
1174 struct i386_insn i386_frame_setup_skip_insns
[] =
1176 /* Check for `movb imm8, r' and `movl imm32, r'.
1178 ??? Should we handle 16-bit operand-sizes here? */
1180 /* `movb imm8, %al' and `movb imm8, %ah' */
1181 /* `movb imm8, %cl' and `movb imm8, %ch' */
1182 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1183 /* `movb imm8, %dl' and `movb imm8, %dh' */
1184 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1185 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1186 { 5, { 0xb8 }, { 0xfe } },
1187 /* `movl imm32, %edx' */
1188 { 5, { 0xba }, { 0xff } },
1190 /* Check for `mov imm32, r32'. Note that there is an alternative
1191 encoding for `mov m32, %eax'.
1193 ??? Should we handle SIB adressing here?
1194 ??? Should we handle 16-bit operand-sizes here? */
1196 /* `movl m32, %eax' */
1197 { 5, { 0xa1 }, { 0xff } },
1198 /* `movl m32, %eax' and `mov; m32, %ecx' */
1199 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1200 /* `movl m32, %edx' */
1201 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1203 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1204 Because of the symmetry, there are actually two ways to encode
1205 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1206 opcode bytes 0x31 and 0x33 for `xorl'. */
1208 /* `subl %eax, %eax' */
1209 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1210 /* `subl %ecx, %ecx' */
1211 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1212 /* `subl %edx, %edx' */
1213 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1214 /* `xorl %eax, %eax' */
1215 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1216 /* `xorl %ecx, %ecx' */
1217 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1218 /* `xorl %edx, %edx' */
1219 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1224 /* Check whether PC points to a no-op instruction. */
1226 i386_skip_noop (CORE_ADDR pc
)
1231 if (target_read_memory (pc
, &op
, 1))
1237 /* Ignore `nop' instruction. */
1241 if (target_read_memory (pc
, &op
, 1))
1245 /* Ignore no-op instruction `mov %edi, %edi'.
1246 Microsoft system dlls often start with
1247 a `mov %edi,%edi' instruction.
1248 The 5 bytes before the function start are
1249 filled with `nop' instructions.
1250 This pattern can be used for hot-patching:
1251 The `mov %edi, %edi' instruction can be replaced by a
1252 near jump to the location of the 5 `nop' instructions
1253 which can be replaced by a 32-bit jump to anywhere
1254 in the 32-bit address space. */
1256 else if (op
== 0x8b)
1258 if (target_read_memory (pc
+ 1, &op
, 1))
1264 if (target_read_memory (pc
, &op
, 1))
1274 /* Check whether PC points at a code that sets up a new stack frame.
1275 If so, it updates CACHE and returns the address of the first
1276 instruction after the sequence that sets up the frame or LIMIT,
1277 whichever is smaller. If we don't recognize the code, return PC. */
1280 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1281 CORE_ADDR pc
, CORE_ADDR limit
,
1282 struct i386_frame_cache
*cache
)
1284 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1285 struct i386_insn
*insn
;
1292 if (target_read_memory (pc
, &op
, 1))
1295 if (op
== 0x55) /* pushl %ebp */
1297 /* Take into account that we've executed the `pushl %ebp' that
1298 starts this instruction sequence. */
1299 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1300 cache
->sp_offset
+= 4;
1303 /* If that's all, return now. */
1307 /* Check for some special instructions that might be migrated by
1308 GCC into the prologue and skip them. At this point in the
1309 prologue, code should only touch the scratch registers %eax,
1310 %ecx and %edx, so while the number of posibilities is sheer,
1313 Make sure we only skip these instructions if we later see the
1314 `movl %esp, %ebp' that actually sets up the frame. */
1315 while (pc
+ skip
< limit
)
1317 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1324 /* If that's all, return now. */
1325 if (limit
<= pc
+ skip
)
1328 if (target_read_memory (pc
+ skip
, &op
, 1))
1331 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1335 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1340 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1348 /* OK, we actually have a frame. We just don't know how large
1349 it is yet. Set its size to zero. We'll adjust it if
1350 necessary. We also now commit to skipping the special
1351 instructions mentioned before. */
1355 /* If that's all, return now. */
1359 /* Check for stack adjustment
1363 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1364 reg, so we don't have to worry about a data16 prefix. */
1365 if (target_read_memory (pc
, &op
, 1))
1369 /* `subl' with 8-bit immediate. */
1370 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1371 /* Some instruction starting with 0x83 other than `subl'. */
1374 /* `subl' with signed 8-bit immediate (though it wouldn't
1375 make sense to be negative). */
1376 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1379 else if (op
== 0x81)
1381 /* Maybe it is `subl' with a 32-bit immediate. */
1382 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1383 /* Some instruction starting with 0x81 other than `subl'. */
1386 /* It is `subl' with a 32-bit immediate. */
1387 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1392 /* Some instruction other than `subl'. */
1396 else if (op
== 0xc8) /* enter */
1398 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1405 /* Check whether PC points at code that saves registers on the stack.
1406 If so, it updates CACHE and returns the address of the first
1407 instruction after the register saves or CURRENT_PC, whichever is
1408 smaller. Otherwise, return PC. */
1411 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1412 struct i386_frame_cache
*cache
)
1414 CORE_ADDR offset
= 0;
1418 if (cache
->locals
> 0)
1419 offset
-= cache
->locals
;
1420 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1422 if (target_read_memory (pc
, &op
, 1))
1424 if (op
< 0x50 || op
> 0x57)
1428 cache
->saved_regs
[op
- 0x50] = offset
;
1429 cache
->sp_offset
+= 4;
1436 /* Do a full analysis of the prologue at PC and update CACHE
1437 accordingly. Bail out early if CURRENT_PC is reached. Return the
1438 address where the analysis stopped.
1440 We handle these cases:
1442 The startup sequence can be at the start of the function, or the
1443 function can start with a branch to startup code at the end.
1445 %ebp can be set up with either the 'enter' instruction, or "pushl
1446 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1447 once used in the System V compiler).
1449 Local space is allocated just below the saved %ebp by either the
1450 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1451 16-bit unsigned argument for space to allocate, and the 'addl'
1452 instruction could have either a signed byte, or 32-bit immediate.
1454 Next, the registers used by this function are pushed. With the
1455 System V compiler they will always be in the order: %edi, %esi,
1456 %ebx (and sometimes a harmless bug causes it to also save but not
1457 restore %eax); however, the code below is willing to see the pushes
1458 in any order, and will handle up to 8 of them.
1460 If the setup sequence is at the end of the function, then the next
1461 instruction will be a branch back to the start. */
1464 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1465 CORE_ADDR pc
, CORE_ADDR current_pc
,
1466 struct i386_frame_cache
*cache
)
1468 pc
= i386_skip_noop (pc
);
1469 pc
= i386_follow_jump (gdbarch
, pc
);
1470 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1471 pc
= i386_skip_probe (pc
);
1472 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1473 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1474 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1477 /* Return PC of first real instruction. */
1480 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1482 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1484 static gdb_byte pic_pat
[6] =
1486 0xe8, 0, 0, 0, 0, /* call 0x0 */
1487 0x5b, /* popl %ebx */
1489 struct i386_frame_cache cache
;
1495 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1496 if (cache
.locals
< 0)
1499 /* Found valid frame setup. */
1501 /* The native cc on SVR4 in -K PIC mode inserts the following code
1502 to get the address of the global offset table (GOT) into register
1507 movl %ebx,x(%ebp) (optional)
1510 This code is with the rest of the prologue (at the end of the
1511 function), so we have to skip it to get to the first real
1512 instruction at the start of the function. */
1514 for (i
= 0; i
< 6; i
++)
1516 if (target_read_memory (pc
+ i
, &op
, 1))
1519 if (pic_pat
[i
] != op
)
1526 if (target_read_memory (pc
+ delta
, &op
, 1))
1529 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1531 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1533 if (op
== 0x5d) /* One byte offset from %ebp. */
1535 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1537 else /* Unexpected instruction. */
1540 if (target_read_memory (pc
+ delta
, &op
, 1))
1545 if (delta
> 0 && op
== 0x81
1546 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1553 /* If the function starts with a branch (to startup code at the end)
1554 the last instruction should bring us back to the first
1555 instruction of the real code. */
1556 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1557 pc
= i386_follow_jump (gdbarch
, pc
);
1562 /* Check that the code pointed to by PC corresponds to a call to
1563 __main, skip it if so. Return PC otherwise. */
1566 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1568 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1571 if (target_read_memory (pc
, &op
, 1))
1577 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1579 /* Make sure address is computed correctly as a 32bit
1580 integer even if CORE_ADDR is 64 bit wide. */
1581 struct minimal_symbol
*s
;
1582 CORE_ADDR call_dest
;
1584 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1585 call_dest
= call_dest
& 0xffffffffU
;
1586 s
= lookup_minimal_symbol_by_pc (call_dest
);
1588 && SYMBOL_LINKAGE_NAME (s
) != NULL
1589 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1597 /* This function is 64-bit safe. */
1600 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1604 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1605 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1609 /* Normal frames. */
1611 static struct i386_frame_cache
*
1612 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1614 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1615 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1616 struct i386_frame_cache
*cache
;
1623 cache
= i386_alloc_frame_cache ();
1624 *this_cache
= cache
;
1626 /* In principle, for normal frames, %ebp holds the frame pointer,
1627 which holds the base address for the current stack frame.
1628 However, for functions that don't need it, the frame pointer is
1629 optional. For these "frameless" functions the frame pointer is
1630 actually the frame pointer of the calling frame. Signal
1631 trampolines are just a special case of a "frameless" function.
1632 They (usually) share their frame pointer with the frame that was
1633 in progress when the signal occurred. */
1635 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1636 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1637 if (cache
->base
== 0)
1640 /* For normal frames, %eip is stored at 4(%ebp). */
1641 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1643 cache
->pc
= get_frame_func (this_frame
);
1645 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1648 if (cache
->saved_sp_reg
!= -1)
1650 /* Saved stack pointer has been saved. */
1651 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1652 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1655 if (cache
->locals
< 0)
1657 /* We didn't find a valid frame, which means that CACHE->base
1658 currently holds the frame pointer for our calling frame. If
1659 we're at the start of a function, or somewhere half-way its
1660 prologue, the function's frame probably hasn't been fully
1661 setup yet. Try to reconstruct the base address for the stack
1662 frame by looking at the stack pointer. For truly "frameless"
1663 functions this might work too. */
1665 if (cache
->saved_sp_reg
!= -1)
1667 /* We're halfway aligning the stack. */
1668 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1669 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1671 /* This will be added back below. */
1672 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1674 else if (cache
->pc
!= 0
1675 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1677 /* We're in a known function, but did not find a frame
1678 setup. Assume that the function does not use %ebp.
1679 Alternatively, we may have jumped to an invalid
1680 address; in that case there is definitely no new
1682 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1683 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1687 /* We're in an unknown function. We could not find the start
1688 of the function to analyze the prologue; our best option is
1689 to assume a typical frame layout with the caller's %ebp
1691 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1694 /* Now that we have the base address for the stack frame we can
1695 calculate the value of %esp in the calling frame. */
1696 if (cache
->saved_sp
== 0)
1697 cache
->saved_sp
= cache
->base
+ 8;
1699 /* Adjust all the saved registers such that they contain addresses
1700 instead of offsets. */
1701 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1702 if (cache
->saved_regs
[i
] != -1)
1703 cache
->saved_regs
[i
] += cache
->base
;
1709 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1710 struct frame_id
*this_id
)
1712 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1714 /* This marks the outermost frame. */
1715 if (cache
->base
== 0)
1718 /* See the end of i386_push_dummy_call. */
1719 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1722 static struct value
*
1723 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1726 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1728 gdb_assert (regnum
>= 0);
1730 /* The System V ABI says that:
1732 "The flags register contains the system flags, such as the
1733 direction flag and the carry flag. The direction flag must be
1734 set to the forward (that is, zero) direction before entry and
1735 upon exit from a function. Other user flags have no specified
1736 role in the standard calling sequence and are not preserved."
1738 To guarantee the "upon exit" part of that statement we fake a
1739 saved flags register that has its direction flag cleared.
1741 Note that GCC doesn't seem to rely on the fact that the direction
1742 flag is cleared after a function return; it always explicitly
1743 clears the flag before operations where it matters.
1745 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1746 right thing to do. The way we fake the flags register here makes
1747 it impossible to change it. */
1749 if (regnum
== I386_EFLAGS_REGNUM
)
1753 val
= get_frame_register_unsigned (this_frame
, regnum
);
1755 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1758 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1759 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1761 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1762 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1764 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1765 return frame_unwind_got_memory (this_frame
, regnum
,
1766 cache
->saved_regs
[regnum
]);
1768 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1771 static const struct frame_unwind i386_frame_unwind
=
1775 i386_frame_prev_register
,
1777 default_frame_sniffer
1780 /* Normal frames, but in a function epilogue. */
1782 /* The epilogue is defined here as the 'ret' instruction, which will
1783 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1784 the function's stack frame. */
1787 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1791 if (target_read_memory (pc
, &insn
, 1))
1792 return 0; /* Can't read memory at pc. */
1794 if (insn
!= 0xc3) /* 'ret' instruction. */
1801 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1802 struct frame_info
*this_frame
,
1803 void **this_prologue_cache
)
1805 if (frame_relative_level (this_frame
) == 0)
1806 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1807 get_frame_pc (this_frame
));
1812 static struct i386_frame_cache
*
1813 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1815 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1816 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1817 struct i386_frame_cache
*cache
;
1823 cache
= i386_alloc_frame_cache ();
1824 *this_cache
= cache
;
1826 /* Cache base will be %esp plus cache->sp_offset (-4). */
1827 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1828 cache
->base
= extract_unsigned_integer (buf
, 4,
1829 byte_order
) + cache
->sp_offset
;
1831 /* Cache pc will be the frame func. */
1832 cache
->pc
= get_frame_pc (this_frame
);
1834 /* The saved %esp will be at cache->base plus 8. */
1835 cache
->saved_sp
= cache
->base
+ 8;
1837 /* The saved %eip will be at cache->base plus 4. */
1838 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1844 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1846 struct frame_id
*this_id
)
1848 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1851 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1854 static const struct frame_unwind i386_epilogue_frame_unwind
=
1857 i386_epilogue_frame_this_id
,
1858 i386_frame_prev_register
,
1860 i386_epilogue_frame_sniffer
1864 /* Signal trampolines. */
1866 static struct i386_frame_cache
*
1867 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1869 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1871 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1872 struct i386_frame_cache
*cache
;
1879 cache
= i386_alloc_frame_cache ();
1881 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1882 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1884 addr
= tdep
->sigcontext_addr (this_frame
);
1885 if (tdep
->sc_reg_offset
)
1889 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1891 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1892 if (tdep
->sc_reg_offset
[i
] != -1)
1893 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1897 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1898 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1901 *this_cache
= cache
;
1906 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1907 struct frame_id
*this_id
)
1909 struct i386_frame_cache
*cache
=
1910 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1912 /* See the end of i386_push_dummy_call. */
1913 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1916 static struct value
*
1917 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1918 void **this_cache
, int regnum
)
1920 /* Make sure we've initialized the cache. */
1921 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1923 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1927 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1928 struct frame_info
*this_frame
,
1929 void **this_prologue_cache
)
1931 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1933 /* We shouldn't even bother if we don't have a sigcontext_addr
1935 if (tdep
->sigcontext_addr
== NULL
)
1938 if (tdep
->sigtramp_p
!= NULL
)
1940 if (tdep
->sigtramp_p (this_frame
))
1944 if (tdep
->sigtramp_start
!= 0)
1946 CORE_ADDR pc
= get_frame_pc (this_frame
);
1948 gdb_assert (tdep
->sigtramp_end
!= 0);
1949 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1956 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1959 i386_sigtramp_frame_this_id
,
1960 i386_sigtramp_frame_prev_register
,
1962 i386_sigtramp_frame_sniffer
1967 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1969 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1974 static const struct frame_base i386_frame_base
=
1977 i386_frame_base_address
,
1978 i386_frame_base_address
,
1979 i386_frame_base_address
1982 static struct frame_id
1983 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1987 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1989 /* See the end of i386_push_dummy_call. */
1990 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1994 /* Figure out where the longjmp will land. Slurp the args out of the
1995 stack. We expect the first arg to be a pointer to the jmp_buf
1996 structure from which we extract the address that we will land at.
1997 This address is copied into PC. This routine returns non-zero on
2001 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2004 CORE_ADDR sp
, jb_addr
;
2005 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2006 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2007 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2009 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2010 longjmp will land. */
2011 if (jb_pc_offset
== -1)
2014 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2015 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2016 if (target_read_memory (sp
+ 4, buf
, 4))
2019 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2020 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2023 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2028 /* Check whether TYPE must be 16-byte-aligned when passed as a
2029 function argument. 16-byte vectors, _Decimal128 and structures or
2030 unions containing such types must be 16-byte-aligned; other
2031 arguments are 4-byte-aligned. */
2034 i386_16_byte_align_p (struct type
*type
)
2036 type
= check_typedef (type
);
2037 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2038 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2039 && TYPE_LENGTH (type
) == 16)
2041 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2042 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2043 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2044 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2047 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2049 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2057 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2058 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2059 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2060 CORE_ADDR struct_addr
)
2062 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2068 /* Determine the total space required for arguments and struct
2069 return address in a first pass (allowing for 16-byte-aligned
2070 arguments), then push arguments in a second pass. */
2072 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2074 int args_space_used
= 0;
2075 int have_16_byte_aligned_arg
= 0;
2081 /* Push value address. */
2082 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2083 write_memory (sp
, buf
, 4);
2084 args_space_used
+= 4;
2090 for (i
= 0; i
< nargs
; i
++)
2092 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2096 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2097 args_space_used
= align_up (args_space_used
, 16);
2099 write_memory (sp
+ args_space_used
,
2100 value_contents_all (args
[i
]), len
);
2101 /* The System V ABI says that:
2103 "An argument's size is increased, if necessary, to make it a
2104 multiple of [32-bit] words. This may require tail padding,
2105 depending on the size of the argument."
2107 This makes sure the stack stays word-aligned. */
2108 args_space_used
+= align_up (len
, 4);
2112 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2114 args_space
= align_up (args_space
, 16);
2115 have_16_byte_aligned_arg
= 1;
2117 args_space
+= align_up (len
, 4);
2123 if (have_16_byte_aligned_arg
)
2124 args_space
= align_up (args_space
, 16);
2129 /* Store return address. */
2131 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2132 write_memory (sp
, buf
, 4);
2134 /* Finally, update the stack pointer... */
2135 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2136 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2138 /* ...and fake a frame pointer. */
2139 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2141 /* MarkK wrote: This "+ 8" is all over the place:
2142 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2143 i386_dummy_id). It's there, since all frame unwinders for
2144 a given target have to agree (within a certain margin) on the
2145 definition of the stack address of a frame. Otherwise frame id
2146 comparison might not work correctly. Since DWARF2/GCC uses the
2147 stack address *before* the function call as a frame's CFA. On
2148 the i386, when %ebp is used as a frame pointer, the offset
2149 between the contents %ebp and the CFA as defined by GCC. */
2153 /* These registers are used for returning integers (and on some
2154 targets also for returning `struct' and `union' values when their
2155 size and alignment match an integer type). */
2156 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2157 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2159 /* Read, for architecture GDBARCH, a function return value of TYPE
2160 from REGCACHE, and copy that into VALBUF. */
2163 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2164 struct regcache
*regcache
, gdb_byte
*valbuf
)
2166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2167 int len
= TYPE_LENGTH (type
);
2168 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2170 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2172 if (tdep
->st0_regnum
< 0)
2174 warning (_("Cannot find floating-point return value."));
2175 memset (valbuf
, 0, len
);
2179 /* Floating-point return values can be found in %st(0). Convert
2180 its contents to the desired type. This is probably not
2181 exactly how it would happen on the target itself, but it is
2182 the best we can do. */
2183 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2184 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2188 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2189 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2191 if (len
<= low_size
)
2193 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2194 memcpy (valbuf
, buf
, len
);
2196 else if (len
<= (low_size
+ high_size
))
2198 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2199 memcpy (valbuf
, buf
, low_size
);
2200 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2201 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2204 internal_error (__FILE__
, __LINE__
,
2205 _("Cannot extract return value of %d bytes long."),
2210 /* Write, for architecture GDBARCH, a function return value of TYPE
2211 from VALBUF into REGCACHE. */
2214 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2215 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2218 int len
= TYPE_LENGTH (type
);
2220 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2223 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2225 if (tdep
->st0_regnum
< 0)
2227 warning (_("Cannot set floating-point return value."));
2231 /* Returning floating-point values is a bit tricky. Apart from
2232 storing the return value in %st(0), we have to simulate the
2233 state of the FPU at function return point. */
2235 /* Convert the value found in VALBUF to the extended
2236 floating-point format used by the FPU. This is probably
2237 not exactly how it would happen on the target itself, but
2238 it is the best we can do. */
2239 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2240 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2242 /* Set the top of the floating-point register stack to 7. The
2243 actual value doesn't really matter, but 7 is what a normal
2244 function return would end up with if the program started out
2245 with a freshly initialized FPU. */
2246 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2248 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2250 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2251 the floating-point register stack to 7, the appropriate value
2252 for the tag word is 0x3fff. */
2253 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2257 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2258 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2260 if (len
<= low_size
)
2261 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2262 else if (len
<= (low_size
+ high_size
))
2264 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2265 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2266 len
- low_size
, valbuf
+ low_size
);
2269 internal_error (__FILE__
, __LINE__
,
2270 _("Cannot store return value of %d bytes long."), len
);
2275 /* This is the variable that is set with "set struct-convention", and
2276 its legitimate values. */
2277 static const char default_struct_convention
[] = "default";
2278 static const char pcc_struct_convention
[] = "pcc";
2279 static const char reg_struct_convention
[] = "reg";
2280 static const char *valid_conventions
[] =
2282 default_struct_convention
,
2283 pcc_struct_convention
,
2284 reg_struct_convention
,
2287 static const char *struct_convention
= default_struct_convention
;
2289 /* Return non-zero if TYPE, which is assumed to be a structure,
2290 a union type, or an array type, should be returned in registers
2291 for architecture GDBARCH. */
2294 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2297 enum type_code code
= TYPE_CODE (type
);
2298 int len
= TYPE_LENGTH (type
);
2300 gdb_assert (code
== TYPE_CODE_STRUCT
2301 || code
== TYPE_CODE_UNION
2302 || code
== TYPE_CODE_ARRAY
);
2304 if (struct_convention
== pcc_struct_convention
2305 || (struct_convention
== default_struct_convention
2306 && tdep
->struct_return
== pcc_struct_return
))
2309 /* Structures consisting of a single `float', `double' or 'long
2310 double' member are returned in %st(0). */
2311 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2313 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2314 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2315 return (len
== 4 || len
== 8 || len
== 12);
2318 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2321 /* Determine, for architecture GDBARCH, how a return value of TYPE
2322 should be returned. If it is supposed to be returned in registers,
2323 and READBUF is non-zero, read the appropriate value from REGCACHE,
2324 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2325 from WRITEBUF into REGCACHE. */
2327 static enum return_value_convention
2328 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2329 struct type
*type
, struct regcache
*regcache
,
2330 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2332 enum type_code code
= TYPE_CODE (type
);
2334 if (((code
== TYPE_CODE_STRUCT
2335 || code
== TYPE_CODE_UNION
2336 || code
== TYPE_CODE_ARRAY
)
2337 && !i386_reg_struct_return_p (gdbarch
, type
))
2338 /* 128-bit decimal float uses the struct return convention. */
2339 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2341 /* The System V ABI says that:
2343 "A function that returns a structure or union also sets %eax
2344 to the value of the original address of the caller's area
2345 before it returns. Thus when the caller receives control
2346 again, the address of the returned object resides in register
2347 %eax and can be used to access the object."
2349 So the ABI guarantees that we can always find the return
2350 value just after the function has returned. */
2352 /* Note that the ABI doesn't mention functions returning arrays,
2353 which is something possible in certain languages such as Ada.
2354 In this case, the value is returned as if it was wrapped in
2355 a record, so the convention applied to records also applies
2362 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2363 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2366 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2369 /* This special case is for structures consisting of a single
2370 `float', `double' or 'long double' member. These structures are
2371 returned in %st(0). For these structures, we call ourselves
2372 recursively, changing TYPE into the type of the first member of
2373 the structure. Since that should work for all structures that
2374 have only one member, we don't bother to check the member's type
2376 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2378 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2379 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2384 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2386 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2388 return RETURN_VALUE_REGISTER_CONVENTION
;
2393 i387_ext_type (struct gdbarch
*gdbarch
)
2395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2397 if (!tdep
->i387_ext_type
)
2399 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2400 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2403 return tdep
->i387_ext_type
;
2406 /* Construct vector type for pseudo YMM registers. We can't use
2407 tdesc_find_type since YMM isn't described in target description. */
2409 static struct type
*
2410 i386_ymm_type (struct gdbarch
*gdbarch
)
2412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2414 if (!tdep
->i386_ymm_type
)
2416 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2418 /* The type we're building is this: */
2420 union __gdb_builtin_type_vec256i
2422 int128_t uint128
[2];
2423 int64_t v2_int64
[4];
2424 int32_t v4_int32
[8];
2425 int16_t v8_int16
[16];
2426 int8_t v16_int8
[32];
2427 double v2_double
[4];
2434 t
= arch_composite_type (gdbarch
,
2435 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2436 append_composite_type_field (t
, "v8_float",
2437 init_vector_type (bt
->builtin_float
, 8));
2438 append_composite_type_field (t
, "v4_double",
2439 init_vector_type (bt
->builtin_double
, 4));
2440 append_composite_type_field (t
, "v32_int8",
2441 init_vector_type (bt
->builtin_int8
, 32));
2442 append_composite_type_field (t
, "v16_int16",
2443 init_vector_type (bt
->builtin_int16
, 16));
2444 append_composite_type_field (t
, "v8_int32",
2445 init_vector_type (bt
->builtin_int32
, 8));
2446 append_composite_type_field (t
, "v4_int64",
2447 init_vector_type (bt
->builtin_int64
, 4));
2448 append_composite_type_field (t
, "v2_int128",
2449 init_vector_type (bt
->builtin_int128
, 2));
2451 TYPE_VECTOR (t
) = 1;
2452 TYPE_NAME (t
) = "builtin_type_vec256i";
2453 tdep
->i386_ymm_type
= t
;
2456 return tdep
->i386_ymm_type
;
2459 /* Construct vector type for MMX registers. */
2460 static struct type
*
2461 i386_mmx_type (struct gdbarch
*gdbarch
)
2463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2465 if (!tdep
->i386_mmx_type
)
2467 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2469 /* The type we're building is this: */
2471 union __gdb_builtin_type_vec64i
2474 int32_t v2_int32
[2];
2475 int16_t v4_int16
[4];
2482 t
= arch_composite_type (gdbarch
,
2483 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2485 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2486 append_composite_type_field (t
, "v2_int32",
2487 init_vector_type (bt
->builtin_int32
, 2));
2488 append_composite_type_field (t
, "v4_int16",
2489 init_vector_type (bt
->builtin_int16
, 4));
2490 append_composite_type_field (t
, "v8_int8",
2491 init_vector_type (bt
->builtin_int8
, 8));
2493 TYPE_VECTOR (t
) = 1;
2494 TYPE_NAME (t
) = "builtin_type_vec64i";
2495 tdep
->i386_mmx_type
= t
;
2498 return tdep
->i386_mmx_type
;
2501 /* Return the GDB type object for the "standard" data type of data in
2504 static struct type
*
2505 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2507 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2508 return i386_mmx_type (gdbarch
);
2509 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2510 return i386_ymm_type (gdbarch
);
2513 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2514 if (i386_byte_regnum_p (gdbarch
, regnum
))
2515 return bt
->builtin_int8
;
2516 else if (i386_word_regnum_p (gdbarch
, regnum
))
2517 return bt
->builtin_int16
;
2518 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2519 return bt
->builtin_int32
;
2522 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2525 /* Map a cooked register onto a raw register or memory. For the i386,
2526 the MMX registers need to be mapped onto floating point registers. */
2529 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2531 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2536 mmxreg
= regnum
- tdep
->mm0_regnum
;
2537 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2538 tos
= (fstat
>> 11) & 0x7;
2539 fpreg
= (mmxreg
+ tos
) % 8;
2541 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2545 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2546 int regnum
, gdb_byte
*buf
)
2548 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2550 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2552 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2554 /* Extract (always little endian). */
2555 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2556 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2560 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2562 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2564 regnum
-= tdep
->ymm0_regnum
;
2566 /* Extract (always little endian). Read lower 128bits. */
2567 regcache_raw_read (regcache
,
2568 I387_XMM0_REGNUM (tdep
) + regnum
,
2570 memcpy (buf
, raw_buf
, 16);
2571 /* Read upper 128bits. */
2572 regcache_raw_read (regcache
,
2573 tdep
->ymm0h_regnum
+ regnum
,
2575 memcpy (buf
+ 16, raw_buf
, 16);
2577 else if (i386_word_regnum_p (gdbarch
, regnum
))
2579 int gpnum
= regnum
- tdep
->ax_regnum
;
2581 /* Extract (always little endian). */
2582 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2583 memcpy (buf
, raw_buf
, 2);
2585 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2587 /* Check byte pseudo registers last since this function will
2588 be called from amd64_pseudo_register_read, which handles
2589 byte pseudo registers differently. */
2590 int gpnum
= regnum
- tdep
->al_regnum
;
2592 /* Extract (always little endian). We read both lower and
2594 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2596 memcpy (buf
, raw_buf
+ 1, 1);
2598 memcpy (buf
, raw_buf
, 1);
2601 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2606 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2607 int regnum
, const gdb_byte
*buf
)
2609 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2611 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2613 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2616 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2617 /* ... Modify ... (always little endian). */
2618 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2620 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2624 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2626 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2628 regnum
-= tdep
->ymm0_regnum
;
2630 /* ... Write lower 128bits. */
2631 regcache_raw_write (regcache
,
2632 I387_XMM0_REGNUM (tdep
) + regnum
,
2634 /* ... Write upper 128bits. */
2635 regcache_raw_write (regcache
,
2636 tdep
->ymm0h_regnum
+ regnum
,
2639 else if (i386_word_regnum_p (gdbarch
, regnum
))
2641 int gpnum
= regnum
- tdep
->ax_regnum
;
2644 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2645 /* ... Modify ... (always little endian). */
2646 memcpy (raw_buf
, buf
, 2);
2648 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2650 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2652 /* Check byte pseudo registers last since this function will
2653 be called from amd64_pseudo_register_read, which handles
2654 byte pseudo registers differently. */
2655 int gpnum
= regnum
- tdep
->al_regnum
;
2657 /* Read ... We read both lower and upper registers. */
2658 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2659 /* ... Modify ... (always little endian). */
2661 memcpy (raw_buf
+ 1, buf
, 1);
2663 memcpy (raw_buf
, buf
, 1);
2665 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2668 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2673 /* Return the register number of the register allocated by GCC after
2674 REGNUM, or -1 if there is no such register. */
2677 i386_next_regnum (int regnum
)
2679 /* GCC allocates the registers in the order:
2681 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2683 Since storing a variable in %esp doesn't make any sense we return
2684 -1 for %ebp and for %esp itself. */
2685 static int next_regnum
[] =
2687 I386_EDX_REGNUM
, /* Slot for %eax. */
2688 I386_EBX_REGNUM
, /* Slot for %ecx. */
2689 I386_ECX_REGNUM
, /* Slot for %edx. */
2690 I386_ESI_REGNUM
, /* Slot for %ebx. */
2691 -1, -1, /* Slots for %esp and %ebp. */
2692 I386_EDI_REGNUM
, /* Slot for %esi. */
2693 I386_EBP_REGNUM
/* Slot for %edi. */
2696 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2697 return next_regnum
[regnum
];
2702 /* Return nonzero if a value of type TYPE stored in register REGNUM
2703 needs any special handling. */
2706 i386_convert_register_p (struct gdbarch
*gdbarch
,
2707 int regnum
, struct type
*type
)
2709 int len
= TYPE_LENGTH (type
);
2711 /* Values may be spread across multiple registers. Most debugging
2712 formats aren't expressive enough to specify the locations, so
2713 some heuristics is involved. Right now we only handle types that
2714 have a length that is a multiple of the word size, since GCC
2715 doesn't seem to put any other types into registers. */
2716 if (len
> 4 && len
% 4 == 0)
2718 int last_regnum
= regnum
;
2722 last_regnum
= i386_next_regnum (last_regnum
);
2726 if (last_regnum
!= -1)
2730 return i387_convert_register_p (gdbarch
, regnum
, type
);
2733 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2734 return its contents in TO. */
2737 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2738 struct type
*type
, gdb_byte
*to
)
2740 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2741 int len
= TYPE_LENGTH (type
);
2743 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2744 available in FRAME (i.e. if it wasn't saved)? */
2746 if (i386_fp_regnum_p (gdbarch
, regnum
))
2748 i387_register_to_value (frame
, regnum
, type
, to
);
2752 /* Read a value spread across multiple registers. */
2754 gdb_assert (len
> 4 && len
% 4 == 0);
2758 gdb_assert (regnum
!= -1);
2759 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2761 get_frame_register (frame
, regnum
, to
);
2762 regnum
= i386_next_regnum (regnum
);
2768 /* Write the contents FROM of a value of type TYPE into register
2769 REGNUM in frame FRAME. */
2772 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2773 struct type
*type
, const gdb_byte
*from
)
2775 int len
= TYPE_LENGTH (type
);
2777 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2779 i387_value_to_register (frame
, regnum
, type
, from
);
2783 /* Write a value spread across multiple registers. */
2785 gdb_assert (len
> 4 && len
% 4 == 0);
2789 gdb_assert (regnum
!= -1);
2790 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2792 put_frame_register (frame
, regnum
, from
);
2793 regnum
= i386_next_regnum (regnum
);
2799 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2800 in the general-purpose register set REGSET to register cache
2801 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2804 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2805 int regnum
, const void *gregs
, size_t len
)
2807 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2808 const gdb_byte
*regs
= gregs
;
2811 gdb_assert (len
== tdep
->sizeof_gregset
);
2813 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2815 if ((regnum
== i
|| regnum
== -1)
2816 && tdep
->gregset_reg_offset
[i
] != -1)
2817 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2821 /* Collect register REGNUM from the register cache REGCACHE and store
2822 it in the buffer specified by GREGS and LEN as described by the
2823 general-purpose register set REGSET. If REGNUM is -1, do this for
2824 all registers in REGSET. */
2827 i386_collect_gregset (const struct regset
*regset
,
2828 const struct regcache
*regcache
,
2829 int regnum
, void *gregs
, size_t len
)
2831 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2832 gdb_byte
*regs
= gregs
;
2835 gdb_assert (len
== tdep
->sizeof_gregset
);
2837 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2839 if ((regnum
== i
|| regnum
== -1)
2840 && tdep
->gregset_reg_offset
[i
] != -1)
2841 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2845 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2846 in the floating-point register set REGSET to register cache
2847 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2850 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2851 int regnum
, const void *fpregs
, size_t len
)
2853 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2855 if (len
== I387_SIZEOF_FXSAVE
)
2857 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2861 gdb_assert (len
== tdep
->sizeof_fpregset
);
2862 i387_supply_fsave (regcache
, regnum
, fpregs
);
2865 /* Collect register REGNUM from the register cache REGCACHE and store
2866 it in the buffer specified by FPREGS and LEN as described by the
2867 floating-point register set REGSET. If REGNUM is -1, do this for
2868 all registers in REGSET. */
2871 i386_collect_fpregset (const struct regset
*regset
,
2872 const struct regcache
*regcache
,
2873 int regnum
, void *fpregs
, size_t len
)
2875 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2877 if (len
== I387_SIZEOF_FXSAVE
)
2879 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2883 gdb_assert (len
== tdep
->sizeof_fpregset
);
2884 i387_collect_fsave (regcache
, regnum
, fpregs
);
2887 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2890 i386_supply_xstateregset (const struct regset
*regset
,
2891 struct regcache
*regcache
, int regnum
,
2892 const void *xstateregs
, size_t len
)
2894 i387_supply_xsave (regcache
, regnum
, xstateregs
);
2897 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2900 i386_collect_xstateregset (const struct regset
*regset
,
2901 const struct regcache
*regcache
,
2902 int regnum
, void *xstateregs
, size_t len
)
2904 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2907 /* Return the appropriate register set for the core section identified
2908 by SECT_NAME and SECT_SIZE. */
2910 const struct regset
*
2911 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2912 const char *sect_name
, size_t sect_size
)
2914 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2916 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2918 if (tdep
->gregset
== NULL
)
2919 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2920 i386_collect_gregset
);
2921 return tdep
->gregset
;
2924 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2925 || (strcmp (sect_name
, ".reg-xfp") == 0
2926 && sect_size
== I387_SIZEOF_FXSAVE
))
2928 if (tdep
->fpregset
== NULL
)
2929 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2930 i386_collect_fpregset
);
2931 return tdep
->fpregset
;
2934 if (strcmp (sect_name
, ".reg-xstate") == 0)
2936 if (tdep
->xstateregset
== NULL
)
2937 tdep
->xstateregset
= regset_alloc (gdbarch
,
2938 i386_supply_xstateregset
,
2939 i386_collect_xstateregset
);
2941 return tdep
->xstateregset
;
2948 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2951 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2952 CORE_ADDR pc
, char *name
)
2954 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2955 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2958 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2960 unsigned long indirect
=
2961 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2962 struct minimal_symbol
*indsym
=
2963 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2964 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2968 if (strncmp (symname
, "__imp_", 6) == 0
2969 || strncmp (symname
, "_imp_", 5) == 0)
2971 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2974 return 0; /* Not a trampoline. */
2978 /* Return whether the THIS_FRAME corresponds to a sigtramp
2982 i386_sigtramp_p (struct frame_info
*this_frame
)
2984 CORE_ADDR pc
= get_frame_pc (this_frame
);
2987 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2988 return (name
&& strcmp ("_sigtramp", name
) == 0);
2992 /* We have two flavours of disassembly. The machinery on this page
2993 deals with switching between those. */
2996 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2998 gdb_assert (disassembly_flavor
== att_flavor
2999 || disassembly_flavor
== intel_flavor
);
3001 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3002 constified, cast to prevent a compiler warning. */
3003 info
->disassembler_options
= (char *) disassembly_flavor
;
3005 return print_insn_i386 (pc
, info
);
3009 /* There are a few i386 architecture variants that differ only
3010 slightly from the generic i386 target. For now, we don't give them
3011 their own source file, but include them here. As a consequence,
3012 they'll always be included. */
3014 /* System V Release 4 (SVR4). */
3016 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3020 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3022 CORE_ADDR pc
= get_frame_pc (this_frame
);
3025 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3026 currently unknown. */
3027 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3028 return (name
&& (strcmp ("_sigreturn", name
) == 0
3029 || strcmp ("_sigacthandler", name
) == 0
3030 || strcmp ("sigvechandler", name
) == 0));
3033 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3034 address of the associated sigcontext (ucontext) structure. */
3037 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3039 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3040 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3044 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3045 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3047 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3054 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3056 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3057 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3060 /* System V Release 4 (SVR4). */
3063 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3065 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3067 /* System V Release 4 uses ELF. */
3068 i386_elf_init_abi (info
, gdbarch
);
3070 /* System V Release 4 has shared libraries. */
3071 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3073 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3074 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3075 tdep
->sc_pc_offset
= 36 + 14 * 4;
3076 tdep
->sc_sp_offset
= 36 + 17 * 4;
3078 tdep
->jb_pc_offset
= 20;
3084 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3086 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3088 /* DJGPP doesn't have any special frames for signal handlers. */
3089 tdep
->sigtramp_p
= NULL
;
3091 tdep
->jb_pc_offset
= 36;
3093 /* DJGPP does not support the SSE registers. */
3094 if (! tdesc_has_registers (info
.target_desc
))
3095 tdep
->tdesc
= tdesc_i386_mmx
;
3097 /* Native compiler is GCC, which uses the SVR4 register numbering
3098 even in COFF and STABS. See the comment in i386_gdbarch_init,
3099 before the calls to set_gdbarch_stab_reg_to_regnum and
3100 set_gdbarch_sdb_reg_to_regnum. */
3101 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3102 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3104 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3108 /* i386 register groups. In addition to the normal groups, add "mmx"
3111 static struct reggroup
*i386_sse_reggroup
;
3112 static struct reggroup
*i386_mmx_reggroup
;
3115 i386_init_reggroups (void)
3117 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3118 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3122 i386_add_reggroups (struct gdbarch
*gdbarch
)
3124 reggroup_add (gdbarch
, i386_sse_reggroup
);
3125 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3126 reggroup_add (gdbarch
, general_reggroup
);
3127 reggroup_add (gdbarch
, float_reggroup
);
3128 reggroup_add (gdbarch
, all_reggroup
);
3129 reggroup_add (gdbarch
, save_reggroup
);
3130 reggroup_add (gdbarch
, restore_reggroup
);
3131 reggroup_add (gdbarch
, vector_reggroup
);
3132 reggroup_add (gdbarch
, system_reggroup
);
3136 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3137 struct reggroup
*group
)
3139 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3140 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3141 ymm_regnum_p
, ymmh_regnum_p
;
3143 /* Don't include pseudo registers, except for MMX, in any register
3145 if (i386_byte_regnum_p (gdbarch
, regnum
))
3148 if (i386_word_regnum_p (gdbarch
, regnum
))
3151 if (i386_dword_regnum_p (gdbarch
, regnum
))
3154 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3155 if (group
== i386_mmx_reggroup
)
3156 return mmx_regnum_p
;
3158 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3159 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3160 if (group
== i386_sse_reggroup
)
3161 return xmm_regnum_p
|| mxcsr_regnum_p
;
3163 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3164 if (group
== vector_reggroup
)
3165 return (mmx_regnum_p
3169 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3170 == I386_XSTATE_SSE_MASK
)));
3172 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3173 || i386_fpc_regnum_p (gdbarch
, regnum
));
3174 if (group
== float_reggroup
)
3177 /* For "info reg all", don't include upper YMM registers nor XMM
3178 registers when AVX is supported. */
3179 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3180 if (group
== all_reggroup
3182 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3186 if (group
== general_reggroup
)
3187 return (!fp_regnum_p
3194 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3198 /* Get the ARGIth function argument for the current function. */
3201 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3204 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3205 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3206 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3207 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3211 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3213 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3215 /* On i386, breakpoint is exactly 1 byte long, so we just
3216 adjust the PC in the regcache. */
3218 regcache_write_pc (regcache
, current_pc
);
3222 #define PREFIX_REPZ 0x01
3223 #define PREFIX_REPNZ 0x02
3224 #define PREFIX_LOCK 0x04
3225 #define PREFIX_DATA 0x08
3226 #define PREFIX_ADDR 0x10
3238 /* i386 arith/logic operations */
3251 struct i386_record_s
3253 struct gdbarch
*gdbarch
;
3254 struct regcache
*regcache
;
3255 CORE_ADDR orig_addr
;
3261 uint8_t mod
, reg
, rm
;
3270 /* Parse "modrm" part in current memory address that irp->addr point to
3271 Return -1 if something wrong. */
3274 i386_record_modrm (struct i386_record_s
*irp
)
3276 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3278 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3281 printf_unfiltered (_("Process record: error reading memory at "
3282 "addr %s len = 1.\n"),
3283 paddress (gdbarch
, irp
->addr
));
3287 irp
->mod
= (irp
->modrm
>> 6) & 3;
3288 irp
->reg
= (irp
->modrm
>> 3) & 7;
3289 irp
->rm
= irp
->modrm
& 7;
3294 /* Get the memory address that current instruction write to and set it to
3295 the argument "addr".
3296 Return -1 if something wrong. */
3299 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3301 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3302 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3314 uint8_t base
= irp
->rm
;
3319 if (target_read_memory (irp
->addr
, &byte
, 1))
3322 printf_unfiltered (_("Process record: error reading memory "
3323 "at addr %s len = 1.\n"),
3324 paddress (gdbarch
, irp
->addr
));
3328 scale
= (byte
>> 6) & 3;
3329 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3337 if ((base
& 7) == 5)
3340 if (target_read_memory (irp
->addr
, buf
, 4))
3343 printf_unfiltered (_("Process record: error reading "
3344 "memory at addr %s len = 4.\n"),
3345 paddress (gdbarch
, irp
->addr
));
3349 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3350 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3351 *addr
+= irp
->addr
+ irp
->rip_offset
;
3355 if (target_read_memory (irp
->addr
, buf
, 1))
3358 printf_unfiltered (_("Process record: error reading memory "
3359 "at addr %s len = 1.\n"),
3360 paddress (gdbarch
, irp
->addr
));
3364 *addr
= (int8_t) buf
[0];
3367 if (target_read_memory (irp
->addr
, buf
, 4))
3370 printf_unfiltered (_("Process record: error reading memory "
3371 "at addr %s len = 4.\n"),
3372 paddress (gdbarch
, irp
->addr
));
3375 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3383 if (base
== 4 && irp
->popl_esp_hack
)
3384 *addr
+= irp
->popl_esp_hack
;
3385 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3388 if (irp
->aflag
== 2)
3393 *addr
= (uint32_t) (offset64
+ *addr
);
3395 if (havesib
&& (index
!= 4 || scale
!= 0))
3397 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3399 if (irp
->aflag
== 2)
3400 *addr
+= offset64
<< scale
;
3402 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3413 if (target_read_memory (irp
->addr
, buf
, 2))
3416 printf_unfiltered (_("Process record: error reading "
3417 "memory at addr %s len = 2.\n"),
3418 paddress (gdbarch
, irp
->addr
));
3422 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3428 if (target_read_memory (irp
->addr
, buf
, 1))
3431 printf_unfiltered (_("Process record: error reading memory "
3432 "at addr %s len = 1.\n"),
3433 paddress (gdbarch
, irp
->addr
));
3437 *addr
= (int8_t) buf
[0];
3440 if (target_read_memory (irp
->addr
, buf
, 2))
3443 printf_unfiltered (_("Process record: error reading memory "
3444 "at addr %s len = 2.\n"),
3445 paddress (gdbarch
, irp
->addr
));
3449 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3456 regcache_raw_read_unsigned (irp
->regcache
,
3457 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3459 *addr
= (uint32_t) (*addr
+ offset64
);
3460 regcache_raw_read_unsigned (irp
->regcache
,
3461 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3463 *addr
= (uint32_t) (*addr
+ offset64
);
3466 regcache_raw_read_unsigned (irp
->regcache
,
3467 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3469 *addr
= (uint32_t) (*addr
+ offset64
);
3470 regcache_raw_read_unsigned (irp
->regcache
,
3471 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3473 *addr
= (uint32_t) (*addr
+ offset64
);
3476 regcache_raw_read_unsigned (irp
->regcache
,
3477 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3479 *addr
= (uint32_t) (*addr
+ offset64
);
3480 regcache_raw_read_unsigned (irp
->regcache
,
3481 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3483 *addr
= (uint32_t) (*addr
+ offset64
);
3486 regcache_raw_read_unsigned (irp
->regcache
,
3487 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3489 *addr
= (uint32_t) (*addr
+ offset64
);
3490 regcache_raw_read_unsigned (irp
->regcache
,
3491 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3493 *addr
= (uint32_t) (*addr
+ offset64
);
3496 regcache_raw_read_unsigned (irp
->regcache
,
3497 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3499 *addr
= (uint32_t) (*addr
+ offset64
);
3502 regcache_raw_read_unsigned (irp
->regcache
,
3503 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3505 *addr
= (uint32_t) (*addr
+ offset64
);
3508 regcache_raw_read_unsigned (irp
->regcache
,
3509 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3511 *addr
= (uint32_t) (*addr
+ offset64
);
3514 regcache_raw_read_unsigned (irp
->regcache
,
3515 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3517 *addr
= (uint32_t) (*addr
+ offset64
);
3527 /* Record the value of the memory that willbe changed in current instruction
3528 to "record_arch_list".
3529 Return -1 if something wrong. */
3532 i386_record_lea_modrm (struct i386_record_s
*irp
)
3534 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3537 if (irp
->override
>= 0)
3539 if (record_memory_query
)
3543 target_terminal_ours ();
3545 Process record ignores the memory change of instruction at address %s\n\
3546 because it can't get the value of the segment register.\n\
3547 Do you want to stop the program?"),
3548 paddress (gdbarch
, irp
->orig_addr
));
3549 target_terminal_inferior ();
3557 if (i386_record_lea_modrm_addr (irp
, &addr
))
3560 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3566 /* Record the push operation to "record_arch_list".
3567 Return -1 if something wrong. */
3570 i386_record_push (struct i386_record_s
*irp
, int size
)
3574 if (record_arch_list_add_reg (irp
->regcache
,
3575 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3577 regcache_raw_read_unsigned (irp
->regcache
,
3578 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3580 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3587 /* Defines contents to record. */
3588 #define I386_SAVE_FPU_REGS 0xfffd
3589 #define I386_SAVE_FPU_ENV 0xfffe
3590 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3592 /* Record the value of floating point registers which will be changed
3593 by the current instruction to "record_arch_list". Return -1 if
3594 something is wrong. */
3596 static int i386_record_floats (struct gdbarch
*gdbarch
,
3597 struct i386_record_s
*ir
,
3600 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3603 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3604 happen. Currently we store st0-st7 registers, but we need not store all
3605 registers all the time, in future we use ftag register and record only
3606 those who are not marked as an empty. */
3608 if (I386_SAVE_FPU_REGS
== iregnum
)
3610 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3612 if (record_arch_list_add_reg (ir
->regcache
, i
))
3616 else if (I386_SAVE_FPU_ENV
== iregnum
)
3618 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3620 if (record_arch_list_add_reg (ir
->regcache
, i
))
3624 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3626 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3628 if (record_arch_list_add_reg (ir
->regcache
, i
))
3632 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3633 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3635 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3640 /* Parameter error. */
3643 if(I386_SAVE_FPU_ENV
!= iregnum
)
3645 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3647 if (record_arch_list_add_reg (ir
->regcache
, i
))
3654 /* Parse the current instruction and record the values of the registers and
3655 memory that will be changed in current instruction to "record_arch_list".
3656 Return -1 if something wrong. */
3658 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3659 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3662 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3663 CORE_ADDR input_addr
)
3665 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3671 gdb_byte buf
[MAX_REGISTER_SIZE
];
3672 struct i386_record_s ir
;
3673 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3678 memset (&ir
, 0, sizeof (struct i386_record_s
));
3679 ir
.regcache
= regcache
;
3680 ir
.addr
= input_addr
;
3681 ir
.orig_addr
= input_addr
;
3685 ir
.popl_esp_hack
= 0;
3686 ir
.regmap
= tdep
->record_regmap
;
3687 ir
.gdbarch
= gdbarch
;
3689 if (record_debug
> 1)
3690 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3692 paddress (gdbarch
, ir
.addr
));
3697 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3700 printf_unfiltered (_("Process record: error reading memory at "
3701 "addr %s len = 1.\n"),
3702 paddress (gdbarch
, ir
.addr
));
3706 switch (opcode8
) /* Instruction prefixes */
3708 case REPE_PREFIX_OPCODE
:
3709 prefixes
|= PREFIX_REPZ
;
3711 case REPNE_PREFIX_OPCODE
:
3712 prefixes
|= PREFIX_REPNZ
;
3714 case LOCK_PREFIX_OPCODE
:
3715 prefixes
|= PREFIX_LOCK
;
3717 case CS_PREFIX_OPCODE
:
3718 ir
.override
= X86_RECORD_CS_REGNUM
;
3720 case SS_PREFIX_OPCODE
:
3721 ir
.override
= X86_RECORD_SS_REGNUM
;
3723 case DS_PREFIX_OPCODE
:
3724 ir
.override
= X86_RECORD_DS_REGNUM
;
3726 case ES_PREFIX_OPCODE
:
3727 ir
.override
= X86_RECORD_ES_REGNUM
;
3729 case FS_PREFIX_OPCODE
:
3730 ir
.override
= X86_RECORD_FS_REGNUM
;
3732 case GS_PREFIX_OPCODE
:
3733 ir
.override
= X86_RECORD_GS_REGNUM
;
3735 case DATA_PREFIX_OPCODE
:
3736 prefixes
|= PREFIX_DATA
;
3738 case ADDR_PREFIX_OPCODE
:
3739 prefixes
|= PREFIX_ADDR
;
3741 case 0x40: /* i386 inc %eax */
3742 case 0x41: /* i386 inc %ecx */
3743 case 0x42: /* i386 inc %edx */
3744 case 0x43: /* i386 inc %ebx */
3745 case 0x44: /* i386 inc %esp */
3746 case 0x45: /* i386 inc %ebp */
3747 case 0x46: /* i386 inc %esi */
3748 case 0x47: /* i386 inc %edi */
3749 case 0x48: /* i386 dec %eax */
3750 case 0x49: /* i386 dec %ecx */
3751 case 0x4a: /* i386 dec %edx */
3752 case 0x4b: /* i386 dec %ebx */
3753 case 0x4c: /* i386 dec %esp */
3754 case 0x4d: /* i386 dec %ebp */
3755 case 0x4e: /* i386 dec %esi */
3756 case 0x4f: /* i386 dec %edi */
3757 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3761 rex_w
= (opcode8
>> 3) & 1;
3762 rex_r
= (opcode8
& 0x4) << 1;
3763 ir
.rex_x
= (opcode8
& 0x2) << 2;
3764 ir
.rex_b
= (opcode8
& 0x1) << 3;
3766 else /* 32 bit target */
3775 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3781 if (prefixes
& PREFIX_DATA
)
3784 if (prefixes
& PREFIX_ADDR
)
3786 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3789 /* Now check op code. */
3790 opcode
= (uint32_t) opcode8
;
3795 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3798 printf_unfiltered (_("Process record: error reading memory at "
3799 "addr %s len = 1.\n"),
3800 paddress (gdbarch
, ir
.addr
));
3804 opcode
= (uint32_t) opcode8
| 0x0f00;
3808 case 0x00: /* arith & logic */
3856 if (((opcode
>> 3) & 7) != OP_CMPL
)
3858 if ((opcode
& 1) == 0)
3861 ir
.ot
= ir
.dflag
+ OT_WORD
;
3863 switch ((opcode
>> 1) & 3)
3865 case 0: /* OP Ev, Gv */
3866 if (i386_record_modrm (&ir
))
3870 if (i386_record_lea_modrm (&ir
))
3876 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3878 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3881 case 1: /* OP Gv, Ev */
3882 if (i386_record_modrm (&ir
))
3885 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3887 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3889 case 2: /* OP A, Iv */
3890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3897 case 0x80: /* GRP1 */
3901 if (i386_record_modrm (&ir
))
3904 if (ir
.reg
!= OP_CMPL
)
3906 if ((opcode
& 1) == 0)
3909 ir
.ot
= ir
.dflag
+ OT_WORD
;
3916 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3917 if (i386_record_lea_modrm (&ir
))
3921 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3926 case 0x40: /* inc */
3935 case 0x48: /* dec */
3944 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3948 case 0xf6: /* GRP3 */
3950 if ((opcode
& 1) == 0)
3953 ir
.ot
= ir
.dflag
+ OT_WORD
;
3954 if (i386_record_modrm (&ir
))
3957 if (ir
.mod
!= 3 && ir
.reg
== 0)
3958 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3969 if (i386_record_lea_modrm (&ir
))
3975 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3977 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3979 if (ir
.reg
== 3) /* neg */
3980 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3986 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3987 if (ir
.ot
!= OT_BYTE
)
3988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3993 opcode
= opcode
<< 8 | ir
.modrm
;
3999 case 0xfe: /* GRP4 */
4000 case 0xff: /* GRP5 */
4001 if (i386_record_modrm (&ir
))
4003 if (ir
.reg
>= 2 && opcode
== 0xfe)
4006 opcode
= opcode
<< 8 | ir
.modrm
;
4013 if ((opcode
& 1) == 0)
4016 ir
.ot
= ir
.dflag
+ OT_WORD
;
4019 if (i386_record_lea_modrm (&ir
))
4025 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4027 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4032 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4034 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4036 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4039 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4040 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4042 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4046 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4049 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4051 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4056 opcode
= opcode
<< 8 | ir
.modrm
;
4062 case 0x84: /* test */
4066 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4069 case 0x98: /* CWDE/CBW */
4070 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4073 case 0x99: /* CDQ/CWD */
4074 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4075 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4078 case 0x0faf: /* imul */
4081 ir
.ot
= ir
.dflag
+ OT_WORD
;
4082 if (i386_record_modrm (&ir
))
4085 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4086 else if (opcode
== 0x6b)
4089 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4091 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4092 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4095 case 0x0fc0: /* xadd */
4097 if ((opcode
& 1) == 0)
4100 ir
.ot
= ir
.dflag
+ OT_WORD
;
4101 if (i386_record_modrm (&ir
))
4106 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4108 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4109 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4111 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4115 if (i386_record_lea_modrm (&ir
))
4117 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4119 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4121 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4124 case 0x0fb0: /* cmpxchg */
4126 if ((opcode
& 1) == 0)
4129 ir
.ot
= ir
.dflag
+ OT_WORD
;
4130 if (i386_record_modrm (&ir
))
4135 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4136 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4138 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4143 if (i386_record_lea_modrm (&ir
))
4146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4149 case 0x0fc7: /* cmpxchg8b */
4150 if (i386_record_modrm (&ir
))
4155 opcode
= opcode
<< 8 | ir
.modrm
;
4158 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4160 if (i386_record_lea_modrm (&ir
))
4162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4165 case 0x50: /* push */
4175 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4177 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4181 case 0x06: /* push es */
4182 case 0x0e: /* push cs */
4183 case 0x16: /* push ss */
4184 case 0x1e: /* push ds */
4185 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4190 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4194 case 0x0fa0: /* push fs */
4195 case 0x0fa8: /* push gs */
4196 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4201 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4205 case 0x60: /* pusha */
4206 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4211 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4215 case 0x58: /* pop */
4223 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4224 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4227 case 0x61: /* popa */
4228 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4233 for (regnum
= X86_RECORD_REAX_REGNUM
;
4234 regnum
<= X86_RECORD_REDI_REGNUM
;
4236 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4239 case 0x8f: /* pop */
4240 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4241 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4243 ir
.ot
= ir
.dflag
+ OT_WORD
;
4244 if (i386_record_modrm (&ir
))
4247 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4250 ir
.popl_esp_hack
= 1 << ir
.ot
;
4251 if (i386_record_lea_modrm (&ir
))
4254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4257 case 0xc8: /* enter */
4258 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4259 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4261 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4265 case 0xc9: /* leave */
4266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4270 case 0x07: /* pop es */
4271 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4281 case 0x17: /* pop ss */
4282 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4287 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4288 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4292 case 0x1f: /* pop ds */
4293 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4299 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4300 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4303 case 0x0fa1: /* pop fs */
4304 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4306 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4309 case 0x0fa9: /* pop gs */
4310 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4311 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4315 case 0x88: /* mov */
4319 if ((opcode
& 1) == 0)
4322 ir
.ot
= ir
.dflag
+ OT_WORD
;
4324 if (i386_record_modrm (&ir
))
4329 if (opcode
== 0xc6 || opcode
== 0xc7)
4330 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4331 if (i386_record_lea_modrm (&ir
))
4336 if (opcode
== 0xc6 || opcode
== 0xc7)
4338 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4340 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4344 case 0x8a: /* mov */
4346 if ((opcode
& 1) == 0)
4349 ir
.ot
= ir
.dflag
+ OT_WORD
;
4350 if (i386_record_modrm (&ir
))
4353 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4355 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4358 case 0x8c: /* mov seg */
4359 if (i386_record_modrm (&ir
))
4364 opcode
= opcode
<< 8 | ir
.modrm
;
4369 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4373 if (i386_record_lea_modrm (&ir
))
4378 case 0x8e: /* mov seg */
4379 if (i386_record_modrm (&ir
))
4384 regnum
= X86_RECORD_ES_REGNUM
;
4387 regnum
= X86_RECORD_SS_REGNUM
;
4390 regnum
= X86_RECORD_DS_REGNUM
;
4393 regnum
= X86_RECORD_FS_REGNUM
;
4396 regnum
= X86_RECORD_GS_REGNUM
;
4400 opcode
= opcode
<< 8 | ir
.modrm
;
4404 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4408 case 0x0fb6: /* movzbS */
4409 case 0x0fb7: /* movzwS */
4410 case 0x0fbe: /* movsbS */
4411 case 0x0fbf: /* movswS */
4412 if (i386_record_modrm (&ir
))
4414 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4417 case 0x8d: /* lea */
4418 if (i386_record_modrm (&ir
))
4423 opcode
= opcode
<< 8 | ir
.modrm
;
4428 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4430 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4433 case 0xa0: /* mov EAX */
4436 case 0xd7: /* xlat */
4437 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4440 case 0xa2: /* mov EAX */
4442 if (ir
.override
>= 0)
4444 if (record_memory_query
)
4448 target_terminal_ours ();
4450 Process record ignores the memory change of instruction at address %s\n\
4451 because it can't get the value of the segment register.\n\
4452 Do you want to stop the program?"),
4453 paddress (gdbarch
, ir
.orig_addr
));
4454 target_terminal_inferior ();
4461 if ((opcode
& 1) == 0)
4464 ir
.ot
= ir
.dflag
+ OT_WORD
;
4467 if (target_read_memory (ir
.addr
, buf
, 8))
4470 printf_unfiltered (_("Process record: error reading "
4471 "memory at addr 0x%s len = 8.\n"),
4472 paddress (gdbarch
, ir
.addr
));
4476 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4480 if (target_read_memory (ir
.addr
, buf
, 4))
4483 printf_unfiltered (_("Process record: error reading "
4484 "memory at addr 0x%s len = 4.\n"),
4485 paddress (gdbarch
, ir
.addr
));
4489 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4493 if (target_read_memory (ir
.addr
, buf
, 2))
4496 printf_unfiltered (_("Process record: error reading "
4497 "memory at addr 0x%s len = 2.\n"),
4498 paddress (gdbarch
, ir
.addr
));
4502 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4504 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4509 case 0xb0: /* mov R, Ib */
4517 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4518 ? ((opcode
& 0x7) | ir
.rex_b
)
4519 : ((opcode
& 0x7) & 0x3));
4522 case 0xb8: /* mov R, Iv */
4530 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4533 case 0x91: /* xchg R, EAX */
4540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4541 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4544 case 0x86: /* xchg Ev, Gv */
4546 if ((opcode
& 1) == 0)
4549 ir
.ot
= ir
.dflag
+ OT_WORD
;
4550 if (i386_record_modrm (&ir
))
4555 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4557 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4561 if (i386_record_lea_modrm (&ir
))
4565 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4567 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4570 case 0xc4: /* les Gv */
4571 case 0xc5: /* lds Gv */
4572 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4578 case 0x0fb2: /* lss Gv */
4579 case 0x0fb4: /* lfs Gv */
4580 case 0x0fb5: /* lgs Gv */
4581 if (i386_record_modrm (&ir
))
4589 opcode
= opcode
<< 8 | ir
.modrm
;
4594 case 0xc4: /* les Gv */
4595 regnum
= X86_RECORD_ES_REGNUM
;
4597 case 0xc5: /* lds Gv */
4598 regnum
= X86_RECORD_DS_REGNUM
;
4600 case 0x0fb2: /* lss Gv */
4601 regnum
= X86_RECORD_SS_REGNUM
;
4603 case 0x0fb4: /* lfs Gv */
4604 regnum
= X86_RECORD_FS_REGNUM
;
4606 case 0x0fb5: /* lgs Gv */
4607 regnum
= X86_RECORD_GS_REGNUM
;
4610 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4611 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4612 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4615 case 0xc0: /* shifts */
4621 if ((opcode
& 1) == 0)
4624 ir
.ot
= ir
.dflag
+ OT_WORD
;
4625 if (i386_record_modrm (&ir
))
4627 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4629 if (i386_record_lea_modrm (&ir
))
4635 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4637 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4639 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4646 if (i386_record_modrm (&ir
))
4650 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4655 if (i386_record_lea_modrm (&ir
))
4660 case 0xd8: /* Floats. */
4668 if (i386_record_modrm (&ir
))
4670 ir
.reg
|= ((opcode
& 7) << 3);
4676 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4684 /* For fcom, ficom nothing to do. */
4690 /* For fcomp, ficomp pop FPU stack, store all. */
4691 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4718 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4719 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4720 of code, always affects st(0) register. */
4721 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4745 /* Handling fld, fild. */
4746 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4750 switch (ir
.reg
>> 4)
4753 if (record_arch_list_add_mem (addr64
, 4))
4757 if (record_arch_list_add_mem (addr64
, 8))
4763 if (record_arch_list_add_mem (addr64
, 2))
4769 switch (ir
.reg
>> 4)
4772 if (record_arch_list_add_mem (addr64
, 4))
4774 if (3 == (ir
.reg
& 7))
4776 /* For fstp m32fp. */
4777 if (i386_record_floats (gdbarch
, &ir
,
4778 I386_SAVE_FPU_REGS
))
4783 if (record_arch_list_add_mem (addr64
, 4))
4785 if ((3 == (ir
.reg
& 7))
4786 || (5 == (ir
.reg
& 7))
4787 || (7 == (ir
.reg
& 7)))
4789 /* For fstp insn. */
4790 if (i386_record_floats (gdbarch
, &ir
,
4791 I386_SAVE_FPU_REGS
))
4796 if (record_arch_list_add_mem (addr64
, 8))
4798 if (3 == (ir
.reg
& 7))
4800 /* For fstp m64fp. */
4801 if (i386_record_floats (gdbarch
, &ir
,
4802 I386_SAVE_FPU_REGS
))
4807 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4809 /* For fistp, fbld, fild, fbstp. */
4810 if (i386_record_floats (gdbarch
, &ir
,
4811 I386_SAVE_FPU_REGS
))
4816 if (record_arch_list_add_mem (addr64
, 2))
4825 if (i386_record_floats (gdbarch
, &ir
,
4826 I386_SAVE_FPU_ENV_REG_STACK
))
4831 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4836 if (i386_record_floats (gdbarch
, &ir
,
4837 I386_SAVE_FPU_ENV_REG_STACK
))
4843 if (record_arch_list_add_mem (addr64
, 28))
4848 if (record_arch_list_add_mem (addr64
, 14))
4854 if (record_arch_list_add_mem (addr64
, 2))
4856 /* Insn fstp, fbstp. */
4857 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4862 if (record_arch_list_add_mem (addr64
, 10))
4868 if (record_arch_list_add_mem (addr64
, 28))
4874 if (record_arch_list_add_mem (addr64
, 14))
4878 if (record_arch_list_add_mem (addr64
, 80))
4881 if (i386_record_floats (gdbarch
, &ir
,
4882 I386_SAVE_FPU_ENV_REG_STACK
))
4886 if (record_arch_list_add_mem (addr64
, 8))
4889 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4894 opcode
= opcode
<< 8 | ir
.modrm
;
4899 /* Opcode is an extension of modR/M byte. */
4905 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4909 if (0x0c == (ir
.modrm
>> 4))
4911 if ((ir
.modrm
& 0x0f) <= 7)
4913 if (i386_record_floats (gdbarch
, &ir
,
4914 I386_SAVE_FPU_REGS
))
4919 if (i386_record_floats (gdbarch
, &ir
,
4920 I387_ST0_REGNUM (tdep
)))
4922 /* If only st(0) is changing, then we have already
4924 if ((ir
.modrm
& 0x0f) - 0x08)
4926 if (i386_record_floats (gdbarch
, &ir
,
4927 I387_ST0_REGNUM (tdep
) +
4928 ((ir
.modrm
& 0x0f) - 0x08)))
4946 if (i386_record_floats (gdbarch
, &ir
,
4947 I387_ST0_REGNUM (tdep
)))
4965 if (i386_record_floats (gdbarch
, &ir
,
4966 I386_SAVE_FPU_REGS
))
4970 if (i386_record_floats (gdbarch
, &ir
,
4971 I387_ST0_REGNUM (tdep
)))
4973 if (i386_record_floats (gdbarch
, &ir
,
4974 I387_ST0_REGNUM (tdep
) + 1))
4981 if (0xe9 == ir
.modrm
)
4983 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4986 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4988 if (i386_record_floats (gdbarch
, &ir
,
4989 I387_ST0_REGNUM (tdep
)))
4991 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4993 if (i386_record_floats (gdbarch
, &ir
,
4994 I387_ST0_REGNUM (tdep
) +
4998 else if ((ir
.modrm
& 0x0f) - 0x08)
5000 if (i386_record_floats (gdbarch
, &ir
,
5001 I387_ST0_REGNUM (tdep
) +
5002 ((ir
.modrm
& 0x0f) - 0x08)))
5008 if (0xe3 == ir
.modrm
)
5010 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5013 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5015 if (i386_record_floats (gdbarch
, &ir
,
5016 I387_ST0_REGNUM (tdep
)))
5018 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5020 if (i386_record_floats (gdbarch
, &ir
,
5021 I387_ST0_REGNUM (tdep
) +
5025 else if ((ir
.modrm
& 0x0f) - 0x08)
5027 if (i386_record_floats (gdbarch
, &ir
,
5028 I387_ST0_REGNUM (tdep
) +
5029 ((ir
.modrm
& 0x0f) - 0x08)))
5035 if ((0x0c == ir
.modrm
>> 4)
5036 || (0x0d == ir
.modrm
>> 4)
5037 || (0x0f == ir
.modrm
>> 4))
5039 if ((ir
.modrm
& 0x0f) <= 7)
5041 if (i386_record_floats (gdbarch
, &ir
,
5042 I387_ST0_REGNUM (tdep
) +
5048 if (i386_record_floats (gdbarch
, &ir
,
5049 I387_ST0_REGNUM (tdep
) +
5050 ((ir
.modrm
& 0x0f) - 0x08)))
5056 if (0x0c == ir
.modrm
>> 4)
5058 if (i386_record_floats (gdbarch
, &ir
,
5059 I387_FTAG_REGNUM (tdep
)))
5062 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5064 if ((ir
.modrm
& 0x0f) <= 7)
5066 if (i386_record_floats (gdbarch
, &ir
,
5067 I387_ST0_REGNUM (tdep
) +
5073 if (i386_record_floats (gdbarch
, &ir
,
5074 I386_SAVE_FPU_REGS
))
5080 if ((0x0c == ir
.modrm
>> 4)
5081 || (0x0e == ir
.modrm
>> 4)
5082 || (0x0f == ir
.modrm
>> 4)
5083 || (0xd9 == ir
.modrm
))
5085 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5090 if (0xe0 == ir
.modrm
)
5092 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5095 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5097 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5105 case 0xa4: /* movsS */
5107 case 0xaa: /* stosS */
5109 case 0x6c: /* insS */
5111 regcache_raw_read_unsigned (ir
.regcache
,
5112 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5118 if ((opcode
& 1) == 0)
5121 ir
.ot
= ir
.dflag
+ OT_WORD
;
5122 regcache_raw_read_unsigned (ir
.regcache
,
5123 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5126 regcache_raw_read_unsigned (ir
.regcache
,
5127 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5129 regcache_raw_read_unsigned (ir
.regcache
,
5130 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5132 if (ir
.aflag
&& (es
!= ds
))
5134 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5135 if (record_memory_query
)
5139 target_terminal_ours ();
5141 Process record ignores the memory change of instruction at address %s\n\
5142 because it can't get the value of the segment register.\n\
5143 Do you want to stop the program?"),
5144 paddress (gdbarch
, ir
.orig_addr
));
5145 target_terminal_inferior ();
5152 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5156 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5157 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5158 if (opcode
== 0xa4 || opcode
== 0xa5)
5159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5165 case 0xa6: /* cmpsS */
5167 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5168 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5169 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5171 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5174 case 0xac: /* lodsS */
5176 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5177 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5178 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5179 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5180 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5183 case 0xae: /* scasS */
5185 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5186 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5187 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5188 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5191 case 0x6e: /* outsS */
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5194 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5195 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5196 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5199 case 0xe4: /* port I/O */
5203 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5204 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5214 case 0xc2: /* ret im */
5215 case 0xc3: /* ret */
5216 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5220 case 0xca: /* lret im */
5221 case 0xcb: /* lret */
5222 case 0xcf: /* iret */
5223 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5224 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5225 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5228 case 0xe8: /* call im */
5229 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5231 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5235 case 0x9a: /* lcall im */
5236 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5241 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5242 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5246 case 0xe9: /* jmp im */
5247 case 0xea: /* ljmp im */
5248 case 0xeb: /* jmp Jb */
5249 case 0x70: /* jcc Jb */
5265 case 0x0f80: /* jcc Jv */
5283 case 0x0f90: /* setcc Gv */
5299 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5301 if (i386_record_modrm (&ir
))
5304 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5308 if (i386_record_lea_modrm (&ir
))
5313 case 0x0f40: /* cmov Gv, Ev */
5329 if (i386_record_modrm (&ir
))
5332 if (ir
.dflag
== OT_BYTE
)
5334 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5338 case 0x9c: /* pushf */
5339 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5340 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5342 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5346 case 0x9d: /* popf */
5347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5351 case 0x9e: /* sahf */
5352 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5358 case 0xf5: /* cmc */
5359 case 0xf8: /* clc */
5360 case 0xf9: /* stc */
5361 case 0xfc: /* cld */
5362 case 0xfd: /* std */
5363 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5366 case 0x9f: /* lahf */
5367 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5372 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5373 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5376 /* bit operations */
5377 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5378 ir
.ot
= ir
.dflag
+ OT_WORD
;
5379 if (i386_record_modrm (&ir
))
5384 opcode
= opcode
<< 8 | ir
.modrm
;
5390 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5393 if (i386_record_lea_modrm (&ir
))
5397 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5400 case 0x0fa3: /* bt Gv, Ev */
5401 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5404 case 0x0fab: /* bts */
5405 case 0x0fb3: /* btr */
5406 case 0x0fbb: /* btc */
5407 ir
.ot
= ir
.dflag
+ OT_WORD
;
5408 if (i386_record_modrm (&ir
))
5411 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5415 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5417 regcache_raw_read_unsigned (ir
.regcache
,
5418 ir
.regmap
[ir
.reg
| rex_r
],
5423 addr64
+= ((int16_t) addr
>> 4) << 4;
5426 addr64
+= ((int32_t) addr
>> 5) << 5;
5429 addr64
+= ((int64_t) addr
>> 6) << 6;
5432 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5434 if (i386_record_lea_modrm (&ir
))
5437 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5440 case 0x0fbc: /* bsf */
5441 case 0x0fbd: /* bsr */
5442 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5443 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5447 case 0x27: /* daa */
5448 case 0x2f: /* das */
5449 case 0x37: /* aaa */
5450 case 0x3f: /* aas */
5451 case 0xd4: /* aam */
5452 case 0xd5: /* aad */
5453 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5463 case 0x90: /* nop */
5464 if (prefixes
& PREFIX_LOCK
)
5471 case 0x9b: /* fwait */
5472 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5475 printf_unfiltered (_("Process record: error reading memory at "
5476 "addr 0x%s len = 1.\n"),
5477 paddress (gdbarch
, ir
.addr
));
5480 opcode
= (uint32_t) opcode8
;
5486 case 0xcc: /* int3 */
5487 printf_unfiltered (_("Process record does not support instruction "
5494 case 0xcd: /* int */
5498 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5501 printf_unfiltered (_("Process record: error reading memory "
5502 "at addr %s len = 1.\n"),
5503 paddress (gdbarch
, ir
.addr
));
5507 if (interrupt
!= 0x80
5508 || tdep
->i386_intx80_record
== NULL
)
5510 printf_unfiltered (_("Process record does not support "
5511 "instruction int 0x%02x.\n"),
5516 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5523 case 0xce: /* into */
5524 printf_unfiltered (_("Process record does not support "
5525 "instruction into.\n"));
5530 case 0xfa: /* cli */
5531 case 0xfb: /* sti */
5534 case 0x62: /* bound */
5535 printf_unfiltered (_("Process record does not support "
5536 "instruction bound.\n"));
5541 case 0x0fc8: /* bswap reg */
5549 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5552 case 0xd6: /* salc */
5553 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5562 case 0xe0: /* loopnz */
5563 case 0xe1: /* loopz */
5564 case 0xe2: /* loop */
5565 case 0xe3: /* jecxz */
5566 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5567 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5570 case 0x0f30: /* wrmsr */
5571 printf_unfiltered (_("Process record does not support "
5572 "instruction wrmsr.\n"));
5577 case 0x0f32: /* rdmsr */
5578 printf_unfiltered (_("Process record does not support "
5579 "instruction rdmsr.\n"));
5584 case 0x0f31: /* rdtsc */
5585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5586 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5589 case 0x0f34: /* sysenter */
5592 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5597 if (tdep
->i386_sysenter_record
== NULL
)
5599 printf_unfiltered (_("Process record does not support "
5600 "instruction sysenter.\n"));
5604 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5610 case 0x0f35: /* sysexit */
5611 printf_unfiltered (_("Process record does not support "
5612 "instruction sysexit.\n"));
5617 case 0x0f05: /* syscall */
5620 if (tdep
->i386_syscall_record
== NULL
)
5622 printf_unfiltered (_("Process record does not support "
5623 "instruction syscall.\n"));
5627 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5633 case 0x0f07: /* sysret */
5634 printf_unfiltered (_("Process record does not support "
5635 "instruction sysret.\n"));
5640 case 0x0fa2: /* cpuid */
5641 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5642 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5643 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5644 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5647 case 0xf4: /* hlt */
5648 printf_unfiltered (_("Process record does not support "
5649 "instruction hlt.\n"));
5655 if (i386_record_modrm (&ir
))
5662 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5666 if (i386_record_lea_modrm (&ir
))
5675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5679 opcode
= opcode
<< 8 | ir
.modrm
;
5686 if (i386_record_modrm (&ir
))
5697 opcode
= opcode
<< 8 | ir
.modrm
;
5700 if (ir
.override
>= 0)
5702 if (record_memory_query
)
5706 target_terminal_ours ();
5708 Process record ignores the memory change of instruction at address %s\n\
5709 because it can't get the value of the segment register.\n\
5710 Do you want to stop the program?"),
5711 paddress (gdbarch
, ir
.orig_addr
));
5712 target_terminal_inferior ();
5719 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5721 if (record_arch_list_add_mem (addr64
, 2))
5724 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5726 if (record_arch_list_add_mem (addr64
, 8))
5731 if (record_arch_list_add_mem (addr64
, 4))
5742 case 0: /* monitor */
5745 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5749 opcode
= opcode
<< 8 | ir
.modrm
;
5757 if (ir
.override
>= 0)
5759 if (record_memory_query
)
5763 target_terminal_ours ();
5765 Process record ignores the memory change of instruction at address %s\n\
5766 because it can't get the value of the segment register.\n\
5767 Do you want to stop the program?"),
5768 paddress (gdbarch
, ir
.orig_addr
));
5769 target_terminal_inferior ();
5778 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5780 if (record_arch_list_add_mem (addr64
, 2))
5783 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5785 if (record_arch_list_add_mem (addr64
, 8))
5790 if (record_arch_list_add_mem (addr64
, 4))
5802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5807 else if (ir
.rm
== 1)
5814 opcode
= opcode
<< 8 | ir
.modrm
;
5821 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5827 if (i386_record_lea_modrm (&ir
))
5830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5833 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5835 case 7: /* invlpg */
5838 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5839 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5843 opcode
= opcode
<< 8 | ir
.modrm
;
5848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5852 opcode
= opcode
<< 8 | ir
.modrm
;
5858 case 0x0f08: /* invd */
5859 case 0x0f09: /* wbinvd */
5862 case 0x63: /* arpl */
5863 if (i386_record_modrm (&ir
))
5865 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5867 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5868 ? (ir
.reg
| rex_r
) : ir
.rm
);
5872 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5873 if (i386_record_lea_modrm (&ir
))
5876 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5877 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5880 case 0x0f02: /* lar */
5881 case 0x0f03: /* lsl */
5882 if (i386_record_modrm (&ir
))
5884 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5885 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5889 if (i386_record_modrm (&ir
))
5891 if (ir
.mod
== 3 && ir
.reg
== 3)
5894 opcode
= opcode
<< 8 | ir
.modrm
;
5906 /* nop (multi byte) */
5909 case 0x0f20: /* mov reg, crN */
5910 case 0x0f22: /* mov crN, reg */
5911 if (i386_record_modrm (&ir
))
5913 if ((ir
.modrm
& 0xc0) != 0xc0)
5916 opcode
= opcode
<< 8 | ir
.modrm
;
5927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5929 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5933 opcode
= opcode
<< 8 | ir
.modrm
;
5939 case 0x0f21: /* mov reg, drN */
5940 case 0x0f23: /* mov drN, reg */
5941 if (i386_record_modrm (&ir
))
5943 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5944 || ir
.reg
== 5 || ir
.reg
>= 8)
5947 opcode
= opcode
<< 8 | ir
.modrm
;
5951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5953 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5956 case 0x0f06: /* clts */
5957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5960 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5962 case 0x0f0d: /* 3DNow! prefetch */
5965 case 0x0f0e: /* 3DNow! femms */
5966 case 0x0f77: /* emms */
5967 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
5969 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
5972 case 0x0f0f: /* 3DNow! data */
5973 if (i386_record_modrm (&ir
))
5975 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5977 printf_unfiltered (_("Process record: error reading memory at "
5978 "addr %s len = 1.\n"),
5979 paddress (gdbarch
, ir
.addr
));
5985 case 0x0c: /* 3DNow! pi2fw */
5986 case 0x0d: /* 3DNow! pi2fd */
5987 case 0x1c: /* 3DNow! pf2iw */
5988 case 0x1d: /* 3DNow! pf2id */
5989 case 0x8a: /* 3DNow! pfnacc */
5990 case 0x8e: /* 3DNow! pfpnacc */
5991 case 0x90: /* 3DNow! pfcmpge */
5992 case 0x94: /* 3DNow! pfmin */
5993 case 0x96: /* 3DNow! pfrcp */
5994 case 0x97: /* 3DNow! pfrsqrt */
5995 case 0x9a: /* 3DNow! pfsub */
5996 case 0x9e: /* 3DNow! pfadd */
5997 case 0xa0: /* 3DNow! pfcmpgt */
5998 case 0xa4: /* 3DNow! pfmax */
5999 case 0xa6: /* 3DNow! pfrcpit1 */
6000 case 0xa7: /* 3DNow! pfrsqit1 */
6001 case 0xaa: /* 3DNow! pfsubr */
6002 case 0xae: /* 3DNow! pfacc */
6003 case 0xb0: /* 3DNow! pfcmpeq */
6004 case 0xb4: /* 3DNow! pfmul */
6005 case 0xb6: /* 3DNow! pfrcpit2 */
6006 case 0xb7: /* 3DNow! pmulhrw */
6007 case 0xbb: /* 3DNow! pswapd */
6008 case 0xbf: /* 3DNow! pavgusb */
6009 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6010 goto no_support_3dnow_data
;
6011 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6015 no_support_3dnow_data
:
6016 opcode
= (opcode
<< 8) | opcode8
;
6022 case 0x0faa: /* rsm */
6023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6025 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6026 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6027 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6028 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6030 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6031 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6035 if (i386_record_modrm (&ir
))
6039 case 0: /* fxsave */
6043 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6044 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6046 if (record_arch_list_add_mem (tmpu64
, 512))
6051 case 1: /* fxrstor */
6055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6057 for (i
= I387_MM0_REGNUM (tdep
);
6058 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6059 record_arch_list_add_reg (ir
.regcache
, i
);
6061 for (i
= I387_XMM0_REGNUM (tdep
);
6062 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6063 record_arch_list_add_reg (ir
.regcache
, i
);
6065 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6066 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6068 for (i
= I387_ST0_REGNUM (tdep
);
6069 i386_fp_regnum_p (gdbarch
, i
); i
++)
6070 record_arch_list_add_reg (ir
.regcache
, i
);
6072 for (i
= I387_FCTRL_REGNUM (tdep
);
6073 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6074 record_arch_list_add_reg (ir
.regcache
, i
);
6078 case 2: /* ldmxcsr */
6079 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6081 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6084 case 3: /* stmxcsr */
6086 if (i386_record_lea_modrm (&ir
))
6090 case 5: /* lfence */
6091 case 6: /* mfence */
6092 case 7: /* sfence clflush */
6096 opcode
= (opcode
<< 8) | ir
.modrm
;
6102 case 0x0fc3: /* movnti */
6103 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6104 if (i386_record_modrm (&ir
))
6109 if (i386_record_lea_modrm (&ir
))
6113 /* Add prefix to opcode. */
6240 reswitch_prefix_add
:
6248 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6250 printf_unfiltered (_("Process record: error reading memory at "
6251 "addr %s len = 1.\n"),
6252 paddress (gdbarch
, ir
.addr
));
6256 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6257 goto reswitch_prefix_add
;
6260 case 0x0f10: /* movups */
6261 case 0x660f10: /* movupd */
6262 case 0xf30f10: /* movss */
6263 case 0xf20f10: /* movsd */
6264 case 0x0f12: /* movlps */
6265 case 0x660f12: /* movlpd */
6266 case 0xf30f12: /* movsldup */
6267 case 0xf20f12: /* movddup */
6268 case 0x0f14: /* unpcklps */
6269 case 0x660f14: /* unpcklpd */
6270 case 0x0f15: /* unpckhps */
6271 case 0x660f15: /* unpckhpd */
6272 case 0x0f16: /* movhps */
6273 case 0x660f16: /* movhpd */
6274 case 0xf30f16: /* movshdup */
6275 case 0x0f28: /* movaps */
6276 case 0x660f28: /* movapd */
6277 case 0x0f2a: /* cvtpi2ps */
6278 case 0x660f2a: /* cvtpi2pd */
6279 case 0xf30f2a: /* cvtsi2ss */
6280 case 0xf20f2a: /* cvtsi2sd */
6281 case 0x0f2c: /* cvttps2pi */
6282 case 0x660f2c: /* cvttpd2pi */
6283 case 0x0f2d: /* cvtps2pi */
6284 case 0x660f2d: /* cvtpd2pi */
6285 case 0x660f3800: /* pshufb */
6286 case 0x660f3801: /* phaddw */
6287 case 0x660f3802: /* phaddd */
6288 case 0x660f3803: /* phaddsw */
6289 case 0x660f3804: /* pmaddubsw */
6290 case 0x660f3805: /* phsubw */
6291 case 0x660f3806: /* phsubd */
6292 case 0x660f3807: /* phsubsw */
6293 case 0x660f3808: /* psignb */
6294 case 0x660f3809: /* psignw */
6295 case 0x660f380a: /* psignd */
6296 case 0x660f380b: /* pmulhrsw */
6297 case 0x660f3810: /* pblendvb */
6298 case 0x660f3814: /* blendvps */
6299 case 0x660f3815: /* blendvpd */
6300 case 0x660f381c: /* pabsb */
6301 case 0x660f381d: /* pabsw */
6302 case 0x660f381e: /* pabsd */
6303 case 0x660f3820: /* pmovsxbw */
6304 case 0x660f3821: /* pmovsxbd */
6305 case 0x660f3822: /* pmovsxbq */
6306 case 0x660f3823: /* pmovsxwd */
6307 case 0x660f3824: /* pmovsxwq */
6308 case 0x660f3825: /* pmovsxdq */
6309 case 0x660f3828: /* pmuldq */
6310 case 0x660f3829: /* pcmpeqq */
6311 case 0x660f382a: /* movntdqa */
6312 case 0x660f3a08: /* roundps */
6313 case 0x660f3a09: /* roundpd */
6314 case 0x660f3a0a: /* roundss */
6315 case 0x660f3a0b: /* roundsd */
6316 case 0x660f3a0c: /* blendps */
6317 case 0x660f3a0d: /* blendpd */
6318 case 0x660f3a0e: /* pblendw */
6319 case 0x660f3a0f: /* palignr */
6320 case 0x660f3a20: /* pinsrb */
6321 case 0x660f3a21: /* insertps */
6322 case 0x660f3a22: /* pinsrd pinsrq */
6323 case 0x660f3a40: /* dpps */
6324 case 0x660f3a41: /* dppd */
6325 case 0x660f3a42: /* mpsadbw */
6326 case 0x660f3a60: /* pcmpestrm */
6327 case 0x660f3a61: /* pcmpestri */
6328 case 0x660f3a62: /* pcmpistrm */
6329 case 0x660f3a63: /* pcmpistri */
6330 case 0x0f51: /* sqrtps */
6331 case 0x660f51: /* sqrtpd */
6332 case 0xf20f51: /* sqrtsd */
6333 case 0xf30f51: /* sqrtss */
6334 case 0x0f52: /* rsqrtps */
6335 case 0xf30f52: /* rsqrtss */
6336 case 0x0f53: /* rcpps */
6337 case 0xf30f53: /* rcpss */
6338 case 0x0f54: /* andps */
6339 case 0x660f54: /* andpd */
6340 case 0x0f55: /* andnps */
6341 case 0x660f55: /* andnpd */
6342 case 0x0f56: /* orps */
6343 case 0x660f56: /* orpd */
6344 case 0x0f57: /* xorps */
6345 case 0x660f57: /* xorpd */
6346 case 0x0f58: /* addps */
6347 case 0x660f58: /* addpd */
6348 case 0xf20f58: /* addsd */
6349 case 0xf30f58: /* addss */
6350 case 0x0f59: /* mulps */
6351 case 0x660f59: /* mulpd */
6352 case 0xf20f59: /* mulsd */
6353 case 0xf30f59: /* mulss */
6354 case 0x0f5a: /* cvtps2pd */
6355 case 0x660f5a: /* cvtpd2ps */
6356 case 0xf20f5a: /* cvtsd2ss */
6357 case 0xf30f5a: /* cvtss2sd */
6358 case 0x0f5b: /* cvtdq2ps */
6359 case 0x660f5b: /* cvtps2dq */
6360 case 0xf30f5b: /* cvttps2dq */
6361 case 0x0f5c: /* subps */
6362 case 0x660f5c: /* subpd */
6363 case 0xf20f5c: /* subsd */
6364 case 0xf30f5c: /* subss */
6365 case 0x0f5d: /* minps */
6366 case 0x660f5d: /* minpd */
6367 case 0xf20f5d: /* minsd */
6368 case 0xf30f5d: /* minss */
6369 case 0x0f5e: /* divps */
6370 case 0x660f5e: /* divpd */
6371 case 0xf20f5e: /* divsd */
6372 case 0xf30f5e: /* divss */
6373 case 0x0f5f: /* maxps */
6374 case 0x660f5f: /* maxpd */
6375 case 0xf20f5f: /* maxsd */
6376 case 0xf30f5f: /* maxss */
6377 case 0x660f60: /* punpcklbw */
6378 case 0x660f61: /* punpcklwd */
6379 case 0x660f62: /* punpckldq */
6380 case 0x660f63: /* packsswb */
6381 case 0x660f64: /* pcmpgtb */
6382 case 0x660f65: /* pcmpgtw */
6383 case 0x660f66: /* pcmpgtd */
6384 case 0x660f67: /* packuswb */
6385 case 0x660f68: /* punpckhbw */
6386 case 0x660f69: /* punpckhwd */
6387 case 0x660f6a: /* punpckhdq */
6388 case 0x660f6b: /* packssdw */
6389 case 0x660f6c: /* punpcklqdq */
6390 case 0x660f6d: /* punpckhqdq */
6391 case 0x660f6e: /* movd */
6392 case 0x660f6f: /* movdqa */
6393 case 0xf30f6f: /* movdqu */
6394 case 0x660f70: /* pshufd */
6395 case 0xf20f70: /* pshuflw */
6396 case 0xf30f70: /* pshufhw */
6397 case 0x660f74: /* pcmpeqb */
6398 case 0x660f75: /* pcmpeqw */
6399 case 0x660f76: /* pcmpeqd */
6400 case 0x660f7c: /* haddpd */
6401 case 0xf20f7c: /* haddps */
6402 case 0x660f7d: /* hsubpd */
6403 case 0xf20f7d: /* hsubps */
6404 case 0xf30f7e: /* movq */
6405 case 0x0fc2: /* cmpps */
6406 case 0x660fc2: /* cmppd */
6407 case 0xf20fc2: /* cmpsd */
6408 case 0xf30fc2: /* cmpss */
6409 case 0x660fc4: /* pinsrw */
6410 case 0x0fc6: /* shufps */
6411 case 0x660fc6: /* shufpd */
6412 case 0x660fd0: /* addsubpd */
6413 case 0xf20fd0: /* addsubps */
6414 case 0x660fd1: /* psrlw */
6415 case 0x660fd2: /* psrld */
6416 case 0x660fd3: /* psrlq */
6417 case 0x660fd4: /* paddq */
6418 case 0x660fd5: /* pmullw */
6419 case 0xf30fd6: /* movq2dq */
6420 case 0x660fd8: /* psubusb */
6421 case 0x660fd9: /* psubusw */
6422 case 0x660fda: /* pminub */
6423 case 0x660fdb: /* pand */
6424 case 0x660fdc: /* paddusb */
6425 case 0x660fdd: /* paddusw */
6426 case 0x660fde: /* pmaxub */
6427 case 0x660fdf: /* pandn */
6428 case 0x660fe0: /* pavgb */
6429 case 0x660fe1: /* psraw */
6430 case 0x660fe2: /* psrad */
6431 case 0x660fe3: /* pavgw */
6432 case 0x660fe4: /* pmulhuw */
6433 case 0x660fe5: /* pmulhw */
6434 case 0x660fe6: /* cvttpd2dq */
6435 case 0xf20fe6: /* cvtpd2dq */
6436 case 0xf30fe6: /* cvtdq2pd */
6437 case 0x660fe8: /* psubsb */
6438 case 0x660fe9: /* psubsw */
6439 case 0x660fea: /* pminsw */
6440 case 0x660feb: /* por */
6441 case 0x660fec: /* paddsb */
6442 case 0x660fed: /* paddsw */
6443 case 0x660fee: /* pmaxsw */
6444 case 0x660fef: /* pxor */
6445 case 0xf20ff0: /* lddqu */
6446 case 0x660ff1: /* psllw */
6447 case 0x660ff2: /* pslld */
6448 case 0x660ff3: /* psllq */
6449 case 0x660ff4: /* pmuludq */
6450 case 0x660ff5: /* pmaddwd */
6451 case 0x660ff6: /* psadbw */
6452 case 0x660ff8: /* psubb */
6453 case 0x660ff9: /* psubw */
6454 case 0x660ffa: /* psubd */
6455 case 0x660ffb: /* psubq */
6456 case 0x660ffc: /* paddb */
6457 case 0x660ffd: /* paddw */
6458 case 0x660ffe: /* paddd */
6459 if (i386_record_modrm (&ir
))
6462 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6464 record_arch_list_add_reg (ir
.regcache
,
6465 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6466 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6467 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6470 case 0x0f11: /* movups */
6471 case 0x660f11: /* movupd */
6472 case 0xf30f11: /* movss */
6473 case 0xf20f11: /* movsd */
6474 case 0x0f13: /* movlps */
6475 case 0x660f13: /* movlpd */
6476 case 0x0f17: /* movhps */
6477 case 0x660f17: /* movhpd */
6478 case 0x0f29: /* movaps */
6479 case 0x660f29: /* movapd */
6480 case 0x660f3a14: /* pextrb */
6481 case 0x660f3a15: /* pextrw */
6482 case 0x660f3a16: /* pextrd pextrq */
6483 case 0x660f3a17: /* extractps */
6484 case 0x660f7f: /* movdqa */
6485 case 0xf30f7f: /* movdqu */
6486 if (i386_record_modrm (&ir
))
6490 if (opcode
== 0x0f13 || opcode
== 0x660f13
6491 || opcode
== 0x0f17 || opcode
== 0x660f17)
6494 if (!i386_xmm_regnum_p (gdbarch
,
6495 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6497 record_arch_list_add_reg (ir
.regcache
,
6498 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6520 if (i386_record_lea_modrm (&ir
))
6525 case 0x0f2b: /* movntps */
6526 case 0x660f2b: /* movntpd */
6527 case 0x0fe7: /* movntq */
6528 case 0x660fe7: /* movntdq */
6531 if (opcode
== 0x0fe7)
6535 if (i386_record_lea_modrm (&ir
))
6539 case 0xf30f2c: /* cvttss2si */
6540 case 0xf20f2c: /* cvttsd2si */
6541 case 0xf30f2d: /* cvtss2si */
6542 case 0xf20f2d: /* cvtsd2si */
6543 case 0xf20f38f0: /* crc32 */
6544 case 0xf20f38f1: /* crc32 */
6545 case 0x0f50: /* movmskps */
6546 case 0x660f50: /* movmskpd */
6547 case 0x0fc5: /* pextrw */
6548 case 0x660fc5: /* pextrw */
6549 case 0x0fd7: /* pmovmskb */
6550 case 0x660fd7: /* pmovmskb */
6551 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6554 case 0x0f3800: /* pshufb */
6555 case 0x0f3801: /* phaddw */
6556 case 0x0f3802: /* phaddd */
6557 case 0x0f3803: /* phaddsw */
6558 case 0x0f3804: /* pmaddubsw */
6559 case 0x0f3805: /* phsubw */
6560 case 0x0f3806: /* phsubd */
6561 case 0x0f3807: /* phsubsw */
6562 case 0x0f3808: /* psignb */
6563 case 0x0f3809: /* psignw */
6564 case 0x0f380a: /* psignd */
6565 case 0x0f380b: /* pmulhrsw */
6566 case 0x0f381c: /* pabsb */
6567 case 0x0f381d: /* pabsw */
6568 case 0x0f381e: /* pabsd */
6569 case 0x0f382b: /* packusdw */
6570 case 0x0f3830: /* pmovzxbw */
6571 case 0x0f3831: /* pmovzxbd */
6572 case 0x0f3832: /* pmovzxbq */
6573 case 0x0f3833: /* pmovzxwd */
6574 case 0x0f3834: /* pmovzxwq */
6575 case 0x0f3835: /* pmovzxdq */
6576 case 0x0f3837: /* pcmpgtq */
6577 case 0x0f3838: /* pminsb */
6578 case 0x0f3839: /* pminsd */
6579 case 0x0f383a: /* pminuw */
6580 case 0x0f383b: /* pminud */
6581 case 0x0f383c: /* pmaxsb */
6582 case 0x0f383d: /* pmaxsd */
6583 case 0x0f383e: /* pmaxuw */
6584 case 0x0f383f: /* pmaxud */
6585 case 0x0f3840: /* pmulld */
6586 case 0x0f3841: /* phminposuw */
6587 case 0x0f3a0f: /* palignr */
6588 case 0x0f60: /* punpcklbw */
6589 case 0x0f61: /* punpcklwd */
6590 case 0x0f62: /* punpckldq */
6591 case 0x0f63: /* packsswb */
6592 case 0x0f64: /* pcmpgtb */
6593 case 0x0f65: /* pcmpgtw */
6594 case 0x0f66: /* pcmpgtd */
6595 case 0x0f67: /* packuswb */
6596 case 0x0f68: /* punpckhbw */
6597 case 0x0f69: /* punpckhwd */
6598 case 0x0f6a: /* punpckhdq */
6599 case 0x0f6b: /* packssdw */
6600 case 0x0f6e: /* movd */
6601 case 0x0f6f: /* movq */
6602 case 0x0f70: /* pshufw */
6603 case 0x0f74: /* pcmpeqb */
6604 case 0x0f75: /* pcmpeqw */
6605 case 0x0f76: /* pcmpeqd */
6606 case 0x0fc4: /* pinsrw */
6607 case 0x0fd1: /* psrlw */
6608 case 0x0fd2: /* psrld */
6609 case 0x0fd3: /* psrlq */
6610 case 0x0fd4: /* paddq */
6611 case 0x0fd5: /* pmullw */
6612 case 0xf20fd6: /* movdq2q */
6613 case 0x0fd8: /* psubusb */
6614 case 0x0fd9: /* psubusw */
6615 case 0x0fda: /* pminub */
6616 case 0x0fdb: /* pand */
6617 case 0x0fdc: /* paddusb */
6618 case 0x0fdd: /* paddusw */
6619 case 0x0fde: /* pmaxub */
6620 case 0x0fdf: /* pandn */
6621 case 0x0fe0: /* pavgb */
6622 case 0x0fe1: /* psraw */
6623 case 0x0fe2: /* psrad */
6624 case 0x0fe3: /* pavgw */
6625 case 0x0fe4: /* pmulhuw */
6626 case 0x0fe5: /* pmulhw */
6627 case 0x0fe8: /* psubsb */
6628 case 0x0fe9: /* psubsw */
6629 case 0x0fea: /* pminsw */
6630 case 0x0feb: /* por */
6631 case 0x0fec: /* paddsb */
6632 case 0x0fed: /* paddsw */
6633 case 0x0fee: /* pmaxsw */
6634 case 0x0fef: /* pxor */
6635 case 0x0ff1: /* psllw */
6636 case 0x0ff2: /* pslld */
6637 case 0x0ff3: /* psllq */
6638 case 0x0ff4: /* pmuludq */
6639 case 0x0ff5: /* pmaddwd */
6640 case 0x0ff6: /* psadbw */
6641 case 0x0ff8: /* psubb */
6642 case 0x0ff9: /* psubw */
6643 case 0x0ffa: /* psubd */
6644 case 0x0ffb: /* psubq */
6645 case 0x0ffc: /* paddb */
6646 case 0x0ffd: /* paddw */
6647 case 0x0ffe: /* paddd */
6648 if (i386_record_modrm (&ir
))
6650 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6652 record_arch_list_add_reg (ir
.regcache
,
6653 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6656 case 0x0f71: /* psllw */
6657 case 0x0f72: /* pslld */
6658 case 0x0f73: /* psllq */
6659 if (i386_record_modrm (&ir
))
6661 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6663 record_arch_list_add_reg (ir
.regcache
,
6664 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6667 case 0x660f71: /* psllw */
6668 case 0x660f72: /* pslld */
6669 case 0x660f73: /* psllq */
6670 if (i386_record_modrm (&ir
))
6673 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6675 record_arch_list_add_reg (ir
.regcache
,
6676 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6679 case 0x0f7e: /* movd */
6680 case 0x660f7e: /* movd */
6681 if (i386_record_modrm (&ir
))
6684 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6691 if (i386_record_lea_modrm (&ir
))
6696 case 0x0f7f: /* movq */
6697 if (i386_record_modrm (&ir
))
6701 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6703 record_arch_list_add_reg (ir
.regcache
,
6704 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6709 if (i386_record_lea_modrm (&ir
))
6714 case 0xf30fb8: /* popcnt */
6715 if (i386_record_modrm (&ir
))
6717 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6718 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6721 case 0x660fd6: /* movq */
6722 if (i386_record_modrm (&ir
))
6727 if (!i386_xmm_regnum_p (gdbarch
,
6728 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6730 record_arch_list_add_reg (ir
.regcache
,
6731 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6736 if (i386_record_lea_modrm (&ir
))
6741 case 0x660f3817: /* ptest */
6742 case 0x0f2e: /* ucomiss */
6743 case 0x660f2e: /* ucomisd */
6744 case 0x0f2f: /* comiss */
6745 case 0x660f2f: /* comisd */
6746 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6749 case 0x0ff7: /* maskmovq */
6750 regcache_raw_read_unsigned (ir
.regcache
,
6751 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6753 if (record_arch_list_add_mem (addr
, 64))
6757 case 0x660ff7: /* maskmovdqu */
6758 regcache_raw_read_unsigned (ir
.regcache
,
6759 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6761 if (record_arch_list_add_mem (addr
, 128))
6776 /* In the future, maybe still need to deal with need_dasm. */
6777 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6778 if (record_arch_list_add_end ())
6784 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6785 "at address %s.\n"),
6786 (unsigned int) (opcode
),
6787 paddress (gdbarch
, ir
.orig_addr
));
6791 static const int i386_record_regmap
[] =
6793 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6794 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6795 0, 0, 0, 0, 0, 0, 0, 0,
6796 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6797 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6800 /* Check that the given address appears suitable for a fast
6801 tracepoint, which on x86 means that we need an instruction of at
6802 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6803 jump and not have to worry about program jumps to an address in the
6804 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6805 of instruction to replace, and 0 if not, plus an explanatory
6809 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6810 CORE_ADDR addr
, int *isize
, char **msg
)
6813 static struct ui_file
*gdb_null
= NULL
;
6815 /* This is based on the target agent using a 4-byte relative jump.
6816 Alternate future possibilities include 8-byte offset for x86-84,
6817 or 3-byte jumps if the program has trampoline space close by. */
6820 /* Dummy file descriptor for the disassembler. */
6822 gdb_null
= ui_file_new ();
6824 /* Check for fit. */
6825 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6828 /* Return a bit of target-specific detail to add to the caller's
6829 generic failure message. */
6831 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
6832 "need at least %d bytes for the jump"),
6845 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6846 struct tdesc_arch_data
*tdesc_data
)
6848 const struct target_desc
*tdesc
= tdep
->tdesc
;
6849 const struct tdesc_feature
*feature_core
;
6850 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6851 int i
, num_regs
, valid_p
;
6853 if (! tdesc_has_registers (tdesc
))
6856 /* Get core registers. */
6857 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6858 if (feature_core
== NULL
)
6861 /* Get SSE registers. */
6862 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6864 /* Try AVX registers. */
6865 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6869 /* The XCR0 bits. */
6872 /* AVX register description requires SSE register description. */
6876 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6878 /* It may have been set by OSABI initialization function. */
6879 if (tdep
->num_ymm_regs
== 0)
6881 tdep
->ymmh_register_names
= i386_ymmh_names
;
6882 tdep
->num_ymm_regs
= 8;
6883 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
6886 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
6887 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
6888 tdep
->ymm0h_regnum
+ i
,
6889 tdep
->ymmh_register_names
[i
]);
6891 else if (feature_sse
)
6892 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
6895 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
6896 tdep
->num_xmm_regs
= 0;
6899 num_regs
= tdep
->num_core_regs
;
6900 for (i
= 0; i
< num_regs
; i
++)
6901 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
6902 tdep
->register_names
[i
]);
6906 /* Need to include %mxcsr, so add one. */
6907 num_regs
+= tdep
->num_xmm_regs
+ 1;
6908 for (; i
< num_regs
; i
++)
6909 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
6910 tdep
->register_names
[i
]);
6917 static struct gdbarch
*
6918 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6920 struct gdbarch_tdep
*tdep
;
6921 struct gdbarch
*gdbarch
;
6922 struct tdesc_arch_data
*tdesc_data
;
6923 const struct target_desc
*tdesc
;
6927 /* If there is already a candidate, use it. */
6928 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6930 return arches
->gdbarch
;
6932 /* Allocate space for the new architecture. */
6933 tdep
= XCALLOC (1, struct gdbarch_tdep
);
6934 gdbarch
= gdbarch_alloc (&info
, tdep
);
6936 /* General-purpose registers. */
6937 tdep
->gregset
= NULL
;
6938 tdep
->gregset_reg_offset
= NULL
;
6939 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
6940 tdep
->sizeof_gregset
= 0;
6942 /* Floating-point registers. */
6943 tdep
->fpregset
= NULL
;
6944 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
6946 tdep
->xstateregset
= NULL
;
6948 /* The default settings include the FPU registers, the MMX registers
6949 and the SSE registers. This can be overridden for a specific ABI
6950 by adjusting the members `st0_regnum', `mm0_regnum' and
6951 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6952 will show up in the output of "info all-registers". */
6954 tdep
->st0_regnum
= I386_ST0_REGNUM
;
6956 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6957 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
6959 tdep
->jb_pc_offset
= -1;
6960 tdep
->struct_return
= pcc_struct_return
;
6961 tdep
->sigtramp_start
= 0;
6962 tdep
->sigtramp_end
= 0;
6963 tdep
->sigtramp_p
= i386_sigtramp_p
;
6964 tdep
->sigcontext_addr
= NULL
;
6965 tdep
->sc_reg_offset
= NULL
;
6966 tdep
->sc_pc_offset
= -1;
6967 tdep
->sc_sp_offset
= -1;
6969 tdep
->xsave_xcr0_offset
= -1;
6971 tdep
->record_regmap
= i386_record_regmap
;
6973 /* The format used for `long double' on almost all i386 targets is
6974 the i387 extended floating-point format. In fact, of all targets
6975 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6976 on having a `long double' that's not `long' at all. */
6977 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
6979 /* Although the i387 extended floating-point has only 80 significant
6980 bits, a `long double' actually takes up 96, probably to enforce
6982 set_gdbarch_long_double_bit (gdbarch
, 96);
6984 /* Register numbers of various important registers. */
6985 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
6986 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
6987 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
6988 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
6990 /* NOTE: kettenis/20040418: GCC does have two possible register
6991 numbering schemes on the i386: dbx and SVR4. These schemes
6992 differ in how they number %ebp, %esp, %eflags, and the
6993 floating-point registers, and are implemented by the arrays
6994 dbx_register_map[] and svr4_dbx_register_map in
6995 gcc/config/i386.c. GCC also defines a third numbering scheme in
6996 gcc/config/i386.c, which it designates as the "default" register
6997 map used in 64bit mode. This last register numbering scheme is
6998 implemented in dbx64_register_map, and is used for AMD64; see
7001 Currently, each GCC i386 target always uses the same register
7002 numbering scheme across all its supported debugging formats
7003 i.e. SDB (COFF), stabs and DWARF 2. This is because
7004 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7005 DBX_REGISTER_NUMBER macro which is defined by each target's
7006 respective config header in a manner independent of the requested
7007 output debugging format.
7009 This does not match the arrangement below, which presumes that
7010 the SDB and stabs numbering schemes differ from the DWARF and
7011 DWARF 2 ones. The reason for this arrangement is that it is
7012 likely to get the numbering scheme for the target's
7013 default/native debug format right. For targets where GCC is the
7014 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7015 targets where the native toolchain uses a different numbering
7016 scheme for a particular debug format (stabs-in-ELF on Solaris)
7017 the defaults below will have to be overridden, like
7018 i386_elf_init_abi() does. */
7020 /* Use the dbx register numbering scheme for stabs and COFF. */
7021 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7022 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7024 /* Use the SVR4 register numbering scheme for DWARF 2. */
7025 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7027 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7028 be in use on any of the supported i386 targets. */
7030 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7032 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7034 /* Call dummy code. */
7035 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7037 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7038 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7039 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7041 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7043 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7045 /* Stack grows downward. */
7046 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7048 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7049 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7050 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7052 set_gdbarch_frame_args_skip (gdbarch
, 8);
7054 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7056 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7058 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7060 /* Add the i386 register groups. */
7061 i386_add_reggroups (gdbarch
);
7062 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7064 /* Helper for function argument information. */
7065 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7067 /* Hook the function epilogue frame unwinder. This unwinder is
7068 appended to the list first, so that it supercedes the Dwarf
7069 unwinder in function epilogues (where the Dwarf unwinder
7070 currently fails). */
7071 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7073 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7074 to the list before the prologue-based unwinders, so that Dwarf
7075 CFI info will be used if it is available. */
7076 dwarf2_append_unwinders (gdbarch
);
7078 frame_base_set_default (gdbarch
, &i386_frame_base
);
7080 /* Pseudo registers may be changed by amd64_init_abi. */
7081 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7082 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7084 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7085 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7087 /* Override the normal target description method to make the AVX
7088 upper halves anonymous. */
7089 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7091 /* Even though the default ABI only includes general-purpose registers,
7092 floating-point registers and the SSE registers, we have to leave a
7093 gap for the upper AVX registers. */
7094 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7096 /* Get the x86 target description from INFO. */
7097 tdesc
= info
.target_desc
;
7098 if (! tdesc_has_registers (tdesc
))
7100 tdep
->tdesc
= tdesc
;
7102 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7103 tdep
->register_names
= i386_register_names
;
7105 /* No upper YMM registers. */
7106 tdep
->ymmh_register_names
= NULL
;
7107 tdep
->ymm0h_regnum
= -1;
7109 tdep
->num_byte_regs
= 8;
7110 tdep
->num_word_regs
= 8;
7111 tdep
->num_dword_regs
= 0;
7112 tdep
->num_mmx_regs
= 8;
7113 tdep
->num_ymm_regs
= 0;
7115 tdesc_data
= tdesc_data_alloc ();
7117 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7119 /* Hook in ABI-specific overrides, if they have been registered. */
7120 info
.tdep_info
= (void *) tdesc_data
;
7121 gdbarch_init_osabi (info
, gdbarch
);
7123 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7125 tdesc_data_cleanup (tdesc_data
);
7127 gdbarch_free (gdbarch
);
7131 /* Wire in pseudo registers. Number of pseudo registers may be
7133 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7134 + tdep
->num_word_regs
7135 + tdep
->num_dword_regs
7136 + tdep
->num_mmx_regs
7137 + tdep
->num_ymm_regs
));
7139 /* Target description may be changed. */
7140 tdesc
= tdep
->tdesc
;
7142 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7144 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7145 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7147 /* Make %al the first pseudo-register. */
7148 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7149 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7151 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7152 if (tdep
->num_dword_regs
)
7154 /* Support dword pseudo-register if it hasn't been disabled. */
7155 tdep
->eax_regnum
= ymm0_regnum
;
7156 ymm0_regnum
+= tdep
->num_dword_regs
;
7159 tdep
->eax_regnum
= -1;
7161 mm0_regnum
= ymm0_regnum
;
7162 if (tdep
->num_ymm_regs
)
7164 /* Support YMM pseudo-register if it is available. */
7165 tdep
->ymm0_regnum
= ymm0_regnum
;
7166 mm0_regnum
+= tdep
->num_ymm_regs
;
7169 tdep
->ymm0_regnum
= -1;
7171 if (tdep
->num_mmx_regs
!= 0)
7173 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7174 tdep
->mm0_regnum
= mm0_regnum
;
7177 tdep
->mm0_regnum
= -1;
7179 /* Hook in the legacy prologue-based unwinders last (fallback). */
7180 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7181 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7183 /* If we have a register mapping, enable the generic core file
7184 support, unless it has already been enabled. */
7185 if (tdep
->gregset_reg_offset
7186 && !gdbarch_regset_from_core_section_p (gdbarch
))
7187 set_gdbarch_regset_from_core_section (gdbarch
,
7188 i386_regset_from_core_section
);
7190 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7191 i386_skip_permanent_breakpoint
);
7193 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7194 i386_fast_tracepoint_valid_at
);
7199 static enum gdb_osabi
7200 i386_coff_osabi_sniffer (bfd
*abfd
)
7202 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7203 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7204 return GDB_OSABI_GO32
;
7206 return GDB_OSABI_UNKNOWN
;
7210 /* Provide a prototype to silence -Wmissing-prototypes. */
7211 void _initialize_i386_tdep (void);
7214 _initialize_i386_tdep (void)
7216 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7218 /* Add the variable that controls the disassembly flavor. */
7219 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7220 &disassembly_flavor
, _("\
7221 Set the disassembly flavor."), _("\
7222 Show the disassembly flavor."), _("\
7223 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7225 NULL
, /* FIXME: i18n: */
7226 &setlist
, &showlist
);
7228 /* Add the variable that controls the convention for returning
7230 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7231 &struct_convention
, _("\
7232 Set the convention for returning small structs."), _("\
7233 Show the convention for returning small structs."), _("\
7234 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7237 NULL
, /* FIXME: i18n: */
7238 &setlist
, &showlist
);
7240 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7241 i386_coff_osabi_sniffer
);
7243 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7244 i386_svr4_init_abi
);
7245 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7246 i386_go32_init_abi
);
7248 /* Initialize the i386-specific register groups. */
7249 i386_init_reggroups ();
7251 /* Initialize the standard target descriptions. */
7252 initialize_tdesc_i386 ();
7253 initialize_tdesc_i386_mmx ();
7254 initialize_tdesc_i386_avx ();
7256 /* Tell remote stub that we support XML target description. */
7257 register_remote_support_xml ("i386");