1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "gdb_assert.h"
49 #include "gdb_string.h"
51 #include "i386-tdep.h"
52 #include "i387-tdep.h"
59 static char *i386_register_names
[] =
61 "eax", "ecx", "edx", "ebx",
62 "esp", "ebp", "esi", "edi",
63 "eip", "eflags", "cs", "ss",
64 "ds", "es", "fs", "gs",
65 "st0", "st1", "st2", "st3",
66 "st4", "st5", "st6", "st7",
67 "fctrl", "fstat", "ftag", "fiseg",
68 "fioff", "foseg", "fooff", "fop",
69 "xmm0", "xmm1", "xmm2", "xmm3",
70 "xmm4", "xmm5", "xmm6", "xmm7",
74 static const int i386_num_register_names
= ARRAY_SIZE (i386_register_names
);
76 /* Register names for MMX pseudo-registers. */
78 static char *i386_mmx_names
[] =
80 "mm0", "mm1", "mm2", "mm3",
81 "mm4", "mm5", "mm6", "mm7"
84 static const int i386_num_mmx_regs
= ARRAY_SIZE (i386_mmx_names
);
87 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
89 int mm0_regnum
= gdbarch_tdep (gdbarch
)->mm0_regnum
;
94 return (regnum
>= mm0_regnum
&& regnum
< mm0_regnum
+ i386_num_mmx_regs
);
100 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
102 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
104 if (I387_NUM_XMM_REGS (tdep
) == 0)
107 return (I387_XMM0_REGNUM (tdep
) <= regnum
108 && regnum
< I387_MXCSR_REGNUM (tdep
));
112 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
116 if (I387_NUM_XMM_REGS (tdep
) == 0)
119 return (regnum
== I387_MXCSR_REGNUM (tdep
));
125 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
129 if (I387_ST0_REGNUM (tdep
) < 0)
132 return (I387_ST0_REGNUM (tdep
) <= regnum
133 && regnum
< I387_FCTRL_REGNUM (tdep
));
137 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 if (I387_ST0_REGNUM (tdep
) < 0)
144 return (I387_FCTRL_REGNUM (tdep
) <= regnum
145 && regnum
< I387_XMM0_REGNUM (tdep
));
148 /* Return the name of register REGNUM. */
151 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
153 if (i386_mmx_regnum_p (gdbarch
, regnum
))
154 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (gdbarch_tdep (gdbarch
))];
156 if (regnum
>= 0 && regnum
< i386_num_register_names
)
157 return i386_register_names
[regnum
];
162 /* Convert a dbx register number REG to the appropriate register
163 number used by GDB. */
166 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
170 /* This implements what GCC calls the "default" register map
171 (dbx_register_map[]). */
173 if (reg
>= 0 && reg
<= 7)
175 /* General-purpose registers. The debug info calls %ebp
176 register 4, and %esp register 5. */
183 else if (reg
>= 12 && reg
<= 19)
185 /* Floating-point registers. */
186 return reg
- 12 + I387_ST0_REGNUM (tdep
);
188 else if (reg
>= 21 && reg
<= 28)
191 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
193 else if (reg
>= 29 && reg
<= 36)
196 return reg
- 29 + I387_MM0_REGNUM (tdep
);
199 /* This will hopefully provoke a warning. */
200 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
203 /* Convert SVR4 register number REG to the appropriate register number
207 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
211 /* This implements the GCC register map that tries to be compatible
212 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
214 /* The SVR4 register numbering includes %eip and %eflags, and
215 numbers the floating point registers differently. */
216 if (reg
>= 0 && reg
<= 9)
218 /* General-purpose registers. */
221 else if (reg
>= 11 && reg
<= 18)
223 /* Floating-point registers. */
224 return reg
- 11 + I387_ST0_REGNUM (tdep
);
226 else if (reg
>= 21 && reg
<= 36)
228 /* The SSE and MMX registers have the same numbers as with dbx. */
229 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
234 case 37: return I387_FCTRL_REGNUM (tdep
);
235 case 38: return I387_FSTAT_REGNUM (tdep
);
236 case 39: return I387_MXCSR_REGNUM (tdep
);
237 case 40: return I386_ES_REGNUM
;
238 case 41: return I386_CS_REGNUM
;
239 case 42: return I386_SS_REGNUM
;
240 case 43: return I386_DS_REGNUM
;
241 case 44: return I386_FS_REGNUM
;
242 case 45: return I386_GS_REGNUM
;
245 /* This will hopefully provoke a warning. */
246 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
251 /* This is the variable that is set with "set disassembly-flavor", and
252 its legitimate values. */
253 static const char att_flavor
[] = "att";
254 static const char intel_flavor
[] = "intel";
255 static const char *valid_flavors
[] =
261 static const char *disassembly_flavor
= att_flavor
;
264 /* Use the program counter to determine the contents and size of a
265 breakpoint instruction. Return a pointer to a string of bytes that
266 encode a breakpoint instruction, store the length of the string in
267 *LEN and optionally adjust *PC to point to the correct memory
268 location for inserting the breakpoint.
270 On the i386 we have a single breakpoint that fits in a single byte
271 and can be inserted anywhere.
273 This function is 64-bit safe. */
275 static const gdb_byte
*
276 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
278 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
280 *len
= sizeof (break_insn
);
284 /* Displaced instruction handling. */
286 /* Skip the legacy instruction prefixes in INSN.
287 Not all prefixes are valid for any particular insn
288 but we needn't care, the insn will fault if it's invalid.
289 The result is a pointer to the first opcode byte,
290 or NULL if we run off the end of the buffer. */
293 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
295 gdb_byte
*end
= insn
+ max_len
;
301 case DATA_PREFIX_OPCODE
:
302 case ADDR_PREFIX_OPCODE
:
303 case CS_PREFIX_OPCODE
:
304 case DS_PREFIX_OPCODE
:
305 case ES_PREFIX_OPCODE
:
306 case FS_PREFIX_OPCODE
:
307 case GS_PREFIX_OPCODE
:
308 case SS_PREFIX_OPCODE
:
309 case LOCK_PREFIX_OPCODE
:
310 case REPE_PREFIX_OPCODE
:
311 case REPNE_PREFIX_OPCODE
:
323 i386_absolute_jmp_p (const gdb_byte
*insn
)
325 /* jmp far (absolute address in operand) */
331 /* jump near, absolute indirect (/4) */
332 if ((insn
[1] & 0x38) == 0x20)
335 /* jump far, absolute indirect (/5) */
336 if ((insn
[1] & 0x38) == 0x28)
344 i386_absolute_call_p (const gdb_byte
*insn
)
346 /* call far, absolute */
352 /* Call near, absolute indirect (/2) */
353 if ((insn
[1] & 0x38) == 0x10)
356 /* Call far, absolute indirect (/3) */
357 if ((insn
[1] & 0x38) == 0x18)
365 i386_ret_p (const gdb_byte
*insn
)
369 case 0xc2: /* ret near, pop N bytes */
370 case 0xc3: /* ret near */
371 case 0xca: /* ret far, pop N bytes */
372 case 0xcb: /* ret far */
373 case 0xcf: /* iret */
382 i386_call_p (const gdb_byte
*insn
)
384 if (i386_absolute_call_p (insn
))
387 /* call near, relative */
394 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
395 length in bytes. Otherwise, return zero. */
398 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
409 /* Fix up the state of registers and memory after having single-stepped
410 a displaced instruction. */
413 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
414 struct displaced_step_closure
*closure
,
415 CORE_ADDR from
, CORE_ADDR to
,
416 struct regcache
*regs
)
418 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
420 /* The offset we applied to the instruction's address.
421 This could well be negative (when viewed as a signed 32-bit
422 value), but ULONGEST won't reflect that, so take care when
424 ULONGEST insn_offset
= to
- from
;
426 /* Since we use simple_displaced_step_copy_insn, our closure is a
427 copy of the instruction. */
428 gdb_byte
*insn
= (gdb_byte
*) closure
;
429 /* The start of the insn, needed in case we see some prefixes. */
430 gdb_byte
*insn_start
= insn
;
433 fprintf_unfiltered (gdb_stdlog
,
434 "displaced: fixup (%s, %s), "
435 "insn = 0x%02x 0x%02x ...\n",
436 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
439 /* The list of issues to contend with here is taken from
440 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
441 Yay for Free Software! */
443 /* Relocate the %eip, if necessary. */
445 /* The instruction recognizers we use assume any leading prefixes
446 have been skipped. */
448 /* This is the size of the buffer in closure. */
449 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
450 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
451 /* If there are too many prefixes, just ignore the insn.
452 It will fault when run. */
457 /* Except in the case of absolute or indirect jump or call
458 instructions, or a return instruction, the new eip is relative to
459 the displaced instruction; make it relative. Well, signal
460 handler returns don't need relocation either, but we use the
461 value of %eip to recognize those; see below. */
462 if (! i386_absolute_jmp_p (insn
)
463 && ! i386_absolute_call_p (insn
)
464 && ! i386_ret_p (insn
))
469 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
471 /* A signal trampoline system call changes the %eip, resuming
472 execution of the main program after the signal handler has
473 returned. That makes them like 'return' instructions; we
474 shouldn't relocate %eip.
476 But most system calls don't, and we do need to relocate %eip.
478 Our heuristic for distinguishing these cases: if stepping
479 over the system call instruction left control directly after
480 the instruction, the we relocate --- control almost certainly
481 doesn't belong in the displaced copy. Otherwise, we assume
482 the instruction has put control where it belongs, and leave
483 it unrelocated. Goodness help us if there are PC-relative
485 if (i386_syscall_p (insn
, &insn_len
)
486 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
489 fprintf_unfiltered (gdb_stdlog
,
490 "displaced: syscall changed %%eip; "
495 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
497 /* If we just stepped over a breakpoint insn, we don't backup
498 the pc on purpose; this is to match behaviour without
501 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
504 fprintf_unfiltered (gdb_stdlog
,
506 "relocated %%eip from %s to %s\n",
507 paddress (gdbarch
, orig_eip
),
508 paddress (gdbarch
, eip
));
512 /* If the instruction was PUSHFL, then the TF bit will be set in the
513 pushed value, and should be cleared. We'll leave this for later,
514 since GDB already messes up the TF flag when stepping over a
517 /* If the instruction was a call, the return address now atop the
518 stack is the address following the copied instruction. We need
519 to make it the address following the original instruction. */
520 if (i386_call_p (insn
))
524 const ULONGEST retaddr_len
= 4;
526 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
527 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
528 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
529 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
532 fprintf_unfiltered (gdb_stdlog
,
533 "displaced: relocated return addr at %s to %s\n",
534 paddress (gdbarch
, esp
),
535 paddress (gdbarch
, retaddr
));
539 #ifdef I386_REGNO_TO_SYMMETRY
540 #error "The Sequent Symmetry is no longer supported."
543 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
544 and %esp "belong" to the calling function. Therefore these
545 registers should be saved if they're going to be modified. */
547 /* The maximum number of saved registers. This should include all
548 registers mentioned above, and %eip. */
549 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
551 struct i386_frame_cache
558 /* Saved registers. */
559 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
564 /* Stack space reserved for local variables. */
568 /* Allocate and initialize a frame cache. */
570 static struct i386_frame_cache
*
571 i386_alloc_frame_cache (void)
573 struct i386_frame_cache
*cache
;
576 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
580 cache
->sp_offset
= -4;
583 /* Saved registers. We initialize these to -1 since zero is a valid
584 offset (that's where %ebp is supposed to be stored). */
585 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
586 cache
->saved_regs
[i
] = -1;
588 cache
->saved_sp_reg
= -1;
589 cache
->pc_in_eax
= 0;
591 /* Frameless until proven otherwise. */
597 /* If the instruction at PC is a jump, return the address of its
598 target. Otherwise, return PC. */
601 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
603 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
608 target_read_memory (pc
, &op
, 1);
612 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
618 /* Relative jump: if data16 == 0, disp32, else disp16. */
621 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
623 /* Include the size of the jmp instruction (including the
629 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
631 /* Include the size of the jmp instruction. */
636 /* Relative jump, disp8 (ignore data16). */
637 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
646 /* Check whether PC points at a prologue for a function returning a
647 structure or union. If so, it updates CACHE and returns the
648 address of the first instruction after the code sequence that
649 removes the "hidden" argument from the stack or CURRENT_PC,
650 whichever is smaller. Otherwise, return PC. */
653 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
654 struct i386_frame_cache
*cache
)
656 /* Functions that return a structure or union start with:
659 xchgl %eax, (%esp) 0x87 0x04 0x24
660 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
662 (the System V compiler puts out the second `xchg' instruction,
663 and the assembler doesn't try to optimize it, so the 'sib' form
664 gets generated). This sequence is used to get the address of the
665 return buffer for a function that returns a structure. */
666 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
667 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
671 if (current_pc
<= pc
)
674 target_read_memory (pc
, &op
, 1);
676 if (op
!= 0x58) /* popl %eax */
679 target_read_memory (pc
+ 1, buf
, 4);
680 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
683 if (current_pc
== pc
)
685 cache
->sp_offset
+= 4;
689 if (current_pc
== pc
+ 1)
691 cache
->pc_in_eax
= 1;
695 if (buf
[1] == proto1
[1])
702 i386_skip_probe (CORE_ADDR pc
)
704 /* A function may start with
718 target_read_memory (pc
, &op
, 1);
720 if (op
== 0x68 || op
== 0x6a)
724 /* Skip past the `pushl' instruction; it has either a one-byte or a
725 four-byte operand, depending on the opcode. */
731 /* Read the following 8 bytes, which should be `call _probe' (6
732 bytes) followed by `addl $4,%esp' (2 bytes). */
733 read_memory (pc
+ delta
, buf
, sizeof (buf
));
734 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
735 pc
+= delta
+ sizeof (buf
);
741 /* GCC 4.1 and later, can put code in the prologue to realign the
742 stack pointer. Check whether PC points to such code, and update
743 CACHE accordingly. Return the first instruction after the code
744 sequence or CURRENT_PC, whichever is smaller. If we don't
745 recognize the code, return PC. */
748 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
749 struct i386_frame_cache
*cache
)
751 /* There are 2 code sequences to re-align stack before the frame
754 1. Use a caller-saved saved register:
760 2. Use a callee-saved saved register:
767 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
769 0x83 0xe4 0xf0 andl $-16, %esp
770 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
775 int offset
, offset_and
;
776 static int regnums
[8] = {
777 I386_EAX_REGNUM
, /* %eax */
778 I386_ECX_REGNUM
, /* %ecx */
779 I386_EDX_REGNUM
, /* %edx */
780 I386_EBX_REGNUM
, /* %ebx */
781 I386_ESP_REGNUM
, /* %esp */
782 I386_EBP_REGNUM
, /* %ebp */
783 I386_ESI_REGNUM
, /* %esi */
784 I386_EDI_REGNUM
/* %edi */
787 if (target_read_memory (pc
, buf
, sizeof buf
))
790 /* Check caller-saved saved register. The first instruction has
791 to be "leal 4(%esp), %reg". */
792 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
794 /* MOD must be binary 10 and R/M must be binary 100. */
795 if ((buf
[1] & 0xc7) != 0x44)
798 /* REG has register number. */
799 reg
= (buf
[1] >> 3) & 7;
804 /* Check callee-saved saved register. The first instruction
805 has to be "pushl %reg". */
806 if ((buf
[0] & 0xf8) != 0x50)
812 /* The next instruction has to be "leal 8(%esp), %reg". */
813 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
816 /* MOD must be binary 10 and R/M must be binary 100. */
817 if ((buf
[2] & 0xc7) != 0x44)
820 /* REG has register number. Registers in pushl and leal have to
822 if (reg
!= ((buf
[2] >> 3) & 7))
828 /* Rigister can't be %esp nor %ebp. */
829 if (reg
== 4 || reg
== 5)
832 /* The next instruction has to be "andl $-XXX, %esp". */
833 if (buf
[offset
+ 1] != 0xe4
834 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
838 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
840 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
841 0xfc. REG must be binary 110 and MOD must be binary 01. */
842 if (buf
[offset
] != 0xff
843 || buf
[offset
+ 2] != 0xfc
844 || (buf
[offset
+ 1] & 0xf8) != 0x70)
847 /* R/M has register. Registers in leal and pushl have to be the
849 if (reg
!= (buf
[offset
+ 1] & 7))
852 if (current_pc
> pc
+ offset_and
)
853 cache
->saved_sp_reg
= regnums
[reg
];
855 return min (pc
+ offset
+ 3, current_pc
);
858 /* Maximum instruction length we need to handle. */
859 #define I386_MAX_MATCHED_INSN_LEN 6
861 /* Instruction description. */
865 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
866 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
869 /* Search for the instruction at PC in the list SKIP_INSNS. Return
870 the first instruction description that matches. Otherwise, return
873 static struct i386_insn
*
874 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
876 struct i386_insn
*insn
;
879 target_read_memory (pc
, &op
, 1);
881 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
883 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
885 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
886 int insn_matched
= 1;
889 gdb_assert (insn
->len
> 1);
890 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
892 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
893 for (i
= 1; i
< insn
->len
; i
++)
895 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
907 /* Some special instructions that might be migrated by GCC into the
908 part of the prologue that sets up the new stack frame. Because the
909 stack frame hasn't been setup yet, no registers have been saved
910 yet, and only the scratch registers %eax, %ecx and %edx can be
913 struct i386_insn i386_frame_setup_skip_insns
[] =
915 /* Check for `movb imm8, r' and `movl imm32, r'.
917 ??? Should we handle 16-bit operand-sizes here? */
919 /* `movb imm8, %al' and `movb imm8, %ah' */
920 /* `movb imm8, %cl' and `movb imm8, %ch' */
921 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
922 /* `movb imm8, %dl' and `movb imm8, %dh' */
923 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
924 /* `movl imm32, %eax' and `movl imm32, %ecx' */
925 { 5, { 0xb8 }, { 0xfe } },
926 /* `movl imm32, %edx' */
927 { 5, { 0xba }, { 0xff } },
929 /* Check for `mov imm32, r32'. Note that there is an alternative
930 encoding for `mov m32, %eax'.
932 ??? Should we handle SIB adressing here?
933 ??? Should we handle 16-bit operand-sizes here? */
935 /* `movl m32, %eax' */
936 { 5, { 0xa1 }, { 0xff } },
937 /* `movl m32, %eax' and `mov; m32, %ecx' */
938 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
939 /* `movl m32, %edx' */
940 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
942 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
943 Because of the symmetry, there are actually two ways to encode
944 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
945 opcode bytes 0x31 and 0x33 for `xorl'. */
947 /* `subl %eax, %eax' */
948 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
949 /* `subl %ecx, %ecx' */
950 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
951 /* `subl %edx, %edx' */
952 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
953 /* `xorl %eax, %eax' */
954 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
955 /* `xorl %ecx, %ecx' */
956 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
957 /* `xorl %edx, %edx' */
958 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
963 /* Check whether PC points to a no-op instruction. */
965 i386_skip_noop (CORE_ADDR pc
)
970 target_read_memory (pc
, &op
, 1);
975 /* Ignore `nop' instruction. */
979 target_read_memory (pc
, &op
, 1);
982 /* Ignore no-op instruction `mov %edi, %edi'.
983 Microsoft system dlls often start with
984 a `mov %edi,%edi' instruction.
985 The 5 bytes before the function start are
986 filled with `nop' instructions.
987 This pattern can be used for hot-patching:
988 The `mov %edi, %edi' instruction can be replaced by a
989 near jump to the location of the 5 `nop' instructions
990 which can be replaced by a 32-bit jump to anywhere
991 in the 32-bit address space. */
995 target_read_memory (pc
+ 1, &op
, 1);
999 target_read_memory (pc
, &op
, 1);
1007 /* Check whether PC points at a code that sets up a new stack frame.
1008 If so, it updates CACHE and returns the address of the first
1009 instruction after the sequence that sets up the frame or LIMIT,
1010 whichever is smaller. If we don't recognize the code, return PC. */
1013 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1014 CORE_ADDR pc
, CORE_ADDR limit
,
1015 struct i386_frame_cache
*cache
)
1017 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1018 struct i386_insn
*insn
;
1025 target_read_memory (pc
, &op
, 1);
1027 if (op
== 0x55) /* pushl %ebp */
1029 /* Take into account that we've executed the `pushl %ebp' that
1030 starts this instruction sequence. */
1031 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1032 cache
->sp_offset
+= 4;
1035 /* If that's all, return now. */
1039 /* Check for some special instructions that might be migrated by
1040 GCC into the prologue and skip them. At this point in the
1041 prologue, code should only touch the scratch registers %eax,
1042 %ecx and %edx, so while the number of posibilities is sheer,
1045 Make sure we only skip these instructions if we later see the
1046 `movl %esp, %ebp' that actually sets up the frame. */
1047 while (pc
+ skip
< limit
)
1049 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1056 /* If that's all, return now. */
1057 if (limit
<= pc
+ skip
)
1060 target_read_memory (pc
+ skip
, &op
, 1);
1062 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1066 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1071 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1079 /* OK, we actually have a frame. We just don't know how large
1080 it is yet. Set its size to zero. We'll adjust it if
1081 necessary. We also now commit to skipping the special
1082 instructions mentioned before. */
1086 /* If that's all, return now. */
1090 /* Check for stack adjustment
1094 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1095 reg, so we don't have to worry about a data16 prefix. */
1096 target_read_memory (pc
, &op
, 1);
1099 /* `subl' with 8-bit immediate. */
1100 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1101 /* Some instruction starting with 0x83 other than `subl'. */
1104 /* `subl' with signed 8-bit immediate (though it wouldn't
1105 make sense to be negative). */
1106 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1109 else if (op
== 0x81)
1111 /* Maybe it is `subl' with a 32-bit immediate. */
1112 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1113 /* Some instruction starting with 0x81 other than `subl'. */
1116 /* It is `subl' with a 32-bit immediate. */
1117 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1122 /* Some instruction other than `subl'. */
1126 else if (op
== 0xc8) /* enter */
1128 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1135 /* Check whether PC points at code that saves registers on the stack.
1136 If so, it updates CACHE and returns the address of the first
1137 instruction after the register saves or CURRENT_PC, whichever is
1138 smaller. Otherwise, return PC. */
1141 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1142 struct i386_frame_cache
*cache
)
1144 CORE_ADDR offset
= 0;
1148 if (cache
->locals
> 0)
1149 offset
-= cache
->locals
;
1150 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1152 target_read_memory (pc
, &op
, 1);
1153 if (op
< 0x50 || op
> 0x57)
1157 cache
->saved_regs
[op
- 0x50] = offset
;
1158 cache
->sp_offset
+= 4;
1165 /* Do a full analysis of the prologue at PC and update CACHE
1166 accordingly. Bail out early if CURRENT_PC is reached. Return the
1167 address where the analysis stopped.
1169 We handle these cases:
1171 The startup sequence can be at the start of the function, or the
1172 function can start with a branch to startup code at the end.
1174 %ebp can be set up with either the 'enter' instruction, or "pushl
1175 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1176 once used in the System V compiler).
1178 Local space is allocated just below the saved %ebp by either the
1179 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1180 16-bit unsigned argument for space to allocate, and the 'addl'
1181 instruction could have either a signed byte, or 32-bit immediate.
1183 Next, the registers used by this function are pushed. With the
1184 System V compiler they will always be in the order: %edi, %esi,
1185 %ebx (and sometimes a harmless bug causes it to also save but not
1186 restore %eax); however, the code below is willing to see the pushes
1187 in any order, and will handle up to 8 of them.
1189 If the setup sequence is at the end of the function, then the next
1190 instruction will be a branch back to the start. */
1193 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1194 CORE_ADDR pc
, CORE_ADDR current_pc
,
1195 struct i386_frame_cache
*cache
)
1197 pc
= i386_skip_noop (pc
);
1198 pc
= i386_follow_jump (gdbarch
, pc
);
1199 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1200 pc
= i386_skip_probe (pc
);
1201 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1202 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1203 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1206 /* Return PC of first real instruction. */
1209 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1211 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1213 static gdb_byte pic_pat
[6] =
1215 0xe8, 0, 0, 0, 0, /* call 0x0 */
1216 0x5b, /* popl %ebx */
1218 struct i386_frame_cache cache
;
1224 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1225 if (cache
.locals
< 0)
1228 /* Found valid frame setup. */
1230 /* The native cc on SVR4 in -K PIC mode inserts the following code
1231 to get the address of the global offset table (GOT) into register
1236 movl %ebx,x(%ebp) (optional)
1239 This code is with the rest of the prologue (at the end of the
1240 function), so we have to skip it to get to the first real
1241 instruction at the start of the function. */
1243 for (i
= 0; i
< 6; i
++)
1245 target_read_memory (pc
+ i
, &op
, 1);
1246 if (pic_pat
[i
] != op
)
1253 target_read_memory (pc
+ delta
, &op
, 1);
1255 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1257 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1259 if (op
== 0x5d) /* One byte offset from %ebp. */
1261 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1263 else /* Unexpected instruction. */
1266 target_read_memory (pc
+ delta
, &op
, 1);
1270 if (delta
> 0 && op
== 0x81
1271 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1278 /* If the function starts with a branch (to startup code at the end)
1279 the last instruction should bring us back to the first
1280 instruction of the real code. */
1281 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1282 pc
= i386_follow_jump (gdbarch
, pc
);
1287 /* Check that the code pointed to by PC corresponds to a call to
1288 __main, skip it if so. Return PC otherwise. */
1291 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1293 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1296 target_read_memory (pc
, &op
, 1);
1301 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1303 /* Make sure address is computed correctly as a 32bit
1304 integer even if CORE_ADDR is 64 bit wide. */
1305 struct minimal_symbol
*s
;
1306 CORE_ADDR call_dest
;
1308 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1309 call_dest
= call_dest
& 0xffffffffU
;
1310 s
= lookup_minimal_symbol_by_pc (call_dest
);
1312 && SYMBOL_LINKAGE_NAME (s
) != NULL
1313 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1321 /* This function is 64-bit safe. */
1324 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1328 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1329 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1333 /* Normal frames. */
1335 static struct i386_frame_cache
*
1336 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1338 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1339 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 struct i386_frame_cache
*cache
;
1347 cache
= i386_alloc_frame_cache ();
1348 *this_cache
= cache
;
1350 /* In principle, for normal frames, %ebp holds the frame pointer,
1351 which holds the base address for the current stack frame.
1352 However, for functions that don't need it, the frame pointer is
1353 optional. For these "frameless" functions the frame pointer is
1354 actually the frame pointer of the calling frame. Signal
1355 trampolines are just a special case of a "frameless" function.
1356 They (usually) share their frame pointer with the frame that was
1357 in progress when the signal occurred. */
1359 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1360 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1361 if (cache
->base
== 0)
1364 /* For normal frames, %eip is stored at 4(%ebp). */
1365 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1367 cache
->pc
= get_frame_func (this_frame
);
1369 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1372 if (cache
->saved_sp_reg
!= -1)
1374 /* Saved stack pointer has been saved. */
1375 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1376 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1379 if (cache
->locals
< 0)
1381 /* We didn't find a valid frame, which means that CACHE->base
1382 currently holds the frame pointer for our calling frame. If
1383 we're at the start of a function, or somewhere half-way its
1384 prologue, the function's frame probably hasn't been fully
1385 setup yet. Try to reconstruct the base address for the stack
1386 frame by looking at the stack pointer. For truly "frameless"
1387 functions this might work too. */
1389 if (cache
->saved_sp_reg
!= -1)
1391 /* We're halfway aligning the stack. */
1392 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1393 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1395 /* This will be added back below. */
1396 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1400 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1401 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1406 /* Now that we have the base address for the stack frame we can
1407 calculate the value of %esp in the calling frame. */
1408 if (cache
->saved_sp
== 0)
1409 cache
->saved_sp
= cache
->base
+ 8;
1411 /* Adjust all the saved registers such that they contain addresses
1412 instead of offsets. */
1413 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1414 if (cache
->saved_regs
[i
] != -1)
1415 cache
->saved_regs
[i
] += cache
->base
;
1421 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1422 struct frame_id
*this_id
)
1424 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1426 /* This marks the outermost frame. */
1427 if (cache
->base
== 0)
1430 /* See the end of i386_push_dummy_call. */
1431 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1434 static struct value
*
1435 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1438 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1440 gdb_assert (regnum
>= 0);
1442 /* The System V ABI says that:
1444 "The flags register contains the system flags, such as the
1445 direction flag and the carry flag. The direction flag must be
1446 set to the forward (that is, zero) direction before entry and
1447 upon exit from a function. Other user flags have no specified
1448 role in the standard calling sequence and are not preserved."
1450 To guarantee the "upon exit" part of that statement we fake a
1451 saved flags register that has its direction flag cleared.
1453 Note that GCC doesn't seem to rely on the fact that the direction
1454 flag is cleared after a function return; it always explicitly
1455 clears the flag before operations where it matters.
1457 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1458 right thing to do. The way we fake the flags register here makes
1459 it impossible to change it. */
1461 if (regnum
== I386_EFLAGS_REGNUM
)
1465 val
= get_frame_register_unsigned (this_frame
, regnum
);
1467 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1470 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1471 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1473 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1474 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1476 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1477 return frame_unwind_got_memory (this_frame
, regnum
,
1478 cache
->saved_regs
[regnum
]);
1480 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1483 static const struct frame_unwind i386_frame_unwind
=
1487 i386_frame_prev_register
,
1489 default_frame_sniffer
1492 /* Normal frames, but in a function epilogue. */
1494 /* The epilogue is defined here as the 'ret' instruction, which will
1495 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1496 the function's stack frame. */
1499 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1503 if (target_read_memory (pc
, &insn
, 1))
1504 return 0; /* Can't read memory at pc. */
1506 if (insn
!= 0xc3) /* 'ret' instruction. */
1513 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1514 struct frame_info
*this_frame
,
1515 void **this_prologue_cache
)
1517 if (frame_relative_level (this_frame
) == 0)
1518 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1519 get_frame_pc (this_frame
));
1524 static struct i386_frame_cache
*
1525 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1527 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1528 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1529 struct i386_frame_cache
*cache
;
1535 cache
= i386_alloc_frame_cache ();
1536 *this_cache
= cache
;
1538 /* Cache base will be %esp plus cache->sp_offset (-4). */
1539 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1540 cache
->base
= extract_unsigned_integer (buf
, 4,
1541 byte_order
) + cache
->sp_offset
;
1543 /* Cache pc will be the frame func. */
1544 cache
->pc
= get_frame_pc (this_frame
);
1546 /* The saved %esp will be at cache->base plus 8. */
1547 cache
->saved_sp
= cache
->base
+ 8;
1549 /* The saved %eip will be at cache->base plus 4. */
1550 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1556 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1558 struct frame_id
*this_id
)
1560 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1563 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1566 static const struct frame_unwind i386_epilogue_frame_unwind
=
1569 i386_epilogue_frame_this_id
,
1570 i386_frame_prev_register
,
1572 i386_epilogue_frame_sniffer
1576 /* Signal trampolines. */
1578 static struct i386_frame_cache
*
1579 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1581 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1582 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1584 struct i386_frame_cache
*cache
;
1591 cache
= i386_alloc_frame_cache ();
1593 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1594 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1596 addr
= tdep
->sigcontext_addr (this_frame
);
1597 if (tdep
->sc_reg_offset
)
1601 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1603 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1604 if (tdep
->sc_reg_offset
[i
] != -1)
1605 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1609 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1610 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1613 *this_cache
= cache
;
1618 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1619 struct frame_id
*this_id
)
1621 struct i386_frame_cache
*cache
=
1622 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1624 /* See the end of i386_push_dummy_call. */
1625 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1628 static struct value
*
1629 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1630 void **this_cache
, int regnum
)
1632 /* Make sure we've initialized the cache. */
1633 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1635 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1639 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1640 struct frame_info
*this_frame
,
1641 void **this_prologue_cache
)
1643 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1645 /* We shouldn't even bother if we don't have a sigcontext_addr
1647 if (tdep
->sigcontext_addr
== NULL
)
1650 if (tdep
->sigtramp_p
!= NULL
)
1652 if (tdep
->sigtramp_p (this_frame
))
1656 if (tdep
->sigtramp_start
!= 0)
1658 CORE_ADDR pc
= get_frame_pc (this_frame
);
1660 gdb_assert (tdep
->sigtramp_end
!= 0);
1661 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1668 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1671 i386_sigtramp_frame_this_id
,
1672 i386_sigtramp_frame_prev_register
,
1674 i386_sigtramp_frame_sniffer
1679 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1681 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1686 static const struct frame_base i386_frame_base
=
1689 i386_frame_base_address
,
1690 i386_frame_base_address
,
1691 i386_frame_base_address
1694 static struct frame_id
1695 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1699 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1701 /* See the end of i386_push_dummy_call. */
1702 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1706 /* Figure out where the longjmp will land. Slurp the args out of the
1707 stack. We expect the first arg to be a pointer to the jmp_buf
1708 structure from which we extract the address that we will land at.
1709 This address is copied into PC. This routine returns non-zero on
1713 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1716 CORE_ADDR sp
, jb_addr
;
1717 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1718 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1719 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1721 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1722 longjmp will land. */
1723 if (jb_pc_offset
== -1)
1726 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1727 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1728 if (target_read_memory (sp
+ 4, buf
, 4))
1731 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1732 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1735 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1740 /* Check whether TYPE must be 16-byte-aligned when passed as a
1741 function argument. 16-byte vectors, _Decimal128 and structures or
1742 unions containing such types must be 16-byte-aligned; other
1743 arguments are 4-byte-aligned. */
1746 i386_16_byte_align_p (struct type
*type
)
1748 type
= check_typedef (type
);
1749 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1750 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1751 && TYPE_LENGTH (type
) == 16)
1753 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1754 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1755 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1756 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1759 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1761 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1769 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1770 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1771 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1772 CORE_ADDR struct_addr
)
1774 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1780 /* Determine the total space required for arguments and struct
1781 return address in a first pass (allowing for 16-byte-aligned
1782 arguments), then push arguments in a second pass. */
1784 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1786 int args_space_used
= 0;
1787 int have_16_byte_aligned_arg
= 0;
1793 /* Push value address. */
1794 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1795 write_memory (sp
, buf
, 4);
1796 args_space_used
+= 4;
1802 for (i
= 0; i
< nargs
; i
++)
1804 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1808 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1809 args_space_used
= align_up (args_space_used
, 16);
1811 write_memory (sp
+ args_space_used
,
1812 value_contents_all (args
[i
]), len
);
1813 /* The System V ABI says that:
1815 "An argument's size is increased, if necessary, to make it a
1816 multiple of [32-bit] words. This may require tail padding,
1817 depending on the size of the argument."
1819 This makes sure the stack stays word-aligned. */
1820 args_space_used
+= align_up (len
, 4);
1824 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1826 args_space
= align_up (args_space
, 16);
1827 have_16_byte_aligned_arg
= 1;
1829 args_space
+= align_up (len
, 4);
1835 if (have_16_byte_aligned_arg
)
1836 args_space
= align_up (args_space
, 16);
1841 /* Store return address. */
1843 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1844 write_memory (sp
, buf
, 4);
1846 /* Finally, update the stack pointer... */
1847 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1848 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1850 /* ...and fake a frame pointer. */
1851 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1853 /* MarkK wrote: This "+ 8" is all over the place:
1854 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1855 i386_dummy_id). It's there, since all frame unwinders for
1856 a given target have to agree (within a certain margin) on the
1857 definition of the stack address of a frame. Otherwise frame id
1858 comparison might not work correctly. Since DWARF2/GCC uses the
1859 stack address *before* the function call as a frame's CFA. On
1860 the i386, when %ebp is used as a frame pointer, the offset
1861 between the contents %ebp and the CFA as defined by GCC. */
1865 /* These registers are used for returning integers (and on some
1866 targets also for returning `struct' and `union' values when their
1867 size and alignment match an integer type). */
1868 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1869 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1871 /* Read, for architecture GDBARCH, a function return value of TYPE
1872 from REGCACHE, and copy that into VALBUF. */
1875 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1876 struct regcache
*regcache
, gdb_byte
*valbuf
)
1878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1879 int len
= TYPE_LENGTH (type
);
1880 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1882 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1884 if (tdep
->st0_regnum
< 0)
1886 warning (_("Cannot find floating-point return value."));
1887 memset (valbuf
, 0, len
);
1891 /* Floating-point return values can be found in %st(0). Convert
1892 its contents to the desired type. This is probably not
1893 exactly how it would happen on the target itself, but it is
1894 the best we can do. */
1895 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1896 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1900 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1901 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1903 if (len
<= low_size
)
1905 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1906 memcpy (valbuf
, buf
, len
);
1908 else if (len
<= (low_size
+ high_size
))
1910 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1911 memcpy (valbuf
, buf
, low_size
);
1912 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1913 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1916 internal_error (__FILE__
, __LINE__
,
1917 _("Cannot extract return value of %d bytes long."), len
);
1921 /* Write, for architecture GDBARCH, a function return value of TYPE
1922 from VALBUF into REGCACHE. */
1925 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1926 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1929 int len
= TYPE_LENGTH (type
);
1931 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1934 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1936 if (tdep
->st0_regnum
< 0)
1938 warning (_("Cannot set floating-point return value."));
1942 /* Returning floating-point values is a bit tricky. Apart from
1943 storing the return value in %st(0), we have to simulate the
1944 state of the FPU at function return point. */
1946 /* Convert the value found in VALBUF to the extended
1947 floating-point format used by the FPU. This is probably
1948 not exactly how it would happen on the target itself, but
1949 it is the best we can do. */
1950 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
1951 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
1953 /* Set the top of the floating-point register stack to 7. The
1954 actual value doesn't really matter, but 7 is what a normal
1955 function return would end up with if the program started out
1956 with a freshly initialized FPU. */
1957 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1959 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1961 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1962 the floating-point register stack to 7, the appropriate value
1963 for the tag word is 0x3fff. */
1964 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
1968 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1969 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1971 if (len
<= low_size
)
1972 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
1973 else if (len
<= (low_size
+ high_size
))
1975 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
1976 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
1977 len
- low_size
, valbuf
+ low_size
);
1980 internal_error (__FILE__
, __LINE__
,
1981 _("Cannot store return value of %d bytes long."), len
);
1986 /* This is the variable that is set with "set struct-convention", and
1987 its legitimate values. */
1988 static const char default_struct_convention
[] = "default";
1989 static const char pcc_struct_convention
[] = "pcc";
1990 static const char reg_struct_convention
[] = "reg";
1991 static const char *valid_conventions
[] =
1993 default_struct_convention
,
1994 pcc_struct_convention
,
1995 reg_struct_convention
,
1998 static const char *struct_convention
= default_struct_convention
;
2000 /* Return non-zero if TYPE, which is assumed to be a structure,
2001 a union type, or an array type, should be returned in registers
2002 for architecture GDBARCH. */
2005 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2007 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2008 enum type_code code
= TYPE_CODE (type
);
2009 int len
= TYPE_LENGTH (type
);
2011 gdb_assert (code
== TYPE_CODE_STRUCT
2012 || code
== TYPE_CODE_UNION
2013 || code
== TYPE_CODE_ARRAY
);
2015 if (struct_convention
== pcc_struct_convention
2016 || (struct_convention
== default_struct_convention
2017 && tdep
->struct_return
== pcc_struct_return
))
2020 /* Structures consisting of a single `float', `double' or 'long
2021 double' member are returned in %st(0). */
2022 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2024 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2025 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2026 return (len
== 4 || len
== 8 || len
== 12);
2029 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2032 /* Determine, for architecture GDBARCH, how a return value of TYPE
2033 should be returned. If it is supposed to be returned in registers,
2034 and READBUF is non-zero, read the appropriate value from REGCACHE,
2035 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2036 from WRITEBUF into REGCACHE. */
2038 static enum return_value_convention
2039 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2040 struct type
*type
, struct regcache
*regcache
,
2041 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2043 enum type_code code
= TYPE_CODE (type
);
2045 if (((code
== TYPE_CODE_STRUCT
2046 || code
== TYPE_CODE_UNION
2047 || code
== TYPE_CODE_ARRAY
)
2048 && !i386_reg_struct_return_p (gdbarch
, type
))
2049 /* 128-bit decimal float uses the struct return convention. */
2050 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2052 /* The System V ABI says that:
2054 "A function that returns a structure or union also sets %eax
2055 to the value of the original address of the caller's area
2056 before it returns. Thus when the caller receives control
2057 again, the address of the returned object resides in register
2058 %eax and can be used to access the object."
2060 So the ABI guarantees that we can always find the return
2061 value just after the function has returned. */
2063 /* Note that the ABI doesn't mention functions returning arrays,
2064 which is something possible in certain languages such as Ada.
2065 In this case, the value is returned as if it was wrapped in
2066 a record, so the convention applied to records also applies
2073 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2074 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2077 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2080 /* This special case is for structures consisting of a single
2081 `float', `double' or 'long double' member. These structures are
2082 returned in %st(0). For these structures, we call ourselves
2083 recursively, changing TYPE into the type of the first member of
2084 the structure. Since that should work for all structures that
2085 have only one member, we don't bother to check the member's type
2087 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2089 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2090 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2095 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2097 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2099 return RETURN_VALUE_REGISTER_CONVENTION
;
2103 /* Construct types for ISA-specific registers. */
2105 i386_eflags_type (struct gdbarch
*gdbarch
)
2107 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2109 if (!tdep
->i386_eflags_type
)
2113 type
= arch_flags_type (gdbarch
, "builtin_type_i386_eflags", 4);
2114 append_flags_type_flag (type
, 0, "CF");
2115 append_flags_type_flag (type
, 1, NULL
);
2116 append_flags_type_flag (type
, 2, "PF");
2117 append_flags_type_flag (type
, 4, "AF");
2118 append_flags_type_flag (type
, 6, "ZF");
2119 append_flags_type_flag (type
, 7, "SF");
2120 append_flags_type_flag (type
, 8, "TF");
2121 append_flags_type_flag (type
, 9, "IF");
2122 append_flags_type_flag (type
, 10, "DF");
2123 append_flags_type_flag (type
, 11, "OF");
2124 append_flags_type_flag (type
, 14, "NT");
2125 append_flags_type_flag (type
, 16, "RF");
2126 append_flags_type_flag (type
, 17, "VM");
2127 append_flags_type_flag (type
, 18, "AC");
2128 append_flags_type_flag (type
, 19, "VIF");
2129 append_flags_type_flag (type
, 20, "VIP");
2130 append_flags_type_flag (type
, 21, "ID");
2132 tdep
->i386_eflags_type
= type
;
2135 return tdep
->i386_eflags_type
;
2139 i386_mxcsr_type (struct gdbarch
*gdbarch
)
2141 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2143 if (!tdep
->i386_mxcsr_type
)
2147 type
= arch_flags_type (gdbarch
, "builtin_type_i386_mxcsr", 4);
2148 append_flags_type_flag (type
, 0, "IE");
2149 append_flags_type_flag (type
, 1, "DE");
2150 append_flags_type_flag (type
, 2, "ZE");
2151 append_flags_type_flag (type
, 3, "OE");
2152 append_flags_type_flag (type
, 4, "UE");
2153 append_flags_type_flag (type
, 5, "PE");
2154 append_flags_type_flag (type
, 6, "DAZ");
2155 append_flags_type_flag (type
, 7, "IM");
2156 append_flags_type_flag (type
, 8, "DM");
2157 append_flags_type_flag (type
, 9, "ZM");
2158 append_flags_type_flag (type
, 10, "OM");
2159 append_flags_type_flag (type
, 11, "UM");
2160 append_flags_type_flag (type
, 12, "PM");
2161 append_flags_type_flag (type
, 15, "FZ");
2163 tdep
->i386_mxcsr_type
= type
;
2166 return tdep
->i386_mxcsr_type
;
2170 i387_ext_type (struct gdbarch
*gdbarch
)
2172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2174 if (!tdep
->i387_ext_type
)
2176 = arch_float_type (gdbarch
, -1, "builtin_type_i387_ext",
2177 floatformats_i387_ext
);
2179 return tdep
->i387_ext_type
;
2182 /* Construct vector type for MMX registers. */
2184 i386_mmx_type (struct gdbarch
*gdbarch
)
2186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2188 if (!tdep
->i386_mmx_type
)
2190 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2192 /* The type we're building is this: */
2194 union __gdb_builtin_type_vec64i
2197 int32_t v2_int32
[2];
2198 int16_t v4_int16
[4];
2205 t
= arch_composite_type (gdbarch
,
2206 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2208 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2209 append_composite_type_field (t
, "v2_int32",
2210 init_vector_type (bt
->builtin_int32
, 2));
2211 append_composite_type_field (t
, "v4_int16",
2212 init_vector_type (bt
->builtin_int16
, 4));
2213 append_composite_type_field (t
, "v8_int8",
2214 init_vector_type (bt
->builtin_int8
, 8));
2216 TYPE_VECTOR (t
) = 1;
2217 TYPE_NAME (t
) = "builtin_type_vec64i";
2218 tdep
->i386_mmx_type
= t
;
2221 return tdep
->i386_mmx_type
;
2225 i386_sse_type (struct gdbarch
*gdbarch
)
2227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2229 if (!tdep
->i386_sse_type
)
2231 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2233 /* The type we're building is this: */
2235 union __gdb_builtin_type_vec128i
2238 int64_t v2_int64
[2];
2239 int32_t v4_int32
[4];
2240 int16_t v8_int16
[8];
2241 int8_t v16_int8
[16];
2242 double v2_double
[2];
2249 t
= arch_composite_type (gdbarch
,
2250 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION
);
2251 append_composite_type_field (t
, "v4_float",
2252 init_vector_type (bt
->builtin_float
, 4));
2253 append_composite_type_field (t
, "v2_double",
2254 init_vector_type (bt
->builtin_double
, 2));
2255 append_composite_type_field (t
, "v16_int8",
2256 init_vector_type (bt
->builtin_int8
, 16));
2257 append_composite_type_field (t
, "v8_int16",
2258 init_vector_type (bt
->builtin_int16
, 8));
2259 append_composite_type_field (t
, "v4_int32",
2260 init_vector_type (bt
->builtin_int32
, 4));
2261 append_composite_type_field (t
, "v2_int64",
2262 init_vector_type (bt
->builtin_int64
, 2));
2263 append_composite_type_field (t
, "uint128", bt
->builtin_int128
);
2265 TYPE_VECTOR (t
) = 1;
2266 TYPE_NAME (t
) = "builtin_type_vec128i";
2267 tdep
->i386_sse_type
= t
;
2270 return tdep
->i386_sse_type
;
2273 /* Return the GDB type object for the "standard" data type of data in
2274 register REGNUM. Perhaps %esi and %edi should go here, but
2275 potentially they could be used for things other than address. */
2277 static struct type
*
2278 i386_register_type (struct gdbarch
*gdbarch
, int regnum
)
2280 if (regnum
== I386_EIP_REGNUM
)
2281 return builtin_type (gdbarch
)->builtin_func_ptr
;
2283 if (regnum
== I386_EFLAGS_REGNUM
)
2284 return i386_eflags_type (gdbarch
);
2286 if (regnum
== I386_EBP_REGNUM
|| regnum
== I386_ESP_REGNUM
)
2287 return builtin_type (gdbarch
)->builtin_data_ptr
;
2289 if (i386_fp_regnum_p (gdbarch
, regnum
))
2290 return i387_ext_type (gdbarch
);
2292 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2293 return i386_mmx_type (gdbarch
);
2295 if (i386_sse_regnum_p (gdbarch
, regnum
))
2296 return i386_sse_type (gdbarch
);
2298 if (regnum
== I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch
)))
2299 return i386_mxcsr_type (gdbarch
);
2301 return builtin_type (gdbarch
)->builtin_int
;
2304 /* Map a cooked register onto a raw register or memory. For the i386,
2305 the MMX registers need to be mapped onto floating point registers. */
2308 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2310 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2315 mmxreg
= regnum
- tdep
->mm0_regnum
;
2316 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2317 tos
= (fstat
>> 11) & 0x7;
2318 fpreg
= (mmxreg
+ tos
) % 8;
2320 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2324 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2325 int regnum
, gdb_byte
*buf
)
2327 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2329 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2330 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2332 /* Extract (always little endian). */
2333 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2334 memcpy (buf
, mmx_buf
, register_size (gdbarch
, regnum
));
2337 regcache_raw_read (regcache
, regnum
, buf
);
2341 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2342 int regnum
, const gdb_byte
*buf
)
2344 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2346 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2347 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2350 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2351 /* ... Modify ... (always little endian). */
2352 memcpy (mmx_buf
, buf
, register_size (gdbarch
, regnum
));
2354 regcache_raw_write (regcache
, fpnum
, mmx_buf
);
2357 regcache_raw_write (regcache
, regnum
, buf
);
2361 /* Return the register number of the register allocated by GCC after
2362 REGNUM, or -1 if there is no such register. */
2365 i386_next_regnum (int regnum
)
2367 /* GCC allocates the registers in the order:
2369 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2371 Since storing a variable in %esp doesn't make any sense we return
2372 -1 for %ebp and for %esp itself. */
2373 static int next_regnum
[] =
2375 I386_EDX_REGNUM
, /* Slot for %eax. */
2376 I386_EBX_REGNUM
, /* Slot for %ecx. */
2377 I386_ECX_REGNUM
, /* Slot for %edx. */
2378 I386_ESI_REGNUM
, /* Slot for %ebx. */
2379 -1, -1, /* Slots for %esp and %ebp. */
2380 I386_EDI_REGNUM
, /* Slot for %esi. */
2381 I386_EBP_REGNUM
/* Slot for %edi. */
2384 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2385 return next_regnum
[regnum
];
2390 /* Return nonzero if a value of type TYPE stored in register REGNUM
2391 needs any special handling. */
2394 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2396 int len
= TYPE_LENGTH (type
);
2398 /* Values may be spread across multiple registers. Most debugging
2399 formats aren't expressive enough to specify the locations, so
2400 some heuristics is involved. Right now we only handle types that
2401 have a length that is a multiple of the word size, since GCC
2402 doesn't seem to put any other types into registers. */
2403 if (len
> 4 && len
% 4 == 0)
2405 int last_regnum
= regnum
;
2409 last_regnum
= i386_next_regnum (last_regnum
);
2413 if (last_regnum
!= -1)
2417 return i387_convert_register_p (gdbarch
, regnum
, type
);
2420 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2421 return its contents in TO. */
2424 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2425 struct type
*type
, gdb_byte
*to
)
2427 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2428 int len
= TYPE_LENGTH (type
);
2430 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2431 available in FRAME (i.e. if it wasn't saved)? */
2433 if (i386_fp_regnum_p (gdbarch
, regnum
))
2435 i387_register_to_value (frame
, regnum
, type
, to
);
2439 /* Read a value spread across multiple registers. */
2441 gdb_assert (len
> 4 && len
% 4 == 0);
2445 gdb_assert (regnum
!= -1);
2446 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2448 get_frame_register (frame
, regnum
, to
);
2449 regnum
= i386_next_regnum (regnum
);
2455 /* Write the contents FROM of a value of type TYPE into register
2456 REGNUM in frame FRAME. */
2459 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2460 struct type
*type
, const gdb_byte
*from
)
2462 int len
= TYPE_LENGTH (type
);
2464 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2466 i387_value_to_register (frame
, regnum
, type
, from
);
2470 /* Write a value spread across multiple registers. */
2472 gdb_assert (len
> 4 && len
% 4 == 0);
2476 gdb_assert (regnum
!= -1);
2477 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2479 put_frame_register (frame
, regnum
, from
);
2480 regnum
= i386_next_regnum (regnum
);
2486 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2487 in the general-purpose register set REGSET to register cache
2488 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2491 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2492 int regnum
, const void *gregs
, size_t len
)
2494 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2495 const gdb_byte
*regs
= gregs
;
2498 gdb_assert (len
== tdep
->sizeof_gregset
);
2500 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2502 if ((regnum
== i
|| regnum
== -1)
2503 && tdep
->gregset_reg_offset
[i
] != -1)
2504 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2508 /* Collect register REGNUM from the register cache REGCACHE and store
2509 it in the buffer specified by GREGS and LEN as described by the
2510 general-purpose register set REGSET. If REGNUM is -1, do this for
2511 all registers in REGSET. */
2514 i386_collect_gregset (const struct regset
*regset
,
2515 const struct regcache
*regcache
,
2516 int regnum
, void *gregs
, size_t len
)
2518 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2519 gdb_byte
*regs
= gregs
;
2522 gdb_assert (len
== tdep
->sizeof_gregset
);
2524 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2526 if ((regnum
== i
|| regnum
== -1)
2527 && tdep
->gregset_reg_offset
[i
] != -1)
2528 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2532 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2533 in the floating-point register set REGSET to register cache
2534 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2537 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2538 int regnum
, const void *fpregs
, size_t len
)
2540 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2542 if (len
== I387_SIZEOF_FXSAVE
)
2544 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2548 gdb_assert (len
== tdep
->sizeof_fpregset
);
2549 i387_supply_fsave (regcache
, regnum
, fpregs
);
2552 /* Collect register REGNUM from the register cache REGCACHE and store
2553 it in the buffer specified by FPREGS and LEN as described by the
2554 floating-point register set REGSET. If REGNUM is -1, do this for
2555 all registers in REGSET. */
2558 i386_collect_fpregset (const struct regset
*regset
,
2559 const struct regcache
*regcache
,
2560 int regnum
, void *fpregs
, size_t len
)
2562 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2564 if (len
== I387_SIZEOF_FXSAVE
)
2566 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2570 gdb_assert (len
== tdep
->sizeof_fpregset
);
2571 i387_collect_fsave (regcache
, regnum
, fpregs
);
2574 /* Return the appropriate register set for the core section identified
2575 by SECT_NAME and SECT_SIZE. */
2577 const struct regset
*
2578 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2579 const char *sect_name
, size_t sect_size
)
2581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2583 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2585 if (tdep
->gregset
== NULL
)
2586 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2587 i386_collect_gregset
);
2588 return tdep
->gregset
;
2591 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2592 || (strcmp (sect_name
, ".reg-xfp") == 0
2593 && sect_size
== I387_SIZEOF_FXSAVE
))
2595 if (tdep
->fpregset
== NULL
)
2596 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2597 i386_collect_fpregset
);
2598 return tdep
->fpregset
;
2605 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2608 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2609 CORE_ADDR pc
, char *name
)
2611 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2612 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2615 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2617 unsigned long indirect
=
2618 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2619 struct minimal_symbol
*indsym
=
2620 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2621 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2625 if (strncmp (symname
, "__imp_", 6) == 0
2626 || strncmp (symname
, "_imp_", 5) == 0)
2628 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2631 return 0; /* Not a trampoline. */
2635 /* Return whether the THIS_FRAME corresponds to a sigtramp
2639 i386_sigtramp_p (struct frame_info
*this_frame
)
2641 CORE_ADDR pc
= get_frame_pc (this_frame
);
2644 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2645 return (name
&& strcmp ("_sigtramp", name
) == 0);
2649 /* We have two flavours of disassembly. The machinery on this page
2650 deals with switching between those. */
2653 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2655 gdb_assert (disassembly_flavor
== att_flavor
2656 || disassembly_flavor
== intel_flavor
);
2658 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2659 constified, cast to prevent a compiler warning. */
2660 info
->disassembler_options
= (char *) disassembly_flavor
;
2662 return print_insn_i386 (pc
, info
);
2666 /* There are a few i386 architecture variants that differ only
2667 slightly from the generic i386 target. For now, we don't give them
2668 their own source file, but include them here. As a consequence,
2669 they'll always be included. */
2671 /* System V Release 4 (SVR4). */
2673 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2677 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2679 CORE_ADDR pc
= get_frame_pc (this_frame
);
2682 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2683 currently unknown. */
2684 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2685 return (name
&& (strcmp ("_sigreturn", name
) == 0
2686 || strcmp ("_sigacthandler", name
) == 0
2687 || strcmp ("sigvechandler", name
) == 0));
2690 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2691 address of the associated sigcontext (ucontext) structure. */
2694 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2696 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2697 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2701 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2702 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2704 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2711 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2713 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2714 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2717 /* System V Release 4 (SVR4). */
2720 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2722 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2724 /* System V Release 4 uses ELF. */
2725 i386_elf_init_abi (info
, gdbarch
);
2727 /* System V Release 4 has shared libraries. */
2728 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2730 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2731 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2732 tdep
->sc_pc_offset
= 36 + 14 * 4;
2733 tdep
->sc_sp_offset
= 36 + 17 * 4;
2735 tdep
->jb_pc_offset
= 20;
2741 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2745 /* DJGPP doesn't have any special frames for signal handlers. */
2746 tdep
->sigtramp_p
= NULL
;
2748 tdep
->jb_pc_offset
= 36;
2750 /* DJGPP does not support the SSE registers. */
2751 tdep
->num_xmm_regs
= 0;
2752 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I386_NUM_FREGS
);
2754 /* Native compiler is GCC, which uses the SVR4 register numbering
2755 even in COFF and STABS. See the comment in i386_gdbarch_init,
2756 before the calls to set_gdbarch_stab_reg_to_regnum and
2757 set_gdbarch_sdb_reg_to_regnum. */
2758 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2759 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2763 /* i386 register groups. In addition to the normal groups, add "mmx"
2766 static struct reggroup
*i386_sse_reggroup
;
2767 static struct reggroup
*i386_mmx_reggroup
;
2770 i386_init_reggroups (void)
2772 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2773 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2777 i386_add_reggroups (struct gdbarch
*gdbarch
)
2779 reggroup_add (gdbarch
, i386_sse_reggroup
);
2780 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2781 reggroup_add (gdbarch
, general_reggroup
);
2782 reggroup_add (gdbarch
, float_reggroup
);
2783 reggroup_add (gdbarch
, all_reggroup
);
2784 reggroup_add (gdbarch
, save_reggroup
);
2785 reggroup_add (gdbarch
, restore_reggroup
);
2786 reggroup_add (gdbarch
, vector_reggroup
);
2787 reggroup_add (gdbarch
, system_reggroup
);
2791 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2792 struct reggroup
*group
)
2794 int sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2795 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2796 int fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2797 || i386_fpc_regnum_p (gdbarch
, regnum
));
2798 int mmx_regnum_p
= (i386_mmx_regnum_p (gdbarch
, regnum
));
2800 if (group
== i386_mmx_reggroup
)
2801 return mmx_regnum_p
;
2802 if (group
== i386_sse_reggroup
)
2803 return sse_regnum_p
;
2804 if (group
== vector_reggroup
)
2805 return (mmx_regnum_p
|| sse_regnum_p
);
2806 if (group
== float_reggroup
)
2808 if (group
== general_reggroup
)
2809 return (!fp_regnum_p
&& !mmx_regnum_p
&& !sse_regnum_p
);
2811 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2815 /* Get the ARGIth function argument for the current function. */
2818 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2821 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2823 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2824 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2828 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2830 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2832 /* On i386, breakpoint is exactly 1 byte long, so we just
2833 adjust the PC in the regcache. */
2835 regcache_write_pc (regcache
, current_pc
);
2839 #define PREFIX_REPZ 0x01
2840 #define PREFIX_REPNZ 0x02
2841 #define PREFIX_LOCK 0x04
2842 #define PREFIX_DATA 0x08
2843 #define PREFIX_ADDR 0x10
2854 /* i386 arith/logic operations */
2867 struct i386_record_s
2869 struct gdbarch
*gdbarch
;
2870 struct regcache
*regcache
;
2871 CORE_ADDR orig_addr
;
2877 uint8_t mod
, reg
, rm
;
2886 /* Parse "modrm" part in current memory address that irp->addr point to
2887 Return -1 if something wrong. */
2890 i386_record_modrm (struct i386_record_s
*irp
)
2892 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2894 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2897 printf_unfiltered (_("Process record: error reading memory at "
2898 "addr %s len = 1.\n"),
2899 paddress (gdbarch
, irp
->addr
));
2903 irp
->mod
= (irp
->modrm
>> 6) & 3;
2904 irp
->reg
= (irp
->modrm
>> 3) & 7;
2905 irp
->rm
= irp
->modrm
& 7;
2910 /* Get the memory address that current instruction write to and set it to
2911 the argument "addr".
2912 Return -1 if something wrong. */
2915 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2917 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2921 ULONGEST tmpulongest
;
2930 uint8_t base
= irp
->rm
;
2935 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2938 printf_unfiltered (_("Process record: error reading memory "
2939 "at addr %s len = 1.\n"),
2940 paddress (gdbarch
, irp
->addr
));
2944 scale
= (tmpu8
>> 6) & 3;
2945 index
= ((tmpu8
>> 3) & 7) | irp
->rex_x
;
2953 if ((base
& 7) == 5)
2956 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
2959 printf_unfiltered (_("Process record: error reading "
2960 "memory at addr %s len = 4.\n"),
2961 paddress (gdbarch
, irp
->addr
));
2966 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
2967 *addr
+= irp
->addr
+ irp
->rip_offset
;
2975 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2978 printf_unfiltered (_("Process record: error reading memory "
2979 "at addr %s len = 1.\n"),
2980 paddress (gdbarch
, irp
->addr
));
2984 *addr
= (int8_t) tmpu8
;
2987 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
2990 printf_unfiltered (_("Process record: error reading memory "
2991 "at addr %s len = 4.\n"),
2992 paddress (gdbarch
, irp
->addr
));
3003 if (base
== 4 && irp
->popl_esp_hack
)
3004 *addr
+= irp
->popl_esp_hack
;
3005 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3008 if (irp
->aflag
== 2)
3010 *addr
+= tmpulongest
;
3013 *addr
= (uint32_t) (tmpulongest
+ *addr
);
3015 if (havesib
&& (index
!= 4 || scale
!= 0))
3017 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3019 if (irp
->aflag
== 2)
3020 *addr
+= tmpulongest
<< scale
;
3022 *addr
= (uint32_t) (*addr
+ (tmpulongest
<< scale
));
3033 if (target_read_memory
3034 (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3037 printf_unfiltered (_("Process record: error reading "
3038 "memory at addr %s len = 2.\n"),
3039 paddress (gdbarch
, irp
->addr
));
3053 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
3056 printf_unfiltered (_("Process record: error reading memory "
3057 "at addr %s len = 1.\n"),
3058 paddress (gdbarch
, irp
->addr
));
3062 *addr
= (int8_t) tmpu8
;
3065 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3068 printf_unfiltered (_("Process record: error reading memory "
3069 "at addr %s len = 2.\n"),
3070 paddress (gdbarch
, irp
->addr
));
3081 regcache_raw_read_unsigned (irp
->regcache
,
3082 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3084 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3085 regcache_raw_read_unsigned (irp
->regcache
,
3086 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3088 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3091 regcache_raw_read_unsigned (irp
->regcache
,
3092 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3094 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3095 regcache_raw_read_unsigned (irp
->regcache
,
3096 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3098 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3101 regcache_raw_read_unsigned (irp
->regcache
,
3102 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3104 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3105 regcache_raw_read_unsigned (irp
->regcache
,
3106 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3108 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3111 regcache_raw_read_unsigned (irp
->regcache
,
3112 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3114 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3115 regcache_raw_read_unsigned (irp
->regcache
,
3116 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3118 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3121 regcache_raw_read_unsigned (irp
->regcache
,
3122 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3124 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3127 regcache_raw_read_unsigned (irp
->regcache
,
3128 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3130 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3133 regcache_raw_read_unsigned (irp
->regcache
,
3134 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3136 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3139 regcache_raw_read_unsigned (irp
->regcache
,
3140 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3142 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3152 /* Record the value of the memory that willbe changed in current instruction
3153 to "record_arch_list".
3154 Return -1 if something wrong. */
3157 i386_record_lea_modrm (struct i386_record_s
*irp
)
3159 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3162 if (irp
->override
>= 0)
3164 warning (_("Process record ignores the memory change "
3165 "of instruction at address %s because it "
3166 "can't get the value of the segment register."),
3167 paddress (gdbarch
, irp
->orig_addr
));
3171 if (i386_record_lea_modrm_addr (irp
, &addr
))
3174 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3180 /* Record the push operation to "record_arch_list".
3181 Return -1 if something wrong. */
3184 i386_record_push (struct i386_record_s
*irp
, int size
)
3186 ULONGEST tmpulongest
;
3188 if (record_arch_list_add_reg (irp
->regcache
,
3189 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3191 regcache_raw_read_unsigned (irp
->regcache
,
3192 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3194 if (record_arch_list_add_mem ((CORE_ADDR
) tmpulongest
- size
, size
))
3201 /* Defines contents to record. */
3202 #define I386_SAVE_FPU_REGS 0xfffd
3203 #define I386_SAVE_FPU_ENV 0xfffe
3204 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3206 /* Record the value of floating point registers which will be changed by the
3207 current instruction to "record_arch_list". Return -1 if something is wrong.
3210 static int i386_record_floats (struct gdbarch
*gdbarch
,
3211 struct i386_record_s
*ir
,
3214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3217 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3218 happen. Currently we store st0-st7 registers, but we need not store all
3219 registers all the time, in future we use ftag register and record only
3220 those who are not marked as an empty. */
3222 if (I386_SAVE_FPU_REGS
== iregnum
)
3224 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3226 if (record_arch_list_add_reg (ir
->regcache
, i
))
3230 else if (I386_SAVE_FPU_ENV
== iregnum
)
3232 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3234 if (record_arch_list_add_reg (ir
->regcache
, i
))
3238 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3240 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3242 if (record_arch_list_add_reg (ir
->regcache
, i
))
3246 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3247 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3249 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3254 /* Parameter error. */
3257 if(I386_SAVE_FPU_ENV
!= iregnum
)
3259 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3261 if (record_arch_list_add_reg (ir
->regcache
, i
))
3268 /* Parse the current instruction and record the values of the registers and
3269 memory that will be changed in current instruction to "record_arch_list".
3270 Return -1 if something wrong. */
3272 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3273 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3276 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3283 ULONGEST tmpulongest
;
3285 struct i386_record_s ir
;
3286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3291 memset (&ir
, 0, sizeof (struct i386_record_s
));
3292 ir
.regcache
= regcache
;
3294 ir
.orig_addr
= addr
;
3298 ir
.popl_esp_hack
= 0;
3299 ir
.regmap
= gdbarch_tdep (gdbarch
)->record_regmap
;
3300 ir
.gdbarch
= gdbarch
;
3302 if (record_debug
> 1)
3303 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3305 paddress (gdbarch
, ir
.addr
));
3310 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3313 printf_unfiltered (_("Process record: error reading memory at "
3314 "addr %s len = 1.\n"),
3315 paddress (gdbarch
, ir
.addr
));
3319 switch (tmpu8
) /* Instruction prefixes */
3321 case REPE_PREFIX_OPCODE
:
3322 prefixes
|= PREFIX_REPZ
;
3324 case REPNE_PREFIX_OPCODE
:
3325 prefixes
|= PREFIX_REPNZ
;
3327 case LOCK_PREFIX_OPCODE
:
3328 prefixes
|= PREFIX_LOCK
;
3330 case CS_PREFIX_OPCODE
:
3331 ir
.override
= X86_RECORD_CS_REGNUM
;
3333 case SS_PREFIX_OPCODE
:
3334 ir
.override
= X86_RECORD_SS_REGNUM
;
3336 case DS_PREFIX_OPCODE
:
3337 ir
.override
= X86_RECORD_DS_REGNUM
;
3339 case ES_PREFIX_OPCODE
:
3340 ir
.override
= X86_RECORD_ES_REGNUM
;
3342 case FS_PREFIX_OPCODE
:
3343 ir
.override
= X86_RECORD_FS_REGNUM
;
3345 case GS_PREFIX_OPCODE
:
3346 ir
.override
= X86_RECORD_GS_REGNUM
;
3348 case DATA_PREFIX_OPCODE
:
3349 prefixes
|= PREFIX_DATA
;
3351 case ADDR_PREFIX_OPCODE
:
3352 prefixes
|= PREFIX_ADDR
;
3354 case 0x40: /* i386 inc %eax */
3355 case 0x41: /* i386 inc %ecx */
3356 case 0x42: /* i386 inc %edx */
3357 case 0x43: /* i386 inc %ebx */
3358 case 0x44: /* i386 inc %esp */
3359 case 0x45: /* i386 inc %ebp */
3360 case 0x46: /* i386 inc %esi */
3361 case 0x47: /* i386 inc %edi */
3362 case 0x48: /* i386 dec %eax */
3363 case 0x49: /* i386 dec %ecx */
3364 case 0x4a: /* i386 dec %edx */
3365 case 0x4b: /* i386 dec %ebx */
3366 case 0x4c: /* i386 dec %esp */
3367 case 0x4d: /* i386 dec %ebp */
3368 case 0x4e: /* i386 dec %esi */
3369 case 0x4f: /* i386 dec %edi */
3370 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3374 rex_w
= (tmpu8
>> 3) & 1;
3375 rex_r
= (tmpu8
& 0x4) << 1;
3376 ir
.rex_x
= (tmpu8
& 0x2) << 2;
3377 ir
.rex_b
= (tmpu8
& 0x1) << 3;
3379 else /* 32 bit target */
3388 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3394 if (prefixes
& PREFIX_DATA
)
3397 if (prefixes
& PREFIX_ADDR
)
3399 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3402 /* now check op code */
3403 opcode
= (uint32_t) tmpu8
;
3408 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3411 printf_unfiltered (_("Process record: error reading memory at "
3412 "addr %s len = 1.\n"),
3413 paddress (gdbarch
, ir
.addr
));
3417 opcode
= (uint16_t) tmpu8
| 0x0f00;
3421 case 0x00: /* arith & logic */
3469 if (((opcode
>> 3) & 7) != OP_CMPL
)
3471 if ((opcode
& 1) == 0)
3474 ir
.ot
= ir
.dflag
+ OT_WORD
;
3476 switch ((opcode
>> 1) & 3)
3478 case 0: /* OP Ev, Gv */
3479 if (i386_record_modrm (&ir
))
3483 if (i386_record_lea_modrm (&ir
))
3489 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3491 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3494 case 1: /* OP Gv, Ev */
3495 if (i386_record_modrm (&ir
))
3498 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3500 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3502 case 2: /* OP A, Iv */
3503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3510 case 0x80: /* GRP1 */
3514 if (i386_record_modrm (&ir
))
3517 if (ir
.reg
!= OP_CMPL
)
3519 if ((opcode
& 1) == 0)
3522 ir
.ot
= ir
.dflag
+ OT_WORD
;
3529 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3530 if (i386_record_lea_modrm (&ir
))
3534 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3539 case 0x40: /* inc */
3548 case 0x48: /* dec */
3557 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3561 case 0xf6: /* GRP3 */
3563 if ((opcode
& 1) == 0)
3566 ir
.ot
= ir
.dflag
+ OT_WORD
;
3567 if (i386_record_modrm (&ir
))
3570 if (ir
.mod
!= 3 && ir
.reg
== 0)
3571 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3576 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3582 if (i386_record_lea_modrm (&ir
))
3588 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3590 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3592 if (ir
.reg
== 3) /* neg */
3593 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3600 if (ir
.ot
!= OT_BYTE
)
3601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3606 opcode
= opcode
<< 8 | ir
.modrm
;
3612 case 0xfe: /* GRP4 */
3613 case 0xff: /* GRP5 */
3614 if (i386_record_modrm (&ir
))
3616 if (ir
.reg
>= 2 && opcode
== 0xfe)
3619 opcode
= opcode
<< 8 | ir
.modrm
;
3626 if ((opcode
& 1) == 0)
3629 ir
.ot
= ir
.dflag
+ OT_WORD
;
3632 if (i386_record_lea_modrm (&ir
))
3638 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3640 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3642 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3645 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3647 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3649 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3653 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3655 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3662 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3664 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3669 opcode
= opcode
<< 8 | ir
.modrm
;
3675 case 0x84: /* test */
3679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3682 case 0x98: /* CWDE/CBW */
3683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3686 case 0x99: /* CDQ/CWD */
3687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3688 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3691 case 0x0faf: /* imul */
3694 ir
.ot
= ir
.dflag
+ OT_WORD
;
3695 if (i386_record_modrm (&ir
))
3698 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3699 else if (opcode
== 0x6b)
3702 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3704 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3705 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3708 case 0x0fc0: /* xadd */
3710 if ((opcode
& 1) == 0)
3713 ir
.ot
= ir
.dflag
+ OT_WORD
;
3714 if (i386_record_modrm (&ir
))
3719 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3721 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3722 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3724 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3728 if (i386_record_lea_modrm (&ir
))
3730 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3732 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3734 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3737 case 0x0fb0: /* cmpxchg */
3739 if ((opcode
& 1) == 0)
3742 ir
.ot
= ir
.dflag
+ OT_WORD
;
3743 if (i386_record_modrm (&ir
))
3748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3749 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3751 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3756 if (i386_record_lea_modrm (&ir
))
3759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3762 case 0x0fc7: /* cmpxchg8b */
3763 if (i386_record_modrm (&ir
))
3768 opcode
= opcode
<< 8 | ir
.modrm
;
3771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3772 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3773 if (i386_record_lea_modrm (&ir
))
3775 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3778 case 0x50: /* push */
3788 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3790 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3794 case 0x06: /* push es */
3795 case 0x0e: /* push cs */
3796 case 0x16: /* push ss */
3797 case 0x1e: /* push ds */
3798 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3803 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3807 case 0x0fa0: /* push fs */
3808 case 0x0fa8: /* push gs */
3809 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3814 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3818 case 0x60: /* pusha */
3819 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3824 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3828 case 0x58: /* pop */
3836 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3837 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3840 case 0x61: /* popa */
3841 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3846 for (tmpu8
= X86_RECORD_REAX_REGNUM
; tmpu8
<= X86_RECORD_REDI_REGNUM
;
3848 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
3851 case 0x8f: /* pop */
3852 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3853 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3855 ir
.ot
= ir
.dflag
+ OT_WORD
;
3856 if (i386_record_modrm (&ir
))
3859 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3862 ir
.popl_esp_hack
= 1 << ir
.ot
;
3863 if (i386_record_lea_modrm (&ir
))
3866 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3869 case 0xc8: /* enter */
3870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3871 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3873 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3877 case 0xc9: /* leave */
3878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3879 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3882 case 0x07: /* pop es */
3883 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3888 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3889 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3893 case 0x17: /* pop ss */
3894 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3899 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3901 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3904 case 0x1f: /* pop ds */
3905 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3910 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3911 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3915 case 0x0fa1: /* pop fs */
3916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3917 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3918 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3921 case 0x0fa9: /* pop gs */
3922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3927 case 0x88: /* mov */
3931 if ((opcode
& 1) == 0)
3934 ir
.ot
= ir
.dflag
+ OT_WORD
;
3936 if (i386_record_modrm (&ir
))
3941 if (opcode
== 0xc6 || opcode
== 0xc7)
3942 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3943 if (i386_record_lea_modrm (&ir
))
3948 if (opcode
== 0xc6 || opcode
== 0xc7)
3950 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3952 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3956 case 0x8a: /* mov */
3958 if ((opcode
& 1) == 0)
3961 ir
.ot
= ir
.dflag
+ OT_WORD
;
3962 if (i386_record_modrm (&ir
))
3965 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3967 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3970 case 0x8c: /* mov seg */
3971 if (i386_record_modrm (&ir
))
3976 opcode
= opcode
<< 8 | ir
.modrm
;
3981 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3985 if (i386_record_lea_modrm (&ir
))
3990 case 0x8e: /* mov seg */
3991 if (i386_record_modrm (&ir
))
3996 tmpu8
= X86_RECORD_ES_REGNUM
;
3999 tmpu8
= X86_RECORD_SS_REGNUM
;
4002 tmpu8
= X86_RECORD_DS_REGNUM
;
4005 tmpu8
= X86_RECORD_FS_REGNUM
;
4008 tmpu8
= X86_RECORD_GS_REGNUM
;
4012 opcode
= opcode
<< 8 | ir
.modrm
;
4016 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
4017 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4020 case 0x0fb6: /* movzbS */
4021 case 0x0fb7: /* movzwS */
4022 case 0x0fbe: /* movsbS */
4023 case 0x0fbf: /* movswS */
4024 if (i386_record_modrm (&ir
))
4026 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4029 case 0x8d: /* lea */
4030 if (i386_record_modrm (&ir
))
4035 opcode
= opcode
<< 8 | ir
.modrm
;
4040 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4042 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4045 case 0xa0: /* mov EAX */
4048 case 0xd7: /* xlat */
4049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4052 case 0xa2: /* mov EAX */
4054 if (ir
.override
>= 0)
4056 warning (_("Process record ignores the memory change "
4057 "of instruction at address %s because "
4058 "it can't get the value of the segment "
4060 paddress (gdbarch
, ir
.orig_addr
));
4064 if ((opcode
& 1) == 0)
4067 ir
.ot
= ir
.dflag
+ OT_WORD
;
4070 if (target_read_memory (ir
.addr
, (gdb_byte
*) &addr
, 8))
4073 printf_unfiltered (_("Process record: error reading "
4074 "memory at addr 0x%s len = 8.\n"),
4075 paddress (gdbarch
, ir
.addr
));
4082 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu32
, 4))
4085 printf_unfiltered (_("Process record: error reading "
4086 "memory at addr 0x%s len = 4.\n"),
4087 paddress (gdbarch
, ir
.addr
));
4095 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu16
, 2))
4098 printf_unfiltered (_("Process record: error reading "
4099 "memory at addr 0x%s len = 2.\n"),
4100 paddress (gdbarch
, ir
.addr
));
4106 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4111 case 0xb0: /* mov R, Ib */
4119 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4120 ? ((opcode
& 0x7) | ir
.rex_b
)
4121 : ((opcode
& 0x7) & 0x3));
4124 case 0xb8: /* mov R, Iv */
4132 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4135 case 0x91: /* xchg R, EAX */
4142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4143 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4146 case 0x86: /* xchg Ev, Gv */
4148 if ((opcode
& 1) == 0)
4151 ir
.ot
= ir
.dflag
+ OT_WORD
;
4152 if (i386_record_modrm (&ir
))
4157 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4159 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4163 if (i386_record_lea_modrm (&ir
))
4167 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4169 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4172 case 0xc4: /* les Gv */
4173 case 0xc5: /* lds Gv */
4174 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4179 case 0x0fb2: /* lss Gv */
4180 case 0x0fb4: /* lfs Gv */
4181 case 0x0fb5: /* lgs Gv */
4182 if (i386_record_modrm (&ir
))
4190 opcode
= opcode
<< 8 | ir
.modrm
;
4195 case 0xc4: /* les Gv */
4196 tmpu8
= X86_RECORD_ES_REGNUM
;
4198 case 0xc5: /* lds Gv */
4199 tmpu8
= X86_RECORD_DS_REGNUM
;
4201 case 0x0fb2: /* lss Gv */
4202 tmpu8
= X86_RECORD_SS_REGNUM
;
4204 case 0x0fb4: /* lfs Gv */
4205 tmpu8
= X86_RECORD_FS_REGNUM
;
4207 case 0x0fb5: /* lgs Gv */
4208 tmpu8
= X86_RECORD_GS_REGNUM
;
4211 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
4212 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4213 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4216 case 0xc0: /* shifts */
4222 if ((opcode
& 1) == 0)
4225 ir
.ot
= ir
.dflag
+ OT_WORD
;
4226 if (i386_record_modrm (&ir
))
4228 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4230 if (i386_record_lea_modrm (&ir
))
4236 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4238 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4240 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4247 if (i386_record_modrm (&ir
))
4251 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4256 if (i386_record_lea_modrm (&ir
))
4261 case 0xd8: /* Floats. */
4269 if (i386_record_modrm (&ir
))
4271 ir
.reg
|= ((opcode
& 7) << 3);
4277 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
4285 /* For fcom, ficom nothing to do. */
4291 /* For fcomp, ficomp pop FPU stack, store all. */
4292 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4319 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4320 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4321 of code, always affects st(0) register. */
4322 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4346 /* Handling fld, fild. */
4347 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4351 switch (ir
.reg
>> 4)
4354 if (record_arch_list_add_mem (tmpu64
, 4))
4358 if (record_arch_list_add_mem (tmpu64
, 8))
4364 if (record_arch_list_add_mem (tmpu64
, 2))
4370 switch (ir
.reg
>> 4)
4373 if (record_arch_list_add_mem (tmpu64
, 4))
4375 if (3 == (ir
.reg
& 7))
4377 /* For fstp m32fp. */
4378 if (i386_record_floats (gdbarch
, &ir
,
4379 I386_SAVE_FPU_REGS
))
4384 if (record_arch_list_add_mem (tmpu64
, 4))
4386 if ((3 == (ir
.reg
& 7))
4387 || (5 == (ir
.reg
& 7))
4388 || (7 == (ir
.reg
& 7)))
4390 /* For fstp insn. */
4391 if (i386_record_floats (gdbarch
, &ir
,
4392 I386_SAVE_FPU_REGS
))
4397 if (record_arch_list_add_mem (tmpu64
, 8))
4399 if (3 == (ir
.reg
& 7))
4401 /* For fstp m64fp. */
4402 if (i386_record_floats (gdbarch
, &ir
,
4403 I386_SAVE_FPU_REGS
))
4408 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4410 /* For fistp, fbld, fild, fbstp. */
4411 if (i386_record_floats (gdbarch
, &ir
,
4412 I386_SAVE_FPU_REGS
))
4417 if (record_arch_list_add_mem (tmpu64
, 2))
4426 if (i386_record_floats (gdbarch
, &ir
,
4427 I386_SAVE_FPU_ENV_REG_STACK
))
4432 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4437 if (i386_record_floats (gdbarch
, &ir
,
4438 I386_SAVE_FPU_ENV_REG_STACK
))
4444 if (record_arch_list_add_mem (tmpu64
, 28))
4449 if (record_arch_list_add_mem (tmpu64
, 14))
4455 if (record_arch_list_add_mem (tmpu64
, 2))
4457 /* Insn fstp, fbstp. */
4458 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4463 if (record_arch_list_add_mem (tmpu64
, 10))
4469 if (record_arch_list_add_mem (tmpu64
, 28))
4475 if (record_arch_list_add_mem (tmpu64
, 14))
4479 if (record_arch_list_add_mem (tmpu64
, 80))
4482 if (i386_record_floats (gdbarch
, &ir
,
4483 I386_SAVE_FPU_ENV_REG_STACK
))
4487 if (record_arch_list_add_mem (tmpu64
, 8))
4490 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4495 opcode
= opcode
<< 8 | ir
.modrm
;
4500 /* Opcode is an extension of modR/M byte. */
4506 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4510 if (0x0c == (ir
.modrm
>> 4))
4512 if ((ir
.modrm
& 0x0f) <= 7)
4514 if (i386_record_floats (gdbarch
, &ir
,
4515 I386_SAVE_FPU_REGS
))
4520 if (i386_record_floats (gdbarch
, &ir
,
4521 I387_ST0_REGNUM (tdep
)))
4523 /* If only st(0) is changing, then we have already
4525 if ((ir
.modrm
& 0x0f) - 0x08)
4527 if (i386_record_floats (gdbarch
, &ir
,
4528 I387_ST0_REGNUM (tdep
) +
4529 ((ir
.modrm
& 0x0f) - 0x08)))
4547 if (i386_record_floats (gdbarch
, &ir
,
4548 I387_ST0_REGNUM (tdep
)))
4566 if (i386_record_floats (gdbarch
, &ir
,
4567 I386_SAVE_FPU_REGS
))
4571 if (i386_record_floats (gdbarch
, &ir
,
4572 I387_ST0_REGNUM (tdep
)))
4574 if (i386_record_floats (gdbarch
, &ir
,
4575 I387_ST0_REGNUM (tdep
) + 1))
4582 if (0xe9 == ir
.modrm
)
4584 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4587 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4589 if (i386_record_floats (gdbarch
, &ir
,
4590 I387_ST0_REGNUM (tdep
)))
4592 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4594 if (i386_record_floats (gdbarch
, &ir
,
4595 I387_ST0_REGNUM (tdep
) +
4599 else if ((ir
.modrm
& 0x0f) - 0x08)
4601 if (i386_record_floats (gdbarch
, &ir
,
4602 I387_ST0_REGNUM (tdep
) +
4603 ((ir
.modrm
& 0x0f) - 0x08)))
4609 if (0xe3 == ir
.modrm
)
4611 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4614 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4616 if (i386_record_floats (gdbarch
, &ir
,
4617 I387_ST0_REGNUM (tdep
)))
4619 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4621 if (i386_record_floats (gdbarch
, &ir
,
4622 I387_ST0_REGNUM (tdep
) +
4626 else if ((ir
.modrm
& 0x0f) - 0x08)
4628 if (i386_record_floats (gdbarch
, &ir
,
4629 I387_ST0_REGNUM (tdep
) +
4630 ((ir
.modrm
& 0x0f) - 0x08)))
4636 if ((0x0c == ir
.modrm
>> 4)
4637 || (0x0d == ir
.modrm
>> 4)
4638 || (0x0f == ir
.modrm
>> 4))
4640 if ((ir
.modrm
& 0x0f) <= 7)
4642 if (i386_record_floats (gdbarch
, &ir
,
4643 I387_ST0_REGNUM (tdep
) +
4649 if (i386_record_floats (gdbarch
, &ir
,
4650 I387_ST0_REGNUM (tdep
) +
4651 ((ir
.modrm
& 0x0f) - 0x08)))
4657 if (0x0c == ir
.modrm
>> 4)
4659 if (i386_record_floats (gdbarch
, &ir
,
4660 I387_FTAG_REGNUM (tdep
)))
4663 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4665 if ((ir
.modrm
& 0x0f) <= 7)
4667 if (i386_record_floats (gdbarch
, &ir
,
4668 I387_ST0_REGNUM (tdep
) +
4674 if (i386_record_floats (gdbarch
, &ir
,
4675 I386_SAVE_FPU_REGS
))
4681 if ((0x0c == ir
.modrm
>> 4)
4682 || (0x0e == ir
.modrm
>> 4)
4683 || (0x0f == ir
.modrm
>> 4)
4684 || (0xd9 == ir
.modrm
))
4686 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4691 if (0xe0 == ir
.modrm
)
4693 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4696 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4698 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4706 case 0xa4: /* movsS */
4708 case 0xaa: /* stosS */
4710 case 0x6c: /* insS */
4712 regcache_raw_read_unsigned (ir
.regcache
,
4713 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4719 if ((opcode
& 1) == 0)
4722 ir
.ot
= ir
.dflag
+ OT_WORD
;
4723 regcache_raw_read_unsigned (ir
.regcache
,
4724 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4727 regcache_raw_read_unsigned (ir
.regcache
,
4728 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4730 regcache_raw_read_unsigned (ir
.regcache
,
4731 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4733 if (ir
.aflag
&& (es
!= ds
))
4735 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4736 warning (_("Process record ignores the memory "
4737 "change of instruction at address %s "
4738 "because it can't get the value of the "
4739 "ES segment register."),
4740 paddress (gdbarch
, ir
.orig_addr
));
4744 if (record_arch_list_add_mem (tmpulongest
, 1 << ir
.ot
))
4748 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4750 if (opcode
== 0xa4 || opcode
== 0xa5)
4751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4752 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4753 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4757 case 0xa6: /* cmpsS */
4759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4761 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4762 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4763 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4766 case 0xac: /* lodsS */
4768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4769 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4770 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4772 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4775 case 0xae: /* scasS */
4777 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4778 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4779 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4780 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4783 case 0x6e: /* outsS */
4785 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4786 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4791 case 0xe4: /* port I/O */
4795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4806 case 0xc2: /* ret im */
4807 case 0xc3: /* ret */
4808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4812 case 0xca: /* lret im */
4813 case 0xcb: /* lret */
4814 case 0xcf: /* iret */
4815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4820 case 0xe8: /* call im */
4821 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4823 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4827 case 0x9a: /* lcall im */
4828 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4833 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4834 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4838 case 0xe9: /* jmp im */
4839 case 0xea: /* ljmp im */
4840 case 0xeb: /* jmp Jb */
4841 case 0x70: /* jcc Jb */
4857 case 0x0f80: /* jcc Jv */
4875 case 0x0f90: /* setcc Gv */
4891 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4893 if (i386_record_modrm (&ir
))
4896 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4900 if (i386_record_lea_modrm (&ir
))
4905 case 0x0f40: /* cmov Gv, Ev */
4921 if (i386_record_modrm (&ir
))
4924 if (ir
.dflag
== OT_BYTE
)
4926 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4930 case 0x9c: /* pushf */
4931 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4932 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4934 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4938 case 0x9d: /* popf */
4939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4943 case 0x9e: /* sahf */
4944 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4949 case 0xf5: /* cmc */
4950 case 0xf8: /* clc */
4951 case 0xf9: /* stc */
4952 case 0xfc: /* cld */
4953 case 0xfd: /* std */
4954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4957 case 0x9f: /* lahf */
4958 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4967 /* bit operations */
4968 case 0x0fba: /* bt/bts/btr/btc Gv, im */
4969 ir
.ot
= ir
.dflag
+ OT_WORD
;
4970 if (i386_record_modrm (&ir
))
4975 opcode
= opcode
<< 8 | ir
.modrm
;
4981 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4984 if (i386_record_lea_modrm (&ir
))
4988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4991 case 0x0fa3: /* bt Gv, Ev */
4992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4995 case 0x0fab: /* bts */
4996 case 0x0fb3: /* btr */
4997 case 0x0fbb: /* btc */
4998 ir
.ot
= ir
.dflag
+ OT_WORD
;
4999 if (i386_record_modrm (&ir
))
5002 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5006 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5008 regcache_raw_read_unsigned (ir
.regcache
,
5009 ir
.regmap
[ir
.reg
| rex_r
],
5014 tmpu64
+= ((int16_t) tmpulongest
>> 4) << 4;
5017 tmpu64
+= ((int32_t) tmpulongest
>> 5) << 5;
5020 tmpu64
+= ((int64_t) tmpulongest
>> 6) << 6;
5023 if (record_arch_list_add_mem (tmpu64
, 1 << ir
.ot
))
5025 if (i386_record_lea_modrm (&ir
))
5028 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5031 case 0x0fbc: /* bsf */
5032 case 0x0fbd: /* bsr */
5033 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5034 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5038 case 0x27: /* daa */
5039 case 0x2f: /* das */
5040 case 0x37: /* aaa */
5041 case 0x3f: /* aas */
5042 case 0xd4: /* aam */
5043 case 0xd5: /* aad */
5044 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5050 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5054 case 0x90: /* nop */
5055 if (prefixes
& PREFIX_LOCK
)
5062 case 0x9b: /* fwait */
5063 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
5066 printf_unfiltered (_("Process record: error reading memory at "
5067 "addr 0x%s len = 1.\n"),
5068 paddress (gdbarch
, ir
.addr
));
5071 opcode
= (uint32_t) tmpu8
;
5077 case 0xcc: /* int3 */
5078 printf_unfiltered (_("Process record doesn't support instruction "
5085 case 0xcd: /* int */
5088 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
5091 printf_unfiltered (_("Process record: error reading memory "
5092 "at addr %s len = 1.\n"),
5093 paddress (gdbarch
, ir
.addr
));
5098 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
5100 printf_unfiltered (_("Process record doesn't support "
5101 "instruction int 0x%02x.\n"),
5106 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
5113 case 0xce: /* into */
5114 printf_unfiltered (_("Process record doesn't support "
5115 "instruction into.\n"));
5120 case 0xfa: /* cli */
5121 case 0xfb: /* sti */
5124 case 0x62: /* bound */
5125 printf_unfiltered (_("Process record doesn't support "
5126 "instruction bound.\n"));
5131 case 0x0fc8: /* bswap reg */
5139 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5142 case 0xd6: /* salc */
5143 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5149 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5152 case 0xe0: /* loopnz */
5153 case 0xe1: /* loopz */
5154 case 0xe2: /* loop */
5155 case 0xe3: /* jecxz */
5156 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5157 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5160 case 0x0f30: /* wrmsr */
5161 printf_unfiltered (_("Process record doesn't support "
5162 "instruction wrmsr.\n"));
5167 case 0x0f32: /* rdmsr */
5168 printf_unfiltered (_("Process record doesn't support "
5169 "instruction rdmsr.\n"));
5174 case 0x0f31: /* rdtsc */
5175 printf_unfiltered (_("Process record doesn't support "
5176 "instruction rdtsc.\n"));
5181 case 0x0f34: /* sysenter */
5184 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5189 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
5191 printf_unfiltered (_("Process record doesn't support "
5192 "instruction sysenter.\n"));
5196 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
5202 case 0x0f35: /* sysexit */
5203 printf_unfiltered (_("Process record doesn't support "
5204 "instruction sysexit.\n"));
5209 case 0x0f05: /* syscall */
5212 if (gdbarch_tdep (gdbarch
)->i386_syscall_record
== NULL
)
5214 printf_unfiltered (_("Process record doesn't support "
5215 "instruction syscall.\n"));
5219 ret
= gdbarch_tdep (gdbarch
)->i386_syscall_record (ir
.regcache
);
5225 case 0x0f07: /* sysret */
5226 printf_unfiltered (_("Process record doesn't support "
5227 "instruction sysret.\n"));
5232 case 0x0fa2: /* cpuid */
5233 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5239 case 0xf4: /* hlt */
5240 printf_unfiltered (_("Process record doesn't support "
5241 "instruction hlt.\n"));
5247 if (i386_record_modrm (&ir
))
5254 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5258 if (i386_record_lea_modrm (&ir
))
5267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5271 opcode
= opcode
<< 8 | ir
.modrm
;
5278 if (i386_record_modrm (&ir
))
5289 opcode
= opcode
<< 8 | ir
.modrm
;
5292 if (ir
.override
>= 0)
5294 warning (_("Process record ignores the memory "
5295 "change of instruction at "
5296 "address %s because it can't get "
5297 "the value of the segment "
5299 paddress (gdbarch
, ir
.orig_addr
));
5303 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5305 if (record_arch_list_add_mem (tmpu64
, 2))
5308 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5310 if (record_arch_list_add_mem (tmpu64
, 8))
5315 if (record_arch_list_add_mem (tmpu64
, 4))
5326 case 0: /* monitor */
5329 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5333 opcode
= opcode
<< 8 | ir
.modrm
;
5341 if (ir
.override
>= 0)
5343 warning (_("Process record ignores the memory "
5344 "change of instruction at "
5345 "address %s because it can't get "
5346 "the value of the segment "
5348 paddress (gdbarch
, ir
.orig_addr
));
5354 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5356 if (record_arch_list_add_mem (tmpu64
, 2))
5359 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5361 if (record_arch_list_add_mem (tmpu64
, 8))
5366 if (record_arch_list_add_mem (tmpu64
, 4))
5378 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5383 else if (ir
.rm
== 1)
5390 opcode
= opcode
<< 8 | ir
.modrm
;
5397 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5403 if (i386_record_lea_modrm (&ir
))
5406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5411 case 7: /* invlpg */
5414 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5419 opcode
= opcode
<< 8 | ir
.modrm
;
5424 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5428 opcode
= opcode
<< 8 | ir
.modrm
;
5434 case 0x0f08: /* invd */
5435 case 0x0f09: /* wbinvd */
5438 case 0x63: /* arpl */
5439 if (i386_record_modrm (&ir
))
5441 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5443 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5444 ? (ir
.reg
| rex_r
) : ir
.rm
);
5448 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5449 if (i386_record_lea_modrm (&ir
))
5452 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5456 case 0x0f02: /* lar */
5457 case 0x0f03: /* lsl */
5458 if (i386_record_modrm (&ir
))
5460 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5461 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5465 if (i386_record_modrm (&ir
))
5467 if (ir
.mod
== 3 && ir
.reg
== 3)
5470 opcode
= opcode
<< 8 | ir
.modrm
;
5482 /* nop (multi byte) */
5485 case 0x0f20: /* mov reg, crN */
5486 case 0x0f22: /* mov crN, reg */
5487 if (i386_record_modrm (&ir
))
5489 if ((ir
.modrm
& 0xc0) != 0xc0)
5492 opcode
= opcode
<< 8 | ir
.modrm
;
5503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5505 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5509 opcode
= opcode
<< 8 | ir
.modrm
;
5515 case 0x0f21: /* mov reg, drN */
5516 case 0x0f23: /* mov drN, reg */
5517 if (i386_record_modrm (&ir
))
5519 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5520 || ir
.reg
== 5 || ir
.reg
>= 8)
5523 opcode
= opcode
<< 8 | ir
.modrm
;
5527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5529 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5532 case 0x0f06: /* clts */
5533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5536 /* MMX/SSE/SSE2/PNI support */
5548 /* In the future, maybe still need to deal with need_dasm. */
5549 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
5550 if (record_arch_list_add_end ())
5556 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5557 "at address %s.\n"),
5558 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5562 static const int i386_record_regmap
[] =
5564 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
5565 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
5566 0, 0, 0, 0, 0, 0, 0, 0,
5567 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
5568 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
5571 /* Check that the given address appears suitable for a fast
5572 tracepoint, which on x86 means that we need an instruction of at
5573 least 5 bytes, so that we can overwrite it with a 4-byte-offset
5574 jump and not have to worry about program jumps to an address in the
5575 middle of the tracepoint jump. Returns 1 if OK, and writes a size
5576 of instruction to replace, and 0 if not, plus an explanatory
5580 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
5581 CORE_ADDR addr
, int *isize
, char **msg
)
5584 static struct ui_file
*gdb_null
= NULL
;
5586 /* This is based on the target agent using a 4-byte relative jump.
5587 Alternate future possibilities include 8-byte offset for x86-84,
5588 or 3-byte jumps if the program has trampoline space close by. */
5591 /* Dummy file descriptor for the disassembler. */
5593 gdb_null
= ui_file_new ();
5595 /* Check for fit. */
5596 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
5599 /* Return a bit of target-specific detail to add to the caller's
5600 generic failure message. */
5602 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
5615 static struct gdbarch
*
5616 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5618 struct gdbarch_tdep
*tdep
;
5619 struct gdbarch
*gdbarch
;
5621 /* If there is already a candidate, use it. */
5622 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5624 return arches
->gdbarch
;
5626 /* Allocate space for the new architecture. */
5627 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5628 gdbarch
= gdbarch_alloc (&info
, tdep
);
5630 /* General-purpose registers. */
5631 tdep
->gregset
= NULL
;
5632 tdep
->gregset_reg_offset
= NULL
;
5633 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5634 tdep
->sizeof_gregset
= 0;
5636 /* Floating-point registers. */
5637 tdep
->fpregset
= NULL
;
5638 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5640 /* The default settings include the FPU registers, the MMX registers
5641 and the SSE registers. This can be overridden for a specific ABI
5642 by adjusting the members `st0_regnum', `mm0_regnum' and
5643 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5644 will show up in the output of "info all-registers". Ideally we
5645 should try to autodetect whether they are available, such that we
5646 can prevent "info all-registers" from displaying registers that
5649 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5650 [the SSE registers] always (even when they don't exist) or never
5651 showing them to the user (even when they do exist), I prefer the
5652 former over the latter. */
5654 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5656 /* The MMX registers are implemented as pseudo-registers. Put off
5657 calculating the register number for %mm0 until we know the number
5658 of raw registers. */
5659 tdep
->mm0_regnum
= 0;
5661 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5662 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5664 tdep
->jb_pc_offset
= -1;
5665 tdep
->struct_return
= pcc_struct_return
;
5666 tdep
->sigtramp_start
= 0;
5667 tdep
->sigtramp_end
= 0;
5668 tdep
->sigtramp_p
= i386_sigtramp_p
;
5669 tdep
->sigcontext_addr
= NULL
;
5670 tdep
->sc_reg_offset
= NULL
;
5671 tdep
->sc_pc_offset
= -1;
5672 tdep
->sc_sp_offset
= -1;
5674 tdep
->record_regmap
= i386_record_regmap
;
5676 /* The format used for `long double' on almost all i386 targets is
5677 the i387 extended floating-point format. In fact, of all targets
5678 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5679 on having a `long double' that's not `long' at all. */
5680 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5682 /* Although the i387 extended floating-point has only 80 significant
5683 bits, a `long double' actually takes up 96, probably to enforce
5685 set_gdbarch_long_double_bit (gdbarch
, 96);
5687 /* The default ABI includes general-purpose registers,
5688 floating-point registers, and the SSE registers. */
5689 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5690 set_gdbarch_register_name (gdbarch
, i386_register_name
);
5691 set_gdbarch_register_type (gdbarch
, i386_register_type
);
5693 /* Register numbers of various important registers. */
5694 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5695 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5696 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5697 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5699 /* NOTE: kettenis/20040418: GCC does have two possible register
5700 numbering schemes on the i386: dbx and SVR4. These schemes
5701 differ in how they number %ebp, %esp, %eflags, and the
5702 floating-point registers, and are implemented by the arrays
5703 dbx_register_map[] and svr4_dbx_register_map in
5704 gcc/config/i386.c. GCC also defines a third numbering scheme in
5705 gcc/config/i386.c, which it designates as the "default" register
5706 map used in 64bit mode. This last register numbering scheme is
5707 implemented in dbx64_register_map, and is used for AMD64; see
5710 Currently, each GCC i386 target always uses the same register
5711 numbering scheme across all its supported debugging formats
5712 i.e. SDB (COFF), stabs and DWARF 2. This is because
5713 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5714 DBX_REGISTER_NUMBER macro which is defined by each target's
5715 respective config header in a manner independent of the requested
5716 output debugging format.
5718 This does not match the arrangement below, which presumes that
5719 the SDB and stabs numbering schemes differ from the DWARF and
5720 DWARF 2 ones. The reason for this arrangement is that it is
5721 likely to get the numbering scheme for the target's
5722 default/native debug format right. For targets where GCC is the
5723 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5724 targets where the native toolchain uses a different numbering
5725 scheme for a particular debug format (stabs-in-ELF on Solaris)
5726 the defaults below will have to be overridden, like
5727 i386_elf_init_abi() does. */
5729 /* Use the dbx register numbering scheme for stabs and COFF. */
5730 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5731 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5733 /* Use the SVR4 register numbering scheme for DWARF 2. */
5734 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5736 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5737 be in use on any of the supported i386 targets. */
5739 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5741 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5743 /* Call dummy code. */
5744 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5746 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5747 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5748 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5750 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5752 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5754 /* Stack grows downward. */
5755 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5757 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5758 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5759 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5761 set_gdbarch_frame_args_skip (gdbarch
, 8);
5763 /* Wire in the MMX registers. */
5764 set_gdbarch_num_pseudo_regs (gdbarch
, i386_num_mmx_regs
);
5765 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5766 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5768 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5770 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5772 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5774 /* Add the i386 register groups. */
5775 i386_add_reggroups (gdbarch
);
5776 set_gdbarch_register_reggroup_p (gdbarch
, i386_register_reggroup_p
);
5778 /* Helper for function argument information. */
5779 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5781 /* Hook the function epilogue frame unwinder. This unwinder is
5782 appended to the list first, so that it supercedes the Dwarf
5783 unwinder in function epilogues (where the Dwarf unwinder
5784 currently fails). */
5785 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
5787 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5788 to the list before the prologue-based unwinders, so that Dwarf
5789 CFI info will be used if it is available. */
5790 dwarf2_append_unwinders (gdbarch
);
5792 frame_base_set_default (gdbarch
, &i386_frame_base
);
5794 /* Hook in ABI-specific overrides, if they have been registered. */
5795 gdbarch_init_osabi (info
, gdbarch
);
5797 /* Hook in the legacy prologue-based unwinders last (fallback). */
5798 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5799 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5801 /* If we have a register mapping, enable the generic core file
5802 support, unless it has already been enabled. */
5803 if (tdep
->gregset_reg_offset
5804 && !gdbarch_regset_from_core_section_p (gdbarch
))
5805 set_gdbarch_regset_from_core_section (gdbarch
,
5806 i386_regset_from_core_section
);
5808 /* Unless support for MMX has been disabled, make %mm0 the first
5810 if (tdep
->mm0_regnum
== 0)
5811 tdep
->mm0_regnum
= gdbarch_num_regs (gdbarch
);
5813 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5814 i386_skip_permanent_breakpoint
);
5816 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
5817 i386_fast_tracepoint_valid_at
);
5822 static enum gdb_osabi
5823 i386_coff_osabi_sniffer (bfd
*abfd
)
5825 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5826 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5827 return GDB_OSABI_GO32
;
5829 return GDB_OSABI_UNKNOWN
;
5833 /* Provide a prototype to silence -Wmissing-prototypes. */
5834 void _initialize_i386_tdep (void);
5837 _initialize_i386_tdep (void)
5839 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5841 /* Add the variable that controls the disassembly flavor. */
5842 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5843 &disassembly_flavor
, _("\
5844 Set the disassembly flavor."), _("\
5845 Show the disassembly flavor."), _("\
5846 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5848 NULL
, /* FIXME: i18n: */
5849 &setlist
, &showlist
);
5851 /* Add the variable that controls the convention for returning
5853 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5854 &struct_convention
, _("\
5855 Set the convention for returning small structs."), _("\
5856 Show the convention for returning small structs."), _("\
5857 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5860 NULL
, /* FIXME: i18n: */
5861 &setlist
, &showlist
);
5863 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5864 i386_coff_osabi_sniffer
);
5866 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5867 i386_svr4_init_abi
);
5868 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5869 i386_go32_init_abi
);
5871 /* Initialize the i386-specific register groups. */
5872 i386_init_reggroups ();