1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
53 #include "record-full.h"
54 #include "target-descriptions.h"
55 #include "arch/i386.h"
60 #include "stap-probe.h"
61 #include "user-regs.h"
62 #include "cli/cli-utils.h"
63 #include "expression.h"
64 #include "parser-defs.h"
67 #include <unordered_set>
72 static const char *i386_register_names
[] =
74 "eax", "ecx", "edx", "ebx",
75 "esp", "ebp", "esi", "edi",
76 "eip", "eflags", "cs", "ss",
77 "ds", "es", "fs", "gs",
78 "st0", "st1", "st2", "st3",
79 "st4", "st5", "st6", "st7",
80 "fctrl", "fstat", "ftag", "fiseg",
81 "fioff", "foseg", "fooff", "fop",
82 "xmm0", "xmm1", "xmm2", "xmm3",
83 "xmm4", "xmm5", "xmm6", "xmm7",
87 static const char *i386_zmm_names
[] =
89 "zmm0", "zmm1", "zmm2", "zmm3",
90 "zmm4", "zmm5", "zmm6", "zmm7"
93 static const char *i386_zmmh_names
[] =
95 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
96 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
99 static const char *i386_k_names
[] =
101 "k0", "k1", "k2", "k3",
102 "k4", "k5", "k6", "k7"
105 static const char *i386_ymm_names
[] =
107 "ymm0", "ymm1", "ymm2", "ymm3",
108 "ymm4", "ymm5", "ymm6", "ymm7",
111 static const char *i386_ymmh_names
[] =
113 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
114 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
117 static const char *i386_mpx_names
[] =
119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
122 static const char* i386_pkeys_names
[] =
127 /* Register names for MPX pseudo-registers. */
129 static const char *i386_bnd_names
[] =
131 "bnd0", "bnd1", "bnd2", "bnd3"
134 /* Register names for MMX pseudo-registers. */
136 static const char *i386_mmx_names
[] =
138 "mm0", "mm1", "mm2", "mm3",
139 "mm4", "mm5", "mm6", "mm7"
142 /* Register names for byte pseudo-registers. */
144 static const char *i386_byte_names
[] =
146 "al", "cl", "dl", "bl",
147 "ah", "ch", "dh", "bh"
150 /* Register names for word pseudo-registers. */
152 static const char *i386_word_names
[] =
154 "ax", "cx", "dx", "bx",
158 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
159 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
160 we have 16 upper ZMM regs that have to be handled differently. */
162 const int num_lower_zmm_regs
= 16;
167 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
170 int mm0_regnum
= tdep
->mm0_regnum
;
175 regnum
-= mm0_regnum
;
176 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
182 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 regnum
-= tdep
->al_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
193 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 regnum
-= tdep
->ax_regnum
;
198 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
201 /* Dword register? */
204 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
207 int eax_regnum
= tdep
->eax_regnum
;
212 regnum
-= eax_regnum
;
213 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
216 /* AVX512 register? */
219 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
221 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
224 if (zmm0h_regnum
< 0)
227 regnum
-= zmm0h_regnum
;
228 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
232 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 int zmm0_regnum
= tdep
->zmm0_regnum
;
240 regnum
-= zmm0_regnum
;
241 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
245 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
248 int k0_regnum
= tdep
->k0_regnum
;
254 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
258 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
263 if (ymm0h_regnum
< 0)
266 regnum
-= ymm0h_regnum
;
267 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
273 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
276 int ymm0_regnum
= tdep
->ymm0_regnum
;
281 regnum
-= ymm0_regnum
;
282 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
286 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
289 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
291 if (ymm16h_regnum
< 0)
294 regnum
-= ymm16h_regnum
;
295 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
299 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
302 int ymm16_regnum
= tdep
->ymm16_regnum
;
304 if (ymm16_regnum
< 0)
307 regnum
-= ymm16_regnum
;
308 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
314 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
317 int bnd0_regnum
= tdep
->bnd0_regnum
;
322 regnum
-= bnd0_regnum
;
323 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
329 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
334 if (num_xmm_regs
== 0)
337 regnum
-= I387_XMM0_REGNUM (tdep
);
338 return regnum
>= 0 && regnum
< num_xmm_regs
;
341 /* XMM_512 register? */
344 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
347 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
349 if (num_xmm_avx512_regs
== 0)
352 regnum
-= I387_XMM16_REGNUM (tdep
);
353 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
357 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (I387_NUM_XMM_REGS (tdep
) == 0)
364 return (regnum
== I387_MXCSR_REGNUM (tdep
));
370 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
374 if (I387_ST0_REGNUM (tdep
) < 0)
377 return (I387_ST0_REGNUM (tdep
) <= regnum
378 && regnum
< I387_FCTRL_REGNUM (tdep
));
382 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
384 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
386 if (I387_ST0_REGNUM (tdep
) < 0)
389 return (I387_FCTRL_REGNUM (tdep
) <= regnum
390 && regnum
< I387_XMM0_REGNUM (tdep
));
393 /* BNDr (raw) register? */
396 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
400 if (I387_BND0R_REGNUM (tdep
) < 0)
403 regnum
-= tdep
->bnd0r_regnum
;
404 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
407 /* BND control register? */
410 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
414 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
417 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
418 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
424 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
427 int pkru_regnum
= tdep
->pkru_regnum
;
432 regnum
-= pkru_regnum
;
433 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
436 /* Return the name of register REGNUM, or the empty string if it is
437 an anonymous register. */
440 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
442 /* Hide the upper YMM registers. */
443 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
446 /* Hide the upper YMM16-31 registers. */
447 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
450 /* Hide the upper ZMM registers. */
451 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
454 return tdesc_register_name (gdbarch
, regnum
);
457 /* Return the name of register REGNUM. */
460 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
463 if (i386_bnd_regnum_p (gdbarch
, regnum
))
464 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
465 if (i386_mmx_regnum_p (gdbarch
, regnum
))
466 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
467 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
468 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
469 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
470 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
471 else if (i386_byte_regnum_p (gdbarch
, regnum
))
472 return i386_byte_names
[regnum
- tdep
->al_regnum
];
473 else if (i386_word_regnum_p (gdbarch
, regnum
))
474 return i386_word_names
[regnum
- tdep
->ax_regnum
];
476 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
479 /* Convert a dbx register number REG to the appropriate register
480 number used by GDB. */
483 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
487 /* This implements what GCC calls the "default" register map
488 (dbx_register_map[]). */
490 if (reg
>= 0 && reg
<= 7)
492 /* General-purpose registers. The debug info calls %ebp
493 register 4, and %esp register 5. */
500 else if (reg
>= 12 && reg
<= 19)
502 /* Floating-point registers. */
503 return reg
- 12 + I387_ST0_REGNUM (tdep
);
505 else if (reg
>= 21 && reg
<= 28)
508 int ymm0_regnum
= tdep
->ymm0_regnum
;
511 && i386_xmm_regnum_p (gdbarch
, reg
))
512 return reg
- 21 + ymm0_regnum
;
514 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
516 else if (reg
>= 29 && reg
<= 36)
519 return reg
- 29 + I387_MM0_REGNUM (tdep
);
522 /* This will hopefully provoke a warning. */
523 return gdbarch_num_cooked_regs (gdbarch
);
526 /* Convert SVR4 DWARF register number REG to the appropriate register number
530 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 /* This implements the GCC register map that tries to be compatible
535 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
537 /* The SVR4 register numbering includes %eip and %eflags, and
538 numbers the floating point registers differently. */
539 if (reg
>= 0 && reg
<= 9)
541 /* General-purpose registers. */
544 else if (reg
>= 11 && reg
<= 18)
546 /* Floating-point registers. */
547 return reg
- 11 + I387_ST0_REGNUM (tdep
);
549 else if (reg
>= 21 && reg
<= 36)
551 /* The SSE and MMX registers have the same numbers as with dbx. */
552 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
557 case 37: return I387_FCTRL_REGNUM (tdep
);
558 case 38: return I387_FSTAT_REGNUM (tdep
);
559 case 39: return I387_MXCSR_REGNUM (tdep
);
560 case 40: return I386_ES_REGNUM
;
561 case 41: return I386_CS_REGNUM
;
562 case 42: return I386_SS_REGNUM
;
563 case 43: return I386_DS_REGNUM
;
564 case 44: return I386_FS_REGNUM
;
565 case 45: return I386_GS_REGNUM
;
571 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
572 num_regs + num_pseudo_regs for other debug formats. */
575 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
577 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
580 return gdbarch_num_cooked_regs (gdbarch
);
586 /* This is the variable that is set with "set disassembly-flavor", and
587 its legitimate values. */
588 static const char att_flavor
[] = "att";
589 static const char intel_flavor
[] = "intel";
590 static const char *const valid_flavors
[] =
596 static const char *disassembly_flavor
= att_flavor
;
599 /* Use the program counter to determine the contents and size of a
600 breakpoint instruction. Return a pointer to a string of bytes that
601 encode a breakpoint instruction, store the length of the string in
602 *LEN and optionally adjust *PC to point to the correct memory
603 location for inserting the breakpoint.
605 On the i386 we have a single breakpoint that fits in a single byte
606 and can be inserted anywhere.
608 This function is 64-bit safe. */
610 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
612 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
615 /* Displaced instruction handling. */
617 /* Skip the legacy instruction prefixes in INSN.
618 Not all prefixes are valid for any particular insn
619 but we needn't care, the insn will fault if it's invalid.
620 The result is a pointer to the first opcode byte,
621 or NULL if we run off the end of the buffer. */
624 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
626 gdb_byte
*end
= insn
+ max_len
;
632 case DATA_PREFIX_OPCODE
:
633 case ADDR_PREFIX_OPCODE
:
634 case CS_PREFIX_OPCODE
:
635 case DS_PREFIX_OPCODE
:
636 case ES_PREFIX_OPCODE
:
637 case FS_PREFIX_OPCODE
:
638 case GS_PREFIX_OPCODE
:
639 case SS_PREFIX_OPCODE
:
640 case LOCK_PREFIX_OPCODE
:
641 case REPE_PREFIX_OPCODE
:
642 case REPNE_PREFIX_OPCODE
:
654 i386_absolute_jmp_p (const gdb_byte
*insn
)
656 /* jmp far (absolute address in operand). */
662 /* jump near, absolute indirect (/4). */
663 if ((insn
[1] & 0x38) == 0x20)
666 /* jump far, absolute indirect (/5). */
667 if ((insn
[1] & 0x38) == 0x28)
674 /* Return non-zero if INSN is a jump, zero otherwise. */
677 i386_jmp_p (const gdb_byte
*insn
)
679 /* jump short, relative. */
683 /* jump near, relative. */
687 return i386_absolute_jmp_p (insn
);
691 i386_absolute_call_p (const gdb_byte
*insn
)
693 /* call far, absolute. */
699 /* Call near, absolute indirect (/2). */
700 if ((insn
[1] & 0x38) == 0x10)
703 /* Call far, absolute indirect (/3). */
704 if ((insn
[1] & 0x38) == 0x18)
712 i386_ret_p (const gdb_byte
*insn
)
716 case 0xc2: /* ret near, pop N bytes. */
717 case 0xc3: /* ret near */
718 case 0xca: /* ret far, pop N bytes. */
719 case 0xcb: /* ret far */
720 case 0xcf: /* iret */
729 i386_call_p (const gdb_byte
*insn
)
731 if (i386_absolute_call_p (insn
))
734 /* call near, relative. */
741 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
742 length in bytes. Otherwise, return zero. */
745 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
747 /* Is it 'int $0x80'? */
748 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
749 /* Or is it 'sysenter'? */
750 || (insn
[0] == 0x0f && insn
[1] == 0x34)
751 /* Or is it 'syscall'? */
752 || (insn
[0] == 0x0f && insn
[1] == 0x05))
761 /* The gdbarch insn_is_call method. */
764 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
766 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
768 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
769 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
771 return i386_call_p (insn
);
774 /* The gdbarch insn_is_ret method. */
777 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
779 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
781 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
782 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
784 return i386_ret_p (insn
);
787 /* The gdbarch insn_is_jump method. */
790 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
792 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
794 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
795 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
797 return i386_jmp_p (insn
);
800 /* Some kernels may run one past a syscall insn, so we have to cope. */
802 displaced_step_closure_up
803 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
804 CORE_ADDR from
, CORE_ADDR to
,
805 struct regcache
*regs
)
807 size_t len
= gdbarch_max_insn_length (gdbarch
);
808 std::unique_ptr
<i386_displaced_step_closure
> closure
809 (new i386_displaced_step_closure (len
));
810 gdb_byte
*buf
= closure
->buf
.data ();
812 read_memory (from
, buf
, len
);
814 /* GDB may get control back after the insn after the syscall.
815 Presumably this is a kernel bug.
816 If this is a syscall, make sure there's a nop afterwards. */
821 insn
= i386_skip_prefixes (buf
, len
);
822 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
823 insn
[syscall_length
] = NOP_OPCODE
;
826 write_memory (to
, buf
, len
);
830 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
831 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
832 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
835 /* This is a work around for a problem with g++ 4.8. */
836 return displaced_step_closure_up (closure
.release ());
839 /* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
843 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
844 struct displaced_step_closure
*closure_
,
845 CORE_ADDR from
, CORE_ADDR to
,
846 struct regcache
*regs
)
848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
854 ULONGEST insn_offset
= to
- from
;
856 i386_displaced_step_closure
*closure
857 = (i386_displaced_step_closure
*) closure_
;
858 gdb_byte
*insn
= closure
->buf
.data ();
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte
*insn_start
= insn
;
863 fprintf_unfiltered (gdb_stdlog
,
864 "displaced: fixup (%s, %s), "
865 "insn = 0x%02x 0x%02x ...\n",
866 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
869 /* The list of issues to contend with here is taken from
870 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
871 Yay for Free Software! */
873 /* Relocate the %eip, if necessary. */
875 /* The instruction recognizers we use assume any leading prefixes
876 have been skipped. */
878 /* This is the size of the buffer in closure. */
879 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
880 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
881 /* If there are too many prefixes, just ignore the insn.
882 It will fault when run. */
887 /* Except in the case of absolute or indirect jump or call
888 instructions, or a return instruction, the new eip is relative to
889 the displaced instruction; make it relative. Well, signal
890 handler returns don't need relocation either, but we use the
891 value of %eip to recognize those; see below. */
892 if (! i386_absolute_jmp_p (insn
)
893 && ! i386_absolute_call_p (insn
)
894 && ! i386_ret_p (insn
))
899 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
901 /* A signal trampoline system call changes the %eip, resuming
902 execution of the main program after the signal handler has
903 returned. That makes them like 'return' instructions; we
904 shouldn't relocate %eip.
906 But most system calls don't, and we do need to relocate %eip.
908 Our heuristic for distinguishing these cases: if stepping
909 over the system call instruction left control directly after
910 the instruction, the we relocate --- control almost certainly
911 doesn't belong in the displaced copy. Otherwise, we assume
912 the instruction has put control where it belongs, and leave
913 it unrelocated. Goodness help us if there are PC-relative
915 if (i386_syscall_p (insn
, &insn_len
)
916 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
917 /* GDB can get control back after the insn after the syscall.
918 Presumably this is a kernel bug.
919 i386_displaced_step_copy_insn ensures its a nop,
920 we add one to the length for it. */
921 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
924 fprintf_unfiltered (gdb_stdlog
,
925 "displaced: syscall changed %%eip; "
930 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
932 /* If we just stepped over a breakpoint insn, we don't backup
933 the pc on purpose; this is to match behaviour without
936 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
939 fprintf_unfiltered (gdb_stdlog
,
941 "relocated %%eip from %s to %s\n",
942 paddress (gdbarch
, orig_eip
),
943 paddress (gdbarch
, eip
));
947 /* If the instruction was PUSHFL, then the TF bit will be set in the
948 pushed value, and should be cleared. We'll leave this for later,
949 since GDB already messes up the TF flag when stepping over a
952 /* If the instruction was a call, the return address now atop the
953 stack is the address following the copied instruction. We need
954 to make it the address following the original instruction. */
955 if (i386_call_p (insn
))
959 const ULONGEST retaddr_len
= 4;
961 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
962 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
963 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
964 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
967 fprintf_unfiltered (gdb_stdlog
,
968 "displaced: relocated return addr at %s to %s\n",
969 paddress (gdbarch
, esp
),
970 paddress (gdbarch
, retaddr
));
975 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
977 target_write_memory (*to
, buf
, len
);
982 i386_relocate_instruction (struct gdbarch
*gdbarch
,
983 CORE_ADDR
*to
, CORE_ADDR oldloc
)
985 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
986 gdb_byte buf
[I386_MAX_INSN_LEN
];
987 int offset
= 0, rel32
, newrel
;
989 gdb_byte
*insn
= buf
;
991 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
993 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
994 I386_MAX_INSN_LEN
, oldloc
);
996 /* Get past the prefixes. */
997 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
999 /* Adjust calls with 32-bit relative addresses as push/jump, with
1000 the address pushed being the location where the original call in
1001 the user program would return to. */
1002 if (insn
[0] == 0xe8)
1004 gdb_byte push_buf
[16];
1005 unsigned int ret_addr
;
1007 /* Where "ret" in the original code will return to. */
1008 ret_addr
= oldloc
+ insn_length
;
1009 push_buf
[0] = 0x68; /* pushq $... */
1010 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1011 /* Push the push. */
1012 append_insns (to
, 5, push_buf
);
1014 /* Convert the relative call to a relative jump. */
1017 /* Adjust the destination offset. */
1018 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1019 newrel
= (oldloc
- *to
) + rel32
;
1020 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1022 if (debug_displaced
)
1023 fprintf_unfiltered (gdb_stdlog
,
1024 "Adjusted insn rel32=%s at %s to"
1025 " rel32=%s at %s\n",
1026 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1027 hex_string (newrel
), paddress (gdbarch
, *to
));
1029 /* Write the adjusted jump into its displaced location. */
1030 append_insns (to
, 5, insn
);
1034 /* Adjust jumps with 32-bit relative addresses. Calls are already
1036 if (insn
[0] == 0xe9)
1038 /* Adjust conditional jumps. */
1039 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1044 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1045 newrel
= (oldloc
- *to
) + rel32
;
1046 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1047 if (debug_displaced
)
1048 fprintf_unfiltered (gdb_stdlog
,
1049 "Adjusted insn rel32=%s at %s to"
1050 " rel32=%s at %s\n",
1051 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1052 hex_string (newrel
), paddress (gdbarch
, *to
));
1055 /* Write the adjusted instructions into their displaced
1057 append_insns (to
, insn_length
, buf
);
1061 #ifdef I386_REGNO_TO_SYMMETRY
1062 #error "The Sequent Symmetry is no longer supported."
1065 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1066 and %esp "belong" to the calling function. Therefore these
1067 registers should be saved if they're going to be modified. */
1069 /* The maximum number of saved registers. This should include all
1070 registers mentioned above, and %eip. */
1071 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1073 struct i386_frame_cache
1081 /* Saved registers. */
1082 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1087 /* Stack space reserved for local variables. */
1091 /* Allocate and initialize a frame cache. */
1093 static struct i386_frame_cache
*
1094 i386_alloc_frame_cache (void)
1096 struct i386_frame_cache
*cache
;
1099 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1104 cache
->sp_offset
= -4;
1107 /* Saved registers. We initialize these to -1 since zero is a valid
1108 offset (that's where %ebp is supposed to be stored). */
1109 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1110 cache
->saved_regs
[i
] = -1;
1111 cache
->saved_sp
= 0;
1112 cache
->saved_sp_reg
= -1;
1113 cache
->pc_in_eax
= 0;
1115 /* Frameless until proven otherwise. */
1121 /* If the instruction at PC is a jump, return the address of its
1122 target. Otherwise, return PC. */
1125 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1127 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1132 if (target_read_code (pc
, &op
, 1))
1139 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1145 /* Relative jump: if data16 == 0, disp32, else disp16. */
1148 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1150 /* Include the size of the jmp instruction (including the
1156 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1158 /* Include the size of the jmp instruction. */
1163 /* Relative jump, disp8 (ignore data16). */
1164 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1166 delta
+= data16
+ 2;
1173 /* Check whether PC points at a prologue for a function returning a
1174 structure or union. If so, it updates CACHE and returns the
1175 address of the first instruction after the code sequence that
1176 removes the "hidden" argument from the stack or CURRENT_PC,
1177 whichever is smaller. Otherwise, return PC. */
1180 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1181 struct i386_frame_cache
*cache
)
1183 /* Functions that return a structure or union start with:
1186 xchgl %eax, (%esp) 0x87 0x04 0x24
1187 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1189 (the System V compiler puts out the second `xchg' instruction,
1190 and the assembler doesn't try to optimize it, so the 'sib' form
1191 gets generated). This sequence is used to get the address of the
1192 return buffer for a function that returns a structure. */
1193 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1194 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1198 if (current_pc
<= pc
)
1201 if (target_read_code (pc
, &op
, 1))
1204 if (op
!= 0x58) /* popl %eax */
1207 if (target_read_code (pc
+ 1, buf
, 4))
1210 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1213 if (current_pc
== pc
)
1215 cache
->sp_offset
+= 4;
1219 if (current_pc
== pc
+ 1)
1221 cache
->pc_in_eax
= 1;
1225 if (buf
[1] == proto1
[1])
1232 i386_skip_probe (CORE_ADDR pc
)
1234 /* A function may start with
1248 if (target_read_code (pc
, &op
, 1))
1251 if (op
== 0x68 || op
== 0x6a)
1255 /* Skip past the `pushl' instruction; it has either a one-byte or a
1256 four-byte operand, depending on the opcode. */
1262 /* Read the following 8 bytes, which should be `call _probe' (6
1263 bytes) followed by `addl $4,%esp' (2 bytes). */
1264 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1265 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1266 pc
+= delta
+ sizeof (buf
);
1272 /* GCC 4.1 and later, can put code in the prologue to realign the
1273 stack pointer. Check whether PC points to such code, and update
1274 CACHE accordingly. Return the first instruction after the code
1275 sequence or CURRENT_PC, whichever is smaller. If we don't
1276 recognize the code, return PC. */
1279 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1280 struct i386_frame_cache
*cache
)
1282 /* There are 2 code sequences to re-align stack before the frame
1285 1. Use a caller-saved saved register:
1291 2. Use a callee-saved saved register:
1298 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1300 0x83 0xe4 0xf0 andl $-16, %esp
1301 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1306 int offset
, offset_and
;
1307 static int regnums
[8] = {
1308 I386_EAX_REGNUM
, /* %eax */
1309 I386_ECX_REGNUM
, /* %ecx */
1310 I386_EDX_REGNUM
, /* %edx */
1311 I386_EBX_REGNUM
, /* %ebx */
1312 I386_ESP_REGNUM
, /* %esp */
1313 I386_EBP_REGNUM
, /* %ebp */
1314 I386_ESI_REGNUM
, /* %esi */
1315 I386_EDI_REGNUM
/* %edi */
1318 if (target_read_code (pc
, buf
, sizeof buf
))
1321 /* Check caller-saved saved register. The first instruction has
1322 to be "leal 4(%esp), %reg". */
1323 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf
[1] & 0xc7) != 0x44)
1329 /* REG has register number. */
1330 reg
= (buf
[1] >> 3) & 7;
1335 /* Check callee-saved saved register. The first instruction
1336 has to be "pushl %reg". */
1337 if ((buf
[0] & 0xf8) != 0x50)
1343 /* The next instruction has to be "leal 8(%esp), %reg". */
1344 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1347 /* MOD must be binary 10 and R/M must be binary 100. */
1348 if ((buf
[2] & 0xc7) != 0x44)
1351 /* REG has register number. Registers in pushl and leal have to
1353 if (reg
!= ((buf
[2] >> 3) & 7))
1359 /* Rigister can't be %esp nor %ebp. */
1360 if (reg
== 4 || reg
== 5)
1363 /* The next instruction has to be "andl $-XXX, %esp". */
1364 if (buf
[offset
+ 1] != 0xe4
1365 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1368 offset_and
= offset
;
1369 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1371 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1372 0xfc. REG must be binary 110 and MOD must be binary 01. */
1373 if (buf
[offset
] != 0xff
1374 || buf
[offset
+ 2] != 0xfc
1375 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1378 /* R/M has register. Registers in leal and pushl have to be the
1380 if (reg
!= (buf
[offset
+ 1] & 7))
1383 if (current_pc
> pc
+ offset_and
)
1384 cache
->saved_sp_reg
= regnums
[reg
];
1386 return std::min (pc
+ offset
+ 3, current_pc
);
1389 /* Maximum instruction length we need to handle. */
1390 #define I386_MAX_MATCHED_INSN_LEN 6
1392 /* Instruction description. */
1396 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1397 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1400 /* Return whether instruction at PC matches PATTERN. */
1403 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1407 if (target_read_code (pc
, &op
, 1))
1410 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1412 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1413 int insn_matched
= 1;
1416 gdb_assert (pattern
.len
> 1);
1417 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1419 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1422 for (i
= 1; i
< pattern
.len
; i
++)
1424 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1427 return insn_matched
;
1432 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1433 the first instruction description that matches. Otherwise, return
1436 static struct i386_insn
*
1437 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1439 struct i386_insn
*pattern
;
1441 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1443 if (i386_match_pattern (pc
, *pattern
))
1450 /* Return whether PC points inside a sequence of instructions that
1451 matches INSN_PATTERNS. */
1454 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1456 CORE_ADDR current_pc
;
1458 struct i386_insn
*insn
;
1460 insn
= i386_match_insn (pc
, insn_patterns
);
1465 ix
= insn
- insn_patterns
;
1466 for (i
= ix
- 1; i
>= 0; i
--)
1468 current_pc
-= insn_patterns
[i
].len
;
1470 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1474 current_pc
= pc
+ insn
->len
;
1475 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1477 if (!i386_match_pattern (current_pc
, *insn
))
1480 current_pc
+= insn
->len
;
1486 /* Some special instructions that might be migrated by GCC into the
1487 part of the prologue that sets up the new stack frame. Because the
1488 stack frame hasn't been setup yet, no registers have been saved
1489 yet, and only the scratch registers %eax, %ecx and %edx can be
1492 struct i386_insn i386_frame_setup_skip_insns
[] =
1494 /* Check for `movb imm8, r' and `movl imm32, r'.
1496 ??? Should we handle 16-bit operand-sizes here? */
1498 /* `movb imm8, %al' and `movb imm8, %ah' */
1499 /* `movb imm8, %cl' and `movb imm8, %ch' */
1500 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1501 /* `movb imm8, %dl' and `movb imm8, %dh' */
1502 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1503 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1504 { 5, { 0xb8 }, { 0xfe } },
1505 /* `movl imm32, %edx' */
1506 { 5, { 0xba }, { 0xff } },
1508 /* Check for `mov imm32, r32'. Note that there is an alternative
1509 encoding for `mov m32, %eax'.
1511 ??? Should we handle SIB addressing here?
1512 ??? Should we handle 16-bit operand-sizes here? */
1514 /* `movl m32, %eax' */
1515 { 5, { 0xa1 }, { 0xff } },
1516 /* `movl m32, %eax' and `mov; m32, %ecx' */
1517 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1518 /* `movl m32, %edx' */
1519 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1521 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1522 Because of the symmetry, there are actually two ways to encode
1523 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1524 opcode bytes 0x31 and 0x33 for `xorl'. */
1526 /* `subl %eax, %eax' */
1527 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1528 /* `subl %ecx, %ecx' */
1529 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1530 /* `subl %edx, %edx' */
1531 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1532 /* `xorl %eax, %eax' */
1533 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1534 /* `xorl %ecx, %ecx' */
1535 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1536 /* `xorl %edx, %edx' */
1537 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1542 /* Check whether PC points to a no-op instruction. */
1544 i386_skip_noop (CORE_ADDR pc
)
1549 if (target_read_code (pc
, &op
, 1))
1555 /* Ignore `nop' instruction. */
1559 if (target_read_code (pc
, &op
, 1))
1563 /* Ignore no-op instruction `mov %edi, %edi'.
1564 Microsoft system dlls often start with
1565 a `mov %edi,%edi' instruction.
1566 The 5 bytes before the function start are
1567 filled with `nop' instructions.
1568 This pattern can be used for hot-patching:
1569 The `mov %edi, %edi' instruction can be replaced by a
1570 near jump to the location of the 5 `nop' instructions
1571 which can be replaced by a 32-bit jump to anywhere
1572 in the 32-bit address space. */
1574 else if (op
== 0x8b)
1576 if (target_read_code (pc
+ 1, &op
, 1))
1582 if (target_read_code (pc
, &op
, 1))
1592 /* Check whether PC points at a code that sets up a new stack frame.
1593 If so, it updates CACHE and returns the address of the first
1594 instruction after the sequence that sets up the frame or LIMIT,
1595 whichever is smaller. If we don't recognize the code, return PC. */
1598 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1599 CORE_ADDR pc
, CORE_ADDR limit
,
1600 struct i386_frame_cache
*cache
)
1602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1603 struct i386_insn
*insn
;
1610 if (target_read_code (pc
, &op
, 1))
1613 if (op
== 0x55) /* pushl %ebp */
1615 /* Take into account that we've executed the `pushl %ebp' that
1616 starts this instruction sequence. */
1617 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1618 cache
->sp_offset
+= 4;
1621 /* If that's all, return now. */
1625 /* Check for some special instructions that might be migrated by
1626 GCC into the prologue and skip them. At this point in the
1627 prologue, code should only touch the scratch registers %eax,
1628 %ecx and %edx, so while the number of possibilities is sheer,
1631 Make sure we only skip these instructions if we later see the
1632 `movl %esp, %ebp' that actually sets up the frame. */
1633 while (pc
+ skip
< limit
)
1635 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1642 /* If that's all, return now. */
1643 if (limit
<= pc
+ skip
)
1646 if (target_read_code (pc
+ skip
, &op
, 1))
1649 /* The i386 prologue looks like
1655 and a different prologue can be generated for atom.
1659 lea -0x10(%esp),%esp
1661 We handle both of them here. */
1665 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1667 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1673 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1678 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1679 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1688 /* OK, we actually have a frame. We just don't know how large
1689 it is yet. Set its size to zero. We'll adjust it if
1690 necessary. We also now commit to skipping the special
1691 instructions mentioned before. */
1694 /* If that's all, return now. */
1698 /* Check for stack adjustment
1704 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1705 reg, so we don't have to worry about a data16 prefix. */
1706 if (target_read_code (pc
, &op
, 1))
1710 /* `subl' with 8-bit immediate. */
1711 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1712 /* Some instruction starting with 0x83 other than `subl'. */
1715 /* `subl' with signed 8-bit immediate (though it wouldn't
1716 make sense to be negative). */
1717 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1720 else if (op
== 0x81)
1722 /* Maybe it is `subl' with a 32-bit immediate. */
1723 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1724 /* Some instruction starting with 0x81 other than `subl'. */
1727 /* It is `subl' with a 32-bit immediate. */
1728 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1731 else if (op
== 0x8d)
1733 /* The ModR/M byte is 0x64. */
1734 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1736 /* 'lea' with 8-bit displacement. */
1737 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1742 /* Some instruction other than `subl' nor 'lea'. */
1746 else if (op
== 0xc8) /* enter */
1748 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1755 /* Check whether PC points at code that saves registers on the stack.
1756 If so, it updates CACHE and returns the address of the first
1757 instruction after the register saves or CURRENT_PC, whichever is
1758 smaller. Otherwise, return PC. */
1761 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1762 struct i386_frame_cache
*cache
)
1764 CORE_ADDR offset
= 0;
1768 if (cache
->locals
> 0)
1769 offset
-= cache
->locals
;
1770 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1772 if (target_read_code (pc
, &op
, 1))
1774 if (op
< 0x50 || op
> 0x57)
1778 cache
->saved_regs
[op
- 0x50] = offset
;
1779 cache
->sp_offset
+= 4;
1786 /* Do a full analysis of the prologue at PC and update CACHE
1787 accordingly. Bail out early if CURRENT_PC is reached. Return the
1788 address where the analysis stopped.
1790 We handle these cases:
1792 The startup sequence can be at the start of the function, or the
1793 function can start with a branch to startup code at the end.
1795 %ebp can be set up with either the 'enter' instruction, or "pushl
1796 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1797 once used in the System V compiler).
1799 Local space is allocated just below the saved %ebp by either the
1800 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1801 16-bit unsigned argument for space to allocate, and the 'addl'
1802 instruction could have either a signed byte, or 32-bit immediate.
1804 Next, the registers used by this function are pushed. With the
1805 System V compiler they will always be in the order: %edi, %esi,
1806 %ebx (and sometimes a harmless bug causes it to also save but not
1807 restore %eax); however, the code below is willing to see the pushes
1808 in any order, and will handle up to 8 of them.
1810 If the setup sequence is at the end of the function, then the next
1811 instruction will be a branch back to the start. */
1814 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1815 CORE_ADDR pc
, CORE_ADDR current_pc
,
1816 struct i386_frame_cache
*cache
)
1818 pc
= i386_skip_noop (pc
);
1819 pc
= i386_follow_jump (gdbarch
, pc
);
1820 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1821 pc
= i386_skip_probe (pc
);
1822 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1823 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1824 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1827 /* Return PC of first real instruction. */
1830 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1832 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1834 static gdb_byte pic_pat
[6] =
1836 0xe8, 0, 0, 0, 0, /* call 0x0 */
1837 0x5b, /* popl %ebx */
1839 struct i386_frame_cache cache
;
1843 CORE_ADDR func_addr
;
1845 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1847 CORE_ADDR post_prologue_pc
1848 = skip_prologue_using_sal (gdbarch
, func_addr
);
1849 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1851 /* LLVM backend (Clang/Flang) always emits a line note before the
1852 prologue and another one after. We trust clang to emit usable
1854 if (post_prologue_pc
1856 && COMPUNIT_PRODUCER (cust
) != NULL
1857 && producer_is_llvm (COMPUNIT_PRODUCER (cust
))))
1858 return std::max (start_pc
, post_prologue_pc
);
1862 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1863 if (cache
.locals
< 0)
1866 /* Found valid frame setup. */
1868 /* The native cc on SVR4 in -K PIC mode inserts the following code
1869 to get the address of the global offset table (GOT) into register
1874 movl %ebx,x(%ebp) (optional)
1877 This code is with the rest of the prologue (at the end of the
1878 function), so we have to skip it to get to the first real
1879 instruction at the start of the function. */
1881 for (i
= 0; i
< 6; i
++)
1883 if (target_read_code (pc
+ i
, &op
, 1))
1886 if (pic_pat
[i
] != op
)
1893 if (target_read_code (pc
+ delta
, &op
, 1))
1896 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1898 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1900 if (op
== 0x5d) /* One byte offset from %ebp. */
1902 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1904 else /* Unexpected instruction. */
1907 if (target_read_code (pc
+ delta
, &op
, 1))
1912 if (delta
> 0 && op
== 0x81
1913 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1920 /* If the function starts with a branch (to startup code at the end)
1921 the last instruction should bring us back to the first
1922 instruction of the real code. */
1923 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1924 pc
= i386_follow_jump (gdbarch
, pc
);
1929 /* Check that the code pointed to by PC corresponds to a call to
1930 __main, skip it if so. Return PC otherwise. */
1933 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1935 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1938 if (target_read_code (pc
, &op
, 1))
1944 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1946 /* Make sure address is computed correctly as a 32bit
1947 integer even if CORE_ADDR is 64 bit wide. */
1948 struct bound_minimal_symbol s
;
1949 CORE_ADDR call_dest
;
1951 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1952 call_dest
= call_dest
& 0xffffffffU
;
1953 s
= lookup_minimal_symbol_by_pc (call_dest
);
1954 if (s
.minsym
!= NULL
1955 && s
.minsym
->linkage_name () != NULL
1956 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1964 /* This function is 64-bit safe. */
1967 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1971 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1972 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1976 /* Normal frames. */
1979 i386_frame_cache_1 (struct frame_info
*this_frame
,
1980 struct i386_frame_cache
*cache
)
1982 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1983 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1987 cache
->pc
= get_frame_func (this_frame
);
1989 /* In principle, for normal frames, %ebp holds the frame pointer,
1990 which holds the base address for the current stack frame.
1991 However, for functions that don't need it, the frame pointer is
1992 optional. For these "frameless" functions the frame pointer is
1993 actually the frame pointer of the calling frame. Signal
1994 trampolines are just a special case of a "frameless" function.
1995 They (usually) share their frame pointer with the frame that was
1996 in progress when the signal occurred. */
1998 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1999 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
2000 if (cache
->base
== 0)
2006 /* For normal frames, %eip is stored at 4(%ebp). */
2007 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2010 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2013 if (cache
->locals
< 0)
2015 /* We didn't find a valid frame, which means that CACHE->base
2016 currently holds the frame pointer for our calling frame. If
2017 we're at the start of a function, or somewhere half-way its
2018 prologue, the function's frame probably hasn't been fully
2019 setup yet. Try to reconstruct the base address for the stack
2020 frame by looking at the stack pointer. For truly "frameless"
2021 functions this might work too. */
2023 if (cache
->saved_sp_reg
!= -1)
2025 /* Saved stack pointer has been saved. */
2026 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2027 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2029 /* We're halfway aligning the stack. */
2030 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2031 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2033 /* This will be added back below. */
2034 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2036 else if (cache
->pc
!= 0
2037 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2039 /* We're in a known function, but did not find a frame
2040 setup. Assume that the function does not use %ebp.
2041 Alternatively, we may have jumped to an invalid
2042 address; in that case there is definitely no new
2044 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2045 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2049 /* We're in an unknown function. We could not find the start
2050 of the function to analyze the prologue; our best option is
2051 to assume a typical frame layout with the caller's %ebp
2053 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2056 if (cache
->saved_sp_reg
!= -1)
2058 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2059 register may be unavailable). */
2060 if (cache
->saved_sp
== 0
2061 && deprecated_frame_register_read (this_frame
,
2062 cache
->saved_sp_reg
, buf
))
2063 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2065 /* Now that we have the base address for the stack frame we can
2066 calculate the value of %esp in the calling frame. */
2067 else if (cache
->saved_sp
== 0)
2068 cache
->saved_sp
= cache
->base
+ 8;
2070 /* Adjust all the saved registers such that they contain addresses
2071 instead of offsets. */
2072 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2073 if (cache
->saved_regs
[i
] != -1)
2074 cache
->saved_regs
[i
] += cache
->base
;
2079 static struct i386_frame_cache
*
2080 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2082 struct i386_frame_cache
*cache
;
2085 return (struct i386_frame_cache
*) *this_cache
;
2087 cache
= i386_alloc_frame_cache ();
2088 *this_cache
= cache
;
2092 i386_frame_cache_1 (this_frame
, cache
);
2094 catch (const gdb_exception_error
&ex
)
2096 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2104 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2105 struct frame_id
*this_id
)
2107 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2110 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2111 else if (cache
->base
== 0)
2113 /* This marks the outermost frame. */
2117 /* See the end of i386_push_dummy_call. */
2118 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2122 static enum unwind_stop_reason
2123 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2126 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2129 return UNWIND_UNAVAILABLE
;
2131 /* This marks the outermost frame. */
2132 if (cache
->base
== 0)
2133 return UNWIND_OUTERMOST
;
2135 return UNWIND_NO_REASON
;
2138 static struct value
*
2139 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2142 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2144 gdb_assert (regnum
>= 0);
2146 /* The System V ABI says that:
2148 "The flags register contains the system flags, such as the
2149 direction flag and the carry flag. The direction flag must be
2150 set to the forward (that is, zero) direction before entry and
2151 upon exit from a function. Other user flags have no specified
2152 role in the standard calling sequence and are not preserved."
2154 To guarantee the "upon exit" part of that statement we fake a
2155 saved flags register that has its direction flag cleared.
2157 Note that GCC doesn't seem to rely on the fact that the direction
2158 flag is cleared after a function return; it always explicitly
2159 clears the flag before operations where it matters.
2161 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2162 right thing to do. The way we fake the flags register here makes
2163 it impossible to change it. */
2165 if (regnum
== I386_EFLAGS_REGNUM
)
2169 val
= get_frame_register_unsigned (this_frame
, regnum
);
2171 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2174 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2175 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2177 if (regnum
== I386_ESP_REGNUM
2178 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2180 /* If the SP has been saved, but we don't know where, then this
2181 means that SAVED_SP_REG register was found unavailable back
2182 when we built the cache. */
2183 if (cache
->saved_sp
== 0)
2184 return frame_unwind_got_register (this_frame
, regnum
,
2185 cache
->saved_sp_reg
);
2187 return frame_unwind_got_constant (this_frame
, regnum
,
2191 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2192 return frame_unwind_got_memory (this_frame
, regnum
,
2193 cache
->saved_regs
[regnum
]);
2195 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2198 static const struct frame_unwind i386_frame_unwind
=
2201 i386_frame_unwind_stop_reason
,
2203 i386_frame_prev_register
,
2205 default_frame_sniffer
2208 /* Normal frames, but in a function epilogue. */
2210 /* Implement the stack_frame_destroyed_p gdbarch method.
2212 The epilogue is defined here as the 'ret' instruction, which will
2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2214 the function's stack frame. */
2217 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2220 struct compunit_symtab
*cust
;
2222 cust
= find_pc_compunit_symtab (pc
);
2223 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2226 if (target_read_memory (pc
, &insn
, 1))
2227 return 0; /* Can't read memory at pc. */
2229 if (insn
!= 0xc3) /* 'ret' instruction. */
2236 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2237 struct frame_info
*this_frame
,
2238 void **this_prologue_cache
)
2240 if (frame_relative_level (this_frame
) == 0)
2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2242 get_frame_pc (this_frame
));
2247 static struct i386_frame_cache
*
2248 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2250 struct i386_frame_cache
*cache
;
2254 return (struct i386_frame_cache
*) *this_cache
;
2256 cache
= i386_alloc_frame_cache ();
2257 *this_cache
= cache
;
2261 cache
->pc
= get_frame_func (this_frame
);
2263 /* At this point the stack looks as if we just entered the
2264 function, with the return address at the top of the
2266 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2267 cache
->base
= sp
+ cache
->sp_offset
;
2268 cache
->saved_sp
= cache
->base
+ 8;
2269 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2273 catch (const gdb_exception_error
&ex
)
2275 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2282 static enum unwind_stop_reason
2283 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2286 struct i386_frame_cache
*cache
=
2287 i386_epilogue_frame_cache (this_frame
, this_cache
);
2290 return UNWIND_UNAVAILABLE
;
2292 return UNWIND_NO_REASON
;
2296 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2298 struct frame_id
*this_id
)
2300 struct i386_frame_cache
*cache
=
2301 i386_epilogue_frame_cache (this_frame
, this_cache
);
2304 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2306 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2309 static struct value
*
2310 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2311 void **this_cache
, int regnum
)
2313 /* Make sure we've initialized the cache. */
2314 i386_epilogue_frame_cache (this_frame
, this_cache
);
2316 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2319 static const struct frame_unwind i386_epilogue_frame_unwind
=
2322 i386_epilogue_frame_unwind_stop_reason
,
2323 i386_epilogue_frame_this_id
,
2324 i386_epilogue_frame_prev_register
,
2326 i386_epilogue_frame_sniffer
2330 /* Stack-based trampolines. */
2332 /* These trampolines are used on cross x86 targets, when taking the
2333 address of a nested function. When executing these trampolines,
2334 no stack frame is set up, so we are in a similar situation as in
2335 epilogues and i386_epilogue_frame_this_id can be re-used. */
2337 /* Static chain passed in register. */
2339 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2341 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2342 { 5, { 0xb8 }, { 0xfe } },
2345 { 5, { 0xe9 }, { 0xff } },
2350 /* Static chain passed on stack (when regparm=3). */
2352 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2355 { 5, { 0x68 }, { 0xff } },
2358 { 5, { 0xe9 }, { 0xff } },
2363 /* Return whether PC points inside a stack trampoline. */
2366 i386_in_stack_tramp_p (CORE_ADDR pc
)
2371 /* A stack trampoline is detected if no name is associated
2372 to the current pc and if it points inside a trampoline
2375 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2379 if (target_read_memory (pc
, &insn
, 1))
2382 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2383 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2390 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2391 struct frame_info
*this_frame
,
2394 if (frame_relative_level (this_frame
) == 0)
2395 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2400 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2403 i386_epilogue_frame_unwind_stop_reason
,
2404 i386_epilogue_frame_this_id
,
2405 i386_epilogue_frame_prev_register
,
2407 i386_stack_tramp_frame_sniffer
2410 /* Generate a bytecode expression to get the value of the saved PC. */
2413 i386_gen_return_address (struct gdbarch
*gdbarch
,
2414 struct agent_expr
*ax
, struct axs_value
*value
,
2417 /* The following sequence assumes the traditional use of the base
2419 ax_reg (ax
, I386_EBP_REGNUM
);
2421 ax_simple (ax
, aop_add
);
2422 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2423 value
->kind
= axs_lvalue_memory
;
2427 /* Signal trampolines. */
2429 static struct i386_frame_cache
*
2430 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2432 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2433 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2435 struct i386_frame_cache
*cache
;
2440 return (struct i386_frame_cache
*) *this_cache
;
2442 cache
= i386_alloc_frame_cache ();
2446 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2447 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2449 addr
= tdep
->sigcontext_addr (this_frame
);
2450 if (tdep
->sc_reg_offset
)
2454 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2456 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2457 if (tdep
->sc_reg_offset
[i
] != -1)
2458 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2462 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2463 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2468 catch (const gdb_exception_error
&ex
)
2470 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2474 *this_cache
= cache
;
2478 static enum unwind_stop_reason
2479 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2482 struct i386_frame_cache
*cache
=
2483 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2486 return UNWIND_UNAVAILABLE
;
2488 return UNWIND_NO_REASON
;
2492 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2493 struct frame_id
*this_id
)
2495 struct i386_frame_cache
*cache
=
2496 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2499 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2502 /* See the end of i386_push_dummy_call. */
2503 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2507 static struct value
*
2508 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2509 void **this_cache
, int regnum
)
2511 /* Make sure we've initialized the cache. */
2512 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2514 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2518 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2519 struct frame_info
*this_frame
,
2520 void **this_prologue_cache
)
2522 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2524 /* We shouldn't even bother if we don't have a sigcontext_addr
2526 if (tdep
->sigcontext_addr
== NULL
)
2529 if (tdep
->sigtramp_p
!= NULL
)
2531 if (tdep
->sigtramp_p (this_frame
))
2535 if (tdep
->sigtramp_start
!= 0)
2537 CORE_ADDR pc
= get_frame_pc (this_frame
);
2539 gdb_assert (tdep
->sigtramp_end
!= 0);
2540 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2547 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2550 i386_sigtramp_frame_unwind_stop_reason
,
2551 i386_sigtramp_frame_this_id
,
2552 i386_sigtramp_frame_prev_register
,
2554 i386_sigtramp_frame_sniffer
2559 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2561 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2566 static const struct frame_base i386_frame_base
=
2569 i386_frame_base_address
,
2570 i386_frame_base_address
,
2571 i386_frame_base_address
2574 static struct frame_id
2575 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2579 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2581 /* See the end of i386_push_dummy_call. */
2582 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2585 /* _Decimal128 function return values need 16-byte alignment on the
2589 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2591 return sp
& -(CORE_ADDR
)16;
2595 /* Figure out where the longjmp will land. Slurp the args out of the
2596 stack. We expect the first arg to be a pointer to the jmp_buf
2597 structure from which we extract the address that we will land at.
2598 This address is copied into PC. This routine returns non-zero on
2602 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2605 CORE_ADDR sp
, jb_addr
;
2606 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2607 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2608 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2610 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2611 longjmp will land. */
2612 if (jb_pc_offset
== -1)
2615 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2616 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2617 if (target_read_memory (sp
+ 4, buf
, 4))
2620 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2621 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2624 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2629 /* Check whether TYPE must be 16-byte-aligned when passed as a
2630 function argument. 16-byte vectors, _Decimal128 and structures or
2631 unions containing such types must be 16-byte-aligned; other
2632 arguments are 4-byte-aligned. */
2635 i386_16_byte_align_p (struct type
*type
)
2637 type
= check_typedef (type
);
2638 if ((type
->code () == TYPE_CODE_DECFLOAT
2639 || (type
->code () == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2640 && TYPE_LENGTH (type
) == 16)
2642 if (type
->code () == TYPE_CODE_ARRAY
)
2643 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2644 if (type
->code () == TYPE_CODE_STRUCT
2645 || type
->code () == TYPE_CODE_UNION
)
2648 for (i
= 0; i
< type
->num_fields (); i
++)
2650 if (i386_16_byte_align_p (type
->field (i
).type ()))
2657 /* Implementation for set_gdbarch_push_dummy_code. */
2660 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2661 struct value
**args
, int nargs
, struct type
*value_type
,
2662 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2663 struct regcache
*regcache
)
2665 /* Use 0xcc breakpoint - 1 byte. */
2669 /* Keep the stack aligned. */
2673 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2674 calling convention. */
2677 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2678 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2679 int nargs
, struct value
**args
, CORE_ADDR sp
,
2680 function_call_return_method return_method
,
2681 CORE_ADDR struct_addr
, bool thiscall
)
2683 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2689 /* BND registers can be in arbitrary values at the moment of the
2690 inferior call. This can cause boundary violations that are not
2691 due to a real bug or even desired by the user. The best to be done
2692 is set the BND registers to allow access to the whole memory, INIT
2693 state, before pushing the inferior call. */
2694 i387_reset_bnd_regs (gdbarch
, regcache
);
2696 /* Determine the total space required for arguments and struct
2697 return address in a first pass (allowing for 16-byte-aligned
2698 arguments), then push arguments in a second pass. */
2700 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2702 int args_space_used
= 0;
2704 if (return_method
== return_method_struct
)
2708 /* Push value address. */
2709 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2710 write_memory (sp
, buf
, 4);
2711 args_space_used
+= 4;
2717 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2719 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2723 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2724 args_space_used
= align_up (args_space_used
, 16);
2726 write_memory (sp
+ args_space_used
,
2727 value_contents_all (args
[i
]), len
);
2728 /* The System V ABI says that:
2730 "An argument's size is increased, if necessary, to make it a
2731 multiple of [32-bit] words. This may require tail padding,
2732 depending on the size of the argument."
2734 This makes sure the stack stays word-aligned. */
2735 args_space_used
+= align_up (len
, 4);
2739 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2740 args_space
= align_up (args_space
, 16);
2741 args_space
+= align_up (len
, 4);
2749 /* The original System V ABI only requires word alignment,
2750 but modern incarnations need 16-byte alignment in order
2751 to support SSE. Since wasting a few bytes here isn't
2752 harmful we unconditionally enforce 16-byte alignment. */
2757 /* Store return address. */
2759 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2760 write_memory (sp
, buf
, 4);
2762 /* Finally, update the stack pointer... */
2763 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2764 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2766 /* ...and fake a frame pointer. */
2767 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2769 /* The 'this' pointer needs to be in ECX. */
2771 regcache
->cooked_write (I386_ECX_REGNUM
, value_contents_all (args
[0]));
2773 /* MarkK wrote: This "+ 8" is all over the place:
2774 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2775 i386_dummy_id). It's there, since all frame unwinders for
2776 a given target have to agree (within a certain margin) on the
2777 definition of the stack address of a frame. Otherwise frame id
2778 comparison might not work correctly. Since DWARF2/GCC uses the
2779 stack address *before* the function call as a frame's CFA. On
2780 the i386, when %ebp is used as a frame pointer, the offset
2781 between the contents %ebp and the CFA as defined by GCC. */
2785 /* Implement the "push_dummy_call" gdbarch method. */
2788 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2789 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2790 struct value
**args
, CORE_ADDR sp
,
2791 function_call_return_method return_method
,
2792 CORE_ADDR struct_addr
)
2794 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2795 nargs
, args
, sp
, return_method
,
2796 struct_addr
, false);
2799 /* These registers are used for returning integers (and on some
2800 targets also for returning `struct' and `union' values when their
2801 size and alignment match an integer type). */
2802 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2803 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2805 /* Read, for architecture GDBARCH, a function return value of TYPE
2806 from REGCACHE, and copy that into VALBUF. */
2809 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2810 struct regcache
*regcache
, gdb_byte
*valbuf
)
2812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2813 int len
= TYPE_LENGTH (type
);
2814 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2816 if (type
->code () == TYPE_CODE_FLT
)
2818 if (tdep
->st0_regnum
< 0)
2820 warning (_("Cannot find floating-point return value."));
2821 memset (valbuf
, 0, len
);
2825 /* Floating-point return values can be found in %st(0). Convert
2826 its contents to the desired type. This is probably not
2827 exactly how it would happen on the target itself, but it is
2828 the best we can do. */
2829 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2830 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2834 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2835 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2837 if (len
<= low_size
)
2839 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2840 memcpy (valbuf
, buf
, len
);
2842 else if (len
<= (low_size
+ high_size
))
2844 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2845 memcpy (valbuf
, buf
, low_size
);
2846 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2847 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2850 internal_error (__FILE__
, __LINE__
,
2851 _("Cannot extract return value of %d bytes long."),
2856 /* Write, for architecture GDBARCH, a function return value of TYPE
2857 from VALBUF into REGCACHE. */
2860 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2861 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2864 int len
= TYPE_LENGTH (type
);
2866 if (type
->code () == TYPE_CODE_FLT
)
2869 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2871 if (tdep
->st0_regnum
< 0)
2873 warning (_("Cannot set floating-point return value."));
2877 /* Returning floating-point values is a bit tricky. Apart from
2878 storing the return value in %st(0), we have to simulate the
2879 state of the FPU at function return point. */
2881 /* Convert the value found in VALBUF to the extended
2882 floating-point format used by the FPU. This is probably
2883 not exactly how it would happen on the target itself, but
2884 it is the best we can do. */
2885 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2886 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2888 /* Set the top of the floating-point register stack to 7. The
2889 actual value doesn't really matter, but 7 is what a normal
2890 function return would end up with if the program started out
2891 with a freshly initialized FPU. */
2892 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2894 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2896 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2897 the floating-point register stack to 7, the appropriate value
2898 for the tag word is 0x3fff. */
2899 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2903 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2904 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2906 if (len
<= low_size
)
2907 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2908 else if (len
<= (low_size
+ high_size
))
2910 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2911 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2915 internal_error (__FILE__
, __LINE__
,
2916 _("Cannot store return value of %d bytes long."), len
);
2921 /* This is the variable that is set with "set struct-convention", and
2922 its legitimate values. */
2923 static const char default_struct_convention
[] = "default";
2924 static const char pcc_struct_convention
[] = "pcc";
2925 static const char reg_struct_convention
[] = "reg";
2926 static const char *const valid_conventions
[] =
2928 default_struct_convention
,
2929 pcc_struct_convention
,
2930 reg_struct_convention
,
2933 static const char *struct_convention
= default_struct_convention
;
2935 /* Return non-zero if TYPE, which is assumed to be a structure,
2936 a union type, or an array type, should be returned in registers
2937 for architecture GDBARCH. */
2940 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2942 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2943 enum type_code code
= type
->code ();
2944 int len
= TYPE_LENGTH (type
);
2946 gdb_assert (code
== TYPE_CODE_STRUCT
2947 || code
== TYPE_CODE_UNION
2948 || code
== TYPE_CODE_ARRAY
);
2950 if (struct_convention
== pcc_struct_convention
2951 || (struct_convention
== default_struct_convention
2952 && tdep
->struct_return
== pcc_struct_return
))
2955 /* Structures consisting of a single `float', `double' or 'long
2956 double' member are returned in %st(0). */
2957 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
2959 type
= check_typedef (type
->field (0).type ());
2960 if (type
->code () == TYPE_CODE_FLT
)
2961 return (len
== 4 || len
== 8 || len
== 12);
2964 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2967 /* Determine, for architecture GDBARCH, how a return value of TYPE
2968 should be returned. If it is supposed to be returned in registers,
2969 and READBUF is non-zero, read the appropriate value from REGCACHE,
2970 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2971 from WRITEBUF into REGCACHE. */
2973 static enum return_value_convention
2974 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2975 struct type
*type
, struct regcache
*regcache
,
2976 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2978 enum type_code code
= type
->code ();
2980 if (((code
== TYPE_CODE_STRUCT
2981 || code
== TYPE_CODE_UNION
2982 || code
== TYPE_CODE_ARRAY
)
2983 && !i386_reg_struct_return_p (gdbarch
, type
))
2984 /* Complex double and long double uses the struct return convention. */
2985 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2986 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2987 /* 128-bit decimal float uses the struct return convention. */
2988 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2990 /* The System V ABI says that:
2992 "A function that returns a structure or union also sets %eax
2993 to the value of the original address of the caller's area
2994 before it returns. Thus when the caller receives control
2995 again, the address of the returned object resides in register
2996 %eax and can be used to access the object."
2998 So the ABI guarantees that we can always find the return
2999 value just after the function has returned. */
3001 /* Note that the ABI doesn't mention functions returning arrays,
3002 which is something possible in certain languages such as Ada.
3003 In this case, the value is returned as if it was wrapped in
3004 a record, so the convention applied to records also applies
3011 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3012 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
3015 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3018 /* This special case is for structures consisting of a single
3019 `float', `double' or 'long double' member. These structures are
3020 returned in %st(0). For these structures, we call ourselves
3021 recursively, changing TYPE into the type of the first member of
3022 the structure. Since that should work for all structures that
3023 have only one member, we don't bother to check the member's type
3025 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3027 type
= check_typedef (type
->field (0).type ());
3028 return i386_return_value (gdbarch
, function
, type
, regcache
,
3033 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3035 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3037 return RETURN_VALUE_REGISTER_CONVENTION
;
3042 i387_ext_type (struct gdbarch
*gdbarch
)
3044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3046 if (!tdep
->i387_ext_type
)
3048 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3049 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3052 return tdep
->i387_ext_type
;
3055 /* Construct type for pseudo BND registers. We can't use
3056 tdesc_find_type since a complement of one value has to be used
3057 to describe the upper bound. */
3059 static struct type
*
3060 i386_bnd_type (struct gdbarch
*gdbarch
)
3062 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3065 if (!tdep
->i386_bnd_type
)
3068 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3070 /* The type we're building is described bellow: */
3075 void *ubound
; /* One complement of raw ubound field. */
3079 t
= arch_composite_type (gdbarch
,
3080 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3082 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3083 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3085 t
->set_name ("builtin_type_bound128");
3086 tdep
->i386_bnd_type
= t
;
3089 return tdep
->i386_bnd_type
;
3092 /* Construct vector type for pseudo ZMM registers. We can't use
3093 tdesc_find_type since ZMM isn't described in target description. */
3095 static struct type
*
3096 i386_zmm_type (struct gdbarch
*gdbarch
)
3098 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3100 if (!tdep
->i386_zmm_type
)
3102 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3104 /* The type we're building is this: */
3106 union __gdb_builtin_type_vec512i
3108 int128_t v4_int128
[4];
3109 int64_t v8_int64
[8];
3110 int32_t v16_int32
[16];
3111 int16_t v32_int16
[32];
3112 int8_t v64_int8
[64];
3113 double v8_double
[8];
3114 float v16_float
[16];
3120 t
= arch_composite_type (gdbarch
,
3121 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3122 append_composite_type_field (t
, "v16_float",
3123 init_vector_type (bt
->builtin_float
, 16));
3124 append_composite_type_field (t
, "v8_double",
3125 init_vector_type (bt
->builtin_double
, 8));
3126 append_composite_type_field (t
, "v64_int8",
3127 init_vector_type (bt
->builtin_int8
, 64));
3128 append_composite_type_field (t
, "v32_int16",
3129 init_vector_type (bt
->builtin_int16
, 32));
3130 append_composite_type_field (t
, "v16_int32",
3131 init_vector_type (bt
->builtin_int32
, 16));
3132 append_composite_type_field (t
, "v8_int64",
3133 init_vector_type (bt
->builtin_int64
, 8));
3134 append_composite_type_field (t
, "v4_int128",
3135 init_vector_type (bt
->builtin_int128
, 4));
3137 TYPE_VECTOR (t
) = 1;
3138 t
->set_name ("builtin_type_vec512i");
3139 tdep
->i386_zmm_type
= t
;
3142 return tdep
->i386_zmm_type
;
3145 /* Construct vector type for pseudo YMM registers. We can't use
3146 tdesc_find_type since YMM isn't described in target description. */
3148 static struct type
*
3149 i386_ymm_type (struct gdbarch
*gdbarch
)
3151 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3153 if (!tdep
->i386_ymm_type
)
3155 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3157 /* The type we're building is this: */
3159 union __gdb_builtin_type_vec256i
3161 int128_t v2_int128
[2];
3162 int64_t v4_int64
[4];
3163 int32_t v8_int32
[8];
3164 int16_t v16_int16
[16];
3165 int8_t v32_int8
[32];
3166 double v4_double
[4];
3173 t
= arch_composite_type (gdbarch
,
3174 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3175 append_composite_type_field (t
, "v8_float",
3176 init_vector_type (bt
->builtin_float
, 8));
3177 append_composite_type_field (t
, "v4_double",
3178 init_vector_type (bt
->builtin_double
, 4));
3179 append_composite_type_field (t
, "v32_int8",
3180 init_vector_type (bt
->builtin_int8
, 32));
3181 append_composite_type_field (t
, "v16_int16",
3182 init_vector_type (bt
->builtin_int16
, 16));
3183 append_composite_type_field (t
, "v8_int32",
3184 init_vector_type (bt
->builtin_int32
, 8));
3185 append_composite_type_field (t
, "v4_int64",
3186 init_vector_type (bt
->builtin_int64
, 4));
3187 append_composite_type_field (t
, "v2_int128",
3188 init_vector_type (bt
->builtin_int128
, 2));
3190 TYPE_VECTOR (t
) = 1;
3191 t
->set_name ("builtin_type_vec256i");
3192 tdep
->i386_ymm_type
= t
;
3195 return tdep
->i386_ymm_type
;
3198 /* Construct vector type for MMX registers. */
3199 static struct type
*
3200 i386_mmx_type (struct gdbarch
*gdbarch
)
3202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3204 if (!tdep
->i386_mmx_type
)
3206 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3208 /* The type we're building is this: */
3210 union __gdb_builtin_type_vec64i
3213 int32_t v2_int32
[2];
3214 int16_t v4_int16
[4];
3221 t
= arch_composite_type (gdbarch
,
3222 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3224 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3225 append_composite_type_field (t
, "v2_int32",
3226 init_vector_type (bt
->builtin_int32
, 2));
3227 append_composite_type_field (t
, "v4_int16",
3228 init_vector_type (bt
->builtin_int16
, 4));
3229 append_composite_type_field (t
, "v8_int8",
3230 init_vector_type (bt
->builtin_int8
, 8));
3232 TYPE_VECTOR (t
) = 1;
3233 t
->set_name ("builtin_type_vec64i");
3234 tdep
->i386_mmx_type
= t
;
3237 return tdep
->i386_mmx_type
;
3240 /* Return the GDB type object for the "standard" data type of data in
3244 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3246 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3247 return i386_bnd_type (gdbarch
);
3248 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3249 return i386_mmx_type (gdbarch
);
3250 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3251 return i386_ymm_type (gdbarch
);
3252 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3253 return i386_ymm_type (gdbarch
);
3254 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3255 return i386_zmm_type (gdbarch
);
3258 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3259 if (i386_byte_regnum_p (gdbarch
, regnum
))
3260 return bt
->builtin_int8
;
3261 else if (i386_word_regnum_p (gdbarch
, regnum
))
3262 return bt
->builtin_int16
;
3263 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3264 return bt
->builtin_int32
;
3265 else if (i386_k_regnum_p (gdbarch
, regnum
))
3266 return bt
->builtin_int64
;
3269 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3272 /* Map a cooked register onto a raw register or memory. For the i386,
3273 the MMX registers need to be mapped onto floating point registers. */
3276 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
3283 mmxreg
= regnum
- tdep
->mm0_regnum
;
3284 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3285 tos
= (fstat
>> 11) & 0x7;
3286 fpreg
= (mmxreg
+ tos
) % 8;
3288 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3291 /* A helper function for us by i386_pseudo_register_read_value and
3292 amd64_pseudo_register_read_value. It does all the work but reads
3293 the data into an already-allocated value. */
3296 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3297 readable_regcache
*regcache
,
3299 struct value
*result_value
)
3301 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3302 enum register_status status
;
3303 gdb_byte
*buf
= value_contents_raw (result_value
);
3305 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3307 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3309 /* Extract (always little endian). */
3310 status
= regcache
->raw_read (fpnum
, raw_buf
);
3311 if (status
!= REG_VALID
)
3312 mark_value_bytes_unavailable (result_value
, 0,
3313 TYPE_LENGTH (value_type (result_value
)));
3315 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3320 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3322 regnum
-= tdep
->bnd0_regnum
;
3324 /* Extract (always little endian). Read lower 128bits. */
3325 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3327 if (status
!= REG_VALID
)
3328 mark_value_bytes_unavailable (result_value
, 0, 16);
3331 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3332 LONGEST upper
, lower
;
3333 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3335 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3336 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3339 memcpy (buf
, &lower
, size
);
3340 memcpy (buf
+ size
, &upper
, size
);
3343 else if (i386_k_regnum_p (gdbarch
, regnum
))
3345 regnum
-= tdep
->k0_regnum
;
3347 /* Extract (always little endian). */
3348 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3349 if (status
!= REG_VALID
)
3350 mark_value_bytes_unavailable (result_value
, 0, 8);
3352 memcpy (buf
, raw_buf
, 8);
3354 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3356 regnum
-= tdep
->zmm0_regnum
;
3358 if (regnum
< num_lower_zmm_regs
)
3360 /* Extract (always little endian). Read lower 128bits. */
3361 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3363 if (status
!= REG_VALID
)
3364 mark_value_bytes_unavailable (result_value
, 0, 16);
3366 memcpy (buf
, raw_buf
, 16);
3368 /* Extract (always little endian). Read upper 128bits. */
3369 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3371 if (status
!= REG_VALID
)
3372 mark_value_bytes_unavailable (result_value
, 16, 16);
3374 memcpy (buf
+ 16, raw_buf
, 16);
3378 /* Extract (always little endian). Read lower 128bits. */
3379 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3380 - num_lower_zmm_regs
,
3382 if (status
!= REG_VALID
)
3383 mark_value_bytes_unavailable (result_value
, 0, 16);
3385 memcpy (buf
, raw_buf
, 16);
3387 /* Extract (always little endian). Read upper 128bits. */
3388 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3389 - num_lower_zmm_regs
,
3391 if (status
!= REG_VALID
)
3392 mark_value_bytes_unavailable (result_value
, 16, 16);
3394 memcpy (buf
+ 16, raw_buf
, 16);
3397 /* Read upper 256bits. */
3398 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3400 if (status
!= REG_VALID
)
3401 mark_value_bytes_unavailable (result_value
, 32, 32);
3403 memcpy (buf
+ 32, raw_buf
, 32);
3405 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3407 regnum
-= tdep
->ymm0_regnum
;
3409 /* Extract (always little endian). Read lower 128bits. */
3410 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3412 if (status
!= REG_VALID
)
3413 mark_value_bytes_unavailable (result_value
, 0, 16);
3415 memcpy (buf
, raw_buf
, 16);
3416 /* Read upper 128bits. */
3417 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3419 if (status
!= REG_VALID
)
3420 mark_value_bytes_unavailable (result_value
, 16, 32);
3422 memcpy (buf
+ 16, raw_buf
, 16);
3424 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3426 regnum
-= tdep
->ymm16_regnum
;
3427 /* Extract (always little endian). Read lower 128bits. */
3428 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3430 if (status
!= REG_VALID
)
3431 mark_value_bytes_unavailable (result_value
, 0, 16);
3433 memcpy (buf
, raw_buf
, 16);
3434 /* Read upper 128bits. */
3435 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3437 if (status
!= REG_VALID
)
3438 mark_value_bytes_unavailable (result_value
, 16, 16);
3440 memcpy (buf
+ 16, raw_buf
, 16);
3442 else if (i386_word_regnum_p (gdbarch
, regnum
))
3444 int gpnum
= regnum
- tdep
->ax_regnum
;
3446 /* Extract (always little endian). */
3447 status
= regcache
->raw_read (gpnum
, raw_buf
);
3448 if (status
!= REG_VALID
)
3449 mark_value_bytes_unavailable (result_value
, 0,
3450 TYPE_LENGTH (value_type (result_value
)));
3452 memcpy (buf
, raw_buf
, 2);
3454 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3456 int gpnum
= regnum
- tdep
->al_regnum
;
3458 /* Extract (always little endian). We read both lower and
3460 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3461 if (status
!= REG_VALID
)
3462 mark_value_bytes_unavailable (result_value
, 0,
3463 TYPE_LENGTH (value_type (result_value
)));
3464 else if (gpnum
>= 4)
3465 memcpy (buf
, raw_buf
+ 1, 1);
3467 memcpy (buf
, raw_buf
, 1);
3470 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3474 static struct value
*
3475 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3476 readable_regcache
*regcache
,
3479 struct value
*result
;
3481 result
= allocate_value (register_type (gdbarch
, regnum
));
3482 VALUE_LVAL (result
) = lval_register
;
3483 VALUE_REGNUM (result
) = regnum
;
3485 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3491 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3492 int regnum
, const gdb_byte
*buf
)
3494 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3496 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3498 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3501 regcache
->raw_read (fpnum
, raw_buf
);
3502 /* ... Modify ... (always little endian). */
3503 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3505 regcache
->raw_write (fpnum
, raw_buf
);
3509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3511 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3513 ULONGEST upper
, lower
;
3514 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3515 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3517 /* New values from input value. */
3518 regnum
-= tdep
->bnd0_regnum
;
3519 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3520 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3522 /* Fetching register buffer. */
3523 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3528 /* Set register bits. */
3529 memcpy (raw_buf
, &lower
, 8);
3530 memcpy (raw_buf
+ 8, &upper
, 8);
3532 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3534 else if (i386_k_regnum_p (gdbarch
, regnum
))
3536 regnum
-= tdep
->k0_regnum
;
3538 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3540 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3542 regnum
-= tdep
->zmm0_regnum
;
3544 if (regnum
< num_lower_zmm_regs
)
3546 /* Write lower 128bits. */
3547 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3548 /* Write upper 128bits. */
3549 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3553 /* Write lower 128bits. */
3554 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3555 - num_lower_zmm_regs
, buf
);
3556 /* Write upper 128bits. */
3557 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3558 - num_lower_zmm_regs
, buf
+ 16);
3560 /* Write upper 256bits. */
3561 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3563 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3565 regnum
-= tdep
->ymm0_regnum
;
3567 /* ... Write lower 128bits. */
3568 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3569 /* ... Write upper 128bits. */
3570 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3572 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3574 regnum
-= tdep
->ymm16_regnum
;
3576 /* ... Write lower 128bits. */
3577 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3578 /* ... Write upper 128bits. */
3579 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3581 else if (i386_word_regnum_p (gdbarch
, regnum
))
3583 int gpnum
= regnum
- tdep
->ax_regnum
;
3586 regcache
->raw_read (gpnum
, raw_buf
);
3587 /* ... Modify ... (always little endian). */
3588 memcpy (raw_buf
, buf
, 2);
3590 regcache
->raw_write (gpnum
, raw_buf
);
3592 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3594 int gpnum
= regnum
- tdep
->al_regnum
;
3596 /* Read ... We read both lower and upper registers. */
3597 regcache
->raw_read (gpnum
% 4, raw_buf
);
3598 /* ... Modify ... (always little endian). */
3600 memcpy (raw_buf
+ 1, buf
, 1);
3602 memcpy (raw_buf
, buf
, 1);
3604 regcache
->raw_write (gpnum
% 4, raw_buf
);
3607 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3611 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3614 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3615 struct agent_expr
*ax
, int regnum
)
3617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3619 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3621 /* MMX to FPU register mapping depends on current TOS. Let's just
3622 not care and collect everything... */
3625 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3626 for (i
= 0; i
< 8; i
++)
3627 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3630 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3632 regnum
-= tdep
->bnd0_regnum
;
3633 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3636 else if (i386_k_regnum_p (gdbarch
, regnum
))
3638 regnum
-= tdep
->k0_regnum
;
3639 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3642 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3644 regnum
-= tdep
->zmm0_regnum
;
3645 if (regnum
< num_lower_zmm_regs
)
3647 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3648 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3652 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3653 - num_lower_zmm_regs
);
3654 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3655 - num_lower_zmm_regs
);
3657 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3660 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3662 regnum
-= tdep
->ymm0_regnum
;
3663 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3664 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3667 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3669 regnum
-= tdep
->ymm16_regnum
;
3670 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3671 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3674 else if (i386_word_regnum_p (gdbarch
, regnum
))
3676 int gpnum
= regnum
- tdep
->ax_regnum
;
3678 ax_reg_mask (ax
, gpnum
);
3681 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3683 int gpnum
= regnum
- tdep
->al_regnum
;
3685 ax_reg_mask (ax
, gpnum
% 4);
3689 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3694 /* Return the register number of the register allocated by GCC after
3695 REGNUM, or -1 if there is no such register. */
3698 i386_next_regnum (int regnum
)
3700 /* GCC allocates the registers in the order:
3702 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3704 Since storing a variable in %esp doesn't make any sense we return
3705 -1 for %ebp and for %esp itself. */
3706 static int next_regnum
[] =
3708 I386_EDX_REGNUM
, /* Slot for %eax. */
3709 I386_EBX_REGNUM
, /* Slot for %ecx. */
3710 I386_ECX_REGNUM
, /* Slot for %edx. */
3711 I386_ESI_REGNUM
, /* Slot for %ebx. */
3712 -1, -1, /* Slots for %esp and %ebp. */
3713 I386_EDI_REGNUM
, /* Slot for %esi. */
3714 I386_EBP_REGNUM
/* Slot for %edi. */
3717 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3718 return next_regnum
[regnum
];
3723 /* Return nonzero if a value of type TYPE stored in register REGNUM
3724 needs any special handling. */
3727 i386_convert_register_p (struct gdbarch
*gdbarch
,
3728 int regnum
, struct type
*type
)
3730 int len
= TYPE_LENGTH (type
);
3732 /* Values may be spread across multiple registers. Most debugging
3733 formats aren't expressive enough to specify the locations, so
3734 some heuristics is involved. Right now we only handle types that
3735 have a length that is a multiple of the word size, since GCC
3736 doesn't seem to put any other types into registers. */
3737 if (len
> 4 && len
% 4 == 0)
3739 int last_regnum
= regnum
;
3743 last_regnum
= i386_next_regnum (last_regnum
);
3747 if (last_regnum
!= -1)
3751 return i387_convert_register_p (gdbarch
, regnum
, type
);
3754 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3755 return its contents in TO. */
3758 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3759 struct type
*type
, gdb_byte
*to
,
3760 int *optimizedp
, int *unavailablep
)
3762 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3763 int len
= TYPE_LENGTH (type
);
3765 if (i386_fp_regnum_p (gdbarch
, regnum
))
3766 return i387_register_to_value (frame
, regnum
, type
, to
,
3767 optimizedp
, unavailablep
);
3769 /* Read a value spread across multiple registers. */
3771 gdb_assert (len
> 4 && len
% 4 == 0);
3775 gdb_assert (regnum
!= -1);
3776 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3778 if (!get_frame_register_bytes (frame
, regnum
, 0,
3779 register_size (gdbarch
, regnum
),
3780 to
, optimizedp
, unavailablep
))
3783 regnum
= i386_next_regnum (regnum
);
3788 *optimizedp
= *unavailablep
= 0;
3792 /* Write the contents FROM of a value of type TYPE into register
3793 REGNUM in frame FRAME. */
3796 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3797 struct type
*type
, const gdb_byte
*from
)
3799 int len
= TYPE_LENGTH (type
);
3801 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3803 i387_value_to_register (frame
, regnum
, type
, from
);
3807 /* Write a value spread across multiple registers. */
3809 gdb_assert (len
> 4 && len
% 4 == 0);
3813 gdb_assert (regnum
!= -1);
3814 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3816 put_frame_register (frame
, regnum
, from
);
3817 regnum
= i386_next_regnum (regnum
);
3823 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3824 in the general-purpose register set REGSET to register cache
3825 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3828 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3829 int regnum
, const void *gregs
, size_t len
)
3831 struct gdbarch
*gdbarch
= regcache
->arch ();
3832 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3833 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3836 gdb_assert (len
>= tdep
->sizeof_gregset
);
3838 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3840 if ((regnum
== i
|| regnum
== -1)
3841 && tdep
->gregset_reg_offset
[i
] != -1)
3842 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3846 /* Collect register REGNUM from the register cache REGCACHE and store
3847 it in the buffer specified by GREGS and LEN as described by the
3848 general-purpose register set REGSET. If REGNUM is -1, do this for
3849 all registers in REGSET. */
3852 i386_collect_gregset (const struct regset
*regset
,
3853 const struct regcache
*regcache
,
3854 int regnum
, void *gregs
, size_t len
)
3856 struct gdbarch
*gdbarch
= regcache
->arch ();
3857 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3861 gdb_assert (len
>= tdep
->sizeof_gregset
);
3863 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3865 if ((regnum
== i
|| regnum
== -1)
3866 && tdep
->gregset_reg_offset
[i
] != -1)
3867 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3871 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3872 in the floating-point register set REGSET to register cache
3873 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3876 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3877 int regnum
, const void *fpregs
, size_t len
)
3879 struct gdbarch
*gdbarch
= regcache
->arch ();
3880 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3882 if (len
== I387_SIZEOF_FXSAVE
)
3884 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3888 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3889 i387_supply_fsave (regcache
, regnum
, fpregs
);
3892 /* Collect register REGNUM from the register cache REGCACHE and store
3893 it in the buffer specified by FPREGS and LEN as described by the
3894 floating-point register set REGSET. If REGNUM is -1, do this for
3895 all registers in REGSET. */
3898 i386_collect_fpregset (const struct regset
*regset
,
3899 const struct regcache
*regcache
,
3900 int regnum
, void *fpregs
, size_t len
)
3902 struct gdbarch
*gdbarch
= regcache
->arch ();
3903 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3905 if (len
== I387_SIZEOF_FXSAVE
)
3907 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3911 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3912 i387_collect_fsave (regcache
, regnum
, fpregs
);
3915 /* Register set definitions. */
3917 const struct regset i386_gregset
=
3919 NULL
, i386_supply_gregset
, i386_collect_gregset
3922 const struct regset i386_fpregset
=
3924 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3927 /* Default iterator over core file register note sections. */
3930 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3931 iterate_over_regset_sections_cb
*cb
,
3933 const struct regcache
*regcache
)
3935 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3937 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3939 if (tdep
->sizeof_fpregset
)
3940 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3945 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3948 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3949 CORE_ADDR pc
, char *name
)
3951 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3952 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3955 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3957 unsigned long indirect
=
3958 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3959 struct minimal_symbol
*indsym
=
3960 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3961 const char *symname
= indsym
? indsym
->linkage_name () : 0;
3965 if (startswith (symname
, "__imp_")
3966 || startswith (symname
, "_imp_"))
3968 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3971 return 0; /* Not a trampoline. */
3975 /* Return whether the THIS_FRAME corresponds to a sigtramp
3979 i386_sigtramp_p (struct frame_info
*this_frame
)
3981 CORE_ADDR pc
= get_frame_pc (this_frame
);
3984 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3985 return (name
&& strcmp ("_sigtramp", name
) == 0);
3989 /* We have two flavours of disassembly. The machinery on this page
3990 deals with switching between those. */
3993 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3995 gdb_assert (disassembly_flavor
== att_flavor
3996 || disassembly_flavor
== intel_flavor
);
3998 info
->disassembler_options
= disassembly_flavor
;
4000 return default_print_insn (pc
, info
);
4004 /* There are a few i386 architecture variants that differ only
4005 slightly from the generic i386 target. For now, we don't give them
4006 their own source file, but include them here. As a consequence,
4007 they'll always be included. */
4009 /* System V Release 4 (SVR4). */
4011 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4015 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4017 CORE_ADDR pc
= get_frame_pc (this_frame
);
4020 /* The origin of these symbols is currently unknown. */
4021 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4022 return (name
&& (strcmp ("_sigreturn", name
) == 0
4023 || strcmp ("sigvechandler", name
) == 0));
4026 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4027 address of the associated sigcontext (ucontext) structure. */
4030 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4032 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4033 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4037 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4038 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4040 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4045 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4049 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4051 return (*s
== '$' /* Literal number. */
4052 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4053 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4054 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4057 /* Helper function for i386_stap_parse_special_token.
4059 This function parses operands of the form `-8+3+1(%rbp)', which
4060 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4062 Return true if the operand was parsed successfully, false
4066 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4067 struct stap_parse_info
*p
)
4069 const char *s
= p
->arg
;
4071 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4075 long displacements
[3];
4082 got_minus
[0] = false;
4088 got_minus
[0] = true;
4091 if (!isdigit ((unsigned char) *s
))
4094 displacements
[0] = strtol (s
, &endp
, 10);
4097 if (*s
!= '+' && *s
!= '-')
4099 /* We are not dealing with a triplet. */
4103 got_minus
[1] = false;
4109 got_minus
[1] = true;
4112 if (!isdigit ((unsigned char) *s
))
4115 displacements
[1] = strtol (s
, &endp
, 10);
4118 if (*s
!= '+' && *s
!= '-')
4120 /* We are not dealing with a triplet. */
4124 got_minus
[2] = false;
4130 got_minus
[2] = true;
4133 if (!isdigit ((unsigned char) *s
))
4136 displacements
[2] = strtol (s
, &endp
, 10);
4139 if (*s
!= '(' || s
[1] != '%')
4145 while (isalnum (*s
))
4151 len
= s
- start
- 1;
4152 regname
= (char *) alloca (len
+ 1);
4154 strncpy (regname
, start
, len
);
4155 regname
[len
] = '\0';
4157 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4158 error (_("Invalid register name `%s' on expression `%s'."),
4159 regname
, p
->saved_arg
);
4161 for (i
= 0; i
< 3; i
++)
4163 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4165 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4166 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4167 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4169 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4172 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4175 write_exp_string (&p
->pstate
, str
);
4176 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4178 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4179 write_exp_elt_type (&p
->pstate
,
4180 builtin_type (gdbarch
)->builtin_data_ptr
);
4181 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4183 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4184 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4185 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4187 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4188 write_exp_elt_type (&p
->pstate
,
4189 lookup_pointer_type (p
->arg_type
));
4190 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4192 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4202 /* Helper function for i386_stap_parse_special_token.
4204 This function parses operands of the form `register base +
4205 (register index * size) + offset', as represented in
4206 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4208 Return true if the operand was parsed successfully, false
4212 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4213 struct stap_parse_info
*p
)
4215 const char *s
= p
->arg
;
4217 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4219 bool offset_minus
= false;
4221 bool size_minus
= false;
4228 struct stoken base_token
, index_token
;
4235 offset_minus
= true;
4238 if (offset_minus
&& !isdigit (*s
))
4245 offset
= strtol (s
, &endp
, 10);
4249 if (*s
!= '(' || s
[1] != '%')
4255 while (isalnum (*s
))
4258 if (*s
!= ',' || s
[1] != '%')
4261 len_base
= s
- start
;
4262 base
= (char *) alloca (len_base
+ 1);
4263 strncpy (base
, start
, len_base
);
4264 base
[len_base
] = '\0';
4266 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4267 error (_("Invalid register name `%s' on expression `%s'."),
4268 base
, p
->saved_arg
);
4273 while (isalnum (*s
))
4276 len_index
= s
- start
;
4277 index
= (char *) alloca (len_index
+ 1);
4278 strncpy (index
, start
, len_index
);
4279 index
[len_index
] = '\0';
4281 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4282 error (_("Invalid register name `%s' on expression `%s'."),
4283 index
, p
->saved_arg
);
4285 if (*s
!= ',' && *s
!= ')')
4301 size
= strtol (s
, &endp
, 10);
4312 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4313 write_exp_elt_type (&p
->pstate
,
4314 builtin_type (gdbarch
)->builtin_long
);
4315 write_exp_elt_longcst (&p
->pstate
, offset
);
4316 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4318 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4321 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4322 base_token
.ptr
= base
;
4323 base_token
.length
= len_base
;
4324 write_exp_string (&p
->pstate
, base_token
);
4325 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4328 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4330 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4331 index_token
.ptr
= index
;
4332 index_token
.length
= len_index
;
4333 write_exp_string (&p
->pstate
, index_token
);
4334 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4338 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4339 write_exp_elt_type (&p
->pstate
,
4340 builtin_type (gdbarch
)->builtin_long
);
4341 write_exp_elt_longcst (&p
->pstate
, size
);
4342 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4344 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4345 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4348 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4350 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4351 write_exp_elt_type (&p
->pstate
,
4352 lookup_pointer_type (p
->arg_type
));
4353 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4355 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4365 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4369 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4370 struct stap_parse_info
*p
)
4372 /* In order to parse special tokens, we use a state-machine that go
4373 through every known token and try to get a match. */
4377 THREE_ARG_DISPLACEMENT
,
4382 current_state
= TRIPLET
;
4384 /* The special tokens to be parsed here are:
4386 - `register base + (register index * size) + offset', as represented
4387 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4389 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4390 `*(-8 + 3 - 1 + (void *) $eax)'. */
4392 while (current_state
!= DONE
)
4394 switch (current_state
)
4397 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4401 case THREE_ARG_DISPLACEMENT
:
4402 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4407 /* Advancing to the next state. */
4414 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4418 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4419 const std::string
®name
, int regnum
)
4421 static const std::unordered_set
<std::string
> reg_assoc
4422 = { "ax", "bx", "cx", "dx",
4423 "si", "di", "bp", "sp" };
4425 /* If we are dealing with a register whose size is less than the size
4426 specified by the "[-]N@" prefix, and it is one of the registers that
4427 we know has an extended variant available, then use the extended
4428 version of the register instead. */
4429 if (register_size (gdbarch
, regnum
) < TYPE_LENGTH (p
->arg_type
)
4430 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4431 return "e" + regname
;
4433 /* Otherwise, just use the requested register. */
4439 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4440 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4443 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4445 return "(x86_64|i.86)";
4450 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4453 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4455 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4456 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4462 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4464 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4465 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4466 static const char *const stap_register_indirection_prefixes
[] = { "(",
4468 static const char *const stap_register_indirection_suffixes
[] = { ")",
4471 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4472 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4474 /* Registering SystemTap handlers. */
4475 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4476 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4477 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4478 stap_register_indirection_prefixes
);
4479 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4480 stap_register_indirection_suffixes
);
4481 set_gdbarch_stap_is_single_operand (gdbarch
,
4482 i386_stap_is_single_operand
);
4483 set_gdbarch_stap_parse_special_token (gdbarch
,
4484 i386_stap_parse_special_token
);
4485 set_gdbarch_stap_adjust_register (gdbarch
,
4486 i386_stap_adjust_register
);
4488 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4489 i386_in_indirect_branch_thunk
);
4492 /* System V Release 4 (SVR4). */
4495 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4497 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4499 /* System V Release 4 uses ELF. */
4500 i386_elf_init_abi (info
, gdbarch
);
4502 /* System V Release 4 has shared libraries. */
4503 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4505 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4506 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4507 tdep
->sc_pc_offset
= 36 + 14 * 4;
4508 tdep
->sc_sp_offset
= 36 + 17 * 4;
4510 tdep
->jb_pc_offset
= 20;
4515 /* i386 register groups. In addition to the normal groups, add "mmx"
4518 static struct reggroup
*i386_sse_reggroup
;
4519 static struct reggroup
*i386_mmx_reggroup
;
4522 i386_init_reggroups (void)
4524 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4525 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4529 i386_add_reggroups (struct gdbarch
*gdbarch
)
4531 reggroup_add (gdbarch
, i386_sse_reggroup
);
4532 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4533 reggroup_add (gdbarch
, general_reggroup
);
4534 reggroup_add (gdbarch
, float_reggroup
);
4535 reggroup_add (gdbarch
, all_reggroup
);
4536 reggroup_add (gdbarch
, save_reggroup
);
4537 reggroup_add (gdbarch
, restore_reggroup
);
4538 reggroup_add (gdbarch
, vector_reggroup
);
4539 reggroup_add (gdbarch
, system_reggroup
);
4543 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4544 struct reggroup
*group
)
4546 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4547 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4548 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4549 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4550 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4551 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4553 /* Don't include pseudo registers, except for MMX, in any register
4555 if (i386_byte_regnum_p (gdbarch
, regnum
))
4558 if (i386_word_regnum_p (gdbarch
, regnum
))
4561 if (i386_dword_regnum_p (gdbarch
, regnum
))
4564 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4565 if (group
== i386_mmx_reggroup
)
4566 return mmx_regnum_p
;
4568 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4569 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4570 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4571 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4572 if (group
== i386_sse_reggroup
)
4573 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4575 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4576 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4577 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4579 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4580 == X86_XSTATE_AVX_AVX512_MASK
);
4581 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4582 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4583 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4584 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4586 if (group
== vector_reggroup
)
4587 return (mmx_regnum_p
4588 || (zmm_regnum_p
&& avx512_p
)
4589 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4590 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4593 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4594 || i386_fpc_regnum_p (gdbarch
, regnum
));
4595 if (group
== float_reggroup
)
4598 /* For "info reg all", don't include upper YMM registers nor XMM
4599 registers when AVX is supported. */
4600 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4601 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4602 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4603 if (group
== all_reggroup
4604 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4605 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4607 || ymmh_avx512_regnum_p
4611 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4612 if (group
== all_reggroup
4613 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4614 return bnd_regnum_p
;
4616 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4617 if (group
== all_reggroup
4618 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4621 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4622 if (group
== all_reggroup
4623 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4624 return mpx_ctrl_regnum_p
;
4626 if (group
== general_reggroup
)
4627 return (!fp_regnum_p
4631 && !xmm_avx512_regnum_p
4634 && !ymm_avx512_regnum_p
4635 && !ymmh_avx512_regnum_p
4638 && !mpx_ctrl_regnum_p
4643 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4647 /* Get the ARGIth function argument for the current function. */
4650 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4653 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4654 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4655 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4656 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4659 #define PREFIX_REPZ 0x01
4660 #define PREFIX_REPNZ 0x02
4661 #define PREFIX_LOCK 0x04
4662 #define PREFIX_DATA 0x08
4663 #define PREFIX_ADDR 0x10
4675 /* i386 arith/logic operations */
4688 struct i386_record_s
4690 struct gdbarch
*gdbarch
;
4691 struct regcache
*regcache
;
4692 CORE_ADDR orig_addr
;
4698 uint8_t mod
, reg
, rm
;
4707 /* Parse the "modrm" part of the memory address irp->addr points at.
4708 Returns -1 if something goes wrong, 0 otherwise. */
4711 i386_record_modrm (struct i386_record_s
*irp
)
4713 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4715 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4719 irp
->mod
= (irp
->modrm
>> 6) & 3;
4720 irp
->reg
= (irp
->modrm
>> 3) & 7;
4721 irp
->rm
= irp
->modrm
& 7;
4726 /* Extract the memory address that the current instruction writes to,
4727 and return it in *ADDR. Return -1 if something goes wrong. */
4730 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4732 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4733 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4738 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4745 uint8_t base
= irp
->rm
;
4750 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4753 scale
= (byte
>> 6) & 3;
4754 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4762 if ((base
& 7) == 5)
4765 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4768 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4769 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4770 *addr
+= irp
->addr
+ irp
->rip_offset
;
4774 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4777 *addr
= (int8_t) buf
[0];
4780 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4782 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4790 if (base
== 4 && irp
->popl_esp_hack
)
4791 *addr
+= irp
->popl_esp_hack
;
4792 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4795 if (irp
->aflag
== 2)
4800 *addr
= (uint32_t) (offset64
+ *addr
);
4802 if (havesib
&& (index
!= 4 || scale
!= 0))
4804 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4806 if (irp
->aflag
== 2)
4807 *addr
+= offset64
<< scale
;
4809 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4814 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4815 address from 32-bit to 64-bit. */
4816 *addr
= (uint32_t) *addr
;
4827 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4830 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4836 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4839 *addr
= (int8_t) buf
[0];
4842 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4845 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4852 regcache_raw_read_unsigned (irp
->regcache
,
4853 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4855 *addr
= (uint32_t) (*addr
+ offset64
);
4856 regcache_raw_read_unsigned (irp
->regcache
,
4857 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4859 *addr
= (uint32_t) (*addr
+ offset64
);
4862 regcache_raw_read_unsigned (irp
->regcache
,
4863 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4865 *addr
= (uint32_t) (*addr
+ offset64
);
4866 regcache_raw_read_unsigned (irp
->regcache
,
4867 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4869 *addr
= (uint32_t) (*addr
+ offset64
);
4872 regcache_raw_read_unsigned (irp
->regcache
,
4873 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4875 *addr
= (uint32_t) (*addr
+ offset64
);
4876 regcache_raw_read_unsigned (irp
->regcache
,
4877 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4879 *addr
= (uint32_t) (*addr
+ offset64
);
4882 regcache_raw_read_unsigned (irp
->regcache
,
4883 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4885 *addr
= (uint32_t) (*addr
+ offset64
);
4886 regcache_raw_read_unsigned (irp
->regcache
,
4887 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4889 *addr
= (uint32_t) (*addr
+ offset64
);
4892 regcache_raw_read_unsigned (irp
->regcache
,
4893 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4895 *addr
= (uint32_t) (*addr
+ offset64
);
4898 regcache_raw_read_unsigned (irp
->regcache
,
4899 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4901 *addr
= (uint32_t) (*addr
+ offset64
);
4904 regcache_raw_read_unsigned (irp
->regcache
,
4905 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4907 *addr
= (uint32_t) (*addr
+ offset64
);
4910 regcache_raw_read_unsigned (irp
->regcache
,
4911 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4913 *addr
= (uint32_t) (*addr
+ offset64
);
4923 /* Record the address and contents of the memory that will be changed
4924 by the current instruction. Return -1 if something goes wrong, 0
4928 i386_record_lea_modrm (struct i386_record_s
*irp
)
4930 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4933 if (irp
->override
>= 0)
4935 if (record_full_memory_query
)
4938 Process record ignores the memory change of instruction at address %s\n\
4939 because it can't get the value of the segment register.\n\
4940 Do you want to stop the program?"),
4941 paddress (gdbarch
, irp
->orig_addr
)))
4948 if (i386_record_lea_modrm_addr (irp
, &addr
))
4951 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4957 /* Record the effects of a push operation. Return -1 if something
4958 goes wrong, 0 otherwise. */
4961 i386_record_push (struct i386_record_s
*irp
, int size
)
4965 if (record_full_arch_list_add_reg (irp
->regcache
,
4966 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4968 regcache_raw_read_unsigned (irp
->regcache
,
4969 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4971 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4978 /* Defines contents to record. */
4979 #define I386_SAVE_FPU_REGS 0xfffd
4980 #define I386_SAVE_FPU_ENV 0xfffe
4981 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4983 /* Record the values of the floating point registers which will be
4984 changed by the current instruction. Returns -1 if something is
4985 wrong, 0 otherwise. */
4987 static int i386_record_floats (struct gdbarch
*gdbarch
,
4988 struct i386_record_s
*ir
,
4991 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4994 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4995 happen. Currently we store st0-st7 registers, but we need not store all
4996 registers all the time, in future we use ftag register and record only
4997 those who are not marked as an empty. */
4999 if (I386_SAVE_FPU_REGS
== iregnum
)
5001 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
5003 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5007 else if (I386_SAVE_FPU_ENV
== iregnum
)
5009 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5011 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5015 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
5017 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5019 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5023 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
5024 (iregnum
<= I387_FOP_REGNUM (tdep
)))
5026 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5031 /* Parameter error. */
5034 if(I386_SAVE_FPU_ENV
!= iregnum
)
5036 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5038 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5045 /* Parse the current instruction, and record the values of the
5046 registers and memory that will be changed by the current
5047 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5049 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5050 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5053 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5054 CORE_ADDR input_addr
)
5056 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5062 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5063 struct i386_record_s ir
;
5064 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5068 memset (&ir
, 0, sizeof (struct i386_record_s
));
5069 ir
.regcache
= regcache
;
5070 ir
.addr
= input_addr
;
5071 ir
.orig_addr
= input_addr
;
5075 ir
.popl_esp_hack
= 0;
5076 ir
.regmap
= tdep
->record_regmap
;
5077 ir
.gdbarch
= gdbarch
;
5079 if (record_debug
> 1)
5080 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5082 paddress (gdbarch
, ir
.addr
));
5087 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5090 switch (opcode8
) /* Instruction prefixes */
5092 case REPE_PREFIX_OPCODE
:
5093 prefixes
|= PREFIX_REPZ
;
5095 case REPNE_PREFIX_OPCODE
:
5096 prefixes
|= PREFIX_REPNZ
;
5098 case LOCK_PREFIX_OPCODE
:
5099 prefixes
|= PREFIX_LOCK
;
5101 case CS_PREFIX_OPCODE
:
5102 ir
.override
= X86_RECORD_CS_REGNUM
;
5104 case SS_PREFIX_OPCODE
:
5105 ir
.override
= X86_RECORD_SS_REGNUM
;
5107 case DS_PREFIX_OPCODE
:
5108 ir
.override
= X86_RECORD_DS_REGNUM
;
5110 case ES_PREFIX_OPCODE
:
5111 ir
.override
= X86_RECORD_ES_REGNUM
;
5113 case FS_PREFIX_OPCODE
:
5114 ir
.override
= X86_RECORD_FS_REGNUM
;
5116 case GS_PREFIX_OPCODE
:
5117 ir
.override
= X86_RECORD_GS_REGNUM
;
5119 case DATA_PREFIX_OPCODE
:
5120 prefixes
|= PREFIX_DATA
;
5122 case ADDR_PREFIX_OPCODE
:
5123 prefixes
|= PREFIX_ADDR
;
5125 case 0x40: /* i386 inc %eax */
5126 case 0x41: /* i386 inc %ecx */
5127 case 0x42: /* i386 inc %edx */
5128 case 0x43: /* i386 inc %ebx */
5129 case 0x44: /* i386 inc %esp */
5130 case 0x45: /* i386 inc %ebp */
5131 case 0x46: /* i386 inc %esi */
5132 case 0x47: /* i386 inc %edi */
5133 case 0x48: /* i386 dec %eax */
5134 case 0x49: /* i386 dec %ecx */
5135 case 0x4a: /* i386 dec %edx */
5136 case 0x4b: /* i386 dec %ebx */
5137 case 0x4c: /* i386 dec %esp */
5138 case 0x4d: /* i386 dec %ebp */
5139 case 0x4e: /* i386 dec %esi */
5140 case 0x4f: /* i386 dec %edi */
5141 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5144 rex_w
= (opcode8
>> 3) & 1;
5145 rex_r
= (opcode8
& 0x4) << 1;
5146 ir
.rex_x
= (opcode8
& 0x2) << 2;
5147 ir
.rex_b
= (opcode8
& 0x1) << 3;
5149 else /* 32 bit target */
5158 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5164 if (prefixes
& PREFIX_DATA
)
5167 if (prefixes
& PREFIX_ADDR
)
5169 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5172 /* Now check op code. */
5173 opcode
= (uint32_t) opcode8
;
5178 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5181 opcode
= (uint32_t) opcode8
| 0x0f00;
5185 case 0x00: /* arith & logic */
5233 if (((opcode
>> 3) & 7) != OP_CMPL
)
5235 if ((opcode
& 1) == 0)
5238 ir
.ot
= ir
.dflag
+ OT_WORD
;
5240 switch ((opcode
>> 1) & 3)
5242 case 0: /* OP Ev, Gv */
5243 if (i386_record_modrm (&ir
))
5247 if (i386_record_lea_modrm (&ir
))
5253 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5258 case 1: /* OP Gv, Ev */
5259 if (i386_record_modrm (&ir
))
5262 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5264 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5266 case 2: /* OP A, Iv */
5267 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5274 case 0x80: /* GRP1 */
5278 if (i386_record_modrm (&ir
))
5281 if (ir
.reg
!= OP_CMPL
)
5283 if ((opcode
& 1) == 0)
5286 ir
.ot
= ir
.dflag
+ OT_WORD
;
5293 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5294 if (i386_record_lea_modrm (&ir
))
5298 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5300 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5303 case 0x40: /* inc */
5312 case 0x48: /* dec */
5321 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5325 case 0xf6: /* GRP3 */
5327 if ((opcode
& 1) == 0)
5330 ir
.ot
= ir
.dflag
+ OT_WORD
;
5331 if (i386_record_modrm (&ir
))
5334 if (ir
.mod
!= 3 && ir
.reg
== 0)
5335 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5346 if (i386_record_lea_modrm (&ir
))
5352 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5356 if (ir
.reg
== 3) /* neg */
5357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5364 if (ir
.ot
!= OT_BYTE
)
5365 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5366 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5370 opcode
= opcode
<< 8 | ir
.modrm
;
5376 case 0xfe: /* GRP4 */
5377 case 0xff: /* GRP5 */
5378 if (i386_record_modrm (&ir
))
5380 if (ir
.reg
>= 2 && opcode
== 0xfe)
5383 opcode
= opcode
<< 8 | ir
.modrm
;
5390 if ((opcode
& 1) == 0)
5393 ir
.ot
= ir
.dflag
+ OT_WORD
;
5396 if (i386_record_lea_modrm (&ir
))
5402 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5406 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5409 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5411 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5413 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5417 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5423 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5426 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5428 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5433 opcode
= opcode
<< 8 | ir
.modrm
;
5439 case 0x84: /* test */
5443 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5446 case 0x98: /* CWDE/CBW */
5447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5450 case 0x99: /* CDQ/CWD */
5451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5455 case 0x0faf: /* imul */
5458 ir
.ot
= ir
.dflag
+ OT_WORD
;
5459 if (i386_record_modrm (&ir
))
5462 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5463 else if (opcode
== 0x6b)
5466 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5472 case 0x0fc0: /* xadd */
5474 if ((opcode
& 1) == 0)
5477 ir
.ot
= ir
.dflag
+ OT_WORD
;
5478 if (i386_record_modrm (&ir
))
5483 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5485 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5486 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5488 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5492 if (i386_record_lea_modrm (&ir
))
5494 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5501 case 0x0fb0: /* cmpxchg */
5503 if ((opcode
& 1) == 0)
5506 ir
.ot
= ir
.dflag
+ OT_WORD
;
5507 if (i386_record_modrm (&ir
))
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5513 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5520 if (i386_record_lea_modrm (&ir
))
5523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5526 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5527 if (i386_record_modrm (&ir
))
5531 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5532 an extended opcode. rdrand has bits 110 (/6) and rdseed
5533 has bits 111 (/7). */
5534 if (ir
.reg
== 6 || ir
.reg
== 7)
5536 /* The storage register is described by the 3 R/M bits, but the
5537 REX.B prefix may be used to give access to registers
5538 R8~R15. In this case ir.rex_b + R/M will give us the register
5539 in the range R8~R15.
5541 REX.W may also be used to access 64-bit registers, but we
5542 already record entire registers and not just partial bits
5544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5545 /* These instructions also set conditional bits. */
5546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5551 /* We don't handle this particular instruction yet. */
5553 opcode
= opcode
<< 8 | ir
.modrm
;
5557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5559 if (i386_record_lea_modrm (&ir
))
5561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5564 case 0x50: /* push */
5574 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5576 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5580 case 0x06: /* push es */
5581 case 0x0e: /* push cs */
5582 case 0x16: /* push ss */
5583 case 0x1e: /* push ds */
5584 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5589 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5593 case 0x0fa0: /* push fs */
5594 case 0x0fa8: /* push gs */
5595 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5600 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5604 case 0x60: /* pusha */
5605 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5610 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5614 case 0x58: /* pop */
5622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5623 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5626 case 0x61: /* popa */
5627 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5632 for (regnum
= X86_RECORD_REAX_REGNUM
;
5633 regnum
<= X86_RECORD_REDI_REGNUM
;
5635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5638 case 0x8f: /* pop */
5639 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5640 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5642 ir
.ot
= ir
.dflag
+ OT_WORD
;
5643 if (i386_record_modrm (&ir
))
5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5649 ir
.popl_esp_hack
= 1 << ir
.ot
;
5650 if (i386_record_lea_modrm (&ir
))
5653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5656 case 0xc8: /* enter */
5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5658 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5660 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5664 case 0xc9: /* leave */
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5669 case 0x07: /* pop es */
5670 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5680 case 0x17: /* pop ss */
5681 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5686 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5691 case 0x1f: /* pop ds */
5692 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5697 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5698 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5702 case 0x0fa1: /* pop fs */
5703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5708 case 0x0fa9: /* pop gs */
5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5714 case 0x88: /* mov */
5718 if ((opcode
& 1) == 0)
5721 ir
.ot
= ir
.dflag
+ OT_WORD
;
5723 if (i386_record_modrm (&ir
))
5728 if (opcode
== 0xc6 || opcode
== 0xc7)
5729 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5730 if (i386_record_lea_modrm (&ir
))
5735 if (opcode
== 0xc6 || opcode
== 0xc7)
5737 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5739 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5743 case 0x8a: /* mov */
5745 if ((opcode
& 1) == 0)
5748 ir
.ot
= ir
.dflag
+ OT_WORD
;
5749 if (i386_record_modrm (&ir
))
5752 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5757 case 0x8c: /* mov seg */
5758 if (i386_record_modrm (&ir
))
5763 opcode
= opcode
<< 8 | ir
.modrm
;
5768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5772 if (i386_record_lea_modrm (&ir
))
5777 case 0x8e: /* mov seg */
5778 if (i386_record_modrm (&ir
))
5783 regnum
= X86_RECORD_ES_REGNUM
;
5786 regnum
= X86_RECORD_SS_REGNUM
;
5789 regnum
= X86_RECORD_DS_REGNUM
;
5792 regnum
= X86_RECORD_FS_REGNUM
;
5795 regnum
= X86_RECORD_GS_REGNUM
;
5799 opcode
= opcode
<< 8 | ir
.modrm
;
5803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5804 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5807 case 0x0fb6: /* movzbS */
5808 case 0x0fb7: /* movzwS */
5809 case 0x0fbe: /* movsbS */
5810 case 0x0fbf: /* movswS */
5811 if (i386_record_modrm (&ir
))
5813 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5816 case 0x8d: /* lea */
5817 if (i386_record_modrm (&ir
))
5822 opcode
= opcode
<< 8 | ir
.modrm
;
5827 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5832 case 0xa0: /* mov EAX */
5835 case 0xd7: /* xlat */
5836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5839 case 0xa2: /* mov EAX */
5841 if (ir
.override
>= 0)
5843 if (record_full_memory_query
)
5846 Process record ignores the memory change of instruction at address %s\n\
5847 because it can't get the value of the segment register.\n\
5848 Do you want to stop the program?"),
5849 paddress (gdbarch
, ir
.orig_addr
)))
5855 if ((opcode
& 1) == 0)
5858 ir
.ot
= ir
.dflag
+ OT_WORD
;
5861 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5864 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5868 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5871 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5875 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5878 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5880 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5885 case 0xb0: /* mov R, Ib */
5893 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5894 ? ((opcode
& 0x7) | ir
.rex_b
)
5895 : ((opcode
& 0x7) & 0x3));
5898 case 0xb8: /* mov R, Iv */
5906 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5909 case 0x91: /* xchg R, EAX */
5916 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5917 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5920 case 0x86: /* xchg Ev, Gv */
5922 if ((opcode
& 1) == 0)
5925 ir
.ot
= ir
.dflag
+ OT_WORD
;
5926 if (i386_record_modrm (&ir
))
5931 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5933 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5937 if (i386_record_lea_modrm (&ir
))
5941 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5946 case 0xc4: /* les Gv */
5947 case 0xc5: /* lds Gv */
5948 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5954 case 0x0fb2: /* lss Gv */
5955 case 0x0fb4: /* lfs Gv */
5956 case 0x0fb5: /* lgs Gv */
5957 if (i386_record_modrm (&ir
))
5965 opcode
= opcode
<< 8 | ir
.modrm
;
5970 case 0xc4: /* les Gv */
5971 regnum
= X86_RECORD_ES_REGNUM
;
5973 case 0xc5: /* lds Gv */
5974 regnum
= X86_RECORD_DS_REGNUM
;
5976 case 0x0fb2: /* lss Gv */
5977 regnum
= X86_RECORD_SS_REGNUM
;
5979 case 0x0fb4: /* lfs Gv */
5980 regnum
= X86_RECORD_FS_REGNUM
;
5982 case 0x0fb5: /* lgs Gv */
5983 regnum
= X86_RECORD_GS_REGNUM
;
5986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5987 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5988 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5991 case 0xc0: /* shifts */
5997 if ((opcode
& 1) == 0)
6000 ir
.ot
= ir
.dflag
+ OT_WORD
;
6001 if (i386_record_modrm (&ir
))
6003 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
6005 if (i386_record_lea_modrm (&ir
))
6011 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
6013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
6015 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6022 if (i386_record_modrm (&ir
))
6026 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6031 if (i386_record_lea_modrm (&ir
))
6036 case 0xd8: /* Floats. */
6044 if (i386_record_modrm (&ir
))
6046 ir
.reg
|= ((opcode
& 7) << 3);
6052 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6060 /* For fcom, ficom nothing to do. */
6066 /* For fcomp, ficomp pop FPU stack, store all. */
6067 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6094 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6095 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6096 of code, always affects st(0) register. */
6097 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6121 /* Handling fld, fild. */
6122 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6126 switch (ir
.reg
>> 4)
6129 if (record_full_arch_list_add_mem (addr64
, 4))
6133 if (record_full_arch_list_add_mem (addr64
, 8))
6139 if (record_full_arch_list_add_mem (addr64
, 2))
6145 switch (ir
.reg
>> 4)
6148 if (record_full_arch_list_add_mem (addr64
, 4))
6150 if (3 == (ir
.reg
& 7))
6152 /* For fstp m32fp. */
6153 if (i386_record_floats (gdbarch
, &ir
,
6154 I386_SAVE_FPU_REGS
))
6159 if (record_full_arch_list_add_mem (addr64
, 4))
6161 if ((3 == (ir
.reg
& 7))
6162 || (5 == (ir
.reg
& 7))
6163 || (7 == (ir
.reg
& 7)))
6165 /* For fstp insn. */
6166 if (i386_record_floats (gdbarch
, &ir
,
6167 I386_SAVE_FPU_REGS
))
6172 if (record_full_arch_list_add_mem (addr64
, 8))
6174 if (3 == (ir
.reg
& 7))
6176 /* For fstp m64fp. */
6177 if (i386_record_floats (gdbarch
, &ir
,
6178 I386_SAVE_FPU_REGS
))
6183 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6185 /* For fistp, fbld, fild, fbstp. */
6186 if (i386_record_floats (gdbarch
, &ir
,
6187 I386_SAVE_FPU_REGS
))
6192 if (record_full_arch_list_add_mem (addr64
, 2))
6201 if (i386_record_floats (gdbarch
, &ir
,
6202 I386_SAVE_FPU_ENV_REG_STACK
))
6207 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6212 if (i386_record_floats (gdbarch
, &ir
,
6213 I386_SAVE_FPU_ENV_REG_STACK
))
6219 if (record_full_arch_list_add_mem (addr64
, 28))
6224 if (record_full_arch_list_add_mem (addr64
, 14))
6230 if (record_full_arch_list_add_mem (addr64
, 2))
6232 /* Insn fstp, fbstp. */
6233 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6238 if (record_full_arch_list_add_mem (addr64
, 10))
6244 if (record_full_arch_list_add_mem (addr64
, 28))
6250 if (record_full_arch_list_add_mem (addr64
, 14))
6254 if (record_full_arch_list_add_mem (addr64
, 80))
6257 if (i386_record_floats (gdbarch
, &ir
,
6258 I386_SAVE_FPU_ENV_REG_STACK
))
6262 if (record_full_arch_list_add_mem (addr64
, 8))
6265 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6270 opcode
= opcode
<< 8 | ir
.modrm
;
6275 /* Opcode is an extension of modR/M byte. */
6281 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6285 if (0x0c == (ir
.modrm
>> 4))
6287 if ((ir
.modrm
& 0x0f) <= 7)
6289 if (i386_record_floats (gdbarch
, &ir
,
6290 I386_SAVE_FPU_REGS
))
6295 if (i386_record_floats (gdbarch
, &ir
,
6296 I387_ST0_REGNUM (tdep
)))
6298 /* If only st(0) is changing, then we have already
6300 if ((ir
.modrm
& 0x0f) - 0x08)
6302 if (i386_record_floats (gdbarch
, &ir
,
6303 I387_ST0_REGNUM (tdep
) +
6304 ((ir
.modrm
& 0x0f) - 0x08)))
6322 if (i386_record_floats (gdbarch
, &ir
,
6323 I387_ST0_REGNUM (tdep
)))
6341 if (i386_record_floats (gdbarch
, &ir
,
6342 I386_SAVE_FPU_REGS
))
6346 if (i386_record_floats (gdbarch
, &ir
,
6347 I387_ST0_REGNUM (tdep
)))
6349 if (i386_record_floats (gdbarch
, &ir
,
6350 I387_ST0_REGNUM (tdep
) + 1))
6357 if (0xe9 == ir
.modrm
)
6359 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6362 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6364 if (i386_record_floats (gdbarch
, &ir
,
6365 I387_ST0_REGNUM (tdep
)))
6367 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6369 if (i386_record_floats (gdbarch
, &ir
,
6370 I387_ST0_REGNUM (tdep
) +
6374 else if ((ir
.modrm
& 0x0f) - 0x08)
6376 if (i386_record_floats (gdbarch
, &ir
,
6377 I387_ST0_REGNUM (tdep
) +
6378 ((ir
.modrm
& 0x0f) - 0x08)))
6384 if (0xe3 == ir
.modrm
)
6386 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6389 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6391 if (i386_record_floats (gdbarch
, &ir
,
6392 I387_ST0_REGNUM (tdep
)))
6394 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6396 if (i386_record_floats (gdbarch
, &ir
,
6397 I387_ST0_REGNUM (tdep
) +
6401 else if ((ir
.modrm
& 0x0f) - 0x08)
6403 if (i386_record_floats (gdbarch
, &ir
,
6404 I387_ST0_REGNUM (tdep
) +
6405 ((ir
.modrm
& 0x0f) - 0x08)))
6411 if ((0x0c == ir
.modrm
>> 4)
6412 || (0x0d == ir
.modrm
>> 4)
6413 || (0x0f == ir
.modrm
>> 4))
6415 if ((ir
.modrm
& 0x0f) <= 7)
6417 if (i386_record_floats (gdbarch
, &ir
,
6418 I387_ST0_REGNUM (tdep
) +
6424 if (i386_record_floats (gdbarch
, &ir
,
6425 I387_ST0_REGNUM (tdep
) +
6426 ((ir
.modrm
& 0x0f) - 0x08)))
6432 if (0x0c == ir
.modrm
>> 4)
6434 if (i386_record_floats (gdbarch
, &ir
,
6435 I387_FTAG_REGNUM (tdep
)))
6438 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6440 if ((ir
.modrm
& 0x0f) <= 7)
6442 if (i386_record_floats (gdbarch
, &ir
,
6443 I387_ST0_REGNUM (tdep
) +
6449 if (i386_record_floats (gdbarch
, &ir
,
6450 I386_SAVE_FPU_REGS
))
6456 if ((0x0c == ir
.modrm
>> 4)
6457 || (0x0e == ir
.modrm
>> 4)
6458 || (0x0f == ir
.modrm
>> 4)
6459 || (0xd9 == ir
.modrm
))
6461 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6466 if (0xe0 == ir
.modrm
)
6468 if (record_full_arch_list_add_reg (ir
.regcache
,
6472 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6474 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6482 case 0xa4: /* movsS */
6484 case 0xaa: /* stosS */
6486 case 0x6c: /* insS */
6488 regcache_raw_read_unsigned (ir
.regcache
,
6489 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6495 if ((opcode
& 1) == 0)
6498 ir
.ot
= ir
.dflag
+ OT_WORD
;
6499 regcache_raw_read_unsigned (ir
.regcache
,
6500 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6503 regcache_raw_read_unsigned (ir
.regcache
,
6504 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6506 regcache_raw_read_unsigned (ir
.regcache
,
6507 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6509 if (ir
.aflag
&& (es
!= ds
))
6511 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6512 if (record_full_memory_query
)
6515 Process record ignores the memory change of instruction at address %s\n\
6516 because it can't get the value of the segment register.\n\
6517 Do you want to stop the program?"),
6518 paddress (gdbarch
, ir
.orig_addr
)))
6524 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6528 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6530 if (opcode
== 0xa4 || opcode
== 0xa5)
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6537 case 0xa6: /* cmpsS */
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6541 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6542 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6546 case 0xac: /* lodsS */
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6550 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6555 case 0xae: /* scasS */
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6558 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6563 case 0x6e: /* outsS */
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6566 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6571 case 0xe4: /* port I/O */
6575 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6586 case 0xc2: /* ret im */
6587 case 0xc3: /* ret */
6588 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6589 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6592 case 0xca: /* lret im */
6593 case 0xcb: /* lret */
6594 case 0xcf: /* iret */
6595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6596 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6597 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6600 case 0xe8: /* call im */
6601 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6603 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6607 case 0x9a: /* lcall im */
6608 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6614 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6618 case 0xe9: /* jmp im */
6619 case 0xea: /* ljmp im */
6620 case 0xeb: /* jmp Jb */
6621 case 0x70: /* jcc Jb */
6637 case 0x0f80: /* jcc Jv */
6655 case 0x0f90: /* setcc Gv */
6671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6673 if (i386_record_modrm (&ir
))
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6680 if (i386_record_lea_modrm (&ir
))
6685 case 0x0f40: /* cmov Gv, Ev */
6701 if (i386_record_modrm (&ir
))
6704 if (ir
.dflag
== OT_BYTE
)
6706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6710 case 0x9c: /* pushf */
6711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6712 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6714 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6718 case 0x9d: /* popf */
6719 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6720 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6723 case 0x9e: /* sahf */
6724 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6730 case 0xf5: /* cmc */
6731 case 0xf8: /* clc */
6732 case 0xf9: /* stc */
6733 case 0xfc: /* cld */
6734 case 0xfd: /* std */
6735 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6738 case 0x9f: /* lahf */
6739 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6744 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6748 /* bit operations */
6749 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6750 ir
.ot
= ir
.dflag
+ OT_WORD
;
6751 if (i386_record_modrm (&ir
))
6756 opcode
= opcode
<< 8 | ir
.modrm
;
6762 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6765 if (i386_record_lea_modrm (&ir
))
6769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6772 case 0x0fa3: /* bt Gv, Ev */
6773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6776 case 0x0fab: /* bts */
6777 case 0x0fb3: /* btr */
6778 case 0x0fbb: /* btc */
6779 ir
.ot
= ir
.dflag
+ OT_WORD
;
6780 if (i386_record_modrm (&ir
))
6783 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6787 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6789 regcache_raw_read_unsigned (ir
.regcache
,
6790 ir
.regmap
[ir
.reg
| rex_r
],
6795 addr64
+= ((int16_t) addr
>> 4) << 4;
6798 addr64
+= ((int32_t) addr
>> 5) << 5;
6801 addr64
+= ((int64_t) addr
>> 6) << 6;
6804 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6806 if (i386_record_lea_modrm (&ir
))
6809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6812 case 0x0fbc: /* bsf */
6813 case 0x0fbd: /* bsr */
6814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6819 case 0x27: /* daa */
6820 case 0x2f: /* das */
6821 case 0x37: /* aaa */
6822 case 0x3f: /* aas */
6823 case 0xd4: /* aam */
6824 case 0xd5: /* aad */
6825 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6831 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6835 case 0x90: /* nop */
6836 if (prefixes
& PREFIX_LOCK
)
6843 case 0x9b: /* fwait */
6844 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6846 opcode
= (uint32_t) opcode8
;
6852 case 0xcc: /* int3 */
6853 printf_unfiltered (_("Process record does not support instruction "
6860 case 0xcd: /* int */
6864 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6867 if (interrupt
!= 0x80
6868 || tdep
->i386_intx80_record
== NULL
)
6870 printf_unfiltered (_("Process record does not support "
6871 "instruction int 0x%02x.\n"),
6876 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6883 case 0xce: /* into */
6884 printf_unfiltered (_("Process record does not support "
6885 "instruction into.\n"));
6890 case 0xfa: /* cli */
6891 case 0xfb: /* sti */
6894 case 0x62: /* bound */
6895 printf_unfiltered (_("Process record does not support "
6896 "instruction bound.\n"));
6901 case 0x0fc8: /* bswap reg */
6909 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6912 case 0xd6: /* salc */
6913 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6919 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6922 case 0xe0: /* loopnz */
6923 case 0xe1: /* loopz */
6924 case 0xe2: /* loop */
6925 case 0xe3: /* jecxz */
6926 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6927 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6930 case 0x0f30: /* wrmsr */
6931 printf_unfiltered (_("Process record does not support "
6932 "instruction wrmsr.\n"));
6937 case 0x0f32: /* rdmsr */
6938 printf_unfiltered (_("Process record does not support "
6939 "instruction rdmsr.\n"));
6944 case 0x0f31: /* rdtsc */
6945 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6946 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6949 case 0x0f34: /* sysenter */
6952 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6957 if (tdep
->i386_sysenter_record
== NULL
)
6959 printf_unfiltered (_("Process record does not support "
6960 "instruction sysenter.\n"));
6964 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6970 case 0x0f35: /* sysexit */
6971 printf_unfiltered (_("Process record does not support "
6972 "instruction sysexit.\n"));
6977 case 0x0f05: /* syscall */
6980 if (tdep
->i386_syscall_record
== NULL
)
6982 printf_unfiltered (_("Process record does not support "
6983 "instruction syscall.\n"));
6987 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6993 case 0x0f07: /* sysret */
6994 printf_unfiltered (_("Process record does not support "
6995 "instruction sysret.\n"));
7000 case 0x0fa2: /* cpuid */
7001 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7007 case 0xf4: /* hlt */
7008 printf_unfiltered (_("Process record does not support "
7009 "instruction hlt.\n"));
7015 if (i386_record_modrm (&ir
))
7022 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7026 if (i386_record_lea_modrm (&ir
))
7035 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7039 opcode
= opcode
<< 8 | ir
.modrm
;
7046 if (i386_record_modrm (&ir
))
7057 opcode
= opcode
<< 8 | ir
.modrm
;
7060 if (ir
.override
>= 0)
7062 if (record_full_memory_query
)
7065 Process record ignores the memory change of instruction at address %s\n\
7066 because it can't get the value of the segment register.\n\
7067 Do you want to stop the program?"),
7068 paddress (gdbarch
, ir
.orig_addr
)))
7074 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7076 if (record_full_arch_list_add_mem (addr64
, 2))
7079 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7081 if (record_full_arch_list_add_mem (addr64
, 8))
7086 if (record_full_arch_list_add_mem (addr64
, 4))
7097 case 0: /* monitor */
7100 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7104 opcode
= opcode
<< 8 | ir
.modrm
;
7112 if (ir
.override
>= 0)
7114 if (record_full_memory_query
)
7117 Process record ignores the memory change of instruction at address %s\n\
7118 because it can't get the value of the segment register.\n\
7119 Do you want to stop the program?"),
7120 paddress (gdbarch
, ir
.orig_addr
)))
7128 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7130 if (record_full_arch_list_add_mem (addr64
, 2))
7133 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7135 if (record_full_arch_list_add_mem (addr64
, 8))
7140 if (record_full_arch_list_add_mem (addr64
, 4))
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7153 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7157 else if (ir
.rm
== 1)
7165 opcode
= opcode
<< 8 | ir
.modrm
;
7172 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7178 if (i386_record_lea_modrm (&ir
))
7181 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7184 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7186 case 7: /* invlpg */
7189 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7194 opcode
= opcode
<< 8 | ir
.modrm
;
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7203 opcode
= opcode
<< 8 | ir
.modrm
;
7209 case 0x0f08: /* invd */
7210 case 0x0f09: /* wbinvd */
7213 case 0x63: /* arpl */
7214 if (i386_record_modrm (&ir
))
7216 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7218 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7219 ? (ir
.reg
| rex_r
) : ir
.rm
);
7223 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7224 if (i386_record_lea_modrm (&ir
))
7227 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7228 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7231 case 0x0f02: /* lar */
7232 case 0x0f03: /* lsl */
7233 if (i386_record_modrm (&ir
))
7235 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7240 if (i386_record_modrm (&ir
))
7242 if (ir
.mod
== 3 && ir
.reg
== 3)
7245 opcode
= opcode
<< 8 | ir
.modrm
;
7257 /* nop (multi byte) */
7260 case 0x0f20: /* mov reg, crN */
7261 case 0x0f22: /* mov crN, reg */
7262 if (i386_record_modrm (&ir
))
7264 if ((ir
.modrm
& 0xc0) != 0xc0)
7267 opcode
= opcode
<< 8 | ir
.modrm
;
7278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7284 opcode
= opcode
<< 8 | ir
.modrm
;
7290 case 0x0f21: /* mov reg, drN */
7291 case 0x0f23: /* mov drN, reg */
7292 if (i386_record_modrm (&ir
))
7294 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7295 || ir
.reg
== 5 || ir
.reg
>= 8)
7298 opcode
= opcode
<< 8 | ir
.modrm
;
7302 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7307 case 0x0f06: /* clts */
7308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7311 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7313 case 0x0f0d: /* 3DNow! prefetch */
7316 case 0x0f0e: /* 3DNow! femms */
7317 case 0x0f77: /* emms */
7318 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7320 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7323 case 0x0f0f: /* 3DNow! data */
7324 if (i386_record_modrm (&ir
))
7326 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7331 case 0x0c: /* 3DNow! pi2fw */
7332 case 0x0d: /* 3DNow! pi2fd */
7333 case 0x1c: /* 3DNow! pf2iw */
7334 case 0x1d: /* 3DNow! pf2id */
7335 case 0x8a: /* 3DNow! pfnacc */
7336 case 0x8e: /* 3DNow! pfpnacc */
7337 case 0x90: /* 3DNow! pfcmpge */
7338 case 0x94: /* 3DNow! pfmin */
7339 case 0x96: /* 3DNow! pfrcp */
7340 case 0x97: /* 3DNow! pfrsqrt */
7341 case 0x9a: /* 3DNow! pfsub */
7342 case 0x9e: /* 3DNow! pfadd */
7343 case 0xa0: /* 3DNow! pfcmpgt */
7344 case 0xa4: /* 3DNow! pfmax */
7345 case 0xa6: /* 3DNow! pfrcpit1 */
7346 case 0xa7: /* 3DNow! pfrsqit1 */
7347 case 0xaa: /* 3DNow! pfsubr */
7348 case 0xae: /* 3DNow! pfacc */
7349 case 0xb0: /* 3DNow! pfcmpeq */
7350 case 0xb4: /* 3DNow! pfmul */
7351 case 0xb6: /* 3DNow! pfrcpit2 */
7352 case 0xb7: /* 3DNow! pmulhrw */
7353 case 0xbb: /* 3DNow! pswapd */
7354 case 0xbf: /* 3DNow! pavgusb */
7355 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7356 goto no_support_3dnow_data
;
7357 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7361 no_support_3dnow_data
:
7362 opcode
= (opcode
<< 8) | opcode8
;
7368 case 0x0faa: /* rsm */
7369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7373 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7381 if (i386_record_modrm (&ir
))
7385 case 0: /* fxsave */
7389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7390 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7392 if (record_full_arch_list_add_mem (tmpu64
, 512))
7397 case 1: /* fxrstor */
7401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7403 for (i
= I387_MM0_REGNUM (tdep
);
7404 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7405 record_full_arch_list_add_reg (ir
.regcache
, i
);
7407 for (i
= I387_XMM0_REGNUM (tdep
);
7408 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7409 record_full_arch_list_add_reg (ir
.regcache
, i
);
7411 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7412 record_full_arch_list_add_reg (ir
.regcache
,
7413 I387_MXCSR_REGNUM(tdep
));
7415 for (i
= I387_ST0_REGNUM (tdep
);
7416 i386_fp_regnum_p (gdbarch
, i
); i
++)
7417 record_full_arch_list_add_reg (ir
.regcache
, i
);
7419 for (i
= I387_FCTRL_REGNUM (tdep
);
7420 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7421 record_full_arch_list_add_reg (ir
.regcache
, i
);
7425 case 2: /* ldmxcsr */
7426 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7428 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7431 case 3: /* stmxcsr */
7433 if (i386_record_lea_modrm (&ir
))
7437 case 5: /* lfence */
7438 case 6: /* mfence */
7439 case 7: /* sfence clflush */
7443 opcode
= (opcode
<< 8) | ir
.modrm
;
7449 case 0x0fc3: /* movnti */
7450 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7451 if (i386_record_modrm (&ir
))
7456 if (i386_record_lea_modrm (&ir
))
7460 /* Add prefix to opcode. */
7575 /* Mask out PREFIX_ADDR. */
7576 switch ((prefixes
& ~PREFIX_ADDR
))
7588 reswitch_prefix_add
:
7596 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7599 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7600 goto reswitch_prefix_add
;
7603 case 0x0f10: /* movups */
7604 case 0x660f10: /* movupd */
7605 case 0xf30f10: /* movss */
7606 case 0xf20f10: /* movsd */
7607 case 0x0f12: /* movlps */
7608 case 0x660f12: /* movlpd */
7609 case 0xf30f12: /* movsldup */
7610 case 0xf20f12: /* movddup */
7611 case 0x0f14: /* unpcklps */
7612 case 0x660f14: /* unpcklpd */
7613 case 0x0f15: /* unpckhps */
7614 case 0x660f15: /* unpckhpd */
7615 case 0x0f16: /* movhps */
7616 case 0x660f16: /* movhpd */
7617 case 0xf30f16: /* movshdup */
7618 case 0x0f28: /* movaps */
7619 case 0x660f28: /* movapd */
7620 case 0x0f2a: /* cvtpi2ps */
7621 case 0x660f2a: /* cvtpi2pd */
7622 case 0xf30f2a: /* cvtsi2ss */
7623 case 0xf20f2a: /* cvtsi2sd */
7624 case 0x0f2c: /* cvttps2pi */
7625 case 0x660f2c: /* cvttpd2pi */
7626 case 0x0f2d: /* cvtps2pi */
7627 case 0x660f2d: /* cvtpd2pi */
7628 case 0x660f3800: /* pshufb */
7629 case 0x660f3801: /* phaddw */
7630 case 0x660f3802: /* phaddd */
7631 case 0x660f3803: /* phaddsw */
7632 case 0x660f3804: /* pmaddubsw */
7633 case 0x660f3805: /* phsubw */
7634 case 0x660f3806: /* phsubd */
7635 case 0x660f3807: /* phsubsw */
7636 case 0x660f3808: /* psignb */
7637 case 0x660f3809: /* psignw */
7638 case 0x660f380a: /* psignd */
7639 case 0x660f380b: /* pmulhrsw */
7640 case 0x660f3810: /* pblendvb */
7641 case 0x660f3814: /* blendvps */
7642 case 0x660f3815: /* blendvpd */
7643 case 0x660f381c: /* pabsb */
7644 case 0x660f381d: /* pabsw */
7645 case 0x660f381e: /* pabsd */
7646 case 0x660f3820: /* pmovsxbw */
7647 case 0x660f3821: /* pmovsxbd */
7648 case 0x660f3822: /* pmovsxbq */
7649 case 0x660f3823: /* pmovsxwd */
7650 case 0x660f3824: /* pmovsxwq */
7651 case 0x660f3825: /* pmovsxdq */
7652 case 0x660f3828: /* pmuldq */
7653 case 0x660f3829: /* pcmpeqq */
7654 case 0x660f382a: /* movntdqa */
7655 case 0x660f3a08: /* roundps */
7656 case 0x660f3a09: /* roundpd */
7657 case 0x660f3a0a: /* roundss */
7658 case 0x660f3a0b: /* roundsd */
7659 case 0x660f3a0c: /* blendps */
7660 case 0x660f3a0d: /* blendpd */
7661 case 0x660f3a0e: /* pblendw */
7662 case 0x660f3a0f: /* palignr */
7663 case 0x660f3a20: /* pinsrb */
7664 case 0x660f3a21: /* insertps */
7665 case 0x660f3a22: /* pinsrd pinsrq */
7666 case 0x660f3a40: /* dpps */
7667 case 0x660f3a41: /* dppd */
7668 case 0x660f3a42: /* mpsadbw */
7669 case 0x660f3a60: /* pcmpestrm */
7670 case 0x660f3a61: /* pcmpestri */
7671 case 0x660f3a62: /* pcmpistrm */
7672 case 0x660f3a63: /* pcmpistri */
7673 case 0x0f51: /* sqrtps */
7674 case 0x660f51: /* sqrtpd */
7675 case 0xf20f51: /* sqrtsd */
7676 case 0xf30f51: /* sqrtss */
7677 case 0x0f52: /* rsqrtps */
7678 case 0xf30f52: /* rsqrtss */
7679 case 0x0f53: /* rcpps */
7680 case 0xf30f53: /* rcpss */
7681 case 0x0f54: /* andps */
7682 case 0x660f54: /* andpd */
7683 case 0x0f55: /* andnps */
7684 case 0x660f55: /* andnpd */
7685 case 0x0f56: /* orps */
7686 case 0x660f56: /* orpd */
7687 case 0x0f57: /* xorps */
7688 case 0x660f57: /* xorpd */
7689 case 0x0f58: /* addps */
7690 case 0x660f58: /* addpd */
7691 case 0xf20f58: /* addsd */
7692 case 0xf30f58: /* addss */
7693 case 0x0f59: /* mulps */
7694 case 0x660f59: /* mulpd */
7695 case 0xf20f59: /* mulsd */
7696 case 0xf30f59: /* mulss */
7697 case 0x0f5a: /* cvtps2pd */
7698 case 0x660f5a: /* cvtpd2ps */
7699 case 0xf20f5a: /* cvtsd2ss */
7700 case 0xf30f5a: /* cvtss2sd */
7701 case 0x0f5b: /* cvtdq2ps */
7702 case 0x660f5b: /* cvtps2dq */
7703 case 0xf30f5b: /* cvttps2dq */
7704 case 0x0f5c: /* subps */
7705 case 0x660f5c: /* subpd */
7706 case 0xf20f5c: /* subsd */
7707 case 0xf30f5c: /* subss */
7708 case 0x0f5d: /* minps */
7709 case 0x660f5d: /* minpd */
7710 case 0xf20f5d: /* minsd */
7711 case 0xf30f5d: /* minss */
7712 case 0x0f5e: /* divps */
7713 case 0x660f5e: /* divpd */
7714 case 0xf20f5e: /* divsd */
7715 case 0xf30f5e: /* divss */
7716 case 0x0f5f: /* maxps */
7717 case 0x660f5f: /* maxpd */
7718 case 0xf20f5f: /* maxsd */
7719 case 0xf30f5f: /* maxss */
7720 case 0x660f60: /* punpcklbw */
7721 case 0x660f61: /* punpcklwd */
7722 case 0x660f62: /* punpckldq */
7723 case 0x660f63: /* packsswb */
7724 case 0x660f64: /* pcmpgtb */
7725 case 0x660f65: /* pcmpgtw */
7726 case 0x660f66: /* pcmpgtd */
7727 case 0x660f67: /* packuswb */
7728 case 0x660f68: /* punpckhbw */
7729 case 0x660f69: /* punpckhwd */
7730 case 0x660f6a: /* punpckhdq */
7731 case 0x660f6b: /* packssdw */
7732 case 0x660f6c: /* punpcklqdq */
7733 case 0x660f6d: /* punpckhqdq */
7734 case 0x660f6e: /* movd */
7735 case 0x660f6f: /* movdqa */
7736 case 0xf30f6f: /* movdqu */
7737 case 0x660f70: /* pshufd */
7738 case 0xf20f70: /* pshuflw */
7739 case 0xf30f70: /* pshufhw */
7740 case 0x660f74: /* pcmpeqb */
7741 case 0x660f75: /* pcmpeqw */
7742 case 0x660f76: /* pcmpeqd */
7743 case 0x660f7c: /* haddpd */
7744 case 0xf20f7c: /* haddps */
7745 case 0x660f7d: /* hsubpd */
7746 case 0xf20f7d: /* hsubps */
7747 case 0xf30f7e: /* movq */
7748 case 0x0fc2: /* cmpps */
7749 case 0x660fc2: /* cmppd */
7750 case 0xf20fc2: /* cmpsd */
7751 case 0xf30fc2: /* cmpss */
7752 case 0x660fc4: /* pinsrw */
7753 case 0x0fc6: /* shufps */
7754 case 0x660fc6: /* shufpd */
7755 case 0x660fd0: /* addsubpd */
7756 case 0xf20fd0: /* addsubps */
7757 case 0x660fd1: /* psrlw */
7758 case 0x660fd2: /* psrld */
7759 case 0x660fd3: /* psrlq */
7760 case 0x660fd4: /* paddq */
7761 case 0x660fd5: /* pmullw */
7762 case 0xf30fd6: /* movq2dq */
7763 case 0x660fd8: /* psubusb */
7764 case 0x660fd9: /* psubusw */
7765 case 0x660fda: /* pminub */
7766 case 0x660fdb: /* pand */
7767 case 0x660fdc: /* paddusb */
7768 case 0x660fdd: /* paddusw */
7769 case 0x660fde: /* pmaxub */
7770 case 0x660fdf: /* pandn */
7771 case 0x660fe0: /* pavgb */
7772 case 0x660fe1: /* psraw */
7773 case 0x660fe2: /* psrad */
7774 case 0x660fe3: /* pavgw */
7775 case 0x660fe4: /* pmulhuw */
7776 case 0x660fe5: /* pmulhw */
7777 case 0x660fe6: /* cvttpd2dq */
7778 case 0xf20fe6: /* cvtpd2dq */
7779 case 0xf30fe6: /* cvtdq2pd */
7780 case 0x660fe8: /* psubsb */
7781 case 0x660fe9: /* psubsw */
7782 case 0x660fea: /* pminsw */
7783 case 0x660feb: /* por */
7784 case 0x660fec: /* paddsb */
7785 case 0x660fed: /* paddsw */
7786 case 0x660fee: /* pmaxsw */
7787 case 0x660fef: /* pxor */
7788 case 0xf20ff0: /* lddqu */
7789 case 0x660ff1: /* psllw */
7790 case 0x660ff2: /* pslld */
7791 case 0x660ff3: /* psllq */
7792 case 0x660ff4: /* pmuludq */
7793 case 0x660ff5: /* pmaddwd */
7794 case 0x660ff6: /* psadbw */
7795 case 0x660ff8: /* psubb */
7796 case 0x660ff9: /* psubw */
7797 case 0x660ffa: /* psubd */
7798 case 0x660ffb: /* psubq */
7799 case 0x660ffc: /* paddb */
7800 case 0x660ffd: /* paddw */
7801 case 0x660ffe: /* paddd */
7802 if (i386_record_modrm (&ir
))
7805 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7807 record_full_arch_list_add_reg (ir
.regcache
,
7808 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7809 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7813 case 0x0f11: /* movups */
7814 case 0x660f11: /* movupd */
7815 case 0xf30f11: /* movss */
7816 case 0xf20f11: /* movsd */
7817 case 0x0f13: /* movlps */
7818 case 0x660f13: /* movlpd */
7819 case 0x0f17: /* movhps */
7820 case 0x660f17: /* movhpd */
7821 case 0x0f29: /* movaps */
7822 case 0x660f29: /* movapd */
7823 case 0x660f3a14: /* pextrb */
7824 case 0x660f3a15: /* pextrw */
7825 case 0x660f3a16: /* pextrd pextrq */
7826 case 0x660f3a17: /* extractps */
7827 case 0x660f7f: /* movdqa */
7828 case 0xf30f7f: /* movdqu */
7829 if (i386_record_modrm (&ir
))
7833 if (opcode
== 0x0f13 || opcode
== 0x660f13
7834 || opcode
== 0x0f17 || opcode
== 0x660f17)
7837 if (!i386_xmm_regnum_p (gdbarch
,
7838 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7840 record_full_arch_list_add_reg (ir
.regcache
,
7841 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7863 if (i386_record_lea_modrm (&ir
))
7868 case 0x0f2b: /* movntps */
7869 case 0x660f2b: /* movntpd */
7870 case 0x0fe7: /* movntq */
7871 case 0x660fe7: /* movntdq */
7874 if (opcode
== 0x0fe7)
7878 if (i386_record_lea_modrm (&ir
))
7882 case 0xf30f2c: /* cvttss2si */
7883 case 0xf20f2c: /* cvttsd2si */
7884 case 0xf30f2d: /* cvtss2si */
7885 case 0xf20f2d: /* cvtsd2si */
7886 case 0xf20f38f0: /* crc32 */
7887 case 0xf20f38f1: /* crc32 */
7888 case 0x0f50: /* movmskps */
7889 case 0x660f50: /* movmskpd */
7890 case 0x0fc5: /* pextrw */
7891 case 0x660fc5: /* pextrw */
7892 case 0x0fd7: /* pmovmskb */
7893 case 0x660fd7: /* pmovmskb */
7894 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7897 case 0x0f3800: /* pshufb */
7898 case 0x0f3801: /* phaddw */
7899 case 0x0f3802: /* phaddd */
7900 case 0x0f3803: /* phaddsw */
7901 case 0x0f3804: /* pmaddubsw */
7902 case 0x0f3805: /* phsubw */
7903 case 0x0f3806: /* phsubd */
7904 case 0x0f3807: /* phsubsw */
7905 case 0x0f3808: /* psignb */
7906 case 0x0f3809: /* psignw */
7907 case 0x0f380a: /* psignd */
7908 case 0x0f380b: /* pmulhrsw */
7909 case 0x0f381c: /* pabsb */
7910 case 0x0f381d: /* pabsw */
7911 case 0x0f381e: /* pabsd */
7912 case 0x0f382b: /* packusdw */
7913 case 0x0f3830: /* pmovzxbw */
7914 case 0x0f3831: /* pmovzxbd */
7915 case 0x0f3832: /* pmovzxbq */
7916 case 0x0f3833: /* pmovzxwd */
7917 case 0x0f3834: /* pmovzxwq */
7918 case 0x0f3835: /* pmovzxdq */
7919 case 0x0f3837: /* pcmpgtq */
7920 case 0x0f3838: /* pminsb */
7921 case 0x0f3839: /* pminsd */
7922 case 0x0f383a: /* pminuw */
7923 case 0x0f383b: /* pminud */
7924 case 0x0f383c: /* pmaxsb */
7925 case 0x0f383d: /* pmaxsd */
7926 case 0x0f383e: /* pmaxuw */
7927 case 0x0f383f: /* pmaxud */
7928 case 0x0f3840: /* pmulld */
7929 case 0x0f3841: /* phminposuw */
7930 case 0x0f3a0f: /* palignr */
7931 case 0x0f60: /* punpcklbw */
7932 case 0x0f61: /* punpcklwd */
7933 case 0x0f62: /* punpckldq */
7934 case 0x0f63: /* packsswb */
7935 case 0x0f64: /* pcmpgtb */
7936 case 0x0f65: /* pcmpgtw */
7937 case 0x0f66: /* pcmpgtd */
7938 case 0x0f67: /* packuswb */
7939 case 0x0f68: /* punpckhbw */
7940 case 0x0f69: /* punpckhwd */
7941 case 0x0f6a: /* punpckhdq */
7942 case 0x0f6b: /* packssdw */
7943 case 0x0f6e: /* movd */
7944 case 0x0f6f: /* movq */
7945 case 0x0f70: /* pshufw */
7946 case 0x0f74: /* pcmpeqb */
7947 case 0x0f75: /* pcmpeqw */
7948 case 0x0f76: /* pcmpeqd */
7949 case 0x0fc4: /* pinsrw */
7950 case 0x0fd1: /* psrlw */
7951 case 0x0fd2: /* psrld */
7952 case 0x0fd3: /* psrlq */
7953 case 0x0fd4: /* paddq */
7954 case 0x0fd5: /* pmullw */
7955 case 0xf20fd6: /* movdq2q */
7956 case 0x0fd8: /* psubusb */
7957 case 0x0fd9: /* psubusw */
7958 case 0x0fda: /* pminub */
7959 case 0x0fdb: /* pand */
7960 case 0x0fdc: /* paddusb */
7961 case 0x0fdd: /* paddusw */
7962 case 0x0fde: /* pmaxub */
7963 case 0x0fdf: /* pandn */
7964 case 0x0fe0: /* pavgb */
7965 case 0x0fe1: /* psraw */
7966 case 0x0fe2: /* psrad */
7967 case 0x0fe3: /* pavgw */
7968 case 0x0fe4: /* pmulhuw */
7969 case 0x0fe5: /* pmulhw */
7970 case 0x0fe8: /* psubsb */
7971 case 0x0fe9: /* psubsw */
7972 case 0x0fea: /* pminsw */
7973 case 0x0feb: /* por */
7974 case 0x0fec: /* paddsb */
7975 case 0x0fed: /* paddsw */
7976 case 0x0fee: /* pmaxsw */
7977 case 0x0fef: /* pxor */
7978 case 0x0ff1: /* psllw */
7979 case 0x0ff2: /* pslld */
7980 case 0x0ff3: /* psllq */
7981 case 0x0ff4: /* pmuludq */
7982 case 0x0ff5: /* pmaddwd */
7983 case 0x0ff6: /* psadbw */
7984 case 0x0ff8: /* psubb */
7985 case 0x0ff9: /* psubw */
7986 case 0x0ffa: /* psubd */
7987 case 0x0ffb: /* psubq */
7988 case 0x0ffc: /* paddb */
7989 case 0x0ffd: /* paddw */
7990 case 0x0ffe: /* paddd */
7991 if (i386_record_modrm (&ir
))
7993 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7995 record_full_arch_list_add_reg (ir
.regcache
,
7996 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7999 case 0x0f71: /* psllw */
8000 case 0x0f72: /* pslld */
8001 case 0x0f73: /* psllq */
8002 if (i386_record_modrm (&ir
))
8004 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8006 record_full_arch_list_add_reg (ir
.regcache
,
8007 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8010 case 0x660f71: /* psllw */
8011 case 0x660f72: /* pslld */
8012 case 0x660f73: /* psllq */
8013 if (i386_record_modrm (&ir
))
8016 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8018 record_full_arch_list_add_reg (ir
.regcache
,
8019 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8022 case 0x0f7e: /* movd */
8023 case 0x660f7e: /* movd */
8024 if (i386_record_modrm (&ir
))
8027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8034 if (i386_record_lea_modrm (&ir
))
8039 case 0x0f7f: /* movq */
8040 if (i386_record_modrm (&ir
))
8044 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8046 record_full_arch_list_add_reg (ir
.regcache
,
8047 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8052 if (i386_record_lea_modrm (&ir
))
8057 case 0xf30fb8: /* popcnt */
8058 if (i386_record_modrm (&ir
))
8060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8061 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8064 case 0x660fd6: /* movq */
8065 if (i386_record_modrm (&ir
))
8070 if (!i386_xmm_regnum_p (gdbarch
,
8071 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8073 record_full_arch_list_add_reg (ir
.regcache
,
8074 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8079 if (i386_record_lea_modrm (&ir
))
8084 case 0x660f3817: /* ptest */
8085 case 0x0f2e: /* ucomiss */
8086 case 0x660f2e: /* ucomisd */
8087 case 0x0f2f: /* comiss */
8088 case 0x660f2f: /* comisd */
8089 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8092 case 0x0ff7: /* maskmovq */
8093 regcache_raw_read_unsigned (ir
.regcache
,
8094 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8096 if (record_full_arch_list_add_mem (addr
, 64))
8100 case 0x660ff7: /* maskmovdqu */
8101 regcache_raw_read_unsigned (ir
.regcache
,
8102 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8104 if (record_full_arch_list_add_mem (addr
, 128))
8119 /* In the future, maybe still need to deal with need_dasm. */
8120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8121 if (record_full_arch_list_add_end ())
8127 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8128 "at address %s.\n"),
8129 (unsigned int) (opcode
),
8130 paddress (gdbarch
, ir
.orig_addr
));
8134 static const int i386_record_regmap
[] =
8136 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8137 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8138 0, 0, 0, 0, 0, 0, 0, 0,
8139 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8140 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8143 /* Check that the given address appears suitable for a fast
8144 tracepoint, which on x86-64 means that we need an instruction of at
8145 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8146 jump and not have to worry about program jumps to an address in the
8147 middle of the tracepoint jump. On x86, it may be possible to use
8148 4-byte jumps with a 2-byte offset to a trampoline located in the
8149 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8150 of instruction to replace, and 0 if not, plus an explanatory
8154 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8159 /* Ask the target for the minimum instruction length supported. */
8160 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8164 /* If the target does not support the get_min_fast_tracepoint_insn_len
8165 operation, assume that fast tracepoints will always be implemented
8166 using 4-byte relative jumps on both x86 and x86-64. */
8169 else if (jumplen
== 0)
8171 /* If the target does support get_min_fast_tracepoint_insn_len but
8172 returns zero, then the IPA has not loaded yet. In this case,
8173 we optimistically assume that truncated 2-byte relative jumps
8174 will be available on x86, and compensate later if this assumption
8175 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8176 jumps will always be used. */
8177 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8180 /* Check for fit. */
8181 len
= gdb_insn_length (gdbarch
, addr
);
8185 /* Return a bit of target-specific detail to add to the caller's
8186 generic failure message. */
8188 *msg
= string_printf (_("; instruction is only %d bytes long, "
8189 "need at least %d bytes for the jump"),
8201 /* Return a floating-point format for a floating-point variable of
8202 length LEN in bits. If non-NULL, NAME is the name of its type.
8203 If no suitable type is found, return NULL. */
8205 static const struct floatformat
**
8206 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8207 const char *name
, int len
)
8209 if (len
== 128 && name
)
8210 if (strcmp (name
, "__float128") == 0
8211 || strcmp (name
, "_Float128") == 0
8212 || strcmp (name
, "complex _Float128") == 0
8213 || strcmp (name
, "complex(kind=16)") == 0
8214 || strcmp (name
, "quad complex") == 0
8215 || strcmp (name
, "real(kind=16)") == 0
8216 || strcmp (name
, "real*16") == 0)
8217 return floatformats_ia64_quad
;
8219 return default_floatformat_for_type (gdbarch
, name
, len
);
8223 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8224 struct tdesc_arch_data
*tdesc_data
)
8226 const struct target_desc
*tdesc
= tdep
->tdesc
;
8227 const struct tdesc_feature
*feature_core
;
8229 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8230 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8231 int i
, num_regs
, valid_p
;
8233 if (! tdesc_has_registers (tdesc
))
8236 /* Get core registers. */
8237 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8238 if (feature_core
== NULL
)
8241 /* Get SSE registers. */
8242 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8244 /* Try AVX registers. */
8245 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8247 /* Try MPX registers. */
8248 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8250 /* Try AVX512 registers. */
8251 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8253 /* Try segment base registers. */
8254 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8257 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8261 /* The XCR0 bits. */
8264 /* AVX512 register description requires AVX register description. */
8268 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8270 /* It may have been set by OSABI initialization function. */
8271 if (tdep
->k0_regnum
< 0)
8273 tdep
->k_register_names
= i386_k_names
;
8274 tdep
->k0_regnum
= I386_K0_REGNUM
;
8277 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8278 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8279 tdep
->k0_regnum
+ i
,
8282 if (tdep
->num_zmm_regs
== 0)
8284 tdep
->zmmh_register_names
= i386_zmmh_names
;
8285 tdep
->num_zmm_regs
= 8;
8286 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8289 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8290 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8291 tdep
->zmm0h_regnum
+ i
,
8292 tdep
->zmmh_register_names
[i
]);
8294 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8295 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8296 tdep
->xmm16_regnum
+ i
,
8297 tdep
->xmm_avx512_register_names
[i
]);
8299 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8300 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8301 tdep
->ymm16h_regnum
+ i
,
8302 tdep
->ymm16h_register_names
[i
]);
8306 /* AVX register description requires SSE register description. */
8310 if (!feature_avx512
)
8311 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8313 /* It may have been set by OSABI initialization function. */
8314 if (tdep
->num_ymm_regs
== 0)
8316 tdep
->ymmh_register_names
= i386_ymmh_names
;
8317 tdep
->num_ymm_regs
= 8;
8318 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8321 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8322 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8323 tdep
->ymm0h_regnum
+ i
,
8324 tdep
->ymmh_register_names
[i
]);
8326 else if (feature_sse
)
8327 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8330 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8331 tdep
->num_xmm_regs
= 0;
8334 num_regs
= tdep
->num_core_regs
;
8335 for (i
= 0; i
< num_regs
; i
++)
8336 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8337 tdep
->register_names
[i
]);
8341 /* Need to include %mxcsr, so add one. */
8342 num_regs
+= tdep
->num_xmm_regs
+ 1;
8343 for (; i
< num_regs
; i
++)
8344 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8345 tdep
->register_names
[i
]);
8350 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8352 if (tdep
->bnd0r_regnum
< 0)
8354 tdep
->mpx_register_names
= i386_mpx_names
;
8355 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8356 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8359 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8360 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8361 I387_BND0R_REGNUM (tdep
) + i
,
8362 tdep
->mpx_register_names
[i
]);
8365 if (feature_segments
)
8367 if (tdep
->fsbase_regnum
< 0)
8368 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8369 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8370 tdep
->fsbase_regnum
, "fs_base");
8371 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8372 tdep
->fsbase_regnum
+ 1, "gs_base");
8377 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8378 if (tdep
->pkru_regnum
< 0)
8380 tdep
->pkeys_register_names
= i386_pkeys_names
;
8381 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8382 tdep
->num_pkeys_regs
= 1;
8385 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8386 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8387 I387_PKRU_REGNUM (tdep
) + i
,
8388 tdep
->pkeys_register_names
[i
]);
8396 /* Implement the type_align gdbarch function. */
8399 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8401 type
= check_typedef (type
);
8403 if (gdbarch_ptr_bit (gdbarch
) == 32)
8405 if ((type
->code () == TYPE_CODE_INT
8406 || type
->code () == TYPE_CODE_FLT
)
8407 && TYPE_LENGTH (type
) > 4)
8410 /* Handle x86's funny long double. */
8411 if (type
->code () == TYPE_CODE_FLT
8412 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8420 /* Note: This is called for both i386 and amd64. */
8422 static struct gdbarch
*
8423 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8425 struct gdbarch_tdep
*tdep
;
8426 struct gdbarch
*gdbarch
;
8427 struct tdesc_arch_data
*tdesc_data
;
8428 const struct target_desc
*tdesc
;
8434 /* If there is already a candidate, use it. */
8435 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8437 return arches
->gdbarch
;
8439 /* Allocate space for the new architecture. Assume i386 for now. */
8440 tdep
= XCNEW (struct gdbarch_tdep
);
8441 gdbarch
= gdbarch_alloc (&info
, tdep
);
8443 /* General-purpose registers. */
8444 tdep
->gregset_reg_offset
= NULL
;
8445 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8446 tdep
->sizeof_gregset
= 0;
8448 /* Floating-point registers. */
8449 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8450 tdep
->fpregset
= &i386_fpregset
;
8452 /* The default settings include the FPU registers, the MMX registers
8453 and the SSE registers. This can be overridden for a specific ABI
8454 by adjusting the members `st0_regnum', `mm0_regnum' and
8455 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8456 will show up in the output of "info all-registers". */
8458 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8460 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8461 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8463 tdep
->jb_pc_offset
= -1;
8464 tdep
->struct_return
= pcc_struct_return
;
8465 tdep
->sigtramp_start
= 0;
8466 tdep
->sigtramp_end
= 0;
8467 tdep
->sigtramp_p
= i386_sigtramp_p
;
8468 tdep
->sigcontext_addr
= NULL
;
8469 tdep
->sc_reg_offset
= NULL
;
8470 tdep
->sc_pc_offset
= -1;
8471 tdep
->sc_sp_offset
= -1;
8473 tdep
->xsave_xcr0_offset
= -1;
8475 tdep
->record_regmap
= i386_record_regmap
;
8477 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8479 /* The format used for `long double' on almost all i386 targets is
8480 the i387 extended floating-point format. In fact, of all targets
8481 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8482 on having a `long double' that's not `long' at all. */
8483 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8485 /* Although the i387 extended floating-point has only 80 significant
8486 bits, a `long double' actually takes up 96, probably to enforce
8488 set_gdbarch_long_double_bit (gdbarch
, 96);
8490 /* Support for floating-point data type variants. */
8491 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8493 /* Register numbers of various important registers. */
8494 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8495 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8496 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8497 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8499 /* NOTE: kettenis/20040418: GCC does have two possible register
8500 numbering schemes on the i386: dbx and SVR4. These schemes
8501 differ in how they number %ebp, %esp, %eflags, and the
8502 floating-point registers, and are implemented by the arrays
8503 dbx_register_map[] and svr4_dbx_register_map in
8504 gcc/config/i386.c. GCC also defines a third numbering scheme in
8505 gcc/config/i386.c, which it designates as the "default" register
8506 map used in 64bit mode. This last register numbering scheme is
8507 implemented in dbx64_register_map, and is used for AMD64; see
8510 Currently, each GCC i386 target always uses the same register
8511 numbering scheme across all its supported debugging formats
8512 i.e. SDB (COFF), stabs and DWARF 2. This is because
8513 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8514 DBX_REGISTER_NUMBER macro which is defined by each target's
8515 respective config header in a manner independent of the requested
8516 output debugging format.
8518 This does not match the arrangement below, which presumes that
8519 the SDB and stabs numbering schemes differ from the DWARF and
8520 DWARF 2 ones. The reason for this arrangement is that it is
8521 likely to get the numbering scheme for the target's
8522 default/native debug format right. For targets where GCC is the
8523 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8524 targets where the native toolchain uses a different numbering
8525 scheme for a particular debug format (stabs-in-ELF on Solaris)
8526 the defaults below will have to be overridden, like
8527 i386_elf_init_abi() does. */
8529 /* Use the dbx register numbering scheme for stabs and COFF. */
8530 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8531 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8533 /* Use the SVR4 register numbering scheme for DWARF 2. */
8534 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8536 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8537 be in use on any of the supported i386 targets. */
8539 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8541 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8543 /* Call dummy code. */
8544 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8545 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8546 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8547 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8549 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8550 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8551 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8553 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8555 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8557 /* Stack grows downward. */
8558 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8560 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8561 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8563 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8564 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8566 set_gdbarch_frame_args_skip (gdbarch
, 8);
8568 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8570 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8572 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8574 /* Add the i386 register groups. */
8575 i386_add_reggroups (gdbarch
);
8576 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8578 /* Helper for function argument information. */
8579 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8581 /* Hook the function epilogue frame unwinder. This unwinder is
8582 appended to the list first, so that it supercedes the DWARF
8583 unwinder in function epilogues (where the DWARF unwinder
8584 currently fails). */
8585 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8587 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8588 to the list before the prologue-based unwinders, so that DWARF
8589 CFI info will be used if it is available. */
8590 dwarf2_append_unwinders (gdbarch
);
8592 frame_base_set_default (gdbarch
, &i386_frame_base
);
8594 /* Pseudo registers may be changed by amd64_init_abi. */
8595 set_gdbarch_pseudo_register_read_value (gdbarch
,
8596 i386_pseudo_register_read_value
);
8597 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8598 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8599 i386_ax_pseudo_register_collect
);
8601 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8602 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8604 /* Override the normal target description method to make the AVX
8605 upper halves anonymous. */
8606 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8608 /* Even though the default ABI only includes general-purpose registers,
8609 floating-point registers and the SSE registers, we have to leave a
8610 gap for the upper AVX, MPX and AVX512 registers. */
8611 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8613 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8615 /* Get the x86 target description from INFO. */
8616 tdesc
= info
.target_desc
;
8617 if (! tdesc_has_registers (tdesc
))
8618 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8619 tdep
->tdesc
= tdesc
;
8621 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8622 tdep
->register_names
= i386_register_names
;
8624 /* No upper YMM registers. */
8625 tdep
->ymmh_register_names
= NULL
;
8626 tdep
->ymm0h_regnum
= -1;
8628 /* No upper ZMM registers. */
8629 tdep
->zmmh_register_names
= NULL
;
8630 tdep
->zmm0h_regnum
= -1;
8632 /* No high XMM registers. */
8633 tdep
->xmm_avx512_register_names
= NULL
;
8634 tdep
->xmm16_regnum
= -1;
8636 /* No upper YMM16-31 registers. */
8637 tdep
->ymm16h_register_names
= NULL
;
8638 tdep
->ymm16h_regnum
= -1;
8640 tdep
->num_byte_regs
= 8;
8641 tdep
->num_word_regs
= 8;
8642 tdep
->num_dword_regs
= 0;
8643 tdep
->num_mmx_regs
= 8;
8644 tdep
->num_ymm_regs
= 0;
8646 /* No MPX registers. */
8647 tdep
->bnd0r_regnum
= -1;
8648 tdep
->bndcfgu_regnum
= -1;
8650 /* No AVX512 registers. */
8651 tdep
->k0_regnum
= -1;
8652 tdep
->num_zmm_regs
= 0;
8653 tdep
->num_ymm_avx512_regs
= 0;
8654 tdep
->num_xmm_avx512_regs
= 0;
8656 /* No PKEYS registers */
8657 tdep
->pkru_regnum
= -1;
8658 tdep
->num_pkeys_regs
= 0;
8660 /* No segment base registers. */
8661 tdep
->fsbase_regnum
= -1;
8663 tdesc_data
= tdesc_data_alloc ();
8665 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8667 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8669 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8670 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8671 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8673 /* Hook in ABI-specific overrides, if they have been registered.
8674 Note: If INFO specifies a 64 bit arch, this is where we turn
8675 a 32-bit i386 into a 64-bit amd64. */
8676 info
.tdesc_data
= tdesc_data
;
8677 gdbarch_init_osabi (info
, gdbarch
);
8679 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8681 tdesc_data_cleanup (tdesc_data
);
8683 gdbarch_free (gdbarch
);
8687 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8689 /* Wire in pseudo registers. Number of pseudo registers may be
8691 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8692 + tdep
->num_word_regs
8693 + tdep
->num_dword_regs
8694 + tdep
->num_mmx_regs
8695 + tdep
->num_ymm_regs
8697 + tdep
->num_ymm_avx512_regs
8698 + tdep
->num_zmm_regs
));
8700 /* Target description may be changed. */
8701 tdesc
= tdep
->tdesc
;
8703 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8705 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8706 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8708 /* Make %al the first pseudo-register. */
8709 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8710 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8712 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8713 if (tdep
->num_dword_regs
)
8715 /* Support dword pseudo-register if it hasn't been disabled. */
8716 tdep
->eax_regnum
= ymm0_regnum
;
8717 ymm0_regnum
+= tdep
->num_dword_regs
;
8720 tdep
->eax_regnum
= -1;
8722 mm0_regnum
= ymm0_regnum
;
8723 if (tdep
->num_ymm_regs
)
8725 /* Support YMM pseudo-register if it is available. */
8726 tdep
->ymm0_regnum
= ymm0_regnum
;
8727 mm0_regnum
+= tdep
->num_ymm_regs
;
8730 tdep
->ymm0_regnum
= -1;
8732 if (tdep
->num_ymm_avx512_regs
)
8734 /* Support YMM16-31 pseudo registers if available. */
8735 tdep
->ymm16_regnum
= mm0_regnum
;
8736 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8739 tdep
->ymm16_regnum
= -1;
8741 if (tdep
->num_zmm_regs
)
8743 /* Support ZMM pseudo-register if it is available. */
8744 tdep
->zmm0_regnum
= mm0_regnum
;
8745 mm0_regnum
+= tdep
->num_zmm_regs
;
8748 tdep
->zmm0_regnum
= -1;
8750 bnd0_regnum
= mm0_regnum
;
8751 if (tdep
->num_mmx_regs
!= 0)
8753 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8754 tdep
->mm0_regnum
= mm0_regnum
;
8755 bnd0_regnum
+= tdep
->num_mmx_regs
;
8758 tdep
->mm0_regnum
= -1;
8760 if (tdep
->bnd0r_regnum
> 0)
8761 tdep
->bnd0_regnum
= bnd0_regnum
;
8763 tdep
-> bnd0_regnum
= -1;
8765 /* Hook in the legacy prologue-based unwinders last (fallback). */
8766 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8767 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8768 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8770 /* If we have a register mapping, enable the generic core file
8771 support, unless it has already been enabled. */
8772 if (tdep
->gregset_reg_offset
8773 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8774 set_gdbarch_iterate_over_regset_sections
8775 (gdbarch
, i386_iterate_over_regset_sections
);
8777 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8778 i386_fast_tracepoint_valid_at
);
8785 /* Return the target description for a specified XSAVE feature mask. */
8787 const struct target_desc
*
8788 i386_target_description (uint64_t xcr0
, bool segments
)
8790 static target_desc
*i386_tdescs \
8791 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8792 target_desc
**tdesc
;
8794 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8795 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8796 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8797 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8798 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8802 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8807 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8809 /* Find the bound directory base address. */
8811 static unsigned long
8812 i386_mpx_bd_base (void)
8814 struct regcache
*rcache
;
8815 struct gdbarch_tdep
*tdep
;
8817 enum register_status regstatus
;
8819 rcache
= get_current_regcache ();
8820 tdep
= gdbarch_tdep (rcache
->arch ());
8822 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8824 if (regstatus
!= REG_VALID
)
8825 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8827 return ret
& MPX_BASE_MASK
;
8831 i386_mpx_enabled (void)
8833 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8834 const struct target_desc
*tdesc
= tdep
->tdesc
;
8836 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8839 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8840 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8841 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8842 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8844 /* Find the bound table entry given the pointer location and the base
8845 address of the table. */
8848 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8852 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8853 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8854 CORE_ADDR bd_entry_addr
;
8857 struct gdbarch
*gdbarch
= get_current_arch ();
8858 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8861 if (gdbarch_ptr_bit (gdbarch
) == 64)
8863 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8864 bd_ptr_r_shift
= 20;
8866 bt_select_r_shift
= 3;
8867 bt_select_l_shift
= 5;
8868 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8870 if ( sizeof (CORE_ADDR
) == 4)
8871 error (_("bound table examination not supported\
8872 for 64-bit process with 32-bit GDB"));
8876 mpx_bd_mask
= MPX_BD_MASK_32
;
8877 bd_ptr_r_shift
= 12;
8879 bt_select_r_shift
= 2;
8880 bt_select_l_shift
= 4;
8881 bt_mask
= MPX_BT_MASK_32
;
8884 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8885 bd_entry_addr
= bd_base
+ offset1
;
8886 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8888 if ((bd_entry
& 0x1) == 0)
8889 error (_("Invalid bounds directory entry at %s."),
8890 paddress (get_current_arch (), bd_entry_addr
));
8892 /* Clearing status bit. */
8894 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8895 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8897 return bt_addr
+ offset2
;
8900 /* Print routine for the mpx bounds. */
8903 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8905 struct ui_out
*uiout
= current_uiout
;
8907 struct gdbarch
*gdbarch
= get_current_arch ();
8908 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8909 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8911 if (bounds_in_map
== 1)
8913 uiout
->text ("Null bounds on map:");
8914 uiout
->text (" pointer value = ");
8915 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8921 uiout
->text ("{lbound = ");
8922 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8923 uiout
->text (", ubound = ");
8925 /* The upper bound is stored in 1's complement. */
8926 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8927 uiout
->text ("}: pointer value = ");
8928 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8930 if (gdbarch_ptr_bit (gdbarch
) == 64)
8931 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8933 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8935 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8936 -1 represents in this sense full memory access, and there is no need
8939 size
= (size
> -1 ? size
+ 1 : size
);
8940 uiout
->text (", size = ");
8941 uiout
->field_string ("size", plongest (size
));
8943 uiout
->text (", metadata = ");
8944 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8949 /* Implement the command "show mpx bound". */
8952 i386_mpx_info_bounds (const char *args
, int from_tty
)
8954 CORE_ADDR bd_base
= 0;
8956 CORE_ADDR bt_entry_addr
= 0;
8957 CORE_ADDR bt_entry
[4];
8959 struct gdbarch
*gdbarch
= get_current_arch ();
8960 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8962 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8963 || !i386_mpx_enabled ())
8965 printf_unfiltered (_("Intel Memory Protection Extensions not "
8966 "supported on this target.\n"));
8972 printf_unfiltered (_("Address of pointer variable expected.\n"));
8976 addr
= parse_and_eval_address (args
);
8978 bd_base
= i386_mpx_bd_base ();
8979 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8981 memset (bt_entry
, 0, sizeof (bt_entry
));
8983 for (i
= 0; i
< 4; i
++)
8984 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8985 + i
* TYPE_LENGTH (data_ptr_type
),
8988 i386_mpx_print_bounds (bt_entry
);
8991 /* Implement the command "set mpx bound". */
8994 i386_mpx_set_bounds (const char *args
, int from_tty
)
8996 CORE_ADDR bd_base
= 0;
8997 CORE_ADDR addr
, lower
, upper
;
8998 CORE_ADDR bt_entry_addr
= 0;
8999 CORE_ADDR bt_entry
[2];
9000 const char *input
= args
;
9002 struct gdbarch
*gdbarch
= get_current_arch ();
9003 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9004 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9006 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
9007 || !i386_mpx_enabled ())
9008 error (_("Intel Memory Protection Extensions not supported\
9012 error (_("Pointer value expected."));
9014 addr
= value_as_address (parse_to_comma_and_eval (&input
));
9016 if (input
[0] == ',')
9018 if (input
[0] == '\0')
9019 error (_("wrong number of arguments: missing lower and upper bound."));
9020 lower
= value_as_address (parse_to_comma_and_eval (&input
));
9022 if (input
[0] == ',')
9024 if (input
[0] == '\0')
9025 error (_("Wrong number of arguments; Missing upper bound."));
9026 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9028 bd_base
= i386_mpx_bd_base ();
9029 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9030 for (i
= 0; i
< 2; i
++)
9031 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9032 + i
* TYPE_LENGTH (data_ptr_type
),
9034 bt_entry
[0] = (uint64_t) lower
;
9035 bt_entry
[1] = ~(uint64_t) upper
;
9037 for (i
= 0; i
< 2; i
++)
9038 write_memory_unsigned_integer (bt_entry_addr
9039 + i
* TYPE_LENGTH (data_ptr_type
),
9040 TYPE_LENGTH (data_ptr_type
), byte_order
,
9044 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9046 void _initialize_i386_tdep ();
9048 _initialize_i386_tdep ()
9050 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
9052 /* Add the variable that controls the disassembly flavor. */
9053 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9054 &disassembly_flavor
, _("\
9055 Set the disassembly flavor."), _("\
9056 Show the disassembly flavor."), _("\
9057 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9059 NULL
, /* FIXME: i18n: */
9060 &setlist
, &showlist
);
9062 /* Add the variable that controls the convention for returning
9064 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9065 &struct_convention
, _("\
9066 Set the convention for returning small structs."), _("\
9067 Show the convention for returning small structs."), _("\
9068 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9071 NULL
, /* FIXME: i18n: */
9072 &setlist
, &showlist
);
9074 /* Add "mpx" prefix for the set commands. */
9076 add_basic_prefix_cmd ("mpx", class_support
, _("\
9077 Set Intel Memory Protection Extensions specific variables."),
9078 &mpx_set_cmdlist
, "set mpx ",
9079 0 /* allow-unknown */, &setlist
);
9081 /* Add "mpx" prefix for the show commands. */
9083 add_show_prefix_cmd ("mpx", class_support
, _("\
9084 Show Intel Memory Protection Extensions specific variables."),
9085 &mpx_show_cmdlist
, "show mpx ",
9086 0 /* allow-unknown */, &showlist
);
9088 /* Add "bound" command for the show mpx commands list. */
9090 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9091 "Show the memory bounds for a given array/pointer storage\
9092 in the bound table.",
9095 /* Add "bound" command for the set mpx commands list. */
9097 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9098 "Set the memory bounds for a given array/pointer storage\
9099 in the bound table.",
9102 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9103 i386_svr4_init_abi
);
9105 /* Initialize the i386-specific register groups. */
9106 i386_init_reggroups ();
9108 /* Tell remote stub that we support XML target description. */
9109 register_remote_support_xml ("i386");