1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names
[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names
[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names
[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names
[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names
[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
130 int mm0_regnum
= tdep
->mm0_regnum
;
135 regnum
-= mm0_regnum
;
136 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
142 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
146 regnum
-= tdep
->al_regnum
;
147 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
153 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 regnum
-= tdep
->ax_regnum
;
158 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int eax_regnum
= tdep
->eax_regnum
;
172 regnum
-= eax_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
177 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
180 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
182 if (ymm0h_regnum
< 0)
185 regnum
-= ymm0h_regnum
;
186 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
192 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 int ymm0_regnum
= tdep
->ymm0_regnum
;
200 regnum
-= ymm0_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
207 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
212 if (num_xmm_regs
== 0)
215 regnum
-= I387_XMM0_REGNUM (tdep
);
216 return regnum
>= 0 && regnum
< num_xmm_regs
;
220 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 if (I387_NUM_XMM_REGS (tdep
) == 0)
227 return (regnum
== I387_MXCSR_REGNUM (tdep
));
233 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 if (I387_ST0_REGNUM (tdep
) < 0)
240 return (I387_ST0_REGNUM (tdep
) <= regnum
241 && regnum
< I387_FCTRL_REGNUM (tdep
));
245 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 if (I387_ST0_REGNUM (tdep
) < 0)
252 return (I387_FCTRL_REGNUM (tdep
) <= regnum
253 && regnum
< I387_XMM0_REGNUM (tdep
));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
266 return tdesc_register_name (gdbarch
, regnum
);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
276 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
278 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
279 else if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return i386_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_word_regnum_p (gdbarch
, regnum
))
282 return i386_word_names
[regnum
- tdep
->ax_regnum
];
284 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg
>= 0 && reg
<= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg
>= 12 && reg
<= 19)
310 /* Floating-point registers. */
311 return reg
- 12 + I387_ST0_REGNUM (tdep
);
313 else if (reg
>= 21 && reg
<= 28)
316 int ymm0_regnum
= tdep
->ymm0_regnum
;
319 && i386_xmm_regnum_p (gdbarch
, reg
))
320 return reg
- 21 + ymm0_regnum
;
322 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
324 else if (reg
>= 29 && reg
<= 36)
327 return reg
- 29 + I387_MM0_REGNUM (tdep
);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg
>= 0 && reg
<= 9)
349 /* General-purpose registers. */
352 else if (reg
>= 11 && reg
<= 18)
354 /* Floating-point registers. */
355 return reg
- 11 + I387_ST0_REGNUM (tdep
);
357 else if (reg
>= 21 && reg
<= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
365 case 37: return I387_FCTRL_REGNUM (tdep
);
366 case 38: return I387_FSTAT_REGNUM (tdep
);
367 case 39: return I387_MXCSR_REGNUM (tdep
);
368 case 40: return I386_ES_REGNUM
;
369 case 41: return I386_CS_REGNUM
;
370 case 42: return I386_SS_REGNUM
;
371 case 43: return I386_DS_REGNUM
;
372 case 44: return I386_FS_REGNUM
;
373 case 45: return I386_GS_REGNUM
;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor
[] = "att";
385 static const char intel_flavor
[] = "intel";
386 static const char *const valid_flavors
[] =
392 static const char *disassembly_flavor
= att_flavor
;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte
*
407 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
409 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
411 *len
= sizeof (break_insn
);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
426 gdb_byte
*end
= insn
+ max_len
;
432 case DATA_PREFIX_OPCODE
:
433 case ADDR_PREFIX_OPCODE
:
434 case CS_PREFIX_OPCODE
:
435 case DS_PREFIX_OPCODE
:
436 case ES_PREFIX_OPCODE
:
437 case FS_PREFIX_OPCODE
:
438 case GS_PREFIX_OPCODE
:
439 case SS_PREFIX_OPCODE
:
440 case LOCK_PREFIX_OPCODE
:
441 case REPE_PREFIX_OPCODE
:
442 case REPNE_PREFIX_OPCODE
:
454 i386_absolute_jmp_p (const gdb_byte
*insn
)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn
[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn
[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte
*insn
)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn
[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn
[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte
*insn
)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte
*insn
)
515 if (i386_absolute_call_p (insn
))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
531 /* Is it 'int $0x80'? */
532 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn
[0] == 0x0f && insn
[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn
[0] == 0x0f && insn
[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure
*
549 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
550 CORE_ADDR from
, CORE_ADDR to
,
551 struct regcache
*regs
)
553 size_t len
= gdbarch_max_insn_length (gdbarch
);
554 gdb_byte
*buf
= xmalloc (len
);
556 read_memory (from
, buf
, len
);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn
= i386_skip_prefixes (buf
, len
);
566 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
567 insn
[syscall_length
] = NOP_OPCODE
;
570 write_memory (to
, buf
, len
);
574 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
575 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
576 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
579 return (struct displaced_step_closure
*) buf
;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
587 struct displaced_step_closure
*closure
,
588 CORE_ADDR from
, CORE_ADDR to
,
589 struct regcache
*regs
)
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset
= to
- from
;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte
*insn
= (gdb_byte
*) closure
;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte
*insn_start
= insn
;
606 fprintf_unfiltered (gdb_stdlog
,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
623 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn
)
636 && ! i386_absolute_call_p (insn
)
637 && ! i386_ret_p (insn
))
642 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn
, &insn_len
)
659 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
667 fprintf_unfiltered (gdb_stdlog
,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
682 fprintf_unfiltered (gdb_stdlog
,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch
, orig_eip
),
686 paddress (gdbarch
, eip
));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn
))
702 const ULONGEST retaddr_len
= 4;
704 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
705 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
706 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
707 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
710 fprintf_unfiltered (gdb_stdlog
,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch
, esp
),
713 paddress (gdbarch
, retaddr
));
718 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
720 target_write_memory (*to
, buf
, len
);
725 i386_relocate_instruction (struct gdbarch
*gdbarch
,
726 CORE_ADDR
*to
, CORE_ADDR oldloc
)
728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
729 gdb_byte buf
[I386_MAX_INSN_LEN
];
730 int offset
= 0, rel32
, newrel
;
732 gdb_byte
*insn
= buf
;
734 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
736 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
737 I386_MAX_INSN_LEN
, oldloc
);
739 /* Get past the prefixes. */
740 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf
[16];
748 unsigned int ret_addr
;
750 /* Where "ret" in the original code will return to. */
751 ret_addr
= oldloc
+ insn_length
;
752 push_buf
[0] = 0x68; /* pushq $... */
753 memcpy (&push_buf
[1], &ret_addr
, 4);
755 append_insns (to
, 5, push_buf
);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
762 newrel
= (oldloc
- *to
) + rel32
;
763 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
766 fprintf_unfiltered (gdb_stdlog
,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32
), paddress (gdbarch
, oldloc
),
770 hex_string (newrel
), paddress (gdbarch
, *to
));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to
, 5, insn
);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
787 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
788 newrel
= (oldloc
- *to
) + rel32
;
789 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
791 fprintf_unfiltered (gdb_stdlog
,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32
), paddress (gdbarch
, oldloc
),
795 hex_string (newrel
), paddress (gdbarch
, *to
));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to
, insn_length
, buf
);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache
*
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache
*cache
;
842 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
847 cache
->sp_offset
= -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
853 cache
->saved_regs
[i
] = -1;
855 cache
->saved_sp_reg
= -1;
856 cache
->pc_in_eax
= 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 if (target_read_memory (pc
, &op
, 1))
881 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
892 /* Include the size of the jmp instruction (including the
898 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
923 struct i386_frame_cache
*cache
)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc
<= pc
)
943 if (target_read_memory (pc
, &op
, 1))
946 if (op
!= 0x58) /* popl %eax */
949 if (target_read_memory (pc
+ 1, buf
, 4))
952 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
955 if (current_pc
== pc
)
957 cache
->sp_offset
+= 4;
961 if (current_pc
== pc
+ 1)
963 cache
->pc_in_eax
= 1;
967 if (buf
[1] == proto1
[1])
974 i386_skip_probe (CORE_ADDR pc
)
976 /* A function may start with
990 if (target_read_memory (pc
, &op
, 1))
993 if (op
== 0x68 || op
== 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1007 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1008 pc
+= delta
+ sizeof (buf
);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1022 struct i386_frame_cache
*cache
)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset
, offset_and
;
1049 static int regnums
[8] = {
1050 I386_EAX_REGNUM
, /* %eax */
1051 I386_ECX_REGNUM
, /* %ecx */
1052 I386_EDX_REGNUM
, /* %edx */
1053 I386_EBX_REGNUM
, /* %ebx */
1054 I386_ESP_REGNUM
, /* %esp */
1055 I386_EBP_REGNUM
, /* %ebp */
1056 I386_ESI_REGNUM
, /* %esi */
1057 I386_EDI_REGNUM
/* %edi */
1060 if (target_read_memory (pc
, buf
, sizeof buf
))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg
= (buf
[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf
[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf
[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg
!= ((buf
[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg
== 4 || reg
== 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf
[offset
+ 1] != 0xe4
1107 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1110 offset_and
= offset
;
1111 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf
[offset
] != 0xff
1116 || buf
[offset
+ 2] != 0xfc
1117 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg
!= (buf
[offset
+ 1] & 7))
1125 if (current_pc
> pc
+ offset_and
)
1126 cache
->saved_sp_reg
= regnums
[reg
];
1128 return min (pc
+ offset
+ 3, current_pc
);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1139 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1149 if (target_read_memory (pc
, &op
, 1))
1152 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1154 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1155 int insn_matched
= 1;
1158 gdb_assert (pattern
.len
> 1);
1159 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1161 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1164 for (i
= 1; i
< pattern
.len
; i
++)
1166 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1169 return insn_matched
;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn
*
1179 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1181 struct i386_insn
*pattern
;
1183 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1185 if (i386_match_pattern (pc
, *pattern
))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1198 CORE_ADDR current_pc
;
1200 struct i386_insn
*insn
;
1202 insn
= i386_match_insn (pc
, insn_patterns
);
1207 ix
= insn
- insn_patterns
;
1208 for (i
= ix
- 1; i
>= 0; i
--)
1210 current_pc
-= insn_patterns
[i
].len
;
1212 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1216 current_pc
= pc
+ insn
->len
;
1217 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1219 if (!i386_match_pattern (current_pc
, *insn
))
1222 current_pc
+= insn
->len
;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns
[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc
)
1291 if (target_read_memory (pc
, &op
, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc
, &op
, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op
== 0x8b)
1318 if (target_read_memory (pc
+ 1, &op
, 1))
1324 if (target_read_memory (pc
, &op
, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1341 CORE_ADDR pc
, CORE_ADDR limit
,
1342 struct i386_frame_cache
*cache
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1345 struct i386_insn
*insn
;
1352 if (target_read_memory (pc
, &op
, 1))
1355 if (op
== 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1360 cache
->sp_offset
+= 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc
+ skip
< limit
)
1377 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1384 /* If that's all, return now. */
1385 if (limit
<= pc
+ skip
)
1388 if (target_read_memory (pc
+ skip
, &op
, 1))
1391 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1395 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1400 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1408 /* OK, we actually have a frame. We just don't know how large
1409 it is yet. Set its size to zero. We'll adjust it if
1410 necessary. We also now commit to skipping the special
1411 instructions mentioned before. */
1415 /* If that's all, return now. */
1419 /* Check for stack adjustment
1423 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1424 reg, so we don't have to worry about a data16 prefix. */
1425 if (target_read_memory (pc
, &op
, 1))
1429 /* `subl' with 8-bit immediate. */
1430 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1431 /* Some instruction starting with 0x83 other than `subl'. */
1434 /* `subl' with signed 8-bit immediate (though it wouldn't
1435 make sense to be negative). */
1436 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1439 else if (op
== 0x81)
1441 /* Maybe it is `subl' with a 32-bit immediate. */
1442 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1443 /* Some instruction starting with 0x81 other than `subl'. */
1446 /* It is `subl' with a 32-bit immediate. */
1447 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1452 /* Some instruction other than `subl'. */
1456 else if (op
== 0xc8) /* enter */
1458 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1465 /* Check whether PC points at code that saves registers on the stack.
1466 If so, it updates CACHE and returns the address of the first
1467 instruction after the register saves or CURRENT_PC, whichever is
1468 smaller. Otherwise, return PC. */
1471 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1472 struct i386_frame_cache
*cache
)
1474 CORE_ADDR offset
= 0;
1478 if (cache
->locals
> 0)
1479 offset
-= cache
->locals
;
1480 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1482 if (target_read_memory (pc
, &op
, 1))
1484 if (op
< 0x50 || op
> 0x57)
1488 cache
->saved_regs
[op
- 0x50] = offset
;
1489 cache
->sp_offset
+= 4;
1496 /* Do a full analysis of the prologue at PC and update CACHE
1497 accordingly. Bail out early if CURRENT_PC is reached. Return the
1498 address where the analysis stopped.
1500 We handle these cases:
1502 The startup sequence can be at the start of the function, or the
1503 function can start with a branch to startup code at the end.
1505 %ebp can be set up with either the 'enter' instruction, or "pushl
1506 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1507 once used in the System V compiler).
1509 Local space is allocated just below the saved %ebp by either the
1510 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1511 16-bit unsigned argument for space to allocate, and the 'addl'
1512 instruction could have either a signed byte, or 32-bit immediate.
1514 Next, the registers used by this function are pushed. With the
1515 System V compiler they will always be in the order: %edi, %esi,
1516 %ebx (and sometimes a harmless bug causes it to also save but not
1517 restore %eax); however, the code below is willing to see the pushes
1518 in any order, and will handle up to 8 of them.
1520 If the setup sequence is at the end of the function, then the next
1521 instruction will be a branch back to the start. */
1524 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1525 CORE_ADDR pc
, CORE_ADDR current_pc
,
1526 struct i386_frame_cache
*cache
)
1528 pc
= i386_skip_noop (pc
);
1529 pc
= i386_follow_jump (gdbarch
, pc
);
1530 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1531 pc
= i386_skip_probe (pc
);
1532 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1533 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1534 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1537 /* Return PC of first real instruction. */
1540 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1542 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1544 static gdb_byte pic_pat
[6] =
1546 0xe8, 0, 0, 0, 0, /* call 0x0 */
1547 0x5b, /* popl %ebx */
1549 struct i386_frame_cache cache
;
1555 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1556 if (cache
.locals
< 0)
1559 /* Found valid frame setup. */
1561 /* The native cc on SVR4 in -K PIC mode inserts the following code
1562 to get the address of the global offset table (GOT) into register
1567 movl %ebx,x(%ebp) (optional)
1570 This code is with the rest of the prologue (at the end of the
1571 function), so we have to skip it to get to the first real
1572 instruction at the start of the function. */
1574 for (i
= 0; i
< 6; i
++)
1576 if (target_read_memory (pc
+ i
, &op
, 1))
1579 if (pic_pat
[i
] != op
)
1586 if (target_read_memory (pc
+ delta
, &op
, 1))
1589 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1591 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1593 if (op
== 0x5d) /* One byte offset from %ebp. */
1595 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1597 else /* Unexpected instruction. */
1600 if (target_read_memory (pc
+ delta
, &op
, 1))
1605 if (delta
> 0 && op
== 0x81
1606 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1613 /* If the function starts with a branch (to startup code at the end)
1614 the last instruction should bring us back to the first
1615 instruction of the real code. */
1616 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1617 pc
= i386_follow_jump (gdbarch
, pc
);
1622 /* Check that the code pointed to by PC corresponds to a call to
1623 __main, skip it if so. Return PC otherwise. */
1626 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1628 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1631 if (target_read_memory (pc
, &op
, 1))
1637 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1639 /* Make sure address is computed correctly as a 32bit
1640 integer even if CORE_ADDR is 64 bit wide. */
1641 struct minimal_symbol
*s
;
1642 CORE_ADDR call_dest
;
1644 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1645 call_dest
= call_dest
& 0xffffffffU
;
1646 s
= lookup_minimal_symbol_by_pc (call_dest
);
1648 && SYMBOL_LINKAGE_NAME (s
) != NULL
1649 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1657 /* This function is 64-bit safe. */
1660 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1664 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1665 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1669 /* Normal frames. */
1672 i386_frame_cache_1 (struct frame_info
*this_frame
,
1673 struct i386_frame_cache
*cache
)
1675 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1680 cache
->pc
= get_frame_func (this_frame
);
1682 /* In principle, for normal frames, %ebp holds the frame pointer,
1683 which holds the base address for the current stack frame.
1684 However, for functions that don't need it, the frame pointer is
1685 optional. For these "frameless" functions the frame pointer is
1686 actually the frame pointer of the calling frame. Signal
1687 trampolines are just a special case of a "frameless" function.
1688 They (usually) share their frame pointer with the frame that was
1689 in progress when the signal occurred. */
1691 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1692 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1693 if (cache
->base
== 0)
1699 /* For normal frames, %eip is stored at 4(%ebp). */
1700 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1703 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1706 if (cache
->locals
< 0)
1708 /* We didn't find a valid frame, which means that CACHE->base
1709 currently holds the frame pointer for our calling frame. If
1710 we're at the start of a function, or somewhere half-way its
1711 prologue, the function's frame probably hasn't been fully
1712 setup yet. Try to reconstruct the base address for the stack
1713 frame by looking at the stack pointer. For truly "frameless"
1714 functions this might work too. */
1716 if (cache
->saved_sp_reg
!= -1)
1718 /* Saved stack pointer has been saved. */
1719 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1720 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1722 /* We're halfway aligning the stack. */
1723 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1724 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1726 /* This will be added back below. */
1727 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1729 else if (cache
->pc
!= 0
1730 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1732 /* We're in a known function, but did not find a frame
1733 setup. Assume that the function does not use %ebp.
1734 Alternatively, we may have jumped to an invalid
1735 address; in that case there is definitely no new
1737 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1738 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1742 /* We're in an unknown function. We could not find the start
1743 of the function to analyze the prologue; our best option is
1744 to assume a typical frame layout with the caller's %ebp
1746 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1749 if (cache
->saved_sp_reg
!= -1)
1751 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1752 register may be unavailable). */
1753 if (cache
->saved_sp
== 0
1754 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1755 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1757 /* Now that we have the base address for the stack frame we can
1758 calculate the value of %esp in the calling frame. */
1759 else if (cache
->saved_sp
== 0)
1760 cache
->saved_sp
= cache
->base
+ 8;
1762 /* Adjust all the saved registers such that they contain addresses
1763 instead of offsets. */
1764 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1765 if (cache
->saved_regs
[i
] != -1)
1766 cache
->saved_regs
[i
] += cache
->base
;
1771 static struct i386_frame_cache
*
1772 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1774 volatile struct gdb_exception ex
;
1775 struct i386_frame_cache
*cache
;
1780 cache
= i386_alloc_frame_cache ();
1781 *this_cache
= cache
;
1783 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1785 i386_frame_cache_1 (this_frame
, cache
);
1787 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1788 throw_exception (ex
);
1794 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1795 struct frame_id
*this_id
)
1797 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1799 /* This marks the outermost frame. */
1800 if (cache
->base
== 0)
1803 /* See the end of i386_push_dummy_call. */
1804 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1807 static enum unwind_stop_reason
1808 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1811 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1814 return UNWIND_UNAVAILABLE
;
1816 /* This marks the outermost frame. */
1817 if (cache
->base
== 0)
1818 return UNWIND_OUTERMOST
;
1820 return UNWIND_NO_REASON
;
1823 static struct value
*
1824 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1827 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1829 gdb_assert (regnum
>= 0);
1831 /* The System V ABI says that:
1833 "The flags register contains the system flags, such as the
1834 direction flag and the carry flag. The direction flag must be
1835 set to the forward (that is, zero) direction before entry and
1836 upon exit from a function. Other user flags have no specified
1837 role in the standard calling sequence and are not preserved."
1839 To guarantee the "upon exit" part of that statement we fake a
1840 saved flags register that has its direction flag cleared.
1842 Note that GCC doesn't seem to rely on the fact that the direction
1843 flag is cleared after a function return; it always explicitly
1844 clears the flag before operations where it matters.
1846 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1847 right thing to do. The way we fake the flags register here makes
1848 it impossible to change it. */
1850 if (regnum
== I386_EFLAGS_REGNUM
)
1854 val
= get_frame_register_unsigned (this_frame
, regnum
);
1856 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1859 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1860 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1862 if (regnum
== I386_ESP_REGNUM
1863 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1865 /* If the SP has been saved, but we don't know where, then this
1866 means that SAVED_SP_REG register was found unavailable back
1867 when we built the cache. */
1868 if (cache
->saved_sp
== 0)
1869 return frame_unwind_got_register (this_frame
, regnum
,
1870 cache
->saved_sp_reg
);
1872 return frame_unwind_got_constant (this_frame
, regnum
,
1876 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1877 return frame_unwind_got_memory (this_frame
, regnum
,
1878 cache
->saved_regs
[regnum
]);
1880 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1883 static const struct frame_unwind i386_frame_unwind
=
1886 i386_frame_unwind_stop_reason
,
1888 i386_frame_prev_register
,
1890 default_frame_sniffer
1893 /* Normal frames, but in a function epilogue. */
1895 /* The epilogue is defined here as the 'ret' instruction, which will
1896 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1897 the function's stack frame. */
1900 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1903 struct symtab
*symtab
;
1905 symtab
= find_pc_symtab (pc
);
1906 if (symtab
&& symtab
->epilogue_unwind_valid
)
1909 if (target_read_memory (pc
, &insn
, 1))
1910 return 0; /* Can't read memory at pc. */
1912 if (insn
!= 0xc3) /* 'ret' instruction. */
1919 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1920 struct frame_info
*this_frame
,
1921 void **this_prologue_cache
)
1923 if (frame_relative_level (this_frame
) == 0)
1924 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1925 get_frame_pc (this_frame
));
1930 static struct i386_frame_cache
*
1931 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1933 volatile struct gdb_exception ex
;
1934 struct i386_frame_cache
*cache
;
1940 cache
= i386_alloc_frame_cache ();
1941 *this_cache
= cache
;
1943 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1945 cache
->pc
= get_frame_func (this_frame
);
1947 /* At this point the stack looks as if we just entered the
1948 function, with the return address at the top of the
1950 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1951 cache
->base
= sp
+ cache
->sp_offset
;
1952 cache
->saved_sp
= cache
->base
+ 8;
1953 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1957 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1958 throw_exception (ex
);
1963 static enum unwind_stop_reason
1964 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1967 struct i386_frame_cache
*cache
=
1968 i386_epilogue_frame_cache (this_frame
, this_cache
);
1971 return UNWIND_UNAVAILABLE
;
1973 return UNWIND_NO_REASON
;
1977 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1979 struct frame_id
*this_id
)
1981 struct i386_frame_cache
*cache
=
1982 i386_epilogue_frame_cache (this_frame
, this_cache
);
1987 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1990 static struct value
*
1991 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1992 void **this_cache
, int regnum
)
1994 /* Make sure we've initialized the cache. */
1995 i386_epilogue_frame_cache (this_frame
, this_cache
);
1997 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2000 static const struct frame_unwind i386_epilogue_frame_unwind
=
2003 i386_epilogue_frame_unwind_stop_reason
,
2004 i386_epilogue_frame_this_id
,
2005 i386_epilogue_frame_prev_register
,
2007 i386_epilogue_frame_sniffer
2011 /* Stack-based trampolines. */
2013 /* These trampolines are used on cross x86 targets, when taking the
2014 address of a nested function. When executing these trampolines,
2015 no stack frame is set up, so we are in a similar situation as in
2016 epilogues and i386_epilogue_frame_this_id can be re-used. */
2018 /* Static chain passed in register. */
2020 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2022 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2023 { 5, { 0xb8 }, { 0xfe } },
2026 { 5, { 0xe9 }, { 0xff } },
2031 /* Static chain passed on stack (when regparm=3). */
2033 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2036 { 5, { 0x68 }, { 0xff } },
2039 { 5, { 0xe9 }, { 0xff } },
2044 /* Return whether PC points inside a stack trampoline. */
2047 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2052 /* A stack trampoline is detected if no name is associated
2053 to the current pc and if it points inside a trampoline
2056 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2060 if (target_read_memory (pc
, &insn
, 1))
2063 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2064 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2071 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2072 struct frame_info
*this_frame
,
2075 if (frame_relative_level (this_frame
) == 0)
2076 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2077 get_frame_pc (this_frame
));
2082 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2085 i386_epilogue_frame_unwind_stop_reason
,
2086 i386_epilogue_frame_this_id
,
2087 i386_epilogue_frame_prev_register
,
2089 i386_stack_tramp_frame_sniffer
2092 /* Generate a bytecode expression to get the value of the saved PC. */
2095 i386_gen_return_address (struct gdbarch
*gdbarch
,
2096 struct agent_expr
*ax
, struct axs_value
*value
,
2099 /* The following sequence assumes the traditional use of the base
2101 ax_reg (ax
, I386_EBP_REGNUM
);
2103 ax_simple (ax
, aop_add
);
2104 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2105 value
->kind
= axs_lvalue_memory
;
2109 /* Signal trampolines. */
2111 static struct i386_frame_cache
*
2112 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2114 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2115 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2116 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2117 volatile struct gdb_exception ex
;
2118 struct i386_frame_cache
*cache
;
2125 cache
= i386_alloc_frame_cache ();
2127 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2129 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2130 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2132 addr
= tdep
->sigcontext_addr (this_frame
);
2133 if (tdep
->sc_reg_offset
)
2137 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2139 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2140 if (tdep
->sc_reg_offset
[i
] != -1)
2141 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2145 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2146 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2151 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2152 throw_exception (ex
);
2154 *this_cache
= cache
;
2158 static enum unwind_stop_reason
2159 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2162 struct i386_frame_cache
*cache
=
2163 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2166 return UNWIND_UNAVAILABLE
;
2168 return UNWIND_NO_REASON
;
2172 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2173 struct frame_id
*this_id
)
2175 struct i386_frame_cache
*cache
=
2176 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2181 /* See the end of i386_push_dummy_call. */
2182 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2185 static struct value
*
2186 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2187 void **this_cache
, int regnum
)
2189 /* Make sure we've initialized the cache. */
2190 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2192 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2196 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2197 struct frame_info
*this_frame
,
2198 void **this_prologue_cache
)
2200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2202 /* We shouldn't even bother if we don't have a sigcontext_addr
2204 if (tdep
->sigcontext_addr
== NULL
)
2207 if (tdep
->sigtramp_p
!= NULL
)
2209 if (tdep
->sigtramp_p (this_frame
))
2213 if (tdep
->sigtramp_start
!= 0)
2215 CORE_ADDR pc
= get_frame_pc (this_frame
);
2217 gdb_assert (tdep
->sigtramp_end
!= 0);
2218 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2225 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2228 i386_sigtramp_frame_unwind_stop_reason
,
2229 i386_sigtramp_frame_this_id
,
2230 i386_sigtramp_frame_prev_register
,
2232 i386_sigtramp_frame_sniffer
2237 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2239 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2244 static const struct frame_base i386_frame_base
=
2247 i386_frame_base_address
,
2248 i386_frame_base_address
,
2249 i386_frame_base_address
2252 static struct frame_id
2253 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2257 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2259 /* See the end of i386_push_dummy_call. */
2260 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2263 /* _Decimal128 function return values need 16-byte alignment on the
2267 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2269 return sp
& -(CORE_ADDR
)16;
2273 /* Figure out where the longjmp will land. Slurp the args out of the
2274 stack. We expect the first arg to be a pointer to the jmp_buf
2275 structure from which we extract the address that we will land at.
2276 This address is copied into PC. This routine returns non-zero on
2280 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2283 CORE_ADDR sp
, jb_addr
;
2284 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2286 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2288 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2289 longjmp will land. */
2290 if (jb_pc_offset
== -1)
2293 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2294 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2295 if (target_read_memory (sp
+ 4, buf
, 4))
2298 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2299 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2302 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2307 /* Check whether TYPE must be 16-byte-aligned when passed as a
2308 function argument. 16-byte vectors, _Decimal128 and structures or
2309 unions containing such types must be 16-byte-aligned; other
2310 arguments are 4-byte-aligned. */
2313 i386_16_byte_align_p (struct type
*type
)
2315 type
= check_typedef (type
);
2316 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2317 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2318 && TYPE_LENGTH (type
) == 16)
2320 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2321 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2322 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2323 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2326 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2328 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2335 /* Implementation for set_gdbarch_push_dummy_code. */
2338 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2339 struct value
**args
, int nargs
, struct type
*value_type
,
2340 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2341 struct regcache
*regcache
)
2343 /* Use 0xcc breakpoint - 1 byte. */
2347 /* Keep the stack aligned. */
2352 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2353 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2354 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2355 CORE_ADDR struct_addr
)
2357 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2363 /* Determine the total space required for arguments and struct
2364 return address in a first pass (allowing for 16-byte-aligned
2365 arguments), then push arguments in a second pass. */
2367 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2369 int args_space_used
= 0;
2375 /* Push value address. */
2376 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2377 write_memory (sp
, buf
, 4);
2378 args_space_used
+= 4;
2384 for (i
= 0; i
< nargs
; i
++)
2386 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2390 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2391 args_space_used
= align_up (args_space_used
, 16);
2393 write_memory (sp
+ args_space_used
,
2394 value_contents_all (args
[i
]), len
);
2395 /* The System V ABI says that:
2397 "An argument's size is increased, if necessary, to make it a
2398 multiple of [32-bit] words. This may require tail padding,
2399 depending on the size of the argument."
2401 This makes sure the stack stays word-aligned. */
2402 args_space_used
+= align_up (len
, 4);
2406 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2407 args_space
= align_up (args_space
, 16);
2408 args_space
+= align_up (len
, 4);
2416 /* The original System V ABI only requires word alignment,
2417 but modern incarnations need 16-byte alignment in order
2418 to support SSE. Since wasting a few bytes here isn't
2419 harmful we unconditionally enforce 16-byte alignment. */
2424 /* Store return address. */
2426 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2427 write_memory (sp
, buf
, 4);
2429 /* Finally, update the stack pointer... */
2430 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2431 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2433 /* ...and fake a frame pointer. */
2434 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2436 /* MarkK wrote: This "+ 8" is all over the place:
2437 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2438 i386_dummy_id). It's there, since all frame unwinders for
2439 a given target have to agree (within a certain margin) on the
2440 definition of the stack address of a frame. Otherwise frame id
2441 comparison might not work correctly. Since DWARF2/GCC uses the
2442 stack address *before* the function call as a frame's CFA. On
2443 the i386, when %ebp is used as a frame pointer, the offset
2444 between the contents %ebp and the CFA as defined by GCC. */
2448 /* These registers are used for returning integers (and on some
2449 targets also for returning `struct' and `union' values when their
2450 size and alignment match an integer type). */
2451 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2452 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2454 /* Read, for architecture GDBARCH, a function return value of TYPE
2455 from REGCACHE, and copy that into VALBUF. */
2458 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2459 struct regcache
*regcache
, gdb_byte
*valbuf
)
2461 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2462 int len
= TYPE_LENGTH (type
);
2463 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2465 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2467 if (tdep
->st0_regnum
< 0)
2469 warning (_("Cannot find floating-point return value."));
2470 memset (valbuf
, 0, len
);
2474 /* Floating-point return values can be found in %st(0). Convert
2475 its contents to the desired type. This is probably not
2476 exactly how it would happen on the target itself, but it is
2477 the best we can do. */
2478 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2479 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2483 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2484 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2486 if (len
<= low_size
)
2488 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2489 memcpy (valbuf
, buf
, len
);
2491 else if (len
<= (low_size
+ high_size
))
2493 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2494 memcpy (valbuf
, buf
, low_size
);
2495 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2496 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2499 internal_error (__FILE__
, __LINE__
,
2500 _("Cannot extract return value of %d bytes long."),
2505 /* Write, for architecture GDBARCH, a function return value of TYPE
2506 from VALBUF into REGCACHE. */
2509 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2510 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2513 int len
= TYPE_LENGTH (type
);
2515 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2518 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2520 if (tdep
->st0_regnum
< 0)
2522 warning (_("Cannot set floating-point return value."));
2526 /* Returning floating-point values is a bit tricky. Apart from
2527 storing the return value in %st(0), we have to simulate the
2528 state of the FPU at function return point. */
2530 /* Convert the value found in VALBUF to the extended
2531 floating-point format used by the FPU. This is probably
2532 not exactly how it would happen on the target itself, but
2533 it is the best we can do. */
2534 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2535 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2537 /* Set the top of the floating-point register stack to 7. The
2538 actual value doesn't really matter, but 7 is what a normal
2539 function return would end up with if the program started out
2540 with a freshly initialized FPU. */
2541 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2543 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2545 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2546 the floating-point register stack to 7, the appropriate value
2547 for the tag word is 0x3fff. */
2548 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2552 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2553 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2555 if (len
<= low_size
)
2556 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2557 else if (len
<= (low_size
+ high_size
))
2559 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2560 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2561 len
- low_size
, valbuf
+ low_size
);
2564 internal_error (__FILE__
, __LINE__
,
2565 _("Cannot store return value of %d bytes long."), len
);
2570 /* This is the variable that is set with "set struct-convention", and
2571 its legitimate values. */
2572 static const char default_struct_convention
[] = "default";
2573 static const char pcc_struct_convention
[] = "pcc";
2574 static const char reg_struct_convention
[] = "reg";
2575 static const char *const valid_conventions
[] =
2577 default_struct_convention
,
2578 pcc_struct_convention
,
2579 reg_struct_convention
,
2582 static const char *struct_convention
= default_struct_convention
;
2584 /* Return non-zero if TYPE, which is assumed to be a structure,
2585 a union type, or an array type, should be returned in registers
2586 for architecture GDBARCH. */
2589 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2591 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2592 enum type_code code
= TYPE_CODE (type
);
2593 int len
= TYPE_LENGTH (type
);
2595 gdb_assert (code
== TYPE_CODE_STRUCT
2596 || code
== TYPE_CODE_UNION
2597 || code
== TYPE_CODE_ARRAY
);
2599 if (struct_convention
== pcc_struct_convention
2600 || (struct_convention
== default_struct_convention
2601 && tdep
->struct_return
== pcc_struct_return
))
2604 /* Structures consisting of a single `float', `double' or 'long
2605 double' member are returned in %st(0). */
2606 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2608 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2609 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2610 return (len
== 4 || len
== 8 || len
== 12);
2613 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2616 /* Determine, for architecture GDBARCH, how a return value of TYPE
2617 should be returned. If it is supposed to be returned in registers,
2618 and READBUF is non-zero, read the appropriate value from REGCACHE,
2619 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2620 from WRITEBUF into REGCACHE. */
2622 static enum return_value_convention
2623 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2624 struct type
*type
, struct regcache
*regcache
,
2625 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2627 enum type_code code
= TYPE_CODE (type
);
2629 if (((code
== TYPE_CODE_STRUCT
2630 || code
== TYPE_CODE_UNION
2631 || code
== TYPE_CODE_ARRAY
)
2632 && !i386_reg_struct_return_p (gdbarch
, type
))
2633 /* Complex double and long double uses the struct return covention. */
2634 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2635 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2636 /* 128-bit decimal float uses the struct return convention. */
2637 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2639 /* The System V ABI says that:
2641 "A function that returns a structure or union also sets %eax
2642 to the value of the original address of the caller's area
2643 before it returns. Thus when the caller receives control
2644 again, the address of the returned object resides in register
2645 %eax and can be used to access the object."
2647 So the ABI guarantees that we can always find the return
2648 value just after the function has returned. */
2650 /* Note that the ABI doesn't mention functions returning arrays,
2651 which is something possible in certain languages such as Ada.
2652 In this case, the value is returned as if it was wrapped in
2653 a record, so the convention applied to records also applies
2660 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2661 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2664 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2667 /* This special case is for structures consisting of a single
2668 `float', `double' or 'long double' member. These structures are
2669 returned in %st(0). For these structures, we call ourselves
2670 recursively, changing TYPE into the type of the first member of
2671 the structure. Since that should work for all structures that
2672 have only one member, we don't bother to check the member's type
2674 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2676 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2677 return i386_return_value (gdbarch
, function
, type
, regcache
,
2682 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2684 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2686 return RETURN_VALUE_REGISTER_CONVENTION
;
2691 i387_ext_type (struct gdbarch
*gdbarch
)
2693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2695 if (!tdep
->i387_ext_type
)
2697 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2698 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2701 return tdep
->i387_ext_type
;
2704 /* Construct vector type for pseudo YMM registers. We can't use
2705 tdesc_find_type since YMM isn't described in target description. */
2707 static struct type
*
2708 i386_ymm_type (struct gdbarch
*gdbarch
)
2710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2712 if (!tdep
->i386_ymm_type
)
2714 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2716 /* The type we're building is this: */
2718 union __gdb_builtin_type_vec256i
2720 int128_t uint128
[2];
2721 int64_t v2_int64
[4];
2722 int32_t v4_int32
[8];
2723 int16_t v8_int16
[16];
2724 int8_t v16_int8
[32];
2725 double v2_double
[4];
2732 t
= arch_composite_type (gdbarch
,
2733 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2734 append_composite_type_field (t
, "v8_float",
2735 init_vector_type (bt
->builtin_float
, 8));
2736 append_composite_type_field (t
, "v4_double",
2737 init_vector_type (bt
->builtin_double
, 4));
2738 append_composite_type_field (t
, "v32_int8",
2739 init_vector_type (bt
->builtin_int8
, 32));
2740 append_composite_type_field (t
, "v16_int16",
2741 init_vector_type (bt
->builtin_int16
, 16));
2742 append_composite_type_field (t
, "v8_int32",
2743 init_vector_type (bt
->builtin_int32
, 8));
2744 append_composite_type_field (t
, "v4_int64",
2745 init_vector_type (bt
->builtin_int64
, 4));
2746 append_composite_type_field (t
, "v2_int128",
2747 init_vector_type (bt
->builtin_int128
, 2));
2749 TYPE_VECTOR (t
) = 1;
2750 TYPE_NAME (t
) = "builtin_type_vec256i";
2751 tdep
->i386_ymm_type
= t
;
2754 return tdep
->i386_ymm_type
;
2757 /* Construct vector type for MMX registers. */
2758 static struct type
*
2759 i386_mmx_type (struct gdbarch
*gdbarch
)
2761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2763 if (!tdep
->i386_mmx_type
)
2765 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2767 /* The type we're building is this: */
2769 union __gdb_builtin_type_vec64i
2772 int32_t v2_int32
[2];
2773 int16_t v4_int16
[4];
2780 t
= arch_composite_type (gdbarch
,
2781 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2783 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2784 append_composite_type_field (t
, "v2_int32",
2785 init_vector_type (bt
->builtin_int32
, 2));
2786 append_composite_type_field (t
, "v4_int16",
2787 init_vector_type (bt
->builtin_int16
, 4));
2788 append_composite_type_field (t
, "v8_int8",
2789 init_vector_type (bt
->builtin_int8
, 8));
2791 TYPE_VECTOR (t
) = 1;
2792 TYPE_NAME (t
) = "builtin_type_vec64i";
2793 tdep
->i386_mmx_type
= t
;
2796 return tdep
->i386_mmx_type
;
2799 /* Return the GDB type object for the "standard" data type of data in
2803 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2805 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2806 return i386_mmx_type (gdbarch
);
2807 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2808 return i386_ymm_type (gdbarch
);
2811 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2812 if (i386_byte_regnum_p (gdbarch
, regnum
))
2813 return bt
->builtin_int8
;
2814 else if (i386_word_regnum_p (gdbarch
, regnum
))
2815 return bt
->builtin_int16
;
2816 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2817 return bt
->builtin_int32
;
2820 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2823 /* Map a cooked register onto a raw register or memory. For the i386,
2824 the MMX registers need to be mapped onto floating point registers. */
2827 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2829 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2834 mmxreg
= regnum
- tdep
->mm0_regnum
;
2835 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2836 tos
= (fstat
>> 11) & 0x7;
2837 fpreg
= (mmxreg
+ tos
) % 8;
2839 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2842 /* A helper function for us by i386_pseudo_register_read_value and
2843 amd64_pseudo_register_read_value. It does all the work but reads
2844 the data into an already-allocated value. */
2847 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2848 struct regcache
*regcache
,
2850 struct value
*result_value
)
2852 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2853 enum register_status status
;
2854 gdb_byte
*buf
= value_contents_raw (result_value
);
2856 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2858 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2860 /* Extract (always little endian). */
2861 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2862 if (status
!= REG_VALID
)
2863 mark_value_bytes_unavailable (result_value
, 0,
2864 TYPE_LENGTH (value_type (result_value
)));
2866 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2872 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2874 regnum
-= tdep
->ymm0_regnum
;
2876 /* Extract (always little endian). Read lower 128bits. */
2877 status
= regcache_raw_read (regcache
,
2878 I387_XMM0_REGNUM (tdep
) + regnum
,
2880 if (status
!= REG_VALID
)
2881 mark_value_bytes_unavailable (result_value
, 0, 16);
2883 memcpy (buf
, raw_buf
, 16);
2884 /* Read upper 128bits. */
2885 status
= regcache_raw_read (regcache
,
2886 tdep
->ymm0h_regnum
+ regnum
,
2888 if (status
!= REG_VALID
)
2889 mark_value_bytes_unavailable (result_value
, 16, 32);
2891 memcpy (buf
+ 16, raw_buf
, 16);
2893 else if (i386_word_regnum_p (gdbarch
, regnum
))
2895 int gpnum
= regnum
- tdep
->ax_regnum
;
2897 /* Extract (always little endian). */
2898 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2899 if (status
!= REG_VALID
)
2900 mark_value_bytes_unavailable (result_value
, 0,
2901 TYPE_LENGTH (value_type (result_value
)));
2903 memcpy (buf
, raw_buf
, 2);
2905 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2907 /* Check byte pseudo registers last since this function will
2908 be called from amd64_pseudo_register_read, which handles
2909 byte pseudo registers differently. */
2910 int gpnum
= regnum
- tdep
->al_regnum
;
2912 /* Extract (always little endian). We read both lower and
2914 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2915 if (status
!= REG_VALID
)
2916 mark_value_bytes_unavailable (result_value
, 0,
2917 TYPE_LENGTH (value_type (result_value
)));
2918 else if (gpnum
>= 4)
2919 memcpy (buf
, raw_buf
+ 1, 1);
2921 memcpy (buf
, raw_buf
, 1);
2924 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2928 static struct value
*
2929 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2930 struct regcache
*regcache
,
2933 struct value
*result
;
2935 result
= allocate_value (register_type (gdbarch
, regnum
));
2936 VALUE_LVAL (result
) = lval_register
;
2937 VALUE_REGNUM (result
) = regnum
;
2939 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2945 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2946 int regnum
, const gdb_byte
*buf
)
2948 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2950 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2952 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2955 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2956 /* ... Modify ... (always little endian). */
2957 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2959 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2965 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2967 regnum
-= tdep
->ymm0_regnum
;
2969 /* ... Write lower 128bits. */
2970 regcache_raw_write (regcache
,
2971 I387_XMM0_REGNUM (tdep
) + regnum
,
2973 /* ... Write upper 128bits. */
2974 regcache_raw_write (regcache
,
2975 tdep
->ymm0h_regnum
+ regnum
,
2978 else if (i386_word_regnum_p (gdbarch
, regnum
))
2980 int gpnum
= regnum
- tdep
->ax_regnum
;
2983 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2984 /* ... Modify ... (always little endian). */
2985 memcpy (raw_buf
, buf
, 2);
2987 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2989 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2991 /* Check byte pseudo registers last since this function will
2992 be called from amd64_pseudo_register_read, which handles
2993 byte pseudo registers differently. */
2994 int gpnum
= regnum
- tdep
->al_regnum
;
2996 /* Read ... We read both lower and upper registers. */
2997 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2998 /* ... Modify ... (always little endian). */
3000 memcpy (raw_buf
+ 1, buf
, 1);
3002 memcpy (raw_buf
, buf
, 1);
3004 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3007 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3012 /* Return the register number of the register allocated by GCC after
3013 REGNUM, or -1 if there is no such register. */
3016 i386_next_regnum (int regnum
)
3018 /* GCC allocates the registers in the order:
3020 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3022 Since storing a variable in %esp doesn't make any sense we return
3023 -1 for %ebp and for %esp itself. */
3024 static int next_regnum
[] =
3026 I386_EDX_REGNUM
, /* Slot for %eax. */
3027 I386_EBX_REGNUM
, /* Slot for %ecx. */
3028 I386_ECX_REGNUM
, /* Slot for %edx. */
3029 I386_ESI_REGNUM
, /* Slot for %ebx. */
3030 -1, -1, /* Slots for %esp and %ebp. */
3031 I386_EDI_REGNUM
, /* Slot for %esi. */
3032 I386_EBP_REGNUM
/* Slot for %edi. */
3035 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3036 return next_regnum
[regnum
];
3041 /* Return nonzero if a value of type TYPE stored in register REGNUM
3042 needs any special handling. */
3045 i386_convert_register_p (struct gdbarch
*gdbarch
,
3046 int regnum
, struct type
*type
)
3048 int len
= TYPE_LENGTH (type
);
3050 /* Values may be spread across multiple registers. Most debugging
3051 formats aren't expressive enough to specify the locations, so
3052 some heuristics is involved. Right now we only handle types that
3053 have a length that is a multiple of the word size, since GCC
3054 doesn't seem to put any other types into registers. */
3055 if (len
> 4 && len
% 4 == 0)
3057 int last_regnum
= regnum
;
3061 last_regnum
= i386_next_regnum (last_regnum
);
3065 if (last_regnum
!= -1)
3069 return i387_convert_register_p (gdbarch
, regnum
, type
);
3072 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3073 return its contents in TO. */
3076 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3077 struct type
*type
, gdb_byte
*to
,
3078 int *optimizedp
, int *unavailablep
)
3080 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3081 int len
= TYPE_LENGTH (type
);
3083 if (i386_fp_regnum_p (gdbarch
, regnum
))
3084 return i387_register_to_value (frame
, regnum
, type
, to
,
3085 optimizedp
, unavailablep
);
3087 /* Read a value spread across multiple registers. */
3089 gdb_assert (len
> 4 && len
% 4 == 0);
3093 gdb_assert (regnum
!= -1);
3094 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3096 if (!get_frame_register_bytes (frame
, regnum
, 0,
3097 register_size (gdbarch
, regnum
),
3098 to
, optimizedp
, unavailablep
))
3101 regnum
= i386_next_regnum (regnum
);
3106 *optimizedp
= *unavailablep
= 0;
3110 /* Write the contents FROM of a value of type TYPE into register
3111 REGNUM in frame FRAME. */
3114 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3115 struct type
*type
, const gdb_byte
*from
)
3117 int len
= TYPE_LENGTH (type
);
3119 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3121 i387_value_to_register (frame
, regnum
, type
, from
);
3125 /* Write a value spread across multiple registers. */
3127 gdb_assert (len
> 4 && len
% 4 == 0);
3131 gdb_assert (regnum
!= -1);
3132 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3134 put_frame_register (frame
, regnum
, from
);
3135 regnum
= i386_next_regnum (regnum
);
3141 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3142 in the general-purpose register set REGSET to register cache
3143 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3146 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3147 int regnum
, const void *gregs
, size_t len
)
3149 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3150 const gdb_byte
*regs
= gregs
;
3153 gdb_assert (len
== tdep
->sizeof_gregset
);
3155 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3157 if ((regnum
== i
|| regnum
== -1)
3158 && tdep
->gregset_reg_offset
[i
] != -1)
3159 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3163 /* Collect register REGNUM from the register cache REGCACHE and store
3164 it in the buffer specified by GREGS and LEN as described by the
3165 general-purpose register set REGSET. If REGNUM is -1, do this for
3166 all registers in REGSET. */
3169 i386_collect_gregset (const struct regset
*regset
,
3170 const struct regcache
*regcache
,
3171 int regnum
, void *gregs
, size_t len
)
3173 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3174 gdb_byte
*regs
= gregs
;
3177 gdb_assert (len
== tdep
->sizeof_gregset
);
3179 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3181 if ((regnum
== i
|| regnum
== -1)
3182 && tdep
->gregset_reg_offset
[i
] != -1)
3183 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3187 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3188 in the floating-point register set REGSET to register cache
3189 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3192 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3193 int regnum
, const void *fpregs
, size_t len
)
3195 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3197 if (len
== I387_SIZEOF_FXSAVE
)
3199 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3203 gdb_assert (len
== tdep
->sizeof_fpregset
);
3204 i387_supply_fsave (regcache
, regnum
, fpregs
);
3207 /* Collect register REGNUM from the register cache REGCACHE and store
3208 it in the buffer specified by FPREGS and LEN as described by the
3209 floating-point register set REGSET. If REGNUM is -1, do this for
3210 all registers in REGSET. */
3213 i386_collect_fpregset (const struct regset
*regset
,
3214 const struct regcache
*regcache
,
3215 int regnum
, void *fpregs
, size_t len
)
3217 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3219 if (len
== I387_SIZEOF_FXSAVE
)
3221 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3225 gdb_assert (len
== tdep
->sizeof_fpregset
);
3226 i387_collect_fsave (regcache
, regnum
, fpregs
);
3229 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3232 i386_supply_xstateregset (const struct regset
*regset
,
3233 struct regcache
*regcache
, int regnum
,
3234 const void *xstateregs
, size_t len
)
3236 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3239 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3242 i386_collect_xstateregset (const struct regset
*regset
,
3243 const struct regcache
*regcache
,
3244 int regnum
, void *xstateregs
, size_t len
)
3246 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3249 /* Return the appropriate register set for the core section identified
3250 by SECT_NAME and SECT_SIZE. */
3252 const struct regset
*
3253 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3254 const char *sect_name
, size_t sect_size
)
3256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3258 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3260 if (tdep
->gregset
== NULL
)
3261 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3262 i386_collect_gregset
);
3263 return tdep
->gregset
;
3266 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3267 || (strcmp (sect_name
, ".reg-xfp") == 0
3268 && sect_size
== I387_SIZEOF_FXSAVE
))
3270 if (tdep
->fpregset
== NULL
)
3271 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3272 i386_collect_fpregset
);
3273 return tdep
->fpregset
;
3276 if (strcmp (sect_name
, ".reg-xstate") == 0)
3278 if (tdep
->xstateregset
== NULL
)
3279 tdep
->xstateregset
= regset_alloc (gdbarch
,
3280 i386_supply_xstateregset
,
3281 i386_collect_xstateregset
);
3283 return tdep
->xstateregset
;
3290 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3293 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3294 CORE_ADDR pc
, char *name
)
3296 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3300 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3302 unsigned long indirect
=
3303 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3304 struct minimal_symbol
*indsym
=
3305 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3306 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3310 if (strncmp (symname
, "__imp_", 6) == 0
3311 || strncmp (symname
, "_imp_", 5) == 0)
3313 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3316 return 0; /* Not a trampoline. */
3320 /* Return whether the THIS_FRAME corresponds to a sigtramp
3324 i386_sigtramp_p (struct frame_info
*this_frame
)
3326 CORE_ADDR pc
= get_frame_pc (this_frame
);
3329 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3330 return (name
&& strcmp ("_sigtramp", name
) == 0);
3334 /* We have two flavours of disassembly. The machinery on this page
3335 deals with switching between those. */
3338 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3340 gdb_assert (disassembly_flavor
== att_flavor
3341 || disassembly_flavor
== intel_flavor
);
3343 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3344 constified, cast to prevent a compiler warning. */
3345 info
->disassembler_options
= (char *) disassembly_flavor
;
3347 return print_insn_i386 (pc
, info
);
3351 /* There are a few i386 architecture variants that differ only
3352 slightly from the generic i386 target. For now, we don't give them
3353 their own source file, but include them here. As a consequence,
3354 they'll always be included. */
3356 /* System V Release 4 (SVR4). */
3358 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3362 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3364 CORE_ADDR pc
= get_frame_pc (this_frame
);
3367 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3368 currently unknown. */
3369 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3370 return (name
&& (strcmp ("_sigreturn", name
) == 0
3371 || strcmp ("_sigacthandler", name
) == 0
3372 || strcmp ("sigvechandler", name
) == 0));
3375 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3376 address of the associated sigcontext (ucontext) structure. */
3379 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3381 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3382 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3386 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3387 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3389 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3394 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3398 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3400 return (*s
== '$' /* Literal number. */
3401 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3402 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3403 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3406 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3410 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3411 struct stap_parse_info
*p
)
3413 /* In order to parse special tokens, we use a state-machine that go
3414 through every known token and try to get a match. */
3418 THREE_ARG_DISPLACEMENT
,
3422 current_state
= TRIPLET
;
3424 /* The special tokens to be parsed here are:
3426 - `register base + (register index * size) + offset', as represented
3427 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3429 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3430 `*(-8 + 3 - 1 + (void *) $eax)'. */
3432 while (current_state
!= DONE
)
3434 const char *s
= p
->arg
;
3436 switch (current_state
)
3440 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3444 long displacements
[3];
3459 displacements
[0] = strtol (s
, (char **) &s
, 10);
3461 if (*s
!= '+' && *s
!= '-')
3463 /* We are not dealing with a triplet. */
3476 displacements
[1] = strtol (s
, (char **) &s
, 10);
3478 if (*s
!= '+' && *s
!= '-')
3480 /* We are not dealing with a triplet. */
3493 displacements
[2] = strtol (s
, (char **) &s
, 10);
3495 if (*s
!= '(' || s
[1] != '%')
3501 while (isalnum (*s
))
3508 regname
= alloca (len
+ 1);
3510 strncpy (regname
, start
, len
);
3511 regname
[len
] = '\0';
3513 if (user_reg_map_name_to_regnum (gdbarch
,
3514 regname
, len
) == -1)
3515 error (_("Invalid register name `%s' "
3516 "on expression `%s'."),
3517 regname
, p
->saved_arg
);
3519 for (i
= 0; i
< 3; i
++)
3521 write_exp_elt_opcode (OP_LONG
);
3523 (builtin_type (gdbarch
)->builtin_long
);
3524 write_exp_elt_longcst (displacements
[i
]);
3525 write_exp_elt_opcode (OP_LONG
);
3527 write_exp_elt_opcode (UNOP_NEG
);
3530 write_exp_elt_opcode (OP_REGISTER
);
3533 write_exp_string (str
);
3534 write_exp_elt_opcode (OP_REGISTER
);
3536 write_exp_elt_opcode (UNOP_CAST
);
3537 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3538 write_exp_elt_opcode (UNOP_CAST
);
3540 write_exp_elt_opcode (BINOP_ADD
);
3541 write_exp_elt_opcode (BINOP_ADD
);
3542 write_exp_elt_opcode (BINOP_ADD
);
3544 write_exp_elt_opcode (UNOP_CAST
);
3545 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3546 write_exp_elt_opcode (UNOP_CAST
);
3548 write_exp_elt_opcode (UNOP_IND
);
3556 case THREE_ARG_DISPLACEMENT
:
3558 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3560 int offset_minus
= 0;
3569 struct stoken base_token
, index_token
;
3579 if (offset_minus
&& !isdigit (*s
))
3583 offset
= strtol (s
, (char **) &s
, 10);
3585 if (*s
!= '(' || s
[1] != '%')
3591 while (isalnum (*s
))
3594 if (*s
!= ',' || s
[1] != '%')
3597 len_base
= s
- start
;
3598 base
= alloca (len_base
+ 1);
3599 strncpy (base
, start
, len_base
);
3600 base
[len_base
] = '\0';
3602 if (user_reg_map_name_to_regnum (gdbarch
,
3603 base
, len_base
) == -1)
3604 error (_("Invalid register name `%s' "
3605 "on expression `%s'."),
3606 base
, p
->saved_arg
);
3611 while (isalnum (*s
))
3614 len_index
= s
- start
;
3615 index
= alloca (len_index
+ 1);
3616 strncpy (index
, start
, len_index
);
3617 index
[len_index
] = '\0';
3619 if (user_reg_map_name_to_regnum (gdbarch
,
3620 index
, len_index
) == -1)
3621 error (_("Invalid register name `%s' "
3622 "on expression `%s'."),
3623 index
, p
->saved_arg
);
3625 if (*s
!= ',' && *s
!= ')')
3639 size
= strtol (s
, (char **) &s
, 10);
3649 write_exp_elt_opcode (OP_LONG
);
3651 (builtin_type (gdbarch
)->builtin_long
);
3652 write_exp_elt_longcst (offset
);
3653 write_exp_elt_opcode (OP_LONG
);
3655 write_exp_elt_opcode (UNOP_NEG
);
3658 write_exp_elt_opcode (OP_REGISTER
);
3659 base_token
.ptr
= base
;
3660 base_token
.length
= len_base
;
3661 write_exp_string (base_token
);
3662 write_exp_elt_opcode (OP_REGISTER
);
3665 write_exp_elt_opcode (BINOP_ADD
);
3667 write_exp_elt_opcode (OP_REGISTER
);
3668 index_token
.ptr
= index
;
3669 index_token
.length
= len_index
;
3670 write_exp_string (index_token
);
3671 write_exp_elt_opcode (OP_REGISTER
);
3675 write_exp_elt_opcode (OP_LONG
);
3677 (builtin_type (gdbarch
)->builtin_long
);
3678 write_exp_elt_longcst (size
);
3679 write_exp_elt_opcode (OP_LONG
);
3681 write_exp_elt_opcode (UNOP_NEG
);
3682 write_exp_elt_opcode (BINOP_MUL
);
3685 write_exp_elt_opcode (BINOP_ADD
);
3687 write_exp_elt_opcode (UNOP_CAST
);
3688 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3689 write_exp_elt_opcode (UNOP_CAST
);
3691 write_exp_elt_opcode (UNOP_IND
);
3701 /* Advancing to the next state. */
3713 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3715 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3716 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3718 /* Registering SystemTap handlers. */
3719 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3720 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3721 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3722 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3723 set_gdbarch_stap_is_single_operand (gdbarch
,
3724 i386_stap_is_single_operand
);
3725 set_gdbarch_stap_parse_special_token (gdbarch
,
3726 i386_stap_parse_special_token
);
3729 /* System V Release 4 (SVR4). */
3732 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3736 /* System V Release 4 uses ELF. */
3737 i386_elf_init_abi (info
, gdbarch
);
3739 /* System V Release 4 has shared libraries. */
3740 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3742 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3743 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3744 tdep
->sc_pc_offset
= 36 + 14 * 4;
3745 tdep
->sc_sp_offset
= 36 + 17 * 4;
3747 tdep
->jb_pc_offset
= 20;
3753 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3757 /* DJGPP doesn't have any special frames for signal handlers. */
3758 tdep
->sigtramp_p
= NULL
;
3760 tdep
->jb_pc_offset
= 36;
3762 /* DJGPP does not support the SSE registers. */
3763 if (! tdesc_has_registers (info
.target_desc
))
3764 tdep
->tdesc
= tdesc_i386_mmx
;
3766 /* Native compiler is GCC, which uses the SVR4 register numbering
3767 even in COFF and STABS. See the comment in i386_gdbarch_init,
3768 before the calls to set_gdbarch_stab_reg_to_regnum and
3769 set_gdbarch_sdb_reg_to_regnum. */
3770 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3771 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3773 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3777 /* i386 register groups. In addition to the normal groups, add "mmx"
3780 static struct reggroup
*i386_sse_reggroup
;
3781 static struct reggroup
*i386_mmx_reggroup
;
3784 i386_init_reggroups (void)
3786 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3787 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3791 i386_add_reggroups (struct gdbarch
*gdbarch
)
3793 reggroup_add (gdbarch
, i386_sse_reggroup
);
3794 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3795 reggroup_add (gdbarch
, general_reggroup
);
3796 reggroup_add (gdbarch
, float_reggroup
);
3797 reggroup_add (gdbarch
, all_reggroup
);
3798 reggroup_add (gdbarch
, save_reggroup
);
3799 reggroup_add (gdbarch
, restore_reggroup
);
3800 reggroup_add (gdbarch
, vector_reggroup
);
3801 reggroup_add (gdbarch
, system_reggroup
);
3805 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3806 struct reggroup
*group
)
3808 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3809 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3810 ymm_regnum_p
, ymmh_regnum_p
;
3812 /* Don't include pseudo registers, except for MMX, in any register
3814 if (i386_byte_regnum_p (gdbarch
, regnum
))
3817 if (i386_word_regnum_p (gdbarch
, regnum
))
3820 if (i386_dword_regnum_p (gdbarch
, regnum
))
3823 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3824 if (group
== i386_mmx_reggroup
)
3825 return mmx_regnum_p
;
3827 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3828 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3829 if (group
== i386_sse_reggroup
)
3830 return xmm_regnum_p
|| mxcsr_regnum_p
;
3832 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3833 if (group
== vector_reggroup
)
3834 return (mmx_regnum_p
3838 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3839 == I386_XSTATE_SSE_MASK
)));
3841 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3842 || i386_fpc_regnum_p (gdbarch
, regnum
));
3843 if (group
== float_reggroup
)
3846 /* For "info reg all", don't include upper YMM registers nor XMM
3847 registers when AVX is supported. */
3848 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3849 if (group
== all_reggroup
3851 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3855 if (group
== general_reggroup
)
3856 return (!fp_regnum_p
3863 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3867 /* Get the ARGIth function argument for the current function. */
3870 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3873 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3874 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3875 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3876 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3880 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3882 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3884 /* On i386, breakpoint is exactly 1 byte long, so we just
3885 adjust the PC in the regcache. */
3887 regcache_write_pc (regcache
, current_pc
);
3891 #define PREFIX_REPZ 0x01
3892 #define PREFIX_REPNZ 0x02
3893 #define PREFIX_LOCK 0x04
3894 #define PREFIX_DATA 0x08
3895 #define PREFIX_ADDR 0x10
3907 /* i386 arith/logic operations */
3920 struct i386_record_s
3922 struct gdbarch
*gdbarch
;
3923 struct regcache
*regcache
;
3924 CORE_ADDR orig_addr
;
3930 uint8_t mod
, reg
, rm
;
3939 /* Parse the "modrm" part of the memory address irp->addr points at.
3940 Returns -1 if something goes wrong, 0 otherwise. */
3943 i386_record_modrm (struct i386_record_s
*irp
)
3945 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3947 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
3951 irp
->mod
= (irp
->modrm
>> 6) & 3;
3952 irp
->reg
= (irp
->modrm
>> 3) & 7;
3953 irp
->rm
= irp
->modrm
& 7;
3958 /* Extract the memory address that the current instruction writes to,
3959 and return it in *ADDR. Return -1 if something goes wrong. */
3962 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3964 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3965 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3977 uint8_t base
= irp
->rm
;
3982 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
3985 scale
= (byte
>> 6) & 3;
3986 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3994 if ((base
& 7) == 5)
3997 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4000 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4001 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4002 *addr
+= irp
->addr
+ irp
->rip_offset
;
4006 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4009 *addr
= (int8_t) buf
[0];
4012 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4014 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4022 if (base
== 4 && irp
->popl_esp_hack
)
4023 *addr
+= irp
->popl_esp_hack
;
4024 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4027 if (irp
->aflag
== 2)
4032 *addr
= (uint32_t) (offset64
+ *addr
);
4034 if (havesib
&& (index
!= 4 || scale
!= 0))
4036 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4038 if (irp
->aflag
== 2)
4039 *addr
+= offset64
<< scale
;
4041 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4052 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4055 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4061 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4064 *addr
= (int8_t) buf
[0];
4067 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4070 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4077 regcache_raw_read_unsigned (irp
->regcache
,
4078 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4080 *addr
= (uint32_t) (*addr
+ offset64
);
4081 regcache_raw_read_unsigned (irp
->regcache
,
4082 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4084 *addr
= (uint32_t) (*addr
+ offset64
);
4087 regcache_raw_read_unsigned (irp
->regcache
,
4088 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4090 *addr
= (uint32_t) (*addr
+ offset64
);
4091 regcache_raw_read_unsigned (irp
->regcache
,
4092 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4094 *addr
= (uint32_t) (*addr
+ offset64
);
4097 regcache_raw_read_unsigned (irp
->regcache
,
4098 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4100 *addr
= (uint32_t) (*addr
+ offset64
);
4101 regcache_raw_read_unsigned (irp
->regcache
,
4102 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4104 *addr
= (uint32_t) (*addr
+ offset64
);
4107 regcache_raw_read_unsigned (irp
->regcache
,
4108 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4110 *addr
= (uint32_t) (*addr
+ offset64
);
4111 regcache_raw_read_unsigned (irp
->regcache
,
4112 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4114 *addr
= (uint32_t) (*addr
+ offset64
);
4117 regcache_raw_read_unsigned (irp
->regcache
,
4118 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4120 *addr
= (uint32_t) (*addr
+ offset64
);
4123 regcache_raw_read_unsigned (irp
->regcache
,
4124 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4126 *addr
= (uint32_t) (*addr
+ offset64
);
4129 regcache_raw_read_unsigned (irp
->regcache
,
4130 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4132 *addr
= (uint32_t) (*addr
+ offset64
);
4135 regcache_raw_read_unsigned (irp
->regcache
,
4136 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4138 *addr
= (uint32_t) (*addr
+ offset64
);
4148 /* Record the address and contents of the memory that will be changed
4149 by the current instruction. Return -1 if something goes wrong, 0
4153 i386_record_lea_modrm (struct i386_record_s
*irp
)
4155 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4158 if (irp
->override
>= 0)
4160 if (record_memory_query
)
4164 target_terminal_ours ();
4166 Process record ignores the memory change of instruction at address %s\n\
4167 because it can't get the value of the segment register.\n\
4168 Do you want to stop the program?"),
4169 paddress (gdbarch
, irp
->orig_addr
));
4170 target_terminal_inferior ();
4178 if (i386_record_lea_modrm_addr (irp
, &addr
))
4181 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
4187 /* Record the effects of a push operation. Return -1 if something
4188 goes wrong, 0 otherwise. */
4191 i386_record_push (struct i386_record_s
*irp
, int size
)
4195 if (record_arch_list_add_reg (irp
->regcache
,
4196 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4198 regcache_raw_read_unsigned (irp
->regcache
,
4199 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4201 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4208 /* Defines contents to record. */
4209 #define I386_SAVE_FPU_REGS 0xfffd
4210 #define I386_SAVE_FPU_ENV 0xfffe
4211 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4213 /* Record the values of the floating point registers which will be
4214 changed by the current instruction. Returns -1 if something is
4215 wrong, 0 otherwise. */
4217 static int i386_record_floats (struct gdbarch
*gdbarch
,
4218 struct i386_record_s
*ir
,
4221 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4224 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4225 happen. Currently we store st0-st7 registers, but we need not store all
4226 registers all the time, in future we use ftag register and record only
4227 those who are not marked as an empty. */
4229 if (I386_SAVE_FPU_REGS
== iregnum
)
4231 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4233 if (record_arch_list_add_reg (ir
->regcache
, i
))
4237 else if (I386_SAVE_FPU_ENV
== iregnum
)
4239 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4241 if (record_arch_list_add_reg (ir
->regcache
, i
))
4245 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4247 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4249 if (record_arch_list_add_reg (ir
->regcache
, i
))
4253 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4254 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4256 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
4261 /* Parameter error. */
4264 if(I386_SAVE_FPU_ENV
!= iregnum
)
4266 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4268 if (record_arch_list_add_reg (ir
->regcache
, i
))
4275 /* Parse the current instruction, and record the values of the
4276 registers and memory that will be changed by the current
4277 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4279 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4280 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4283 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4284 CORE_ADDR input_addr
)
4286 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4292 gdb_byte buf
[MAX_REGISTER_SIZE
];
4293 struct i386_record_s ir
;
4294 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4299 memset (&ir
, 0, sizeof (struct i386_record_s
));
4300 ir
.regcache
= regcache
;
4301 ir
.addr
= input_addr
;
4302 ir
.orig_addr
= input_addr
;
4306 ir
.popl_esp_hack
= 0;
4307 ir
.regmap
= tdep
->record_regmap
;
4308 ir
.gdbarch
= gdbarch
;
4310 if (record_debug
> 1)
4311 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4313 paddress (gdbarch
, ir
.addr
));
4318 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4321 switch (opcode8
) /* Instruction prefixes */
4323 case REPE_PREFIX_OPCODE
:
4324 prefixes
|= PREFIX_REPZ
;
4326 case REPNE_PREFIX_OPCODE
:
4327 prefixes
|= PREFIX_REPNZ
;
4329 case LOCK_PREFIX_OPCODE
:
4330 prefixes
|= PREFIX_LOCK
;
4332 case CS_PREFIX_OPCODE
:
4333 ir
.override
= X86_RECORD_CS_REGNUM
;
4335 case SS_PREFIX_OPCODE
:
4336 ir
.override
= X86_RECORD_SS_REGNUM
;
4338 case DS_PREFIX_OPCODE
:
4339 ir
.override
= X86_RECORD_DS_REGNUM
;
4341 case ES_PREFIX_OPCODE
:
4342 ir
.override
= X86_RECORD_ES_REGNUM
;
4344 case FS_PREFIX_OPCODE
:
4345 ir
.override
= X86_RECORD_FS_REGNUM
;
4347 case GS_PREFIX_OPCODE
:
4348 ir
.override
= X86_RECORD_GS_REGNUM
;
4350 case DATA_PREFIX_OPCODE
:
4351 prefixes
|= PREFIX_DATA
;
4353 case ADDR_PREFIX_OPCODE
:
4354 prefixes
|= PREFIX_ADDR
;
4356 case 0x40: /* i386 inc %eax */
4357 case 0x41: /* i386 inc %ecx */
4358 case 0x42: /* i386 inc %edx */
4359 case 0x43: /* i386 inc %ebx */
4360 case 0x44: /* i386 inc %esp */
4361 case 0x45: /* i386 inc %ebp */
4362 case 0x46: /* i386 inc %esi */
4363 case 0x47: /* i386 inc %edi */
4364 case 0x48: /* i386 dec %eax */
4365 case 0x49: /* i386 dec %ecx */
4366 case 0x4a: /* i386 dec %edx */
4367 case 0x4b: /* i386 dec %ebx */
4368 case 0x4c: /* i386 dec %esp */
4369 case 0x4d: /* i386 dec %ebp */
4370 case 0x4e: /* i386 dec %esi */
4371 case 0x4f: /* i386 dec %edi */
4372 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4376 rex_w
= (opcode8
>> 3) & 1;
4377 rex_r
= (opcode8
& 0x4) << 1;
4378 ir
.rex_x
= (opcode8
& 0x2) << 2;
4379 ir
.rex_b
= (opcode8
& 0x1) << 3;
4381 else /* 32 bit target */
4390 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4396 if (prefixes
& PREFIX_DATA
)
4399 if (prefixes
& PREFIX_ADDR
)
4401 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4404 /* Now check op code. */
4405 opcode
= (uint32_t) opcode8
;
4410 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4413 opcode
= (uint32_t) opcode8
| 0x0f00;
4417 case 0x00: /* arith & logic */
4465 if (((opcode
>> 3) & 7) != OP_CMPL
)
4467 if ((opcode
& 1) == 0)
4470 ir
.ot
= ir
.dflag
+ OT_WORD
;
4472 switch ((opcode
>> 1) & 3)
4474 case 0: /* OP Ev, Gv */
4475 if (i386_record_modrm (&ir
))
4479 if (i386_record_lea_modrm (&ir
))
4485 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4487 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4490 case 1: /* OP Gv, Ev */
4491 if (i386_record_modrm (&ir
))
4494 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4496 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4498 case 2: /* OP A, Iv */
4499 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4506 case 0x80: /* GRP1 */
4510 if (i386_record_modrm (&ir
))
4513 if (ir
.reg
!= OP_CMPL
)
4515 if ((opcode
& 1) == 0)
4518 ir
.ot
= ir
.dflag
+ OT_WORD
;
4525 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4526 if (i386_record_lea_modrm (&ir
))
4530 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4535 case 0x40: /* inc */
4544 case 0x48: /* dec */
4553 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4557 case 0xf6: /* GRP3 */
4559 if ((opcode
& 1) == 0)
4562 ir
.ot
= ir
.dflag
+ OT_WORD
;
4563 if (i386_record_modrm (&ir
))
4566 if (ir
.mod
!= 3 && ir
.reg
== 0)
4567 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4572 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4578 if (i386_record_lea_modrm (&ir
))
4584 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4586 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4588 if (ir
.reg
== 3) /* neg */
4589 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4596 if (ir
.ot
!= OT_BYTE
)
4597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4602 opcode
= opcode
<< 8 | ir
.modrm
;
4608 case 0xfe: /* GRP4 */
4609 case 0xff: /* GRP5 */
4610 if (i386_record_modrm (&ir
))
4612 if (ir
.reg
>= 2 && opcode
== 0xfe)
4615 opcode
= opcode
<< 8 | ir
.modrm
;
4622 if ((opcode
& 1) == 0)
4625 ir
.ot
= ir
.dflag
+ OT_WORD
;
4628 if (i386_record_lea_modrm (&ir
))
4634 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4636 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4638 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4641 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4643 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4645 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4648 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4649 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4655 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4658 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4660 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4665 opcode
= opcode
<< 8 | ir
.modrm
;
4671 case 0x84: /* test */
4675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4678 case 0x98: /* CWDE/CBW */
4679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4682 case 0x99: /* CDQ/CWD */
4683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4687 case 0x0faf: /* imul */
4690 ir
.ot
= ir
.dflag
+ OT_WORD
;
4691 if (i386_record_modrm (&ir
))
4694 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4695 else if (opcode
== 0x6b)
4698 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4700 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4701 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4704 case 0x0fc0: /* xadd */
4706 if ((opcode
& 1) == 0)
4709 ir
.ot
= ir
.dflag
+ OT_WORD
;
4710 if (i386_record_modrm (&ir
))
4715 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4717 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4718 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4720 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4724 if (i386_record_lea_modrm (&ir
))
4726 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4728 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4730 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4733 case 0x0fb0: /* cmpxchg */
4735 if ((opcode
& 1) == 0)
4738 ir
.ot
= ir
.dflag
+ OT_WORD
;
4739 if (i386_record_modrm (&ir
))
4744 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4745 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4747 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4752 if (i386_record_lea_modrm (&ir
))
4755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4758 case 0x0fc7: /* cmpxchg8b */
4759 if (i386_record_modrm (&ir
))
4764 opcode
= opcode
<< 8 | ir
.modrm
;
4767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4769 if (i386_record_lea_modrm (&ir
))
4771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4774 case 0x50: /* push */
4784 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4786 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4790 case 0x06: /* push es */
4791 case 0x0e: /* push cs */
4792 case 0x16: /* push ss */
4793 case 0x1e: /* push ds */
4794 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4799 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4803 case 0x0fa0: /* push fs */
4804 case 0x0fa8: /* push gs */
4805 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4810 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4814 case 0x60: /* pusha */
4815 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4820 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4824 case 0x58: /* pop */
4832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4833 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4836 case 0x61: /* popa */
4837 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4842 for (regnum
= X86_RECORD_REAX_REGNUM
;
4843 regnum
<= X86_RECORD_REDI_REGNUM
;
4845 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4848 case 0x8f: /* pop */
4849 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4850 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4852 ir
.ot
= ir
.dflag
+ OT_WORD
;
4853 if (i386_record_modrm (&ir
))
4856 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4859 ir
.popl_esp_hack
= 1 << ir
.ot
;
4860 if (i386_record_lea_modrm (&ir
))
4863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4866 case 0xc8: /* enter */
4867 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4868 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4870 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4874 case 0xc9: /* leave */
4875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4876 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4879 case 0x07: /* pop es */
4880 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4885 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4886 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4887 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4890 case 0x17: /* pop ss */
4891 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4896 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4901 case 0x1f: /* pop ds */
4902 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4907 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4909 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4912 case 0x0fa1: /* pop fs */
4913 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4914 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4915 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4918 case 0x0fa9: /* pop gs */
4919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4924 case 0x88: /* mov */
4928 if ((opcode
& 1) == 0)
4931 ir
.ot
= ir
.dflag
+ OT_WORD
;
4933 if (i386_record_modrm (&ir
))
4938 if (opcode
== 0xc6 || opcode
== 0xc7)
4939 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4940 if (i386_record_lea_modrm (&ir
))
4945 if (opcode
== 0xc6 || opcode
== 0xc7)
4947 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4949 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4953 case 0x8a: /* mov */
4955 if ((opcode
& 1) == 0)
4958 ir
.ot
= ir
.dflag
+ OT_WORD
;
4959 if (i386_record_modrm (&ir
))
4962 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4964 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4967 case 0x8c: /* mov seg */
4968 if (i386_record_modrm (&ir
))
4973 opcode
= opcode
<< 8 | ir
.modrm
;
4978 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4982 if (i386_record_lea_modrm (&ir
))
4987 case 0x8e: /* mov seg */
4988 if (i386_record_modrm (&ir
))
4993 regnum
= X86_RECORD_ES_REGNUM
;
4996 regnum
= X86_RECORD_SS_REGNUM
;
4999 regnum
= X86_RECORD_DS_REGNUM
;
5002 regnum
= X86_RECORD_FS_REGNUM
;
5005 regnum
= X86_RECORD_GS_REGNUM
;
5009 opcode
= opcode
<< 8 | ir
.modrm
;
5013 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5014 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5017 case 0x0fb6: /* movzbS */
5018 case 0x0fb7: /* movzwS */
5019 case 0x0fbe: /* movsbS */
5020 case 0x0fbf: /* movswS */
5021 if (i386_record_modrm (&ir
))
5023 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5026 case 0x8d: /* lea */
5027 if (i386_record_modrm (&ir
))
5032 opcode
= opcode
<< 8 | ir
.modrm
;
5037 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5039 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5042 case 0xa0: /* mov EAX */
5045 case 0xd7: /* xlat */
5046 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5049 case 0xa2: /* mov EAX */
5051 if (ir
.override
>= 0)
5053 if (record_memory_query
)
5057 target_terminal_ours ();
5059 Process record ignores the memory change of instruction at address %s\n\
5060 because it can't get the value of the segment register.\n\
5061 Do you want to stop the program?"),
5062 paddress (gdbarch
, ir
.orig_addr
));
5063 target_terminal_inferior ();
5070 if ((opcode
& 1) == 0)
5073 ir
.ot
= ir
.dflag
+ OT_WORD
;
5076 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5079 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5083 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5086 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5090 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5093 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5095 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5100 case 0xb0: /* mov R, Ib */
5108 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5109 ? ((opcode
& 0x7) | ir
.rex_b
)
5110 : ((opcode
& 0x7) & 0x3));
5113 case 0xb8: /* mov R, Iv */
5121 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5124 case 0x91: /* xchg R, EAX */
5131 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5132 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
5135 case 0x86: /* xchg Ev, Gv */
5137 if ((opcode
& 1) == 0)
5140 ir
.ot
= ir
.dflag
+ OT_WORD
;
5141 if (i386_record_modrm (&ir
))
5146 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5148 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5152 if (i386_record_lea_modrm (&ir
))
5156 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5158 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5161 case 0xc4: /* les Gv */
5162 case 0xc5: /* lds Gv */
5163 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5169 case 0x0fb2: /* lss Gv */
5170 case 0x0fb4: /* lfs Gv */
5171 case 0x0fb5: /* lgs Gv */
5172 if (i386_record_modrm (&ir
))
5180 opcode
= opcode
<< 8 | ir
.modrm
;
5185 case 0xc4: /* les Gv */
5186 regnum
= X86_RECORD_ES_REGNUM
;
5188 case 0xc5: /* lds Gv */
5189 regnum
= X86_RECORD_DS_REGNUM
;
5191 case 0x0fb2: /* lss Gv */
5192 regnum
= X86_RECORD_SS_REGNUM
;
5194 case 0x0fb4: /* lfs Gv */
5195 regnum
= X86_RECORD_FS_REGNUM
;
5197 case 0x0fb5: /* lgs Gv */
5198 regnum
= X86_RECORD_GS_REGNUM
;
5201 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5202 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5203 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5206 case 0xc0: /* shifts */
5212 if ((opcode
& 1) == 0)
5215 ir
.ot
= ir
.dflag
+ OT_WORD
;
5216 if (i386_record_modrm (&ir
))
5218 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5220 if (i386_record_lea_modrm (&ir
))
5226 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5228 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5230 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5237 if (i386_record_modrm (&ir
))
5241 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5246 if (i386_record_lea_modrm (&ir
))
5251 case 0xd8: /* Floats. */
5259 if (i386_record_modrm (&ir
))
5261 ir
.reg
|= ((opcode
& 7) << 3);
5267 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5275 /* For fcom, ficom nothing to do. */
5281 /* For fcomp, ficomp pop FPU stack, store all. */
5282 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5309 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5310 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5311 of code, always affects st(0) register. */
5312 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5336 /* Handling fld, fild. */
5337 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5341 switch (ir
.reg
>> 4)
5344 if (record_arch_list_add_mem (addr64
, 4))
5348 if (record_arch_list_add_mem (addr64
, 8))
5354 if (record_arch_list_add_mem (addr64
, 2))
5360 switch (ir
.reg
>> 4)
5363 if (record_arch_list_add_mem (addr64
, 4))
5365 if (3 == (ir
.reg
& 7))
5367 /* For fstp m32fp. */
5368 if (i386_record_floats (gdbarch
, &ir
,
5369 I386_SAVE_FPU_REGS
))
5374 if (record_arch_list_add_mem (addr64
, 4))
5376 if ((3 == (ir
.reg
& 7))
5377 || (5 == (ir
.reg
& 7))
5378 || (7 == (ir
.reg
& 7)))
5380 /* For fstp insn. */
5381 if (i386_record_floats (gdbarch
, &ir
,
5382 I386_SAVE_FPU_REGS
))
5387 if (record_arch_list_add_mem (addr64
, 8))
5389 if (3 == (ir
.reg
& 7))
5391 /* For fstp m64fp. */
5392 if (i386_record_floats (gdbarch
, &ir
,
5393 I386_SAVE_FPU_REGS
))
5398 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5400 /* For fistp, fbld, fild, fbstp. */
5401 if (i386_record_floats (gdbarch
, &ir
,
5402 I386_SAVE_FPU_REGS
))
5407 if (record_arch_list_add_mem (addr64
, 2))
5416 if (i386_record_floats (gdbarch
, &ir
,
5417 I386_SAVE_FPU_ENV_REG_STACK
))
5422 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5427 if (i386_record_floats (gdbarch
, &ir
,
5428 I386_SAVE_FPU_ENV_REG_STACK
))
5434 if (record_arch_list_add_mem (addr64
, 28))
5439 if (record_arch_list_add_mem (addr64
, 14))
5445 if (record_arch_list_add_mem (addr64
, 2))
5447 /* Insn fstp, fbstp. */
5448 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5453 if (record_arch_list_add_mem (addr64
, 10))
5459 if (record_arch_list_add_mem (addr64
, 28))
5465 if (record_arch_list_add_mem (addr64
, 14))
5469 if (record_arch_list_add_mem (addr64
, 80))
5472 if (i386_record_floats (gdbarch
, &ir
,
5473 I386_SAVE_FPU_ENV_REG_STACK
))
5477 if (record_arch_list_add_mem (addr64
, 8))
5480 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5485 opcode
= opcode
<< 8 | ir
.modrm
;
5490 /* Opcode is an extension of modR/M byte. */
5496 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5500 if (0x0c == (ir
.modrm
>> 4))
5502 if ((ir
.modrm
& 0x0f) <= 7)
5504 if (i386_record_floats (gdbarch
, &ir
,
5505 I386_SAVE_FPU_REGS
))
5510 if (i386_record_floats (gdbarch
, &ir
,
5511 I387_ST0_REGNUM (tdep
)))
5513 /* If only st(0) is changing, then we have already
5515 if ((ir
.modrm
& 0x0f) - 0x08)
5517 if (i386_record_floats (gdbarch
, &ir
,
5518 I387_ST0_REGNUM (tdep
) +
5519 ((ir
.modrm
& 0x0f) - 0x08)))
5537 if (i386_record_floats (gdbarch
, &ir
,
5538 I387_ST0_REGNUM (tdep
)))
5556 if (i386_record_floats (gdbarch
, &ir
,
5557 I386_SAVE_FPU_REGS
))
5561 if (i386_record_floats (gdbarch
, &ir
,
5562 I387_ST0_REGNUM (tdep
)))
5564 if (i386_record_floats (gdbarch
, &ir
,
5565 I387_ST0_REGNUM (tdep
) + 1))
5572 if (0xe9 == ir
.modrm
)
5574 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5577 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5579 if (i386_record_floats (gdbarch
, &ir
,
5580 I387_ST0_REGNUM (tdep
)))
5582 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5584 if (i386_record_floats (gdbarch
, &ir
,
5585 I387_ST0_REGNUM (tdep
) +
5589 else if ((ir
.modrm
& 0x0f) - 0x08)
5591 if (i386_record_floats (gdbarch
, &ir
,
5592 I387_ST0_REGNUM (tdep
) +
5593 ((ir
.modrm
& 0x0f) - 0x08)))
5599 if (0xe3 == ir
.modrm
)
5601 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5604 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5606 if (i386_record_floats (gdbarch
, &ir
,
5607 I387_ST0_REGNUM (tdep
)))
5609 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5611 if (i386_record_floats (gdbarch
, &ir
,
5612 I387_ST0_REGNUM (tdep
) +
5616 else if ((ir
.modrm
& 0x0f) - 0x08)
5618 if (i386_record_floats (gdbarch
, &ir
,
5619 I387_ST0_REGNUM (tdep
) +
5620 ((ir
.modrm
& 0x0f) - 0x08)))
5626 if ((0x0c == ir
.modrm
>> 4)
5627 || (0x0d == ir
.modrm
>> 4)
5628 || (0x0f == ir
.modrm
>> 4))
5630 if ((ir
.modrm
& 0x0f) <= 7)
5632 if (i386_record_floats (gdbarch
, &ir
,
5633 I387_ST0_REGNUM (tdep
) +
5639 if (i386_record_floats (gdbarch
, &ir
,
5640 I387_ST0_REGNUM (tdep
) +
5641 ((ir
.modrm
& 0x0f) - 0x08)))
5647 if (0x0c == ir
.modrm
>> 4)
5649 if (i386_record_floats (gdbarch
, &ir
,
5650 I387_FTAG_REGNUM (tdep
)))
5653 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5655 if ((ir
.modrm
& 0x0f) <= 7)
5657 if (i386_record_floats (gdbarch
, &ir
,
5658 I387_ST0_REGNUM (tdep
) +
5664 if (i386_record_floats (gdbarch
, &ir
,
5665 I386_SAVE_FPU_REGS
))
5671 if ((0x0c == ir
.modrm
>> 4)
5672 || (0x0e == ir
.modrm
>> 4)
5673 || (0x0f == ir
.modrm
>> 4)
5674 || (0xd9 == ir
.modrm
))
5676 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5681 if (0xe0 == ir
.modrm
)
5683 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5686 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5688 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5696 case 0xa4: /* movsS */
5698 case 0xaa: /* stosS */
5700 case 0x6c: /* insS */
5702 regcache_raw_read_unsigned (ir
.regcache
,
5703 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5709 if ((opcode
& 1) == 0)
5712 ir
.ot
= ir
.dflag
+ OT_WORD
;
5713 regcache_raw_read_unsigned (ir
.regcache
,
5714 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5717 regcache_raw_read_unsigned (ir
.regcache
,
5718 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5720 regcache_raw_read_unsigned (ir
.regcache
,
5721 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5723 if (ir
.aflag
&& (es
!= ds
))
5725 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5726 if (record_memory_query
)
5730 target_terminal_ours ();
5732 Process record ignores the memory change of instruction at address %s\n\
5733 because it can't get the value of the segment register.\n\
5734 Do you want to stop the program?"),
5735 paddress (gdbarch
, ir
.orig_addr
));
5736 target_terminal_inferior ();
5743 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5747 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5749 if (opcode
== 0xa4 || opcode
== 0xa5)
5750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5752 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5756 case 0xa6: /* cmpsS */
5758 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5760 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5762 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5765 case 0xac: /* lodsS */
5767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5769 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5770 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5774 case 0xae: /* scasS */
5776 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5777 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5778 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5779 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5782 case 0x6e: /* outsS */
5784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5785 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5786 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5790 case 0xe4: /* port I/O */
5794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5805 case 0xc2: /* ret im */
5806 case 0xc3: /* ret */
5807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5811 case 0xca: /* lret im */
5812 case 0xcb: /* lret */
5813 case 0xcf: /* iret */
5814 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5819 case 0xe8: /* call im */
5820 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5822 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5826 case 0x9a: /* lcall im */
5827 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5833 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5837 case 0xe9: /* jmp im */
5838 case 0xea: /* ljmp im */
5839 case 0xeb: /* jmp Jb */
5840 case 0x70: /* jcc Jb */
5856 case 0x0f80: /* jcc Jv */
5874 case 0x0f90: /* setcc Gv */
5890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5892 if (i386_record_modrm (&ir
))
5895 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5899 if (i386_record_lea_modrm (&ir
))
5904 case 0x0f40: /* cmov Gv, Ev */
5920 if (i386_record_modrm (&ir
))
5923 if (ir
.dflag
== OT_BYTE
)
5925 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5929 case 0x9c: /* pushf */
5930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5931 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5933 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5937 case 0x9d: /* popf */
5938 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5942 case 0x9e: /* sahf */
5943 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5949 case 0xf5: /* cmc */
5950 case 0xf8: /* clc */
5951 case 0xf9: /* stc */
5952 case 0xfc: /* cld */
5953 case 0xfd: /* std */
5954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5957 case 0x9f: /* lahf */
5958 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5967 /* bit operations */
5968 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5969 ir
.ot
= ir
.dflag
+ OT_WORD
;
5970 if (i386_record_modrm (&ir
))
5975 opcode
= opcode
<< 8 | ir
.modrm
;
5981 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5984 if (i386_record_lea_modrm (&ir
))
5988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5991 case 0x0fa3: /* bt Gv, Ev */
5992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5995 case 0x0fab: /* bts */
5996 case 0x0fb3: /* btr */
5997 case 0x0fbb: /* btc */
5998 ir
.ot
= ir
.dflag
+ OT_WORD
;
5999 if (i386_record_modrm (&ir
))
6002 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6006 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6008 regcache_raw_read_unsigned (ir
.regcache
,
6009 ir
.regmap
[ir
.reg
| rex_r
],
6014 addr64
+= ((int16_t) addr
>> 4) << 4;
6017 addr64
+= ((int32_t) addr
>> 5) << 5;
6020 addr64
+= ((int64_t) addr
>> 6) << 6;
6023 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6025 if (i386_record_lea_modrm (&ir
))
6028 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6031 case 0x0fbc: /* bsf */
6032 case 0x0fbd: /* bsr */
6033 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6034 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6038 case 0x27: /* daa */
6039 case 0x2f: /* das */
6040 case 0x37: /* aaa */
6041 case 0x3f: /* aas */
6042 case 0xd4: /* aam */
6043 case 0xd5: /* aad */
6044 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6050 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6054 case 0x90: /* nop */
6055 if (prefixes
& PREFIX_LOCK
)
6062 case 0x9b: /* fwait */
6063 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6065 opcode
= (uint32_t) opcode8
;
6071 case 0xcc: /* int3 */
6072 printf_unfiltered (_("Process record does not support instruction "
6079 case 0xcd: /* int */
6083 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6086 if (interrupt
!= 0x80
6087 || tdep
->i386_intx80_record
== NULL
)
6089 printf_unfiltered (_("Process record does not support "
6090 "instruction int 0x%02x.\n"),
6095 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6102 case 0xce: /* into */
6103 printf_unfiltered (_("Process record does not support "
6104 "instruction into.\n"));
6109 case 0xfa: /* cli */
6110 case 0xfb: /* sti */
6113 case 0x62: /* bound */
6114 printf_unfiltered (_("Process record does not support "
6115 "instruction bound.\n"));
6120 case 0x0fc8: /* bswap reg */
6128 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6131 case 0xd6: /* salc */
6132 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6137 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6138 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6141 case 0xe0: /* loopnz */
6142 case 0xe1: /* loopz */
6143 case 0xe2: /* loop */
6144 case 0xe3: /* jecxz */
6145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6149 case 0x0f30: /* wrmsr */
6150 printf_unfiltered (_("Process record does not support "
6151 "instruction wrmsr.\n"));
6156 case 0x0f32: /* rdmsr */
6157 printf_unfiltered (_("Process record does not support "
6158 "instruction rdmsr.\n"));
6163 case 0x0f31: /* rdtsc */
6164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6165 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6168 case 0x0f34: /* sysenter */
6171 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6176 if (tdep
->i386_sysenter_record
== NULL
)
6178 printf_unfiltered (_("Process record does not support "
6179 "instruction sysenter.\n"));
6183 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6189 case 0x0f35: /* sysexit */
6190 printf_unfiltered (_("Process record does not support "
6191 "instruction sysexit.\n"));
6196 case 0x0f05: /* syscall */
6199 if (tdep
->i386_syscall_record
== NULL
)
6201 printf_unfiltered (_("Process record does not support "
6202 "instruction syscall.\n"));
6206 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6212 case 0x0f07: /* sysret */
6213 printf_unfiltered (_("Process record does not support "
6214 "instruction sysret.\n"));
6219 case 0x0fa2: /* cpuid */
6220 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6221 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6222 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6223 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6226 case 0xf4: /* hlt */
6227 printf_unfiltered (_("Process record does not support "
6228 "instruction hlt.\n"));
6234 if (i386_record_modrm (&ir
))
6241 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6245 if (i386_record_lea_modrm (&ir
))
6254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6258 opcode
= opcode
<< 8 | ir
.modrm
;
6265 if (i386_record_modrm (&ir
))
6276 opcode
= opcode
<< 8 | ir
.modrm
;
6279 if (ir
.override
>= 0)
6281 if (record_memory_query
)
6285 target_terminal_ours ();
6287 Process record ignores the memory change of instruction at address %s\n\
6288 because it can't get the value of the segment register.\n\
6289 Do you want to stop the program?"),
6290 paddress (gdbarch
, ir
.orig_addr
));
6291 target_terminal_inferior ();
6298 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6300 if (record_arch_list_add_mem (addr64
, 2))
6303 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6305 if (record_arch_list_add_mem (addr64
, 8))
6310 if (record_arch_list_add_mem (addr64
, 4))
6321 case 0: /* monitor */
6324 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6328 opcode
= opcode
<< 8 | ir
.modrm
;
6336 if (ir
.override
>= 0)
6338 if (record_memory_query
)
6342 target_terminal_ours ();
6344 Process record ignores the memory change of instruction at address %s\n\
6345 because it can't get the value of the segment register.\n\
6346 Do you want to stop the program?"),
6347 paddress (gdbarch
, ir
.orig_addr
));
6348 target_terminal_inferior ();
6357 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6359 if (record_arch_list_add_mem (addr64
, 2))
6362 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6364 if (record_arch_list_add_mem (addr64
, 8))
6369 if (record_arch_list_add_mem (addr64
, 4))
6381 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6382 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6386 else if (ir
.rm
== 1)
6393 opcode
= opcode
<< 8 | ir
.modrm
;
6400 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6406 if (i386_record_lea_modrm (&ir
))
6409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6412 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6414 case 7: /* invlpg */
6417 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6418 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6422 opcode
= opcode
<< 8 | ir
.modrm
;
6427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6431 opcode
= opcode
<< 8 | ir
.modrm
;
6437 case 0x0f08: /* invd */
6438 case 0x0f09: /* wbinvd */
6441 case 0x63: /* arpl */
6442 if (i386_record_modrm (&ir
))
6444 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6446 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6447 ? (ir
.reg
| rex_r
) : ir
.rm
);
6451 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6452 if (i386_record_lea_modrm (&ir
))
6455 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6456 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6459 case 0x0f02: /* lar */
6460 case 0x0f03: /* lsl */
6461 if (i386_record_modrm (&ir
))
6463 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6464 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6468 if (i386_record_modrm (&ir
))
6470 if (ir
.mod
== 3 && ir
.reg
== 3)
6473 opcode
= opcode
<< 8 | ir
.modrm
;
6485 /* nop (multi byte) */
6488 case 0x0f20: /* mov reg, crN */
6489 case 0x0f22: /* mov crN, reg */
6490 if (i386_record_modrm (&ir
))
6492 if ((ir
.modrm
& 0xc0) != 0xc0)
6495 opcode
= opcode
<< 8 | ir
.modrm
;
6506 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6508 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6512 opcode
= opcode
<< 8 | ir
.modrm
;
6518 case 0x0f21: /* mov reg, drN */
6519 case 0x0f23: /* mov drN, reg */
6520 if (i386_record_modrm (&ir
))
6522 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6523 || ir
.reg
== 5 || ir
.reg
>= 8)
6526 opcode
= opcode
<< 8 | ir
.modrm
;
6530 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6532 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6535 case 0x0f06: /* clts */
6536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6539 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6541 case 0x0f0d: /* 3DNow! prefetch */
6544 case 0x0f0e: /* 3DNow! femms */
6545 case 0x0f77: /* emms */
6546 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6548 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6551 case 0x0f0f: /* 3DNow! data */
6552 if (i386_record_modrm (&ir
))
6554 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6559 case 0x0c: /* 3DNow! pi2fw */
6560 case 0x0d: /* 3DNow! pi2fd */
6561 case 0x1c: /* 3DNow! pf2iw */
6562 case 0x1d: /* 3DNow! pf2id */
6563 case 0x8a: /* 3DNow! pfnacc */
6564 case 0x8e: /* 3DNow! pfpnacc */
6565 case 0x90: /* 3DNow! pfcmpge */
6566 case 0x94: /* 3DNow! pfmin */
6567 case 0x96: /* 3DNow! pfrcp */
6568 case 0x97: /* 3DNow! pfrsqrt */
6569 case 0x9a: /* 3DNow! pfsub */
6570 case 0x9e: /* 3DNow! pfadd */
6571 case 0xa0: /* 3DNow! pfcmpgt */
6572 case 0xa4: /* 3DNow! pfmax */
6573 case 0xa6: /* 3DNow! pfrcpit1 */
6574 case 0xa7: /* 3DNow! pfrsqit1 */
6575 case 0xaa: /* 3DNow! pfsubr */
6576 case 0xae: /* 3DNow! pfacc */
6577 case 0xb0: /* 3DNow! pfcmpeq */
6578 case 0xb4: /* 3DNow! pfmul */
6579 case 0xb6: /* 3DNow! pfrcpit2 */
6580 case 0xb7: /* 3DNow! pmulhrw */
6581 case 0xbb: /* 3DNow! pswapd */
6582 case 0xbf: /* 3DNow! pavgusb */
6583 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6584 goto no_support_3dnow_data
;
6585 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6589 no_support_3dnow_data
:
6590 opcode
= (opcode
<< 8) | opcode8
;
6596 case 0x0faa: /* rsm */
6597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6600 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6604 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6609 if (i386_record_modrm (&ir
))
6613 case 0: /* fxsave */
6617 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6618 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6620 if (record_arch_list_add_mem (tmpu64
, 512))
6625 case 1: /* fxrstor */
6629 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6631 for (i
= I387_MM0_REGNUM (tdep
);
6632 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6633 record_arch_list_add_reg (ir
.regcache
, i
);
6635 for (i
= I387_XMM0_REGNUM (tdep
);
6636 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6637 record_arch_list_add_reg (ir
.regcache
, i
);
6639 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6640 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6642 for (i
= I387_ST0_REGNUM (tdep
);
6643 i386_fp_regnum_p (gdbarch
, i
); i
++)
6644 record_arch_list_add_reg (ir
.regcache
, i
);
6646 for (i
= I387_FCTRL_REGNUM (tdep
);
6647 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6648 record_arch_list_add_reg (ir
.regcache
, i
);
6652 case 2: /* ldmxcsr */
6653 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6655 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6658 case 3: /* stmxcsr */
6660 if (i386_record_lea_modrm (&ir
))
6664 case 5: /* lfence */
6665 case 6: /* mfence */
6666 case 7: /* sfence clflush */
6670 opcode
= (opcode
<< 8) | ir
.modrm
;
6676 case 0x0fc3: /* movnti */
6677 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6678 if (i386_record_modrm (&ir
))
6683 if (i386_record_lea_modrm (&ir
))
6687 /* Add prefix to opcode. */
6814 reswitch_prefix_add
:
6822 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6825 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6826 goto reswitch_prefix_add
;
6829 case 0x0f10: /* movups */
6830 case 0x660f10: /* movupd */
6831 case 0xf30f10: /* movss */
6832 case 0xf20f10: /* movsd */
6833 case 0x0f12: /* movlps */
6834 case 0x660f12: /* movlpd */
6835 case 0xf30f12: /* movsldup */
6836 case 0xf20f12: /* movddup */
6837 case 0x0f14: /* unpcklps */
6838 case 0x660f14: /* unpcklpd */
6839 case 0x0f15: /* unpckhps */
6840 case 0x660f15: /* unpckhpd */
6841 case 0x0f16: /* movhps */
6842 case 0x660f16: /* movhpd */
6843 case 0xf30f16: /* movshdup */
6844 case 0x0f28: /* movaps */
6845 case 0x660f28: /* movapd */
6846 case 0x0f2a: /* cvtpi2ps */
6847 case 0x660f2a: /* cvtpi2pd */
6848 case 0xf30f2a: /* cvtsi2ss */
6849 case 0xf20f2a: /* cvtsi2sd */
6850 case 0x0f2c: /* cvttps2pi */
6851 case 0x660f2c: /* cvttpd2pi */
6852 case 0x0f2d: /* cvtps2pi */
6853 case 0x660f2d: /* cvtpd2pi */
6854 case 0x660f3800: /* pshufb */
6855 case 0x660f3801: /* phaddw */
6856 case 0x660f3802: /* phaddd */
6857 case 0x660f3803: /* phaddsw */
6858 case 0x660f3804: /* pmaddubsw */
6859 case 0x660f3805: /* phsubw */
6860 case 0x660f3806: /* phsubd */
6861 case 0x660f3807: /* phsubsw */
6862 case 0x660f3808: /* psignb */
6863 case 0x660f3809: /* psignw */
6864 case 0x660f380a: /* psignd */
6865 case 0x660f380b: /* pmulhrsw */
6866 case 0x660f3810: /* pblendvb */
6867 case 0x660f3814: /* blendvps */
6868 case 0x660f3815: /* blendvpd */
6869 case 0x660f381c: /* pabsb */
6870 case 0x660f381d: /* pabsw */
6871 case 0x660f381e: /* pabsd */
6872 case 0x660f3820: /* pmovsxbw */
6873 case 0x660f3821: /* pmovsxbd */
6874 case 0x660f3822: /* pmovsxbq */
6875 case 0x660f3823: /* pmovsxwd */
6876 case 0x660f3824: /* pmovsxwq */
6877 case 0x660f3825: /* pmovsxdq */
6878 case 0x660f3828: /* pmuldq */
6879 case 0x660f3829: /* pcmpeqq */
6880 case 0x660f382a: /* movntdqa */
6881 case 0x660f3a08: /* roundps */
6882 case 0x660f3a09: /* roundpd */
6883 case 0x660f3a0a: /* roundss */
6884 case 0x660f3a0b: /* roundsd */
6885 case 0x660f3a0c: /* blendps */
6886 case 0x660f3a0d: /* blendpd */
6887 case 0x660f3a0e: /* pblendw */
6888 case 0x660f3a0f: /* palignr */
6889 case 0x660f3a20: /* pinsrb */
6890 case 0x660f3a21: /* insertps */
6891 case 0x660f3a22: /* pinsrd pinsrq */
6892 case 0x660f3a40: /* dpps */
6893 case 0x660f3a41: /* dppd */
6894 case 0x660f3a42: /* mpsadbw */
6895 case 0x660f3a60: /* pcmpestrm */
6896 case 0x660f3a61: /* pcmpestri */
6897 case 0x660f3a62: /* pcmpistrm */
6898 case 0x660f3a63: /* pcmpistri */
6899 case 0x0f51: /* sqrtps */
6900 case 0x660f51: /* sqrtpd */
6901 case 0xf20f51: /* sqrtsd */
6902 case 0xf30f51: /* sqrtss */
6903 case 0x0f52: /* rsqrtps */
6904 case 0xf30f52: /* rsqrtss */
6905 case 0x0f53: /* rcpps */
6906 case 0xf30f53: /* rcpss */
6907 case 0x0f54: /* andps */
6908 case 0x660f54: /* andpd */
6909 case 0x0f55: /* andnps */
6910 case 0x660f55: /* andnpd */
6911 case 0x0f56: /* orps */
6912 case 0x660f56: /* orpd */
6913 case 0x0f57: /* xorps */
6914 case 0x660f57: /* xorpd */
6915 case 0x0f58: /* addps */
6916 case 0x660f58: /* addpd */
6917 case 0xf20f58: /* addsd */
6918 case 0xf30f58: /* addss */
6919 case 0x0f59: /* mulps */
6920 case 0x660f59: /* mulpd */
6921 case 0xf20f59: /* mulsd */
6922 case 0xf30f59: /* mulss */
6923 case 0x0f5a: /* cvtps2pd */
6924 case 0x660f5a: /* cvtpd2ps */
6925 case 0xf20f5a: /* cvtsd2ss */
6926 case 0xf30f5a: /* cvtss2sd */
6927 case 0x0f5b: /* cvtdq2ps */
6928 case 0x660f5b: /* cvtps2dq */
6929 case 0xf30f5b: /* cvttps2dq */
6930 case 0x0f5c: /* subps */
6931 case 0x660f5c: /* subpd */
6932 case 0xf20f5c: /* subsd */
6933 case 0xf30f5c: /* subss */
6934 case 0x0f5d: /* minps */
6935 case 0x660f5d: /* minpd */
6936 case 0xf20f5d: /* minsd */
6937 case 0xf30f5d: /* minss */
6938 case 0x0f5e: /* divps */
6939 case 0x660f5e: /* divpd */
6940 case 0xf20f5e: /* divsd */
6941 case 0xf30f5e: /* divss */
6942 case 0x0f5f: /* maxps */
6943 case 0x660f5f: /* maxpd */
6944 case 0xf20f5f: /* maxsd */
6945 case 0xf30f5f: /* maxss */
6946 case 0x660f60: /* punpcklbw */
6947 case 0x660f61: /* punpcklwd */
6948 case 0x660f62: /* punpckldq */
6949 case 0x660f63: /* packsswb */
6950 case 0x660f64: /* pcmpgtb */
6951 case 0x660f65: /* pcmpgtw */
6952 case 0x660f66: /* pcmpgtd */
6953 case 0x660f67: /* packuswb */
6954 case 0x660f68: /* punpckhbw */
6955 case 0x660f69: /* punpckhwd */
6956 case 0x660f6a: /* punpckhdq */
6957 case 0x660f6b: /* packssdw */
6958 case 0x660f6c: /* punpcklqdq */
6959 case 0x660f6d: /* punpckhqdq */
6960 case 0x660f6e: /* movd */
6961 case 0x660f6f: /* movdqa */
6962 case 0xf30f6f: /* movdqu */
6963 case 0x660f70: /* pshufd */
6964 case 0xf20f70: /* pshuflw */
6965 case 0xf30f70: /* pshufhw */
6966 case 0x660f74: /* pcmpeqb */
6967 case 0x660f75: /* pcmpeqw */
6968 case 0x660f76: /* pcmpeqd */
6969 case 0x660f7c: /* haddpd */
6970 case 0xf20f7c: /* haddps */
6971 case 0x660f7d: /* hsubpd */
6972 case 0xf20f7d: /* hsubps */
6973 case 0xf30f7e: /* movq */
6974 case 0x0fc2: /* cmpps */
6975 case 0x660fc2: /* cmppd */
6976 case 0xf20fc2: /* cmpsd */
6977 case 0xf30fc2: /* cmpss */
6978 case 0x660fc4: /* pinsrw */
6979 case 0x0fc6: /* shufps */
6980 case 0x660fc6: /* shufpd */
6981 case 0x660fd0: /* addsubpd */
6982 case 0xf20fd0: /* addsubps */
6983 case 0x660fd1: /* psrlw */
6984 case 0x660fd2: /* psrld */
6985 case 0x660fd3: /* psrlq */
6986 case 0x660fd4: /* paddq */
6987 case 0x660fd5: /* pmullw */
6988 case 0xf30fd6: /* movq2dq */
6989 case 0x660fd8: /* psubusb */
6990 case 0x660fd9: /* psubusw */
6991 case 0x660fda: /* pminub */
6992 case 0x660fdb: /* pand */
6993 case 0x660fdc: /* paddusb */
6994 case 0x660fdd: /* paddusw */
6995 case 0x660fde: /* pmaxub */
6996 case 0x660fdf: /* pandn */
6997 case 0x660fe0: /* pavgb */
6998 case 0x660fe1: /* psraw */
6999 case 0x660fe2: /* psrad */
7000 case 0x660fe3: /* pavgw */
7001 case 0x660fe4: /* pmulhuw */
7002 case 0x660fe5: /* pmulhw */
7003 case 0x660fe6: /* cvttpd2dq */
7004 case 0xf20fe6: /* cvtpd2dq */
7005 case 0xf30fe6: /* cvtdq2pd */
7006 case 0x660fe8: /* psubsb */
7007 case 0x660fe9: /* psubsw */
7008 case 0x660fea: /* pminsw */
7009 case 0x660feb: /* por */
7010 case 0x660fec: /* paddsb */
7011 case 0x660fed: /* paddsw */
7012 case 0x660fee: /* pmaxsw */
7013 case 0x660fef: /* pxor */
7014 case 0xf20ff0: /* lddqu */
7015 case 0x660ff1: /* psllw */
7016 case 0x660ff2: /* pslld */
7017 case 0x660ff3: /* psllq */
7018 case 0x660ff4: /* pmuludq */
7019 case 0x660ff5: /* pmaddwd */
7020 case 0x660ff6: /* psadbw */
7021 case 0x660ff8: /* psubb */
7022 case 0x660ff9: /* psubw */
7023 case 0x660ffa: /* psubd */
7024 case 0x660ffb: /* psubq */
7025 case 0x660ffc: /* paddb */
7026 case 0x660ffd: /* paddw */
7027 case 0x660ffe: /* paddd */
7028 if (i386_record_modrm (&ir
))
7031 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7033 record_arch_list_add_reg (ir
.regcache
,
7034 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7035 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7036 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7039 case 0x0f11: /* movups */
7040 case 0x660f11: /* movupd */
7041 case 0xf30f11: /* movss */
7042 case 0xf20f11: /* movsd */
7043 case 0x0f13: /* movlps */
7044 case 0x660f13: /* movlpd */
7045 case 0x0f17: /* movhps */
7046 case 0x660f17: /* movhpd */
7047 case 0x0f29: /* movaps */
7048 case 0x660f29: /* movapd */
7049 case 0x660f3a14: /* pextrb */
7050 case 0x660f3a15: /* pextrw */
7051 case 0x660f3a16: /* pextrd pextrq */
7052 case 0x660f3a17: /* extractps */
7053 case 0x660f7f: /* movdqa */
7054 case 0xf30f7f: /* movdqu */
7055 if (i386_record_modrm (&ir
))
7059 if (opcode
== 0x0f13 || opcode
== 0x660f13
7060 || opcode
== 0x0f17 || opcode
== 0x660f17)
7063 if (!i386_xmm_regnum_p (gdbarch
,
7064 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7066 record_arch_list_add_reg (ir
.regcache
,
7067 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7089 if (i386_record_lea_modrm (&ir
))
7094 case 0x0f2b: /* movntps */
7095 case 0x660f2b: /* movntpd */
7096 case 0x0fe7: /* movntq */
7097 case 0x660fe7: /* movntdq */
7100 if (opcode
== 0x0fe7)
7104 if (i386_record_lea_modrm (&ir
))
7108 case 0xf30f2c: /* cvttss2si */
7109 case 0xf20f2c: /* cvttsd2si */
7110 case 0xf30f2d: /* cvtss2si */
7111 case 0xf20f2d: /* cvtsd2si */
7112 case 0xf20f38f0: /* crc32 */
7113 case 0xf20f38f1: /* crc32 */
7114 case 0x0f50: /* movmskps */
7115 case 0x660f50: /* movmskpd */
7116 case 0x0fc5: /* pextrw */
7117 case 0x660fc5: /* pextrw */
7118 case 0x0fd7: /* pmovmskb */
7119 case 0x660fd7: /* pmovmskb */
7120 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7123 case 0x0f3800: /* pshufb */
7124 case 0x0f3801: /* phaddw */
7125 case 0x0f3802: /* phaddd */
7126 case 0x0f3803: /* phaddsw */
7127 case 0x0f3804: /* pmaddubsw */
7128 case 0x0f3805: /* phsubw */
7129 case 0x0f3806: /* phsubd */
7130 case 0x0f3807: /* phsubsw */
7131 case 0x0f3808: /* psignb */
7132 case 0x0f3809: /* psignw */
7133 case 0x0f380a: /* psignd */
7134 case 0x0f380b: /* pmulhrsw */
7135 case 0x0f381c: /* pabsb */
7136 case 0x0f381d: /* pabsw */
7137 case 0x0f381e: /* pabsd */
7138 case 0x0f382b: /* packusdw */
7139 case 0x0f3830: /* pmovzxbw */
7140 case 0x0f3831: /* pmovzxbd */
7141 case 0x0f3832: /* pmovzxbq */
7142 case 0x0f3833: /* pmovzxwd */
7143 case 0x0f3834: /* pmovzxwq */
7144 case 0x0f3835: /* pmovzxdq */
7145 case 0x0f3837: /* pcmpgtq */
7146 case 0x0f3838: /* pminsb */
7147 case 0x0f3839: /* pminsd */
7148 case 0x0f383a: /* pminuw */
7149 case 0x0f383b: /* pminud */
7150 case 0x0f383c: /* pmaxsb */
7151 case 0x0f383d: /* pmaxsd */
7152 case 0x0f383e: /* pmaxuw */
7153 case 0x0f383f: /* pmaxud */
7154 case 0x0f3840: /* pmulld */
7155 case 0x0f3841: /* phminposuw */
7156 case 0x0f3a0f: /* palignr */
7157 case 0x0f60: /* punpcklbw */
7158 case 0x0f61: /* punpcklwd */
7159 case 0x0f62: /* punpckldq */
7160 case 0x0f63: /* packsswb */
7161 case 0x0f64: /* pcmpgtb */
7162 case 0x0f65: /* pcmpgtw */
7163 case 0x0f66: /* pcmpgtd */
7164 case 0x0f67: /* packuswb */
7165 case 0x0f68: /* punpckhbw */
7166 case 0x0f69: /* punpckhwd */
7167 case 0x0f6a: /* punpckhdq */
7168 case 0x0f6b: /* packssdw */
7169 case 0x0f6e: /* movd */
7170 case 0x0f6f: /* movq */
7171 case 0x0f70: /* pshufw */
7172 case 0x0f74: /* pcmpeqb */
7173 case 0x0f75: /* pcmpeqw */
7174 case 0x0f76: /* pcmpeqd */
7175 case 0x0fc4: /* pinsrw */
7176 case 0x0fd1: /* psrlw */
7177 case 0x0fd2: /* psrld */
7178 case 0x0fd3: /* psrlq */
7179 case 0x0fd4: /* paddq */
7180 case 0x0fd5: /* pmullw */
7181 case 0xf20fd6: /* movdq2q */
7182 case 0x0fd8: /* psubusb */
7183 case 0x0fd9: /* psubusw */
7184 case 0x0fda: /* pminub */
7185 case 0x0fdb: /* pand */
7186 case 0x0fdc: /* paddusb */
7187 case 0x0fdd: /* paddusw */
7188 case 0x0fde: /* pmaxub */
7189 case 0x0fdf: /* pandn */
7190 case 0x0fe0: /* pavgb */
7191 case 0x0fe1: /* psraw */
7192 case 0x0fe2: /* psrad */
7193 case 0x0fe3: /* pavgw */
7194 case 0x0fe4: /* pmulhuw */
7195 case 0x0fe5: /* pmulhw */
7196 case 0x0fe8: /* psubsb */
7197 case 0x0fe9: /* psubsw */
7198 case 0x0fea: /* pminsw */
7199 case 0x0feb: /* por */
7200 case 0x0fec: /* paddsb */
7201 case 0x0fed: /* paddsw */
7202 case 0x0fee: /* pmaxsw */
7203 case 0x0fef: /* pxor */
7204 case 0x0ff1: /* psllw */
7205 case 0x0ff2: /* pslld */
7206 case 0x0ff3: /* psllq */
7207 case 0x0ff4: /* pmuludq */
7208 case 0x0ff5: /* pmaddwd */
7209 case 0x0ff6: /* psadbw */
7210 case 0x0ff8: /* psubb */
7211 case 0x0ff9: /* psubw */
7212 case 0x0ffa: /* psubd */
7213 case 0x0ffb: /* psubq */
7214 case 0x0ffc: /* paddb */
7215 case 0x0ffd: /* paddw */
7216 case 0x0ffe: /* paddd */
7217 if (i386_record_modrm (&ir
))
7219 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7221 record_arch_list_add_reg (ir
.regcache
,
7222 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7225 case 0x0f71: /* psllw */
7226 case 0x0f72: /* pslld */
7227 case 0x0f73: /* psllq */
7228 if (i386_record_modrm (&ir
))
7230 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7232 record_arch_list_add_reg (ir
.regcache
,
7233 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7236 case 0x660f71: /* psllw */
7237 case 0x660f72: /* pslld */
7238 case 0x660f73: /* psllq */
7239 if (i386_record_modrm (&ir
))
7242 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7244 record_arch_list_add_reg (ir
.regcache
,
7245 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7248 case 0x0f7e: /* movd */
7249 case 0x660f7e: /* movd */
7250 if (i386_record_modrm (&ir
))
7253 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7260 if (i386_record_lea_modrm (&ir
))
7265 case 0x0f7f: /* movq */
7266 if (i386_record_modrm (&ir
))
7270 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7272 record_arch_list_add_reg (ir
.regcache
,
7273 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7278 if (i386_record_lea_modrm (&ir
))
7283 case 0xf30fb8: /* popcnt */
7284 if (i386_record_modrm (&ir
))
7286 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7287 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7290 case 0x660fd6: /* movq */
7291 if (i386_record_modrm (&ir
))
7296 if (!i386_xmm_regnum_p (gdbarch
,
7297 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7299 record_arch_list_add_reg (ir
.regcache
,
7300 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7305 if (i386_record_lea_modrm (&ir
))
7310 case 0x660f3817: /* ptest */
7311 case 0x0f2e: /* ucomiss */
7312 case 0x660f2e: /* ucomisd */
7313 case 0x0f2f: /* comiss */
7314 case 0x660f2f: /* comisd */
7315 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7318 case 0x0ff7: /* maskmovq */
7319 regcache_raw_read_unsigned (ir
.regcache
,
7320 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7322 if (record_arch_list_add_mem (addr
, 64))
7326 case 0x660ff7: /* maskmovdqu */
7327 regcache_raw_read_unsigned (ir
.regcache
,
7328 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7330 if (record_arch_list_add_mem (addr
, 128))
7345 /* In the future, maybe still need to deal with need_dasm. */
7346 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7347 if (record_arch_list_add_end ())
7353 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7354 "at address %s.\n"),
7355 (unsigned int) (opcode
),
7356 paddress (gdbarch
, ir
.orig_addr
));
7360 static const int i386_record_regmap
[] =
7362 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7363 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7364 0, 0, 0, 0, 0, 0, 0, 0,
7365 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7366 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7369 /* Check that the given address appears suitable for a fast
7370 tracepoint, which on x86-64 means that we need an instruction of at
7371 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7372 jump and not have to worry about program jumps to an address in the
7373 middle of the tracepoint jump. On x86, it may be possible to use
7374 4-byte jumps with a 2-byte offset to a trampoline located in the
7375 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7376 of instruction to replace, and 0 if not, plus an explanatory
7380 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7381 CORE_ADDR addr
, int *isize
, char **msg
)
7384 static struct ui_file
*gdb_null
= NULL
;
7386 /* Ask the target for the minimum instruction length supported. */
7387 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7391 /* If the target does not support the get_min_fast_tracepoint_insn_len
7392 operation, assume that fast tracepoints will always be implemented
7393 using 4-byte relative jumps on both x86 and x86-64. */
7396 else if (jumplen
== 0)
7398 /* If the target does support get_min_fast_tracepoint_insn_len but
7399 returns zero, then the IPA has not loaded yet. In this case,
7400 we optimistically assume that truncated 2-byte relative jumps
7401 will be available on x86, and compensate later if this assumption
7402 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7403 jumps will always be used. */
7404 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7407 /* Dummy file descriptor for the disassembler. */
7409 gdb_null
= ui_file_new ();
7411 /* Check for fit. */
7412 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7418 /* Return a bit of target-specific detail to add to the caller's
7419 generic failure message. */
7421 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7422 "need at least %d bytes for the jump"),
7435 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7436 struct tdesc_arch_data
*tdesc_data
)
7438 const struct target_desc
*tdesc
= tdep
->tdesc
;
7439 const struct tdesc_feature
*feature_core
;
7440 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7441 int i
, num_regs
, valid_p
;
7443 if (! tdesc_has_registers (tdesc
))
7446 /* Get core registers. */
7447 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7448 if (feature_core
== NULL
)
7451 /* Get SSE registers. */
7452 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7454 /* Try AVX registers. */
7455 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7459 /* The XCR0 bits. */
7462 /* AVX register description requires SSE register description. */
7466 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7468 /* It may have been set by OSABI initialization function. */
7469 if (tdep
->num_ymm_regs
== 0)
7471 tdep
->ymmh_register_names
= i386_ymmh_names
;
7472 tdep
->num_ymm_regs
= 8;
7473 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7476 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7477 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7478 tdep
->ymm0h_regnum
+ i
,
7479 tdep
->ymmh_register_names
[i
]);
7481 else if (feature_sse
)
7482 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7485 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7486 tdep
->num_xmm_regs
= 0;
7489 num_regs
= tdep
->num_core_regs
;
7490 for (i
= 0; i
< num_regs
; i
++)
7491 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7492 tdep
->register_names
[i
]);
7496 /* Need to include %mxcsr, so add one. */
7497 num_regs
+= tdep
->num_xmm_regs
+ 1;
7498 for (; i
< num_regs
; i
++)
7499 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7500 tdep
->register_names
[i
]);
7507 static struct gdbarch
*
7508 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7510 struct gdbarch_tdep
*tdep
;
7511 struct gdbarch
*gdbarch
;
7512 struct tdesc_arch_data
*tdesc_data
;
7513 const struct target_desc
*tdesc
;
7517 /* If there is already a candidate, use it. */
7518 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7520 return arches
->gdbarch
;
7522 /* Allocate space for the new architecture. */
7523 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7524 gdbarch
= gdbarch_alloc (&info
, tdep
);
7526 /* General-purpose registers. */
7527 tdep
->gregset
= NULL
;
7528 tdep
->gregset_reg_offset
= NULL
;
7529 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7530 tdep
->sizeof_gregset
= 0;
7532 /* Floating-point registers. */
7533 tdep
->fpregset
= NULL
;
7534 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7536 tdep
->xstateregset
= NULL
;
7538 /* The default settings include the FPU registers, the MMX registers
7539 and the SSE registers. This can be overridden for a specific ABI
7540 by adjusting the members `st0_regnum', `mm0_regnum' and
7541 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7542 will show up in the output of "info all-registers". */
7544 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7546 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7547 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7549 tdep
->jb_pc_offset
= -1;
7550 tdep
->struct_return
= pcc_struct_return
;
7551 tdep
->sigtramp_start
= 0;
7552 tdep
->sigtramp_end
= 0;
7553 tdep
->sigtramp_p
= i386_sigtramp_p
;
7554 tdep
->sigcontext_addr
= NULL
;
7555 tdep
->sc_reg_offset
= NULL
;
7556 tdep
->sc_pc_offset
= -1;
7557 tdep
->sc_sp_offset
= -1;
7559 tdep
->xsave_xcr0_offset
= -1;
7561 tdep
->record_regmap
= i386_record_regmap
;
7563 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7565 /* The format used for `long double' on almost all i386 targets is
7566 the i387 extended floating-point format. In fact, of all targets
7567 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7568 on having a `long double' that's not `long' at all. */
7569 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7571 /* Although the i387 extended floating-point has only 80 significant
7572 bits, a `long double' actually takes up 96, probably to enforce
7574 set_gdbarch_long_double_bit (gdbarch
, 96);
7576 /* Register numbers of various important registers. */
7577 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7578 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7579 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7580 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7582 /* NOTE: kettenis/20040418: GCC does have two possible register
7583 numbering schemes on the i386: dbx and SVR4. These schemes
7584 differ in how they number %ebp, %esp, %eflags, and the
7585 floating-point registers, and are implemented by the arrays
7586 dbx_register_map[] and svr4_dbx_register_map in
7587 gcc/config/i386.c. GCC also defines a third numbering scheme in
7588 gcc/config/i386.c, which it designates as the "default" register
7589 map used in 64bit mode. This last register numbering scheme is
7590 implemented in dbx64_register_map, and is used for AMD64; see
7593 Currently, each GCC i386 target always uses the same register
7594 numbering scheme across all its supported debugging formats
7595 i.e. SDB (COFF), stabs and DWARF 2. This is because
7596 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7597 DBX_REGISTER_NUMBER macro which is defined by each target's
7598 respective config header in a manner independent of the requested
7599 output debugging format.
7601 This does not match the arrangement below, which presumes that
7602 the SDB and stabs numbering schemes differ from the DWARF and
7603 DWARF 2 ones. The reason for this arrangement is that it is
7604 likely to get the numbering scheme for the target's
7605 default/native debug format right. For targets where GCC is the
7606 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7607 targets where the native toolchain uses a different numbering
7608 scheme for a particular debug format (stabs-in-ELF on Solaris)
7609 the defaults below will have to be overridden, like
7610 i386_elf_init_abi() does. */
7612 /* Use the dbx register numbering scheme for stabs and COFF. */
7613 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7614 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7616 /* Use the SVR4 register numbering scheme for DWARF 2. */
7617 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7619 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7620 be in use on any of the supported i386 targets. */
7622 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7624 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7626 /* Call dummy code. */
7627 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7628 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7629 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7630 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7632 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7633 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7634 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7636 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7638 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7640 /* Stack grows downward. */
7641 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7643 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7644 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7645 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7647 set_gdbarch_frame_args_skip (gdbarch
, 8);
7649 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7651 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7653 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7655 /* Add the i386 register groups. */
7656 i386_add_reggroups (gdbarch
);
7657 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7659 /* Helper for function argument information. */
7660 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7662 /* Hook the function epilogue frame unwinder. This unwinder is
7663 appended to the list first, so that it supercedes the DWARF
7664 unwinder in function epilogues (where the DWARF unwinder
7665 currently fails). */
7666 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7668 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7669 to the list before the prologue-based unwinders, so that DWARF
7670 CFI info will be used if it is available. */
7671 dwarf2_append_unwinders (gdbarch
);
7673 frame_base_set_default (gdbarch
, &i386_frame_base
);
7675 /* Pseudo registers may be changed by amd64_init_abi. */
7676 set_gdbarch_pseudo_register_read_value (gdbarch
,
7677 i386_pseudo_register_read_value
);
7678 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7680 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7681 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7683 /* Override the normal target description method to make the AVX
7684 upper halves anonymous. */
7685 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7687 /* Even though the default ABI only includes general-purpose registers,
7688 floating-point registers and the SSE registers, we have to leave a
7689 gap for the upper AVX registers. */
7690 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7692 /* Get the x86 target description from INFO. */
7693 tdesc
= info
.target_desc
;
7694 if (! tdesc_has_registers (tdesc
))
7696 tdep
->tdesc
= tdesc
;
7698 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7699 tdep
->register_names
= i386_register_names
;
7701 /* No upper YMM registers. */
7702 tdep
->ymmh_register_names
= NULL
;
7703 tdep
->ymm0h_regnum
= -1;
7705 tdep
->num_byte_regs
= 8;
7706 tdep
->num_word_regs
= 8;
7707 tdep
->num_dword_regs
= 0;
7708 tdep
->num_mmx_regs
= 8;
7709 tdep
->num_ymm_regs
= 0;
7711 tdesc_data
= tdesc_data_alloc ();
7713 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7715 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7717 /* Hook in ABI-specific overrides, if they have been registered. */
7718 info
.tdep_info
= (void *) tdesc_data
;
7719 gdbarch_init_osabi (info
, gdbarch
);
7721 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7723 tdesc_data_cleanup (tdesc_data
);
7725 gdbarch_free (gdbarch
);
7729 /* Wire in pseudo registers. Number of pseudo registers may be
7731 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7732 + tdep
->num_word_regs
7733 + tdep
->num_dword_regs
7734 + tdep
->num_mmx_regs
7735 + tdep
->num_ymm_regs
));
7737 /* Target description may be changed. */
7738 tdesc
= tdep
->tdesc
;
7740 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7742 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7743 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7745 /* Make %al the first pseudo-register. */
7746 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7747 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7749 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7750 if (tdep
->num_dword_regs
)
7752 /* Support dword pseudo-register if it hasn't been disabled. */
7753 tdep
->eax_regnum
= ymm0_regnum
;
7754 ymm0_regnum
+= tdep
->num_dword_regs
;
7757 tdep
->eax_regnum
= -1;
7759 mm0_regnum
= ymm0_regnum
;
7760 if (tdep
->num_ymm_regs
)
7762 /* Support YMM pseudo-register if it is available. */
7763 tdep
->ymm0_regnum
= ymm0_regnum
;
7764 mm0_regnum
+= tdep
->num_ymm_regs
;
7767 tdep
->ymm0_regnum
= -1;
7769 if (tdep
->num_mmx_regs
!= 0)
7771 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7772 tdep
->mm0_regnum
= mm0_regnum
;
7775 tdep
->mm0_regnum
= -1;
7777 /* Hook in the legacy prologue-based unwinders last (fallback). */
7778 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7779 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7780 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7782 /* If we have a register mapping, enable the generic core file
7783 support, unless it has already been enabled. */
7784 if (tdep
->gregset_reg_offset
7785 && !gdbarch_regset_from_core_section_p (gdbarch
))
7786 set_gdbarch_regset_from_core_section (gdbarch
,
7787 i386_regset_from_core_section
);
7789 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7790 i386_skip_permanent_breakpoint
);
7792 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7793 i386_fast_tracepoint_valid_at
);
7798 static enum gdb_osabi
7799 i386_coff_osabi_sniffer (bfd
*abfd
)
7801 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7802 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7803 return GDB_OSABI_GO32
;
7805 return GDB_OSABI_UNKNOWN
;
7809 /* Provide a prototype to silence -Wmissing-prototypes. */
7810 void _initialize_i386_tdep (void);
7813 _initialize_i386_tdep (void)
7815 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7817 /* Add the variable that controls the disassembly flavor. */
7818 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7819 &disassembly_flavor
, _("\
7820 Set the disassembly flavor."), _("\
7821 Show the disassembly flavor."), _("\
7822 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7824 NULL
, /* FIXME: i18n: */
7825 &setlist
, &showlist
);
7827 /* Add the variable that controls the convention for returning
7829 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7830 &struct_convention
, _("\
7831 Set the convention for returning small structs."), _("\
7832 Show the convention for returning small structs."), _("\
7833 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7836 NULL
, /* FIXME: i18n: */
7837 &setlist
, &showlist
);
7839 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7840 i386_coff_osabi_sniffer
);
7842 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7843 i386_svr4_init_abi
);
7844 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7845 i386_go32_init_abi
);
7847 /* Initialize the i386-specific register groups. */
7848 i386_init_reggroups ();
7850 /* Initialize the standard target descriptions. */
7851 initialize_tdesc_i386 ();
7852 initialize_tdesc_i386_mmx ();
7853 initialize_tdesc_i386_avx ();
7855 /* Tell remote stub that we support XML target description. */
7856 register_remote_support_xml ("i386");