1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, newrel
, byte_order
);
752 /* Write the adjusted jump into its displaced location. */
753 append_insns (to
, 5, insn
);
757 /* Adjust jumps with 32-bit relative addresses. Calls are already
761 /* Adjust conditional jumps. */
762 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
767 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
768 newrel
= (oldloc
- *to
) + rel32
;
769 store_signed_integer (insn
+ offset
, 4, newrel
, byte_order
);
771 fprintf_unfiltered (gdb_stdlog
,
772 "Adjusted insn rel32=0x%s at 0x%s to"
773 " rel32=0x%s at 0x%s\n",
774 hex_string (rel32
), paddress (gdbarch
, oldloc
),
775 hex_string (newrel
), paddress (gdbarch
, *to
));
778 /* Write the adjusted instructions into their displaced
780 append_insns (to
, insn_length
, buf
);
784 #ifdef I386_REGNO_TO_SYMMETRY
785 #error "The Sequent Symmetry is no longer supported."
788 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
789 and %esp "belong" to the calling function. Therefore these
790 registers should be saved if they're going to be modified. */
792 /* The maximum number of saved registers. This should include all
793 registers mentioned above, and %eip. */
794 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
796 struct i386_frame_cache
803 /* Saved registers. */
804 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
809 /* Stack space reserved for local variables. */
813 /* Allocate and initialize a frame cache. */
815 static struct i386_frame_cache
*
816 i386_alloc_frame_cache (void)
818 struct i386_frame_cache
*cache
;
821 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
825 cache
->sp_offset
= -4;
828 /* Saved registers. We initialize these to -1 since zero is a valid
829 offset (that's where %ebp is supposed to be stored). */
830 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
831 cache
->saved_regs
[i
] = -1;
833 cache
->saved_sp_reg
= -1;
834 cache
->pc_in_eax
= 0;
836 /* Frameless until proven otherwise. */
842 /* If the instruction at PC is a jump, return the address of its
843 target. Otherwise, return PC. */
846 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
853 if (target_read_memory (pc
, &op
, 1))
859 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
865 /* Relative jump: if data16 == 0, disp32, else disp16. */
868 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
870 /* Include the size of the jmp instruction (including the
876 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
878 /* Include the size of the jmp instruction. */
883 /* Relative jump, disp8 (ignore data16). */
884 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
893 /* Check whether PC points at a prologue for a function returning a
894 structure or union. If so, it updates CACHE and returns the
895 address of the first instruction after the code sequence that
896 removes the "hidden" argument from the stack or CURRENT_PC,
897 whichever is smaller. Otherwise, return PC. */
900 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
901 struct i386_frame_cache
*cache
)
903 /* Functions that return a structure or union start with:
906 xchgl %eax, (%esp) 0x87 0x04 0x24
907 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
909 (the System V compiler puts out the second `xchg' instruction,
910 and the assembler doesn't try to optimize it, so the 'sib' form
911 gets generated). This sequence is used to get the address of the
912 return buffer for a function that returns a structure. */
913 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
914 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
918 if (current_pc
<= pc
)
921 if (target_read_memory (pc
, &op
, 1))
924 if (op
!= 0x58) /* popl %eax */
927 if (target_read_memory (pc
+ 1, buf
, 4))
930 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
933 if (current_pc
== pc
)
935 cache
->sp_offset
+= 4;
939 if (current_pc
== pc
+ 1)
941 cache
->pc_in_eax
= 1;
945 if (buf
[1] == proto1
[1])
952 i386_skip_probe (CORE_ADDR pc
)
954 /* A function may start with
968 if (target_read_memory (pc
, &op
, 1))
971 if (op
== 0x68 || op
== 0x6a)
975 /* Skip past the `pushl' instruction; it has either a one-byte or a
976 four-byte operand, depending on the opcode. */
982 /* Read the following 8 bytes, which should be `call _probe' (6
983 bytes) followed by `addl $4,%esp' (2 bytes). */
984 read_memory (pc
+ delta
, buf
, sizeof (buf
));
985 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
986 pc
+= delta
+ sizeof (buf
);
992 /* GCC 4.1 and later, can put code in the prologue to realign the
993 stack pointer. Check whether PC points to such code, and update
994 CACHE accordingly. Return the first instruction after the code
995 sequence or CURRENT_PC, whichever is smaller. If we don't
996 recognize the code, return PC. */
999 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1000 struct i386_frame_cache
*cache
)
1002 /* There are 2 code sequences to re-align stack before the frame
1005 1. Use a caller-saved saved register:
1011 2. Use a callee-saved saved register:
1018 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1020 0x83 0xe4 0xf0 andl $-16, %esp
1021 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1026 int offset
, offset_and
;
1027 static int regnums
[8] = {
1028 I386_EAX_REGNUM
, /* %eax */
1029 I386_ECX_REGNUM
, /* %ecx */
1030 I386_EDX_REGNUM
, /* %edx */
1031 I386_EBX_REGNUM
, /* %ebx */
1032 I386_ESP_REGNUM
, /* %esp */
1033 I386_EBP_REGNUM
, /* %ebp */
1034 I386_ESI_REGNUM
, /* %esi */
1035 I386_EDI_REGNUM
/* %edi */
1038 if (target_read_memory (pc
, buf
, sizeof buf
))
1041 /* Check caller-saved saved register. The first instruction has
1042 to be "leal 4(%esp), %reg". */
1043 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1045 /* MOD must be binary 10 and R/M must be binary 100. */
1046 if ((buf
[1] & 0xc7) != 0x44)
1049 /* REG has register number. */
1050 reg
= (buf
[1] >> 3) & 7;
1055 /* Check callee-saved saved register. The first instruction
1056 has to be "pushl %reg". */
1057 if ((buf
[0] & 0xf8) != 0x50)
1063 /* The next instruction has to be "leal 8(%esp), %reg". */
1064 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[2] & 0xc7) != 0x44)
1071 /* REG has register number. Registers in pushl and leal have to
1073 if (reg
!= ((buf
[2] >> 3) & 7))
1079 /* Rigister can't be %esp nor %ebp. */
1080 if (reg
== 4 || reg
== 5)
1083 /* The next instruction has to be "andl $-XXX, %esp". */
1084 if (buf
[offset
+ 1] != 0xe4
1085 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1088 offset_and
= offset
;
1089 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1091 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1092 0xfc. REG must be binary 110 and MOD must be binary 01. */
1093 if (buf
[offset
] != 0xff
1094 || buf
[offset
+ 2] != 0xfc
1095 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1098 /* R/M has register. Registers in leal and pushl have to be the
1100 if (reg
!= (buf
[offset
+ 1] & 7))
1103 if (current_pc
> pc
+ offset_and
)
1104 cache
->saved_sp_reg
= regnums
[reg
];
1106 return min (pc
+ offset
+ 3, current_pc
);
1109 /* Maximum instruction length we need to handle. */
1110 #define I386_MAX_MATCHED_INSN_LEN 6
1112 /* Instruction description. */
1116 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1117 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1120 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1121 the first instruction description that matches. Otherwise, return
1124 static struct i386_insn
*
1125 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
1127 struct i386_insn
*insn
;
1130 if (target_read_memory (pc
, &op
, 1))
1133 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1135 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1137 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1138 int insn_matched
= 1;
1141 gdb_assert (insn
->len
> 1);
1142 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1144 if (target_read_memory (pc
+ 1, buf
, insn
->len
- 1))
1147 for (i
= 1; i
< insn
->len
; i
++)
1149 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1161 /* Some special instructions that might be migrated by GCC into the
1162 part of the prologue that sets up the new stack frame. Because the
1163 stack frame hasn't been setup yet, no registers have been saved
1164 yet, and only the scratch registers %eax, %ecx and %edx can be
1167 struct i386_insn i386_frame_setup_skip_insns
[] =
1169 /* Check for `movb imm8, r' and `movl imm32, r'.
1171 ??? Should we handle 16-bit operand-sizes here? */
1173 /* `movb imm8, %al' and `movb imm8, %ah' */
1174 /* `movb imm8, %cl' and `movb imm8, %ch' */
1175 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1176 /* `movb imm8, %dl' and `movb imm8, %dh' */
1177 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1178 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1179 { 5, { 0xb8 }, { 0xfe } },
1180 /* `movl imm32, %edx' */
1181 { 5, { 0xba }, { 0xff } },
1183 /* Check for `mov imm32, r32'. Note that there is an alternative
1184 encoding for `mov m32, %eax'.
1186 ??? Should we handle SIB adressing here?
1187 ??? Should we handle 16-bit operand-sizes here? */
1189 /* `movl m32, %eax' */
1190 { 5, { 0xa1 }, { 0xff } },
1191 /* `movl m32, %eax' and `mov; m32, %ecx' */
1192 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1193 /* `movl m32, %edx' */
1194 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1196 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1197 Because of the symmetry, there are actually two ways to encode
1198 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1199 opcode bytes 0x31 and 0x33 for `xorl'. */
1201 /* `subl %eax, %eax' */
1202 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1203 /* `subl %ecx, %ecx' */
1204 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1205 /* `subl %edx, %edx' */
1206 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1207 /* `xorl %eax, %eax' */
1208 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1209 /* `xorl %ecx, %ecx' */
1210 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1211 /* `xorl %edx, %edx' */
1212 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1217 /* Check whether PC points to a no-op instruction. */
1219 i386_skip_noop (CORE_ADDR pc
)
1224 if (target_read_memory (pc
, &op
, 1))
1230 /* Ignore `nop' instruction. */
1234 if (target_read_memory (pc
, &op
, 1))
1238 /* Ignore no-op instruction `mov %edi, %edi'.
1239 Microsoft system dlls often start with
1240 a `mov %edi,%edi' instruction.
1241 The 5 bytes before the function start are
1242 filled with `nop' instructions.
1243 This pattern can be used for hot-patching:
1244 The `mov %edi, %edi' instruction can be replaced by a
1245 near jump to the location of the 5 `nop' instructions
1246 which can be replaced by a 32-bit jump to anywhere
1247 in the 32-bit address space. */
1249 else if (op
== 0x8b)
1251 if (target_read_memory (pc
+ 1, &op
, 1))
1257 if (target_read_memory (pc
, &op
, 1))
1267 /* Check whether PC points at a code that sets up a new stack frame.
1268 If so, it updates CACHE and returns the address of the first
1269 instruction after the sequence that sets up the frame or LIMIT,
1270 whichever is smaller. If we don't recognize the code, return PC. */
1273 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1274 CORE_ADDR pc
, CORE_ADDR limit
,
1275 struct i386_frame_cache
*cache
)
1277 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1278 struct i386_insn
*insn
;
1285 if (target_read_memory (pc
, &op
, 1))
1288 if (op
== 0x55) /* pushl %ebp */
1290 /* Take into account that we've executed the `pushl %ebp' that
1291 starts this instruction sequence. */
1292 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1293 cache
->sp_offset
+= 4;
1296 /* If that's all, return now. */
1300 /* Check for some special instructions that might be migrated by
1301 GCC into the prologue and skip them. At this point in the
1302 prologue, code should only touch the scratch registers %eax,
1303 %ecx and %edx, so while the number of posibilities is sheer,
1306 Make sure we only skip these instructions if we later see the
1307 `movl %esp, %ebp' that actually sets up the frame. */
1308 while (pc
+ skip
< limit
)
1310 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1317 /* If that's all, return now. */
1318 if (limit
<= pc
+ skip
)
1321 if (target_read_memory (pc
+ skip
, &op
, 1))
1324 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1328 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1333 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1341 /* OK, we actually have a frame. We just don't know how large
1342 it is yet. Set its size to zero. We'll adjust it if
1343 necessary. We also now commit to skipping the special
1344 instructions mentioned before. */
1348 /* If that's all, return now. */
1352 /* Check for stack adjustment
1356 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1357 reg, so we don't have to worry about a data16 prefix. */
1358 if (target_read_memory (pc
, &op
, 1))
1362 /* `subl' with 8-bit immediate. */
1363 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1364 /* Some instruction starting with 0x83 other than `subl'. */
1367 /* `subl' with signed 8-bit immediate (though it wouldn't
1368 make sense to be negative). */
1369 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1372 else if (op
== 0x81)
1374 /* Maybe it is `subl' with a 32-bit immediate. */
1375 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1376 /* Some instruction starting with 0x81 other than `subl'. */
1379 /* It is `subl' with a 32-bit immediate. */
1380 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1385 /* Some instruction other than `subl'. */
1389 else if (op
== 0xc8) /* enter */
1391 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1398 /* Check whether PC points at code that saves registers on the stack.
1399 If so, it updates CACHE and returns the address of the first
1400 instruction after the register saves or CURRENT_PC, whichever is
1401 smaller. Otherwise, return PC. */
1404 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1405 struct i386_frame_cache
*cache
)
1407 CORE_ADDR offset
= 0;
1411 if (cache
->locals
> 0)
1412 offset
-= cache
->locals
;
1413 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1415 if (target_read_memory (pc
, &op
, 1))
1417 if (op
< 0x50 || op
> 0x57)
1421 cache
->saved_regs
[op
- 0x50] = offset
;
1422 cache
->sp_offset
+= 4;
1429 /* Do a full analysis of the prologue at PC and update CACHE
1430 accordingly. Bail out early if CURRENT_PC is reached. Return the
1431 address where the analysis stopped.
1433 We handle these cases:
1435 The startup sequence can be at the start of the function, or the
1436 function can start with a branch to startup code at the end.
1438 %ebp can be set up with either the 'enter' instruction, or "pushl
1439 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1440 once used in the System V compiler).
1442 Local space is allocated just below the saved %ebp by either the
1443 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1444 16-bit unsigned argument for space to allocate, and the 'addl'
1445 instruction could have either a signed byte, or 32-bit immediate.
1447 Next, the registers used by this function are pushed. With the
1448 System V compiler they will always be in the order: %edi, %esi,
1449 %ebx (and sometimes a harmless bug causes it to also save but not
1450 restore %eax); however, the code below is willing to see the pushes
1451 in any order, and will handle up to 8 of them.
1453 If the setup sequence is at the end of the function, then the next
1454 instruction will be a branch back to the start. */
1457 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1458 CORE_ADDR pc
, CORE_ADDR current_pc
,
1459 struct i386_frame_cache
*cache
)
1461 pc
= i386_skip_noop (pc
);
1462 pc
= i386_follow_jump (gdbarch
, pc
);
1463 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1464 pc
= i386_skip_probe (pc
);
1465 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1466 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1467 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1470 /* Return PC of first real instruction. */
1473 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1475 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1477 static gdb_byte pic_pat
[6] =
1479 0xe8, 0, 0, 0, 0, /* call 0x0 */
1480 0x5b, /* popl %ebx */
1482 struct i386_frame_cache cache
;
1488 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1489 if (cache
.locals
< 0)
1492 /* Found valid frame setup. */
1494 /* The native cc on SVR4 in -K PIC mode inserts the following code
1495 to get the address of the global offset table (GOT) into register
1500 movl %ebx,x(%ebp) (optional)
1503 This code is with the rest of the prologue (at the end of the
1504 function), so we have to skip it to get to the first real
1505 instruction at the start of the function. */
1507 for (i
= 0; i
< 6; i
++)
1509 if (target_read_memory (pc
+ i
, &op
, 1))
1512 if (pic_pat
[i
] != op
)
1519 if (target_read_memory (pc
+ delta
, &op
, 1))
1522 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1524 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1526 if (op
== 0x5d) /* One byte offset from %ebp. */
1528 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1530 else /* Unexpected instruction. */
1533 if (target_read_memory (pc
+ delta
, &op
, 1))
1538 if (delta
> 0 && op
== 0x81
1539 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1546 /* If the function starts with a branch (to startup code at the end)
1547 the last instruction should bring us back to the first
1548 instruction of the real code. */
1549 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1550 pc
= i386_follow_jump (gdbarch
, pc
);
1555 /* Check that the code pointed to by PC corresponds to a call to
1556 __main, skip it if so. Return PC otherwise. */
1559 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1561 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1564 if (target_read_memory (pc
, &op
, 1))
1570 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1572 /* Make sure address is computed correctly as a 32bit
1573 integer even if CORE_ADDR is 64 bit wide. */
1574 struct minimal_symbol
*s
;
1575 CORE_ADDR call_dest
;
1577 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1578 call_dest
= call_dest
& 0xffffffffU
;
1579 s
= lookup_minimal_symbol_by_pc (call_dest
);
1581 && SYMBOL_LINKAGE_NAME (s
) != NULL
1582 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1590 /* This function is 64-bit safe. */
1593 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1597 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1598 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1602 /* Normal frames. */
1604 static struct i386_frame_cache
*
1605 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1607 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1608 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1609 struct i386_frame_cache
*cache
;
1616 cache
= i386_alloc_frame_cache ();
1617 *this_cache
= cache
;
1619 /* In principle, for normal frames, %ebp holds the frame pointer,
1620 which holds the base address for the current stack frame.
1621 However, for functions that don't need it, the frame pointer is
1622 optional. For these "frameless" functions the frame pointer is
1623 actually the frame pointer of the calling frame. Signal
1624 trampolines are just a special case of a "frameless" function.
1625 They (usually) share their frame pointer with the frame that was
1626 in progress when the signal occurred. */
1628 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1629 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1630 if (cache
->base
== 0)
1633 /* For normal frames, %eip is stored at 4(%ebp). */
1634 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1636 cache
->pc
= get_frame_func (this_frame
);
1638 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1641 if (cache
->saved_sp_reg
!= -1)
1643 /* Saved stack pointer has been saved. */
1644 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1645 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1648 if (cache
->locals
< 0)
1650 /* We didn't find a valid frame, which means that CACHE->base
1651 currently holds the frame pointer for our calling frame. If
1652 we're at the start of a function, or somewhere half-way its
1653 prologue, the function's frame probably hasn't been fully
1654 setup yet. Try to reconstruct the base address for the stack
1655 frame by looking at the stack pointer. For truly "frameless"
1656 functions this might work too. */
1658 if (cache
->saved_sp_reg
!= -1)
1660 /* We're halfway aligning the stack. */
1661 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1662 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1664 /* This will be added back below. */
1665 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1667 else if (cache
->pc
!= 0
1668 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1670 /* We're in a known function, but did not find a frame
1671 setup. Assume that the function does not use %ebp.
1672 Alternatively, we may have jumped to an invalid
1673 address; in that case there is definitely no new
1675 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1676 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1680 /* We're in an unknown function. We could not find the start
1681 of the function to analyze the prologue; our best option is
1682 to assume a typical frame layout with the caller's %ebp
1684 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1687 /* Now that we have the base address for the stack frame we can
1688 calculate the value of %esp in the calling frame. */
1689 if (cache
->saved_sp
== 0)
1690 cache
->saved_sp
= cache
->base
+ 8;
1692 /* Adjust all the saved registers such that they contain addresses
1693 instead of offsets. */
1694 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1695 if (cache
->saved_regs
[i
] != -1)
1696 cache
->saved_regs
[i
] += cache
->base
;
1702 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1703 struct frame_id
*this_id
)
1705 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1707 /* This marks the outermost frame. */
1708 if (cache
->base
== 0)
1711 /* See the end of i386_push_dummy_call. */
1712 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1715 static struct value
*
1716 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1719 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1721 gdb_assert (regnum
>= 0);
1723 /* The System V ABI says that:
1725 "The flags register contains the system flags, such as the
1726 direction flag and the carry flag. The direction flag must be
1727 set to the forward (that is, zero) direction before entry and
1728 upon exit from a function. Other user flags have no specified
1729 role in the standard calling sequence and are not preserved."
1731 To guarantee the "upon exit" part of that statement we fake a
1732 saved flags register that has its direction flag cleared.
1734 Note that GCC doesn't seem to rely on the fact that the direction
1735 flag is cleared after a function return; it always explicitly
1736 clears the flag before operations where it matters.
1738 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1739 right thing to do. The way we fake the flags register here makes
1740 it impossible to change it. */
1742 if (regnum
== I386_EFLAGS_REGNUM
)
1746 val
= get_frame_register_unsigned (this_frame
, regnum
);
1748 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1751 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1752 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1754 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1755 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1757 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1758 return frame_unwind_got_memory (this_frame
, regnum
,
1759 cache
->saved_regs
[regnum
]);
1761 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1764 static const struct frame_unwind i386_frame_unwind
=
1768 i386_frame_prev_register
,
1770 default_frame_sniffer
1773 /* Normal frames, but in a function epilogue. */
1775 /* The epilogue is defined here as the 'ret' instruction, which will
1776 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1777 the function's stack frame. */
1780 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1784 if (target_read_memory (pc
, &insn
, 1))
1785 return 0; /* Can't read memory at pc. */
1787 if (insn
!= 0xc3) /* 'ret' instruction. */
1794 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1795 struct frame_info
*this_frame
,
1796 void **this_prologue_cache
)
1798 if (frame_relative_level (this_frame
) == 0)
1799 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1800 get_frame_pc (this_frame
));
1805 static struct i386_frame_cache
*
1806 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1808 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1809 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1810 struct i386_frame_cache
*cache
;
1816 cache
= i386_alloc_frame_cache ();
1817 *this_cache
= cache
;
1819 /* Cache base will be %esp plus cache->sp_offset (-4). */
1820 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1821 cache
->base
= extract_unsigned_integer (buf
, 4,
1822 byte_order
) + cache
->sp_offset
;
1824 /* Cache pc will be the frame func. */
1825 cache
->pc
= get_frame_pc (this_frame
);
1827 /* The saved %esp will be at cache->base plus 8. */
1828 cache
->saved_sp
= cache
->base
+ 8;
1830 /* The saved %eip will be at cache->base plus 4. */
1831 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1837 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1839 struct frame_id
*this_id
)
1841 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1844 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1847 static const struct frame_unwind i386_epilogue_frame_unwind
=
1850 i386_epilogue_frame_this_id
,
1851 i386_frame_prev_register
,
1853 i386_epilogue_frame_sniffer
1857 /* Signal trampolines. */
1859 static struct i386_frame_cache
*
1860 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1862 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1864 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1865 struct i386_frame_cache
*cache
;
1872 cache
= i386_alloc_frame_cache ();
1874 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1875 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1877 addr
= tdep
->sigcontext_addr (this_frame
);
1878 if (tdep
->sc_reg_offset
)
1882 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1884 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1885 if (tdep
->sc_reg_offset
[i
] != -1)
1886 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1890 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1891 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1894 *this_cache
= cache
;
1899 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1900 struct frame_id
*this_id
)
1902 struct i386_frame_cache
*cache
=
1903 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1905 /* See the end of i386_push_dummy_call. */
1906 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1909 static struct value
*
1910 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1911 void **this_cache
, int regnum
)
1913 /* Make sure we've initialized the cache. */
1914 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1916 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1920 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1921 struct frame_info
*this_frame
,
1922 void **this_prologue_cache
)
1924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1926 /* We shouldn't even bother if we don't have a sigcontext_addr
1928 if (tdep
->sigcontext_addr
== NULL
)
1931 if (tdep
->sigtramp_p
!= NULL
)
1933 if (tdep
->sigtramp_p (this_frame
))
1937 if (tdep
->sigtramp_start
!= 0)
1939 CORE_ADDR pc
= get_frame_pc (this_frame
);
1941 gdb_assert (tdep
->sigtramp_end
!= 0);
1942 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1949 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1952 i386_sigtramp_frame_this_id
,
1953 i386_sigtramp_frame_prev_register
,
1955 i386_sigtramp_frame_sniffer
1960 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1962 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1967 static const struct frame_base i386_frame_base
=
1970 i386_frame_base_address
,
1971 i386_frame_base_address
,
1972 i386_frame_base_address
1975 static struct frame_id
1976 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1980 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1982 /* See the end of i386_push_dummy_call. */
1983 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1987 /* Figure out where the longjmp will land. Slurp the args out of the
1988 stack. We expect the first arg to be a pointer to the jmp_buf
1989 structure from which we extract the address that we will land at.
1990 This address is copied into PC. This routine returns non-zero on
1994 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1997 CORE_ADDR sp
, jb_addr
;
1998 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1999 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2000 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2002 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2003 longjmp will land. */
2004 if (jb_pc_offset
== -1)
2007 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2008 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2009 if (target_read_memory (sp
+ 4, buf
, 4))
2012 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2013 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2016 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2021 /* Check whether TYPE must be 16-byte-aligned when passed as a
2022 function argument. 16-byte vectors, _Decimal128 and structures or
2023 unions containing such types must be 16-byte-aligned; other
2024 arguments are 4-byte-aligned. */
2027 i386_16_byte_align_p (struct type
*type
)
2029 type
= check_typedef (type
);
2030 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2031 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2032 && TYPE_LENGTH (type
) == 16)
2034 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2035 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2036 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2037 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2040 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2042 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2050 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2051 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2052 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2053 CORE_ADDR struct_addr
)
2055 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2061 /* Determine the total space required for arguments and struct
2062 return address in a first pass (allowing for 16-byte-aligned
2063 arguments), then push arguments in a second pass. */
2065 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2067 int args_space_used
= 0;
2068 int have_16_byte_aligned_arg
= 0;
2074 /* Push value address. */
2075 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2076 write_memory (sp
, buf
, 4);
2077 args_space_used
+= 4;
2083 for (i
= 0; i
< nargs
; i
++)
2085 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2089 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2090 args_space_used
= align_up (args_space_used
, 16);
2092 write_memory (sp
+ args_space_used
,
2093 value_contents_all (args
[i
]), len
);
2094 /* The System V ABI says that:
2096 "An argument's size is increased, if necessary, to make it a
2097 multiple of [32-bit] words. This may require tail padding,
2098 depending on the size of the argument."
2100 This makes sure the stack stays word-aligned. */
2101 args_space_used
+= align_up (len
, 4);
2105 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2107 args_space
= align_up (args_space
, 16);
2108 have_16_byte_aligned_arg
= 1;
2110 args_space
+= align_up (len
, 4);
2116 if (have_16_byte_aligned_arg
)
2117 args_space
= align_up (args_space
, 16);
2122 /* Store return address. */
2124 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2125 write_memory (sp
, buf
, 4);
2127 /* Finally, update the stack pointer... */
2128 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2129 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2131 /* ...and fake a frame pointer. */
2132 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2134 /* MarkK wrote: This "+ 8" is all over the place:
2135 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2136 i386_dummy_id). It's there, since all frame unwinders for
2137 a given target have to agree (within a certain margin) on the
2138 definition of the stack address of a frame. Otherwise frame id
2139 comparison might not work correctly. Since DWARF2/GCC uses the
2140 stack address *before* the function call as a frame's CFA. On
2141 the i386, when %ebp is used as a frame pointer, the offset
2142 between the contents %ebp and the CFA as defined by GCC. */
2146 /* These registers are used for returning integers (and on some
2147 targets also for returning `struct' and `union' values when their
2148 size and alignment match an integer type). */
2149 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2150 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2152 /* Read, for architecture GDBARCH, a function return value of TYPE
2153 from REGCACHE, and copy that into VALBUF. */
2156 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2157 struct regcache
*regcache
, gdb_byte
*valbuf
)
2159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2160 int len
= TYPE_LENGTH (type
);
2161 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2163 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2165 if (tdep
->st0_regnum
< 0)
2167 warning (_("Cannot find floating-point return value."));
2168 memset (valbuf
, 0, len
);
2172 /* Floating-point return values can be found in %st(0). Convert
2173 its contents to the desired type. This is probably not
2174 exactly how it would happen on the target itself, but it is
2175 the best we can do. */
2176 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2177 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2181 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2182 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2184 if (len
<= low_size
)
2186 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2187 memcpy (valbuf
, buf
, len
);
2189 else if (len
<= (low_size
+ high_size
))
2191 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2192 memcpy (valbuf
, buf
, low_size
);
2193 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2194 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2197 internal_error (__FILE__
, __LINE__
,
2198 _("Cannot extract return value of %d bytes long."),
2203 /* Write, for architecture GDBARCH, a function return value of TYPE
2204 from VALBUF into REGCACHE. */
2207 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2208 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2211 int len
= TYPE_LENGTH (type
);
2213 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2216 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2218 if (tdep
->st0_regnum
< 0)
2220 warning (_("Cannot set floating-point return value."));
2224 /* Returning floating-point values is a bit tricky. Apart from
2225 storing the return value in %st(0), we have to simulate the
2226 state of the FPU at function return point. */
2228 /* Convert the value found in VALBUF to the extended
2229 floating-point format used by the FPU. This is probably
2230 not exactly how it would happen on the target itself, but
2231 it is the best we can do. */
2232 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2233 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2235 /* Set the top of the floating-point register stack to 7. The
2236 actual value doesn't really matter, but 7 is what a normal
2237 function return would end up with if the program started out
2238 with a freshly initialized FPU. */
2239 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2241 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2243 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2244 the floating-point register stack to 7, the appropriate value
2245 for the tag word is 0x3fff. */
2246 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2250 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2251 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2253 if (len
<= low_size
)
2254 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2255 else if (len
<= (low_size
+ high_size
))
2257 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2258 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2259 len
- low_size
, valbuf
+ low_size
);
2262 internal_error (__FILE__
, __LINE__
,
2263 _("Cannot store return value of %d bytes long."), len
);
2268 /* This is the variable that is set with "set struct-convention", and
2269 its legitimate values. */
2270 static const char default_struct_convention
[] = "default";
2271 static const char pcc_struct_convention
[] = "pcc";
2272 static const char reg_struct_convention
[] = "reg";
2273 static const char *valid_conventions
[] =
2275 default_struct_convention
,
2276 pcc_struct_convention
,
2277 reg_struct_convention
,
2280 static const char *struct_convention
= default_struct_convention
;
2282 /* Return non-zero if TYPE, which is assumed to be a structure,
2283 a union type, or an array type, should be returned in registers
2284 for architecture GDBARCH. */
2287 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2290 enum type_code code
= TYPE_CODE (type
);
2291 int len
= TYPE_LENGTH (type
);
2293 gdb_assert (code
== TYPE_CODE_STRUCT
2294 || code
== TYPE_CODE_UNION
2295 || code
== TYPE_CODE_ARRAY
);
2297 if (struct_convention
== pcc_struct_convention
2298 || (struct_convention
== default_struct_convention
2299 && tdep
->struct_return
== pcc_struct_return
))
2302 /* Structures consisting of a single `float', `double' or 'long
2303 double' member are returned in %st(0). */
2304 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2306 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2307 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2308 return (len
== 4 || len
== 8 || len
== 12);
2311 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2314 /* Determine, for architecture GDBARCH, how a return value of TYPE
2315 should be returned. If it is supposed to be returned in registers,
2316 and READBUF is non-zero, read the appropriate value from REGCACHE,
2317 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2318 from WRITEBUF into REGCACHE. */
2320 static enum return_value_convention
2321 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2322 struct type
*type
, struct regcache
*regcache
,
2323 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2325 enum type_code code
= TYPE_CODE (type
);
2327 if (((code
== TYPE_CODE_STRUCT
2328 || code
== TYPE_CODE_UNION
2329 || code
== TYPE_CODE_ARRAY
)
2330 && !i386_reg_struct_return_p (gdbarch
, type
))
2331 /* 128-bit decimal float uses the struct return convention. */
2332 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2334 /* The System V ABI says that:
2336 "A function that returns a structure or union also sets %eax
2337 to the value of the original address of the caller's area
2338 before it returns. Thus when the caller receives control
2339 again, the address of the returned object resides in register
2340 %eax and can be used to access the object."
2342 So the ABI guarantees that we can always find the return
2343 value just after the function has returned. */
2345 /* Note that the ABI doesn't mention functions returning arrays,
2346 which is something possible in certain languages such as Ada.
2347 In this case, the value is returned as if it was wrapped in
2348 a record, so the convention applied to records also applies
2355 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2356 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2359 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2362 /* This special case is for structures consisting of a single
2363 `float', `double' or 'long double' member. These structures are
2364 returned in %st(0). For these structures, we call ourselves
2365 recursively, changing TYPE into the type of the first member of
2366 the structure. Since that should work for all structures that
2367 have only one member, we don't bother to check the member's type
2369 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2371 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2372 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2377 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2379 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2381 return RETURN_VALUE_REGISTER_CONVENTION
;
2386 i387_ext_type (struct gdbarch
*gdbarch
)
2388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2390 if (!tdep
->i387_ext_type
)
2392 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2393 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2396 return tdep
->i387_ext_type
;
2399 /* Construct vector type for pseudo YMM registers. We can't use
2400 tdesc_find_type since YMM isn't described in target description. */
2402 static struct type
*
2403 i386_ymm_type (struct gdbarch
*gdbarch
)
2405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2407 if (!tdep
->i386_ymm_type
)
2409 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2411 /* The type we're building is this: */
2413 union __gdb_builtin_type_vec256i
2415 int128_t uint128
[2];
2416 int64_t v2_int64
[4];
2417 int32_t v4_int32
[8];
2418 int16_t v8_int16
[16];
2419 int8_t v16_int8
[32];
2420 double v2_double
[4];
2427 t
= arch_composite_type (gdbarch
,
2428 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2429 append_composite_type_field (t
, "v8_float",
2430 init_vector_type (bt
->builtin_float
, 8));
2431 append_composite_type_field (t
, "v4_double",
2432 init_vector_type (bt
->builtin_double
, 4));
2433 append_composite_type_field (t
, "v32_int8",
2434 init_vector_type (bt
->builtin_int8
, 32));
2435 append_composite_type_field (t
, "v16_int16",
2436 init_vector_type (bt
->builtin_int16
, 16));
2437 append_composite_type_field (t
, "v8_int32",
2438 init_vector_type (bt
->builtin_int32
, 8));
2439 append_composite_type_field (t
, "v4_int64",
2440 init_vector_type (bt
->builtin_int64
, 4));
2441 append_composite_type_field (t
, "v2_int128",
2442 init_vector_type (bt
->builtin_int128
, 2));
2444 TYPE_VECTOR (t
) = 1;
2445 TYPE_NAME (t
) = "builtin_type_vec256i";
2446 tdep
->i386_ymm_type
= t
;
2449 return tdep
->i386_ymm_type
;
2452 /* Construct vector type for MMX registers. */
2453 static struct type
*
2454 i386_mmx_type (struct gdbarch
*gdbarch
)
2456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2458 if (!tdep
->i386_mmx_type
)
2460 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2462 /* The type we're building is this: */
2464 union __gdb_builtin_type_vec64i
2467 int32_t v2_int32
[2];
2468 int16_t v4_int16
[4];
2475 t
= arch_composite_type (gdbarch
,
2476 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2478 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2479 append_composite_type_field (t
, "v2_int32",
2480 init_vector_type (bt
->builtin_int32
, 2));
2481 append_composite_type_field (t
, "v4_int16",
2482 init_vector_type (bt
->builtin_int16
, 4));
2483 append_composite_type_field (t
, "v8_int8",
2484 init_vector_type (bt
->builtin_int8
, 8));
2486 TYPE_VECTOR (t
) = 1;
2487 TYPE_NAME (t
) = "builtin_type_vec64i";
2488 tdep
->i386_mmx_type
= t
;
2491 return tdep
->i386_mmx_type
;
2494 /* Return the GDB type object for the "standard" data type of data in
2497 static struct type
*
2498 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2500 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2501 return i386_mmx_type (gdbarch
);
2502 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2503 return i386_ymm_type (gdbarch
);
2506 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2507 if (i386_byte_regnum_p (gdbarch
, regnum
))
2508 return bt
->builtin_int8
;
2509 else if (i386_word_regnum_p (gdbarch
, regnum
))
2510 return bt
->builtin_int16
;
2511 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2512 return bt
->builtin_int32
;
2515 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2518 /* Map a cooked register onto a raw register or memory. For the i386,
2519 the MMX registers need to be mapped onto floating point registers. */
2522 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2529 mmxreg
= regnum
- tdep
->mm0_regnum
;
2530 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2531 tos
= (fstat
>> 11) & 0x7;
2532 fpreg
= (mmxreg
+ tos
) % 8;
2534 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2538 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2539 int regnum
, gdb_byte
*buf
)
2541 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2543 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2545 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2547 /* Extract (always little endian). */
2548 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2549 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2555 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2557 regnum
-= tdep
->ymm0_regnum
;
2559 /* Extract (always little endian). Read lower 128bits. */
2560 regcache_raw_read (regcache
,
2561 I387_XMM0_REGNUM (tdep
) + regnum
,
2563 memcpy (buf
, raw_buf
, 16);
2564 /* Read upper 128bits. */
2565 regcache_raw_read (regcache
,
2566 tdep
->ymm0h_regnum
+ regnum
,
2568 memcpy (buf
+ 16, raw_buf
, 16);
2570 else if (i386_word_regnum_p (gdbarch
, regnum
))
2572 int gpnum
= regnum
- tdep
->ax_regnum
;
2574 /* Extract (always little endian). */
2575 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2576 memcpy (buf
, raw_buf
, 2);
2578 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2580 /* Check byte pseudo registers last since this function will
2581 be called from amd64_pseudo_register_read, which handles
2582 byte pseudo registers differently. */
2583 int gpnum
= regnum
- tdep
->al_regnum
;
2585 /* Extract (always little endian). We read both lower and
2587 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2589 memcpy (buf
, raw_buf
+ 1, 1);
2591 memcpy (buf
, raw_buf
, 1);
2594 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2599 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2600 int regnum
, const gdb_byte
*buf
)
2602 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2604 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2606 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2609 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2610 /* ... Modify ... (always little endian). */
2611 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2613 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2619 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2621 regnum
-= tdep
->ymm0_regnum
;
2623 /* ... Write lower 128bits. */
2624 regcache_raw_write (regcache
,
2625 I387_XMM0_REGNUM (tdep
) + regnum
,
2627 /* ... Write upper 128bits. */
2628 regcache_raw_write (regcache
,
2629 tdep
->ymm0h_regnum
+ regnum
,
2632 else if (i386_word_regnum_p (gdbarch
, regnum
))
2634 int gpnum
= regnum
- tdep
->ax_regnum
;
2637 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2638 /* ... Modify ... (always little endian). */
2639 memcpy (raw_buf
, buf
, 2);
2641 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2643 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2645 /* Check byte pseudo registers last since this function will
2646 be called from amd64_pseudo_register_read, which handles
2647 byte pseudo registers differently. */
2648 int gpnum
= regnum
- tdep
->al_regnum
;
2650 /* Read ... We read both lower and upper registers. */
2651 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2652 /* ... Modify ... (always little endian). */
2654 memcpy (raw_buf
+ 1, buf
, 1);
2656 memcpy (raw_buf
, buf
, 1);
2658 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2661 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2666 /* Return the register number of the register allocated by GCC after
2667 REGNUM, or -1 if there is no such register. */
2670 i386_next_regnum (int regnum
)
2672 /* GCC allocates the registers in the order:
2674 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2676 Since storing a variable in %esp doesn't make any sense we return
2677 -1 for %ebp and for %esp itself. */
2678 static int next_regnum
[] =
2680 I386_EDX_REGNUM
, /* Slot for %eax. */
2681 I386_EBX_REGNUM
, /* Slot for %ecx. */
2682 I386_ECX_REGNUM
, /* Slot for %edx. */
2683 I386_ESI_REGNUM
, /* Slot for %ebx. */
2684 -1, -1, /* Slots for %esp and %ebp. */
2685 I386_EDI_REGNUM
, /* Slot for %esi. */
2686 I386_EBP_REGNUM
/* Slot for %edi. */
2689 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2690 return next_regnum
[regnum
];
2695 /* Return nonzero if a value of type TYPE stored in register REGNUM
2696 needs any special handling. */
2699 i386_convert_register_p (struct gdbarch
*gdbarch
,
2700 int regnum
, struct type
*type
)
2702 int len
= TYPE_LENGTH (type
);
2704 /* Values may be spread across multiple registers. Most debugging
2705 formats aren't expressive enough to specify the locations, so
2706 some heuristics is involved. Right now we only handle types that
2707 have a length that is a multiple of the word size, since GCC
2708 doesn't seem to put any other types into registers. */
2709 if (len
> 4 && len
% 4 == 0)
2711 int last_regnum
= regnum
;
2715 last_regnum
= i386_next_regnum (last_regnum
);
2719 if (last_regnum
!= -1)
2723 return i387_convert_register_p (gdbarch
, regnum
, type
);
2726 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2727 return its contents in TO. */
2730 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2731 struct type
*type
, gdb_byte
*to
)
2733 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2734 int len
= TYPE_LENGTH (type
);
2736 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2737 available in FRAME (i.e. if it wasn't saved)? */
2739 if (i386_fp_regnum_p (gdbarch
, regnum
))
2741 i387_register_to_value (frame
, regnum
, type
, to
);
2745 /* Read a value spread across multiple registers. */
2747 gdb_assert (len
> 4 && len
% 4 == 0);
2751 gdb_assert (regnum
!= -1);
2752 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2754 get_frame_register (frame
, regnum
, to
);
2755 regnum
= i386_next_regnum (regnum
);
2761 /* Write the contents FROM of a value of type TYPE into register
2762 REGNUM in frame FRAME. */
2765 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2766 struct type
*type
, const gdb_byte
*from
)
2768 int len
= TYPE_LENGTH (type
);
2770 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2772 i387_value_to_register (frame
, regnum
, type
, from
);
2776 /* Write a value spread across multiple registers. */
2778 gdb_assert (len
> 4 && len
% 4 == 0);
2782 gdb_assert (regnum
!= -1);
2783 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2785 put_frame_register (frame
, regnum
, from
);
2786 regnum
= i386_next_regnum (regnum
);
2792 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2793 in the general-purpose register set REGSET to register cache
2794 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2797 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2798 int regnum
, const void *gregs
, size_t len
)
2800 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2801 const gdb_byte
*regs
= gregs
;
2804 gdb_assert (len
== tdep
->sizeof_gregset
);
2806 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2808 if ((regnum
== i
|| regnum
== -1)
2809 && tdep
->gregset_reg_offset
[i
] != -1)
2810 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2814 /* Collect register REGNUM from the register cache REGCACHE and store
2815 it in the buffer specified by GREGS and LEN as described by the
2816 general-purpose register set REGSET. If REGNUM is -1, do this for
2817 all registers in REGSET. */
2820 i386_collect_gregset (const struct regset
*regset
,
2821 const struct regcache
*regcache
,
2822 int regnum
, void *gregs
, size_t len
)
2824 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2825 gdb_byte
*regs
= gregs
;
2828 gdb_assert (len
== tdep
->sizeof_gregset
);
2830 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2832 if ((regnum
== i
|| regnum
== -1)
2833 && tdep
->gregset_reg_offset
[i
] != -1)
2834 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2838 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2839 in the floating-point register set REGSET to register cache
2840 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2843 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2844 int regnum
, const void *fpregs
, size_t len
)
2846 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2848 if (len
== I387_SIZEOF_FXSAVE
)
2850 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2854 gdb_assert (len
== tdep
->sizeof_fpregset
);
2855 i387_supply_fsave (regcache
, regnum
, fpregs
);
2858 /* Collect register REGNUM from the register cache REGCACHE and store
2859 it in the buffer specified by FPREGS and LEN as described by the
2860 floating-point register set REGSET. If REGNUM is -1, do this for
2861 all registers in REGSET. */
2864 i386_collect_fpregset (const struct regset
*regset
,
2865 const struct regcache
*regcache
,
2866 int regnum
, void *fpregs
, size_t len
)
2868 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2870 if (len
== I387_SIZEOF_FXSAVE
)
2872 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2876 gdb_assert (len
== tdep
->sizeof_fpregset
);
2877 i387_collect_fsave (regcache
, regnum
, fpregs
);
2880 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2883 i386_supply_xstateregset (const struct regset
*regset
,
2884 struct regcache
*regcache
, int regnum
,
2885 const void *xstateregs
, size_t len
)
2887 i387_supply_xsave (regcache
, regnum
, xstateregs
);
2890 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2893 i386_collect_xstateregset (const struct regset
*regset
,
2894 const struct regcache
*regcache
,
2895 int regnum
, void *xstateregs
, size_t len
)
2897 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2900 /* Return the appropriate register set for the core section identified
2901 by SECT_NAME and SECT_SIZE. */
2903 const struct regset
*
2904 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2905 const char *sect_name
, size_t sect_size
)
2907 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2909 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2911 if (tdep
->gregset
== NULL
)
2912 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2913 i386_collect_gregset
);
2914 return tdep
->gregset
;
2917 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2918 || (strcmp (sect_name
, ".reg-xfp") == 0
2919 && sect_size
== I387_SIZEOF_FXSAVE
))
2921 if (tdep
->fpregset
== NULL
)
2922 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2923 i386_collect_fpregset
);
2924 return tdep
->fpregset
;
2927 if (strcmp (sect_name
, ".reg-xstate") == 0)
2929 if (tdep
->xstateregset
== NULL
)
2930 tdep
->xstateregset
= regset_alloc (gdbarch
,
2931 i386_supply_xstateregset
,
2932 i386_collect_xstateregset
);
2934 return tdep
->xstateregset
;
2941 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2944 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2945 CORE_ADDR pc
, char *name
)
2947 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2948 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2951 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2953 unsigned long indirect
=
2954 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2955 struct minimal_symbol
*indsym
=
2956 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2957 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2961 if (strncmp (symname
, "__imp_", 6) == 0
2962 || strncmp (symname
, "_imp_", 5) == 0)
2964 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2967 return 0; /* Not a trampoline. */
2971 /* Return whether the THIS_FRAME corresponds to a sigtramp
2975 i386_sigtramp_p (struct frame_info
*this_frame
)
2977 CORE_ADDR pc
= get_frame_pc (this_frame
);
2980 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2981 return (name
&& strcmp ("_sigtramp", name
) == 0);
2985 /* We have two flavours of disassembly. The machinery on this page
2986 deals with switching between those. */
2989 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2991 gdb_assert (disassembly_flavor
== att_flavor
2992 || disassembly_flavor
== intel_flavor
);
2994 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2995 constified, cast to prevent a compiler warning. */
2996 info
->disassembler_options
= (char *) disassembly_flavor
;
2998 return print_insn_i386 (pc
, info
);
3002 /* There are a few i386 architecture variants that differ only
3003 slightly from the generic i386 target. For now, we don't give them
3004 their own source file, but include them here. As a consequence,
3005 they'll always be included. */
3007 /* System V Release 4 (SVR4). */
3009 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3013 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3015 CORE_ADDR pc
= get_frame_pc (this_frame
);
3018 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3019 currently unknown. */
3020 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3021 return (name
&& (strcmp ("_sigreturn", name
) == 0
3022 || strcmp ("_sigacthandler", name
) == 0
3023 || strcmp ("sigvechandler", name
) == 0));
3026 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3027 address of the associated sigcontext (ucontext) structure. */
3030 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3032 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3033 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3037 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3038 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3040 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3047 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3049 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3050 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3053 /* System V Release 4 (SVR4). */
3056 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3058 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3060 /* System V Release 4 uses ELF. */
3061 i386_elf_init_abi (info
, gdbarch
);
3063 /* System V Release 4 has shared libraries. */
3064 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3066 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3067 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3068 tdep
->sc_pc_offset
= 36 + 14 * 4;
3069 tdep
->sc_sp_offset
= 36 + 17 * 4;
3071 tdep
->jb_pc_offset
= 20;
3077 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3081 /* DJGPP doesn't have any special frames for signal handlers. */
3082 tdep
->sigtramp_p
= NULL
;
3084 tdep
->jb_pc_offset
= 36;
3086 /* DJGPP does not support the SSE registers. */
3087 if (! tdesc_has_registers (info
.target_desc
))
3088 tdep
->tdesc
= tdesc_i386_mmx
;
3090 /* Native compiler is GCC, which uses the SVR4 register numbering
3091 even in COFF and STABS. See the comment in i386_gdbarch_init,
3092 before the calls to set_gdbarch_stab_reg_to_regnum and
3093 set_gdbarch_sdb_reg_to_regnum. */
3094 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3095 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3097 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3101 /* i386 register groups. In addition to the normal groups, add "mmx"
3104 static struct reggroup
*i386_sse_reggroup
;
3105 static struct reggroup
*i386_mmx_reggroup
;
3108 i386_init_reggroups (void)
3110 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3111 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3115 i386_add_reggroups (struct gdbarch
*gdbarch
)
3117 reggroup_add (gdbarch
, i386_sse_reggroup
);
3118 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3119 reggroup_add (gdbarch
, general_reggroup
);
3120 reggroup_add (gdbarch
, float_reggroup
);
3121 reggroup_add (gdbarch
, all_reggroup
);
3122 reggroup_add (gdbarch
, save_reggroup
);
3123 reggroup_add (gdbarch
, restore_reggroup
);
3124 reggroup_add (gdbarch
, vector_reggroup
);
3125 reggroup_add (gdbarch
, system_reggroup
);
3129 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3130 struct reggroup
*group
)
3132 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3133 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3134 ymm_regnum_p
, ymmh_regnum_p
;
3136 /* Don't include pseudo registers, except for MMX, in any register
3138 if (i386_byte_regnum_p (gdbarch
, regnum
))
3141 if (i386_word_regnum_p (gdbarch
, regnum
))
3144 if (i386_dword_regnum_p (gdbarch
, regnum
))
3147 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3148 if (group
== i386_mmx_reggroup
)
3149 return mmx_regnum_p
;
3151 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3152 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3153 if (group
== i386_sse_reggroup
)
3154 return xmm_regnum_p
|| mxcsr_regnum_p
;
3156 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3157 if (group
== vector_reggroup
)
3158 return (mmx_regnum_p
3162 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3163 == I386_XSTATE_SSE_MASK
)));
3165 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3166 || i386_fpc_regnum_p (gdbarch
, regnum
));
3167 if (group
== float_reggroup
)
3170 /* For "info reg all", don't include upper YMM registers nor XMM
3171 registers when AVX is supported. */
3172 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3173 if (group
== all_reggroup
3175 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3179 if (group
== general_reggroup
)
3180 return (!fp_regnum_p
3187 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3191 /* Get the ARGIth function argument for the current function. */
3194 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3197 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3198 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3199 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3200 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3204 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3206 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3208 /* On i386, breakpoint is exactly 1 byte long, so we just
3209 adjust the PC in the regcache. */
3211 regcache_write_pc (regcache
, current_pc
);
3215 #define PREFIX_REPZ 0x01
3216 #define PREFIX_REPNZ 0x02
3217 #define PREFIX_LOCK 0x04
3218 #define PREFIX_DATA 0x08
3219 #define PREFIX_ADDR 0x10
3231 /* i386 arith/logic operations */
3244 struct i386_record_s
3246 struct gdbarch
*gdbarch
;
3247 struct regcache
*regcache
;
3248 CORE_ADDR orig_addr
;
3254 uint8_t mod
, reg
, rm
;
3263 /* Parse "modrm" part in current memory address that irp->addr point to
3264 Return -1 if something wrong. */
3267 i386_record_modrm (struct i386_record_s
*irp
)
3269 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3271 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3274 printf_unfiltered (_("Process record: error reading memory at "
3275 "addr %s len = 1.\n"),
3276 paddress (gdbarch
, irp
->addr
));
3280 irp
->mod
= (irp
->modrm
>> 6) & 3;
3281 irp
->reg
= (irp
->modrm
>> 3) & 7;
3282 irp
->rm
= irp
->modrm
& 7;
3287 /* Get the memory address that current instruction write to and set it to
3288 the argument "addr".
3289 Return -1 if something wrong. */
3292 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3294 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3295 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3307 uint8_t base
= irp
->rm
;
3312 if (target_read_memory (irp
->addr
, &byte
, 1))
3315 printf_unfiltered (_("Process record: error reading memory "
3316 "at addr %s len = 1.\n"),
3317 paddress (gdbarch
, irp
->addr
));
3321 scale
= (byte
>> 6) & 3;
3322 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3330 if ((base
& 7) == 5)
3333 if (target_read_memory (irp
->addr
, buf
, 4))
3336 printf_unfiltered (_("Process record: error reading "
3337 "memory at addr %s len = 4.\n"),
3338 paddress (gdbarch
, irp
->addr
));
3342 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3343 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3344 *addr
+= irp
->addr
+ irp
->rip_offset
;
3348 if (target_read_memory (irp
->addr
, buf
, 1))
3351 printf_unfiltered (_("Process record: error reading memory "
3352 "at addr %s len = 1.\n"),
3353 paddress (gdbarch
, irp
->addr
));
3357 *addr
= (int8_t) buf
[0];
3360 if (target_read_memory (irp
->addr
, buf
, 4))
3363 printf_unfiltered (_("Process record: error reading memory "
3364 "at addr %s len = 4.\n"),
3365 paddress (gdbarch
, irp
->addr
));
3368 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3376 if (base
== 4 && irp
->popl_esp_hack
)
3377 *addr
+= irp
->popl_esp_hack
;
3378 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3381 if (irp
->aflag
== 2)
3386 *addr
= (uint32_t) (offset64
+ *addr
);
3388 if (havesib
&& (index
!= 4 || scale
!= 0))
3390 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3392 if (irp
->aflag
== 2)
3393 *addr
+= offset64
<< scale
;
3395 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3406 if (target_read_memory (irp
->addr
, buf
, 2))
3409 printf_unfiltered (_("Process record: error reading "
3410 "memory at addr %s len = 2.\n"),
3411 paddress (gdbarch
, irp
->addr
));
3415 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3421 if (target_read_memory (irp
->addr
, buf
, 1))
3424 printf_unfiltered (_("Process record: error reading memory "
3425 "at addr %s len = 1.\n"),
3426 paddress (gdbarch
, irp
->addr
));
3430 *addr
= (int8_t) buf
[0];
3433 if (target_read_memory (irp
->addr
, buf
, 2))
3436 printf_unfiltered (_("Process record: error reading memory "
3437 "at addr %s len = 2.\n"),
3438 paddress (gdbarch
, irp
->addr
));
3442 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3449 regcache_raw_read_unsigned (irp
->regcache
,
3450 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3452 *addr
= (uint32_t) (*addr
+ offset64
);
3453 regcache_raw_read_unsigned (irp
->regcache
,
3454 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3456 *addr
= (uint32_t) (*addr
+ offset64
);
3459 regcache_raw_read_unsigned (irp
->regcache
,
3460 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3462 *addr
= (uint32_t) (*addr
+ offset64
);
3463 regcache_raw_read_unsigned (irp
->regcache
,
3464 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3466 *addr
= (uint32_t) (*addr
+ offset64
);
3469 regcache_raw_read_unsigned (irp
->regcache
,
3470 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3472 *addr
= (uint32_t) (*addr
+ offset64
);
3473 regcache_raw_read_unsigned (irp
->regcache
,
3474 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3476 *addr
= (uint32_t) (*addr
+ offset64
);
3479 regcache_raw_read_unsigned (irp
->regcache
,
3480 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3482 *addr
= (uint32_t) (*addr
+ offset64
);
3483 regcache_raw_read_unsigned (irp
->regcache
,
3484 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3486 *addr
= (uint32_t) (*addr
+ offset64
);
3489 regcache_raw_read_unsigned (irp
->regcache
,
3490 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3492 *addr
= (uint32_t) (*addr
+ offset64
);
3495 regcache_raw_read_unsigned (irp
->regcache
,
3496 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3498 *addr
= (uint32_t) (*addr
+ offset64
);
3501 regcache_raw_read_unsigned (irp
->regcache
,
3502 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3504 *addr
= (uint32_t) (*addr
+ offset64
);
3507 regcache_raw_read_unsigned (irp
->regcache
,
3508 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3510 *addr
= (uint32_t) (*addr
+ offset64
);
3520 /* Record the value of the memory that willbe changed in current instruction
3521 to "record_arch_list".
3522 Return -1 if something wrong. */
3525 i386_record_lea_modrm (struct i386_record_s
*irp
)
3527 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3530 if (irp
->override
>= 0)
3532 if (record_memory_query
)
3536 target_terminal_ours ();
3538 Process record ignores the memory change of instruction at address %s\n\
3539 because it can't get the value of the segment register.\n\
3540 Do you want to stop the program?"),
3541 paddress (gdbarch
, irp
->orig_addr
));
3542 target_terminal_inferior ();
3550 if (i386_record_lea_modrm_addr (irp
, &addr
))
3553 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3559 /* Record the push operation to "record_arch_list".
3560 Return -1 if something wrong. */
3563 i386_record_push (struct i386_record_s
*irp
, int size
)
3567 if (record_arch_list_add_reg (irp
->regcache
,
3568 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3570 regcache_raw_read_unsigned (irp
->regcache
,
3571 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3573 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3580 /* Defines contents to record. */
3581 #define I386_SAVE_FPU_REGS 0xfffd
3582 #define I386_SAVE_FPU_ENV 0xfffe
3583 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3585 /* Record the value of floating point registers which will be changed
3586 by the current instruction to "record_arch_list". Return -1 if
3587 something is wrong. */
3589 static int i386_record_floats (struct gdbarch
*gdbarch
,
3590 struct i386_record_s
*ir
,
3593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3596 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3597 happen. Currently we store st0-st7 registers, but we need not store all
3598 registers all the time, in future we use ftag register and record only
3599 those who are not marked as an empty. */
3601 if (I386_SAVE_FPU_REGS
== iregnum
)
3603 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3605 if (record_arch_list_add_reg (ir
->regcache
, i
))
3609 else if (I386_SAVE_FPU_ENV
== iregnum
)
3611 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3613 if (record_arch_list_add_reg (ir
->regcache
, i
))
3617 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3619 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3621 if (record_arch_list_add_reg (ir
->regcache
, i
))
3625 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3626 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3628 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3633 /* Parameter error. */
3636 if(I386_SAVE_FPU_ENV
!= iregnum
)
3638 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3640 if (record_arch_list_add_reg (ir
->regcache
, i
))
3647 /* Parse the current instruction and record the values of the registers and
3648 memory that will be changed in current instruction to "record_arch_list".
3649 Return -1 if something wrong. */
3651 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3652 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3655 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3656 CORE_ADDR input_addr
)
3658 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3664 gdb_byte buf
[MAX_REGISTER_SIZE
];
3665 struct i386_record_s ir
;
3666 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3671 memset (&ir
, 0, sizeof (struct i386_record_s
));
3672 ir
.regcache
= regcache
;
3673 ir
.addr
= input_addr
;
3674 ir
.orig_addr
= input_addr
;
3678 ir
.popl_esp_hack
= 0;
3679 ir
.regmap
= tdep
->record_regmap
;
3680 ir
.gdbarch
= gdbarch
;
3682 if (record_debug
> 1)
3683 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3685 paddress (gdbarch
, ir
.addr
));
3690 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3693 printf_unfiltered (_("Process record: error reading memory at "
3694 "addr %s len = 1.\n"),
3695 paddress (gdbarch
, ir
.addr
));
3699 switch (opcode8
) /* Instruction prefixes */
3701 case REPE_PREFIX_OPCODE
:
3702 prefixes
|= PREFIX_REPZ
;
3704 case REPNE_PREFIX_OPCODE
:
3705 prefixes
|= PREFIX_REPNZ
;
3707 case LOCK_PREFIX_OPCODE
:
3708 prefixes
|= PREFIX_LOCK
;
3710 case CS_PREFIX_OPCODE
:
3711 ir
.override
= X86_RECORD_CS_REGNUM
;
3713 case SS_PREFIX_OPCODE
:
3714 ir
.override
= X86_RECORD_SS_REGNUM
;
3716 case DS_PREFIX_OPCODE
:
3717 ir
.override
= X86_RECORD_DS_REGNUM
;
3719 case ES_PREFIX_OPCODE
:
3720 ir
.override
= X86_RECORD_ES_REGNUM
;
3722 case FS_PREFIX_OPCODE
:
3723 ir
.override
= X86_RECORD_FS_REGNUM
;
3725 case GS_PREFIX_OPCODE
:
3726 ir
.override
= X86_RECORD_GS_REGNUM
;
3728 case DATA_PREFIX_OPCODE
:
3729 prefixes
|= PREFIX_DATA
;
3731 case ADDR_PREFIX_OPCODE
:
3732 prefixes
|= PREFIX_ADDR
;
3734 case 0x40: /* i386 inc %eax */
3735 case 0x41: /* i386 inc %ecx */
3736 case 0x42: /* i386 inc %edx */
3737 case 0x43: /* i386 inc %ebx */
3738 case 0x44: /* i386 inc %esp */
3739 case 0x45: /* i386 inc %ebp */
3740 case 0x46: /* i386 inc %esi */
3741 case 0x47: /* i386 inc %edi */
3742 case 0x48: /* i386 dec %eax */
3743 case 0x49: /* i386 dec %ecx */
3744 case 0x4a: /* i386 dec %edx */
3745 case 0x4b: /* i386 dec %ebx */
3746 case 0x4c: /* i386 dec %esp */
3747 case 0x4d: /* i386 dec %ebp */
3748 case 0x4e: /* i386 dec %esi */
3749 case 0x4f: /* i386 dec %edi */
3750 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3754 rex_w
= (opcode8
>> 3) & 1;
3755 rex_r
= (opcode8
& 0x4) << 1;
3756 ir
.rex_x
= (opcode8
& 0x2) << 2;
3757 ir
.rex_b
= (opcode8
& 0x1) << 3;
3759 else /* 32 bit target */
3768 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3774 if (prefixes
& PREFIX_DATA
)
3777 if (prefixes
& PREFIX_ADDR
)
3779 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3782 /* Now check op code. */
3783 opcode
= (uint32_t) opcode8
;
3788 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3791 printf_unfiltered (_("Process record: error reading memory at "
3792 "addr %s len = 1.\n"),
3793 paddress (gdbarch
, ir
.addr
));
3797 opcode
= (uint32_t) opcode8
| 0x0f00;
3801 case 0x00: /* arith & logic */
3849 if (((opcode
>> 3) & 7) != OP_CMPL
)
3851 if ((opcode
& 1) == 0)
3854 ir
.ot
= ir
.dflag
+ OT_WORD
;
3856 switch ((opcode
>> 1) & 3)
3858 case 0: /* OP Ev, Gv */
3859 if (i386_record_modrm (&ir
))
3863 if (i386_record_lea_modrm (&ir
))
3869 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3871 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3874 case 1: /* OP Gv, Ev */
3875 if (i386_record_modrm (&ir
))
3878 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3880 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3882 case 2: /* OP A, Iv */
3883 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3887 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3890 case 0x80: /* GRP1 */
3894 if (i386_record_modrm (&ir
))
3897 if (ir
.reg
!= OP_CMPL
)
3899 if ((opcode
& 1) == 0)
3902 ir
.ot
= ir
.dflag
+ OT_WORD
;
3909 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3910 if (i386_record_lea_modrm (&ir
))
3914 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3919 case 0x40: /* inc */
3928 case 0x48: /* dec */
3937 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3938 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3941 case 0xf6: /* GRP3 */
3943 if ((opcode
& 1) == 0)
3946 ir
.ot
= ir
.dflag
+ OT_WORD
;
3947 if (i386_record_modrm (&ir
))
3950 if (ir
.mod
!= 3 && ir
.reg
== 0)
3951 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3962 if (i386_record_lea_modrm (&ir
))
3968 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3970 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3972 if (ir
.reg
== 3) /* neg */
3973 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3979 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3980 if (ir
.ot
!= OT_BYTE
)
3981 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3982 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3986 opcode
= opcode
<< 8 | ir
.modrm
;
3992 case 0xfe: /* GRP4 */
3993 case 0xff: /* GRP5 */
3994 if (i386_record_modrm (&ir
))
3996 if (ir
.reg
>= 2 && opcode
== 0xfe)
3999 opcode
= opcode
<< 8 | ir
.modrm
;
4006 if ((opcode
& 1) == 0)
4009 ir
.ot
= ir
.dflag
+ OT_WORD
;
4012 if (i386_record_lea_modrm (&ir
))
4018 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4020 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4022 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4025 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4027 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4029 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4032 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4033 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4035 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4039 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4042 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4044 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4049 opcode
= opcode
<< 8 | ir
.modrm
;
4055 case 0x84: /* test */
4059 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4062 case 0x98: /* CWDE/CBW */
4063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4066 case 0x99: /* CDQ/CWD */
4067 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4068 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4071 case 0x0faf: /* imul */
4074 ir
.ot
= ir
.dflag
+ OT_WORD
;
4075 if (i386_record_modrm (&ir
))
4078 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4079 else if (opcode
== 0x6b)
4082 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4084 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4088 case 0x0fc0: /* xadd */
4090 if ((opcode
& 1) == 0)
4093 ir
.ot
= ir
.dflag
+ OT_WORD
;
4094 if (i386_record_modrm (&ir
))
4099 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4101 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4102 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4104 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4108 if (i386_record_lea_modrm (&ir
))
4110 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4112 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4117 case 0x0fb0: /* cmpxchg */
4119 if ((opcode
& 1) == 0)
4122 ir
.ot
= ir
.dflag
+ OT_WORD
;
4123 if (i386_record_modrm (&ir
))
4128 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4129 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4131 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4135 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4136 if (i386_record_lea_modrm (&ir
))
4139 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4142 case 0x0fc7: /* cmpxchg8b */
4143 if (i386_record_modrm (&ir
))
4148 opcode
= opcode
<< 8 | ir
.modrm
;
4151 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4152 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4153 if (i386_record_lea_modrm (&ir
))
4155 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4158 case 0x50: /* push */
4168 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4170 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4174 case 0x06: /* push es */
4175 case 0x0e: /* push cs */
4176 case 0x16: /* push ss */
4177 case 0x1e: /* push ds */
4178 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4183 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4187 case 0x0fa0: /* push fs */
4188 case 0x0fa8: /* push gs */
4189 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4194 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4198 case 0x60: /* pusha */
4199 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4204 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4208 case 0x58: /* pop */
4216 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4217 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4220 case 0x61: /* popa */
4221 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4226 for (regnum
= X86_RECORD_REAX_REGNUM
;
4227 regnum
<= X86_RECORD_REDI_REGNUM
;
4229 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4232 case 0x8f: /* pop */
4233 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4234 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4236 ir
.ot
= ir
.dflag
+ OT_WORD
;
4237 if (i386_record_modrm (&ir
))
4240 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4243 ir
.popl_esp_hack
= 1 << ir
.ot
;
4244 if (i386_record_lea_modrm (&ir
))
4247 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4250 case 0xc8: /* enter */
4251 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4252 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4254 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4258 case 0xc9: /* leave */
4259 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4260 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4263 case 0x07: /* pop es */
4264 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4274 case 0x17: /* pop ss */
4275 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4282 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4285 case 0x1f: /* pop ds */
4286 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4293 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4296 case 0x0fa1: /* pop fs */
4297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4299 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4302 case 0x0fa9: /* pop gs */
4303 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4304 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4308 case 0x88: /* mov */
4312 if ((opcode
& 1) == 0)
4315 ir
.ot
= ir
.dflag
+ OT_WORD
;
4317 if (i386_record_modrm (&ir
))
4322 if (opcode
== 0xc6 || opcode
== 0xc7)
4323 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4324 if (i386_record_lea_modrm (&ir
))
4329 if (opcode
== 0xc6 || opcode
== 0xc7)
4331 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4333 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4337 case 0x8a: /* mov */
4339 if ((opcode
& 1) == 0)
4342 ir
.ot
= ir
.dflag
+ OT_WORD
;
4343 if (i386_record_modrm (&ir
))
4346 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4348 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4351 case 0x8c: /* mov seg */
4352 if (i386_record_modrm (&ir
))
4357 opcode
= opcode
<< 8 | ir
.modrm
;
4362 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4366 if (i386_record_lea_modrm (&ir
))
4371 case 0x8e: /* mov seg */
4372 if (i386_record_modrm (&ir
))
4377 regnum
= X86_RECORD_ES_REGNUM
;
4380 regnum
= X86_RECORD_SS_REGNUM
;
4383 regnum
= X86_RECORD_DS_REGNUM
;
4386 regnum
= X86_RECORD_FS_REGNUM
;
4389 regnum
= X86_RECORD_GS_REGNUM
;
4393 opcode
= opcode
<< 8 | ir
.modrm
;
4397 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4398 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4401 case 0x0fb6: /* movzbS */
4402 case 0x0fb7: /* movzwS */
4403 case 0x0fbe: /* movsbS */
4404 case 0x0fbf: /* movswS */
4405 if (i386_record_modrm (&ir
))
4407 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4410 case 0x8d: /* lea */
4411 if (i386_record_modrm (&ir
))
4416 opcode
= opcode
<< 8 | ir
.modrm
;
4421 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4423 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4426 case 0xa0: /* mov EAX */
4429 case 0xd7: /* xlat */
4430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4433 case 0xa2: /* mov EAX */
4435 if (ir
.override
>= 0)
4437 if (record_memory_query
)
4441 target_terminal_ours ();
4443 Process record ignores the memory change of instruction at address %s\n\
4444 because it can't get the value of the segment register.\n\
4445 Do you want to stop the program?"),
4446 paddress (gdbarch
, ir
.orig_addr
));
4447 target_terminal_inferior ();
4454 if ((opcode
& 1) == 0)
4457 ir
.ot
= ir
.dflag
+ OT_WORD
;
4460 if (target_read_memory (ir
.addr
, buf
, 8))
4463 printf_unfiltered (_("Process record: error reading "
4464 "memory at addr 0x%s len = 8.\n"),
4465 paddress (gdbarch
, ir
.addr
));
4469 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4473 if (target_read_memory (ir
.addr
, buf
, 4))
4476 printf_unfiltered (_("Process record: error reading "
4477 "memory at addr 0x%s len = 4.\n"),
4478 paddress (gdbarch
, ir
.addr
));
4482 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4486 if (target_read_memory (ir
.addr
, buf
, 2))
4489 printf_unfiltered (_("Process record: error reading "
4490 "memory at addr 0x%s len = 2.\n"),
4491 paddress (gdbarch
, ir
.addr
));
4495 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4497 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4502 case 0xb0: /* mov R, Ib */
4510 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4511 ? ((opcode
& 0x7) | ir
.rex_b
)
4512 : ((opcode
& 0x7) & 0x3));
4515 case 0xb8: /* mov R, Iv */
4523 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4526 case 0x91: /* xchg R, EAX */
4533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4534 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4537 case 0x86: /* xchg Ev, Gv */
4539 if ((opcode
& 1) == 0)
4542 ir
.ot
= ir
.dflag
+ OT_WORD
;
4543 if (i386_record_modrm (&ir
))
4548 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4550 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4554 if (i386_record_lea_modrm (&ir
))
4558 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4560 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4563 case 0xc4: /* les Gv */
4564 case 0xc5: /* lds Gv */
4565 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4571 case 0x0fb2: /* lss Gv */
4572 case 0x0fb4: /* lfs Gv */
4573 case 0x0fb5: /* lgs Gv */
4574 if (i386_record_modrm (&ir
))
4582 opcode
= opcode
<< 8 | ir
.modrm
;
4587 case 0xc4: /* les Gv */
4588 regnum
= X86_RECORD_ES_REGNUM
;
4590 case 0xc5: /* lds Gv */
4591 regnum
= X86_RECORD_DS_REGNUM
;
4593 case 0x0fb2: /* lss Gv */
4594 regnum
= X86_RECORD_SS_REGNUM
;
4596 case 0x0fb4: /* lfs Gv */
4597 regnum
= X86_RECORD_FS_REGNUM
;
4599 case 0x0fb5: /* lgs Gv */
4600 regnum
= X86_RECORD_GS_REGNUM
;
4603 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4604 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4608 case 0xc0: /* shifts */
4614 if ((opcode
& 1) == 0)
4617 ir
.ot
= ir
.dflag
+ OT_WORD
;
4618 if (i386_record_modrm (&ir
))
4620 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4622 if (i386_record_lea_modrm (&ir
))
4628 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4630 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4639 if (i386_record_modrm (&ir
))
4643 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4648 if (i386_record_lea_modrm (&ir
))
4653 case 0xd8: /* Floats. */
4661 if (i386_record_modrm (&ir
))
4663 ir
.reg
|= ((opcode
& 7) << 3);
4669 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4677 /* For fcom, ficom nothing to do. */
4683 /* For fcomp, ficomp pop FPU stack, store all. */
4684 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4711 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4712 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4713 of code, always affects st(0) register. */
4714 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4738 /* Handling fld, fild. */
4739 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4743 switch (ir
.reg
>> 4)
4746 if (record_arch_list_add_mem (addr64
, 4))
4750 if (record_arch_list_add_mem (addr64
, 8))
4756 if (record_arch_list_add_mem (addr64
, 2))
4762 switch (ir
.reg
>> 4)
4765 if (record_arch_list_add_mem (addr64
, 4))
4767 if (3 == (ir
.reg
& 7))
4769 /* For fstp m32fp. */
4770 if (i386_record_floats (gdbarch
, &ir
,
4771 I386_SAVE_FPU_REGS
))
4776 if (record_arch_list_add_mem (addr64
, 4))
4778 if ((3 == (ir
.reg
& 7))
4779 || (5 == (ir
.reg
& 7))
4780 || (7 == (ir
.reg
& 7)))
4782 /* For fstp insn. */
4783 if (i386_record_floats (gdbarch
, &ir
,
4784 I386_SAVE_FPU_REGS
))
4789 if (record_arch_list_add_mem (addr64
, 8))
4791 if (3 == (ir
.reg
& 7))
4793 /* For fstp m64fp. */
4794 if (i386_record_floats (gdbarch
, &ir
,
4795 I386_SAVE_FPU_REGS
))
4800 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4802 /* For fistp, fbld, fild, fbstp. */
4803 if (i386_record_floats (gdbarch
, &ir
,
4804 I386_SAVE_FPU_REGS
))
4809 if (record_arch_list_add_mem (addr64
, 2))
4818 if (i386_record_floats (gdbarch
, &ir
,
4819 I386_SAVE_FPU_ENV_REG_STACK
))
4824 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4829 if (i386_record_floats (gdbarch
, &ir
,
4830 I386_SAVE_FPU_ENV_REG_STACK
))
4836 if (record_arch_list_add_mem (addr64
, 28))
4841 if (record_arch_list_add_mem (addr64
, 14))
4847 if (record_arch_list_add_mem (addr64
, 2))
4849 /* Insn fstp, fbstp. */
4850 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4855 if (record_arch_list_add_mem (addr64
, 10))
4861 if (record_arch_list_add_mem (addr64
, 28))
4867 if (record_arch_list_add_mem (addr64
, 14))
4871 if (record_arch_list_add_mem (addr64
, 80))
4874 if (i386_record_floats (gdbarch
, &ir
,
4875 I386_SAVE_FPU_ENV_REG_STACK
))
4879 if (record_arch_list_add_mem (addr64
, 8))
4882 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4887 opcode
= opcode
<< 8 | ir
.modrm
;
4892 /* Opcode is an extension of modR/M byte. */
4898 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4902 if (0x0c == (ir
.modrm
>> 4))
4904 if ((ir
.modrm
& 0x0f) <= 7)
4906 if (i386_record_floats (gdbarch
, &ir
,
4907 I386_SAVE_FPU_REGS
))
4912 if (i386_record_floats (gdbarch
, &ir
,
4913 I387_ST0_REGNUM (tdep
)))
4915 /* If only st(0) is changing, then we have already
4917 if ((ir
.modrm
& 0x0f) - 0x08)
4919 if (i386_record_floats (gdbarch
, &ir
,
4920 I387_ST0_REGNUM (tdep
) +
4921 ((ir
.modrm
& 0x0f) - 0x08)))
4939 if (i386_record_floats (gdbarch
, &ir
,
4940 I387_ST0_REGNUM (tdep
)))
4958 if (i386_record_floats (gdbarch
, &ir
,
4959 I386_SAVE_FPU_REGS
))
4963 if (i386_record_floats (gdbarch
, &ir
,
4964 I387_ST0_REGNUM (tdep
)))
4966 if (i386_record_floats (gdbarch
, &ir
,
4967 I387_ST0_REGNUM (tdep
) + 1))
4974 if (0xe9 == ir
.modrm
)
4976 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4979 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4981 if (i386_record_floats (gdbarch
, &ir
,
4982 I387_ST0_REGNUM (tdep
)))
4984 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4986 if (i386_record_floats (gdbarch
, &ir
,
4987 I387_ST0_REGNUM (tdep
) +
4991 else if ((ir
.modrm
& 0x0f) - 0x08)
4993 if (i386_record_floats (gdbarch
, &ir
,
4994 I387_ST0_REGNUM (tdep
) +
4995 ((ir
.modrm
& 0x0f) - 0x08)))
5001 if (0xe3 == ir
.modrm
)
5003 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5006 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5008 if (i386_record_floats (gdbarch
, &ir
,
5009 I387_ST0_REGNUM (tdep
)))
5011 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5013 if (i386_record_floats (gdbarch
, &ir
,
5014 I387_ST0_REGNUM (tdep
) +
5018 else if ((ir
.modrm
& 0x0f) - 0x08)
5020 if (i386_record_floats (gdbarch
, &ir
,
5021 I387_ST0_REGNUM (tdep
) +
5022 ((ir
.modrm
& 0x0f) - 0x08)))
5028 if ((0x0c == ir
.modrm
>> 4)
5029 || (0x0d == ir
.modrm
>> 4)
5030 || (0x0f == ir
.modrm
>> 4))
5032 if ((ir
.modrm
& 0x0f) <= 7)
5034 if (i386_record_floats (gdbarch
, &ir
,
5035 I387_ST0_REGNUM (tdep
) +
5041 if (i386_record_floats (gdbarch
, &ir
,
5042 I387_ST0_REGNUM (tdep
) +
5043 ((ir
.modrm
& 0x0f) - 0x08)))
5049 if (0x0c == ir
.modrm
>> 4)
5051 if (i386_record_floats (gdbarch
, &ir
,
5052 I387_FTAG_REGNUM (tdep
)))
5055 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5057 if ((ir
.modrm
& 0x0f) <= 7)
5059 if (i386_record_floats (gdbarch
, &ir
,
5060 I387_ST0_REGNUM (tdep
) +
5066 if (i386_record_floats (gdbarch
, &ir
,
5067 I386_SAVE_FPU_REGS
))
5073 if ((0x0c == ir
.modrm
>> 4)
5074 || (0x0e == ir
.modrm
>> 4)
5075 || (0x0f == ir
.modrm
>> 4)
5076 || (0xd9 == ir
.modrm
))
5078 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5083 if (0xe0 == ir
.modrm
)
5085 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5088 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5090 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5098 case 0xa4: /* movsS */
5100 case 0xaa: /* stosS */
5102 case 0x6c: /* insS */
5104 regcache_raw_read_unsigned (ir
.regcache
,
5105 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5111 if ((opcode
& 1) == 0)
5114 ir
.ot
= ir
.dflag
+ OT_WORD
;
5115 regcache_raw_read_unsigned (ir
.regcache
,
5116 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5119 regcache_raw_read_unsigned (ir
.regcache
,
5120 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5122 regcache_raw_read_unsigned (ir
.regcache
,
5123 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5125 if (ir
.aflag
&& (es
!= ds
))
5127 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5128 if (record_memory_query
)
5132 target_terminal_ours ();
5134 Process record ignores the memory change of instruction at address %s\n\
5135 because it can't get the value of the segment register.\n\
5136 Do you want to stop the program?"),
5137 paddress (gdbarch
, ir
.orig_addr
));
5138 target_terminal_inferior ();
5145 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5149 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5150 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5151 if (opcode
== 0xa4 || opcode
== 0xa5)
5152 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5153 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5158 case 0xa6: /* cmpsS */
5160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5162 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5163 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5167 case 0xac: /* lodsS */
5169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5171 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5176 case 0xae: /* scasS */
5178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5179 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5180 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5181 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5184 case 0x6e: /* outsS */
5186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5187 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5188 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5192 case 0xe4: /* port I/O */
5196 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5207 case 0xc2: /* ret im */
5208 case 0xc3: /* ret */
5209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5210 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5213 case 0xca: /* lret im */
5214 case 0xcb: /* lret */
5215 case 0xcf: /* iret */
5216 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5218 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5221 case 0xe8: /* call im */
5222 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5224 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5228 case 0x9a: /* lcall im */
5229 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5235 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5239 case 0xe9: /* jmp im */
5240 case 0xea: /* ljmp im */
5241 case 0xeb: /* jmp Jb */
5242 case 0x70: /* jcc Jb */
5258 case 0x0f80: /* jcc Jv */
5276 case 0x0f90: /* setcc Gv */
5292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5294 if (i386_record_modrm (&ir
))
5297 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5301 if (i386_record_lea_modrm (&ir
))
5306 case 0x0f40: /* cmov Gv, Ev */
5322 if (i386_record_modrm (&ir
))
5325 if (ir
.dflag
== OT_BYTE
)
5327 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5331 case 0x9c: /* pushf */
5332 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5333 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5335 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5339 case 0x9d: /* popf */
5340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5344 case 0x9e: /* sahf */
5345 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5351 case 0xf5: /* cmc */
5352 case 0xf8: /* clc */
5353 case 0xf9: /* stc */
5354 case 0xfc: /* cld */
5355 case 0xfd: /* std */
5356 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5359 case 0x9f: /* lahf */
5360 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5365 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5369 /* bit operations */
5370 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5371 ir
.ot
= ir
.dflag
+ OT_WORD
;
5372 if (i386_record_modrm (&ir
))
5377 opcode
= opcode
<< 8 | ir
.modrm
;
5383 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5386 if (i386_record_lea_modrm (&ir
))
5390 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5393 case 0x0fa3: /* bt Gv, Ev */
5394 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5397 case 0x0fab: /* bts */
5398 case 0x0fb3: /* btr */
5399 case 0x0fbb: /* btc */
5400 ir
.ot
= ir
.dflag
+ OT_WORD
;
5401 if (i386_record_modrm (&ir
))
5404 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5408 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5410 regcache_raw_read_unsigned (ir
.regcache
,
5411 ir
.regmap
[ir
.reg
| rex_r
],
5416 addr64
+= ((int16_t) addr
>> 4) << 4;
5419 addr64
+= ((int32_t) addr
>> 5) << 5;
5422 addr64
+= ((int64_t) addr
>> 6) << 6;
5425 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5427 if (i386_record_lea_modrm (&ir
))
5430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5433 case 0x0fbc: /* bsf */
5434 case 0x0fbd: /* bsr */
5435 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5436 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5440 case 0x27: /* daa */
5441 case 0x2f: /* das */
5442 case 0x37: /* aaa */
5443 case 0x3f: /* aas */
5444 case 0xd4: /* aam */
5445 case 0xd5: /* aad */
5446 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5456 case 0x90: /* nop */
5457 if (prefixes
& PREFIX_LOCK
)
5464 case 0x9b: /* fwait */
5465 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5468 printf_unfiltered (_("Process record: error reading memory at "
5469 "addr 0x%s len = 1.\n"),
5470 paddress (gdbarch
, ir
.addr
));
5473 opcode
= (uint32_t) opcode8
;
5479 case 0xcc: /* int3 */
5480 printf_unfiltered (_("Process record does not support instruction "
5487 case 0xcd: /* int */
5491 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5494 printf_unfiltered (_("Process record: error reading memory "
5495 "at addr %s len = 1.\n"),
5496 paddress (gdbarch
, ir
.addr
));
5500 if (interrupt
!= 0x80
5501 || tdep
->i386_intx80_record
== NULL
)
5503 printf_unfiltered (_("Process record does not support "
5504 "instruction int 0x%02x.\n"),
5509 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5516 case 0xce: /* into */
5517 printf_unfiltered (_("Process record does not support "
5518 "instruction into.\n"));
5523 case 0xfa: /* cli */
5524 case 0xfb: /* sti */
5527 case 0x62: /* bound */
5528 printf_unfiltered (_("Process record does not support "
5529 "instruction bound.\n"));
5534 case 0x0fc8: /* bswap reg */
5542 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5545 case 0xd6: /* salc */
5546 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5551 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5552 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5555 case 0xe0: /* loopnz */
5556 case 0xe1: /* loopz */
5557 case 0xe2: /* loop */
5558 case 0xe3: /* jecxz */
5559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5563 case 0x0f30: /* wrmsr */
5564 printf_unfiltered (_("Process record does not support "
5565 "instruction wrmsr.\n"));
5570 case 0x0f32: /* rdmsr */
5571 printf_unfiltered (_("Process record does not support "
5572 "instruction rdmsr.\n"));
5577 case 0x0f31: /* rdtsc */
5578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5582 case 0x0f34: /* sysenter */
5585 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5590 if (tdep
->i386_sysenter_record
== NULL
)
5592 printf_unfiltered (_("Process record does not support "
5593 "instruction sysenter.\n"));
5597 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5603 case 0x0f35: /* sysexit */
5604 printf_unfiltered (_("Process record does not support "
5605 "instruction sysexit.\n"));
5610 case 0x0f05: /* syscall */
5613 if (tdep
->i386_syscall_record
== NULL
)
5615 printf_unfiltered (_("Process record does not support "
5616 "instruction syscall.\n"));
5620 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5626 case 0x0f07: /* sysret */
5627 printf_unfiltered (_("Process record does not support "
5628 "instruction sysret.\n"));
5633 case 0x0fa2: /* cpuid */
5634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5637 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5640 case 0xf4: /* hlt */
5641 printf_unfiltered (_("Process record does not support "
5642 "instruction hlt.\n"));
5648 if (i386_record_modrm (&ir
))
5655 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5659 if (i386_record_lea_modrm (&ir
))
5668 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5672 opcode
= opcode
<< 8 | ir
.modrm
;
5679 if (i386_record_modrm (&ir
))
5690 opcode
= opcode
<< 8 | ir
.modrm
;
5693 if (ir
.override
>= 0)
5695 if (record_memory_query
)
5699 target_terminal_ours ();
5701 Process record ignores the memory change of instruction at address %s\n\
5702 because it can't get the value of the segment register.\n\
5703 Do you want to stop the program?"),
5704 paddress (gdbarch
, ir
.orig_addr
));
5705 target_terminal_inferior ();
5712 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5714 if (record_arch_list_add_mem (addr64
, 2))
5717 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5719 if (record_arch_list_add_mem (addr64
, 8))
5724 if (record_arch_list_add_mem (addr64
, 4))
5735 case 0: /* monitor */
5738 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5742 opcode
= opcode
<< 8 | ir
.modrm
;
5750 if (ir
.override
>= 0)
5752 if (record_memory_query
)
5756 target_terminal_ours ();
5758 Process record ignores the memory change of instruction at address %s\n\
5759 because it can't get the value of the segment register.\n\
5760 Do you want to stop the program?"),
5761 paddress (gdbarch
, ir
.orig_addr
));
5762 target_terminal_inferior ();
5771 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5773 if (record_arch_list_add_mem (addr64
, 2))
5776 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5778 if (record_arch_list_add_mem (addr64
, 8))
5783 if (record_arch_list_add_mem (addr64
, 4))
5795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5800 else if (ir
.rm
== 1)
5807 opcode
= opcode
<< 8 | ir
.modrm
;
5814 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5820 if (i386_record_lea_modrm (&ir
))
5823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5828 case 7: /* invlpg */
5831 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5836 opcode
= opcode
<< 8 | ir
.modrm
;
5841 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5845 opcode
= opcode
<< 8 | ir
.modrm
;
5851 case 0x0f08: /* invd */
5852 case 0x0f09: /* wbinvd */
5855 case 0x63: /* arpl */
5856 if (i386_record_modrm (&ir
))
5858 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5860 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5861 ? (ir
.reg
| rex_r
) : ir
.rm
);
5865 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5866 if (i386_record_lea_modrm (&ir
))
5869 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5873 case 0x0f02: /* lar */
5874 case 0x0f03: /* lsl */
5875 if (i386_record_modrm (&ir
))
5877 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5882 if (i386_record_modrm (&ir
))
5884 if (ir
.mod
== 3 && ir
.reg
== 3)
5887 opcode
= opcode
<< 8 | ir
.modrm
;
5899 /* nop (multi byte) */
5902 case 0x0f20: /* mov reg, crN */
5903 case 0x0f22: /* mov crN, reg */
5904 if (i386_record_modrm (&ir
))
5906 if ((ir
.modrm
& 0xc0) != 0xc0)
5909 opcode
= opcode
<< 8 | ir
.modrm
;
5920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5922 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5926 opcode
= opcode
<< 8 | ir
.modrm
;
5932 case 0x0f21: /* mov reg, drN */
5933 case 0x0f23: /* mov drN, reg */
5934 if (i386_record_modrm (&ir
))
5936 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5937 || ir
.reg
== 5 || ir
.reg
>= 8)
5940 opcode
= opcode
<< 8 | ir
.modrm
;
5944 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5946 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5949 case 0x0f06: /* clts */
5950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5953 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5955 case 0x0f0d: /* 3DNow! prefetch */
5958 case 0x0f0e: /* 3DNow! femms */
5959 case 0x0f77: /* emms */
5960 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
5962 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
5965 case 0x0f0f: /* 3DNow! data */
5966 if (i386_record_modrm (&ir
))
5968 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5970 printf_unfiltered (_("Process record: error reading memory at "
5971 "addr %s len = 1.\n"),
5972 paddress (gdbarch
, ir
.addr
));
5978 case 0x0c: /* 3DNow! pi2fw */
5979 case 0x0d: /* 3DNow! pi2fd */
5980 case 0x1c: /* 3DNow! pf2iw */
5981 case 0x1d: /* 3DNow! pf2id */
5982 case 0x8a: /* 3DNow! pfnacc */
5983 case 0x8e: /* 3DNow! pfpnacc */
5984 case 0x90: /* 3DNow! pfcmpge */
5985 case 0x94: /* 3DNow! pfmin */
5986 case 0x96: /* 3DNow! pfrcp */
5987 case 0x97: /* 3DNow! pfrsqrt */
5988 case 0x9a: /* 3DNow! pfsub */
5989 case 0x9e: /* 3DNow! pfadd */
5990 case 0xa0: /* 3DNow! pfcmpgt */
5991 case 0xa4: /* 3DNow! pfmax */
5992 case 0xa6: /* 3DNow! pfrcpit1 */
5993 case 0xa7: /* 3DNow! pfrsqit1 */
5994 case 0xaa: /* 3DNow! pfsubr */
5995 case 0xae: /* 3DNow! pfacc */
5996 case 0xb0: /* 3DNow! pfcmpeq */
5997 case 0xb4: /* 3DNow! pfmul */
5998 case 0xb6: /* 3DNow! pfrcpit2 */
5999 case 0xb7: /* 3DNow! pmulhrw */
6000 case 0xbb: /* 3DNow! pswapd */
6001 case 0xbf: /* 3DNow! pavgusb */
6002 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6003 goto no_support_3dnow_data
;
6004 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6008 no_support_3dnow_data
:
6009 opcode
= (opcode
<< 8) | opcode8
;
6015 case 0x0faa: /* rsm */
6016 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6017 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6018 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6019 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6020 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6021 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6022 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6028 if (i386_record_modrm (&ir
))
6032 case 0: /* fxsave */
6036 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6037 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6039 if (record_arch_list_add_mem (tmpu64
, 512))
6044 case 1: /* fxrstor */
6048 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6050 for (i
= I387_MM0_REGNUM (tdep
);
6051 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6052 record_arch_list_add_reg (ir
.regcache
, i
);
6054 for (i
= I387_XMM0_REGNUM (tdep
);
6055 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6056 record_arch_list_add_reg (ir
.regcache
, i
);
6058 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6059 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6061 for (i
= I387_ST0_REGNUM (tdep
);
6062 i386_fp_regnum_p (gdbarch
, i
); i
++)
6063 record_arch_list_add_reg (ir
.regcache
, i
);
6065 for (i
= I387_FCTRL_REGNUM (tdep
);
6066 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6067 record_arch_list_add_reg (ir
.regcache
, i
);
6071 case 2: /* ldmxcsr */
6072 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6074 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6077 case 3: /* stmxcsr */
6079 if (i386_record_lea_modrm (&ir
))
6083 case 5: /* lfence */
6084 case 6: /* mfence */
6085 case 7: /* sfence clflush */
6089 opcode
= (opcode
<< 8) | ir
.modrm
;
6095 case 0x0fc3: /* movnti */
6096 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6097 if (i386_record_modrm (&ir
))
6102 if (i386_record_lea_modrm (&ir
))
6106 /* Add prefix to opcode. */
6233 reswitch_prefix_add
:
6241 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6243 printf_unfiltered (_("Process record: error reading memory at "
6244 "addr %s len = 1.\n"),
6245 paddress (gdbarch
, ir
.addr
));
6249 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6250 goto reswitch_prefix_add
;
6253 case 0x0f10: /* movups */
6254 case 0x660f10: /* movupd */
6255 case 0xf30f10: /* movss */
6256 case 0xf20f10: /* movsd */
6257 case 0x0f12: /* movlps */
6258 case 0x660f12: /* movlpd */
6259 case 0xf30f12: /* movsldup */
6260 case 0xf20f12: /* movddup */
6261 case 0x0f14: /* unpcklps */
6262 case 0x660f14: /* unpcklpd */
6263 case 0x0f15: /* unpckhps */
6264 case 0x660f15: /* unpckhpd */
6265 case 0x0f16: /* movhps */
6266 case 0x660f16: /* movhpd */
6267 case 0xf30f16: /* movshdup */
6268 case 0x0f28: /* movaps */
6269 case 0x660f28: /* movapd */
6270 case 0x0f2a: /* cvtpi2ps */
6271 case 0x660f2a: /* cvtpi2pd */
6272 case 0xf30f2a: /* cvtsi2ss */
6273 case 0xf20f2a: /* cvtsi2sd */
6274 case 0x0f2c: /* cvttps2pi */
6275 case 0x660f2c: /* cvttpd2pi */
6276 case 0x0f2d: /* cvtps2pi */
6277 case 0x660f2d: /* cvtpd2pi */
6278 case 0x660f3800: /* pshufb */
6279 case 0x660f3801: /* phaddw */
6280 case 0x660f3802: /* phaddd */
6281 case 0x660f3803: /* phaddsw */
6282 case 0x660f3804: /* pmaddubsw */
6283 case 0x660f3805: /* phsubw */
6284 case 0x660f3806: /* phsubd */
6285 case 0x660f3807: /* phsubsw */
6286 case 0x660f3808: /* psignb */
6287 case 0x660f3809: /* psignw */
6288 case 0x660f380a: /* psignd */
6289 case 0x660f380b: /* pmulhrsw */
6290 case 0x660f3810: /* pblendvb */
6291 case 0x660f3814: /* blendvps */
6292 case 0x660f3815: /* blendvpd */
6293 case 0x660f381c: /* pabsb */
6294 case 0x660f381d: /* pabsw */
6295 case 0x660f381e: /* pabsd */
6296 case 0x660f3820: /* pmovsxbw */
6297 case 0x660f3821: /* pmovsxbd */
6298 case 0x660f3822: /* pmovsxbq */
6299 case 0x660f3823: /* pmovsxwd */
6300 case 0x660f3824: /* pmovsxwq */
6301 case 0x660f3825: /* pmovsxdq */
6302 case 0x660f3828: /* pmuldq */
6303 case 0x660f3829: /* pcmpeqq */
6304 case 0x660f382a: /* movntdqa */
6305 case 0x660f3a08: /* roundps */
6306 case 0x660f3a09: /* roundpd */
6307 case 0x660f3a0a: /* roundss */
6308 case 0x660f3a0b: /* roundsd */
6309 case 0x660f3a0c: /* blendps */
6310 case 0x660f3a0d: /* blendpd */
6311 case 0x660f3a0e: /* pblendw */
6312 case 0x660f3a0f: /* palignr */
6313 case 0x660f3a20: /* pinsrb */
6314 case 0x660f3a21: /* insertps */
6315 case 0x660f3a22: /* pinsrd pinsrq */
6316 case 0x660f3a40: /* dpps */
6317 case 0x660f3a41: /* dppd */
6318 case 0x660f3a42: /* mpsadbw */
6319 case 0x660f3a60: /* pcmpestrm */
6320 case 0x660f3a61: /* pcmpestri */
6321 case 0x660f3a62: /* pcmpistrm */
6322 case 0x660f3a63: /* pcmpistri */
6323 case 0x0f51: /* sqrtps */
6324 case 0x660f51: /* sqrtpd */
6325 case 0xf20f51: /* sqrtsd */
6326 case 0xf30f51: /* sqrtss */
6327 case 0x0f52: /* rsqrtps */
6328 case 0xf30f52: /* rsqrtss */
6329 case 0x0f53: /* rcpps */
6330 case 0xf30f53: /* rcpss */
6331 case 0x0f54: /* andps */
6332 case 0x660f54: /* andpd */
6333 case 0x0f55: /* andnps */
6334 case 0x660f55: /* andnpd */
6335 case 0x0f56: /* orps */
6336 case 0x660f56: /* orpd */
6337 case 0x0f57: /* xorps */
6338 case 0x660f57: /* xorpd */
6339 case 0x0f58: /* addps */
6340 case 0x660f58: /* addpd */
6341 case 0xf20f58: /* addsd */
6342 case 0xf30f58: /* addss */
6343 case 0x0f59: /* mulps */
6344 case 0x660f59: /* mulpd */
6345 case 0xf20f59: /* mulsd */
6346 case 0xf30f59: /* mulss */
6347 case 0x0f5a: /* cvtps2pd */
6348 case 0x660f5a: /* cvtpd2ps */
6349 case 0xf20f5a: /* cvtsd2ss */
6350 case 0xf30f5a: /* cvtss2sd */
6351 case 0x0f5b: /* cvtdq2ps */
6352 case 0x660f5b: /* cvtps2dq */
6353 case 0xf30f5b: /* cvttps2dq */
6354 case 0x0f5c: /* subps */
6355 case 0x660f5c: /* subpd */
6356 case 0xf20f5c: /* subsd */
6357 case 0xf30f5c: /* subss */
6358 case 0x0f5d: /* minps */
6359 case 0x660f5d: /* minpd */
6360 case 0xf20f5d: /* minsd */
6361 case 0xf30f5d: /* minss */
6362 case 0x0f5e: /* divps */
6363 case 0x660f5e: /* divpd */
6364 case 0xf20f5e: /* divsd */
6365 case 0xf30f5e: /* divss */
6366 case 0x0f5f: /* maxps */
6367 case 0x660f5f: /* maxpd */
6368 case 0xf20f5f: /* maxsd */
6369 case 0xf30f5f: /* maxss */
6370 case 0x660f60: /* punpcklbw */
6371 case 0x660f61: /* punpcklwd */
6372 case 0x660f62: /* punpckldq */
6373 case 0x660f63: /* packsswb */
6374 case 0x660f64: /* pcmpgtb */
6375 case 0x660f65: /* pcmpgtw */
6376 case 0x660f66: /* pcmpgtd */
6377 case 0x660f67: /* packuswb */
6378 case 0x660f68: /* punpckhbw */
6379 case 0x660f69: /* punpckhwd */
6380 case 0x660f6a: /* punpckhdq */
6381 case 0x660f6b: /* packssdw */
6382 case 0x660f6c: /* punpcklqdq */
6383 case 0x660f6d: /* punpckhqdq */
6384 case 0x660f6e: /* movd */
6385 case 0x660f6f: /* movdqa */
6386 case 0xf30f6f: /* movdqu */
6387 case 0x660f70: /* pshufd */
6388 case 0xf20f70: /* pshuflw */
6389 case 0xf30f70: /* pshufhw */
6390 case 0x660f74: /* pcmpeqb */
6391 case 0x660f75: /* pcmpeqw */
6392 case 0x660f76: /* pcmpeqd */
6393 case 0x660f7c: /* haddpd */
6394 case 0xf20f7c: /* haddps */
6395 case 0x660f7d: /* hsubpd */
6396 case 0xf20f7d: /* hsubps */
6397 case 0xf30f7e: /* movq */
6398 case 0x0fc2: /* cmpps */
6399 case 0x660fc2: /* cmppd */
6400 case 0xf20fc2: /* cmpsd */
6401 case 0xf30fc2: /* cmpss */
6402 case 0x660fc4: /* pinsrw */
6403 case 0x0fc6: /* shufps */
6404 case 0x660fc6: /* shufpd */
6405 case 0x660fd0: /* addsubpd */
6406 case 0xf20fd0: /* addsubps */
6407 case 0x660fd1: /* psrlw */
6408 case 0x660fd2: /* psrld */
6409 case 0x660fd3: /* psrlq */
6410 case 0x660fd4: /* paddq */
6411 case 0x660fd5: /* pmullw */
6412 case 0xf30fd6: /* movq2dq */
6413 case 0x660fd8: /* psubusb */
6414 case 0x660fd9: /* psubusw */
6415 case 0x660fda: /* pminub */
6416 case 0x660fdb: /* pand */
6417 case 0x660fdc: /* paddusb */
6418 case 0x660fdd: /* paddusw */
6419 case 0x660fde: /* pmaxub */
6420 case 0x660fdf: /* pandn */
6421 case 0x660fe0: /* pavgb */
6422 case 0x660fe1: /* psraw */
6423 case 0x660fe2: /* psrad */
6424 case 0x660fe3: /* pavgw */
6425 case 0x660fe4: /* pmulhuw */
6426 case 0x660fe5: /* pmulhw */
6427 case 0x660fe6: /* cvttpd2dq */
6428 case 0xf20fe6: /* cvtpd2dq */
6429 case 0xf30fe6: /* cvtdq2pd */
6430 case 0x660fe8: /* psubsb */
6431 case 0x660fe9: /* psubsw */
6432 case 0x660fea: /* pminsw */
6433 case 0x660feb: /* por */
6434 case 0x660fec: /* paddsb */
6435 case 0x660fed: /* paddsw */
6436 case 0x660fee: /* pmaxsw */
6437 case 0x660fef: /* pxor */
6438 case 0xf20ff0: /* lddqu */
6439 case 0x660ff1: /* psllw */
6440 case 0x660ff2: /* pslld */
6441 case 0x660ff3: /* psllq */
6442 case 0x660ff4: /* pmuludq */
6443 case 0x660ff5: /* pmaddwd */
6444 case 0x660ff6: /* psadbw */
6445 case 0x660ff8: /* psubb */
6446 case 0x660ff9: /* psubw */
6447 case 0x660ffa: /* psubd */
6448 case 0x660ffb: /* psubq */
6449 case 0x660ffc: /* paddb */
6450 case 0x660ffd: /* paddw */
6451 case 0x660ffe: /* paddd */
6452 if (i386_record_modrm (&ir
))
6455 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6457 record_arch_list_add_reg (ir
.regcache
,
6458 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6459 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6463 case 0x0f11: /* movups */
6464 case 0x660f11: /* movupd */
6465 case 0xf30f11: /* movss */
6466 case 0xf20f11: /* movsd */
6467 case 0x0f13: /* movlps */
6468 case 0x660f13: /* movlpd */
6469 case 0x0f17: /* movhps */
6470 case 0x660f17: /* movhpd */
6471 case 0x0f29: /* movaps */
6472 case 0x660f29: /* movapd */
6473 case 0x660f3a14: /* pextrb */
6474 case 0x660f3a15: /* pextrw */
6475 case 0x660f3a16: /* pextrd pextrq */
6476 case 0x660f3a17: /* extractps */
6477 case 0x660f7f: /* movdqa */
6478 case 0xf30f7f: /* movdqu */
6479 if (i386_record_modrm (&ir
))
6483 if (opcode
== 0x0f13 || opcode
== 0x660f13
6484 || opcode
== 0x0f17 || opcode
== 0x660f17)
6487 if (!i386_xmm_regnum_p (gdbarch
,
6488 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6490 record_arch_list_add_reg (ir
.regcache
,
6491 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6513 if (i386_record_lea_modrm (&ir
))
6518 case 0x0f2b: /* movntps */
6519 case 0x660f2b: /* movntpd */
6520 case 0x0fe7: /* movntq */
6521 case 0x660fe7: /* movntdq */
6524 if (opcode
== 0x0fe7)
6528 if (i386_record_lea_modrm (&ir
))
6532 case 0xf30f2c: /* cvttss2si */
6533 case 0xf20f2c: /* cvttsd2si */
6534 case 0xf30f2d: /* cvtss2si */
6535 case 0xf20f2d: /* cvtsd2si */
6536 case 0xf20f38f0: /* crc32 */
6537 case 0xf20f38f1: /* crc32 */
6538 case 0x0f50: /* movmskps */
6539 case 0x660f50: /* movmskpd */
6540 case 0x0fc5: /* pextrw */
6541 case 0x660fc5: /* pextrw */
6542 case 0x0fd7: /* pmovmskb */
6543 case 0x660fd7: /* pmovmskb */
6544 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6547 case 0x0f3800: /* pshufb */
6548 case 0x0f3801: /* phaddw */
6549 case 0x0f3802: /* phaddd */
6550 case 0x0f3803: /* phaddsw */
6551 case 0x0f3804: /* pmaddubsw */
6552 case 0x0f3805: /* phsubw */
6553 case 0x0f3806: /* phsubd */
6554 case 0x0f3807: /* phsubsw */
6555 case 0x0f3808: /* psignb */
6556 case 0x0f3809: /* psignw */
6557 case 0x0f380a: /* psignd */
6558 case 0x0f380b: /* pmulhrsw */
6559 case 0x0f381c: /* pabsb */
6560 case 0x0f381d: /* pabsw */
6561 case 0x0f381e: /* pabsd */
6562 case 0x0f382b: /* packusdw */
6563 case 0x0f3830: /* pmovzxbw */
6564 case 0x0f3831: /* pmovzxbd */
6565 case 0x0f3832: /* pmovzxbq */
6566 case 0x0f3833: /* pmovzxwd */
6567 case 0x0f3834: /* pmovzxwq */
6568 case 0x0f3835: /* pmovzxdq */
6569 case 0x0f3837: /* pcmpgtq */
6570 case 0x0f3838: /* pminsb */
6571 case 0x0f3839: /* pminsd */
6572 case 0x0f383a: /* pminuw */
6573 case 0x0f383b: /* pminud */
6574 case 0x0f383c: /* pmaxsb */
6575 case 0x0f383d: /* pmaxsd */
6576 case 0x0f383e: /* pmaxuw */
6577 case 0x0f383f: /* pmaxud */
6578 case 0x0f3840: /* pmulld */
6579 case 0x0f3841: /* phminposuw */
6580 case 0x0f3a0f: /* palignr */
6581 case 0x0f60: /* punpcklbw */
6582 case 0x0f61: /* punpcklwd */
6583 case 0x0f62: /* punpckldq */
6584 case 0x0f63: /* packsswb */
6585 case 0x0f64: /* pcmpgtb */
6586 case 0x0f65: /* pcmpgtw */
6587 case 0x0f66: /* pcmpgtd */
6588 case 0x0f67: /* packuswb */
6589 case 0x0f68: /* punpckhbw */
6590 case 0x0f69: /* punpckhwd */
6591 case 0x0f6a: /* punpckhdq */
6592 case 0x0f6b: /* packssdw */
6593 case 0x0f6e: /* movd */
6594 case 0x0f6f: /* movq */
6595 case 0x0f70: /* pshufw */
6596 case 0x0f74: /* pcmpeqb */
6597 case 0x0f75: /* pcmpeqw */
6598 case 0x0f76: /* pcmpeqd */
6599 case 0x0fc4: /* pinsrw */
6600 case 0x0fd1: /* psrlw */
6601 case 0x0fd2: /* psrld */
6602 case 0x0fd3: /* psrlq */
6603 case 0x0fd4: /* paddq */
6604 case 0x0fd5: /* pmullw */
6605 case 0xf20fd6: /* movdq2q */
6606 case 0x0fd8: /* psubusb */
6607 case 0x0fd9: /* psubusw */
6608 case 0x0fda: /* pminub */
6609 case 0x0fdb: /* pand */
6610 case 0x0fdc: /* paddusb */
6611 case 0x0fdd: /* paddusw */
6612 case 0x0fde: /* pmaxub */
6613 case 0x0fdf: /* pandn */
6614 case 0x0fe0: /* pavgb */
6615 case 0x0fe1: /* psraw */
6616 case 0x0fe2: /* psrad */
6617 case 0x0fe3: /* pavgw */
6618 case 0x0fe4: /* pmulhuw */
6619 case 0x0fe5: /* pmulhw */
6620 case 0x0fe8: /* psubsb */
6621 case 0x0fe9: /* psubsw */
6622 case 0x0fea: /* pminsw */
6623 case 0x0feb: /* por */
6624 case 0x0fec: /* paddsb */
6625 case 0x0fed: /* paddsw */
6626 case 0x0fee: /* pmaxsw */
6627 case 0x0fef: /* pxor */
6628 case 0x0ff1: /* psllw */
6629 case 0x0ff2: /* pslld */
6630 case 0x0ff3: /* psllq */
6631 case 0x0ff4: /* pmuludq */
6632 case 0x0ff5: /* pmaddwd */
6633 case 0x0ff6: /* psadbw */
6634 case 0x0ff8: /* psubb */
6635 case 0x0ff9: /* psubw */
6636 case 0x0ffa: /* psubd */
6637 case 0x0ffb: /* psubq */
6638 case 0x0ffc: /* paddb */
6639 case 0x0ffd: /* paddw */
6640 case 0x0ffe: /* paddd */
6641 if (i386_record_modrm (&ir
))
6643 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6645 record_arch_list_add_reg (ir
.regcache
,
6646 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6649 case 0x0f71: /* psllw */
6650 case 0x0f72: /* pslld */
6651 case 0x0f73: /* psllq */
6652 if (i386_record_modrm (&ir
))
6654 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6656 record_arch_list_add_reg (ir
.regcache
,
6657 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6660 case 0x660f71: /* psllw */
6661 case 0x660f72: /* pslld */
6662 case 0x660f73: /* psllq */
6663 if (i386_record_modrm (&ir
))
6666 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6668 record_arch_list_add_reg (ir
.regcache
,
6669 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6672 case 0x0f7e: /* movd */
6673 case 0x660f7e: /* movd */
6674 if (i386_record_modrm (&ir
))
6677 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6684 if (i386_record_lea_modrm (&ir
))
6689 case 0x0f7f: /* movq */
6690 if (i386_record_modrm (&ir
))
6694 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6696 record_arch_list_add_reg (ir
.regcache
,
6697 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6702 if (i386_record_lea_modrm (&ir
))
6707 case 0xf30fb8: /* popcnt */
6708 if (i386_record_modrm (&ir
))
6710 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6711 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6714 case 0x660fd6: /* movq */
6715 if (i386_record_modrm (&ir
))
6720 if (!i386_xmm_regnum_p (gdbarch
,
6721 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6723 record_arch_list_add_reg (ir
.regcache
,
6724 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6729 if (i386_record_lea_modrm (&ir
))
6734 case 0x660f3817: /* ptest */
6735 case 0x0f2e: /* ucomiss */
6736 case 0x660f2e: /* ucomisd */
6737 case 0x0f2f: /* comiss */
6738 case 0x660f2f: /* comisd */
6739 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6742 case 0x0ff7: /* maskmovq */
6743 regcache_raw_read_unsigned (ir
.regcache
,
6744 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6746 if (record_arch_list_add_mem (addr
, 64))
6750 case 0x660ff7: /* maskmovdqu */
6751 regcache_raw_read_unsigned (ir
.regcache
,
6752 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6754 if (record_arch_list_add_mem (addr
, 128))
6769 /* In the future, maybe still need to deal with need_dasm. */
6770 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6771 if (record_arch_list_add_end ())
6777 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6778 "at address %s.\n"),
6779 (unsigned int) (opcode
),
6780 paddress (gdbarch
, ir
.orig_addr
));
6784 static const int i386_record_regmap
[] =
6786 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6787 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6788 0, 0, 0, 0, 0, 0, 0, 0,
6789 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6790 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6793 /* Check that the given address appears suitable for a fast
6794 tracepoint, which on x86 means that we need an instruction of at
6795 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6796 jump and not have to worry about program jumps to an address in the
6797 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6798 of instruction to replace, and 0 if not, plus an explanatory
6802 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6803 CORE_ADDR addr
, int *isize
, char **msg
)
6806 static struct ui_file
*gdb_null
= NULL
;
6808 /* This is based on the target agent using a 4-byte relative jump.
6809 Alternate future possibilities include 8-byte offset for x86-84,
6810 or 3-byte jumps if the program has trampoline space close by. */
6813 /* Dummy file descriptor for the disassembler. */
6815 gdb_null
= ui_file_new ();
6817 /* Check for fit. */
6818 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6821 /* Return a bit of target-specific detail to add to the caller's
6822 generic failure message. */
6824 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
6825 "need at least %d bytes for the jump"),
6838 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6839 struct tdesc_arch_data
*tdesc_data
)
6841 const struct target_desc
*tdesc
= tdep
->tdesc
;
6842 const struct tdesc_feature
*feature_core
;
6843 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6844 int i
, num_regs
, valid_p
;
6846 if (! tdesc_has_registers (tdesc
))
6849 /* Get core registers. */
6850 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6851 if (feature_core
== NULL
)
6854 /* Get SSE registers. */
6855 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6857 /* Try AVX registers. */
6858 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6862 /* The XCR0 bits. */
6865 /* AVX register description requires SSE register description. */
6869 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6871 /* It may have been set by OSABI initialization function. */
6872 if (tdep
->num_ymm_regs
== 0)
6874 tdep
->ymmh_register_names
= i386_ymmh_names
;
6875 tdep
->num_ymm_regs
= 8;
6876 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
6879 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
6880 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
6881 tdep
->ymm0h_regnum
+ i
,
6882 tdep
->ymmh_register_names
[i
]);
6884 else if (feature_sse
)
6885 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
6888 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
6889 tdep
->num_xmm_regs
= 0;
6892 num_regs
= tdep
->num_core_regs
;
6893 for (i
= 0; i
< num_regs
; i
++)
6894 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
6895 tdep
->register_names
[i
]);
6899 /* Need to include %mxcsr, so add one. */
6900 num_regs
+= tdep
->num_xmm_regs
+ 1;
6901 for (; i
< num_regs
; i
++)
6902 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
6903 tdep
->register_names
[i
]);
6910 static struct gdbarch
*
6911 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6913 struct gdbarch_tdep
*tdep
;
6914 struct gdbarch
*gdbarch
;
6915 struct tdesc_arch_data
*tdesc_data
;
6916 const struct target_desc
*tdesc
;
6920 /* If there is already a candidate, use it. */
6921 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6923 return arches
->gdbarch
;
6925 /* Allocate space for the new architecture. */
6926 tdep
= XCALLOC (1, struct gdbarch_tdep
);
6927 gdbarch
= gdbarch_alloc (&info
, tdep
);
6929 /* General-purpose registers. */
6930 tdep
->gregset
= NULL
;
6931 tdep
->gregset_reg_offset
= NULL
;
6932 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
6933 tdep
->sizeof_gregset
= 0;
6935 /* Floating-point registers. */
6936 tdep
->fpregset
= NULL
;
6937 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
6939 tdep
->xstateregset
= NULL
;
6941 /* The default settings include the FPU registers, the MMX registers
6942 and the SSE registers. This can be overridden for a specific ABI
6943 by adjusting the members `st0_regnum', `mm0_regnum' and
6944 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6945 will show up in the output of "info all-registers". */
6947 tdep
->st0_regnum
= I386_ST0_REGNUM
;
6949 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6950 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
6952 tdep
->jb_pc_offset
= -1;
6953 tdep
->struct_return
= pcc_struct_return
;
6954 tdep
->sigtramp_start
= 0;
6955 tdep
->sigtramp_end
= 0;
6956 tdep
->sigtramp_p
= i386_sigtramp_p
;
6957 tdep
->sigcontext_addr
= NULL
;
6958 tdep
->sc_reg_offset
= NULL
;
6959 tdep
->sc_pc_offset
= -1;
6960 tdep
->sc_sp_offset
= -1;
6962 tdep
->xsave_xcr0_offset
= -1;
6964 tdep
->record_regmap
= i386_record_regmap
;
6966 /* The format used for `long double' on almost all i386 targets is
6967 the i387 extended floating-point format. In fact, of all targets
6968 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6969 on having a `long double' that's not `long' at all. */
6970 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
6972 /* Although the i387 extended floating-point has only 80 significant
6973 bits, a `long double' actually takes up 96, probably to enforce
6975 set_gdbarch_long_double_bit (gdbarch
, 96);
6977 /* Register numbers of various important registers. */
6978 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
6979 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
6980 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
6981 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
6983 /* NOTE: kettenis/20040418: GCC does have two possible register
6984 numbering schemes on the i386: dbx and SVR4. These schemes
6985 differ in how they number %ebp, %esp, %eflags, and the
6986 floating-point registers, and are implemented by the arrays
6987 dbx_register_map[] and svr4_dbx_register_map in
6988 gcc/config/i386.c. GCC also defines a third numbering scheme in
6989 gcc/config/i386.c, which it designates as the "default" register
6990 map used in 64bit mode. This last register numbering scheme is
6991 implemented in dbx64_register_map, and is used for AMD64; see
6994 Currently, each GCC i386 target always uses the same register
6995 numbering scheme across all its supported debugging formats
6996 i.e. SDB (COFF), stabs and DWARF 2. This is because
6997 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6998 DBX_REGISTER_NUMBER macro which is defined by each target's
6999 respective config header in a manner independent of the requested
7000 output debugging format.
7002 This does not match the arrangement below, which presumes that
7003 the SDB and stabs numbering schemes differ from the DWARF and
7004 DWARF 2 ones. The reason for this arrangement is that it is
7005 likely to get the numbering scheme for the target's
7006 default/native debug format right. For targets where GCC is the
7007 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7008 targets where the native toolchain uses a different numbering
7009 scheme for a particular debug format (stabs-in-ELF on Solaris)
7010 the defaults below will have to be overridden, like
7011 i386_elf_init_abi() does. */
7013 /* Use the dbx register numbering scheme for stabs and COFF. */
7014 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7015 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7017 /* Use the SVR4 register numbering scheme for DWARF 2. */
7018 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7020 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7021 be in use on any of the supported i386 targets. */
7023 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7025 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7027 /* Call dummy code. */
7028 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7030 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7031 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7032 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7034 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7036 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7038 /* Stack grows downward. */
7039 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7041 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7042 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7043 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7045 set_gdbarch_frame_args_skip (gdbarch
, 8);
7047 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7049 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7051 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7053 /* Add the i386 register groups. */
7054 i386_add_reggroups (gdbarch
);
7055 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7057 /* Helper for function argument information. */
7058 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7060 /* Hook the function epilogue frame unwinder. This unwinder is
7061 appended to the list first, so that it supercedes the Dwarf
7062 unwinder in function epilogues (where the Dwarf unwinder
7063 currently fails). */
7064 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7066 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7067 to the list before the prologue-based unwinders, so that Dwarf
7068 CFI info will be used if it is available. */
7069 dwarf2_append_unwinders (gdbarch
);
7071 frame_base_set_default (gdbarch
, &i386_frame_base
);
7073 /* Pseudo registers may be changed by amd64_init_abi. */
7074 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7075 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7077 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7078 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7080 /* Override the normal target description method to make the AVX
7081 upper halves anonymous. */
7082 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7084 /* Even though the default ABI only includes general-purpose registers,
7085 floating-point registers and the SSE registers, we have to leave a
7086 gap for the upper AVX registers. */
7087 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7089 /* Get the x86 target description from INFO. */
7090 tdesc
= info
.target_desc
;
7091 if (! tdesc_has_registers (tdesc
))
7093 tdep
->tdesc
= tdesc
;
7095 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7096 tdep
->register_names
= i386_register_names
;
7098 /* No upper YMM registers. */
7099 tdep
->ymmh_register_names
= NULL
;
7100 tdep
->ymm0h_regnum
= -1;
7102 tdep
->num_byte_regs
= 8;
7103 tdep
->num_word_regs
= 8;
7104 tdep
->num_dword_regs
= 0;
7105 tdep
->num_mmx_regs
= 8;
7106 tdep
->num_ymm_regs
= 0;
7108 tdesc_data
= tdesc_data_alloc ();
7110 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7112 /* Hook in ABI-specific overrides, if they have been registered. */
7113 info
.tdep_info
= (void *) tdesc_data
;
7114 gdbarch_init_osabi (info
, gdbarch
);
7116 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7118 tdesc_data_cleanup (tdesc_data
);
7120 gdbarch_free (gdbarch
);
7124 /* Wire in pseudo registers. Number of pseudo registers may be
7126 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7127 + tdep
->num_word_regs
7128 + tdep
->num_dword_regs
7129 + tdep
->num_mmx_regs
7130 + tdep
->num_ymm_regs
));
7132 /* Target description may be changed. */
7133 tdesc
= tdep
->tdesc
;
7135 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7137 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7138 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7140 /* Make %al the first pseudo-register. */
7141 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7142 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7144 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7145 if (tdep
->num_dword_regs
)
7147 /* Support dword pseudo-register if it hasn't been disabled. */
7148 tdep
->eax_regnum
= ymm0_regnum
;
7149 ymm0_regnum
+= tdep
->num_dword_regs
;
7152 tdep
->eax_regnum
= -1;
7154 mm0_regnum
= ymm0_regnum
;
7155 if (tdep
->num_ymm_regs
)
7157 /* Support YMM pseudo-register if it is available. */
7158 tdep
->ymm0_regnum
= ymm0_regnum
;
7159 mm0_regnum
+= tdep
->num_ymm_regs
;
7162 tdep
->ymm0_regnum
= -1;
7164 if (tdep
->num_mmx_regs
!= 0)
7166 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7167 tdep
->mm0_regnum
= mm0_regnum
;
7170 tdep
->mm0_regnum
= -1;
7172 /* Hook in the legacy prologue-based unwinders last (fallback). */
7173 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7174 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7176 /* If we have a register mapping, enable the generic core file
7177 support, unless it has already been enabled. */
7178 if (tdep
->gregset_reg_offset
7179 && !gdbarch_regset_from_core_section_p (gdbarch
))
7180 set_gdbarch_regset_from_core_section (gdbarch
,
7181 i386_regset_from_core_section
);
7183 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7184 i386_skip_permanent_breakpoint
);
7186 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7187 i386_fast_tracepoint_valid_at
);
7192 static enum gdb_osabi
7193 i386_coff_osabi_sniffer (bfd
*abfd
)
7195 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7196 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7197 return GDB_OSABI_GO32
;
7199 return GDB_OSABI_UNKNOWN
;
7203 /* Provide a prototype to silence -Wmissing-prototypes. */
7204 void _initialize_i386_tdep (void);
7207 _initialize_i386_tdep (void)
7209 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7211 /* Add the variable that controls the disassembly flavor. */
7212 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7213 &disassembly_flavor
, _("\
7214 Set the disassembly flavor."), _("\
7215 Show the disassembly flavor."), _("\
7216 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7218 NULL
, /* FIXME: i18n: */
7219 &setlist
, &showlist
);
7221 /* Add the variable that controls the convention for returning
7223 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7224 &struct_convention
, _("\
7225 Set the convention for returning small structs."), _("\
7226 Show the convention for returning small structs."), _("\
7227 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7230 NULL
, /* FIXME: i18n: */
7231 &setlist
, &showlist
);
7233 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7234 i386_coff_osabi_sniffer
);
7236 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7237 i386_svr4_init_abi
);
7238 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7239 i386_go32_init_abi
);
7241 /* Initialize the i386-specific register groups. */
7242 i386_init_reggroups ();
7244 /* Initialize the standard target descriptions. */
7245 initialize_tdesc_i386 ();
7246 initialize_tdesc_i386_mmx ();
7247 initialize_tdesc_i386_avx ();
7249 /* Tell remote stub that we support XML target description. */
7250 register_remote_support_xml ("i386");