1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand) */
454 /* jump near, absolute indirect (/4) */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5) */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute */
475 /* Call near, absolute indirect (/2) */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3) */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
532 /* Fix up the state of registers and memory after having single-stepped
533 a displaced instruction. */
536 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
537 struct displaced_step_closure
*closure
,
538 CORE_ADDR from
, CORE_ADDR to
,
539 struct regcache
*regs
)
541 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
543 /* The offset we applied to the instruction's address.
544 This could well be negative (when viewed as a signed 32-bit
545 value), but ULONGEST won't reflect that, so take care when
547 ULONGEST insn_offset
= to
- from
;
549 /* Since we use simple_displaced_step_copy_insn, our closure is a
550 copy of the instruction. */
551 gdb_byte
*insn
= (gdb_byte
*) closure
;
552 /* The start of the insn, needed in case we see some prefixes. */
553 gdb_byte
*insn_start
= insn
;
556 fprintf_unfiltered (gdb_stdlog
,
557 "displaced: fixup (%s, %s), "
558 "insn = 0x%02x 0x%02x ...\n",
559 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
562 /* The list of issues to contend with here is taken from
563 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
564 Yay for Free Software! */
566 /* Relocate the %eip, if necessary. */
568 /* The instruction recognizers we use assume any leading prefixes
569 have been skipped. */
571 /* This is the size of the buffer in closure. */
572 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
573 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
574 /* If there are too many prefixes, just ignore the insn.
575 It will fault when run. */
580 /* Except in the case of absolute or indirect jump or call
581 instructions, or a return instruction, the new eip is relative to
582 the displaced instruction; make it relative. Well, signal
583 handler returns don't need relocation either, but we use the
584 value of %eip to recognize those; see below. */
585 if (! i386_absolute_jmp_p (insn
)
586 && ! i386_absolute_call_p (insn
)
587 && ! i386_ret_p (insn
))
592 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
594 /* A signal trampoline system call changes the %eip, resuming
595 execution of the main program after the signal handler has
596 returned. That makes them like 'return' instructions; we
597 shouldn't relocate %eip.
599 But most system calls don't, and we do need to relocate %eip.
601 Our heuristic for distinguishing these cases: if stepping
602 over the system call instruction left control directly after
603 the instruction, the we relocate --- control almost certainly
604 doesn't belong in the displaced copy. Otherwise, we assume
605 the instruction has put control where it belongs, and leave
606 it unrelocated. Goodness help us if there are PC-relative
608 if (i386_syscall_p (insn
, &insn_len
)
609 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
612 fprintf_unfiltered (gdb_stdlog
,
613 "displaced: syscall changed %%eip; "
618 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
620 /* If we just stepped over a breakpoint insn, we don't backup
621 the pc on purpose; this is to match behaviour without
624 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
627 fprintf_unfiltered (gdb_stdlog
,
629 "relocated %%eip from %s to %s\n",
630 paddress (gdbarch
, orig_eip
),
631 paddress (gdbarch
, eip
));
635 /* If the instruction was PUSHFL, then the TF bit will be set in the
636 pushed value, and should be cleared. We'll leave this for later,
637 since GDB already messes up the TF flag when stepping over a
640 /* If the instruction was a call, the return address now atop the
641 stack is the address following the copied instruction. We need
642 to make it the address following the original instruction. */
643 if (i386_call_p (insn
))
647 const ULONGEST retaddr_len
= 4;
649 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
650 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
651 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
652 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
655 fprintf_unfiltered (gdb_stdlog
,
656 "displaced: relocated return addr at %s to %s\n",
657 paddress (gdbarch
, esp
),
658 paddress (gdbarch
, retaddr
));
662 #ifdef I386_REGNO_TO_SYMMETRY
663 #error "The Sequent Symmetry is no longer supported."
666 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
667 and %esp "belong" to the calling function. Therefore these
668 registers should be saved if they're going to be modified. */
670 /* The maximum number of saved registers. This should include all
671 registers mentioned above, and %eip. */
672 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
674 struct i386_frame_cache
681 /* Saved registers. */
682 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
687 /* Stack space reserved for local variables. */
691 /* Allocate and initialize a frame cache. */
693 static struct i386_frame_cache
*
694 i386_alloc_frame_cache (void)
696 struct i386_frame_cache
*cache
;
699 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
703 cache
->sp_offset
= -4;
706 /* Saved registers. We initialize these to -1 since zero is a valid
707 offset (that's where %ebp is supposed to be stored). */
708 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
709 cache
->saved_regs
[i
] = -1;
711 cache
->saved_sp_reg
= -1;
712 cache
->pc_in_eax
= 0;
714 /* Frameless until proven otherwise. */
720 /* If the instruction at PC is a jump, return the address of its
721 target. Otherwise, return PC. */
724 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
726 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
731 target_read_memory (pc
, &op
, 1);
735 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
741 /* Relative jump: if data16 == 0, disp32, else disp16. */
744 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
746 /* Include the size of the jmp instruction (including the
752 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
754 /* Include the size of the jmp instruction. */
759 /* Relative jump, disp8 (ignore data16). */
760 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
769 /* Check whether PC points at a prologue for a function returning a
770 structure or union. If so, it updates CACHE and returns the
771 address of the first instruction after the code sequence that
772 removes the "hidden" argument from the stack or CURRENT_PC,
773 whichever is smaller. Otherwise, return PC. */
776 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
777 struct i386_frame_cache
*cache
)
779 /* Functions that return a structure or union start with:
782 xchgl %eax, (%esp) 0x87 0x04 0x24
783 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
785 (the System V compiler puts out the second `xchg' instruction,
786 and the assembler doesn't try to optimize it, so the 'sib' form
787 gets generated). This sequence is used to get the address of the
788 return buffer for a function that returns a structure. */
789 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
790 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
794 if (current_pc
<= pc
)
797 target_read_memory (pc
, &op
, 1);
799 if (op
!= 0x58) /* popl %eax */
802 target_read_memory (pc
+ 1, buf
, 4);
803 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
806 if (current_pc
== pc
)
808 cache
->sp_offset
+= 4;
812 if (current_pc
== pc
+ 1)
814 cache
->pc_in_eax
= 1;
818 if (buf
[1] == proto1
[1])
825 i386_skip_probe (CORE_ADDR pc
)
827 /* A function may start with
841 target_read_memory (pc
, &op
, 1);
843 if (op
== 0x68 || op
== 0x6a)
847 /* Skip past the `pushl' instruction; it has either a one-byte or a
848 four-byte operand, depending on the opcode. */
854 /* Read the following 8 bytes, which should be `call _probe' (6
855 bytes) followed by `addl $4,%esp' (2 bytes). */
856 read_memory (pc
+ delta
, buf
, sizeof (buf
));
857 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
858 pc
+= delta
+ sizeof (buf
);
864 /* GCC 4.1 and later, can put code in the prologue to realign the
865 stack pointer. Check whether PC points to such code, and update
866 CACHE accordingly. Return the first instruction after the code
867 sequence or CURRENT_PC, whichever is smaller. If we don't
868 recognize the code, return PC. */
871 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
872 struct i386_frame_cache
*cache
)
874 /* There are 2 code sequences to re-align stack before the frame
877 1. Use a caller-saved saved register:
883 2. Use a callee-saved saved register:
890 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
892 0x83 0xe4 0xf0 andl $-16, %esp
893 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
898 int offset
, offset_and
;
899 static int regnums
[8] = {
900 I386_EAX_REGNUM
, /* %eax */
901 I386_ECX_REGNUM
, /* %ecx */
902 I386_EDX_REGNUM
, /* %edx */
903 I386_EBX_REGNUM
, /* %ebx */
904 I386_ESP_REGNUM
, /* %esp */
905 I386_EBP_REGNUM
, /* %ebp */
906 I386_ESI_REGNUM
, /* %esi */
907 I386_EDI_REGNUM
/* %edi */
910 if (target_read_memory (pc
, buf
, sizeof buf
))
913 /* Check caller-saved saved register. The first instruction has
914 to be "leal 4(%esp), %reg". */
915 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
917 /* MOD must be binary 10 and R/M must be binary 100. */
918 if ((buf
[1] & 0xc7) != 0x44)
921 /* REG has register number. */
922 reg
= (buf
[1] >> 3) & 7;
927 /* Check callee-saved saved register. The first instruction
928 has to be "pushl %reg". */
929 if ((buf
[0] & 0xf8) != 0x50)
935 /* The next instruction has to be "leal 8(%esp), %reg". */
936 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
939 /* MOD must be binary 10 and R/M must be binary 100. */
940 if ((buf
[2] & 0xc7) != 0x44)
943 /* REG has register number. Registers in pushl and leal have to
945 if (reg
!= ((buf
[2] >> 3) & 7))
951 /* Rigister can't be %esp nor %ebp. */
952 if (reg
== 4 || reg
== 5)
955 /* The next instruction has to be "andl $-XXX, %esp". */
956 if (buf
[offset
+ 1] != 0xe4
957 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
961 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
963 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
964 0xfc. REG must be binary 110 and MOD must be binary 01. */
965 if (buf
[offset
] != 0xff
966 || buf
[offset
+ 2] != 0xfc
967 || (buf
[offset
+ 1] & 0xf8) != 0x70)
970 /* R/M has register. Registers in leal and pushl have to be the
972 if (reg
!= (buf
[offset
+ 1] & 7))
975 if (current_pc
> pc
+ offset_and
)
976 cache
->saved_sp_reg
= regnums
[reg
];
978 return min (pc
+ offset
+ 3, current_pc
);
981 /* Maximum instruction length we need to handle. */
982 #define I386_MAX_MATCHED_INSN_LEN 6
984 /* Instruction description. */
988 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
989 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
992 /* Search for the instruction at PC in the list SKIP_INSNS. Return
993 the first instruction description that matches. Otherwise, return
996 static struct i386_insn
*
997 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
999 struct i386_insn
*insn
;
1002 target_read_memory (pc
, &op
, 1);
1004 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1006 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1008 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1009 int insn_matched
= 1;
1012 gdb_assert (insn
->len
> 1);
1013 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1015 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
1016 for (i
= 1; i
< insn
->len
; i
++)
1018 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1030 /* Some special instructions that might be migrated by GCC into the
1031 part of the prologue that sets up the new stack frame. Because the
1032 stack frame hasn't been setup yet, no registers have been saved
1033 yet, and only the scratch registers %eax, %ecx and %edx can be
1036 struct i386_insn i386_frame_setup_skip_insns
[] =
1038 /* Check for `movb imm8, r' and `movl imm32, r'.
1040 ??? Should we handle 16-bit operand-sizes here? */
1042 /* `movb imm8, %al' and `movb imm8, %ah' */
1043 /* `movb imm8, %cl' and `movb imm8, %ch' */
1044 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1045 /* `movb imm8, %dl' and `movb imm8, %dh' */
1046 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1047 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1048 { 5, { 0xb8 }, { 0xfe } },
1049 /* `movl imm32, %edx' */
1050 { 5, { 0xba }, { 0xff } },
1052 /* Check for `mov imm32, r32'. Note that there is an alternative
1053 encoding for `mov m32, %eax'.
1055 ??? Should we handle SIB adressing here?
1056 ??? Should we handle 16-bit operand-sizes here? */
1058 /* `movl m32, %eax' */
1059 { 5, { 0xa1 }, { 0xff } },
1060 /* `movl m32, %eax' and `mov; m32, %ecx' */
1061 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1062 /* `movl m32, %edx' */
1063 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1065 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1066 Because of the symmetry, there are actually two ways to encode
1067 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1068 opcode bytes 0x31 and 0x33 for `xorl'. */
1070 /* `subl %eax, %eax' */
1071 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1072 /* `subl %ecx, %ecx' */
1073 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1074 /* `subl %edx, %edx' */
1075 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1076 /* `xorl %eax, %eax' */
1077 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1078 /* `xorl %ecx, %ecx' */
1079 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1080 /* `xorl %edx, %edx' */
1081 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1086 /* Check whether PC points to a no-op instruction. */
1088 i386_skip_noop (CORE_ADDR pc
)
1093 target_read_memory (pc
, &op
, 1);
1098 /* Ignore `nop' instruction. */
1102 target_read_memory (pc
, &op
, 1);
1105 /* Ignore no-op instruction `mov %edi, %edi'.
1106 Microsoft system dlls often start with
1107 a `mov %edi,%edi' instruction.
1108 The 5 bytes before the function start are
1109 filled with `nop' instructions.
1110 This pattern can be used for hot-patching:
1111 The `mov %edi, %edi' instruction can be replaced by a
1112 near jump to the location of the 5 `nop' instructions
1113 which can be replaced by a 32-bit jump to anywhere
1114 in the 32-bit address space. */
1116 else if (op
== 0x8b)
1118 target_read_memory (pc
+ 1, &op
, 1);
1122 target_read_memory (pc
, &op
, 1);
1130 /* Check whether PC points at a code that sets up a new stack frame.
1131 If so, it updates CACHE and returns the address of the first
1132 instruction after the sequence that sets up the frame or LIMIT,
1133 whichever is smaller. If we don't recognize the code, return PC. */
1136 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1137 CORE_ADDR pc
, CORE_ADDR limit
,
1138 struct i386_frame_cache
*cache
)
1140 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1141 struct i386_insn
*insn
;
1148 target_read_memory (pc
, &op
, 1);
1150 if (op
== 0x55) /* pushl %ebp */
1152 /* Take into account that we've executed the `pushl %ebp' that
1153 starts this instruction sequence. */
1154 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1155 cache
->sp_offset
+= 4;
1158 /* If that's all, return now. */
1162 /* Check for some special instructions that might be migrated by
1163 GCC into the prologue and skip them. At this point in the
1164 prologue, code should only touch the scratch registers %eax,
1165 %ecx and %edx, so while the number of posibilities is sheer,
1168 Make sure we only skip these instructions if we later see the
1169 `movl %esp, %ebp' that actually sets up the frame. */
1170 while (pc
+ skip
< limit
)
1172 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1179 /* If that's all, return now. */
1180 if (limit
<= pc
+ skip
)
1183 target_read_memory (pc
+ skip
, &op
, 1);
1185 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1189 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1194 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1202 /* OK, we actually have a frame. We just don't know how large
1203 it is yet. Set its size to zero. We'll adjust it if
1204 necessary. We also now commit to skipping the special
1205 instructions mentioned before. */
1209 /* If that's all, return now. */
1213 /* Check for stack adjustment
1217 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1218 reg, so we don't have to worry about a data16 prefix. */
1219 target_read_memory (pc
, &op
, 1);
1222 /* `subl' with 8-bit immediate. */
1223 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1224 /* Some instruction starting with 0x83 other than `subl'. */
1227 /* `subl' with signed 8-bit immediate (though it wouldn't
1228 make sense to be negative). */
1229 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1232 else if (op
== 0x81)
1234 /* Maybe it is `subl' with a 32-bit immediate. */
1235 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1236 /* Some instruction starting with 0x81 other than `subl'. */
1239 /* It is `subl' with a 32-bit immediate. */
1240 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1245 /* Some instruction other than `subl'. */
1249 else if (op
== 0xc8) /* enter */
1251 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1258 /* Check whether PC points at code that saves registers on the stack.
1259 If so, it updates CACHE and returns the address of the first
1260 instruction after the register saves or CURRENT_PC, whichever is
1261 smaller. Otherwise, return PC. */
1264 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1265 struct i386_frame_cache
*cache
)
1267 CORE_ADDR offset
= 0;
1271 if (cache
->locals
> 0)
1272 offset
-= cache
->locals
;
1273 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1275 target_read_memory (pc
, &op
, 1);
1276 if (op
< 0x50 || op
> 0x57)
1280 cache
->saved_regs
[op
- 0x50] = offset
;
1281 cache
->sp_offset
+= 4;
1288 /* Do a full analysis of the prologue at PC and update CACHE
1289 accordingly. Bail out early if CURRENT_PC is reached. Return the
1290 address where the analysis stopped.
1292 We handle these cases:
1294 The startup sequence can be at the start of the function, or the
1295 function can start with a branch to startup code at the end.
1297 %ebp can be set up with either the 'enter' instruction, or "pushl
1298 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1299 once used in the System V compiler).
1301 Local space is allocated just below the saved %ebp by either the
1302 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1303 16-bit unsigned argument for space to allocate, and the 'addl'
1304 instruction could have either a signed byte, or 32-bit immediate.
1306 Next, the registers used by this function are pushed. With the
1307 System V compiler they will always be in the order: %edi, %esi,
1308 %ebx (and sometimes a harmless bug causes it to also save but not
1309 restore %eax); however, the code below is willing to see the pushes
1310 in any order, and will handle up to 8 of them.
1312 If the setup sequence is at the end of the function, then the next
1313 instruction will be a branch back to the start. */
1316 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1317 CORE_ADDR pc
, CORE_ADDR current_pc
,
1318 struct i386_frame_cache
*cache
)
1320 pc
= i386_skip_noop (pc
);
1321 pc
= i386_follow_jump (gdbarch
, pc
);
1322 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1323 pc
= i386_skip_probe (pc
);
1324 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1325 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1326 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1329 /* Return PC of first real instruction. */
1332 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1334 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1336 static gdb_byte pic_pat
[6] =
1338 0xe8, 0, 0, 0, 0, /* call 0x0 */
1339 0x5b, /* popl %ebx */
1341 struct i386_frame_cache cache
;
1347 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1348 if (cache
.locals
< 0)
1351 /* Found valid frame setup. */
1353 /* The native cc on SVR4 in -K PIC mode inserts the following code
1354 to get the address of the global offset table (GOT) into register
1359 movl %ebx,x(%ebp) (optional)
1362 This code is with the rest of the prologue (at the end of the
1363 function), so we have to skip it to get to the first real
1364 instruction at the start of the function. */
1366 for (i
= 0; i
< 6; i
++)
1368 target_read_memory (pc
+ i
, &op
, 1);
1369 if (pic_pat
[i
] != op
)
1376 target_read_memory (pc
+ delta
, &op
, 1);
1378 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1380 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1382 if (op
== 0x5d) /* One byte offset from %ebp. */
1384 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1386 else /* Unexpected instruction. */
1389 target_read_memory (pc
+ delta
, &op
, 1);
1393 if (delta
> 0 && op
== 0x81
1394 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1401 /* If the function starts with a branch (to startup code at the end)
1402 the last instruction should bring us back to the first
1403 instruction of the real code. */
1404 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1405 pc
= i386_follow_jump (gdbarch
, pc
);
1410 /* Check that the code pointed to by PC corresponds to a call to
1411 __main, skip it if so. Return PC otherwise. */
1414 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1416 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1419 target_read_memory (pc
, &op
, 1);
1424 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1426 /* Make sure address is computed correctly as a 32bit
1427 integer even if CORE_ADDR is 64 bit wide. */
1428 struct minimal_symbol
*s
;
1429 CORE_ADDR call_dest
;
1431 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1432 call_dest
= call_dest
& 0xffffffffU
;
1433 s
= lookup_minimal_symbol_by_pc (call_dest
);
1435 && SYMBOL_LINKAGE_NAME (s
) != NULL
1436 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1444 /* This function is 64-bit safe. */
1447 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1451 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1452 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1456 /* Normal frames. */
1458 static struct i386_frame_cache
*
1459 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1461 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1462 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1463 struct i386_frame_cache
*cache
;
1470 cache
= i386_alloc_frame_cache ();
1471 *this_cache
= cache
;
1473 /* In principle, for normal frames, %ebp holds the frame pointer,
1474 which holds the base address for the current stack frame.
1475 However, for functions that don't need it, the frame pointer is
1476 optional. For these "frameless" functions the frame pointer is
1477 actually the frame pointer of the calling frame. Signal
1478 trampolines are just a special case of a "frameless" function.
1479 They (usually) share their frame pointer with the frame that was
1480 in progress when the signal occurred. */
1482 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1483 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1484 if (cache
->base
== 0)
1487 /* For normal frames, %eip is stored at 4(%ebp). */
1488 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1490 cache
->pc
= get_frame_func (this_frame
);
1492 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1495 if (cache
->saved_sp_reg
!= -1)
1497 /* Saved stack pointer has been saved. */
1498 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1499 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1502 if (cache
->locals
< 0)
1504 /* We didn't find a valid frame, which means that CACHE->base
1505 currently holds the frame pointer for our calling frame. If
1506 we're at the start of a function, or somewhere half-way its
1507 prologue, the function's frame probably hasn't been fully
1508 setup yet. Try to reconstruct the base address for the stack
1509 frame by looking at the stack pointer. For truly "frameless"
1510 functions this might work too. */
1512 if (cache
->saved_sp_reg
!= -1)
1514 /* We're halfway aligning the stack. */
1515 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1516 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1518 /* This will be added back below. */
1519 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1521 else if (cache
->pc
!= 0
1522 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1524 /* We're in a known function, but did not find a frame
1525 setup. Assume that the function does not use %ebp.
1526 Alternatively, we may have jumped to an invalid
1527 address; in that case there is definitely no new
1529 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1530 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1534 /* We're in an unknown function. We could not find the start
1535 of the function to analyze the prologue; our best option is
1536 to assume a typical frame layout with the caller's %ebp
1538 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1541 /* Now that we have the base address for the stack frame we can
1542 calculate the value of %esp in the calling frame. */
1543 if (cache
->saved_sp
== 0)
1544 cache
->saved_sp
= cache
->base
+ 8;
1546 /* Adjust all the saved registers such that they contain addresses
1547 instead of offsets. */
1548 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1549 if (cache
->saved_regs
[i
] != -1)
1550 cache
->saved_regs
[i
] += cache
->base
;
1556 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1557 struct frame_id
*this_id
)
1559 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1561 /* This marks the outermost frame. */
1562 if (cache
->base
== 0)
1565 /* See the end of i386_push_dummy_call. */
1566 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1569 static struct value
*
1570 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1573 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1575 gdb_assert (regnum
>= 0);
1577 /* The System V ABI says that:
1579 "The flags register contains the system flags, such as the
1580 direction flag and the carry flag. The direction flag must be
1581 set to the forward (that is, zero) direction before entry and
1582 upon exit from a function. Other user flags have no specified
1583 role in the standard calling sequence and are not preserved."
1585 To guarantee the "upon exit" part of that statement we fake a
1586 saved flags register that has its direction flag cleared.
1588 Note that GCC doesn't seem to rely on the fact that the direction
1589 flag is cleared after a function return; it always explicitly
1590 clears the flag before operations where it matters.
1592 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1593 right thing to do. The way we fake the flags register here makes
1594 it impossible to change it. */
1596 if (regnum
== I386_EFLAGS_REGNUM
)
1600 val
= get_frame_register_unsigned (this_frame
, regnum
);
1602 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1605 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1606 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1608 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1609 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1611 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1612 return frame_unwind_got_memory (this_frame
, regnum
,
1613 cache
->saved_regs
[regnum
]);
1615 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1618 static const struct frame_unwind i386_frame_unwind
=
1622 i386_frame_prev_register
,
1624 default_frame_sniffer
1627 /* Normal frames, but in a function epilogue. */
1629 /* The epilogue is defined here as the 'ret' instruction, which will
1630 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1631 the function's stack frame. */
1634 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1638 if (target_read_memory (pc
, &insn
, 1))
1639 return 0; /* Can't read memory at pc. */
1641 if (insn
!= 0xc3) /* 'ret' instruction. */
1648 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1649 struct frame_info
*this_frame
,
1650 void **this_prologue_cache
)
1652 if (frame_relative_level (this_frame
) == 0)
1653 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1654 get_frame_pc (this_frame
));
1659 static struct i386_frame_cache
*
1660 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1662 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1663 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1664 struct i386_frame_cache
*cache
;
1670 cache
= i386_alloc_frame_cache ();
1671 *this_cache
= cache
;
1673 /* Cache base will be %esp plus cache->sp_offset (-4). */
1674 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1675 cache
->base
= extract_unsigned_integer (buf
, 4,
1676 byte_order
) + cache
->sp_offset
;
1678 /* Cache pc will be the frame func. */
1679 cache
->pc
= get_frame_pc (this_frame
);
1681 /* The saved %esp will be at cache->base plus 8. */
1682 cache
->saved_sp
= cache
->base
+ 8;
1684 /* The saved %eip will be at cache->base plus 4. */
1685 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1691 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1693 struct frame_id
*this_id
)
1695 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1698 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1701 static const struct frame_unwind i386_epilogue_frame_unwind
=
1704 i386_epilogue_frame_this_id
,
1705 i386_frame_prev_register
,
1707 i386_epilogue_frame_sniffer
1711 /* Signal trampolines. */
1713 static struct i386_frame_cache
*
1714 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1716 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1718 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1719 struct i386_frame_cache
*cache
;
1726 cache
= i386_alloc_frame_cache ();
1728 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1729 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1731 addr
= tdep
->sigcontext_addr (this_frame
);
1732 if (tdep
->sc_reg_offset
)
1736 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1738 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1739 if (tdep
->sc_reg_offset
[i
] != -1)
1740 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1744 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1745 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1748 *this_cache
= cache
;
1753 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1754 struct frame_id
*this_id
)
1756 struct i386_frame_cache
*cache
=
1757 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1759 /* See the end of i386_push_dummy_call. */
1760 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1763 static struct value
*
1764 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1765 void **this_cache
, int regnum
)
1767 /* Make sure we've initialized the cache. */
1768 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1770 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1774 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1775 struct frame_info
*this_frame
,
1776 void **this_prologue_cache
)
1778 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1780 /* We shouldn't even bother if we don't have a sigcontext_addr
1782 if (tdep
->sigcontext_addr
== NULL
)
1785 if (tdep
->sigtramp_p
!= NULL
)
1787 if (tdep
->sigtramp_p (this_frame
))
1791 if (tdep
->sigtramp_start
!= 0)
1793 CORE_ADDR pc
= get_frame_pc (this_frame
);
1795 gdb_assert (tdep
->sigtramp_end
!= 0);
1796 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1803 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1806 i386_sigtramp_frame_this_id
,
1807 i386_sigtramp_frame_prev_register
,
1809 i386_sigtramp_frame_sniffer
1814 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1816 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1821 static const struct frame_base i386_frame_base
=
1824 i386_frame_base_address
,
1825 i386_frame_base_address
,
1826 i386_frame_base_address
1829 static struct frame_id
1830 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1834 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1836 /* See the end of i386_push_dummy_call. */
1837 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1841 /* Figure out where the longjmp will land. Slurp the args out of the
1842 stack. We expect the first arg to be a pointer to the jmp_buf
1843 structure from which we extract the address that we will land at.
1844 This address is copied into PC. This routine returns non-zero on
1848 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1851 CORE_ADDR sp
, jb_addr
;
1852 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1853 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1854 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1856 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1857 longjmp will land. */
1858 if (jb_pc_offset
== -1)
1861 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1862 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1863 if (target_read_memory (sp
+ 4, buf
, 4))
1866 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1867 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1870 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1875 /* Check whether TYPE must be 16-byte-aligned when passed as a
1876 function argument. 16-byte vectors, _Decimal128 and structures or
1877 unions containing such types must be 16-byte-aligned; other
1878 arguments are 4-byte-aligned. */
1881 i386_16_byte_align_p (struct type
*type
)
1883 type
= check_typedef (type
);
1884 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1885 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1886 && TYPE_LENGTH (type
) == 16)
1888 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1889 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1890 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1891 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1894 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1896 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1904 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1905 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1906 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1907 CORE_ADDR struct_addr
)
1909 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1915 /* Determine the total space required for arguments and struct
1916 return address in a first pass (allowing for 16-byte-aligned
1917 arguments), then push arguments in a second pass. */
1919 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1921 int args_space_used
= 0;
1922 int have_16_byte_aligned_arg
= 0;
1928 /* Push value address. */
1929 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1930 write_memory (sp
, buf
, 4);
1931 args_space_used
+= 4;
1937 for (i
= 0; i
< nargs
; i
++)
1939 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1943 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1944 args_space_used
= align_up (args_space_used
, 16);
1946 write_memory (sp
+ args_space_used
,
1947 value_contents_all (args
[i
]), len
);
1948 /* The System V ABI says that:
1950 "An argument's size is increased, if necessary, to make it a
1951 multiple of [32-bit] words. This may require tail padding,
1952 depending on the size of the argument."
1954 This makes sure the stack stays word-aligned. */
1955 args_space_used
+= align_up (len
, 4);
1959 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1961 args_space
= align_up (args_space
, 16);
1962 have_16_byte_aligned_arg
= 1;
1964 args_space
+= align_up (len
, 4);
1970 if (have_16_byte_aligned_arg
)
1971 args_space
= align_up (args_space
, 16);
1976 /* Store return address. */
1978 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1979 write_memory (sp
, buf
, 4);
1981 /* Finally, update the stack pointer... */
1982 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1983 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1985 /* ...and fake a frame pointer. */
1986 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1988 /* MarkK wrote: This "+ 8" is all over the place:
1989 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1990 i386_dummy_id). It's there, since all frame unwinders for
1991 a given target have to agree (within a certain margin) on the
1992 definition of the stack address of a frame. Otherwise frame id
1993 comparison might not work correctly. Since DWARF2/GCC uses the
1994 stack address *before* the function call as a frame's CFA. On
1995 the i386, when %ebp is used as a frame pointer, the offset
1996 between the contents %ebp and the CFA as defined by GCC. */
2000 /* These registers are used for returning integers (and on some
2001 targets also for returning `struct' and `union' values when their
2002 size and alignment match an integer type). */
2003 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2004 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2006 /* Read, for architecture GDBARCH, a function return value of TYPE
2007 from REGCACHE, and copy that into VALBUF. */
2010 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2011 struct regcache
*regcache
, gdb_byte
*valbuf
)
2013 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2014 int len
= TYPE_LENGTH (type
);
2015 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2017 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2019 if (tdep
->st0_regnum
< 0)
2021 warning (_("Cannot find floating-point return value."));
2022 memset (valbuf
, 0, len
);
2026 /* Floating-point return values can be found in %st(0). Convert
2027 its contents to the desired type. This is probably not
2028 exactly how it would happen on the target itself, but it is
2029 the best we can do. */
2030 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2031 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2035 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2036 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2038 if (len
<= low_size
)
2040 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2041 memcpy (valbuf
, buf
, len
);
2043 else if (len
<= (low_size
+ high_size
))
2045 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2046 memcpy (valbuf
, buf
, low_size
);
2047 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2048 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2051 internal_error (__FILE__
, __LINE__
,
2052 _("Cannot extract return value of %d bytes long."), len
);
2056 /* Write, for architecture GDBARCH, a function return value of TYPE
2057 from VALBUF into REGCACHE. */
2060 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2061 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2063 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2064 int len
= TYPE_LENGTH (type
);
2066 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2069 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2071 if (tdep
->st0_regnum
< 0)
2073 warning (_("Cannot set floating-point return value."));
2077 /* Returning floating-point values is a bit tricky. Apart from
2078 storing the return value in %st(0), we have to simulate the
2079 state of the FPU at function return point. */
2081 /* Convert the value found in VALBUF to the extended
2082 floating-point format used by the FPU. This is probably
2083 not exactly how it would happen on the target itself, but
2084 it is the best we can do. */
2085 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2086 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2088 /* Set the top of the floating-point register stack to 7. The
2089 actual value doesn't really matter, but 7 is what a normal
2090 function return would end up with if the program started out
2091 with a freshly initialized FPU. */
2092 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2094 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2096 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2097 the floating-point register stack to 7, the appropriate value
2098 for the tag word is 0x3fff. */
2099 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2103 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2104 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2106 if (len
<= low_size
)
2107 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2108 else if (len
<= (low_size
+ high_size
))
2110 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2111 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2112 len
- low_size
, valbuf
+ low_size
);
2115 internal_error (__FILE__
, __LINE__
,
2116 _("Cannot store return value of %d bytes long."), len
);
2121 /* This is the variable that is set with "set struct-convention", and
2122 its legitimate values. */
2123 static const char default_struct_convention
[] = "default";
2124 static const char pcc_struct_convention
[] = "pcc";
2125 static const char reg_struct_convention
[] = "reg";
2126 static const char *valid_conventions
[] =
2128 default_struct_convention
,
2129 pcc_struct_convention
,
2130 reg_struct_convention
,
2133 static const char *struct_convention
= default_struct_convention
;
2135 /* Return non-zero if TYPE, which is assumed to be a structure,
2136 a union type, or an array type, should be returned in registers
2137 for architecture GDBARCH. */
2140 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2143 enum type_code code
= TYPE_CODE (type
);
2144 int len
= TYPE_LENGTH (type
);
2146 gdb_assert (code
== TYPE_CODE_STRUCT
2147 || code
== TYPE_CODE_UNION
2148 || code
== TYPE_CODE_ARRAY
);
2150 if (struct_convention
== pcc_struct_convention
2151 || (struct_convention
== default_struct_convention
2152 && tdep
->struct_return
== pcc_struct_return
))
2155 /* Structures consisting of a single `float', `double' or 'long
2156 double' member are returned in %st(0). */
2157 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2159 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2160 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2161 return (len
== 4 || len
== 8 || len
== 12);
2164 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2167 /* Determine, for architecture GDBARCH, how a return value of TYPE
2168 should be returned. If it is supposed to be returned in registers,
2169 and READBUF is non-zero, read the appropriate value from REGCACHE,
2170 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2171 from WRITEBUF into REGCACHE. */
2173 static enum return_value_convention
2174 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2175 struct type
*type
, struct regcache
*regcache
,
2176 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2178 enum type_code code
= TYPE_CODE (type
);
2180 if (((code
== TYPE_CODE_STRUCT
2181 || code
== TYPE_CODE_UNION
2182 || code
== TYPE_CODE_ARRAY
)
2183 && !i386_reg_struct_return_p (gdbarch
, type
))
2184 /* 128-bit decimal float uses the struct return convention. */
2185 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2187 /* The System V ABI says that:
2189 "A function that returns a structure or union also sets %eax
2190 to the value of the original address of the caller's area
2191 before it returns. Thus when the caller receives control
2192 again, the address of the returned object resides in register
2193 %eax and can be used to access the object."
2195 So the ABI guarantees that we can always find the return
2196 value just after the function has returned. */
2198 /* Note that the ABI doesn't mention functions returning arrays,
2199 which is something possible in certain languages such as Ada.
2200 In this case, the value is returned as if it was wrapped in
2201 a record, so the convention applied to records also applies
2208 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2209 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2212 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2215 /* This special case is for structures consisting of a single
2216 `float', `double' or 'long double' member. These structures are
2217 returned in %st(0). For these structures, we call ourselves
2218 recursively, changing TYPE into the type of the first member of
2219 the structure. Since that should work for all structures that
2220 have only one member, we don't bother to check the member's type
2222 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2224 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2225 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2230 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2232 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2234 return RETURN_VALUE_REGISTER_CONVENTION
;
2239 i387_ext_type (struct gdbarch
*gdbarch
)
2241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2243 if (!tdep
->i387_ext_type
)
2245 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2246 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2249 return tdep
->i387_ext_type
;
2252 /* Construct vector type for pseudo YMM registers. We can't use
2253 tdesc_find_type since YMM isn't described in target description. */
2255 static struct type
*
2256 i386_ymm_type (struct gdbarch
*gdbarch
)
2258 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2260 if (!tdep
->i386_ymm_type
)
2262 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2264 /* The type we're building is this: */
2266 union __gdb_builtin_type_vec256i
2268 int128_t uint128
[2];
2269 int64_t v2_int64
[4];
2270 int32_t v4_int32
[8];
2271 int16_t v8_int16
[16];
2272 int8_t v16_int8
[32];
2273 double v2_double
[4];
2280 t
= arch_composite_type (gdbarch
,
2281 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2282 append_composite_type_field (t
, "v8_float",
2283 init_vector_type (bt
->builtin_float
, 8));
2284 append_composite_type_field (t
, "v4_double",
2285 init_vector_type (bt
->builtin_double
, 4));
2286 append_composite_type_field (t
, "v32_int8",
2287 init_vector_type (bt
->builtin_int8
, 32));
2288 append_composite_type_field (t
, "v16_int16",
2289 init_vector_type (bt
->builtin_int16
, 16));
2290 append_composite_type_field (t
, "v8_int32",
2291 init_vector_type (bt
->builtin_int32
, 8));
2292 append_composite_type_field (t
, "v4_int64",
2293 init_vector_type (bt
->builtin_int64
, 4));
2294 append_composite_type_field (t
, "v2_int128",
2295 init_vector_type (bt
->builtin_int128
, 2));
2297 TYPE_VECTOR (t
) = 1;
2298 TYPE_NAME (t
) = "builtin_type_vec128i";
2299 tdep
->i386_ymm_type
= t
;
2302 return tdep
->i386_ymm_type
;
2305 /* Construct vector type for MMX registers. */
2306 static struct type
*
2307 i386_mmx_type (struct gdbarch
*gdbarch
)
2309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2311 if (!tdep
->i386_mmx_type
)
2313 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2315 /* The type we're building is this: */
2317 union __gdb_builtin_type_vec64i
2320 int32_t v2_int32
[2];
2321 int16_t v4_int16
[4];
2328 t
= arch_composite_type (gdbarch
,
2329 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2331 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2332 append_composite_type_field (t
, "v2_int32",
2333 init_vector_type (bt
->builtin_int32
, 2));
2334 append_composite_type_field (t
, "v4_int16",
2335 init_vector_type (bt
->builtin_int16
, 4));
2336 append_composite_type_field (t
, "v8_int8",
2337 init_vector_type (bt
->builtin_int8
, 8));
2339 TYPE_VECTOR (t
) = 1;
2340 TYPE_NAME (t
) = "builtin_type_vec64i";
2341 tdep
->i386_mmx_type
= t
;
2344 return tdep
->i386_mmx_type
;
2347 /* Return the GDB type object for the "standard" data type of data in
2350 static struct type
*
2351 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2353 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2354 return i386_mmx_type (gdbarch
);
2355 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2356 return i386_ymm_type (gdbarch
);
2359 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2360 if (i386_byte_regnum_p (gdbarch
, regnum
))
2361 return bt
->builtin_int8
;
2362 else if (i386_word_regnum_p (gdbarch
, regnum
))
2363 return bt
->builtin_int16
;
2364 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2365 return bt
->builtin_int32
;
2368 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2371 /* Map a cooked register onto a raw register or memory. For the i386,
2372 the MMX registers need to be mapped onto floating point registers. */
2375 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2382 mmxreg
= regnum
- tdep
->mm0_regnum
;
2383 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2384 tos
= (fstat
>> 11) & 0x7;
2385 fpreg
= (mmxreg
+ tos
) % 8;
2387 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2391 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2392 int regnum
, gdb_byte
*buf
)
2394 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2396 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2398 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2400 /* Extract (always little endian). */
2401 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2402 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2406 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2408 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2410 regnum
-= tdep
->ymm0_regnum
;
2412 /* Extract (always little endian). Read lower 128bits. */
2413 regcache_raw_read (regcache
,
2414 I387_XMM0_REGNUM (tdep
) + regnum
,
2416 memcpy (buf
, raw_buf
, 16);
2417 /* Read upper 128bits. */
2418 regcache_raw_read (regcache
,
2419 tdep
->ymm0h_regnum
+ regnum
,
2421 memcpy (buf
+ 16, raw_buf
, 16);
2423 else if (i386_word_regnum_p (gdbarch
, regnum
))
2425 int gpnum
= regnum
- tdep
->ax_regnum
;
2427 /* Extract (always little endian). */
2428 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2429 memcpy (buf
, raw_buf
, 2);
2431 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2433 /* Check byte pseudo registers last since this function will
2434 be called from amd64_pseudo_register_read, which handles
2435 byte pseudo registers differently. */
2436 int gpnum
= regnum
- tdep
->al_regnum
;
2438 /* Extract (always little endian). We read both lower and
2440 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2442 memcpy (buf
, raw_buf
+ 1, 1);
2444 memcpy (buf
, raw_buf
, 1);
2447 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2452 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2453 int regnum
, const gdb_byte
*buf
)
2455 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2457 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2459 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2462 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2463 /* ... Modify ... (always little endian). */
2464 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2466 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2470 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2472 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2474 regnum
-= tdep
->ymm0_regnum
;
2476 /* ... Write lower 128bits. */
2477 regcache_raw_write (regcache
,
2478 I387_XMM0_REGNUM (tdep
) + regnum
,
2480 /* ... Write upper 128bits. */
2481 regcache_raw_write (regcache
,
2482 tdep
->ymm0h_regnum
+ regnum
,
2485 else if (i386_word_regnum_p (gdbarch
, regnum
))
2487 int gpnum
= regnum
- tdep
->ax_regnum
;
2490 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2491 /* ... Modify ... (always little endian). */
2492 memcpy (raw_buf
, buf
, 2);
2494 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2496 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2498 /* Check byte pseudo registers last since this function will
2499 be called from amd64_pseudo_register_read, which handles
2500 byte pseudo registers differently. */
2501 int gpnum
= regnum
- tdep
->al_regnum
;
2503 /* Read ... We read both lower and upper registers. */
2504 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2505 /* ... Modify ... (always little endian). */
2507 memcpy (raw_buf
+ 1, buf
, 1);
2509 memcpy (raw_buf
, buf
, 1);
2511 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2514 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2519 /* Return the register number of the register allocated by GCC after
2520 REGNUM, or -1 if there is no such register. */
2523 i386_next_regnum (int regnum
)
2525 /* GCC allocates the registers in the order:
2527 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2529 Since storing a variable in %esp doesn't make any sense we return
2530 -1 for %ebp and for %esp itself. */
2531 static int next_regnum
[] =
2533 I386_EDX_REGNUM
, /* Slot for %eax. */
2534 I386_EBX_REGNUM
, /* Slot for %ecx. */
2535 I386_ECX_REGNUM
, /* Slot for %edx. */
2536 I386_ESI_REGNUM
, /* Slot for %ebx. */
2537 -1, -1, /* Slots for %esp and %ebp. */
2538 I386_EDI_REGNUM
, /* Slot for %esi. */
2539 I386_EBP_REGNUM
/* Slot for %edi. */
2542 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2543 return next_regnum
[regnum
];
2548 /* Return nonzero if a value of type TYPE stored in register REGNUM
2549 needs any special handling. */
2552 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2554 int len
= TYPE_LENGTH (type
);
2556 /* Values may be spread across multiple registers. Most debugging
2557 formats aren't expressive enough to specify the locations, so
2558 some heuristics is involved. Right now we only handle types that
2559 have a length that is a multiple of the word size, since GCC
2560 doesn't seem to put any other types into registers. */
2561 if (len
> 4 && len
% 4 == 0)
2563 int last_regnum
= regnum
;
2567 last_regnum
= i386_next_regnum (last_regnum
);
2571 if (last_regnum
!= -1)
2575 return i387_convert_register_p (gdbarch
, regnum
, type
);
2578 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2579 return its contents in TO. */
2582 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2583 struct type
*type
, gdb_byte
*to
)
2585 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2586 int len
= TYPE_LENGTH (type
);
2588 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2589 available in FRAME (i.e. if it wasn't saved)? */
2591 if (i386_fp_regnum_p (gdbarch
, regnum
))
2593 i387_register_to_value (frame
, regnum
, type
, to
);
2597 /* Read a value spread across multiple registers. */
2599 gdb_assert (len
> 4 && len
% 4 == 0);
2603 gdb_assert (regnum
!= -1);
2604 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2606 get_frame_register (frame
, regnum
, to
);
2607 regnum
= i386_next_regnum (regnum
);
2613 /* Write the contents FROM of a value of type TYPE into register
2614 REGNUM in frame FRAME. */
2617 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2618 struct type
*type
, const gdb_byte
*from
)
2620 int len
= TYPE_LENGTH (type
);
2622 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2624 i387_value_to_register (frame
, regnum
, type
, from
);
2628 /* Write a value spread across multiple registers. */
2630 gdb_assert (len
> 4 && len
% 4 == 0);
2634 gdb_assert (regnum
!= -1);
2635 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2637 put_frame_register (frame
, regnum
, from
);
2638 regnum
= i386_next_regnum (regnum
);
2644 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2645 in the general-purpose register set REGSET to register cache
2646 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2649 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2650 int regnum
, const void *gregs
, size_t len
)
2652 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2653 const gdb_byte
*regs
= gregs
;
2656 gdb_assert (len
== tdep
->sizeof_gregset
);
2658 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2660 if ((regnum
== i
|| regnum
== -1)
2661 && tdep
->gregset_reg_offset
[i
] != -1)
2662 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2666 /* Collect register REGNUM from the register cache REGCACHE and store
2667 it in the buffer specified by GREGS and LEN as described by the
2668 general-purpose register set REGSET. If REGNUM is -1, do this for
2669 all registers in REGSET. */
2672 i386_collect_gregset (const struct regset
*regset
,
2673 const struct regcache
*regcache
,
2674 int regnum
, void *gregs
, size_t len
)
2676 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2677 gdb_byte
*regs
= gregs
;
2680 gdb_assert (len
== tdep
->sizeof_gregset
);
2682 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2684 if ((regnum
== i
|| regnum
== -1)
2685 && tdep
->gregset_reg_offset
[i
] != -1)
2686 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2690 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2691 in the floating-point register set REGSET to register cache
2692 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2695 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2696 int regnum
, const void *fpregs
, size_t len
)
2698 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2700 if (len
== I387_SIZEOF_FXSAVE
)
2702 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2706 gdb_assert (len
== tdep
->sizeof_fpregset
);
2707 i387_supply_fsave (regcache
, regnum
, fpregs
);
2710 /* Collect register REGNUM from the register cache REGCACHE and store
2711 it in the buffer specified by FPREGS and LEN as described by the
2712 floating-point register set REGSET. If REGNUM is -1, do this for
2713 all registers in REGSET. */
2716 i386_collect_fpregset (const struct regset
*regset
,
2717 const struct regcache
*regcache
,
2718 int regnum
, void *fpregs
, size_t len
)
2720 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2722 if (len
== I387_SIZEOF_FXSAVE
)
2724 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2728 gdb_assert (len
== tdep
->sizeof_fpregset
);
2729 i387_collect_fsave (regcache
, regnum
, fpregs
);
2732 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2735 i386_supply_xstateregset (const struct regset
*regset
,
2736 struct regcache
*regcache
, int regnum
,
2737 const void *xstateregs
, size_t len
)
2739 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2740 i387_supply_xsave (regcache
, regnum
, xstateregs
);
2743 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2746 i386_collect_xstateregset (const struct regset
*regset
,
2747 const struct regcache
*regcache
,
2748 int regnum
, void *xstateregs
, size_t len
)
2750 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2751 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2754 /* Return the appropriate register set for the core section identified
2755 by SECT_NAME and SECT_SIZE. */
2757 const struct regset
*
2758 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2759 const char *sect_name
, size_t sect_size
)
2761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2763 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2765 if (tdep
->gregset
== NULL
)
2766 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2767 i386_collect_gregset
);
2768 return tdep
->gregset
;
2771 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2772 || (strcmp (sect_name
, ".reg-xfp") == 0
2773 && sect_size
== I387_SIZEOF_FXSAVE
))
2775 if (tdep
->fpregset
== NULL
)
2776 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2777 i386_collect_fpregset
);
2778 return tdep
->fpregset
;
2781 if (strcmp (sect_name
, ".reg-xstate") == 0)
2783 if (tdep
->xstateregset
== NULL
)
2784 tdep
->xstateregset
= regset_alloc (gdbarch
,
2785 i386_supply_xstateregset
,
2786 i386_collect_xstateregset
);
2788 return tdep
->xstateregset
;
2795 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2798 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2799 CORE_ADDR pc
, char *name
)
2801 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2802 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2805 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2807 unsigned long indirect
=
2808 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2809 struct minimal_symbol
*indsym
=
2810 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2811 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2815 if (strncmp (symname
, "__imp_", 6) == 0
2816 || strncmp (symname
, "_imp_", 5) == 0)
2818 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2821 return 0; /* Not a trampoline. */
2825 /* Return whether the THIS_FRAME corresponds to a sigtramp
2829 i386_sigtramp_p (struct frame_info
*this_frame
)
2831 CORE_ADDR pc
= get_frame_pc (this_frame
);
2834 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2835 return (name
&& strcmp ("_sigtramp", name
) == 0);
2839 /* We have two flavours of disassembly. The machinery on this page
2840 deals with switching between those. */
2843 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2845 gdb_assert (disassembly_flavor
== att_flavor
2846 || disassembly_flavor
== intel_flavor
);
2848 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2849 constified, cast to prevent a compiler warning. */
2850 info
->disassembler_options
= (char *) disassembly_flavor
;
2852 return print_insn_i386 (pc
, info
);
2856 /* There are a few i386 architecture variants that differ only
2857 slightly from the generic i386 target. For now, we don't give them
2858 their own source file, but include them here. As a consequence,
2859 they'll always be included. */
2861 /* System V Release 4 (SVR4). */
2863 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2867 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2869 CORE_ADDR pc
= get_frame_pc (this_frame
);
2872 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2873 currently unknown. */
2874 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2875 return (name
&& (strcmp ("_sigreturn", name
) == 0
2876 || strcmp ("_sigacthandler", name
) == 0
2877 || strcmp ("sigvechandler", name
) == 0));
2880 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2881 address of the associated sigcontext (ucontext) structure. */
2884 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2886 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2887 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2891 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2892 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2894 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2901 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2903 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2904 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2907 /* System V Release 4 (SVR4). */
2910 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2914 /* System V Release 4 uses ELF. */
2915 i386_elf_init_abi (info
, gdbarch
);
2917 /* System V Release 4 has shared libraries. */
2918 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2920 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2921 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2922 tdep
->sc_pc_offset
= 36 + 14 * 4;
2923 tdep
->sc_sp_offset
= 36 + 17 * 4;
2925 tdep
->jb_pc_offset
= 20;
2931 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2935 /* DJGPP doesn't have any special frames for signal handlers. */
2936 tdep
->sigtramp_p
= NULL
;
2938 tdep
->jb_pc_offset
= 36;
2940 /* DJGPP does not support the SSE registers. */
2941 if (! tdesc_has_registers (info
.target_desc
))
2942 tdep
->tdesc
= tdesc_i386_mmx
;
2944 /* Native compiler is GCC, which uses the SVR4 register numbering
2945 even in COFF and STABS. See the comment in i386_gdbarch_init,
2946 before the calls to set_gdbarch_stab_reg_to_regnum and
2947 set_gdbarch_sdb_reg_to_regnum. */
2948 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2949 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2951 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
2955 /* i386 register groups. In addition to the normal groups, add "mmx"
2958 static struct reggroup
*i386_sse_reggroup
;
2959 static struct reggroup
*i386_mmx_reggroup
;
2962 i386_init_reggroups (void)
2964 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2965 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2969 i386_add_reggroups (struct gdbarch
*gdbarch
)
2971 reggroup_add (gdbarch
, i386_sse_reggroup
);
2972 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2973 reggroup_add (gdbarch
, general_reggroup
);
2974 reggroup_add (gdbarch
, float_reggroup
);
2975 reggroup_add (gdbarch
, all_reggroup
);
2976 reggroup_add (gdbarch
, save_reggroup
);
2977 reggroup_add (gdbarch
, restore_reggroup
);
2978 reggroup_add (gdbarch
, vector_reggroup
);
2979 reggroup_add (gdbarch
, system_reggroup
);
2983 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2984 struct reggroup
*group
)
2986 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2987 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
2988 ymm_regnum_p
, ymmh_regnum_p
;
2990 /* Don't include pseudo registers, except for MMX, in any register
2992 if (i386_byte_regnum_p (gdbarch
, regnum
))
2995 if (i386_word_regnum_p (gdbarch
, regnum
))
2998 if (i386_dword_regnum_p (gdbarch
, regnum
))
3001 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3002 if (group
== i386_mmx_reggroup
)
3003 return mmx_regnum_p
;
3005 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3006 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3007 if (group
== i386_sse_reggroup
)
3008 return xmm_regnum_p
|| mxcsr_regnum_p
;
3010 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3011 if (group
== vector_reggroup
)
3012 return (mmx_regnum_p
3016 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3017 == I386_XSTATE_SSE_MASK
)));
3019 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3020 || i386_fpc_regnum_p (gdbarch
, regnum
));
3021 if (group
== float_reggroup
)
3024 /* For "info reg all", don't include upper YMM registers nor XMM
3025 registers when AVX is supported. */
3026 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3027 if (group
== all_reggroup
3029 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3033 if (group
== general_reggroup
)
3034 return (!fp_regnum_p
3041 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3045 /* Get the ARGIth function argument for the current function. */
3048 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3051 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3052 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3053 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3054 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3058 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3060 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3062 /* On i386, breakpoint is exactly 1 byte long, so we just
3063 adjust the PC in the regcache. */
3065 regcache_write_pc (regcache
, current_pc
);
3069 #define PREFIX_REPZ 0x01
3070 #define PREFIX_REPNZ 0x02
3071 #define PREFIX_LOCK 0x04
3072 #define PREFIX_DATA 0x08
3073 #define PREFIX_ADDR 0x10
3085 /* i386 arith/logic operations */
3098 struct i386_record_s
3100 struct gdbarch
*gdbarch
;
3101 struct regcache
*regcache
;
3102 CORE_ADDR orig_addr
;
3108 uint8_t mod
, reg
, rm
;
3117 /* Parse "modrm" part in current memory address that irp->addr point to
3118 Return -1 if something wrong. */
3121 i386_record_modrm (struct i386_record_s
*irp
)
3123 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3125 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3128 printf_unfiltered (_("Process record: error reading memory at "
3129 "addr %s len = 1.\n"),
3130 paddress (gdbarch
, irp
->addr
));
3134 irp
->mod
= (irp
->modrm
>> 6) & 3;
3135 irp
->reg
= (irp
->modrm
>> 3) & 7;
3136 irp
->rm
= irp
->modrm
& 7;
3141 /* Get the memory address that current instruction write to and set it to
3142 the argument "addr".
3143 Return -1 if something wrong. */
3146 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3148 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3149 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3161 uint8_t base
= irp
->rm
;
3166 if (target_read_memory (irp
->addr
, &byte
, 1))
3169 printf_unfiltered (_("Process record: error reading memory "
3170 "at addr %s len = 1.\n"),
3171 paddress (gdbarch
, irp
->addr
));
3175 scale
= (byte
>> 6) & 3;
3176 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3184 if ((base
& 7) == 5)
3187 if (target_read_memory (irp
->addr
, buf
, 4))
3190 printf_unfiltered (_("Process record: error reading "
3191 "memory at addr %s len = 4.\n"),
3192 paddress (gdbarch
, irp
->addr
));
3196 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3197 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3198 *addr
+= irp
->addr
+ irp
->rip_offset
;
3202 if (target_read_memory (irp
->addr
, buf
, 1))
3205 printf_unfiltered (_("Process record: error reading memory "
3206 "at addr %s len = 1.\n"),
3207 paddress (gdbarch
, irp
->addr
));
3211 *addr
= (int8_t) buf
[0];
3214 if (target_read_memory (irp
->addr
, buf
, 4))
3217 printf_unfiltered (_("Process record: error reading memory "
3218 "at addr %s len = 4.\n"),
3219 paddress (gdbarch
, irp
->addr
));
3222 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3230 if (base
== 4 && irp
->popl_esp_hack
)
3231 *addr
+= irp
->popl_esp_hack
;
3232 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3235 if (irp
->aflag
== 2)
3240 *addr
= (uint32_t) (offset64
+ *addr
);
3242 if (havesib
&& (index
!= 4 || scale
!= 0))
3244 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3246 if (irp
->aflag
== 2)
3247 *addr
+= offset64
<< scale
;
3249 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3260 if (target_read_memory (irp
->addr
, buf
, 2))
3263 printf_unfiltered (_("Process record: error reading "
3264 "memory at addr %s len = 2.\n"),
3265 paddress (gdbarch
, irp
->addr
));
3269 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3275 if (target_read_memory (irp
->addr
, buf
, 1))
3278 printf_unfiltered (_("Process record: error reading memory "
3279 "at addr %s len = 1.\n"),
3280 paddress (gdbarch
, irp
->addr
));
3284 *addr
= (int8_t) buf
[0];
3287 if (target_read_memory (irp
->addr
, buf
, 2))
3290 printf_unfiltered (_("Process record: error reading memory "
3291 "at addr %s len = 2.\n"),
3292 paddress (gdbarch
, irp
->addr
));
3296 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3303 regcache_raw_read_unsigned (irp
->regcache
,
3304 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3306 *addr
= (uint32_t) (*addr
+ offset64
);
3307 regcache_raw_read_unsigned (irp
->regcache
,
3308 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3310 *addr
= (uint32_t) (*addr
+ offset64
);
3313 regcache_raw_read_unsigned (irp
->regcache
,
3314 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3316 *addr
= (uint32_t) (*addr
+ offset64
);
3317 regcache_raw_read_unsigned (irp
->regcache
,
3318 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3320 *addr
= (uint32_t) (*addr
+ offset64
);
3323 regcache_raw_read_unsigned (irp
->regcache
,
3324 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3326 *addr
= (uint32_t) (*addr
+ offset64
);
3327 regcache_raw_read_unsigned (irp
->regcache
,
3328 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3330 *addr
= (uint32_t) (*addr
+ offset64
);
3333 regcache_raw_read_unsigned (irp
->regcache
,
3334 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3336 *addr
= (uint32_t) (*addr
+ offset64
);
3337 regcache_raw_read_unsigned (irp
->regcache
,
3338 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3340 *addr
= (uint32_t) (*addr
+ offset64
);
3343 regcache_raw_read_unsigned (irp
->regcache
,
3344 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3346 *addr
= (uint32_t) (*addr
+ offset64
);
3349 regcache_raw_read_unsigned (irp
->regcache
,
3350 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3352 *addr
= (uint32_t) (*addr
+ offset64
);
3355 regcache_raw_read_unsigned (irp
->regcache
,
3356 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3358 *addr
= (uint32_t) (*addr
+ offset64
);
3361 regcache_raw_read_unsigned (irp
->regcache
,
3362 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3364 *addr
= (uint32_t) (*addr
+ offset64
);
3374 /* Record the value of the memory that willbe changed in current instruction
3375 to "record_arch_list".
3376 Return -1 if something wrong. */
3379 i386_record_lea_modrm (struct i386_record_s
*irp
)
3381 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3384 if (irp
->override
>= 0)
3386 warning (_("Process record ignores the memory change "
3387 "of instruction at address %s because it "
3388 "can't get the value of the segment register."),
3389 paddress (gdbarch
, irp
->orig_addr
));
3393 if (i386_record_lea_modrm_addr (irp
, &addr
))
3396 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3402 /* Record the push operation to "record_arch_list".
3403 Return -1 if something wrong. */
3406 i386_record_push (struct i386_record_s
*irp
, int size
)
3410 if (record_arch_list_add_reg (irp
->regcache
,
3411 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3413 regcache_raw_read_unsigned (irp
->regcache
,
3414 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3416 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3423 /* Defines contents to record. */
3424 #define I386_SAVE_FPU_REGS 0xfffd
3425 #define I386_SAVE_FPU_ENV 0xfffe
3426 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3428 /* Record the value of floating point registers which will be changed by the
3429 current instruction to "record_arch_list". Return -1 if something is wrong.
3432 static int i386_record_floats (struct gdbarch
*gdbarch
,
3433 struct i386_record_s
*ir
,
3436 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3439 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3440 happen. Currently we store st0-st7 registers, but we need not store all
3441 registers all the time, in future we use ftag register and record only
3442 those who are not marked as an empty. */
3444 if (I386_SAVE_FPU_REGS
== iregnum
)
3446 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3448 if (record_arch_list_add_reg (ir
->regcache
, i
))
3452 else if (I386_SAVE_FPU_ENV
== iregnum
)
3454 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3456 if (record_arch_list_add_reg (ir
->regcache
, i
))
3460 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3462 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3464 if (record_arch_list_add_reg (ir
->regcache
, i
))
3468 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3469 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3471 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3476 /* Parameter error. */
3479 if(I386_SAVE_FPU_ENV
!= iregnum
)
3481 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3483 if (record_arch_list_add_reg (ir
->regcache
, i
))
3490 /* Parse the current instruction and record the values of the registers and
3491 memory that will be changed in current instruction to "record_arch_list".
3492 Return -1 if something wrong. */
3494 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3495 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3498 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3499 CORE_ADDR input_addr
)
3501 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3507 gdb_byte buf
[MAX_REGISTER_SIZE
];
3508 struct i386_record_s ir
;
3509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3514 memset (&ir
, 0, sizeof (struct i386_record_s
));
3515 ir
.regcache
= regcache
;
3516 ir
.addr
= input_addr
;
3517 ir
.orig_addr
= input_addr
;
3521 ir
.popl_esp_hack
= 0;
3522 ir
.regmap
= tdep
->record_regmap
;
3523 ir
.gdbarch
= gdbarch
;
3525 if (record_debug
> 1)
3526 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3528 paddress (gdbarch
, ir
.addr
));
3533 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3536 printf_unfiltered (_("Process record: error reading memory at "
3537 "addr %s len = 1.\n"),
3538 paddress (gdbarch
, ir
.addr
));
3542 switch (opcode8
) /* Instruction prefixes */
3544 case REPE_PREFIX_OPCODE
:
3545 prefixes
|= PREFIX_REPZ
;
3547 case REPNE_PREFIX_OPCODE
:
3548 prefixes
|= PREFIX_REPNZ
;
3550 case LOCK_PREFIX_OPCODE
:
3551 prefixes
|= PREFIX_LOCK
;
3553 case CS_PREFIX_OPCODE
:
3554 ir
.override
= X86_RECORD_CS_REGNUM
;
3556 case SS_PREFIX_OPCODE
:
3557 ir
.override
= X86_RECORD_SS_REGNUM
;
3559 case DS_PREFIX_OPCODE
:
3560 ir
.override
= X86_RECORD_DS_REGNUM
;
3562 case ES_PREFIX_OPCODE
:
3563 ir
.override
= X86_RECORD_ES_REGNUM
;
3565 case FS_PREFIX_OPCODE
:
3566 ir
.override
= X86_RECORD_FS_REGNUM
;
3568 case GS_PREFIX_OPCODE
:
3569 ir
.override
= X86_RECORD_GS_REGNUM
;
3571 case DATA_PREFIX_OPCODE
:
3572 prefixes
|= PREFIX_DATA
;
3574 case ADDR_PREFIX_OPCODE
:
3575 prefixes
|= PREFIX_ADDR
;
3577 case 0x40: /* i386 inc %eax */
3578 case 0x41: /* i386 inc %ecx */
3579 case 0x42: /* i386 inc %edx */
3580 case 0x43: /* i386 inc %ebx */
3581 case 0x44: /* i386 inc %esp */
3582 case 0x45: /* i386 inc %ebp */
3583 case 0x46: /* i386 inc %esi */
3584 case 0x47: /* i386 inc %edi */
3585 case 0x48: /* i386 dec %eax */
3586 case 0x49: /* i386 dec %ecx */
3587 case 0x4a: /* i386 dec %edx */
3588 case 0x4b: /* i386 dec %ebx */
3589 case 0x4c: /* i386 dec %esp */
3590 case 0x4d: /* i386 dec %ebp */
3591 case 0x4e: /* i386 dec %esi */
3592 case 0x4f: /* i386 dec %edi */
3593 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3597 rex_w
= (opcode8
>> 3) & 1;
3598 rex_r
= (opcode8
& 0x4) << 1;
3599 ir
.rex_x
= (opcode8
& 0x2) << 2;
3600 ir
.rex_b
= (opcode8
& 0x1) << 3;
3602 else /* 32 bit target */
3611 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3617 if (prefixes
& PREFIX_DATA
)
3620 if (prefixes
& PREFIX_ADDR
)
3622 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3625 /* now check op code */
3626 opcode
= (uint32_t) opcode8
;
3631 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3634 printf_unfiltered (_("Process record: error reading memory at "
3635 "addr %s len = 1.\n"),
3636 paddress (gdbarch
, ir
.addr
));
3640 opcode
= (uint32_t) opcode8
| 0x0f00;
3644 case 0x00: /* arith & logic */
3692 if (((opcode
>> 3) & 7) != OP_CMPL
)
3694 if ((opcode
& 1) == 0)
3697 ir
.ot
= ir
.dflag
+ OT_WORD
;
3699 switch ((opcode
>> 1) & 3)
3701 case 0: /* OP Ev, Gv */
3702 if (i386_record_modrm (&ir
))
3706 if (i386_record_lea_modrm (&ir
))
3712 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3714 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3717 case 1: /* OP Gv, Ev */
3718 if (i386_record_modrm (&ir
))
3721 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3723 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3725 case 2: /* OP A, Iv */
3726 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3730 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3733 case 0x80: /* GRP1 */
3737 if (i386_record_modrm (&ir
))
3740 if (ir
.reg
!= OP_CMPL
)
3742 if ((opcode
& 1) == 0)
3745 ir
.ot
= ir
.dflag
+ OT_WORD
;
3752 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3753 if (i386_record_lea_modrm (&ir
))
3757 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3762 case 0x40: /* inc */
3771 case 0x48: /* dec */
3780 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3784 case 0xf6: /* GRP3 */
3786 if ((opcode
& 1) == 0)
3789 ir
.ot
= ir
.dflag
+ OT_WORD
;
3790 if (i386_record_modrm (&ir
))
3793 if (ir
.mod
!= 3 && ir
.reg
== 0)
3794 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3805 if (i386_record_lea_modrm (&ir
))
3811 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3813 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3815 if (ir
.reg
== 3) /* neg */
3816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3822 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3823 if (ir
.ot
!= OT_BYTE
)
3824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3825 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3829 opcode
= opcode
<< 8 | ir
.modrm
;
3835 case 0xfe: /* GRP4 */
3836 case 0xff: /* GRP5 */
3837 if (i386_record_modrm (&ir
))
3839 if (ir
.reg
>= 2 && opcode
== 0xfe)
3842 opcode
= opcode
<< 8 | ir
.modrm
;
3849 if ((opcode
& 1) == 0)
3852 ir
.ot
= ir
.dflag
+ OT_WORD
;
3855 if (i386_record_lea_modrm (&ir
))
3861 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3863 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3865 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3868 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3870 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3872 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3876 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3882 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3885 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3887 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3892 opcode
= opcode
<< 8 | ir
.modrm
;
3898 case 0x84: /* test */
3902 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3905 case 0x98: /* CWDE/CBW */
3906 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3909 case 0x99: /* CDQ/CWD */
3910 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3911 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3914 case 0x0faf: /* imul */
3917 ir
.ot
= ir
.dflag
+ OT_WORD
;
3918 if (i386_record_modrm (&ir
))
3921 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3922 else if (opcode
== 0x6b)
3925 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3927 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3928 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3931 case 0x0fc0: /* xadd */
3933 if ((opcode
& 1) == 0)
3936 ir
.ot
= ir
.dflag
+ OT_WORD
;
3937 if (i386_record_modrm (&ir
))
3942 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3944 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3945 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3947 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3951 if (i386_record_lea_modrm (&ir
))
3953 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3955 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3960 case 0x0fb0: /* cmpxchg */
3962 if ((opcode
& 1) == 0)
3965 ir
.ot
= ir
.dflag
+ OT_WORD
;
3966 if (i386_record_modrm (&ir
))
3971 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3972 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3974 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3978 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3979 if (i386_record_lea_modrm (&ir
))
3982 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3985 case 0x0fc7: /* cmpxchg8b */
3986 if (i386_record_modrm (&ir
))
3991 opcode
= opcode
<< 8 | ir
.modrm
;
3994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3996 if (i386_record_lea_modrm (&ir
))
3998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4001 case 0x50: /* push */
4011 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4013 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4017 case 0x06: /* push es */
4018 case 0x0e: /* push cs */
4019 case 0x16: /* push ss */
4020 case 0x1e: /* push ds */
4021 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4026 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4030 case 0x0fa0: /* push fs */
4031 case 0x0fa8: /* push gs */
4032 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4037 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4041 case 0x60: /* pusha */
4042 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4047 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4051 case 0x58: /* pop */
4059 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4060 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4063 case 0x61: /* popa */
4064 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4069 for (regnum
= X86_RECORD_REAX_REGNUM
;
4070 regnum
<= X86_RECORD_REDI_REGNUM
;
4072 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4075 case 0x8f: /* pop */
4076 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4077 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4079 ir
.ot
= ir
.dflag
+ OT_WORD
;
4080 if (i386_record_modrm (&ir
))
4083 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4086 ir
.popl_esp_hack
= 1 << ir
.ot
;
4087 if (i386_record_lea_modrm (&ir
))
4090 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4093 case 0xc8: /* enter */
4094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4095 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4097 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4101 case 0xc9: /* leave */
4102 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4103 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4106 case 0x07: /* pop es */
4107 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4112 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4113 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4117 case 0x17: /* pop ss */
4118 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4123 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4124 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4125 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4128 case 0x1f: /* pop ds */
4129 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4134 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4135 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4136 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4139 case 0x0fa1: /* pop fs */
4140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4141 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4145 case 0x0fa9: /* pop gs */
4146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4147 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4151 case 0x88: /* mov */
4155 if ((opcode
& 1) == 0)
4158 ir
.ot
= ir
.dflag
+ OT_WORD
;
4160 if (i386_record_modrm (&ir
))
4165 if (opcode
== 0xc6 || opcode
== 0xc7)
4166 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4167 if (i386_record_lea_modrm (&ir
))
4172 if (opcode
== 0xc6 || opcode
== 0xc7)
4174 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4176 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4180 case 0x8a: /* mov */
4182 if ((opcode
& 1) == 0)
4185 ir
.ot
= ir
.dflag
+ OT_WORD
;
4186 if (i386_record_modrm (&ir
))
4189 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4191 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4194 case 0x8c: /* mov seg */
4195 if (i386_record_modrm (&ir
))
4200 opcode
= opcode
<< 8 | ir
.modrm
;
4205 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4209 if (i386_record_lea_modrm (&ir
))
4214 case 0x8e: /* mov seg */
4215 if (i386_record_modrm (&ir
))
4220 regnum
= X86_RECORD_ES_REGNUM
;
4223 regnum
= X86_RECORD_SS_REGNUM
;
4226 regnum
= X86_RECORD_DS_REGNUM
;
4229 regnum
= X86_RECORD_FS_REGNUM
;
4232 regnum
= X86_RECORD_GS_REGNUM
;
4236 opcode
= opcode
<< 8 | ir
.modrm
;
4240 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4241 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4244 case 0x0fb6: /* movzbS */
4245 case 0x0fb7: /* movzwS */
4246 case 0x0fbe: /* movsbS */
4247 case 0x0fbf: /* movswS */
4248 if (i386_record_modrm (&ir
))
4250 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4253 case 0x8d: /* lea */
4254 if (i386_record_modrm (&ir
))
4259 opcode
= opcode
<< 8 | ir
.modrm
;
4264 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4266 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4269 case 0xa0: /* mov EAX */
4272 case 0xd7: /* xlat */
4273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4276 case 0xa2: /* mov EAX */
4278 if (ir
.override
>= 0)
4280 warning (_("Process record ignores the memory change "
4281 "of instruction at address %s because "
4282 "it can't get the value of the segment "
4284 paddress (gdbarch
, ir
.orig_addr
));
4288 if ((opcode
& 1) == 0)
4291 ir
.ot
= ir
.dflag
+ OT_WORD
;
4294 if (target_read_memory (ir
.addr
, buf
, 8))
4297 printf_unfiltered (_("Process record: error reading "
4298 "memory at addr 0x%s len = 8.\n"),
4299 paddress (gdbarch
, ir
.addr
));
4303 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4307 if (target_read_memory (ir
.addr
, buf
, 4))
4310 printf_unfiltered (_("Process record: error reading "
4311 "memory at addr 0x%s len = 4.\n"),
4312 paddress (gdbarch
, ir
.addr
));
4316 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4320 if (target_read_memory (ir
.addr
, buf
, 2))
4323 printf_unfiltered (_("Process record: error reading "
4324 "memory at addr 0x%s len = 2.\n"),
4325 paddress (gdbarch
, ir
.addr
));
4329 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4331 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4336 case 0xb0: /* mov R, Ib */
4344 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4345 ? ((opcode
& 0x7) | ir
.rex_b
)
4346 : ((opcode
& 0x7) & 0x3));
4349 case 0xb8: /* mov R, Iv */
4357 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4360 case 0x91: /* xchg R, EAX */
4367 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4368 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4371 case 0x86: /* xchg Ev, Gv */
4373 if ((opcode
& 1) == 0)
4376 ir
.ot
= ir
.dflag
+ OT_WORD
;
4377 if (i386_record_modrm (&ir
))
4382 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4384 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4388 if (i386_record_lea_modrm (&ir
))
4392 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4394 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4397 case 0xc4: /* les Gv */
4398 case 0xc5: /* lds Gv */
4399 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4404 case 0x0fb2: /* lss Gv */
4405 case 0x0fb4: /* lfs Gv */
4406 case 0x0fb5: /* lgs Gv */
4407 if (i386_record_modrm (&ir
))
4415 opcode
= opcode
<< 8 | ir
.modrm
;
4420 case 0xc4: /* les Gv */
4421 regnum
= X86_RECORD_ES_REGNUM
;
4423 case 0xc5: /* lds Gv */
4424 regnum
= X86_RECORD_DS_REGNUM
;
4426 case 0x0fb2: /* lss Gv */
4427 regnum
= X86_RECORD_SS_REGNUM
;
4429 case 0x0fb4: /* lfs Gv */
4430 regnum
= X86_RECORD_FS_REGNUM
;
4432 case 0x0fb5: /* lgs Gv */
4433 regnum
= X86_RECORD_GS_REGNUM
;
4436 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4437 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4438 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4441 case 0xc0: /* shifts */
4447 if ((opcode
& 1) == 0)
4450 ir
.ot
= ir
.dflag
+ OT_WORD
;
4451 if (i386_record_modrm (&ir
))
4453 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4455 if (i386_record_lea_modrm (&ir
))
4461 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4463 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4465 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4472 if (i386_record_modrm (&ir
))
4476 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4481 if (i386_record_lea_modrm (&ir
))
4486 case 0xd8: /* Floats. */
4494 if (i386_record_modrm (&ir
))
4496 ir
.reg
|= ((opcode
& 7) << 3);
4502 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4510 /* For fcom, ficom nothing to do. */
4516 /* For fcomp, ficomp pop FPU stack, store all. */
4517 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4544 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4545 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4546 of code, always affects st(0) register. */
4547 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4571 /* Handling fld, fild. */
4572 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4576 switch (ir
.reg
>> 4)
4579 if (record_arch_list_add_mem (addr64
, 4))
4583 if (record_arch_list_add_mem (addr64
, 8))
4589 if (record_arch_list_add_mem (addr64
, 2))
4595 switch (ir
.reg
>> 4)
4598 if (record_arch_list_add_mem (addr64
, 4))
4600 if (3 == (ir
.reg
& 7))
4602 /* For fstp m32fp. */
4603 if (i386_record_floats (gdbarch
, &ir
,
4604 I386_SAVE_FPU_REGS
))
4609 if (record_arch_list_add_mem (addr64
, 4))
4611 if ((3 == (ir
.reg
& 7))
4612 || (5 == (ir
.reg
& 7))
4613 || (7 == (ir
.reg
& 7)))
4615 /* For fstp insn. */
4616 if (i386_record_floats (gdbarch
, &ir
,
4617 I386_SAVE_FPU_REGS
))
4622 if (record_arch_list_add_mem (addr64
, 8))
4624 if (3 == (ir
.reg
& 7))
4626 /* For fstp m64fp. */
4627 if (i386_record_floats (gdbarch
, &ir
,
4628 I386_SAVE_FPU_REGS
))
4633 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4635 /* For fistp, fbld, fild, fbstp. */
4636 if (i386_record_floats (gdbarch
, &ir
,
4637 I386_SAVE_FPU_REGS
))
4642 if (record_arch_list_add_mem (addr64
, 2))
4651 if (i386_record_floats (gdbarch
, &ir
,
4652 I386_SAVE_FPU_ENV_REG_STACK
))
4657 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4662 if (i386_record_floats (gdbarch
, &ir
,
4663 I386_SAVE_FPU_ENV_REG_STACK
))
4669 if (record_arch_list_add_mem (addr64
, 28))
4674 if (record_arch_list_add_mem (addr64
, 14))
4680 if (record_arch_list_add_mem (addr64
, 2))
4682 /* Insn fstp, fbstp. */
4683 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4688 if (record_arch_list_add_mem (addr64
, 10))
4694 if (record_arch_list_add_mem (addr64
, 28))
4700 if (record_arch_list_add_mem (addr64
, 14))
4704 if (record_arch_list_add_mem (addr64
, 80))
4707 if (i386_record_floats (gdbarch
, &ir
,
4708 I386_SAVE_FPU_ENV_REG_STACK
))
4712 if (record_arch_list_add_mem (addr64
, 8))
4715 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4720 opcode
= opcode
<< 8 | ir
.modrm
;
4725 /* Opcode is an extension of modR/M byte. */
4731 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4735 if (0x0c == (ir
.modrm
>> 4))
4737 if ((ir
.modrm
& 0x0f) <= 7)
4739 if (i386_record_floats (gdbarch
, &ir
,
4740 I386_SAVE_FPU_REGS
))
4745 if (i386_record_floats (gdbarch
, &ir
,
4746 I387_ST0_REGNUM (tdep
)))
4748 /* If only st(0) is changing, then we have already
4750 if ((ir
.modrm
& 0x0f) - 0x08)
4752 if (i386_record_floats (gdbarch
, &ir
,
4753 I387_ST0_REGNUM (tdep
) +
4754 ((ir
.modrm
& 0x0f) - 0x08)))
4772 if (i386_record_floats (gdbarch
, &ir
,
4773 I387_ST0_REGNUM (tdep
)))
4791 if (i386_record_floats (gdbarch
, &ir
,
4792 I386_SAVE_FPU_REGS
))
4796 if (i386_record_floats (gdbarch
, &ir
,
4797 I387_ST0_REGNUM (tdep
)))
4799 if (i386_record_floats (gdbarch
, &ir
,
4800 I387_ST0_REGNUM (tdep
) + 1))
4807 if (0xe9 == ir
.modrm
)
4809 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4812 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4814 if (i386_record_floats (gdbarch
, &ir
,
4815 I387_ST0_REGNUM (tdep
)))
4817 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4819 if (i386_record_floats (gdbarch
, &ir
,
4820 I387_ST0_REGNUM (tdep
) +
4824 else if ((ir
.modrm
& 0x0f) - 0x08)
4826 if (i386_record_floats (gdbarch
, &ir
,
4827 I387_ST0_REGNUM (tdep
) +
4828 ((ir
.modrm
& 0x0f) - 0x08)))
4834 if (0xe3 == ir
.modrm
)
4836 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4839 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4841 if (i386_record_floats (gdbarch
, &ir
,
4842 I387_ST0_REGNUM (tdep
)))
4844 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4846 if (i386_record_floats (gdbarch
, &ir
,
4847 I387_ST0_REGNUM (tdep
) +
4851 else if ((ir
.modrm
& 0x0f) - 0x08)
4853 if (i386_record_floats (gdbarch
, &ir
,
4854 I387_ST0_REGNUM (tdep
) +
4855 ((ir
.modrm
& 0x0f) - 0x08)))
4861 if ((0x0c == ir
.modrm
>> 4)
4862 || (0x0d == ir
.modrm
>> 4)
4863 || (0x0f == ir
.modrm
>> 4))
4865 if ((ir
.modrm
& 0x0f) <= 7)
4867 if (i386_record_floats (gdbarch
, &ir
,
4868 I387_ST0_REGNUM (tdep
) +
4874 if (i386_record_floats (gdbarch
, &ir
,
4875 I387_ST0_REGNUM (tdep
) +
4876 ((ir
.modrm
& 0x0f) - 0x08)))
4882 if (0x0c == ir
.modrm
>> 4)
4884 if (i386_record_floats (gdbarch
, &ir
,
4885 I387_FTAG_REGNUM (tdep
)))
4888 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4890 if ((ir
.modrm
& 0x0f) <= 7)
4892 if (i386_record_floats (gdbarch
, &ir
,
4893 I387_ST0_REGNUM (tdep
) +
4899 if (i386_record_floats (gdbarch
, &ir
,
4900 I386_SAVE_FPU_REGS
))
4906 if ((0x0c == ir
.modrm
>> 4)
4907 || (0x0e == ir
.modrm
>> 4)
4908 || (0x0f == ir
.modrm
>> 4)
4909 || (0xd9 == ir
.modrm
))
4911 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4916 if (0xe0 == ir
.modrm
)
4918 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4921 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4923 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4931 case 0xa4: /* movsS */
4933 case 0xaa: /* stosS */
4935 case 0x6c: /* insS */
4937 regcache_raw_read_unsigned (ir
.regcache
,
4938 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4944 if ((opcode
& 1) == 0)
4947 ir
.ot
= ir
.dflag
+ OT_WORD
;
4948 regcache_raw_read_unsigned (ir
.regcache
,
4949 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4952 regcache_raw_read_unsigned (ir
.regcache
,
4953 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4955 regcache_raw_read_unsigned (ir
.regcache
,
4956 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4958 if (ir
.aflag
&& (es
!= ds
))
4960 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4961 warning (_("Process record ignores the memory "
4962 "change of instruction at address %s "
4963 "because it can't get the value of the "
4964 "ES segment register."),
4965 paddress (gdbarch
, ir
.orig_addr
));
4969 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4973 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4974 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4975 if (opcode
== 0xa4 || opcode
== 0xa5)
4976 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4977 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4978 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4982 case 0xa6: /* cmpsS */
4984 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4985 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4986 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4987 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4991 case 0xac: /* lodsS */
4993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4995 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4997 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5000 case 0xae: /* scasS */
5002 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5003 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5004 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5005 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5008 case 0x6e: /* outsS */
5010 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5011 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5012 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5013 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5016 case 0xe4: /* port I/O */
5020 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5021 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5031 case 0xc2: /* ret im */
5032 case 0xc3: /* ret */
5033 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5034 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5037 case 0xca: /* lret im */
5038 case 0xcb: /* lret */
5039 case 0xcf: /* iret */
5040 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5041 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5042 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5045 case 0xe8: /* call im */
5046 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5048 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5052 case 0x9a: /* lcall im */
5053 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5058 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5059 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5063 case 0xe9: /* jmp im */
5064 case 0xea: /* ljmp im */
5065 case 0xeb: /* jmp Jb */
5066 case 0x70: /* jcc Jb */
5082 case 0x0f80: /* jcc Jv */
5100 case 0x0f90: /* setcc Gv */
5116 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5118 if (i386_record_modrm (&ir
))
5121 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5125 if (i386_record_lea_modrm (&ir
))
5130 case 0x0f40: /* cmov Gv, Ev */
5146 if (i386_record_modrm (&ir
))
5149 if (ir
.dflag
== OT_BYTE
)
5151 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5155 case 0x9c: /* pushf */
5156 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5157 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5159 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5163 case 0x9d: /* popf */
5164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5165 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5168 case 0x9e: /* sahf */
5169 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5174 case 0xf5: /* cmc */
5175 case 0xf8: /* clc */
5176 case 0xf9: /* stc */
5177 case 0xfc: /* cld */
5178 case 0xfd: /* std */
5179 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5182 case 0x9f: /* lahf */
5183 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5188 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5192 /* bit operations */
5193 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5194 ir
.ot
= ir
.dflag
+ OT_WORD
;
5195 if (i386_record_modrm (&ir
))
5200 opcode
= opcode
<< 8 | ir
.modrm
;
5206 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5209 if (i386_record_lea_modrm (&ir
))
5213 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5216 case 0x0fa3: /* bt Gv, Ev */
5217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5220 case 0x0fab: /* bts */
5221 case 0x0fb3: /* btr */
5222 case 0x0fbb: /* btc */
5223 ir
.ot
= ir
.dflag
+ OT_WORD
;
5224 if (i386_record_modrm (&ir
))
5227 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5231 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5233 regcache_raw_read_unsigned (ir
.regcache
,
5234 ir
.regmap
[ir
.reg
| rex_r
],
5239 addr64
+= ((int16_t) addr
>> 4) << 4;
5242 addr64
+= ((int32_t) addr
>> 5) << 5;
5245 addr64
+= ((int64_t) addr
>> 6) << 6;
5248 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5250 if (i386_record_lea_modrm (&ir
))
5253 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5256 case 0x0fbc: /* bsf */
5257 case 0x0fbd: /* bsr */
5258 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5259 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5263 case 0x27: /* daa */
5264 case 0x2f: /* das */
5265 case 0x37: /* aaa */
5266 case 0x3f: /* aas */
5267 case 0xd4: /* aam */
5268 case 0xd5: /* aad */
5269 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5279 case 0x90: /* nop */
5280 if (prefixes
& PREFIX_LOCK
)
5287 case 0x9b: /* fwait */
5288 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5291 printf_unfiltered (_("Process record: error reading memory at "
5292 "addr 0x%s len = 1.\n"),
5293 paddress (gdbarch
, ir
.addr
));
5296 opcode
= (uint32_t) opcode8
;
5302 case 0xcc: /* int3 */
5303 printf_unfiltered (_("Process record does not support instruction "
5310 case 0xcd: /* int */
5314 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5317 printf_unfiltered (_("Process record: error reading memory "
5318 "at addr %s len = 1.\n"),
5319 paddress (gdbarch
, ir
.addr
));
5323 if (interrupt
!= 0x80
5324 || tdep
->i386_intx80_record
== NULL
)
5326 printf_unfiltered (_("Process record does not support "
5327 "instruction int 0x%02x.\n"),
5332 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5339 case 0xce: /* into */
5340 printf_unfiltered (_("Process record does not support "
5341 "instruction into.\n"));
5346 case 0xfa: /* cli */
5347 case 0xfb: /* sti */
5350 case 0x62: /* bound */
5351 printf_unfiltered (_("Process record does not support "
5352 "instruction bound.\n"));
5357 case 0x0fc8: /* bswap reg */
5365 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5368 case 0xd6: /* salc */
5369 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5374 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5375 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5378 case 0xe0: /* loopnz */
5379 case 0xe1: /* loopz */
5380 case 0xe2: /* loop */
5381 case 0xe3: /* jecxz */
5382 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5383 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5386 case 0x0f30: /* wrmsr */
5387 printf_unfiltered (_("Process record does not support "
5388 "instruction wrmsr.\n"));
5393 case 0x0f32: /* rdmsr */
5394 printf_unfiltered (_("Process record does not support "
5395 "instruction rdmsr.\n"));
5400 case 0x0f31: /* rdtsc */
5401 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5402 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5405 case 0x0f34: /* sysenter */
5408 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5413 if (tdep
->i386_sysenter_record
== NULL
)
5415 printf_unfiltered (_("Process record does not support "
5416 "instruction sysenter.\n"));
5420 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5426 case 0x0f35: /* sysexit */
5427 printf_unfiltered (_("Process record does not support "
5428 "instruction sysexit.\n"));
5433 case 0x0f05: /* syscall */
5436 if (tdep
->i386_syscall_record
== NULL
)
5438 printf_unfiltered (_("Process record does not support "
5439 "instruction syscall.\n"));
5443 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5449 case 0x0f07: /* sysret */
5450 printf_unfiltered (_("Process record does not support "
5451 "instruction sysret.\n"));
5456 case 0x0fa2: /* cpuid */
5457 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5463 case 0xf4: /* hlt */
5464 printf_unfiltered (_("Process record does not support "
5465 "instruction hlt.\n"));
5471 if (i386_record_modrm (&ir
))
5478 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5482 if (i386_record_lea_modrm (&ir
))
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5495 opcode
= opcode
<< 8 | ir
.modrm
;
5502 if (i386_record_modrm (&ir
))
5513 opcode
= opcode
<< 8 | ir
.modrm
;
5516 if (ir
.override
>= 0)
5518 warning (_("Process record ignores the memory "
5519 "change of instruction at "
5520 "address %s because it can't get "
5521 "the value of the segment "
5523 paddress (gdbarch
, ir
.orig_addr
));
5527 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5529 if (record_arch_list_add_mem (addr64
, 2))
5532 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5534 if (record_arch_list_add_mem (addr64
, 8))
5539 if (record_arch_list_add_mem (addr64
, 4))
5550 case 0: /* monitor */
5553 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5557 opcode
= opcode
<< 8 | ir
.modrm
;
5565 if (ir
.override
>= 0)
5567 warning (_("Process record ignores the memory "
5568 "change of instruction at "
5569 "address %s because it can't get "
5570 "the value of the segment "
5572 paddress (gdbarch
, ir
.orig_addr
));
5578 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5580 if (record_arch_list_add_mem (addr64
, 2))
5583 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5585 if (record_arch_list_add_mem (addr64
, 8))
5590 if (record_arch_list_add_mem (addr64
, 4))
5602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5607 else if (ir
.rm
== 1)
5614 opcode
= opcode
<< 8 | ir
.modrm
;
5621 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5627 if (i386_record_lea_modrm (&ir
))
5630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5635 case 7: /* invlpg */
5638 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5639 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5643 opcode
= opcode
<< 8 | ir
.modrm
;
5648 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5652 opcode
= opcode
<< 8 | ir
.modrm
;
5658 case 0x0f08: /* invd */
5659 case 0x0f09: /* wbinvd */
5662 case 0x63: /* arpl */
5663 if (i386_record_modrm (&ir
))
5665 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5667 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5668 ? (ir
.reg
| rex_r
) : ir
.rm
);
5672 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5673 if (i386_record_lea_modrm (&ir
))
5676 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5677 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5680 case 0x0f02: /* lar */
5681 case 0x0f03: /* lsl */
5682 if (i386_record_modrm (&ir
))
5684 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5685 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5689 if (i386_record_modrm (&ir
))
5691 if (ir
.mod
== 3 && ir
.reg
== 3)
5694 opcode
= opcode
<< 8 | ir
.modrm
;
5706 /* nop (multi byte) */
5709 case 0x0f20: /* mov reg, crN */
5710 case 0x0f22: /* mov crN, reg */
5711 if (i386_record_modrm (&ir
))
5713 if ((ir
.modrm
& 0xc0) != 0xc0)
5716 opcode
= opcode
<< 8 | ir
.modrm
;
5727 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5729 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5733 opcode
= opcode
<< 8 | ir
.modrm
;
5739 case 0x0f21: /* mov reg, drN */
5740 case 0x0f23: /* mov drN, reg */
5741 if (i386_record_modrm (&ir
))
5743 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5744 || ir
.reg
== 5 || ir
.reg
>= 8)
5747 opcode
= opcode
<< 8 | ir
.modrm
;
5751 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5753 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5756 case 0x0f06: /* clts */
5757 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5760 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5762 case 0x0f0d: /* 3DNow! prefetch */
5765 case 0x0f0e: /* 3DNow! femms */
5766 case 0x0f77: /* emms */
5767 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
5769 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
5772 case 0x0f0f: /* 3DNow! data */
5773 if (i386_record_modrm (&ir
))
5775 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5777 printf_unfiltered (_("Process record: error reading memory at "
5778 "addr %s len = 1.\n"),
5779 paddress (gdbarch
, ir
.addr
));
5785 case 0x0c: /* 3DNow! pi2fw */
5786 case 0x0d: /* 3DNow! pi2fd */
5787 case 0x1c: /* 3DNow! pf2iw */
5788 case 0x1d: /* 3DNow! pf2id */
5789 case 0x8a: /* 3DNow! pfnacc */
5790 case 0x8e: /* 3DNow! pfpnacc */
5791 case 0x90: /* 3DNow! pfcmpge */
5792 case 0x94: /* 3DNow! pfmin */
5793 case 0x96: /* 3DNow! pfrcp */
5794 case 0x97: /* 3DNow! pfrsqrt */
5795 case 0x9a: /* 3DNow! pfsub */
5796 case 0x9e: /* 3DNow! pfadd */
5797 case 0xa0: /* 3DNow! pfcmpgt */
5798 case 0xa4: /* 3DNow! pfmax */
5799 case 0xa6: /* 3DNow! pfrcpit1 */
5800 case 0xa7: /* 3DNow! pfrsqit1 */
5801 case 0xaa: /* 3DNow! pfsubr */
5802 case 0xae: /* 3DNow! pfacc */
5803 case 0xb0: /* 3DNow! pfcmpeq */
5804 case 0xb4: /* 3DNow! pfmul */
5805 case 0xb6: /* 3DNow! pfrcpit2 */
5806 case 0xb7: /* 3DNow! pmulhrw */
5807 case 0xbb: /* 3DNow! pswapd */
5808 case 0xbf: /* 3DNow! pavgusb */
5809 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
5810 goto no_support_3dnow_data
;
5811 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
5815 no_support_3dnow_data
:
5816 opcode
= (opcode
<< 8) | opcode8
;
5822 case 0x0faa: /* rsm */
5823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5825 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5828 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5831 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5835 if (i386_record_modrm (&ir
))
5839 case 0: /* fxsave */
5843 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5844 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5846 if (record_arch_list_add_mem (tmpu64
, 512))
5851 case 1: /* fxrstor */
5855 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5857 for (i
= I387_MM0_REGNUM (tdep
);
5858 i386_mmx_regnum_p (gdbarch
, i
); i
++)
5859 record_arch_list_add_reg (ir
.regcache
, i
);
5861 for (i
= I387_XMM0_REGNUM (tdep
);
5862 i386_xmm_regnum_p (gdbarch
, i
); i
++)
5863 record_arch_list_add_reg (ir
.regcache
, i
);
5865 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
5866 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
5868 for (i
= I387_ST0_REGNUM (tdep
);
5869 i386_fp_regnum_p (gdbarch
, i
); i
++)
5870 record_arch_list_add_reg (ir
.regcache
, i
);
5872 for (i
= I387_FCTRL_REGNUM (tdep
);
5873 i386_fpc_regnum_p (gdbarch
, i
); i
++)
5874 record_arch_list_add_reg (ir
.regcache
, i
);
5878 case 2: /* ldmxcsr */
5879 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
5881 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
5884 case 3: /* stmxcsr */
5886 if (i386_record_lea_modrm (&ir
))
5890 case 5: /* lfence */
5891 case 6: /* mfence */
5892 case 7: /* sfence clflush */
5896 opcode
= (opcode
<< 8) | ir
.modrm
;
5902 case 0x0fc3: /* movnti */
5903 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
5904 if (i386_record_modrm (&ir
))
5909 if (i386_record_lea_modrm (&ir
))
5913 /* Add prefix to opcode. */
6040 reswitch_prefix_add
:
6048 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6050 printf_unfiltered (_("Process record: error reading memory at "
6051 "addr %s len = 1.\n"),
6052 paddress (gdbarch
, ir
.addr
));
6056 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6057 goto reswitch_prefix_add
;
6060 case 0x0f10: /* movups */
6061 case 0x660f10: /* movupd */
6062 case 0xf30f10: /* movss */
6063 case 0xf20f10: /* movsd */
6064 case 0x0f12: /* movlps */
6065 case 0x660f12: /* movlpd */
6066 case 0xf30f12: /* movsldup */
6067 case 0xf20f12: /* movddup */
6068 case 0x0f14: /* unpcklps */
6069 case 0x660f14: /* unpcklpd */
6070 case 0x0f15: /* unpckhps */
6071 case 0x660f15: /* unpckhpd */
6072 case 0x0f16: /* movhps */
6073 case 0x660f16: /* movhpd */
6074 case 0xf30f16: /* movshdup */
6075 case 0x0f28: /* movaps */
6076 case 0x660f28: /* movapd */
6077 case 0x0f2a: /* cvtpi2ps */
6078 case 0x660f2a: /* cvtpi2pd */
6079 case 0xf30f2a: /* cvtsi2ss */
6080 case 0xf20f2a: /* cvtsi2sd */
6081 case 0x0f2c: /* cvttps2pi */
6082 case 0x660f2c: /* cvttpd2pi */
6083 case 0x0f2d: /* cvtps2pi */
6084 case 0x660f2d: /* cvtpd2pi */
6085 case 0x660f3800: /* pshufb */
6086 case 0x660f3801: /* phaddw */
6087 case 0x660f3802: /* phaddd */
6088 case 0x660f3803: /* phaddsw */
6089 case 0x660f3804: /* pmaddubsw */
6090 case 0x660f3805: /* phsubw */
6091 case 0x660f3806: /* phsubd */
6092 case 0x660f3807: /* phaddsw */
6093 case 0x660f3808: /* psignb */
6094 case 0x660f3809: /* psignw */
6095 case 0x660f380a: /* psignd */
6096 case 0x660f380b: /* pmulhrsw */
6097 case 0x660f3810: /* pblendvb */
6098 case 0x660f3814: /* blendvps */
6099 case 0x660f3815: /* blendvpd */
6100 case 0x660f381c: /* pabsb */
6101 case 0x660f381d: /* pabsw */
6102 case 0x660f381e: /* pabsd */
6103 case 0x660f3820: /* pmovsxbw */
6104 case 0x660f3821: /* pmovsxbd */
6105 case 0x660f3822: /* pmovsxbq */
6106 case 0x660f3823: /* pmovsxwd */
6107 case 0x660f3824: /* pmovsxwq */
6108 case 0x660f3825: /* pmovsxdq */
6109 case 0x660f3828: /* pmuldq */
6110 case 0x660f3829: /* pcmpeqq */
6111 case 0x660f382a: /* movntdqa */
6112 case 0x660f3a08: /* roundps */
6113 case 0x660f3a09: /* roundpd */
6114 case 0x660f3a0a: /* roundss */
6115 case 0x660f3a0b: /* roundsd */
6116 case 0x660f3a0c: /* blendps */
6117 case 0x660f3a0d: /* blendpd */
6118 case 0x660f3a0e: /* pblendw */
6119 case 0x660f3a0f: /* palignr */
6120 case 0x660f3a20: /* pinsrb */
6121 case 0x660f3a21: /* insertps */
6122 case 0x660f3a22: /* pinsrd pinsrq */
6123 case 0x660f3a40: /* dpps */
6124 case 0x660f3a41: /* dppd */
6125 case 0x660f3a42: /* mpsadbw */
6126 case 0x660f3a60: /* pcmpestrm */
6127 case 0x660f3a61: /* pcmpestri */
6128 case 0x660f3a62: /* pcmpistrm */
6129 case 0x660f3a63: /* pcmpistri */
6130 case 0x0f51: /* sqrtps */
6131 case 0x660f51: /* sqrtpd */
6132 case 0xf20f51: /* sqrtsd */
6133 case 0xf30f51: /* sqrtss */
6134 case 0x0f52: /* rsqrtps */
6135 case 0xf30f52: /* rsqrtss */
6136 case 0x0f53: /* rcpps */
6137 case 0xf30f53: /* rcpss */
6138 case 0x0f54: /* andps */
6139 case 0x660f54: /* andpd */
6140 case 0x0f55: /* andnps */
6141 case 0x660f55: /* andnpd */
6142 case 0x0f56: /* orps */
6143 case 0x660f56: /* orpd */
6144 case 0x0f57: /* xorps */
6145 case 0x660f57: /* xorpd */
6146 case 0x0f58: /* addps */
6147 case 0x660f58: /* addpd */
6148 case 0xf20f58: /* addsd */
6149 case 0xf30f58: /* addss */
6150 case 0x0f59: /* mulps */
6151 case 0x660f59: /* mulpd */
6152 case 0xf20f59: /* mulsd */
6153 case 0xf30f59: /* mulss */
6154 case 0x0f5a: /* cvtps2pd */
6155 case 0x660f5a: /* cvtpd2ps */
6156 case 0xf20f5a: /* cvtsd2ss */
6157 case 0xf30f5a: /* cvtss2sd */
6158 case 0x0f5b: /* cvtdq2ps */
6159 case 0x660f5b: /* cvtps2dq */
6160 case 0xf30f5b: /* cvttps2dq */
6161 case 0x0f5c: /* subps */
6162 case 0x660f5c: /* subpd */
6163 case 0xf20f5c: /* subsd */
6164 case 0xf30f5c: /* subss */
6165 case 0x0f5d: /* minps */
6166 case 0x660f5d: /* minpd */
6167 case 0xf20f5d: /* minsd */
6168 case 0xf30f5d: /* minss */
6169 case 0x0f5e: /* divps */
6170 case 0x660f5e: /* divpd */
6171 case 0xf20f5e: /* divsd */
6172 case 0xf30f5e: /* divss */
6173 case 0x0f5f: /* maxps */
6174 case 0x660f5f: /* maxpd */
6175 case 0xf20f5f: /* maxsd */
6176 case 0xf30f5f: /* maxss */
6177 case 0x660f60: /* punpcklbw */
6178 case 0x660f61: /* punpcklwd */
6179 case 0x660f62: /* punpckldq */
6180 case 0x660f63: /* packsswb */
6181 case 0x660f64: /* pcmpgtb */
6182 case 0x660f65: /* pcmpgtw */
6183 case 0x660f66: /* pcmpgtl */
6184 case 0x660f67: /* packuswb */
6185 case 0x660f68: /* punpckhbw */
6186 case 0x660f69: /* punpckhwd */
6187 case 0x660f6a: /* punpckhdq */
6188 case 0x660f6b: /* packssdw */
6189 case 0x660f6c: /* punpcklqdq */
6190 case 0x660f6d: /* punpckhqdq */
6191 case 0x660f6e: /* movd */
6192 case 0x660f6f: /* movdqa */
6193 case 0xf30f6f: /* movdqu */
6194 case 0x660f70: /* pshufd */
6195 case 0xf20f70: /* pshuflw */
6196 case 0xf30f70: /* pshufhw */
6197 case 0x660f74: /* pcmpeqb */
6198 case 0x660f75: /* pcmpeqw */
6199 case 0x660f76: /* pcmpeql */
6200 case 0x660f7c: /* haddpd */
6201 case 0xf20f7c: /* haddps */
6202 case 0x660f7d: /* hsubpd */
6203 case 0xf20f7d: /* hsubps */
6204 case 0xf30f7e: /* movq */
6205 case 0x0fc2: /* cmpps */
6206 case 0x660fc2: /* cmppd */
6207 case 0xf20fc2: /* cmpsd */
6208 case 0xf30fc2: /* cmpss */
6209 case 0x660fc4: /* pinsrw */
6210 case 0x0fc6: /* shufps */
6211 case 0x660fc6: /* shufpd */
6212 case 0x660fd0: /* addsubpd */
6213 case 0xf20fd0: /* addsubps */
6214 case 0x660fd1: /* psrlw */
6215 case 0x660fd2: /* psrld */
6216 case 0x660fd3: /* psrlq */
6217 case 0x660fd4: /* paddq */
6218 case 0x660fd5: /* pmullw */
6219 case 0xf30fd6: /* movq2dq */
6220 case 0x660fd8: /* psubusb */
6221 case 0x660fd9: /* psubusw */
6222 case 0x660fda: /* pminub */
6223 case 0x660fdb: /* pand */
6224 case 0x660fdc: /* paddusb */
6225 case 0x660fdd: /* paddusw */
6226 case 0x660fde: /* pmaxub */
6227 case 0x660fdf: /* pandn */
6228 case 0x660fe0: /* pavgb */
6229 case 0x660fe1: /* psraw */
6230 case 0x660fe2: /* psrad */
6231 case 0x660fe3: /* pavgw */
6232 case 0x660fe4: /* pmulhuw */
6233 case 0x660fe5: /* pmulhw */
6234 case 0x660fe6: /* cvttpd2dq */
6235 case 0xf20fe6: /* cvtpd2dq */
6236 case 0xf30fe6: /* cvtdq2pd */
6237 case 0x660fe8: /* psubsb */
6238 case 0x660fe9: /* psubsw */
6239 case 0x660fea: /* pminsw */
6240 case 0x660feb: /* por */
6241 case 0x660fec: /* paddsb */
6242 case 0x660fed: /* paddsw */
6243 case 0x660fee: /* pmaxsw */
6244 case 0x660fef: /* pxor */
6245 case 0x660ff0: /* lddqu */
6246 case 0x660ff1: /* psllw */
6247 case 0x660ff2: /* pslld */
6248 case 0x660ff3: /* psllq */
6249 case 0x660ff4: /* pmuludq */
6250 case 0x660ff5: /* pmaddwd */
6251 case 0x660ff6: /* psadbw */
6252 case 0x660ff8: /* psubb */
6253 case 0x660ff9: /* psubw */
6254 case 0x660ffa: /* psubl */
6255 case 0x660ffb: /* psubq */
6256 case 0x660ffc: /* paddb */
6257 case 0x660ffd: /* paddw */
6258 case 0x660ffe: /* paddl */
6259 if (i386_record_modrm (&ir
))
6262 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6264 record_arch_list_add_reg (ir
.regcache
,
6265 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6266 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6270 case 0x0f11: /* movups */
6271 case 0x660f11: /* movupd */
6272 case 0xf30f11: /* movss */
6273 case 0xf20f11: /* movsd */
6274 case 0x0f13: /* movlps */
6275 case 0x660f13: /* movlpd */
6276 case 0x0f17: /* movhps */
6277 case 0x660f17: /* movhpd */
6278 case 0x0f29: /* movaps */
6279 case 0x660f29: /* movapd */
6280 case 0x660f3a14: /* pextrb */
6281 case 0x660f3a15: /* pextrw */
6282 case 0x660f3a16: /* pextrd pextrq */
6283 case 0x660f3a17: /* extractps */
6284 case 0x660f7f: /* movdqa */
6285 case 0xf30f7f: /* movdqu */
6286 if (i386_record_modrm (&ir
))
6290 if (opcode
== 0x0f13 || opcode
== 0x660f13
6291 || opcode
== 0x0f17 || opcode
== 0x660f17)
6294 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6296 record_arch_list_add_reg (ir
.regcache
,
6297 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6319 if (i386_record_lea_modrm (&ir
))
6324 case 0x0f2b: /* movntps */
6325 case 0x660f2b: /* movntpd */
6326 case 0x0fe7: /* movntq */
6327 case 0x660fe7: /* movntdq */
6330 if (opcode
== 0x0fe7)
6334 if (i386_record_lea_modrm (&ir
))
6338 case 0xf30f2c: /* cvttss2si */
6339 case 0xf20f2c: /* cvttsd2si */
6340 case 0xf30f2d: /* cvtss2si */
6341 case 0xf20f2d: /* cvtsd2si */
6342 case 0xf20f38f0: /* crc32 */
6343 case 0xf20f38f1: /* crc32 */
6344 case 0x0f50: /* movmskps */
6345 case 0x660f50: /* movmskpd */
6346 case 0x0fc5: /* pextrw */
6347 case 0x660fc5: /* pextrw */
6348 case 0x0fd7: /* pmovmskb */
6349 case 0x660fd7: /* pmovmskb */
6350 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6353 case 0x0f3800: /* pshufb */
6354 case 0x0f3801: /* phaddw */
6355 case 0x0f3802: /* phaddd */
6356 case 0x0f3803: /* phaddsw */
6357 case 0x0f3804: /* pmaddubsw */
6358 case 0x0f3805: /* phsubw */
6359 case 0x0f3806: /* phsubd */
6360 case 0x0f3807: /* phaddsw */
6361 case 0x0f3808: /* psignb */
6362 case 0x0f3809: /* psignw */
6363 case 0x0f380a: /* psignd */
6364 case 0x0f380b: /* pmulhrsw */
6365 case 0x0f381c: /* pabsb */
6366 case 0x0f381d: /* pabsw */
6367 case 0x0f381e: /* pabsd */
6368 case 0x0f382b: /* packusdw */
6369 case 0x0f3830: /* pmovzxbw */
6370 case 0x0f3831: /* pmovzxbd */
6371 case 0x0f3832: /* pmovzxbq */
6372 case 0x0f3833: /* pmovzxwd */
6373 case 0x0f3834: /* pmovzxwq */
6374 case 0x0f3835: /* pmovzxdq */
6375 case 0x0f3837: /* pcmpgtq */
6376 case 0x0f3838: /* pminsb */
6377 case 0x0f3839: /* pminsd */
6378 case 0x0f383a: /* pminuw */
6379 case 0x0f383b: /* pminud */
6380 case 0x0f383c: /* pmaxsb */
6381 case 0x0f383d: /* pmaxsd */
6382 case 0x0f383e: /* pmaxuw */
6383 case 0x0f383f: /* pmaxud */
6384 case 0x0f3840: /* pmulld */
6385 case 0x0f3841: /* phminposuw */
6386 case 0x0f3a0f: /* palignr */
6387 case 0x0f60: /* punpcklbw */
6388 case 0x0f61: /* punpcklwd */
6389 case 0x0f62: /* punpckldq */
6390 case 0x0f63: /* packsswb */
6391 case 0x0f64: /* pcmpgtb */
6392 case 0x0f65: /* pcmpgtw */
6393 case 0x0f66: /* pcmpgtl */
6394 case 0x0f67: /* packuswb */
6395 case 0x0f68: /* punpckhbw */
6396 case 0x0f69: /* punpckhwd */
6397 case 0x0f6a: /* punpckhdq */
6398 case 0x0f6b: /* packssdw */
6399 case 0x0f6e: /* movd */
6400 case 0x0f6f: /* movq */
6401 case 0x0f70: /* pshufw */
6402 case 0x0f74: /* pcmpeqb */
6403 case 0x0f75: /* pcmpeqw */
6404 case 0x0f76: /* pcmpeql */
6405 case 0x0fc4: /* pinsrw */
6406 case 0x0fd1: /* psrlw */
6407 case 0x0fd2: /* psrld */
6408 case 0x0fd3: /* psrlq */
6409 case 0x0fd4: /* paddq */
6410 case 0x0fd5: /* pmullw */
6411 case 0xf20fd6: /* movdq2q */
6412 case 0x0fd8: /* psubusb */
6413 case 0x0fd9: /* psubusw */
6414 case 0x0fda: /* pminub */
6415 case 0x0fdb: /* pand */
6416 case 0x0fdc: /* paddusb */
6417 case 0x0fdd: /* paddusw */
6418 case 0x0fde: /* pmaxub */
6419 case 0x0fdf: /* pandn */
6420 case 0x0fe0: /* pavgb */
6421 case 0x0fe1: /* psraw */
6422 case 0x0fe2: /* psrad */
6423 case 0x0fe3: /* pavgw */
6424 case 0x0fe4: /* pmulhuw */
6425 case 0x0fe5: /* pmulhw */
6426 case 0x0fe8: /* psubsb */
6427 case 0x0fe9: /* psubsw */
6428 case 0x0fea: /* pminsw */
6429 case 0x0feb: /* por */
6430 case 0x0fec: /* paddsb */
6431 case 0x0fed: /* paddsw */
6432 case 0x0fee: /* pmaxsw */
6433 case 0x0fef: /* pxor */
6434 case 0x0ff1: /* psllw */
6435 case 0x0ff2: /* pslld */
6436 case 0x0ff3: /* psllq */
6437 case 0x0ff4: /* pmuludq */
6438 case 0x0ff5: /* pmaddwd */
6439 case 0x0ff6: /* psadbw */
6440 case 0x0ff8: /* psubb */
6441 case 0x0ff9: /* psubw */
6442 case 0x0ffa: /* psubl */
6443 case 0x0ffb: /* psubq */
6444 case 0x0ffc: /* paddb */
6445 case 0x0ffd: /* paddw */
6446 case 0x0ffe: /* paddl */
6447 if (i386_record_modrm (&ir
))
6449 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6451 record_arch_list_add_reg (ir
.regcache
,
6452 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6455 case 0x0f71: /* psllw */
6456 case 0x0f72: /* pslld */
6457 case 0x0f73: /* psllq */
6458 if (i386_record_modrm (&ir
))
6460 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6462 record_arch_list_add_reg (ir
.regcache
,
6463 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6466 case 0x660f71: /* psllw */
6467 case 0x660f72: /* pslld */
6468 case 0x660f73: /* psllq */
6469 if (i386_record_modrm (&ir
))
6472 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6474 record_arch_list_add_reg (ir
.regcache
,
6475 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6478 case 0x0f7e: /* movd */
6479 case 0x660f7e: /* movd */
6480 if (i386_record_modrm (&ir
))
6483 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6490 if (i386_record_lea_modrm (&ir
))
6495 case 0x0f7f: /* movq */
6496 if (i386_record_modrm (&ir
))
6500 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6502 record_arch_list_add_reg (ir
.regcache
,
6503 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6508 if (i386_record_lea_modrm (&ir
))
6513 case 0xf30fb8: /* popcnt */
6514 if (i386_record_modrm (&ir
))
6516 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6517 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6520 case 0x660fd6: /* movq */
6521 if (i386_record_modrm (&ir
))
6526 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6528 record_arch_list_add_reg (ir
.regcache
,
6529 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6534 if (i386_record_lea_modrm (&ir
))
6539 case 0x660f3817: /* ptest */
6540 case 0x0f2e: /* ucomiss */
6541 case 0x660f2e: /* ucomisd */
6542 case 0x0f2f: /* comiss */
6543 case 0x660f2f: /* comisd */
6544 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6547 case 0x0ff7: /* maskmovq */
6548 regcache_raw_read_unsigned (ir
.regcache
,
6549 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6551 if (record_arch_list_add_mem (addr
, 64))
6555 case 0x660ff7: /* maskmovdqu */
6556 regcache_raw_read_unsigned (ir
.regcache
,
6557 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6559 if (record_arch_list_add_mem (addr
, 128))
6574 /* In the future, maybe still need to deal with need_dasm. */
6575 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6576 if (record_arch_list_add_end ())
6582 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6583 "at address %s.\n"),
6584 (unsigned int) (opcode
),
6585 paddress (gdbarch
, ir
.orig_addr
));
6589 static const int i386_record_regmap
[] =
6591 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6592 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6593 0, 0, 0, 0, 0, 0, 0, 0,
6594 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6595 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6598 /* Check that the given address appears suitable for a fast
6599 tracepoint, which on x86 means that we need an instruction of at
6600 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6601 jump and not have to worry about program jumps to an address in the
6602 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6603 of instruction to replace, and 0 if not, plus an explanatory
6607 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6608 CORE_ADDR addr
, int *isize
, char **msg
)
6611 static struct ui_file
*gdb_null
= NULL
;
6613 /* This is based on the target agent using a 4-byte relative jump.
6614 Alternate future possibilities include 8-byte offset for x86-84,
6615 or 3-byte jumps if the program has trampoline space close by. */
6618 /* Dummy file descriptor for the disassembler. */
6620 gdb_null
= ui_file_new ();
6622 /* Check for fit. */
6623 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6626 /* Return a bit of target-specific detail to add to the caller's
6627 generic failure message. */
6629 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
6642 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6643 struct tdesc_arch_data
*tdesc_data
)
6645 const struct target_desc
*tdesc
= tdep
->tdesc
;
6646 const struct tdesc_feature
*feature_core
;
6647 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6648 int i
, num_regs
, valid_p
;
6650 if (! tdesc_has_registers (tdesc
))
6653 /* Get core registers. */
6654 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6655 if (feature_core
== NULL
)
6658 /* Get SSE registers. */
6659 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6661 /* Try AVX registers. */
6662 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6666 /* The XCR0 bits. */
6669 /* AVX register description requires SSE register description. */
6673 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6675 /* It may have been set by OSABI initialization function. */
6676 if (tdep
->num_ymm_regs
== 0)
6678 tdep
->ymmh_register_names
= i386_ymmh_names
;
6679 tdep
->num_ymm_regs
= 8;
6680 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
6683 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
6684 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
6685 tdep
->ymm0h_regnum
+ i
,
6686 tdep
->ymmh_register_names
[i
]);
6688 else if (feature_sse
)
6689 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
6692 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
6693 tdep
->num_xmm_regs
= 0;
6696 num_regs
= tdep
->num_core_regs
;
6697 for (i
= 0; i
< num_regs
; i
++)
6698 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
6699 tdep
->register_names
[i
]);
6703 /* Need to include %mxcsr, so add one. */
6704 num_regs
+= tdep
->num_xmm_regs
+ 1;
6705 for (; i
< num_regs
; i
++)
6706 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
6707 tdep
->register_names
[i
]);
6714 static struct gdbarch
*
6715 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6717 struct gdbarch_tdep
*tdep
;
6718 struct gdbarch
*gdbarch
;
6719 struct tdesc_arch_data
*tdesc_data
;
6720 const struct target_desc
*tdesc
;
6724 /* If there is already a candidate, use it. */
6725 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6727 return arches
->gdbarch
;
6729 /* Allocate space for the new architecture. */
6730 tdep
= XCALLOC (1, struct gdbarch_tdep
);
6731 gdbarch
= gdbarch_alloc (&info
, tdep
);
6733 /* General-purpose registers. */
6734 tdep
->gregset
= NULL
;
6735 tdep
->gregset_reg_offset
= NULL
;
6736 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
6737 tdep
->sizeof_gregset
= 0;
6739 /* Floating-point registers. */
6740 tdep
->fpregset
= NULL
;
6741 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
6743 tdep
->xstateregset
= NULL
;
6745 /* The default settings include the FPU registers, the MMX registers
6746 and the SSE registers. This can be overridden for a specific ABI
6747 by adjusting the members `st0_regnum', `mm0_regnum' and
6748 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6749 will show up in the output of "info all-registers". */
6751 tdep
->st0_regnum
= I386_ST0_REGNUM
;
6753 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6754 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
6756 tdep
->jb_pc_offset
= -1;
6757 tdep
->struct_return
= pcc_struct_return
;
6758 tdep
->sigtramp_start
= 0;
6759 tdep
->sigtramp_end
= 0;
6760 tdep
->sigtramp_p
= i386_sigtramp_p
;
6761 tdep
->sigcontext_addr
= NULL
;
6762 tdep
->sc_reg_offset
= NULL
;
6763 tdep
->sc_pc_offset
= -1;
6764 tdep
->sc_sp_offset
= -1;
6766 tdep
->xsave_xcr0_offset
= -1;
6768 tdep
->record_regmap
= i386_record_regmap
;
6770 /* The format used for `long double' on almost all i386 targets is
6771 the i387 extended floating-point format. In fact, of all targets
6772 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6773 on having a `long double' that's not `long' at all. */
6774 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
6776 /* Although the i387 extended floating-point has only 80 significant
6777 bits, a `long double' actually takes up 96, probably to enforce
6779 set_gdbarch_long_double_bit (gdbarch
, 96);
6781 /* Register numbers of various important registers. */
6782 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
6783 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
6784 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
6785 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
6787 /* NOTE: kettenis/20040418: GCC does have two possible register
6788 numbering schemes on the i386: dbx and SVR4. These schemes
6789 differ in how they number %ebp, %esp, %eflags, and the
6790 floating-point registers, and are implemented by the arrays
6791 dbx_register_map[] and svr4_dbx_register_map in
6792 gcc/config/i386.c. GCC also defines a third numbering scheme in
6793 gcc/config/i386.c, which it designates as the "default" register
6794 map used in 64bit mode. This last register numbering scheme is
6795 implemented in dbx64_register_map, and is used for AMD64; see
6798 Currently, each GCC i386 target always uses the same register
6799 numbering scheme across all its supported debugging formats
6800 i.e. SDB (COFF), stabs and DWARF 2. This is because
6801 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6802 DBX_REGISTER_NUMBER macro which is defined by each target's
6803 respective config header in a manner independent of the requested
6804 output debugging format.
6806 This does not match the arrangement below, which presumes that
6807 the SDB and stabs numbering schemes differ from the DWARF and
6808 DWARF 2 ones. The reason for this arrangement is that it is
6809 likely to get the numbering scheme for the target's
6810 default/native debug format right. For targets where GCC is the
6811 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6812 targets where the native toolchain uses a different numbering
6813 scheme for a particular debug format (stabs-in-ELF on Solaris)
6814 the defaults below will have to be overridden, like
6815 i386_elf_init_abi() does. */
6817 /* Use the dbx register numbering scheme for stabs and COFF. */
6818 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6819 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6821 /* Use the SVR4 register numbering scheme for DWARF 2. */
6822 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
6824 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6825 be in use on any of the supported i386 targets. */
6827 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
6829 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
6831 /* Call dummy code. */
6832 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
6834 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
6835 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
6836 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
6838 set_gdbarch_return_value (gdbarch
, i386_return_value
);
6840 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
6842 /* Stack grows downward. */
6843 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6845 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
6846 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
6847 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
6849 set_gdbarch_frame_args_skip (gdbarch
, 8);
6851 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
6853 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
6855 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
6857 /* Add the i386 register groups. */
6858 i386_add_reggroups (gdbarch
);
6859 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
6861 /* Helper for function argument information. */
6862 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
6864 /* Hook the function epilogue frame unwinder. This unwinder is
6865 appended to the list first, so that it supercedes the Dwarf
6866 unwinder in function epilogues (where the Dwarf unwinder
6867 currently fails). */
6868 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
6870 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
6871 to the list before the prologue-based unwinders, so that Dwarf
6872 CFI info will be used if it is available. */
6873 dwarf2_append_unwinders (gdbarch
);
6875 frame_base_set_default (gdbarch
, &i386_frame_base
);
6877 /* Pseudo registers may be changed by amd64_init_abi. */
6878 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
6879 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
6881 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
6882 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
6884 /* Override the normal target description method to make the AVX
6885 upper halves anonymous. */
6886 set_gdbarch_register_name (gdbarch
, i386_register_name
);
6888 /* Even though the default ABI only includes general-purpose registers,
6889 floating-point registers and the SSE registers, we have to leave a
6890 gap for the upper AVX registers. */
6891 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
6893 /* Get the x86 target description from INFO. */
6894 tdesc
= info
.target_desc
;
6895 if (! tdesc_has_registers (tdesc
))
6897 tdep
->tdesc
= tdesc
;
6899 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
6900 tdep
->register_names
= i386_register_names
;
6902 /* No upper YMM registers. */
6903 tdep
->ymmh_register_names
= NULL
;
6904 tdep
->ymm0h_regnum
= -1;
6906 tdep
->num_byte_regs
= 8;
6907 tdep
->num_word_regs
= 8;
6908 tdep
->num_dword_regs
= 0;
6909 tdep
->num_mmx_regs
= 8;
6910 tdep
->num_ymm_regs
= 0;
6912 tdesc_data
= tdesc_data_alloc ();
6914 /* Hook in ABI-specific overrides, if they have been registered. */
6915 info
.tdep_info
= (void *) tdesc_data
;
6916 gdbarch_init_osabi (info
, gdbarch
);
6918 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
6920 tdesc_data_cleanup (tdesc_data
);
6922 gdbarch_free (gdbarch
);
6926 /* Wire in pseudo registers. Number of pseudo registers may be
6928 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
6929 + tdep
->num_word_regs
6930 + tdep
->num_dword_regs
6931 + tdep
->num_mmx_regs
6932 + tdep
->num_ymm_regs
));
6934 /* Target description may be changed. */
6935 tdesc
= tdep
->tdesc
;
6937 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6939 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
6940 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
6942 /* Make %al the first pseudo-register. */
6943 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
6944 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
6946 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
6947 if (tdep
->num_dword_regs
)
6949 /* Support dword pseudo-registesr if it hasn't been disabled, */
6950 tdep
->eax_regnum
= ymm0_regnum
;
6951 ymm0_regnum
+= tdep
->num_dword_regs
;
6954 tdep
->eax_regnum
= -1;
6956 mm0_regnum
= ymm0_regnum
;
6957 if (tdep
->num_ymm_regs
)
6959 /* Support YMM pseudo-registesr if it is available, */
6960 tdep
->ymm0_regnum
= ymm0_regnum
;
6961 mm0_regnum
+= tdep
->num_ymm_regs
;
6964 tdep
->ymm0_regnum
= -1;
6966 if (tdep
->num_mmx_regs
!= 0)
6968 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
6969 tdep
->mm0_regnum
= mm0_regnum
;
6972 tdep
->mm0_regnum
= -1;
6974 /* Hook in the legacy prologue-based unwinders last (fallback). */
6975 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
6976 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
6978 /* If we have a register mapping, enable the generic core file
6979 support, unless it has already been enabled. */
6980 if (tdep
->gregset_reg_offset
6981 && !gdbarch_regset_from_core_section_p (gdbarch
))
6982 set_gdbarch_regset_from_core_section (gdbarch
,
6983 i386_regset_from_core_section
);
6985 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
6986 i386_skip_permanent_breakpoint
);
6988 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
6989 i386_fast_tracepoint_valid_at
);
6994 static enum gdb_osabi
6995 i386_coff_osabi_sniffer (bfd
*abfd
)
6997 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
6998 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
6999 return GDB_OSABI_GO32
;
7001 return GDB_OSABI_UNKNOWN
;
7005 /* Provide a prototype to silence -Wmissing-prototypes. */
7006 void _initialize_i386_tdep (void);
7009 _initialize_i386_tdep (void)
7011 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7013 /* Add the variable that controls the disassembly flavor. */
7014 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7015 &disassembly_flavor
, _("\
7016 Set the disassembly flavor."), _("\
7017 Show the disassembly flavor."), _("\
7018 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7020 NULL
, /* FIXME: i18n: */
7021 &setlist
, &showlist
);
7023 /* Add the variable that controls the convention for returning
7025 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7026 &struct_convention
, _("\
7027 Set the convention for returning small structs."), _("\
7028 Show the convention for returning small structs."), _("\
7029 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7032 NULL
, /* FIXME: i18n: */
7033 &setlist
, &showlist
);
7035 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7036 i386_coff_osabi_sniffer
);
7038 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7039 i386_svr4_init_abi
);
7040 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7041 i386_go32_init_abi
);
7043 /* Initialize the i386-specific register groups. */
7044 i386_init_reggroups ();
7046 /* Initialize the standard target descriptions. */
7047 initialize_tdesc_i386 ();
7048 initialize_tdesc_i386_mmx ();
7049 initialize_tdesc_i386_avx ();
7051 /* Tell remote stub that we support XML target description. */
7052 register_remote_support_xml ("i386");