1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, newrel
, byte_order
);
752 /* Write the adjusted jump into its displaced location. */
753 append_insns (to
, 5, insn
);
757 /* Adjust jumps with 32-bit relative addresses. Calls are already
761 /* Adjust conditional jumps. */
762 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
767 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
768 newrel
= (oldloc
- *to
) + rel32
;
769 store_signed_integer (insn
+ offset
, 4, newrel
, byte_order
);
771 fprintf_unfiltered (gdb_stdlog
,
772 "Adjusted insn rel32=0x%s at 0x%s to"
773 " rel32=0x%s at 0x%s\n",
774 hex_string (rel32
), paddress (gdbarch
, oldloc
),
775 hex_string (newrel
), paddress (gdbarch
, *to
));
778 /* Write the adjusted instructions into their displaced
780 append_insns (to
, insn_length
, buf
);
784 #ifdef I386_REGNO_TO_SYMMETRY
785 #error "The Sequent Symmetry is no longer supported."
788 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
789 and %esp "belong" to the calling function. Therefore these
790 registers should be saved if they're going to be modified. */
792 /* The maximum number of saved registers. This should include all
793 registers mentioned above, and %eip. */
794 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
796 struct i386_frame_cache
803 /* Saved registers. */
804 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
809 /* Stack space reserved for local variables. */
813 /* Allocate and initialize a frame cache. */
815 static struct i386_frame_cache
*
816 i386_alloc_frame_cache (void)
818 struct i386_frame_cache
*cache
;
821 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
825 cache
->sp_offset
= -4;
828 /* Saved registers. We initialize these to -1 since zero is a valid
829 offset (that's where %ebp is supposed to be stored). */
830 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
831 cache
->saved_regs
[i
] = -1;
833 cache
->saved_sp_reg
= -1;
834 cache
->pc_in_eax
= 0;
836 /* Frameless until proven otherwise. */
842 /* If the instruction at PC is a jump, return the address of its
843 target. Otherwise, return PC. */
846 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
853 target_read_memory (pc
, &op
, 1);
857 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
863 /* Relative jump: if data16 == 0, disp32, else disp16. */
866 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
868 /* Include the size of the jmp instruction (including the
874 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
876 /* Include the size of the jmp instruction. */
881 /* Relative jump, disp8 (ignore data16). */
882 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
891 /* Check whether PC points at a prologue for a function returning a
892 structure or union. If so, it updates CACHE and returns the
893 address of the first instruction after the code sequence that
894 removes the "hidden" argument from the stack or CURRENT_PC,
895 whichever is smaller. Otherwise, return PC. */
898 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
899 struct i386_frame_cache
*cache
)
901 /* Functions that return a structure or union start with:
904 xchgl %eax, (%esp) 0x87 0x04 0x24
905 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
907 (the System V compiler puts out the second `xchg' instruction,
908 and the assembler doesn't try to optimize it, so the 'sib' form
909 gets generated). This sequence is used to get the address of the
910 return buffer for a function that returns a structure. */
911 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
912 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
916 if (current_pc
<= pc
)
919 target_read_memory (pc
, &op
, 1);
921 if (op
!= 0x58) /* popl %eax */
924 target_read_memory (pc
+ 1, buf
, 4);
925 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
928 if (current_pc
== pc
)
930 cache
->sp_offset
+= 4;
934 if (current_pc
== pc
+ 1)
936 cache
->pc_in_eax
= 1;
940 if (buf
[1] == proto1
[1])
947 i386_skip_probe (CORE_ADDR pc
)
949 /* A function may start with
963 target_read_memory (pc
, &op
, 1);
965 if (op
== 0x68 || op
== 0x6a)
969 /* Skip past the `pushl' instruction; it has either a one-byte or a
970 four-byte operand, depending on the opcode. */
976 /* Read the following 8 bytes, which should be `call _probe' (6
977 bytes) followed by `addl $4,%esp' (2 bytes). */
978 read_memory (pc
+ delta
, buf
, sizeof (buf
));
979 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
980 pc
+= delta
+ sizeof (buf
);
986 /* GCC 4.1 and later, can put code in the prologue to realign the
987 stack pointer. Check whether PC points to such code, and update
988 CACHE accordingly. Return the first instruction after the code
989 sequence or CURRENT_PC, whichever is smaller. If we don't
990 recognize the code, return PC. */
993 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
994 struct i386_frame_cache
*cache
)
996 /* There are 2 code sequences to re-align stack before the frame
999 1. Use a caller-saved saved register:
1005 2. Use a callee-saved saved register:
1012 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1014 0x83 0xe4 0xf0 andl $-16, %esp
1015 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1020 int offset
, offset_and
;
1021 static int regnums
[8] = {
1022 I386_EAX_REGNUM
, /* %eax */
1023 I386_ECX_REGNUM
, /* %ecx */
1024 I386_EDX_REGNUM
, /* %edx */
1025 I386_EBX_REGNUM
, /* %ebx */
1026 I386_ESP_REGNUM
, /* %esp */
1027 I386_EBP_REGNUM
, /* %ebp */
1028 I386_ESI_REGNUM
, /* %esi */
1029 I386_EDI_REGNUM
/* %edi */
1032 if (target_read_memory (pc
, buf
, sizeof buf
))
1035 /* Check caller-saved saved register. The first instruction has
1036 to be "leal 4(%esp), %reg". */
1037 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1039 /* MOD must be binary 10 and R/M must be binary 100. */
1040 if ((buf
[1] & 0xc7) != 0x44)
1043 /* REG has register number. */
1044 reg
= (buf
[1] >> 3) & 7;
1049 /* Check callee-saved saved register. The first instruction
1050 has to be "pushl %reg". */
1051 if ((buf
[0] & 0xf8) != 0x50)
1057 /* The next instruction has to be "leal 8(%esp), %reg". */
1058 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1061 /* MOD must be binary 10 and R/M must be binary 100. */
1062 if ((buf
[2] & 0xc7) != 0x44)
1065 /* REG has register number. Registers in pushl and leal have to
1067 if (reg
!= ((buf
[2] >> 3) & 7))
1073 /* Rigister can't be %esp nor %ebp. */
1074 if (reg
== 4 || reg
== 5)
1077 /* The next instruction has to be "andl $-XXX, %esp". */
1078 if (buf
[offset
+ 1] != 0xe4
1079 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1082 offset_and
= offset
;
1083 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1085 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1086 0xfc. REG must be binary 110 and MOD must be binary 01. */
1087 if (buf
[offset
] != 0xff
1088 || buf
[offset
+ 2] != 0xfc
1089 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1092 /* R/M has register. Registers in leal and pushl have to be the
1094 if (reg
!= (buf
[offset
+ 1] & 7))
1097 if (current_pc
> pc
+ offset_and
)
1098 cache
->saved_sp_reg
= regnums
[reg
];
1100 return min (pc
+ offset
+ 3, current_pc
);
1103 /* Maximum instruction length we need to handle. */
1104 #define I386_MAX_MATCHED_INSN_LEN 6
1106 /* Instruction description. */
1110 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1111 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1114 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1115 the first instruction description that matches. Otherwise, return
1118 static struct i386_insn
*
1119 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
1121 struct i386_insn
*insn
;
1124 target_read_memory (pc
, &op
, 1);
1126 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1128 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1130 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1131 int insn_matched
= 1;
1134 gdb_assert (insn
->len
> 1);
1135 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1137 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
1138 for (i
= 1; i
< insn
->len
; i
++)
1140 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1152 /* Some special instructions that might be migrated by GCC into the
1153 part of the prologue that sets up the new stack frame. Because the
1154 stack frame hasn't been setup yet, no registers have been saved
1155 yet, and only the scratch registers %eax, %ecx and %edx can be
1158 struct i386_insn i386_frame_setup_skip_insns
[] =
1160 /* Check for `movb imm8, r' and `movl imm32, r'.
1162 ??? Should we handle 16-bit operand-sizes here? */
1164 /* `movb imm8, %al' and `movb imm8, %ah' */
1165 /* `movb imm8, %cl' and `movb imm8, %ch' */
1166 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1167 /* `movb imm8, %dl' and `movb imm8, %dh' */
1168 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1169 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1170 { 5, { 0xb8 }, { 0xfe } },
1171 /* `movl imm32, %edx' */
1172 { 5, { 0xba }, { 0xff } },
1174 /* Check for `mov imm32, r32'. Note that there is an alternative
1175 encoding for `mov m32, %eax'.
1177 ??? Should we handle SIB adressing here?
1178 ??? Should we handle 16-bit operand-sizes here? */
1180 /* `movl m32, %eax' */
1181 { 5, { 0xa1 }, { 0xff } },
1182 /* `movl m32, %eax' and `mov; m32, %ecx' */
1183 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1184 /* `movl m32, %edx' */
1185 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1187 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1188 Because of the symmetry, there are actually two ways to encode
1189 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1190 opcode bytes 0x31 and 0x33 for `xorl'. */
1192 /* `subl %eax, %eax' */
1193 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1194 /* `subl %ecx, %ecx' */
1195 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1196 /* `subl %edx, %edx' */
1197 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1198 /* `xorl %eax, %eax' */
1199 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1200 /* `xorl %ecx, %ecx' */
1201 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1202 /* `xorl %edx, %edx' */
1203 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1208 /* Check whether PC points to a no-op instruction. */
1210 i386_skip_noop (CORE_ADDR pc
)
1215 target_read_memory (pc
, &op
, 1);
1220 /* Ignore `nop' instruction. */
1224 target_read_memory (pc
, &op
, 1);
1227 /* Ignore no-op instruction `mov %edi, %edi'.
1228 Microsoft system dlls often start with
1229 a `mov %edi,%edi' instruction.
1230 The 5 bytes before the function start are
1231 filled with `nop' instructions.
1232 This pattern can be used for hot-patching:
1233 The `mov %edi, %edi' instruction can be replaced by a
1234 near jump to the location of the 5 `nop' instructions
1235 which can be replaced by a 32-bit jump to anywhere
1236 in the 32-bit address space. */
1238 else if (op
== 0x8b)
1240 target_read_memory (pc
+ 1, &op
, 1);
1244 target_read_memory (pc
, &op
, 1);
1252 /* Check whether PC points at a code that sets up a new stack frame.
1253 If so, it updates CACHE and returns the address of the first
1254 instruction after the sequence that sets up the frame or LIMIT,
1255 whichever is smaller. If we don't recognize the code, return PC. */
1258 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1259 CORE_ADDR pc
, CORE_ADDR limit
,
1260 struct i386_frame_cache
*cache
)
1262 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1263 struct i386_insn
*insn
;
1270 target_read_memory (pc
, &op
, 1);
1272 if (op
== 0x55) /* pushl %ebp */
1274 /* Take into account that we've executed the `pushl %ebp' that
1275 starts this instruction sequence. */
1276 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1277 cache
->sp_offset
+= 4;
1280 /* If that's all, return now. */
1284 /* Check for some special instructions that might be migrated by
1285 GCC into the prologue and skip them. At this point in the
1286 prologue, code should only touch the scratch registers %eax,
1287 %ecx and %edx, so while the number of posibilities is sheer,
1290 Make sure we only skip these instructions if we later see the
1291 `movl %esp, %ebp' that actually sets up the frame. */
1292 while (pc
+ skip
< limit
)
1294 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1301 /* If that's all, return now. */
1302 if (limit
<= pc
+ skip
)
1305 target_read_memory (pc
+ skip
, &op
, 1);
1307 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1311 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1316 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1324 /* OK, we actually have a frame. We just don't know how large
1325 it is yet. Set its size to zero. We'll adjust it if
1326 necessary. We also now commit to skipping the special
1327 instructions mentioned before. */
1331 /* If that's all, return now. */
1335 /* Check for stack adjustment
1339 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1340 reg, so we don't have to worry about a data16 prefix. */
1341 target_read_memory (pc
, &op
, 1);
1344 /* `subl' with 8-bit immediate. */
1345 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1346 /* Some instruction starting with 0x83 other than `subl'. */
1349 /* `subl' with signed 8-bit immediate (though it wouldn't
1350 make sense to be negative). */
1351 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1354 else if (op
== 0x81)
1356 /* Maybe it is `subl' with a 32-bit immediate. */
1357 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1358 /* Some instruction starting with 0x81 other than `subl'. */
1361 /* It is `subl' with a 32-bit immediate. */
1362 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1367 /* Some instruction other than `subl'. */
1371 else if (op
== 0xc8) /* enter */
1373 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1380 /* Check whether PC points at code that saves registers on the stack.
1381 If so, it updates CACHE and returns the address of the first
1382 instruction after the register saves or CURRENT_PC, whichever is
1383 smaller. Otherwise, return PC. */
1386 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1387 struct i386_frame_cache
*cache
)
1389 CORE_ADDR offset
= 0;
1393 if (cache
->locals
> 0)
1394 offset
-= cache
->locals
;
1395 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1397 target_read_memory (pc
, &op
, 1);
1398 if (op
< 0x50 || op
> 0x57)
1402 cache
->saved_regs
[op
- 0x50] = offset
;
1403 cache
->sp_offset
+= 4;
1410 /* Do a full analysis of the prologue at PC and update CACHE
1411 accordingly. Bail out early if CURRENT_PC is reached. Return the
1412 address where the analysis stopped.
1414 We handle these cases:
1416 The startup sequence can be at the start of the function, or the
1417 function can start with a branch to startup code at the end.
1419 %ebp can be set up with either the 'enter' instruction, or "pushl
1420 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1421 once used in the System V compiler).
1423 Local space is allocated just below the saved %ebp by either the
1424 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1425 16-bit unsigned argument for space to allocate, and the 'addl'
1426 instruction could have either a signed byte, or 32-bit immediate.
1428 Next, the registers used by this function are pushed. With the
1429 System V compiler they will always be in the order: %edi, %esi,
1430 %ebx (and sometimes a harmless bug causes it to also save but not
1431 restore %eax); however, the code below is willing to see the pushes
1432 in any order, and will handle up to 8 of them.
1434 If the setup sequence is at the end of the function, then the next
1435 instruction will be a branch back to the start. */
1438 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1439 CORE_ADDR pc
, CORE_ADDR current_pc
,
1440 struct i386_frame_cache
*cache
)
1442 pc
= i386_skip_noop (pc
);
1443 pc
= i386_follow_jump (gdbarch
, pc
);
1444 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1445 pc
= i386_skip_probe (pc
);
1446 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1447 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1448 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1451 /* Return PC of first real instruction. */
1454 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1456 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1458 static gdb_byte pic_pat
[6] =
1460 0xe8, 0, 0, 0, 0, /* call 0x0 */
1461 0x5b, /* popl %ebx */
1463 struct i386_frame_cache cache
;
1469 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1470 if (cache
.locals
< 0)
1473 /* Found valid frame setup. */
1475 /* The native cc on SVR4 in -K PIC mode inserts the following code
1476 to get the address of the global offset table (GOT) into register
1481 movl %ebx,x(%ebp) (optional)
1484 This code is with the rest of the prologue (at the end of the
1485 function), so we have to skip it to get to the first real
1486 instruction at the start of the function. */
1488 for (i
= 0; i
< 6; i
++)
1490 target_read_memory (pc
+ i
, &op
, 1);
1491 if (pic_pat
[i
] != op
)
1498 target_read_memory (pc
+ delta
, &op
, 1);
1500 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1502 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1504 if (op
== 0x5d) /* One byte offset from %ebp. */
1506 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1508 else /* Unexpected instruction. */
1511 target_read_memory (pc
+ delta
, &op
, 1);
1515 if (delta
> 0 && op
== 0x81
1516 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1523 /* If the function starts with a branch (to startup code at the end)
1524 the last instruction should bring us back to the first
1525 instruction of the real code. */
1526 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1527 pc
= i386_follow_jump (gdbarch
, pc
);
1532 /* Check that the code pointed to by PC corresponds to a call to
1533 __main, skip it if so. Return PC otherwise. */
1536 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1538 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1541 target_read_memory (pc
, &op
, 1);
1546 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1548 /* Make sure address is computed correctly as a 32bit
1549 integer even if CORE_ADDR is 64 bit wide. */
1550 struct minimal_symbol
*s
;
1551 CORE_ADDR call_dest
;
1553 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1554 call_dest
= call_dest
& 0xffffffffU
;
1555 s
= lookup_minimal_symbol_by_pc (call_dest
);
1557 && SYMBOL_LINKAGE_NAME (s
) != NULL
1558 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1566 /* This function is 64-bit safe. */
1569 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1573 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1574 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1578 /* Normal frames. */
1580 static struct i386_frame_cache
*
1581 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1583 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1584 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1585 struct i386_frame_cache
*cache
;
1592 cache
= i386_alloc_frame_cache ();
1593 *this_cache
= cache
;
1595 /* In principle, for normal frames, %ebp holds the frame pointer,
1596 which holds the base address for the current stack frame.
1597 However, for functions that don't need it, the frame pointer is
1598 optional. For these "frameless" functions the frame pointer is
1599 actually the frame pointer of the calling frame. Signal
1600 trampolines are just a special case of a "frameless" function.
1601 They (usually) share their frame pointer with the frame that was
1602 in progress when the signal occurred. */
1604 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1605 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1606 if (cache
->base
== 0)
1609 /* For normal frames, %eip is stored at 4(%ebp). */
1610 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1612 cache
->pc
= get_frame_func (this_frame
);
1614 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1617 if (cache
->saved_sp_reg
!= -1)
1619 /* Saved stack pointer has been saved. */
1620 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1621 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1624 if (cache
->locals
< 0)
1626 /* We didn't find a valid frame, which means that CACHE->base
1627 currently holds the frame pointer for our calling frame. If
1628 we're at the start of a function, or somewhere half-way its
1629 prologue, the function's frame probably hasn't been fully
1630 setup yet. Try to reconstruct the base address for the stack
1631 frame by looking at the stack pointer. For truly "frameless"
1632 functions this might work too. */
1634 if (cache
->saved_sp_reg
!= -1)
1636 /* We're halfway aligning the stack. */
1637 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1638 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1640 /* This will be added back below. */
1641 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1643 else if (cache
->pc
!= 0
1644 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1646 /* We're in a known function, but did not find a frame
1647 setup. Assume that the function does not use %ebp.
1648 Alternatively, we may have jumped to an invalid
1649 address; in that case there is definitely no new
1651 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1652 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1656 /* We're in an unknown function. We could not find the start
1657 of the function to analyze the prologue; our best option is
1658 to assume a typical frame layout with the caller's %ebp
1660 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1663 /* Now that we have the base address for the stack frame we can
1664 calculate the value of %esp in the calling frame. */
1665 if (cache
->saved_sp
== 0)
1666 cache
->saved_sp
= cache
->base
+ 8;
1668 /* Adjust all the saved registers such that they contain addresses
1669 instead of offsets. */
1670 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1671 if (cache
->saved_regs
[i
] != -1)
1672 cache
->saved_regs
[i
] += cache
->base
;
1678 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1679 struct frame_id
*this_id
)
1681 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1683 /* This marks the outermost frame. */
1684 if (cache
->base
== 0)
1687 /* See the end of i386_push_dummy_call. */
1688 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1691 static struct value
*
1692 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1695 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1697 gdb_assert (regnum
>= 0);
1699 /* The System V ABI says that:
1701 "The flags register contains the system flags, such as the
1702 direction flag and the carry flag. The direction flag must be
1703 set to the forward (that is, zero) direction before entry and
1704 upon exit from a function. Other user flags have no specified
1705 role in the standard calling sequence and are not preserved."
1707 To guarantee the "upon exit" part of that statement we fake a
1708 saved flags register that has its direction flag cleared.
1710 Note that GCC doesn't seem to rely on the fact that the direction
1711 flag is cleared after a function return; it always explicitly
1712 clears the flag before operations where it matters.
1714 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1715 right thing to do. The way we fake the flags register here makes
1716 it impossible to change it. */
1718 if (regnum
== I386_EFLAGS_REGNUM
)
1722 val
= get_frame_register_unsigned (this_frame
, regnum
);
1724 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1727 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1728 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1730 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1731 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1733 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1734 return frame_unwind_got_memory (this_frame
, regnum
,
1735 cache
->saved_regs
[regnum
]);
1737 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1740 static const struct frame_unwind i386_frame_unwind
=
1744 i386_frame_prev_register
,
1746 default_frame_sniffer
1749 /* Normal frames, but in a function epilogue. */
1751 /* The epilogue is defined here as the 'ret' instruction, which will
1752 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1753 the function's stack frame. */
1756 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1760 if (target_read_memory (pc
, &insn
, 1))
1761 return 0; /* Can't read memory at pc. */
1763 if (insn
!= 0xc3) /* 'ret' instruction. */
1770 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1771 struct frame_info
*this_frame
,
1772 void **this_prologue_cache
)
1774 if (frame_relative_level (this_frame
) == 0)
1775 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1776 get_frame_pc (this_frame
));
1781 static struct i386_frame_cache
*
1782 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1784 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1785 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1786 struct i386_frame_cache
*cache
;
1792 cache
= i386_alloc_frame_cache ();
1793 *this_cache
= cache
;
1795 /* Cache base will be %esp plus cache->sp_offset (-4). */
1796 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1797 cache
->base
= extract_unsigned_integer (buf
, 4,
1798 byte_order
) + cache
->sp_offset
;
1800 /* Cache pc will be the frame func. */
1801 cache
->pc
= get_frame_pc (this_frame
);
1803 /* The saved %esp will be at cache->base plus 8. */
1804 cache
->saved_sp
= cache
->base
+ 8;
1806 /* The saved %eip will be at cache->base plus 4. */
1807 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1813 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1815 struct frame_id
*this_id
)
1817 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1820 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1823 static const struct frame_unwind i386_epilogue_frame_unwind
=
1826 i386_epilogue_frame_this_id
,
1827 i386_frame_prev_register
,
1829 i386_epilogue_frame_sniffer
1833 /* Signal trampolines. */
1835 static struct i386_frame_cache
*
1836 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1838 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1839 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1840 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1841 struct i386_frame_cache
*cache
;
1848 cache
= i386_alloc_frame_cache ();
1850 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1851 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1853 addr
= tdep
->sigcontext_addr (this_frame
);
1854 if (tdep
->sc_reg_offset
)
1858 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1860 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1861 if (tdep
->sc_reg_offset
[i
] != -1)
1862 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1866 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1867 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1870 *this_cache
= cache
;
1875 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1876 struct frame_id
*this_id
)
1878 struct i386_frame_cache
*cache
=
1879 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1881 /* See the end of i386_push_dummy_call. */
1882 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1885 static struct value
*
1886 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1887 void **this_cache
, int regnum
)
1889 /* Make sure we've initialized the cache. */
1890 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1892 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1896 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1897 struct frame_info
*this_frame
,
1898 void **this_prologue_cache
)
1900 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1902 /* We shouldn't even bother if we don't have a sigcontext_addr
1904 if (tdep
->sigcontext_addr
== NULL
)
1907 if (tdep
->sigtramp_p
!= NULL
)
1909 if (tdep
->sigtramp_p (this_frame
))
1913 if (tdep
->sigtramp_start
!= 0)
1915 CORE_ADDR pc
= get_frame_pc (this_frame
);
1917 gdb_assert (tdep
->sigtramp_end
!= 0);
1918 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1925 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1928 i386_sigtramp_frame_this_id
,
1929 i386_sigtramp_frame_prev_register
,
1931 i386_sigtramp_frame_sniffer
1936 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1938 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1943 static const struct frame_base i386_frame_base
=
1946 i386_frame_base_address
,
1947 i386_frame_base_address
,
1948 i386_frame_base_address
1951 static struct frame_id
1952 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1956 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1958 /* See the end of i386_push_dummy_call. */
1959 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1963 /* Figure out where the longjmp will land. Slurp the args out of the
1964 stack. We expect the first arg to be a pointer to the jmp_buf
1965 structure from which we extract the address that we will land at.
1966 This address is copied into PC. This routine returns non-zero on
1970 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1973 CORE_ADDR sp
, jb_addr
;
1974 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1975 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1976 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1978 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1979 longjmp will land. */
1980 if (jb_pc_offset
== -1)
1983 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1984 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1985 if (target_read_memory (sp
+ 4, buf
, 4))
1988 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1989 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1992 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1997 /* Check whether TYPE must be 16-byte-aligned when passed as a
1998 function argument. 16-byte vectors, _Decimal128 and structures or
1999 unions containing such types must be 16-byte-aligned; other
2000 arguments are 4-byte-aligned. */
2003 i386_16_byte_align_p (struct type
*type
)
2005 type
= check_typedef (type
);
2006 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2007 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2008 && TYPE_LENGTH (type
) == 16)
2010 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2011 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2012 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2013 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2016 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2018 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2026 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2027 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2028 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2029 CORE_ADDR struct_addr
)
2031 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2037 /* Determine the total space required for arguments and struct
2038 return address in a first pass (allowing for 16-byte-aligned
2039 arguments), then push arguments in a second pass. */
2041 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2043 int args_space_used
= 0;
2044 int have_16_byte_aligned_arg
= 0;
2050 /* Push value address. */
2051 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2052 write_memory (sp
, buf
, 4);
2053 args_space_used
+= 4;
2059 for (i
= 0; i
< nargs
; i
++)
2061 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2065 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2066 args_space_used
= align_up (args_space_used
, 16);
2068 write_memory (sp
+ args_space_used
,
2069 value_contents_all (args
[i
]), len
);
2070 /* The System V ABI says that:
2072 "An argument's size is increased, if necessary, to make it a
2073 multiple of [32-bit] words. This may require tail padding,
2074 depending on the size of the argument."
2076 This makes sure the stack stays word-aligned. */
2077 args_space_used
+= align_up (len
, 4);
2081 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2083 args_space
= align_up (args_space
, 16);
2084 have_16_byte_aligned_arg
= 1;
2086 args_space
+= align_up (len
, 4);
2092 if (have_16_byte_aligned_arg
)
2093 args_space
= align_up (args_space
, 16);
2098 /* Store return address. */
2100 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2101 write_memory (sp
, buf
, 4);
2103 /* Finally, update the stack pointer... */
2104 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2105 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2107 /* ...and fake a frame pointer. */
2108 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2110 /* MarkK wrote: This "+ 8" is all over the place:
2111 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2112 i386_dummy_id). It's there, since all frame unwinders for
2113 a given target have to agree (within a certain margin) on the
2114 definition of the stack address of a frame. Otherwise frame id
2115 comparison might not work correctly. Since DWARF2/GCC uses the
2116 stack address *before* the function call as a frame's CFA. On
2117 the i386, when %ebp is used as a frame pointer, the offset
2118 between the contents %ebp and the CFA as defined by GCC. */
2122 /* These registers are used for returning integers (and on some
2123 targets also for returning `struct' and `union' values when their
2124 size and alignment match an integer type). */
2125 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2126 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2128 /* Read, for architecture GDBARCH, a function return value of TYPE
2129 from REGCACHE, and copy that into VALBUF. */
2132 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2133 struct regcache
*regcache
, gdb_byte
*valbuf
)
2135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2136 int len
= TYPE_LENGTH (type
);
2137 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2139 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2141 if (tdep
->st0_regnum
< 0)
2143 warning (_("Cannot find floating-point return value."));
2144 memset (valbuf
, 0, len
);
2148 /* Floating-point return values can be found in %st(0). Convert
2149 its contents to the desired type. This is probably not
2150 exactly how it would happen on the target itself, but it is
2151 the best we can do. */
2152 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2153 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2157 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2158 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2160 if (len
<= low_size
)
2162 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2163 memcpy (valbuf
, buf
, len
);
2165 else if (len
<= (low_size
+ high_size
))
2167 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2168 memcpy (valbuf
, buf
, low_size
);
2169 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2170 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2173 internal_error (__FILE__
, __LINE__
,
2174 _("Cannot extract return value of %d bytes long."),
2179 /* Write, for architecture GDBARCH, a function return value of TYPE
2180 from VALBUF into REGCACHE. */
2183 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2184 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2187 int len
= TYPE_LENGTH (type
);
2189 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2192 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2194 if (tdep
->st0_regnum
< 0)
2196 warning (_("Cannot set floating-point return value."));
2200 /* Returning floating-point values is a bit tricky. Apart from
2201 storing the return value in %st(0), we have to simulate the
2202 state of the FPU at function return point. */
2204 /* Convert the value found in VALBUF to the extended
2205 floating-point format used by the FPU. This is probably
2206 not exactly how it would happen on the target itself, but
2207 it is the best we can do. */
2208 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2209 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2211 /* Set the top of the floating-point register stack to 7. The
2212 actual value doesn't really matter, but 7 is what a normal
2213 function return would end up with if the program started out
2214 with a freshly initialized FPU. */
2215 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2217 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2219 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2220 the floating-point register stack to 7, the appropriate value
2221 for the tag word is 0x3fff. */
2222 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2226 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2227 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2229 if (len
<= low_size
)
2230 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2231 else if (len
<= (low_size
+ high_size
))
2233 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2234 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2235 len
- low_size
, valbuf
+ low_size
);
2238 internal_error (__FILE__
, __LINE__
,
2239 _("Cannot store return value of %d bytes long."), len
);
2244 /* This is the variable that is set with "set struct-convention", and
2245 its legitimate values. */
2246 static const char default_struct_convention
[] = "default";
2247 static const char pcc_struct_convention
[] = "pcc";
2248 static const char reg_struct_convention
[] = "reg";
2249 static const char *valid_conventions
[] =
2251 default_struct_convention
,
2252 pcc_struct_convention
,
2253 reg_struct_convention
,
2256 static const char *struct_convention
= default_struct_convention
;
2258 /* Return non-zero if TYPE, which is assumed to be a structure,
2259 a union type, or an array type, should be returned in registers
2260 for architecture GDBARCH. */
2263 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2265 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2266 enum type_code code
= TYPE_CODE (type
);
2267 int len
= TYPE_LENGTH (type
);
2269 gdb_assert (code
== TYPE_CODE_STRUCT
2270 || code
== TYPE_CODE_UNION
2271 || code
== TYPE_CODE_ARRAY
);
2273 if (struct_convention
== pcc_struct_convention
2274 || (struct_convention
== default_struct_convention
2275 && tdep
->struct_return
== pcc_struct_return
))
2278 /* Structures consisting of a single `float', `double' or 'long
2279 double' member are returned in %st(0). */
2280 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2282 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2283 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2284 return (len
== 4 || len
== 8 || len
== 12);
2287 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2290 /* Determine, for architecture GDBARCH, how a return value of TYPE
2291 should be returned. If it is supposed to be returned in registers,
2292 and READBUF is non-zero, read the appropriate value from REGCACHE,
2293 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2294 from WRITEBUF into REGCACHE. */
2296 static enum return_value_convention
2297 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2298 struct type
*type
, struct regcache
*regcache
,
2299 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2301 enum type_code code
= TYPE_CODE (type
);
2303 if (((code
== TYPE_CODE_STRUCT
2304 || code
== TYPE_CODE_UNION
2305 || code
== TYPE_CODE_ARRAY
)
2306 && !i386_reg_struct_return_p (gdbarch
, type
))
2307 /* 128-bit decimal float uses the struct return convention. */
2308 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2310 /* The System V ABI says that:
2312 "A function that returns a structure or union also sets %eax
2313 to the value of the original address of the caller's area
2314 before it returns. Thus when the caller receives control
2315 again, the address of the returned object resides in register
2316 %eax and can be used to access the object."
2318 So the ABI guarantees that we can always find the return
2319 value just after the function has returned. */
2321 /* Note that the ABI doesn't mention functions returning arrays,
2322 which is something possible in certain languages such as Ada.
2323 In this case, the value is returned as if it was wrapped in
2324 a record, so the convention applied to records also applies
2331 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2332 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2335 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2338 /* This special case is for structures consisting of a single
2339 `float', `double' or 'long double' member. These structures are
2340 returned in %st(0). For these structures, we call ourselves
2341 recursively, changing TYPE into the type of the first member of
2342 the structure. Since that should work for all structures that
2343 have only one member, we don't bother to check the member's type
2345 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2347 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2348 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2353 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2355 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2357 return RETURN_VALUE_REGISTER_CONVENTION
;
2362 i387_ext_type (struct gdbarch
*gdbarch
)
2364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2366 if (!tdep
->i387_ext_type
)
2368 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2369 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2372 return tdep
->i387_ext_type
;
2375 /* Construct vector type for pseudo YMM registers. We can't use
2376 tdesc_find_type since YMM isn't described in target description. */
2378 static struct type
*
2379 i386_ymm_type (struct gdbarch
*gdbarch
)
2381 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2383 if (!tdep
->i386_ymm_type
)
2385 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2387 /* The type we're building is this: */
2389 union __gdb_builtin_type_vec256i
2391 int128_t uint128
[2];
2392 int64_t v2_int64
[4];
2393 int32_t v4_int32
[8];
2394 int16_t v8_int16
[16];
2395 int8_t v16_int8
[32];
2396 double v2_double
[4];
2403 t
= arch_composite_type (gdbarch
,
2404 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2405 append_composite_type_field (t
, "v8_float",
2406 init_vector_type (bt
->builtin_float
, 8));
2407 append_composite_type_field (t
, "v4_double",
2408 init_vector_type (bt
->builtin_double
, 4));
2409 append_composite_type_field (t
, "v32_int8",
2410 init_vector_type (bt
->builtin_int8
, 32));
2411 append_composite_type_field (t
, "v16_int16",
2412 init_vector_type (bt
->builtin_int16
, 16));
2413 append_composite_type_field (t
, "v8_int32",
2414 init_vector_type (bt
->builtin_int32
, 8));
2415 append_composite_type_field (t
, "v4_int64",
2416 init_vector_type (bt
->builtin_int64
, 4));
2417 append_composite_type_field (t
, "v2_int128",
2418 init_vector_type (bt
->builtin_int128
, 2));
2420 TYPE_VECTOR (t
) = 1;
2421 TYPE_NAME (t
) = "builtin_type_vec256i";
2422 tdep
->i386_ymm_type
= t
;
2425 return tdep
->i386_ymm_type
;
2428 /* Construct vector type for MMX registers. */
2429 static struct type
*
2430 i386_mmx_type (struct gdbarch
*gdbarch
)
2432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2434 if (!tdep
->i386_mmx_type
)
2436 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2438 /* The type we're building is this: */
2440 union __gdb_builtin_type_vec64i
2443 int32_t v2_int32
[2];
2444 int16_t v4_int16
[4];
2451 t
= arch_composite_type (gdbarch
,
2452 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2454 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2455 append_composite_type_field (t
, "v2_int32",
2456 init_vector_type (bt
->builtin_int32
, 2));
2457 append_composite_type_field (t
, "v4_int16",
2458 init_vector_type (bt
->builtin_int16
, 4));
2459 append_composite_type_field (t
, "v8_int8",
2460 init_vector_type (bt
->builtin_int8
, 8));
2462 TYPE_VECTOR (t
) = 1;
2463 TYPE_NAME (t
) = "builtin_type_vec64i";
2464 tdep
->i386_mmx_type
= t
;
2467 return tdep
->i386_mmx_type
;
2470 /* Return the GDB type object for the "standard" data type of data in
2473 static struct type
*
2474 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2476 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2477 return i386_mmx_type (gdbarch
);
2478 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2479 return i386_ymm_type (gdbarch
);
2482 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2483 if (i386_byte_regnum_p (gdbarch
, regnum
))
2484 return bt
->builtin_int8
;
2485 else if (i386_word_regnum_p (gdbarch
, regnum
))
2486 return bt
->builtin_int16
;
2487 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2488 return bt
->builtin_int32
;
2491 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2494 /* Map a cooked register onto a raw register or memory. For the i386,
2495 the MMX registers need to be mapped onto floating point registers. */
2498 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2505 mmxreg
= regnum
- tdep
->mm0_regnum
;
2506 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2507 tos
= (fstat
>> 11) & 0x7;
2508 fpreg
= (mmxreg
+ tos
) % 8;
2510 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2514 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2515 int regnum
, gdb_byte
*buf
)
2517 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2519 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2521 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2523 /* Extract (always little endian). */
2524 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2525 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2529 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2531 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2533 regnum
-= tdep
->ymm0_regnum
;
2535 /* Extract (always little endian). Read lower 128bits. */
2536 regcache_raw_read (regcache
,
2537 I387_XMM0_REGNUM (tdep
) + regnum
,
2539 memcpy (buf
, raw_buf
, 16);
2540 /* Read upper 128bits. */
2541 regcache_raw_read (regcache
,
2542 tdep
->ymm0h_regnum
+ regnum
,
2544 memcpy (buf
+ 16, raw_buf
, 16);
2546 else if (i386_word_regnum_p (gdbarch
, regnum
))
2548 int gpnum
= regnum
- tdep
->ax_regnum
;
2550 /* Extract (always little endian). */
2551 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2552 memcpy (buf
, raw_buf
, 2);
2554 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2556 /* Check byte pseudo registers last since this function will
2557 be called from amd64_pseudo_register_read, which handles
2558 byte pseudo registers differently. */
2559 int gpnum
= regnum
- tdep
->al_regnum
;
2561 /* Extract (always little endian). We read both lower and
2563 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2565 memcpy (buf
, raw_buf
+ 1, 1);
2567 memcpy (buf
, raw_buf
, 1);
2570 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2575 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2576 int regnum
, const gdb_byte
*buf
)
2578 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2580 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2582 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2585 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2586 /* ... Modify ... (always little endian). */
2587 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2589 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2595 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2597 regnum
-= tdep
->ymm0_regnum
;
2599 /* ... Write lower 128bits. */
2600 regcache_raw_write (regcache
,
2601 I387_XMM0_REGNUM (tdep
) + regnum
,
2603 /* ... Write upper 128bits. */
2604 regcache_raw_write (regcache
,
2605 tdep
->ymm0h_regnum
+ regnum
,
2608 else if (i386_word_regnum_p (gdbarch
, regnum
))
2610 int gpnum
= regnum
- tdep
->ax_regnum
;
2613 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2614 /* ... Modify ... (always little endian). */
2615 memcpy (raw_buf
, buf
, 2);
2617 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2619 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2621 /* Check byte pseudo registers last since this function will
2622 be called from amd64_pseudo_register_read, which handles
2623 byte pseudo registers differently. */
2624 int gpnum
= regnum
- tdep
->al_regnum
;
2626 /* Read ... We read both lower and upper registers. */
2627 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2628 /* ... Modify ... (always little endian). */
2630 memcpy (raw_buf
+ 1, buf
, 1);
2632 memcpy (raw_buf
, buf
, 1);
2634 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2637 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2642 /* Return the register number of the register allocated by GCC after
2643 REGNUM, or -1 if there is no such register. */
2646 i386_next_regnum (int regnum
)
2648 /* GCC allocates the registers in the order:
2650 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2652 Since storing a variable in %esp doesn't make any sense we return
2653 -1 for %ebp and for %esp itself. */
2654 static int next_regnum
[] =
2656 I386_EDX_REGNUM
, /* Slot for %eax. */
2657 I386_EBX_REGNUM
, /* Slot for %ecx. */
2658 I386_ECX_REGNUM
, /* Slot for %edx. */
2659 I386_ESI_REGNUM
, /* Slot for %ebx. */
2660 -1, -1, /* Slots for %esp and %ebp. */
2661 I386_EDI_REGNUM
, /* Slot for %esi. */
2662 I386_EBP_REGNUM
/* Slot for %edi. */
2665 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2666 return next_regnum
[regnum
];
2671 /* Return nonzero if a value of type TYPE stored in register REGNUM
2672 needs any special handling. */
2675 i386_convert_register_p (struct gdbarch
*gdbarch
,
2676 int regnum
, struct type
*type
)
2678 int len
= TYPE_LENGTH (type
);
2680 /* Values may be spread across multiple registers. Most debugging
2681 formats aren't expressive enough to specify the locations, so
2682 some heuristics is involved. Right now we only handle types that
2683 have a length that is a multiple of the word size, since GCC
2684 doesn't seem to put any other types into registers. */
2685 if (len
> 4 && len
% 4 == 0)
2687 int last_regnum
= regnum
;
2691 last_regnum
= i386_next_regnum (last_regnum
);
2695 if (last_regnum
!= -1)
2699 return i387_convert_register_p (gdbarch
, regnum
, type
);
2702 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2703 return its contents in TO. */
2706 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2707 struct type
*type
, gdb_byte
*to
)
2709 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2710 int len
= TYPE_LENGTH (type
);
2712 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2713 available in FRAME (i.e. if it wasn't saved)? */
2715 if (i386_fp_regnum_p (gdbarch
, regnum
))
2717 i387_register_to_value (frame
, regnum
, type
, to
);
2721 /* Read a value spread across multiple registers. */
2723 gdb_assert (len
> 4 && len
% 4 == 0);
2727 gdb_assert (regnum
!= -1);
2728 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2730 get_frame_register (frame
, regnum
, to
);
2731 regnum
= i386_next_regnum (regnum
);
2737 /* Write the contents FROM of a value of type TYPE into register
2738 REGNUM in frame FRAME. */
2741 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2742 struct type
*type
, const gdb_byte
*from
)
2744 int len
= TYPE_LENGTH (type
);
2746 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2748 i387_value_to_register (frame
, regnum
, type
, from
);
2752 /* Write a value spread across multiple registers. */
2754 gdb_assert (len
> 4 && len
% 4 == 0);
2758 gdb_assert (regnum
!= -1);
2759 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2761 put_frame_register (frame
, regnum
, from
);
2762 regnum
= i386_next_regnum (regnum
);
2768 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2769 in the general-purpose register set REGSET to register cache
2770 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2773 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2774 int regnum
, const void *gregs
, size_t len
)
2776 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2777 const gdb_byte
*regs
= gregs
;
2780 gdb_assert (len
== tdep
->sizeof_gregset
);
2782 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2784 if ((regnum
== i
|| regnum
== -1)
2785 && tdep
->gregset_reg_offset
[i
] != -1)
2786 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2790 /* Collect register REGNUM from the register cache REGCACHE and store
2791 it in the buffer specified by GREGS and LEN as described by the
2792 general-purpose register set REGSET. If REGNUM is -1, do this for
2793 all registers in REGSET. */
2796 i386_collect_gregset (const struct regset
*regset
,
2797 const struct regcache
*regcache
,
2798 int regnum
, void *gregs
, size_t len
)
2800 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2801 gdb_byte
*regs
= gregs
;
2804 gdb_assert (len
== tdep
->sizeof_gregset
);
2806 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2808 if ((regnum
== i
|| regnum
== -1)
2809 && tdep
->gregset_reg_offset
[i
] != -1)
2810 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2814 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2815 in the floating-point register set REGSET to register cache
2816 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2819 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2820 int regnum
, const void *fpregs
, size_t len
)
2822 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2824 if (len
== I387_SIZEOF_FXSAVE
)
2826 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2830 gdb_assert (len
== tdep
->sizeof_fpregset
);
2831 i387_supply_fsave (regcache
, regnum
, fpregs
);
2834 /* Collect register REGNUM from the register cache REGCACHE and store
2835 it in the buffer specified by FPREGS and LEN as described by the
2836 floating-point register set REGSET. If REGNUM is -1, do this for
2837 all registers in REGSET. */
2840 i386_collect_fpregset (const struct regset
*regset
,
2841 const struct regcache
*regcache
,
2842 int regnum
, void *fpregs
, size_t len
)
2844 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2846 if (len
== I387_SIZEOF_FXSAVE
)
2848 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2852 gdb_assert (len
== tdep
->sizeof_fpregset
);
2853 i387_collect_fsave (regcache
, regnum
, fpregs
);
2856 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
2859 i386_supply_xstateregset (const struct regset
*regset
,
2860 struct regcache
*regcache
, int regnum
,
2861 const void *xstateregs
, size_t len
)
2863 i387_supply_xsave (regcache
, regnum
, xstateregs
);
2866 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
2869 i386_collect_xstateregset (const struct regset
*regset
,
2870 const struct regcache
*regcache
,
2871 int regnum
, void *xstateregs
, size_t len
)
2873 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2876 /* Return the appropriate register set for the core section identified
2877 by SECT_NAME and SECT_SIZE. */
2879 const struct regset
*
2880 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2881 const char *sect_name
, size_t sect_size
)
2883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2885 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2887 if (tdep
->gregset
== NULL
)
2888 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2889 i386_collect_gregset
);
2890 return tdep
->gregset
;
2893 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2894 || (strcmp (sect_name
, ".reg-xfp") == 0
2895 && sect_size
== I387_SIZEOF_FXSAVE
))
2897 if (tdep
->fpregset
== NULL
)
2898 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2899 i386_collect_fpregset
);
2900 return tdep
->fpregset
;
2903 if (strcmp (sect_name
, ".reg-xstate") == 0)
2905 if (tdep
->xstateregset
== NULL
)
2906 tdep
->xstateregset
= regset_alloc (gdbarch
,
2907 i386_supply_xstateregset
,
2908 i386_collect_xstateregset
);
2910 return tdep
->xstateregset
;
2917 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2920 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2921 CORE_ADDR pc
, char *name
)
2923 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2924 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2927 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2929 unsigned long indirect
=
2930 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2931 struct minimal_symbol
*indsym
=
2932 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2933 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2937 if (strncmp (symname
, "__imp_", 6) == 0
2938 || strncmp (symname
, "_imp_", 5) == 0)
2940 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2943 return 0; /* Not a trampoline. */
2947 /* Return whether the THIS_FRAME corresponds to a sigtramp
2951 i386_sigtramp_p (struct frame_info
*this_frame
)
2953 CORE_ADDR pc
= get_frame_pc (this_frame
);
2956 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2957 return (name
&& strcmp ("_sigtramp", name
) == 0);
2961 /* We have two flavours of disassembly. The machinery on this page
2962 deals with switching between those. */
2965 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2967 gdb_assert (disassembly_flavor
== att_flavor
2968 || disassembly_flavor
== intel_flavor
);
2970 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2971 constified, cast to prevent a compiler warning. */
2972 info
->disassembler_options
= (char *) disassembly_flavor
;
2974 return print_insn_i386 (pc
, info
);
2978 /* There are a few i386 architecture variants that differ only
2979 slightly from the generic i386 target. For now, we don't give them
2980 their own source file, but include them here. As a consequence,
2981 they'll always be included. */
2983 /* System V Release 4 (SVR4). */
2985 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2989 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2991 CORE_ADDR pc
= get_frame_pc (this_frame
);
2994 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2995 currently unknown. */
2996 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2997 return (name
&& (strcmp ("_sigreturn", name
) == 0
2998 || strcmp ("_sigacthandler", name
) == 0
2999 || strcmp ("sigvechandler", name
) == 0));
3002 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3003 address of the associated sigcontext (ucontext) structure. */
3006 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3008 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3009 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3013 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3014 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3016 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3023 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3025 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3026 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3029 /* System V Release 4 (SVR4). */
3032 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3034 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3036 /* System V Release 4 uses ELF. */
3037 i386_elf_init_abi (info
, gdbarch
);
3039 /* System V Release 4 has shared libraries. */
3040 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3042 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3043 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3044 tdep
->sc_pc_offset
= 36 + 14 * 4;
3045 tdep
->sc_sp_offset
= 36 + 17 * 4;
3047 tdep
->jb_pc_offset
= 20;
3053 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3057 /* DJGPP doesn't have any special frames for signal handlers. */
3058 tdep
->sigtramp_p
= NULL
;
3060 tdep
->jb_pc_offset
= 36;
3062 /* DJGPP does not support the SSE registers. */
3063 if (! tdesc_has_registers (info
.target_desc
))
3064 tdep
->tdesc
= tdesc_i386_mmx
;
3066 /* Native compiler is GCC, which uses the SVR4 register numbering
3067 even in COFF and STABS. See the comment in i386_gdbarch_init,
3068 before the calls to set_gdbarch_stab_reg_to_regnum and
3069 set_gdbarch_sdb_reg_to_regnum. */
3070 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3071 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3073 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3077 /* i386 register groups. In addition to the normal groups, add "mmx"
3080 static struct reggroup
*i386_sse_reggroup
;
3081 static struct reggroup
*i386_mmx_reggroup
;
3084 i386_init_reggroups (void)
3086 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3087 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3091 i386_add_reggroups (struct gdbarch
*gdbarch
)
3093 reggroup_add (gdbarch
, i386_sse_reggroup
);
3094 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3095 reggroup_add (gdbarch
, general_reggroup
);
3096 reggroup_add (gdbarch
, float_reggroup
);
3097 reggroup_add (gdbarch
, all_reggroup
);
3098 reggroup_add (gdbarch
, save_reggroup
);
3099 reggroup_add (gdbarch
, restore_reggroup
);
3100 reggroup_add (gdbarch
, vector_reggroup
);
3101 reggroup_add (gdbarch
, system_reggroup
);
3105 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3106 struct reggroup
*group
)
3108 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3109 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3110 ymm_regnum_p
, ymmh_regnum_p
;
3112 /* Don't include pseudo registers, except for MMX, in any register
3114 if (i386_byte_regnum_p (gdbarch
, regnum
))
3117 if (i386_word_regnum_p (gdbarch
, regnum
))
3120 if (i386_dword_regnum_p (gdbarch
, regnum
))
3123 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3124 if (group
== i386_mmx_reggroup
)
3125 return mmx_regnum_p
;
3127 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3128 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3129 if (group
== i386_sse_reggroup
)
3130 return xmm_regnum_p
|| mxcsr_regnum_p
;
3132 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3133 if (group
== vector_reggroup
)
3134 return (mmx_regnum_p
3138 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3139 == I386_XSTATE_SSE_MASK
)));
3141 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3142 || i386_fpc_regnum_p (gdbarch
, regnum
));
3143 if (group
== float_reggroup
)
3146 /* For "info reg all", don't include upper YMM registers nor XMM
3147 registers when AVX is supported. */
3148 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3149 if (group
== all_reggroup
3151 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3155 if (group
== general_reggroup
)
3156 return (!fp_regnum_p
3163 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3167 /* Get the ARGIth function argument for the current function. */
3170 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3173 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3174 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3175 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3176 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3180 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3182 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3184 /* On i386, breakpoint is exactly 1 byte long, so we just
3185 adjust the PC in the regcache. */
3187 regcache_write_pc (regcache
, current_pc
);
3191 #define PREFIX_REPZ 0x01
3192 #define PREFIX_REPNZ 0x02
3193 #define PREFIX_LOCK 0x04
3194 #define PREFIX_DATA 0x08
3195 #define PREFIX_ADDR 0x10
3207 /* i386 arith/logic operations */
3220 struct i386_record_s
3222 struct gdbarch
*gdbarch
;
3223 struct regcache
*regcache
;
3224 CORE_ADDR orig_addr
;
3230 uint8_t mod
, reg
, rm
;
3239 /* Parse "modrm" part in current memory address that irp->addr point to
3240 Return -1 if something wrong. */
3243 i386_record_modrm (struct i386_record_s
*irp
)
3245 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3247 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3250 printf_unfiltered (_("Process record: error reading memory at "
3251 "addr %s len = 1.\n"),
3252 paddress (gdbarch
, irp
->addr
));
3256 irp
->mod
= (irp
->modrm
>> 6) & 3;
3257 irp
->reg
= (irp
->modrm
>> 3) & 7;
3258 irp
->rm
= irp
->modrm
& 7;
3263 /* Get the memory address that current instruction write to and set it to
3264 the argument "addr".
3265 Return -1 if something wrong. */
3268 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3270 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3271 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3283 uint8_t base
= irp
->rm
;
3288 if (target_read_memory (irp
->addr
, &byte
, 1))
3291 printf_unfiltered (_("Process record: error reading memory "
3292 "at addr %s len = 1.\n"),
3293 paddress (gdbarch
, irp
->addr
));
3297 scale
= (byte
>> 6) & 3;
3298 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3306 if ((base
& 7) == 5)
3309 if (target_read_memory (irp
->addr
, buf
, 4))
3312 printf_unfiltered (_("Process record: error reading "
3313 "memory at addr %s len = 4.\n"),
3314 paddress (gdbarch
, irp
->addr
));
3318 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3319 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3320 *addr
+= irp
->addr
+ irp
->rip_offset
;
3324 if (target_read_memory (irp
->addr
, buf
, 1))
3327 printf_unfiltered (_("Process record: error reading memory "
3328 "at addr %s len = 1.\n"),
3329 paddress (gdbarch
, irp
->addr
));
3333 *addr
= (int8_t) buf
[0];
3336 if (target_read_memory (irp
->addr
, buf
, 4))
3339 printf_unfiltered (_("Process record: error reading memory "
3340 "at addr %s len = 4.\n"),
3341 paddress (gdbarch
, irp
->addr
));
3344 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3352 if (base
== 4 && irp
->popl_esp_hack
)
3353 *addr
+= irp
->popl_esp_hack
;
3354 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3357 if (irp
->aflag
== 2)
3362 *addr
= (uint32_t) (offset64
+ *addr
);
3364 if (havesib
&& (index
!= 4 || scale
!= 0))
3366 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3368 if (irp
->aflag
== 2)
3369 *addr
+= offset64
<< scale
;
3371 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3382 if (target_read_memory (irp
->addr
, buf
, 2))
3385 printf_unfiltered (_("Process record: error reading "
3386 "memory at addr %s len = 2.\n"),
3387 paddress (gdbarch
, irp
->addr
));
3391 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3397 if (target_read_memory (irp
->addr
, buf
, 1))
3400 printf_unfiltered (_("Process record: error reading memory "
3401 "at addr %s len = 1.\n"),
3402 paddress (gdbarch
, irp
->addr
));
3406 *addr
= (int8_t) buf
[0];
3409 if (target_read_memory (irp
->addr
, buf
, 2))
3412 printf_unfiltered (_("Process record: error reading memory "
3413 "at addr %s len = 2.\n"),
3414 paddress (gdbarch
, irp
->addr
));
3418 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3425 regcache_raw_read_unsigned (irp
->regcache
,
3426 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3428 *addr
= (uint32_t) (*addr
+ offset64
);
3429 regcache_raw_read_unsigned (irp
->regcache
,
3430 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3432 *addr
= (uint32_t) (*addr
+ offset64
);
3435 regcache_raw_read_unsigned (irp
->regcache
,
3436 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3438 *addr
= (uint32_t) (*addr
+ offset64
);
3439 regcache_raw_read_unsigned (irp
->regcache
,
3440 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3442 *addr
= (uint32_t) (*addr
+ offset64
);
3445 regcache_raw_read_unsigned (irp
->regcache
,
3446 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3448 *addr
= (uint32_t) (*addr
+ offset64
);
3449 regcache_raw_read_unsigned (irp
->regcache
,
3450 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3452 *addr
= (uint32_t) (*addr
+ offset64
);
3455 regcache_raw_read_unsigned (irp
->regcache
,
3456 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3458 *addr
= (uint32_t) (*addr
+ offset64
);
3459 regcache_raw_read_unsigned (irp
->regcache
,
3460 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3462 *addr
= (uint32_t) (*addr
+ offset64
);
3465 regcache_raw_read_unsigned (irp
->regcache
,
3466 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3468 *addr
= (uint32_t) (*addr
+ offset64
);
3471 regcache_raw_read_unsigned (irp
->regcache
,
3472 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3474 *addr
= (uint32_t) (*addr
+ offset64
);
3477 regcache_raw_read_unsigned (irp
->regcache
,
3478 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3480 *addr
= (uint32_t) (*addr
+ offset64
);
3483 regcache_raw_read_unsigned (irp
->regcache
,
3484 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3486 *addr
= (uint32_t) (*addr
+ offset64
);
3496 /* Record the value of the memory that willbe changed in current instruction
3497 to "record_arch_list".
3498 Return -1 if something wrong. */
3501 i386_record_lea_modrm (struct i386_record_s
*irp
)
3503 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3506 if (irp
->override
>= 0)
3508 if (record_memory_query
)
3512 target_terminal_ours ();
3514 Process record ignores the memory change of instruction at address %s\n\
3515 because it can't get the value of the segment register.\n\
3516 Do you want to stop the program?"),
3517 paddress (gdbarch
, irp
->orig_addr
));
3518 target_terminal_inferior ();
3526 if (i386_record_lea_modrm_addr (irp
, &addr
))
3529 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3535 /* Record the push operation to "record_arch_list".
3536 Return -1 if something wrong. */
3539 i386_record_push (struct i386_record_s
*irp
, int size
)
3543 if (record_arch_list_add_reg (irp
->regcache
,
3544 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3546 regcache_raw_read_unsigned (irp
->regcache
,
3547 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3549 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3556 /* Defines contents to record. */
3557 #define I386_SAVE_FPU_REGS 0xfffd
3558 #define I386_SAVE_FPU_ENV 0xfffe
3559 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3561 /* Record the value of floating point registers which will be changed
3562 by the current instruction to "record_arch_list". Return -1 if
3563 something is wrong. */
3565 static int i386_record_floats (struct gdbarch
*gdbarch
,
3566 struct i386_record_s
*ir
,
3569 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3572 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3573 happen. Currently we store st0-st7 registers, but we need not store all
3574 registers all the time, in future we use ftag register and record only
3575 those who are not marked as an empty. */
3577 if (I386_SAVE_FPU_REGS
== iregnum
)
3579 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3581 if (record_arch_list_add_reg (ir
->regcache
, i
))
3585 else if (I386_SAVE_FPU_ENV
== iregnum
)
3587 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3589 if (record_arch_list_add_reg (ir
->regcache
, i
))
3593 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3595 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3597 if (record_arch_list_add_reg (ir
->regcache
, i
))
3601 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3602 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3604 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3609 /* Parameter error. */
3612 if(I386_SAVE_FPU_ENV
!= iregnum
)
3614 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3616 if (record_arch_list_add_reg (ir
->regcache
, i
))
3623 /* Parse the current instruction and record the values of the registers and
3624 memory that will be changed in current instruction to "record_arch_list".
3625 Return -1 if something wrong. */
3627 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3628 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3631 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3632 CORE_ADDR input_addr
)
3634 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3640 gdb_byte buf
[MAX_REGISTER_SIZE
];
3641 struct i386_record_s ir
;
3642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3647 memset (&ir
, 0, sizeof (struct i386_record_s
));
3648 ir
.regcache
= regcache
;
3649 ir
.addr
= input_addr
;
3650 ir
.orig_addr
= input_addr
;
3654 ir
.popl_esp_hack
= 0;
3655 ir
.regmap
= tdep
->record_regmap
;
3656 ir
.gdbarch
= gdbarch
;
3658 if (record_debug
> 1)
3659 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3661 paddress (gdbarch
, ir
.addr
));
3666 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3669 printf_unfiltered (_("Process record: error reading memory at "
3670 "addr %s len = 1.\n"),
3671 paddress (gdbarch
, ir
.addr
));
3675 switch (opcode8
) /* Instruction prefixes */
3677 case REPE_PREFIX_OPCODE
:
3678 prefixes
|= PREFIX_REPZ
;
3680 case REPNE_PREFIX_OPCODE
:
3681 prefixes
|= PREFIX_REPNZ
;
3683 case LOCK_PREFIX_OPCODE
:
3684 prefixes
|= PREFIX_LOCK
;
3686 case CS_PREFIX_OPCODE
:
3687 ir
.override
= X86_RECORD_CS_REGNUM
;
3689 case SS_PREFIX_OPCODE
:
3690 ir
.override
= X86_RECORD_SS_REGNUM
;
3692 case DS_PREFIX_OPCODE
:
3693 ir
.override
= X86_RECORD_DS_REGNUM
;
3695 case ES_PREFIX_OPCODE
:
3696 ir
.override
= X86_RECORD_ES_REGNUM
;
3698 case FS_PREFIX_OPCODE
:
3699 ir
.override
= X86_RECORD_FS_REGNUM
;
3701 case GS_PREFIX_OPCODE
:
3702 ir
.override
= X86_RECORD_GS_REGNUM
;
3704 case DATA_PREFIX_OPCODE
:
3705 prefixes
|= PREFIX_DATA
;
3707 case ADDR_PREFIX_OPCODE
:
3708 prefixes
|= PREFIX_ADDR
;
3710 case 0x40: /* i386 inc %eax */
3711 case 0x41: /* i386 inc %ecx */
3712 case 0x42: /* i386 inc %edx */
3713 case 0x43: /* i386 inc %ebx */
3714 case 0x44: /* i386 inc %esp */
3715 case 0x45: /* i386 inc %ebp */
3716 case 0x46: /* i386 inc %esi */
3717 case 0x47: /* i386 inc %edi */
3718 case 0x48: /* i386 dec %eax */
3719 case 0x49: /* i386 dec %ecx */
3720 case 0x4a: /* i386 dec %edx */
3721 case 0x4b: /* i386 dec %ebx */
3722 case 0x4c: /* i386 dec %esp */
3723 case 0x4d: /* i386 dec %ebp */
3724 case 0x4e: /* i386 dec %esi */
3725 case 0x4f: /* i386 dec %edi */
3726 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3730 rex_w
= (opcode8
>> 3) & 1;
3731 rex_r
= (opcode8
& 0x4) << 1;
3732 ir
.rex_x
= (opcode8
& 0x2) << 2;
3733 ir
.rex_b
= (opcode8
& 0x1) << 3;
3735 else /* 32 bit target */
3744 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3750 if (prefixes
& PREFIX_DATA
)
3753 if (prefixes
& PREFIX_ADDR
)
3755 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3758 /* Now check op code. */
3759 opcode
= (uint32_t) opcode8
;
3764 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3767 printf_unfiltered (_("Process record: error reading memory at "
3768 "addr %s len = 1.\n"),
3769 paddress (gdbarch
, ir
.addr
));
3773 opcode
= (uint32_t) opcode8
| 0x0f00;
3777 case 0x00: /* arith & logic */
3825 if (((opcode
>> 3) & 7) != OP_CMPL
)
3827 if ((opcode
& 1) == 0)
3830 ir
.ot
= ir
.dflag
+ OT_WORD
;
3832 switch ((opcode
>> 1) & 3)
3834 case 0: /* OP Ev, Gv */
3835 if (i386_record_modrm (&ir
))
3839 if (i386_record_lea_modrm (&ir
))
3845 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3847 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3850 case 1: /* OP Gv, Ev */
3851 if (i386_record_modrm (&ir
))
3854 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3856 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3858 case 2: /* OP A, Iv */
3859 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3866 case 0x80: /* GRP1 */
3870 if (i386_record_modrm (&ir
))
3873 if (ir
.reg
!= OP_CMPL
)
3875 if ((opcode
& 1) == 0)
3878 ir
.ot
= ir
.dflag
+ OT_WORD
;
3885 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3886 if (i386_record_lea_modrm (&ir
))
3890 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3892 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3895 case 0x40: /* inc */
3904 case 0x48: /* dec */
3913 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3914 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3917 case 0xf6: /* GRP3 */
3919 if ((opcode
& 1) == 0)
3922 ir
.ot
= ir
.dflag
+ OT_WORD
;
3923 if (i386_record_modrm (&ir
))
3926 if (ir
.mod
!= 3 && ir
.reg
== 0)
3927 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3932 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3938 if (i386_record_lea_modrm (&ir
))
3944 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3946 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3948 if (ir
.reg
== 3) /* neg */
3949 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3956 if (ir
.ot
!= OT_BYTE
)
3957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3962 opcode
= opcode
<< 8 | ir
.modrm
;
3968 case 0xfe: /* GRP4 */
3969 case 0xff: /* GRP5 */
3970 if (i386_record_modrm (&ir
))
3972 if (ir
.reg
>= 2 && opcode
== 0xfe)
3975 opcode
= opcode
<< 8 | ir
.modrm
;
3982 if ((opcode
& 1) == 0)
3985 ir
.ot
= ir
.dflag
+ OT_WORD
;
3988 if (i386_record_lea_modrm (&ir
))
3994 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3996 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4001 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4003 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4005 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4008 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4009 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4011 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4015 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4018 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4020 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4025 opcode
= opcode
<< 8 | ir
.modrm
;
4031 case 0x84: /* test */
4035 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4038 case 0x98: /* CWDE/CBW */
4039 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4042 case 0x99: /* CDQ/CWD */
4043 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4044 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4047 case 0x0faf: /* imul */
4050 ir
.ot
= ir
.dflag
+ OT_WORD
;
4051 if (i386_record_modrm (&ir
))
4054 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4055 else if (opcode
== 0x6b)
4058 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4060 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4061 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4064 case 0x0fc0: /* xadd */
4066 if ((opcode
& 1) == 0)
4069 ir
.ot
= ir
.dflag
+ OT_WORD
;
4070 if (i386_record_modrm (&ir
))
4075 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4077 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4078 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4080 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4084 if (i386_record_lea_modrm (&ir
))
4086 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4088 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4090 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4093 case 0x0fb0: /* cmpxchg */
4095 if ((opcode
& 1) == 0)
4098 ir
.ot
= ir
.dflag
+ OT_WORD
;
4099 if (i386_record_modrm (&ir
))
4104 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4105 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4107 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4111 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4112 if (i386_record_lea_modrm (&ir
))
4115 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4118 case 0x0fc7: /* cmpxchg8b */
4119 if (i386_record_modrm (&ir
))
4124 opcode
= opcode
<< 8 | ir
.modrm
;
4127 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4128 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4129 if (i386_record_lea_modrm (&ir
))
4131 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4134 case 0x50: /* push */
4144 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4146 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4150 case 0x06: /* push es */
4151 case 0x0e: /* push cs */
4152 case 0x16: /* push ss */
4153 case 0x1e: /* push ds */
4154 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4159 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4163 case 0x0fa0: /* push fs */
4164 case 0x0fa8: /* push gs */
4165 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4170 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4174 case 0x60: /* pusha */
4175 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4180 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4184 case 0x58: /* pop */
4192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4193 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4196 case 0x61: /* popa */
4197 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4202 for (regnum
= X86_RECORD_REAX_REGNUM
;
4203 regnum
<= X86_RECORD_REDI_REGNUM
;
4205 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4208 case 0x8f: /* pop */
4209 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4210 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4212 ir
.ot
= ir
.dflag
+ OT_WORD
;
4213 if (i386_record_modrm (&ir
))
4216 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4219 ir
.popl_esp_hack
= 1 << ir
.ot
;
4220 if (i386_record_lea_modrm (&ir
))
4223 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4226 case 0xc8: /* enter */
4227 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4228 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4230 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4234 case 0xc9: /* leave */
4235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4239 case 0x07: /* pop es */
4240 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4245 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4246 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4247 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4250 case 0x17: /* pop ss */
4251 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4257 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4258 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4261 case 0x1f: /* pop ds */
4262 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4268 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4272 case 0x0fa1: /* pop fs */
4273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4278 case 0x0fa9: /* pop gs */
4279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4284 case 0x88: /* mov */
4288 if ((opcode
& 1) == 0)
4291 ir
.ot
= ir
.dflag
+ OT_WORD
;
4293 if (i386_record_modrm (&ir
))
4298 if (opcode
== 0xc6 || opcode
== 0xc7)
4299 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4300 if (i386_record_lea_modrm (&ir
))
4305 if (opcode
== 0xc6 || opcode
== 0xc7)
4307 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4309 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4313 case 0x8a: /* mov */
4315 if ((opcode
& 1) == 0)
4318 ir
.ot
= ir
.dflag
+ OT_WORD
;
4319 if (i386_record_modrm (&ir
))
4322 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4324 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4327 case 0x8c: /* mov seg */
4328 if (i386_record_modrm (&ir
))
4333 opcode
= opcode
<< 8 | ir
.modrm
;
4338 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4342 if (i386_record_lea_modrm (&ir
))
4347 case 0x8e: /* mov seg */
4348 if (i386_record_modrm (&ir
))
4353 regnum
= X86_RECORD_ES_REGNUM
;
4356 regnum
= X86_RECORD_SS_REGNUM
;
4359 regnum
= X86_RECORD_DS_REGNUM
;
4362 regnum
= X86_RECORD_FS_REGNUM
;
4365 regnum
= X86_RECORD_GS_REGNUM
;
4369 opcode
= opcode
<< 8 | ir
.modrm
;
4373 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4374 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4377 case 0x0fb6: /* movzbS */
4378 case 0x0fb7: /* movzwS */
4379 case 0x0fbe: /* movsbS */
4380 case 0x0fbf: /* movswS */
4381 if (i386_record_modrm (&ir
))
4383 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4386 case 0x8d: /* lea */
4387 if (i386_record_modrm (&ir
))
4392 opcode
= opcode
<< 8 | ir
.modrm
;
4397 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4399 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4402 case 0xa0: /* mov EAX */
4405 case 0xd7: /* xlat */
4406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4409 case 0xa2: /* mov EAX */
4411 if (ir
.override
>= 0)
4413 if (record_memory_query
)
4417 target_terminal_ours ();
4419 Process record ignores the memory change of instruction at address %s\n\
4420 because it can't get the value of the segment register.\n\
4421 Do you want to stop the program?"),
4422 paddress (gdbarch
, ir
.orig_addr
));
4423 target_terminal_inferior ();
4430 if ((opcode
& 1) == 0)
4433 ir
.ot
= ir
.dflag
+ OT_WORD
;
4436 if (target_read_memory (ir
.addr
, buf
, 8))
4439 printf_unfiltered (_("Process record: error reading "
4440 "memory at addr 0x%s len = 8.\n"),
4441 paddress (gdbarch
, ir
.addr
));
4445 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4449 if (target_read_memory (ir
.addr
, buf
, 4))
4452 printf_unfiltered (_("Process record: error reading "
4453 "memory at addr 0x%s len = 4.\n"),
4454 paddress (gdbarch
, ir
.addr
));
4458 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4462 if (target_read_memory (ir
.addr
, buf
, 2))
4465 printf_unfiltered (_("Process record: error reading "
4466 "memory at addr 0x%s len = 2.\n"),
4467 paddress (gdbarch
, ir
.addr
));
4471 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4473 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4478 case 0xb0: /* mov R, Ib */
4486 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4487 ? ((opcode
& 0x7) | ir
.rex_b
)
4488 : ((opcode
& 0x7) & 0x3));
4491 case 0xb8: /* mov R, Iv */
4499 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4502 case 0x91: /* xchg R, EAX */
4509 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4510 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4513 case 0x86: /* xchg Ev, Gv */
4515 if ((opcode
& 1) == 0)
4518 ir
.ot
= ir
.dflag
+ OT_WORD
;
4519 if (i386_record_modrm (&ir
))
4524 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4526 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4530 if (i386_record_lea_modrm (&ir
))
4534 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4536 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4539 case 0xc4: /* les Gv */
4540 case 0xc5: /* lds Gv */
4541 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4547 case 0x0fb2: /* lss Gv */
4548 case 0x0fb4: /* lfs Gv */
4549 case 0x0fb5: /* lgs Gv */
4550 if (i386_record_modrm (&ir
))
4558 opcode
= opcode
<< 8 | ir
.modrm
;
4563 case 0xc4: /* les Gv */
4564 regnum
= X86_RECORD_ES_REGNUM
;
4566 case 0xc5: /* lds Gv */
4567 regnum
= X86_RECORD_DS_REGNUM
;
4569 case 0x0fb2: /* lss Gv */
4570 regnum
= X86_RECORD_SS_REGNUM
;
4572 case 0x0fb4: /* lfs Gv */
4573 regnum
= X86_RECORD_FS_REGNUM
;
4575 case 0x0fb5: /* lgs Gv */
4576 regnum
= X86_RECORD_GS_REGNUM
;
4579 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4580 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4581 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4584 case 0xc0: /* shifts */
4590 if ((opcode
& 1) == 0)
4593 ir
.ot
= ir
.dflag
+ OT_WORD
;
4594 if (i386_record_modrm (&ir
))
4596 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4598 if (i386_record_lea_modrm (&ir
))
4604 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4606 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4608 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4615 if (i386_record_modrm (&ir
))
4619 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4624 if (i386_record_lea_modrm (&ir
))
4629 case 0xd8: /* Floats. */
4637 if (i386_record_modrm (&ir
))
4639 ir
.reg
|= ((opcode
& 7) << 3);
4645 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4653 /* For fcom, ficom nothing to do. */
4659 /* For fcomp, ficomp pop FPU stack, store all. */
4660 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4687 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4688 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4689 of code, always affects st(0) register. */
4690 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4714 /* Handling fld, fild. */
4715 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4719 switch (ir
.reg
>> 4)
4722 if (record_arch_list_add_mem (addr64
, 4))
4726 if (record_arch_list_add_mem (addr64
, 8))
4732 if (record_arch_list_add_mem (addr64
, 2))
4738 switch (ir
.reg
>> 4)
4741 if (record_arch_list_add_mem (addr64
, 4))
4743 if (3 == (ir
.reg
& 7))
4745 /* For fstp m32fp. */
4746 if (i386_record_floats (gdbarch
, &ir
,
4747 I386_SAVE_FPU_REGS
))
4752 if (record_arch_list_add_mem (addr64
, 4))
4754 if ((3 == (ir
.reg
& 7))
4755 || (5 == (ir
.reg
& 7))
4756 || (7 == (ir
.reg
& 7)))
4758 /* For fstp insn. */
4759 if (i386_record_floats (gdbarch
, &ir
,
4760 I386_SAVE_FPU_REGS
))
4765 if (record_arch_list_add_mem (addr64
, 8))
4767 if (3 == (ir
.reg
& 7))
4769 /* For fstp m64fp. */
4770 if (i386_record_floats (gdbarch
, &ir
,
4771 I386_SAVE_FPU_REGS
))
4776 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4778 /* For fistp, fbld, fild, fbstp. */
4779 if (i386_record_floats (gdbarch
, &ir
,
4780 I386_SAVE_FPU_REGS
))
4785 if (record_arch_list_add_mem (addr64
, 2))
4794 if (i386_record_floats (gdbarch
, &ir
,
4795 I386_SAVE_FPU_ENV_REG_STACK
))
4800 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4805 if (i386_record_floats (gdbarch
, &ir
,
4806 I386_SAVE_FPU_ENV_REG_STACK
))
4812 if (record_arch_list_add_mem (addr64
, 28))
4817 if (record_arch_list_add_mem (addr64
, 14))
4823 if (record_arch_list_add_mem (addr64
, 2))
4825 /* Insn fstp, fbstp. */
4826 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4831 if (record_arch_list_add_mem (addr64
, 10))
4837 if (record_arch_list_add_mem (addr64
, 28))
4843 if (record_arch_list_add_mem (addr64
, 14))
4847 if (record_arch_list_add_mem (addr64
, 80))
4850 if (i386_record_floats (gdbarch
, &ir
,
4851 I386_SAVE_FPU_ENV_REG_STACK
))
4855 if (record_arch_list_add_mem (addr64
, 8))
4858 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4863 opcode
= opcode
<< 8 | ir
.modrm
;
4868 /* Opcode is an extension of modR/M byte. */
4874 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4878 if (0x0c == (ir
.modrm
>> 4))
4880 if ((ir
.modrm
& 0x0f) <= 7)
4882 if (i386_record_floats (gdbarch
, &ir
,
4883 I386_SAVE_FPU_REGS
))
4888 if (i386_record_floats (gdbarch
, &ir
,
4889 I387_ST0_REGNUM (tdep
)))
4891 /* If only st(0) is changing, then we have already
4893 if ((ir
.modrm
& 0x0f) - 0x08)
4895 if (i386_record_floats (gdbarch
, &ir
,
4896 I387_ST0_REGNUM (tdep
) +
4897 ((ir
.modrm
& 0x0f) - 0x08)))
4915 if (i386_record_floats (gdbarch
, &ir
,
4916 I387_ST0_REGNUM (tdep
)))
4934 if (i386_record_floats (gdbarch
, &ir
,
4935 I386_SAVE_FPU_REGS
))
4939 if (i386_record_floats (gdbarch
, &ir
,
4940 I387_ST0_REGNUM (tdep
)))
4942 if (i386_record_floats (gdbarch
, &ir
,
4943 I387_ST0_REGNUM (tdep
) + 1))
4950 if (0xe9 == ir
.modrm
)
4952 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4955 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4957 if (i386_record_floats (gdbarch
, &ir
,
4958 I387_ST0_REGNUM (tdep
)))
4960 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4962 if (i386_record_floats (gdbarch
, &ir
,
4963 I387_ST0_REGNUM (tdep
) +
4967 else if ((ir
.modrm
& 0x0f) - 0x08)
4969 if (i386_record_floats (gdbarch
, &ir
,
4970 I387_ST0_REGNUM (tdep
) +
4971 ((ir
.modrm
& 0x0f) - 0x08)))
4977 if (0xe3 == ir
.modrm
)
4979 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4982 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4984 if (i386_record_floats (gdbarch
, &ir
,
4985 I387_ST0_REGNUM (tdep
)))
4987 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4989 if (i386_record_floats (gdbarch
, &ir
,
4990 I387_ST0_REGNUM (tdep
) +
4994 else if ((ir
.modrm
& 0x0f) - 0x08)
4996 if (i386_record_floats (gdbarch
, &ir
,
4997 I387_ST0_REGNUM (tdep
) +
4998 ((ir
.modrm
& 0x0f) - 0x08)))
5004 if ((0x0c == ir
.modrm
>> 4)
5005 || (0x0d == ir
.modrm
>> 4)
5006 || (0x0f == ir
.modrm
>> 4))
5008 if ((ir
.modrm
& 0x0f) <= 7)
5010 if (i386_record_floats (gdbarch
, &ir
,
5011 I387_ST0_REGNUM (tdep
) +
5017 if (i386_record_floats (gdbarch
, &ir
,
5018 I387_ST0_REGNUM (tdep
) +
5019 ((ir
.modrm
& 0x0f) - 0x08)))
5025 if (0x0c == ir
.modrm
>> 4)
5027 if (i386_record_floats (gdbarch
, &ir
,
5028 I387_FTAG_REGNUM (tdep
)))
5031 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5033 if ((ir
.modrm
& 0x0f) <= 7)
5035 if (i386_record_floats (gdbarch
, &ir
,
5036 I387_ST0_REGNUM (tdep
) +
5042 if (i386_record_floats (gdbarch
, &ir
,
5043 I386_SAVE_FPU_REGS
))
5049 if ((0x0c == ir
.modrm
>> 4)
5050 || (0x0e == ir
.modrm
>> 4)
5051 || (0x0f == ir
.modrm
>> 4)
5052 || (0xd9 == ir
.modrm
))
5054 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5059 if (0xe0 == ir
.modrm
)
5061 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5064 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5066 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5074 case 0xa4: /* movsS */
5076 case 0xaa: /* stosS */
5078 case 0x6c: /* insS */
5080 regcache_raw_read_unsigned (ir
.regcache
,
5081 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5087 if ((opcode
& 1) == 0)
5090 ir
.ot
= ir
.dflag
+ OT_WORD
;
5091 regcache_raw_read_unsigned (ir
.regcache
,
5092 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5095 regcache_raw_read_unsigned (ir
.regcache
,
5096 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5098 regcache_raw_read_unsigned (ir
.regcache
,
5099 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5101 if (ir
.aflag
&& (es
!= ds
))
5103 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5104 if (record_memory_query
)
5108 target_terminal_ours ();
5110 Process record ignores the memory change of instruction at address %s\n\
5111 because it can't get the value of the segment register.\n\
5112 Do you want to stop the program?"),
5113 paddress (gdbarch
, ir
.orig_addr
));
5114 target_terminal_inferior ();
5121 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5125 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5126 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5127 if (opcode
== 0xa4 || opcode
== 0xa5)
5128 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5129 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5130 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5134 case 0xa6: /* cmpsS */
5136 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5137 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5138 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5139 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5143 case 0xac: /* lodsS */
5145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5147 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5149 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5152 case 0xae: /* scasS */
5154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5155 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5156 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5157 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5160 case 0x6e: /* outsS */
5162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5163 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5165 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5168 case 0xe4: /* port I/O */
5172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5183 case 0xc2: /* ret im */
5184 case 0xc3: /* ret */
5185 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5189 case 0xca: /* lret im */
5190 case 0xcb: /* lret */
5191 case 0xcf: /* iret */
5192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5197 case 0xe8: /* call im */
5198 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5200 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5204 case 0x9a: /* lcall im */
5205 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5210 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5211 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5215 case 0xe9: /* jmp im */
5216 case 0xea: /* ljmp im */
5217 case 0xeb: /* jmp Jb */
5218 case 0x70: /* jcc Jb */
5234 case 0x0f80: /* jcc Jv */
5252 case 0x0f90: /* setcc Gv */
5268 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5270 if (i386_record_modrm (&ir
))
5273 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5277 if (i386_record_lea_modrm (&ir
))
5282 case 0x0f40: /* cmov Gv, Ev */
5298 if (i386_record_modrm (&ir
))
5301 if (ir
.dflag
== OT_BYTE
)
5303 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5307 case 0x9c: /* pushf */
5308 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5309 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5311 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5315 case 0x9d: /* popf */
5316 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5317 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5320 case 0x9e: /* sahf */
5321 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5327 case 0xf5: /* cmc */
5328 case 0xf8: /* clc */
5329 case 0xf9: /* stc */
5330 case 0xfc: /* cld */
5331 case 0xfd: /* std */
5332 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5335 case 0x9f: /* lahf */
5336 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5345 /* bit operations */
5346 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5347 ir
.ot
= ir
.dflag
+ OT_WORD
;
5348 if (i386_record_modrm (&ir
))
5353 opcode
= opcode
<< 8 | ir
.modrm
;
5359 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5362 if (i386_record_lea_modrm (&ir
))
5366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5369 case 0x0fa3: /* bt Gv, Ev */
5370 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5373 case 0x0fab: /* bts */
5374 case 0x0fb3: /* btr */
5375 case 0x0fbb: /* btc */
5376 ir
.ot
= ir
.dflag
+ OT_WORD
;
5377 if (i386_record_modrm (&ir
))
5380 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5384 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5386 regcache_raw_read_unsigned (ir
.regcache
,
5387 ir
.regmap
[ir
.reg
| rex_r
],
5392 addr64
+= ((int16_t) addr
>> 4) << 4;
5395 addr64
+= ((int32_t) addr
>> 5) << 5;
5398 addr64
+= ((int64_t) addr
>> 6) << 6;
5401 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5403 if (i386_record_lea_modrm (&ir
))
5406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5409 case 0x0fbc: /* bsf */
5410 case 0x0fbd: /* bsr */
5411 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5412 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5416 case 0x27: /* daa */
5417 case 0x2f: /* das */
5418 case 0x37: /* aaa */
5419 case 0x3f: /* aas */
5420 case 0xd4: /* aam */
5421 case 0xd5: /* aad */
5422 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5428 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5432 case 0x90: /* nop */
5433 if (prefixes
& PREFIX_LOCK
)
5440 case 0x9b: /* fwait */
5441 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5444 printf_unfiltered (_("Process record: error reading memory at "
5445 "addr 0x%s len = 1.\n"),
5446 paddress (gdbarch
, ir
.addr
));
5449 opcode
= (uint32_t) opcode8
;
5455 case 0xcc: /* int3 */
5456 printf_unfiltered (_("Process record does not support instruction "
5463 case 0xcd: /* int */
5467 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5470 printf_unfiltered (_("Process record: error reading memory "
5471 "at addr %s len = 1.\n"),
5472 paddress (gdbarch
, ir
.addr
));
5476 if (interrupt
!= 0x80
5477 || tdep
->i386_intx80_record
== NULL
)
5479 printf_unfiltered (_("Process record does not support "
5480 "instruction int 0x%02x.\n"),
5485 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5492 case 0xce: /* into */
5493 printf_unfiltered (_("Process record does not support "
5494 "instruction into.\n"));
5499 case 0xfa: /* cli */
5500 case 0xfb: /* sti */
5503 case 0x62: /* bound */
5504 printf_unfiltered (_("Process record does not support "
5505 "instruction bound.\n"));
5510 case 0x0fc8: /* bswap reg */
5518 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5521 case 0xd6: /* salc */
5522 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5528 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5531 case 0xe0: /* loopnz */
5532 case 0xe1: /* loopz */
5533 case 0xe2: /* loop */
5534 case 0xe3: /* jecxz */
5535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5539 case 0x0f30: /* wrmsr */
5540 printf_unfiltered (_("Process record does not support "
5541 "instruction wrmsr.\n"));
5546 case 0x0f32: /* rdmsr */
5547 printf_unfiltered (_("Process record does not support "
5548 "instruction rdmsr.\n"));
5553 case 0x0f31: /* rdtsc */
5554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5558 case 0x0f34: /* sysenter */
5561 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5566 if (tdep
->i386_sysenter_record
== NULL
)
5568 printf_unfiltered (_("Process record does not support "
5569 "instruction sysenter.\n"));
5573 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5579 case 0x0f35: /* sysexit */
5580 printf_unfiltered (_("Process record does not support "
5581 "instruction sysexit.\n"));
5586 case 0x0f05: /* syscall */
5589 if (tdep
->i386_syscall_record
== NULL
)
5591 printf_unfiltered (_("Process record does not support "
5592 "instruction syscall.\n"));
5596 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5602 case 0x0f07: /* sysret */
5603 printf_unfiltered (_("Process record does not support "
5604 "instruction sysret.\n"));
5609 case 0x0fa2: /* cpuid */
5610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5612 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5613 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5616 case 0xf4: /* hlt */
5617 printf_unfiltered (_("Process record does not support "
5618 "instruction hlt.\n"));
5624 if (i386_record_modrm (&ir
))
5631 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5635 if (i386_record_lea_modrm (&ir
))
5644 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5648 opcode
= opcode
<< 8 | ir
.modrm
;
5655 if (i386_record_modrm (&ir
))
5666 opcode
= opcode
<< 8 | ir
.modrm
;
5669 if (ir
.override
>= 0)
5671 if (record_memory_query
)
5675 target_terminal_ours ();
5677 Process record ignores the memory change of instruction at address %s\n\
5678 because it can't get the value of the segment register.\n\
5679 Do you want to stop the program?"),
5680 paddress (gdbarch
, ir
.orig_addr
));
5681 target_terminal_inferior ();
5688 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5690 if (record_arch_list_add_mem (addr64
, 2))
5693 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5695 if (record_arch_list_add_mem (addr64
, 8))
5700 if (record_arch_list_add_mem (addr64
, 4))
5711 case 0: /* monitor */
5714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5718 opcode
= opcode
<< 8 | ir
.modrm
;
5726 if (ir
.override
>= 0)
5728 if (record_memory_query
)
5732 target_terminal_ours ();
5734 Process record ignores the memory change of instruction at address %s\n\
5735 because it can't get the value of the segment register.\n\
5736 Do you want to stop the program?"),
5737 paddress (gdbarch
, ir
.orig_addr
));
5738 target_terminal_inferior ();
5747 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5749 if (record_arch_list_add_mem (addr64
, 2))
5752 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5754 if (record_arch_list_add_mem (addr64
, 8))
5759 if (record_arch_list_add_mem (addr64
, 4))
5771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5772 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5776 else if (ir
.rm
== 1)
5783 opcode
= opcode
<< 8 | ir
.modrm
;
5790 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5796 if (i386_record_lea_modrm (&ir
))
5799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5804 case 7: /* invlpg */
5807 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5812 opcode
= opcode
<< 8 | ir
.modrm
;
5817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5821 opcode
= opcode
<< 8 | ir
.modrm
;
5827 case 0x0f08: /* invd */
5828 case 0x0f09: /* wbinvd */
5831 case 0x63: /* arpl */
5832 if (i386_record_modrm (&ir
))
5834 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5836 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5837 ? (ir
.reg
| rex_r
) : ir
.rm
);
5841 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5842 if (i386_record_lea_modrm (&ir
))
5845 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5849 case 0x0f02: /* lar */
5850 case 0x0f03: /* lsl */
5851 if (i386_record_modrm (&ir
))
5853 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5854 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5858 if (i386_record_modrm (&ir
))
5860 if (ir
.mod
== 3 && ir
.reg
== 3)
5863 opcode
= opcode
<< 8 | ir
.modrm
;
5875 /* nop (multi byte) */
5878 case 0x0f20: /* mov reg, crN */
5879 case 0x0f22: /* mov crN, reg */
5880 if (i386_record_modrm (&ir
))
5882 if ((ir
.modrm
& 0xc0) != 0xc0)
5885 opcode
= opcode
<< 8 | ir
.modrm
;
5896 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5898 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5902 opcode
= opcode
<< 8 | ir
.modrm
;
5908 case 0x0f21: /* mov reg, drN */
5909 case 0x0f23: /* mov drN, reg */
5910 if (i386_record_modrm (&ir
))
5912 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5913 || ir
.reg
== 5 || ir
.reg
>= 8)
5916 opcode
= opcode
<< 8 | ir
.modrm
;
5920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5922 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5925 case 0x0f06: /* clts */
5926 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5929 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
5931 case 0x0f0d: /* 3DNow! prefetch */
5934 case 0x0f0e: /* 3DNow! femms */
5935 case 0x0f77: /* emms */
5936 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
5938 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
5941 case 0x0f0f: /* 3DNow! data */
5942 if (i386_record_modrm (&ir
))
5944 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5946 printf_unfiltered (_("Process record: error reading memory at "
5947 "addr %s len = 1.\n"),
5948 paddress (gdbarch
, ir
.addr
));
5954 case 0x0c: /* 3DNow! pi2fw */
5955 case 0x0d: /* 3DNow! pi2fd */
5956 case 0x1c: /* 3DNow! pf2iw */
5957 case 0x1d: /* 3DNow! pf2id */
5958 case 0x8a: /* 3DNow! pfnacc */
5959 case 0x8e: /* 3DNow! pfpnacc */
5960 case 0x90: /* 3DNow! pfcmpge */
5961 case 0x94: /* 3DNow! pfmin */
5962 case 0x96: /* 3DNow! pfrcp */
5963 case 0x97: /* 3DNow! pfrsqrt */
5964 case 0x9a: /* 3DNow! pfsub */
5965 case 0x9e: /* 3DNow! pfadd */
5966 case 0xa0: /* 3DNow! pfcmpgt */
5967 case 0xa4: /* 3DNow! pfmax */
5968 case 0xa6: /* 3DNow! pfrcpit1 */
5969 case 0xa7: /* 3DNow! pfrsqit1 */
5970 case 0xaa: /* 3DNow! pfsubr */
5971 case 0xae: /* 3DNow! pfacc */
5972 case 0xb0: /* 3DNow! pfcmpeq */
5973 case 0xb4: /* 3DNow! pfmul */
5974 case 0xb6: /* 3DNow! pfrcpit2 */
5975 case 0xb7: /* 3DNow! pmulhrw */
5976 case 0xbb: /* 3DNow! pswapd */
5977 case 0xbf: /* 3DNow! pavgusb */
5978 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
5979 goto no_support_3dnow_data
;
5980 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
5984 no_support_3dnow_data
:
5985 opcode
= (opcode
<< 8) | opcode8
;
5991 case 0x0faa: /* rsm */
5992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5997 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5999 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6000 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6004 if (i386_record_modrm (&ir
))
6008 case 0: /* fxsave */
6012 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6013 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6015 if (record_arch_list_add_mem (tmpu64
, 512))
6020 case 1: /* fxrstor */
6024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6026 for (i
= I387_MM0_REGNUM (tdep
);
6027 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6028 record_arch_list_add_reg (ir
.regcache
, i
);
6030 for (i
= I387_XMM0_REGNUM (tdep
);
6031 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6032 record_arch_list_add_reg (ir
.regcache
, i
);
6034 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6035 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6037 for (i
= I387_ST0_REGNUM (tdep
);
6038 i386_fp_regnum_p (gdbarch
, i
); i
++)
6039 record_arch_list_add_reg (ir
.regcache
, i
);
6041 for (i
= I387_FCTRL_REGNUM (tdep
);
6042 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6043 record_arch_list_add_reg (ir
.regcache
, i
);
6047 case 2: /* ldmxcsr */
6048 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6050 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6053 case 3: /* stmxcsr */
6055 if (i386_record_lea_modrm (&ir
))
6059 case 5: /* lfence */
6060 case 6: /* mfence */
6061 case 7: /* sfence clflush */
6065 opcode
= (opcode
<< 8) | ir
.modrm
;
6071 case 0x0fc3: /* movnti */
6072 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6073 if (i386_record_modrm (&ir
))
6078 if (i386_record_lea_modrm (&ir
))
6082 /* Add prefix to opcode. */
6209 reswitch_prefix_add
:
6217 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6219 printf_unfiltered (_("Process record: error reading memory at "
6220 "addr %s len = 1.\n"),
6221 paddress (gdbarch
, ir
.addr
));
6225 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6226 goto reswitch_prefix_add
;
6229 case 0x0f10: /* movups */
6230 case 0x660f10: /* movupd */
6231 case 0xf30f10: /* movss */
6232 case 0xf20f10: /* movsd */
6233 case 0x0f12: /* movlps */
6234 case 0x660f12: /* movlpd */
6235 case 0xf30f12: /* movsldup */
6236 case 0xf20f12: /* movddup */
6237 case 0x0f14: /* unpcklps */
6238 case 0x660f14: /* unpcklpd */
6239 case 0x0f15: /* unpckhps */
6240 case 0x660f15: /* unpckhpd */
6241 case 0x0f16: /* movhps */
6242 case 0x660f16: /* movhpd */
6243 case 0xf30f16: /* movshdup */
6244 case 0x0f28: /* movaps */
6245 case 0x660f28: /* movapd */
6246 case 0x0f2a: /* cvtpi2ps */
6247 case 0x660f2a: /* cvtpi2pd */
6248 case 0xf30f2a: /* cvtsi2ss */
6249 case 0xf20f2a: /* cvtsi2sd */
6250 case 0x0f2c: /* cvttps2pi */
6251 case 0x660f2c: /* cvttpd2pi */
6252 case 0x0f2d: /* cvtps2pi */
6253 case 0x660f2d: /* cvtpd2pi */
6254 case 0x660f3800: /* pshufb */
6255 case 0x660f3801: /* phaddw */
6256 case 0x660f3802: /* phaddd */
6257 case 0x660f3803: /* phaddsw */
6258 case 0x660f3804: /* pmaddubsw */
6259 case 0x660f3805: /* phsubw */
6260 case 0x660f3806: /* phsubd */
6261 case 0x660f3807: /* phsubsw */
6262 case 0x660f3808: /* psignb */
6263 case 0x660f3809: /* psignw */
6264 case 0x660f380a: /* psignd */
6265 case 0x660f380b: /* pmulhrsw */
6266 case 0x660f3810: /* pblendvb */
6267 case 0x660f3814: /* blendvps */
6268 case 0x660f3815: /* blendvpd */
6269 case 0x660f381c: /* pabsb */
6270 case 0x660f381d: /* pabsw */
6271 case 0x660f381e: /* pabsd */
6272 case 0x660f3820: /* pmovsxbw */
6273 case 0x660f3821: /* pmovsxbd */
6274 case 0x660f3822: /* pmovsxbq */
6275 case 0x660f3823: /* pmovsxwd */
6276 case 0x660f3824: /* pmovsxwq */
6277 case 0x660f3825: /* pmovsxdq */
6278 case 0x660f3828: /* pmuldq */
6279 case 0x660f3829: /* pcmpeqq */
6280 case 0x660f382a: /* movntdqa */
6281 case 0x660f3a08: /* roundps */
6282 case 0x660f3a09: /* roundpd */
6283 case 0x660f3a0a: /* roundss */
6284 case 0x660f3a0b: /* roundsd */
6285 case 0x660f3a0c: /* blendps */
6286 case 0x660f3a0d: /* blendpd */
6287 case 0x660f3a0e: /* pblendw */
6288 case 0x660f3a0f: /* palignr */
6289 case 0x660f3a20: /* pinsrb */
6290 case 0x660f3a21: /* insertps */
6291 case 0x660f3a22: /* pinsrd pinsrq */
6292 case 0x660f3a40: /* dpps */
6293 case 0x660f3a41: /* dppd */
6294 case 0x660f3a42: /* mpsadbw */
6295 case 0x660f3a60: /* pcmpestrm */
6296 case 0x660f3a61: /* pcmpestri */
6297 case 0x660f3a62: /* pcmpistrm */
6298 case 0x660f3a63: /* pcmpistri */
6299 case 0x0f51: /* sqrtps */
6300 case 0x660f51: /* sqrtpd */
6301 case 0xf20f51: /* sqrtsd */
6302 case 0xf30f51: /* sqrtss */
6303 case 0x0f52: /* rsqrtps */
6304 case 0xf30f52: /* rsqrtss */
6305 case 0x0f53: /* rcpps */
6306 case 0xf30f53: /* rcpss */
6307 case 0x0f54: /* andps */
6308 case 0x660f54: /* andpd */
6309 case 0x0f55: /* andnps */
6310 case 0x660f55: /* andnpd */
6311 case 0x0f56: /* orps */
6312 case 0x660f56: /* orpd */
6313 case 0x0f57: /* xorps */
6314 case 0x660f57: /* xorpd */
6315 case 0x0f58: /* addps */
6316 case 0x660f58: /* addpd */
6317 case 0xf20f58: /* addsd */
6318 case 0xf30f58: /* addss */
6319 case 0x0f59: /* mulps */
6320 case 0x660f59: /* mulpd */
6321 case 0xf20f59: /* mulsd */
6322 case 0xf30f59: /* mulss */
6323 case 0x0f5a: /* cvtps2pd */
6324 case 0x660f5a: /* cvtpd2ps */
6325 case 0xf20f5a: /* cvtsd2ss */
6326 case 0xf30f5a: /* cvtss2sd */
6327 case 0x0f5b: /* cvtdq2ps */
6328 case 0x660f5b: /* cvtps2dq */
6329 case 0xf30f5b: /* cvttps2dq */
6330 case 0x0f5c: /* subps */
6331 case 0x660f5c: /* subpd */
6332 case 0xf20f5c: /* subsd */
6333 case 0xf30f5c: /* subss */
6334 case 0x0f5d: /* minps */
6335 case 0x660f5d: /* minpd */
6336 case 0xf20f5d: /* minsd */
6337 case 0xf30f5d: /* minss */
6338 case 0x0f5e: /* divps */
6339 case 0x660f5e: /* divpd */
6340 case 0xf20f5e: /* divsd */
6341 case 0xf30f5e: /* divss */
6342 case 0x0f5f: /* maxps */
6343 case 0x660f5f: /* maxpd */
6344 case 0xf20f5f: /* maxsd */
6345 case 0xf30f5f: /* maxss */
6346 case 0x660f60: /* punpcklbw */
6347 case 0x660f61: /* punpcklwd */
6348 case 0x660f62: /* punpckldq */
6349 case 0x660f63: /* packsswb */
6350 case 0x660f64: /* pcmpgtb */
6351 case 0x660f65: /* pcmpgtw */
6352 case 0x660f66: /* pcmpgtd */
6353 case 0x660f67: /* packuswb */
6354 case 0x660f68: /* punpckhbw */
6355 case 0x660f69: /* punpckhwd */
6356 case 0x660f6a: /* punpckhdq */
6357 case 0x660f6b: /* packssdw */
6358 case 0x660f6c: /* punpcklqdq */
6359 case 0x660f6d: /* punpckhqdq */
6360 case 0x660f6e: /* movd */
6361 case 0x660f6f: /* movdqa */
6362 case 0xf30f6f: /* movdqu */
6363 case 0x660f70: /* pshufd */
6364 case 0xf20f70: /* pshuflw */
6365 case 0xf30f70: /* pshufhw */
6366 case 0x660f74: /* pcmpeqb */
6367 case 0x660f75: /* pcmpeqw */
6368 case 0x660f76: /* pcmpeqd */
6369 case 0x660f7c: /* haddpd */
6370 case 0xf20f7c: /* haddps */
6371 case 0x660f7d: /* hsubpd */
6372 case 0xf20f7d: /* hsubps */
6373 case 0xf30f7e: /* movq */
6374 case 0x0fc2: /* cmpps */
6375 case 0x660fc2: /* cmppd */
6376 case 0xf20fc2: /* cmpsd */
6377 case 0xf30fc2: /* cmpss */
6378 case 0x660fc4: /* pinsrw */
6379 case 0x0fc6: /* shufps */
6380 case 0x660fc6: /* shufpd */
6381 case 0x660fd0: /* addsubpd */
6382 case 0xf20fd0: /* addsubps */
6383 case 0x660fd1: /* psrlw */
6384 case 0x660fd2: /* psrld */
6385 case 0x660fd3: /* psrlq */
6386 case 0x660fd4: /* paddq */
6387 case 0x660fd5: /* pmullw */
6388 case 0xf30fd6: /* movq2dq */
6389 case 0x660fd8: /* psubusb */
6390 case 0x660fd9: /* psubusw */
6391 case 0x660fda: /* pminub */
6392 case 0x660fdb: /* pand */
6393 case 0x660fdc: /* paddusb */
6394 case 0x660fdd: /* paddusw */
6395 case 0x660fde: /* pmaxub */
6396 case 0x660fdf: /* pandn */
6397 case 0x660fe0: /* pavgb */
6398 case 0x660fe1: /* psraw */
6399 case 0x660fe2: /* psrad */
6400 case 0x660fe3: /* pavgw */
6401 case 0x660fe4: /* pmulhuw */
6402 case 0x660fe5: /* pmulhw */
6403 case 0x660fe6: /* cvttpd2dq */
6404 case 0xf20fe6: /* cvtpd2dq */
6405 case 0xf30fe6: /* cvtdq2pd */
6406 case 0x660fe8: /* psubsb */
6407 case 0x660fe9: /* psubsw */
6408 case 0x660fea: /* pminsw */
6409 case 0x660feb: /* por */
6410 case 0x660fec: /* paddsb */
6411 case 0x660fed: /* paddsw */
6412 case 0x660fee: /* pmaxsw */
6413 case 0x660fef: /* pxor */
6414 case 0xf20ff0: /* lddqu */
6415 case 0x660ff1: /* psllw */
6416 case 0x660ff2: /* pslld */
6417 case 0x660ff3: /* psllq */
6418 case 0x660ff4: /* pmuludq */
6419 case 0x660ff5: /* pmaddwd */
6420 case 0x660ff6: /* psadbw */
6421 case 0x660ff8: /* psubb */
6422 case 0x660ff9: /* psubw */
6423 case 0x660ffa: /* psubd */
6424 case 0x660ffb: /* psubq */
6425 case 0x660ffc: /* paddb */
6426 case 0x660ffd: /* paddw */
6427 case 0x660ffe: /* paddd */
6428 if (i386_record_modrm (&ir
))
6431 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6433 record_arch_list_add_reg (ir
.regcache
,
6434 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6435 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6436 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6439 case 0x0f11: /* movups */
6440 case 0x660f11: /* movupd */
6441 case 0xf30f11: /* movss */
6442 case 0xf20f11: /* movsd */
6443 case 0x0f13: /* movlps */
6444 case 0x660f13: /* movlpd */
6445 case 0x0f17: /* movhps */
6446 case 0x660f17: /* movhpd */
6447 case 0x0f29: /* movaps */
6448 case 0x660f29: /* movapd */
6449 case 0x660f3a14: /* pextrb */
6450 case 0x660f3a15: /* pextrw */
6451 case 0x660f3a16: /* pextrd pextrq */
6452 case 0x660f3a17: /* extractps */
6453 case 0x660f7f: /* movdqa */
6454 case 0xf30f7f: /* movdqu */
6455 if (i386_record_modrm (&ir
))
6459 if (opcode
== 0x0f13 || opcode
== 0x660f13
6460 || opcode
== 0x0f17 || opcode
== 0x660f17)
6463 if (!i386_xmm_regnum_p (gdbarch
,
6464 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6466 record_arch_list_add_reg (ir
.regcache
,
6467 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6489 if (i386_record_lea_modrm (&ir
))
6494 case 0x0f2b: /* movntps */
6495 case 0x660f2b: /* movntpd */
6496 case 0x0fe7: /* movntq */
6497 case 0x660fe7: /* movntdq */
6500 if (opcode
== 0x0fe7)
6504 if (i386_record_lea_modrm (&ir
))
6508 case 0xf30f2c: /* cvttss2si */
6509 case 0xf20f2c: /* cvttsd2si */
6510 case 0xf30f2d: /* cvtss2si */
6511 case 0xf20f2d: /* cvtsd2si */
6512 case 0xf20f38f0: /* crc32 */
6513 case 0xf20f38f1: /* crc32 */
6514 case 0x0f50: /* movmskps */
6515 case 0x660f50: /* movmskpd */
6516 case 0x0fc5: /* pextrw */
6517 case 0x660fc5: /* pextrw */
6518 case 0x0fd7: /* pmovmskb */
6519 case 0x660fd7: /* pmovmskb */
6520 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6523 case 0x0f3800: /* pshufb */
6524 case 0x0f3801: /* phaddw */
6525 case 0x0f3802: /* phaddd */
6526 case 0x0f3803: /* phaddsw */
6527 case 0x0f3804: /* pmaddubsw */
6528 case 0x0f3805: /* phsubw */
6529 case 0x0f3806: /* phsubd */
6530 case 0x0f3807: /* phsubsw */
6531 case 0x0f3808: /* psignb */
6532 case 0x0f3809: /* psignw */
6533 case 0x0f380a: /* psignd */
6534 case 0x0f380b: /* pmulhrsw */
6535 case 0x0f381c: /* pabsb */
6536 case 0x0f381d: /* pabsw */
6537 case 0x0f381e: /* pabsd */
6538 case 0x0f382b: /* packusdw */
6539 case 0x0f3830: /* pmovzxbw */
6540 case 0x0f3831: /* pmovzxbd */
6541 case 0x0f3832: /* pmovzxbq */
6542 case 0x0f3833: /* pmovzxwd */
6543 case 0x0f3834: /* pmovzxwq */
6544 case 0x0f3835: /* pmovzxdq */
6545 case 0x0f3837: /* pcmpgtq */
6546 case 0x0f3838: /* pminsb */
6547 case 0x0f3839: /* pminsd */
6548 case 0x0f383a: /* pminuw */
6549 case 0x0f383b: /* pminud */
6550 case 0x0f383c: /* pmaxsb */
6551 case 0x0f383d: /* pmaxsd */
6552 case 0x0f383e: /* pmaxuw */
6553 case 0x0f383f: /* pmaxud */
6554 case 0x0f3840: /* pmulld */
6555 case 0x0f3841: /* phminposuw */
6556 case 0x0f3a0f: /* palignr */
6557 case 0x0f60: /* punpcklbw */
6558 case 0x0f61: /* punpcklwd */
6559 case 0x0f62: /* punpckldq */
6560 case 0x0f63: /* packsswb */
6561 case 0x0f64: /* pcmpgtb */
6562 case 0x0f65: /* pcmpgtw */
6563 case 0x0f66: /* pcmpgtd */
6564 case 0x0f67: /* packuswb */
6565 case 0x0f68: /* punpckhbw */
6566 case 0x0f69: /* punpckhwd */
6567 case 0x0f6a: /* punpckhdq */
6568 case 0x0f6b: /* packssdw */
6569 case 0x0f6e: /* movd */
6570 case 0x0f6f: /* movq */
6571 case 0x0f70: /* pshufw */
6572 case 0x0f74: /* pcmpeqb */
6573 case 0x0f75: /* pcmpeqw */
6574 case 0x0f76: /* pcmpeqd */
6575 case 0x0fc4: /* pinsrw */
6576 case 0x0fd1: /* psrlw */
6577 case 0x0fd2: /* psrld */
6578 case 0x0fd3: /* psrlq */
6579 case 0x0fd4: /* paddq */
6580 case 0x0fd5: /* pmullw */
6581 case 0xf20fd6: /* movdq2q */
6582 case 0x0fd8: /* psubusb */
6583 case 0x0fd9: /* psubusw */
6584 case 0x0fda: /* pminub */
6585 case 0x0fdb: /* pand */
6586 case 0x0fdc: /* paddusb */
6587 case 0x0fdd: /* paddusw */
6588 case 0x0fde: /* pmaxub */
6589 case 0x0fdf: /* pandn */
6590 case 0x0fe0: /* pavgb */
6591 case 0x0fe1: /* psraw */
6592 case 0x0fe2: /* psrad */
6593 case 0x0fe3: /* pavgw */
6594 case 0x0fe4: /* pmulhuw */
6595 case 0x0fe5: /* pmulhw */
6596 case 0x0fe8: /* psubsb */
6597 case 0x0fe9: /* psubsw */
6598 case 0x0fea: /* pminsw */
6599 case 0x0feb: /* por */
6600 case 0x0fec: /* paddsb */
6601 case 0x0fed: /* paddsw */
6602 case 0x0fee: /* pmaxsw */
6603 case 0x0fef: /* pxor */
6604 case 0x0ff1: /* psllw */
6605 case 0x0ff2: /* pslld */
6606 case 0x0ff3: /* psllq */
6607 case 0x0ff4: /* pmuludq */
6608 case 0x0ff5: /* pmaddwd */
6609 case 0x0ff6: /* psadbw */
6610 case 0x0ff8: /* psubb */
6611 case 0x0ff9: /* psubw */
6612 case 0x0ffa: /* psubd */
6613 case 0x0ffb: /* psubq */
6614 case 0x0ffc: /* paddb */
6615 case 0x0ffd: /* paddw */
6616 case 0x0ffe: /* paddd */
6617 if (i386_record_modrm (&ir
))
6619 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6621 record_arch_list_add_reg (ir
.regcache
,
6622 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6625 case 0x0f71: /* psllw */
6626 case 0x0f72: /* pslld */
6627 case 0x0f73: /* psllq */
6628 if (i386_record_modrm (&ir
))
6630 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6632 record_arch_list_add_reg (ir
.regcache
,
6633 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6636 case 0x660f71: /* psllw */
6637 case 0x660f72: /* pslld */
6638 case 0x660f73: /* psllq */
6639 if (i386_record_modrm (&ir
))
6642 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6644 record_arch_list_add_reg (ir
.regcache
,
6645 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6648 case 0x0f7e: /* movd */
6649 case 0x660f7e: /* movd */
6650 if (i386_record_modrm (&ir
))
6653 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6660 if (i386_record_lea_modrm (&ir
))
6665 case 0x0f7f: /* movq */
6666 if (i386_record_modrm (&ir
))
6670 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6672 record_arch_list_add_reg (ir
.regcache
,
6673 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6678 if (i386_record_lea_modrm (&ir
))
6683 case 0xf30fb8: /* popcnt */
6684 if (i386_record_modrm (&ir
))
6686 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6690 case 0x660fd6: /* movq */
6691 if (i386_record_modrm (&ir
))
6696 if (!i386_xmm_regnum_p (gdbarch
,
6697 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6699 record_arch_list_add_reg (ir
.regcache
,
6700 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6705 if (i386_record_lea_modrm (&ir
))
6710 case 0x660f3817: /* ptest */
6711 case 0x0f2e: /* ucomiss */
6712 case 0x660f2e: /* ucomisd */
6713 case 0x0f2f: /* comiss */
6714 case 0x660f2f: /* comisd */
6715 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6718 case 0x0ff7: /* maskmovq */
6719 regcache_raw_read_unsigned (ir
.regcache
,
6720 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6722 if (record_arch_list_add_mem (addr
, 64))
6726 case 0x660ff7: /* maskmovdqu */
6727 regcache_raw_read_unsigned (ir
.regcache
,
6728 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6730 if (record_arch_list_add_mem (addr
, 128))
6745 /* In the future, maybe still need to deal with need_dasm. */
6746 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6747 if (record_arch_list_add_end ())
6753 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6754 "at address %s.\n"),
6755 (unsigned int) (opcode
),
6756 paddress (gdbarch
, ir
.orig_addr
));
6760 static const int i386_record_regmap
[] =
6762 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6763 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6764 0, 0, 0, 0, 0, 0, 0, 0,
6765 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6766 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6769 /* Check that the given address appears suitable for a fast
6770 tracepoint, which on x86 means that we need an instruction of at
6771 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6772 jump and not have to worry about program jumps to an address in the
6773 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6774 of instruction to replace, and 0 if not, plus an explanatory
6778 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6779 CORE_ADDR addr
, int *isize
, char **msg
)
6782 static struct ui_file
*gdb_null
= NULL
;
6784 /* This is based on the target agent using a 4-byte relative jump.
6785 Alternate future possibilities include 8-byte offset for x86-84,
6786 or 3-byte jumps if the program has trampoline space close by. */
6789 /* Dummy file descriptor for the disassembler. */
6791 gdb_null
= ui_file_new ();
6793 /* Check for fit. */
6794 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6797 /* Return a bit of target-specific detail to add to the caller's
6798 generic failure message. */
6800 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
6801 "need at least %d bytes for the jump"),
6814 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6815 struct tdesc_arch_data
*tdesc_data
)
6817 const struct target_desc
*tdesc
= tdep
->tdesc
;
6818 const struct tdesc_feature
*feature_core
;
6819 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6820 int i
, num_regs
, valid_p
;
6822 if (! tdesc_has_registers (tdesc
))
6825 /* Get core registers. */
6826 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6827 if (feature_core
== NULL
)
6830 /* Get SSE registers. */
6831 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6833 /* Try AVX registers. */
6834 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6838 /* The XCR0 bits. */
6841 /* AVX register description requires SSE register description. */
6845 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6847 /* It may have been set by OSABI initialization function. */
6848 if (tdep
->num_ymm_regs
== 0)
6850 tdep
->ymmh_register_names
= i386_ymmh_names
;
6851 tdep
->num_ymm_regs
= 8;
6852 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
6855 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
6856 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
6857 tdep
->ymm0h_regnum
+ i
,
6858 tdep
->ymmh_register_names
[i
]);
6860 else if (feature_sse
)
6861 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
6864 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
6865 tdep
->num_xmm_regs
= 0;
6868 num_regs
= tdep
->num_core_regs
;
6869 for (i
= 0; i
< num_regs
; i
++)
6870 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
6871 tdep
->register_names
[i
]);
6875 /* Need to include %mxcsr, so add one. */
6876 num_regs
+= tdep
->num_xmm_regs
+ 1;
6877 for (; i
< num_regs
; i
++)
6878 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
6879 tdep
->register_names
[i
]);
6886 static struct gdbarch
*
6887 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6889 struct gdbarch_tdep
*tdep
;
6890 struct gdbarch
*gdbarch
;
6891 struct tdesc_arch_data
*tdesc_data
;
6892 const struct target_desc
*tdesc
;
6896 /* If there is already a candidate, use it. */
6897 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6899 return arches
->gdbarch
;
6901 /* Allocate space for the new architecture. */
6902 tdep
= XCALLOC (1, struct gdbarch_tdep
);
6903 gdbarch
= gdbarch_alloc (&info
, tdep
);
6905 /* General-purpose registers. */
6906 tdep
->gregset
= NULL
;
6907 tdep
->gregset_reg_offset
= NULL
;
6908 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
6909 tdep
->sizeof_gregset
= 0;
6911 /* Floating-point registers. */
6912 tdep
->fpregset
= NULL
;
6913 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
6915 tdep
->xstateregset
= NULL
;
6917 /* The default settings include the FPU registers, the MMX registers
6918 and the SSE registers. This can be overridden for a specific ABI
6919 by adjusting the members `st0_regnum', `mm0_regnum' and
6920 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
6921 will show up in the output of "info all-registers". */
6923 tdep
->st0_regnum
= I386_ST0_REGNUM
;
6925 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
6926 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
6928 tdep
->jb_pc_offset
= -1;
6929 tdep
->struct_return
= pcc_struct_return
;
6930 tdep
->sigtramp_start
= 0;
6931 tdep
->sigtramp_end
= 0;
6932 tdep
->sigtramp_p
= i386_sigtramp_p
;
6933 tdep
->sigcontext_addr
= NULL
;
6934 tdep
->sc_reg_offset
= NULL
;
6935 tdep
->sc_pc_offset
= -1;
6936 tdep
->sc_sp_offset
= -1;
6938 tdep
->xsave_xcr0_offset
= -1;
6940 tdep
->record_regmap
= i386_record_regmap
;
6942 /* The format used for `long double' on almost all i386 targets is
6943 the i387 extended floating-point format. In fact, of all targets
6944 in the GCC 2.95 tree, only OSF/1 does it different, and insists
6945 on having a `long double' that's not `long' at all. */
6946 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
6948 /* Although the i387 extended floating-point has only 80 significant
6949 bits, a `long double' actually takes up 96, probably to enforce
6951 set_gdbarch_long_double_bit (gdbarch
, 96);
6953 /* Register numbers of various important registers. */
6954 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
6955 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
6956 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
6957 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
6959 /* NOTE: kettenis/20040418: GCC does have two possible register
6960 numbering schemes on the i386: dbx and SVR4. These schemes
6961 differ in how they number %ebp, %esp, %eflags, and the
6962 floating-point registers, and are implemented by the arrays
6963 dbx_register_map[] and svr4_dbx_register_map in
6964 gcc/config/i386.c. GCC also defines a third numbering scheme in
6965 gcc/config/i386.c, which it designates as the "default" register
6966 map used in 64bit mode. This last register numbering scheme is
6967 implemented in dbx64_register_map, and is used for AMD64; see
6970 Currently, each GCC i386 target always uses the same register
6971 numbering scheme across all its supported debugging formats
6972 i.e. SDB (COFF), stabs and DWARF 2. This is because
6973 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
6974 DBX_REGISTER_NUMBER macro which is defined by each target's
6975 respective config header in a manner independent of the requested
6976 output debugging format.
6978 This does not match the arrangement below, which presumes that
6979 the SDB and stabs numbering schemes differ from the DWARF and
6980 DWARF 2 ones. The reason for this arrangement is that it is
6981 likely to get the numbering scheme for the target's
6982 default/native debug format right. For targets where GCC is the
6983 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
6984 targets where the native toolchain uses a different numbering
6985 scheme for a particular debug format (stabs-in-ELF on Solaris)
6986 the defaults below will have to be overridden, like
6987 i386_elf_init_abi() does. */
6989 /* Use the dbx register numbering scheme for stabs and COFF. */
6990 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6991 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
6993 /* Use the SVR4 register numbering scheme for DWARF 2. */
6994 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
6996 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
6997 be in use on any of the supported i386 targets. */
6999 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7001 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7003 /* Call dummy code. */
7004 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7006 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7007 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7008 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7010 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7012 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7014 /* Stack grows downward. */
7015 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7017 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7018 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7019 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7021 set_gdbarch_frame_args_skip (gdbarch
, 8);
7023 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7025 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7027 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7029 /* Add the i386 register groups. */
7030 i386_add_reggroups (gdbarch
);
7031 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7033 /* Helper for function argument information. */
7034 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7036 /* Hook the function epilogue frame unwinder. This unwinder is
7037 appended to the list first, so that it supercedes the Dwarf
7038 unwinder in function epilogues (where the Dwarf unwinder
7039 currently fails). */
7040 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7042 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7043 to the list before the prologue-based unwinders, so that Dwarf
7044 CFI info will be used if it is available. */
7045 dwarf2_append_unwinders (gdbarch
);
7047 frame_base_set_default (gdbarch
, &i386_frame_base
);
7049 /* Pseudo registers may be changed by amd64_init_abi. */
7050 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7051 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7053 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7054 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7056 /* Override the normal target description method to make the AVX
7057 upper halves anonymous. */
7058 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7060 /* Even though the default ABI only includes general-purpose registers,
7061 floating-point registers and the SSE registers, we have to leave a
7062 gap for the upper AVX registers. */
7063 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7065 /* Get the x86 target description from INFO. */
7066 tdesc
= info
.target_desc
;
7067 if (! tdesc_has_registers (tdesc
))
7069 tdep
->tdesc
= tdesc
;
7071 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7072 tdep
->register_names
= i386_register_names
;
7074 /* No upper YMM registers. */
7075 tdep
->ymmh_register_names
= NULL
;
7076 tdep
->ymm0h_regnum
= -1;
7078 tdep
->num_byte_regs
= 8;
7079 tdep
->num_word_regs
= 8;
7080 tdep
->num_dword_regs
= 0;
7081 tdep
->num_mmx_regs
= 8;
7082 tdep
->num_ymm_regs
= 0;
7084 tdesc_data
= tdesc_data_alloc ();
7086 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7088 /* Hook in ABI-specific overrides, if they have been registered. */
7089 info
.tdep_info
= (void *) tdesc_data
;
7090 gdbarch_init_osabi (info
, gdbarch
);
7092 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7094 tdesc_data_cleanup (tdesc_data
);
7096 gdbarch_free (gdbarch
);
7100 /* Wire in pseudo registers. Number of pseudo registers may be
7102 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7103 + tdep
->num_word_regs
7104 + tdep
->num_dword_regs
7105 + tdep
->num_mmx_regs
7106 + tdep
->num_ymm_regs
));
7108 /* Target description may be changed. */
7109 tdesc
= tdep
->tdesc
;
7111 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7113 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7114 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7116 /* Make %al the first pseudo-register. */
7117 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7118 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7120 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7121 if (tdep
->num_dword_regs
)
7123 /* Support dword pseudo-register if it hasn't been disabled. */
7124 tdep
->eax_regnum
= ymm0_regnum
;
7125 ymm0_regnum
+= tdep
->num_dword_regs
;
7128 tdep
->eax_regnum
= -1;
7130 mm0_regnum
= ymm0_regnum
;
7131 if (tdep
->num_ymm_regs
)
7133 /* Support YMM pseudo-register if it is available. */
7134 tdep
->ymm0_regnum
= ymm0_regnum
;
7135 mm0_regnum
+= tdep
->num_ymm_regs
;
7138 tdep
->ymm0_regnum
= -1;
7140 if (tdep
->num_mmx_regs
!= 0)
7142 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7143 tdep
->mm0_regnum
= mm0_regnum
;
7146 tdep
->mm0_regnum
= -1;
7148 /* Hook in the legacy prologue-based unwinders last (fallback). */
7149 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7150 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7152 /* If we have a register mapping, enable the generic core file
7153 support, unless it has already been enabled. */
7154 if (tdep
->gregset_reg_offset
7155 && !gdbarch_regset_from_core_section_p (gdbarch
))
7156 set_gdbarch_regset_from_core_section (gdbarch
,
7157 i386_regset_from_core_section
);
7159 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7160 i386_skip_permanent_breakpoint
);
7162 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7163 i386_fast_tracepoint_valid_at
);
7168 static enum gdb_osabi
7169 i386_coff_osabi_sniffer (bfd
*abfd
)
7171 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7172 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7173 return GDB_OSABI_GO32
;
7175 return GDB_OSABI_UNKNOWN
;
7179 /* Provide a prototype to silence -Wmissing-prototypes. */
7180 void _initialize_i386_tdep (void);
7183 _initialize_i386_tdep (void)
7185 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7187 /* Add the variable that controls the disassembly flavor. */
7188 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7189 &disassembly_flavor
, _("\
7190 Set the disassembly flavor."), _("\
7191 Show the disassembly flavor."), _("\
7192 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7194 NULL
, /* FIXME: i18n: */
7195 &setlist
, &showlist
);
7197 /* Add the variable that controls the convention for returning
7199 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7200 &struct_convention
, _("\
7201 Set the convention for returning small structs."), _("\
7202 Show the convention for returning small structs."), _("\
7203 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7206 NULL
, /* FIXME: i18n: */
7207 &setlist
, &showlist
);
7209 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7210 i386_coff_osabi_sniffer
);
7212 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7213 i386_svr4_init_abi
);
7214 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7215 i386_go32_init_abi
);
7217 /* Initialize the i386-specific register groups. */
7218 i386_init_reggroups ();
7220 /* Initialize the standard target descriptions. */
7221 initialize_tdesc_i386 ();
7222 initialize_tdesc_i386_mmx ();
7223 initialize_tdesc_i386_avx ();
7225 /* Tell remote stub that we support XML target description. */
7226 register_remote_support_xml ("i386");