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[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "doublest.h"
22 #include "floatformat.h"
23 #include "frame.h"
24 #include "gdbcore.h"
25 #include "inferior.h"
26 #include "language.h"
27 #include "regcache.h"
28 #include "value.h"
29
30 #include "i386-tdep.h"
31 #include "i387-tdep.h"
32 #include "x86-xstate.h"
33
34 /* Print the floating point number specified by RAW. */
35
36 static void
37 print_i387_value (struct gdbarch *gdbarch,
38 const gdb_byte *raw, struct ui_file *file)
39 {
40 DOUBLEST value;
41
42 /* Using extract_typed_floating here might affect the representation
43 of certain numbers such as NaNs, even if GDB is running natively.
44 This is fine since our caller already detects such special
45 numbers and we print the hexadecimal representation anyway. */
46 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
47
48 /* We try to print 19 digits. The last digit may or may not contain
49 garbage, but we'd better print one too many. We need enough room
50 to print the value, 1 position for the sign, 1 for the decimal
51 point, 19 for the digits and 6 for the exponent adds up to 27. */
52 #ifdef PRINTF_HAS_LONG_DOUBLE
53 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
54 #else
55 fprintf_filtered (file, " %-+27.19g", (double) value);
56 #endif
57 }
58
59 /* Print the classification for the register contents RAW. */
60
61 static void
62 print_i387_ext (struct gdbarch *gdbarch,
63 const gdb_byte *raw, struct ui_file *file)
64 {
65 int sign;
66 int integer;
67 unsigned int exponent;
68 unsigned long fraction[2];
69
70 sign = raw[9] & 0x80;
71 integer = raw[7] & 0x80;
72 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
73 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
74 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
75 | (raw[5] << 8) | raw[4]);
76
77 if (exponent == 0x7fff && integer)
78 {
79 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
80 /* Infinity. */
81 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
82 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
83 /* Real Indefinite (QNaN). */
84 fputs_unfiltered (" Real Indefinite (QNaN)", file);
85 else if (fraction[1] & 0x40000000)
86 /* QNaN. */
87 fputs_filtered (" QNaN", file);
88 else
89 /* SNaN. */
90 fputs_filtered (" SNaN", file);
91 }
92 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
93 /* Normal. */
94 print_i387_value (gdbarch, raw, file);
95 else if (exponent == 0x0000)
96 {
97 /* Denormal or zero. */
98 print_i387_value (gdbarch, raw, file);
99
100 if (integer)
101 /* Pseudo-denormal. */
102 fputs_filtered (" Pseudo-denormal", file);
103 else if (fraction[0] || fraction[1])
104 /* Denormal. */
105 fputs_filtered (" Denormal", file);
106 }
107 else
108 /* Unsupported. */
109 fputs_filtered (" Unsupported", file);
110 }
111
112 /* Print the status word STATUS. If STATUS_P is false, then STATUS
113 was unavailable. */
114
115 static void
116 print_i387_status_word (int status_p,
117 unsigned int status, struct ui_file *file)
118 {
119 fprintf_filtered (file, "Status Word: ");
120 if (!status_p)
121 {
122 fprintf_filtered (file, "%s\n", _("<unavailable>"));
123 return;
124 }
125
126 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
127 fputs_filtered (" ", file);
128 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
129 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
130 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
131 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
134 fputs_filtered (" ", file);
135 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
136 fputs_filtered (" ", file);
137 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
138 fputs_filtered (" ", file);
139 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
140 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
141 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
142 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
143
144 fputs_filtered ("\n", file);
145
146 fprintf_filtered (file,
147 " TOP: %d\n", ((status >> 11) & 7));
148 }
149
150 /* Print the control word CONTROL. If CONTROL_P is false, then
151 CONTROL was unavailable. */
152
153 static void
154 print_i387_control_word (int control_p,
155 unsigned int control, struct ui_file *file)
156 {
157 fprintf_filtered (file, "Control Word: ");
158 if (!control_p)
159 {
160 fprintf_filtered (file, "%s\n", _("<unavailable>"));
161 return;
162 }
163
164 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
165 fputs_filtered (" ", file);
166 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
167 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
168 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
169 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
172
173 fputs_filtered ("\n", file);
174
175 fputs_filtered (" PC: ", file);
176 switch ((control >> 8) & 3)
177 {
178 case 0:
179 fputs_filtered ("Single Precision (24-bits)\n", file);
180 break;
181 case 1:
182 fputs_filtered ("Reserved\n", file);
183 break;
184 case 2:
185 fputs_filtered ("Double Precision (53-bits)\n", file);
186 break;
187 case 3:
188 fputs_filtered ("Extended Precision (64-bits)\n", file);
189 break;
190 }
191
192 fputs_filtered (" RC: ", file);
193 switch ((control >> 10) & 3)
194 {
195 case 0:
196 fputs_filtered ("Round to nearest\n", file);
197 break;
198 case 1:
199 fputs_filtered ("Round down\n", file);
200 break;
201 case 2:
202 fputs_filtered ("Round up\n", file);
203 break;
204 case 3:
205 fputs_filtered ("Round toward zero\n", file);
206 break;
207 }
208 }
209
210 /* Print out the i387 floating point state. Note that we ignore FRAME
211 in the code below. That's OK since floating-point registers are
212 never saved on the stack. */
213
214 void
215 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
216 struct frame_info *frame, const char *args)
217 {
218 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
219 ULONGEST fctrl;
220 int fctrl_p;
221 ULONGEST fstat;
222 int fstat_p;
223 ULONGEST ftag;
224 int ftag_p;
225 ULONGEST fiseg;
226 int fiseg_p;
227 ULONGEST fioff;
228 int fioff_p;
229 ULONGEST foseg;
230 int foseg_p;
231 ULONGEST fooff;
232 int fooff_p;
233 ULONGEST fop;
234 int fop_p;
235 int fpreg;
236 int top;
237
238 gdb_assert (gdbarch == get_frame_arch (frame));
239
240 fctrl_p = read_frame_register_unsigned (frame,
241 I387_FCTRL_REGNUM (tdep), &fctrl);
242 fstat_p = read_frame_register_unsigned (frame,
243 I387_FSTAT_REGNUM (tdep), &fstat);
244 ftag_p = read_frame_register_unsigned (frame,
245 I387_FTAG_REGNUM (tdep), &ftag);
246 fiseg_p = read_frame_register_unsigned (frame,
247 I387_FISEG_REGNUM (tdep), &fiseg);
248 fioff_p = read_frame_register_unsigned (frame,
249 I387_FIOFF_REGNUM (tdep), &fioff);
250 foseg_p = read_frame_register_unsigned (frame,
251 I387_FOSEG_REGNUM (tdep), &foseg);
252 fooff_p = read_frame_register_unsigned (frame,
253 I387_FOOFF_REGNUM (tdep), &fooff);
254 fop_p = read_frame_register_unsigned (frame,
255 I387_FOP_REGNUM (tdep), &fop);
256
257 if (fstat_p)
258 {
259 top = ((fstat >> 11) & 7);
260
261 for (fpreg = 7; fpreg >= 0; fpreg--)
262 {
263 struct value *regval;
264 int regnum;
265 int i;
266 int tag = -1;
267
268 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
269
270 if (ftag_p)
271 {
272 tag = (ftag >> (fpreg * 2)) & 3;
273
274 switch (tag)
275 {
276 case 0:
277 fputs_filtered ("Valid ", file);
278 break;
279 case 1:
280 fputs_filtered ("Zero ", file);
281 break;
282 case 2:
283 fputs_filtered ("Special ", file);
284 break;
285 case 3:
286 fputs_filtered ("Empty ", file);
287 break;
288 }
289 }
290 else
291 fputs_filtered ("Unknown ", file);
292
293 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
294 regval = get_frame_register_value (frame, regnum);
295
296 if (value_entirely_available (regval))
297 {
298 const gdb_byte *raw = value_contents (regval);
299
300 fputs_filtered ("0x", file);
301 for (i = 9; i >= 0; i--)
302 fprintf_filtered (file, "%02x", raw[i]);
303
304 if (tag != -1 && tag != 3)
305 print_i387_ext (gdbarch, raw, file);
306 }
307 else
308 fprintf_filtered (file, "%s", _("<unavailable>"));
309
310 fputs_filtered ("\n", file);
311 }
312 }
313
314 fputs_filtered ("\n", file);
315 print_i387_status_word (fstat_p, fstat, file);
316 print_i387_control_word (fctrl_p, fctrl, file);
317 fprintf_filtered (file, "Tag Word: %s\n",
318 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
319 fprintf_filtered (file, "Instruction Pointer: %s:",
320 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
321 fprintf_filtered (file, "%s\n",
322 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
323 fprintf_filtered (file, "Operand Pointer: %s:",
324 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
325 fprintf_filtered (file, "%s\n",
326 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
327 fprintf_filtered (file, "Opcode: %s\n",
328 fop_p
329 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
330 : _("<unavailable>"));
331 }
332 \f
333
334 /* Return nonzero if a value of type TYPE stored in register REGNUM
335 needs any special handling. */
336
337 int
338 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
339 struct type *type)
340 {
341 if (i386_fp_regnum_p (gdbarch, regnum))
342 {
343 /* Floating point registers must be converted unless we are
344 accessing them in their hardware type. */
345 if (type == i387_ext_type (gdbarch))
346 return 0;
347 else
348 return 1;
349 }
350
351 return 0;
352 }
353
354 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
355 return its contents in TO. */
356
357 int
358 i387_register_to_value (struct frame_info *frame, int regnum,
359 struct type *type, gdb_byte *to,
360 int *optimizedp, int *unavailablep)
361 {
362 struct gdbarch *gdbarch = get_frame_arch (frame);
363 gdb_byte from[I386_MAX_REGISTER_SIZE];
364
365 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
366
367 /* We only support floating-point values. */
368 if (TYPE_CODE (type) != TYPE_CODE_FLT)
369 {
370 warning (_("Cannot convert floating-point register value "
371 "to non-floating-point type."));
372 *optimizedp = *unavailablep = 0;
373 return 0;
374 }
375
376 /* Convert to TYPE. */
377 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
378 from, optimizedp, unavailablep))
379 return 0;
380
381 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
382 *optimizedp = *unavailablep = 0;
383 return 1;
384 }
385
386 /* Write the contents FROM of a value of type TYPE into register
387 REGNUM in frame FRAME. */
388
389 void
390 i387_value_to_register (struct frame_info *frame, int regnum,
391 struct type *type, const gdb_byte *from)
392 {
393 struct gdbarch *gdbarch = get_frame_arch (frame);
394 gdb_byte to[I386_MAX_REGISTER_SIZE];
395
396 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
397
398 /* We only support floating-point values. */
399 if (TYPE_CODE (type) != TYPE_CODE_FLT)
400 {
401 warning (_("Cannot convert non-floating-point type "
402 "to floating-point register value."));
403 return;
404 }
405
406 /* Convert from TYPE. */
407 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
408 put_frame_register (frame, regnum, to);
409 }
410 \f
411
412 /* Handle FSAVE and FXSAVE formats. */
413
414 /* At fsave_offset[REGNUM] you'll find the offset to the location in
415 the data structure used by the "fsave" instruction where GDB
416 register REGNUM is stored. */
417
418 static int fsave_offset[] =
419 {
420 28 + 0 * 10, /* %st(0) ... */
421 28 + 1 * 10,
422 28 + 2 * 10,
423 28 + 3 * 10,
424 28 + 4 * 10,
425 28 + 5 * 10,
426 28 + 6 * 10,
427 28 + 7 * 10, /* ... %st(7). */
428 0, /* `fctrl' (16 bits). */
429 4, /* `fstat' (16 bits). */
430 8, /* `ftag' (16 bits). */
431 16, /* `fiseg' (16 bits). */
432 12, /* `fioff'. */
433 24, /* `foseg' (16 bits). */
434 20, /* `fooff'. */
435 18 /* `fop' (bottom 11 bits). */
436 };
437
438 #define FSAVE_ADDR(tdep, fsave, regnum) \
439 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
440 \f
441
442 /* Fill register REGNUM in REGCACHE with the appropriate value from
443 *FSAVE. This function masks off any of the reserved bits in
444 *FSAVE. */
445
446 void
447 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
448 {
449 struct gdbarch *gdbarch = get_regcache_arch (regcache);
450 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
451 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
452 const gdb_byte *regs = (const gdb_byte *) fsave;
453 int i;
454
455 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
456
457 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
458 if (regnum == -1 || regnum == i)
459 {
460 if (fsave == NULL)
461 {
462 regcache_raw_supply (regcache, i, NULL);
463 continue;
464 }
465
466 /* Most of the FPU control registers occupy only 16 bits in the
467 fsave area. Give those a special treatment. */
468 if (i >= I387_FCTRL_REGNUM (tdep)
469 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
470 {
471 gdb_byte val[4];
472
473 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
474 val[2] = val[3] = 0;
475 if (i == I387_FOP_REGNUM (tdep))
476 val[1] &= ((1 << 3) - 1);
477 regcache_raw_supply (regcache, i, val);
478 }
479 else
480 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
481 }
482
483 /* Provide dummy values for the SSE registers. */
484 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
485 if (regnum == -1 || regnum == i)
486 regcache_raw_supply (regcache, i, NULL);
487 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
488 {
489 gdb_byte buf[4];
490
491 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
492 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
493 }
494 }
495
496 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
497 with the value from REGCACHE. If REGNUM is -1, do this for all
498 registers. This function doesn't touch any of the reserved bits in
499 *FSAVE. */
500
501 void
502 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
503 {
504 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
505 gdb_byte *regs = (gdb_byte *) fsave;
506 int i;
507
508 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
509
510 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
511 if (regnum == -1 || regnum == i)
512 {
513 /* Most of the FPU control registers occupy only 16 bits in
514 the fsave area. Give those a special treatment. */
515 if (i >= I387_FCTRL_REGNUM (tdep)
516 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
517 {
518 gdb_byte buf[4];
519
520 regcache_raw_collect (regcache, i, buf);
521
522 if (i == I387_FOP_REGNUM (tdep))
523 {
524 /* The opcode occupies only 11 bits. Make sure we
525 don't touch the other bits. */
526 buf[1] &= ((1 << 3) - 1);
527 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
528 }
529 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
530 }
531 else
532 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
533 }
534 }
535 \f
536
537 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
538 the data structure used by the "fxsave" instruction where GDB
539 register REGNUM is stored. */
540
541 static int fxsave_offset[] =
542 {
543 32, /* %st(0) through ... */
544 48,
545 64,
546 80,
547 96,
548 112,
549 128,
550 144, /* ... %st(7) (80 bits each). */
551 0, /* `fctrl' (16 bits). */
552 2, /* `fstat' (16 bits). */
553 4, /* `ftag' (16 bits). */
554 12, /* `fiseg' (16 bits). */
555 8, /* `fioff'. */
556 20, /* `foseg' (16 bits). */
557 16, /* `fooff'. */
558 6, /* `fop' (bottom 11 bits). */
559 160 + 0 * 16, /* %xmm0 through ... */
560 160 + 1 * 16,
561 160 + 2 * 16,
562 160 + 3 * 16,
563 160 + 4 * 16,
564 160 + 5 * 16,
565 160 + 6 * 16,
566 160 + 7 * 16,
567 160 + 8 * 16,
568 160 + 9 * 16,
569 160 + 10 * 16,
570 160 + 11 * 16,
571 160 + 12 * 16,
572 160 + 13 * 16,
573 160 + 14 * 16,
574 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
575 };
576
577 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
578 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
579
580 /* We made an unfortunate choice in putting %mxcsr after the SSE
581 registers %xmm0-%xmm7 instead of before, since it makes supporting
582 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
583 don't include the offset for %mxcsr here above. */
584
585 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
586
587 static int i387_tag (const gdb_byte *raw);
588 \f
589
590 /* Fill register REGNUM in REGCACHE with the appropriate
591 floating-point or SSE register value from *FXSAVE. This function
592 masks off any of the reserved bits in *FXSAVE. */
593
594 void
595 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
596 {
597 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
598 const gdb_byte *regs = (const gdb_byte *) fxsave;
599 int i;
600
601 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
602 gdb_assert (tdep->num_xmm_regs > 0);
603
604 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
605 if (regnum == -1 || regnum == i)
606 {
607 if (regs == NULL)
608 {
609 regcache_raw_supply (regcache, i, NULL);
610 continue;
611 }
612
613 /* Most of the FPU control registers occupy only 16 bits in
614 the fxsave area. Give those a special treatment. */
615 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
616 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
617 {
618 gdb_byte val[4];
619
620 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
621 val[2] = val[3] = 0;
622 if (i == I387_FOP_REGNUM (tdep))
623 val[1] &= ((1 << 3) - 1);
624 else if (i== I387_FTAG_REGNUM (tdep))
625 {
626 /* The fxsave area contains a simplified version of
627 the tag word. We have to look at the actual 80-bit
628 FP data to recreate the traditional i387 tag word. */
629
630 unsigned long ftag = 0;
631 int fpreg;
632 int top;
633
634 top = ((FXSAVE_ADDR (tdep, regs,
635 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
636 top &= 0x7;
637
638 for (fpreg = 7; fpreg >= 0; fpreg--)
639 {
640 int tag;
641
642 if (val[0] & (1 << fpreg))
643 {
644 int thisreg = (fpreg + 8 - top) % 8
645 + I387_ST0_REGNUM (tdep);
646 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
647 }
648 else
649 tag = 3; /* Empty */
650
651 ftag |= tag << (2 * fpreg);
652 }
653 val[0] = ftag & 0xff;
654 val[1] = (ftag >> 8) & 0xff;
655 }
656 regcache_raw_supply (regcache, i, val);
657 }
658 else
659 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
660 }
661
662 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
663 {
664 if (regs == NULL)
665 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
666 else
667 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
668 FXSAVE_MXCSR_ADDR (regs));
669 }
670 }
671
672 /* Fill register REGNUM (if it is a floating-point or SSE register) in
673 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
674 all registers. This function doesn't touch any of the reserved
675 bits in *FXSAVE. */
676
677 void
678 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
679 {
680 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
681 gdb_byte *regs = (gdb_byte *) fxsave;
682 int i;
683
684 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
685 gdb_assert (tdep->num_xmm_regs > 0);
686
687 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
688 if (regnum == -1 || regnum == i)
689 {
690 /* Most of the FPU control registers occupy only 16 bits in
691 the fxsave area. Give those a special treatment. */
692 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
693 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
694 {
695 gdb_byte buf[4];
696
697 regcache_raw_collect (regcache, i, buf);
698
699 if (i == I387_FOP_REGNUM (tdep))
700 {
701 /* The opcode occupies only 11 bits. Make sure we
702 don't touch the other bits. */
703 buf[1] &= ((1 << 3) - 1);
704 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
705 }
706 else if (i == I387_FTAG_REGNUM (tdep))
707 {
708 /* Converting back is much easier. */
709
710 unsigned short ftag;
711 int fpreg;
712
713 ftag = (buf[1] << 8) | buf[0];
714 buf[0] = 0;
715 buf[1] = 0;
716
717 for (fpreg = 7; fpreg >= 0; fpreg--)
718 {
719 int tag = (ftag >> (fpreg * 2)) & 3;
720
721 if (tag != 3)
722 buf[0] |= (1 << fpreg);
723 }
724 }
725 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
726 }
727 else
728 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
729 }
730
731 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
732 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
733 FXSAVE_MXCSR_ADDR (regs));
734 }
735
736 /* `xstate_bv' is at byte offset 512. */
737 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
738
739 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
740 the upper 128bit of AVX register data structure used by the "xsave"
741 instruction where GDB register REGNUM is stored. */
742
743 static int xsave_avxh_offset[] =
744 {
745 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
746 576 + 1 * 16,
747 576 + 2 * 16,
748 576 + 3 * 16,
749 576 + 4 * 16,
750 576 + 5 * 16,
751 576 + 6 * 16,
752 576 + 7 * 16,
753 576 + 8 * 16,
754 576 + 9 * 16,
755 576 + 10 * 16,
756 576 + 11 * 16,
757 576 + 12 * 16,
758 576 + 13 * 16,
759 576 + 14 * 16,
760 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
761 };
762
763 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
764 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
765
766 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
767 the upper 128bit of ZMM register data structure used by the "xsave"
768 instruction where GDB register REGNUM is stored. */
769
770 static int xsave_ymm_avx512_offset[] =
771 {
772 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
773 1664 + 16 + 0 * 64, /* %ymm16 through... */
774 1664 + 16 + 1 * 64,
775 1664 + 16 + 2 * 64,
776 1664 + 16 + 3 * 64,
777 1664 + 16 + 4 * 64,
778 1664 + 16 + 5 * 64,
779 1664 + 16 + 6 * 64,
780 1664 + 16 + 7 * 64,
781 1664 + 16 + 8 * 64,
782 1664 + 16 + 9 * 64,
783 1664 + 16 + 10 * 64,
784 1664 + 16 + 11 * 64,
785 1664 + 16 + 12 * 64,
786 1664 + 16 + 13 * 64,
787 1664 + 16 + 14 * 64,
788 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
789 };
790
791 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
792 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
793
794 static int xsave_xmm_avx512_offset[] =
795 {
796 1664 + 0 * 64, /* %ymm16 through... */
797 1664 + 1 * 64,
798 1664 + 2 * 64,
799 1664 + 3 * 64,
800 1664 + 4 * 64,
801 1664 + 5 * 64,
802 1664 + 6 * 64,
803 1664 + 7 * 64,
804 1664 + 8 * 64,
805 1664 + 9 * 64,
806 1664 + 10 * 64,
807 1664 + 11 * 64,
808 1664 + 12 * 64,
809 1664 + 13 * 64,
810 1664 + 14 * 64,
811 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
812 };
813
814 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
815 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
816
817 static int xsave_mpx_offset[] = {
818 960 + 0 * 16, /* bnd0r...bnd3r registers. */
819 960 + 1 * 16,
820 960 + 2 * 16,
821 960 + 3 * 16,
822 1024 + 0 * 8, /* bndcfg ... bndstatus. */
823 1024 + 1 * 8,
824 };
825
826 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
827 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
828
829 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
830 of the AVX512 opmask register data structure used by the "xsave"
831 instruction where GDB register REGNUM is stored. */
832
833 static int xsave_avx512_k_offset[] =
834 {
835 1088 + 0 * 8, /* %k0 through... */
836 1088 + 1 * 8,
837 1088 + 2 * 8,
838 1088 + 3 * 8,
839 1088 + 4 * 8,
840 1088 + 5 * 8,
841 1088 + 6 * 8,
842 1088 + 7 * 8 /* %k7 (64 bits each). */
843 };
844
845 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
846 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
847
848 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
849 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
850 instruction where GDB register REGNUM is stored. */
851
852 static int xsave_avx512_zmm_h_offset[] =
853 {
854 1152 + 0 * 32,
855 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
856 1152 + 2 * 32,
857 1152 + 3 * 32,
858 1152 + 4 * 32,
859 1152 + 5 * 32,
860 1152 + 6 * 32,
861 1152 + 7 * 32,
862 1152 + 8 * 32,
863 1152 + 9 * 32,
864 1152 + 10 * 32,
865 1152 + 11 * 32,
866 1152 + 12 * 32,
867 1152 + 13 * 32,
868 1152 + 14 * 32,
869 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
870 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
871 1664 + 32 + 1 * 64,
872 1664 + 32 + 2 * 64,
873 1664 + 32 + 3 * 64,
874 1664 + 32 + 4 * 64,
875 1664 + 32 + 5 * 64,
876 1664 + 32 + 6 * 64,
877 1664 + 32 + 7 * 64,
878 1664 + 32 + 8 * 64,
879 1664 + 32 + 9 * 64,
880 1664 + 32 + 10 * 64,
881 1664 + 32 + 11 * 64,
882 1664 + 32 + 12 * 64,
883 1664 + 32 + 13 * 64,
884 1664 + 32 + 14 * 64,
885 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
886 };
887
888 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
889 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
890
891 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
892
893 void
894 i387_supply_xsave (struct regcache *regcache, int regnum,
895 const void *xsave)
896 {
897 struct gdbarch *gdbarch = get_regcache_arch (regcache);
898 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
899 const gdb_byte *regs = (const gdb_byte *) xsave;
900 int i;
901 unsigned int clear_bv;
902 static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 };
903 enum
904 {
905 none = 0x0,
906 x87 = 0x1,
907 sse = 0x2,
908 avxh = 0x4,
909 mpx = 0x8,
910 avx512_k = 0x10,
911 avx512_zmm_h = 0x20,
912 avx512_ymmh_avx512 = 0x40,
913 avx512_xmm_avx512 = 0x80,
914 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
915 | avx512_ymmh_avx512 | avx512_xmm_avx512
916 } regclass;
917
918 gdb_assert (regs != NULL);
919 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
920 gdb_assert (tdep->num_xmm_regs > 0);
921
922 if (regnum == -1)
923 regclass = all;
924 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
925 && regnum < I387_ZMMENDH_REGNUM (tdep))
926 regclass = avx512_zmm_h;
927 else if (regnum >= I387_K0_REGNUM (tdep)
928 && regnum < I387_KEND_REGNUM (tdep))
929 regclass = avx512_k;
930 else if (regnum >= I387_YMM16H_REGNUM (tdep)
931 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
932 regclass = avx512_ymmh_avx512;
933 else if (regnum >= I387_XMM16_REGNUM (tdep)
934 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
935 regclass = avx512_xmm_avx512;
936 else if (regnum >= I387_YMM0H_REGNUM (tdep)
937 && regnum < I387_YMMENDH_REGNUM (tdep))
938 regclass = avxh;
939 else if (regnum >= I387_BND0R_REGNUM (tdep)
940 && regnum < I387_MPXEND_REGNUM (tdep))
941 regclass = mpx;
942 else if (regnum >= I387_XMM0_REGNUM (tdep)
943 && regnum < I387_MXCSR_REGNUM (tdep))
944 regclass = sse;
945 else if (regnum >= I387_ST0_REGNUM (tdep)
946 && regnum < I387_FCTRL_REGNUM (tdep))
947 regclass = x87;
948 else
949 regclass = none;
950
951 if (regclass != none)
952 {
953 /* Get `xstat_bv'. */
954 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
955
956 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
957 vector registers if its bit in xstat_bv is zero. */
958 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
959 }
960 else
961 clear_bv = X86_XSTATE_ALL_MASK;
962
963 /* With the delayed xsave mechanism, in between the program
964 starting, and the program accessing the vector registers for the
965 first time, the register's values are invalid. The kernel
966 initializes register states to zero when they are set the first
967 time in a program. This means that from the user-space programs'
968 perspective, it's the same as if the registers have always been
969 zero from the start of the program. Therefore, the debugger
970 should provide the same illusion to the user. */
971
972 switch (regclass)
973 {
974 case none:
975 break;
976
977 case avx512_zmm_h:
978 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
979 regcache_raw_supply (regcache, regnum, zero);
980 else
981 regcache_raw_supply (regcache, regnum,
982 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
983 return;
984
985 case avx512_k:
986 if ((clear_bv & X86_XSTATE_K))
987 regcache_raw_supply (regcache, regnum, zero);
988 else
989 regcache_raw_supply (regcache, regnum,
990 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
991 return;
992
993 case avx512_ymmh_avx512:
994 if ((clear_bv & X86_XSTATE_ZMM))
995 regcache_raw_supply (regcache, regnum, zero);
996 else
997 regcache_raw_supply (regcache, regnum,
998 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
999 return;
1000
1001 case avx512_xmm_avx512:
1002 if ((clear_bv & X86_XSTATE_ZMM))
1003 regcache_raw_supply (regcache, regnum, zero);
1004 else
1005 regcache_raw_supply (regcache, regnum,
1006 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1007 return;
1008
1009 case avxh:
1010 if ((clear_bv & X86_XSTATE_AVX))
1011 regcache_raw_supply (regcache, regnum, zero);
1012 else
1013 regcache_raw_supply (regcache, regnum,
1014 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1015 return;
1016
1017 case mpx:
1018 if ((clear_bv & X86_XSTATE_BNDREGS))
1019 regcache_raw_supply (regcache, regnum, zero);
1020 else
1021 regcache_raw_supply (regcache, regnum,
1022 XSAVE_MPX_ADDR (tdep, regs, regnum));
1023 return;
1024
1025 case sse:
1026 if ((clear_bv & X86_XSTATE_SSE))
1027 regcache_raw_supply (regcache, regnum, zero);
1028 else
1029 regcache_raw_supply (regcache, regnum,
1030 FXSAVE_ADDR (tdep, regs, regnum));
1031 return;
1032
1033 case x87:
1034 if ((clear_bv & X86_XSTATE_X87))
1035 regcache_raw_supply (regcache, regnum, zero);
1036 else
1037 regcache_raw_supply (regcache, regnum,
1038 FXSAVE_ADDR (tdep, regs, regnum));
1039 return;
1040
1041 case all:
1042 /* Handle the upper ZMM registers. */
1043 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1044 {
1045 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1046 {
1047 for (i = I387_ZMM0H_REGNUM (tdep);
1048 i < I387_ZMMENDH_REGNUM (tdep);
1049 i++)
1050 regcache_raw_supply (regcache, i, zero);
1051 }
1052 else
1053 {
1054 for (i = I387_ZMM0H_REGNUM (tdep);
1055 i < I387_ZMMENDH_REGNUM (tdep);
1056 i++)
1057 regcache_raw_supply (regcache, i,
1058 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1059 }
1060 }
1061
1062 /* Handle AVX512 OpMask registers. */
1063 if ((tdep->xcr0 & X86_XSTATE_K))
1064 {
1065 if ((clear_bv & X86_XSTATE_K))
1066 {
1067 for (i = I387_K0_REGNUM (tdep);
1068 i < I387_KEND_REGNUM (tdep);
1069 i++)
1070 regcache_raw_supply (regcache, i, zero);
1071 }
1072 else
1073 {
1074 for (i = I387_K0_REGNUM (tdep);
1075 i < I387_KEND_REGNUM (tdep);
1076 i++)
1077 regcache_raw_supply (regcache, i,
1078 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1079 }
1080 }
1081
1082 /* Handle the YMM_AVX512 registers. */
1083 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1084 {
1085 if ((clear_bv & X86_XSTATE_ZMM))
1086 {
1087 for (i = I387_YMM16H_REGNUM (tdep);
1088 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1089 i++)
1090 regcache_raw_supply (regcache, i, zero);
1091 for (i = I387_XMM16_REGNUM (tdep);
1092 i < I387_XMM_AVX512_END_REGNUM (tdep);
1093 i++)
1094 regcache_raw_supply (regcache, i, zero);
1095 }
1096 else
1097 {
1098 for (i = I387_YMM16H_REGNUM (tdep);
1099 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1100 i++)
1101 regcache_raw_supply (regcache, i,
1102 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1103 for (i = I387_XMM16_REGNUM (tdep);
1104 i < I387_XMM_AVX512_END_REGNUM (tdep);
1105 i++)
1106 regcache_raw_supply (regcache, i,
1107 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1108 }
1109 }
1110 /* Handle the upper YMM registers. */
1111 if ((tdep->xcr0 & X86_XSTATE_AVX))
1112 {
1113 if ((clear_bv & X86_XSTATE_AVX))
1114 {
1115 for (i = I387_YMM0H_REGNUM (tdep);
1116 i < I387_YMMENDH_REGNUM (tdep);
1117 i++)
1118 regcache_raw_supply (regcache, i, zero);
1119 }
1120 else
1121 {
1122 for (i = I387_YMM0H_REGNUM (tdep);
1123 i < I387_YMMENDH_REGNUM (tdep);
1124 i++)
1125 regcache_raw_supply (regcache, i,
1126 XSAVE_AVXH_ADDR (tdep, regs, i));
1127 }
1128 }
1129
1130 /* Handle the MPX registers. */
1131 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1132 {
1133 if (clear_bv & X86_XSTATE_BNDREGS)
1134 {
1135 for (i = I387_BND0R_REGNUM (tdep);
1136 i < I387_BNDCFGU_REGNUM (tdep); i++)
1137 regcache_raw_supply (regcache, i, zero);
1138 }
1139 else
1140 {
1141 for (i = I387_BND0R_REGNUM (tdep);
1142 i < I387_BNDCFGU_REGNUM (tdep); i++)
1143 regcache_raw_supply (regcache, i,
1144 XSAVE_MPX_ADDR (tdep, regs, i));
1145 }
1146 }
1147
1148 /* Handle the MPX registers. */
1149 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1150 {
1151 if (clear_bv & X86_XSTATE_BNDCFG)
1152 {
1153 for (i = I387_BNDCFGU_REGNUM (tdep);
1154 i < I387_MPXEND_REGNUM (tdep); i++)
1155 regcache_raw_supply (regcache, i, zero);
1156 }
1157 else
1158 {
1159 for (i = I387_BNDCFGU_REGNUM (tdep);
1160 i < I387_MPXEND_REGNUM (tdep); i++)
1161 regcache_raw_supply (regcache, i,
1162 XSAVE_MPX_ADDR (tdep, regs, i));
1163 }
1164 }
1165
1166 /* Handle the XMM registers. */
1167 if ((tdep->xcr0 & X86_XSTATE_SSE))
1168 {
1169 if ((clear_bv & X86_XSTATE_SSE))
1170 {
1171 for (i = I387_XMM0_REGNUM (tdep);
1172 i < I387_MXCSR_REGNUM (tdep);
1173 i++)
1174 regcache_raw_supply (regcache, i, zero);
1175 }
1176 else
1177 {
1178 for (i = I387_XMM0_REGNUM (tdep);
1179 i < I387_MXCSR_REGNUM (tdep); i++)
1180 regcache_raw_supply (regcache, i,
1181 FXSAVE_ADDR (tdep, regs, i));
1182 }
1183 }
1184
1185 /* Handle the x87 registers. */
1186 if ((tdep->xcr0 & X86_XSTATE_X87))
1187 {
1188 if ((clear_bv & X86_XSTATE_X87))
1189 {
1190 for (i = I387_ST0_REGNUM (tdep);
1191 i < I387_FCTRL_REGNUM (tdep);
1192 i++)
1193 regcache_raw_supply (regcache, i, zero);
1194 }
1195 else
1196 {
1197 for (i = I387_ST0_REGNUM (tdep);
1198 i < I387_FCTRL_REGNUM (tdep);
1199 i++)
1200 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1201 }
1202 }
1203 break;
1204 }
1205
1206 /* Only handle x87 control registers. */
1207 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1208 if (regnum == -1 || regnum == i)
1209 {
1210 /* Most of the FPU control registers occupy only 16 bits in
1211 the xsave extended state. Give those a special treatment. */
1212 if (i != I387_FIOFF_REGNUM (tdep)
1213 && i != I387_FOOFF_REGNUM (tdep))
1214 {
1215 gdb_byte val[4];
1216
1217 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1218 val[2] = val[3] = 0;
1219 if (i == I387_FOP_REGNUM (tdep))
1220 val[1] &= ((1 << 3) - 1);
1221 else if (i== I387_FTAG_REGNUM (tdep))
1222 {
1223 /* The fxsave area contains a simplified version of
1224 the tag word. We have to look at the actual 80-bit
1225 FP data to recreate the traditional i387 tag word. */
1226
1227 unsigned long ftag = 0;
1228 int fpreg;
1229 int top;
1230
1231 top = ((FXSAVE_ADDR (tdep, regs,
1232 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1233 top &= 0x7;
1234
1235 for (fpreg = 7; fpreg >= 0; fpreg--)
1236 {
1237 int tag;
1238
1239 if (val[0] & (1 << fpreg))
1240 {
1241 int thisreg = (fpreg + 8 - top) % 8
1242 + I387_ST0_REGNUM (tdep);
1243 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1244 }
1245 else
1246 tag = 3; /* Empty */
1247
1248 ftag |= tag << (2 * fpreg);
1249 }
1250 val[0] = ftag & 0xff;
1251 val[1] = (ftag >> 8) & 0xff;
1252 }
1253 regcache_raw_supply (regcache, i, val);
1254 }
1255 else
1256 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1257 }
1258
1259 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1260 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1261 FXSAVE_MXCSR_ADDR (regs));
1262 }
1263
1264 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1265
1266 void
1267 i387_collect_xsave (const struct regcache *regcache, int regnum,
1268 void *xsave, int gcore)
1269 {
1270 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1271 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1272 gdb_byte *regs = (gdb_byte *) xsave;
1273 int i;
1274 enum
1275 {
1276 none = 0x0,
1277 check = 0x1,
1278 x87 = 0x2 | check,
1279 sse = 0x4 | check,
1280 avxh = 0x8 | check,
1281 mpx = 0x10 | check,
1282 avx512_k = 0x20 | check,
1283 avx512_zmm_h = 0x40 | check,
1284 avx512_ymmh_avx512 = 0x80 | check,
1285 avx512_xmm_avx512 = 0x100 | check,
1286 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1287 | avx512_ymmh_avx512 | avx512_xmm_avx512
1288 } regclass;
1289
1290 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1291 gdb_assert (tdep->num_xmm_regs > 0);
1292
1293 if (regnum == -1)
1294 regclass = all;
1295 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1296 && regnum < I387_ZMMENDH_REGNUM (tdep))
1297 regclass = avx512_zmm_h;
1298 else if (regnum >= I387_K0_REGNUM (tdep)
1299 && regnum < I387_KEND_REGNUM (tdep))
1300 regclass = avx512_k;
1301 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1302 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1303 regclass = avx512_ymmh_avx512;
1304 else if (regnum >= I387_XMM16_REGNUM (tdep)
1305 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1306 regclass = avx512_xmm_avx512;
1307 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1308 && regnum < I387_YMMENDH_REGNUM (tdep))
1309 regclass = avxh;
1310 else if (regnum >= I387_BND0R_REGNUM (tdep)
1311 && regnum < I387_MPXEND_REGNUM (tdep))
1312 regclass = mpx;
1313 else if (regnum >= I387_XMM0_REGNUM (tdep)
1314 && regnum < I387_MXCSR_REGNUM (tdep))
1315 regclass = sse;
1316 else if (regnum >= I387_ST0_REGNUM (tdep)
1317 && regnum < I387_FCTRL_REGNUM (tdep))
1318 regclass = x87;
1319 else
1320 regclass = none;
1321
1322 if (gcore)
1323 {
1324 /* Clear XSAVE extended state. */
1325 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
1326
1327 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1328 if (tdep->xsave_xcr0_offset != -1)
1329 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1330 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1331 }
1332
1333 if ((regclass & check))
1334 {
1335 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1336 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1337 unsigned int xstate_bv = 0;
1338 /* The supported bits in `xstat_bv' are 1 byte. */
1339 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1340 gdb_byte *p;
1341
1342 /* Clear register set if its bit in xstat_bv is zero. */
1343 if (clear_bv)
1344 {
1345 if ((clear_bv & X86_XSTATE_BNDREGS))
1346 for (i = I387_BND0R_REGNUM (tdep);
1347 i < I387_BNDCFGU_REGNUM (tdep); i++)
1348 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1349
1350 if ((clear_bv & X86_XSTATE_BNDCFG))
1351 for (i = I387_BNDCFGU_REGNUM (tdep);
1352 i < I387_MPXEND_REGNUM (tdep); i++)
1353 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1354
1355 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1356 for (i = I387_ZMM0H_REGNUM (tdep);
1357 i < I387_ZMMENDH_REGNUM (tdep); i++)
1358 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1359
1360 if ((clear_bv & X86_XSTATE_K))
1361 for (i = I387_K0_REGNUM (tdep);
1362 i < I387_KEND_REGNUM (tdep); i++)
1363 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1364
1365 if ((clear_bv & X86_XSTATE_ZMM))
1366 {
1367 for (i = I387_YMM16H_REGNUM (tdep);
1368 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1369 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1370 for (i = I387_XMM16_REGNUM (tdep);
1371 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1372 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1373 }
1374
1375 if ((clear_bv & X86_XSTATE_AVX))
1376 for (i = I387_YMM0H_REGNUM (tdep);
1377 i < I387_YMMENDH_REGNUM (tdep); i++)
1378 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1379
1380 if ((clear_bv & X86_XSTATE_SSE))
1381 for (i = I387_XMM0_REGNUM (tdep);
1382 i < I387_MXCSR_REGNUM (tdep); i++)
1383 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1384
1385 if ((clear_bv & X86_XSTATE_X87))
1386 for (i = I387_ST0_REGNUM (tdep);
1387 i < I387_FCTRL_REGNUM (tdep); i++)
1388 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1389 }
1390
1391 if (regclass == all)
1392 {
1393 /* Check if any ZMMH registers are changed. */
1394 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1395 for (i = I387_ZMM0H_REGNUM (tdep);
1396 i < I387_ZMMENDH_REGNUM (tdep); i++)
1397 {
1398 regcache_raw_collect (regcache, i, raw);
1399 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1400 if (memcmp (raw, p, 32) != 0)
1401 {
1402 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1403 memcpy (p, raw, 32);
1404 }
1405 }
1406
1407 /* Check if any K registers are changed. */
1408 if ((tdep->xcr0 & X86_XSTATE_K))
1409 for (i = I387_K0_REGNUM (tdep);
1410 i < I387_KEND_REGNUM (tdep); i++)
1411 {
1412 regcache_raw_collect (regcache, i, raw);
1413 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1414 if (memcmp (raw, p, 8) != 0)
1415 {
1416 xstate_bv |= X86_XSTATE_K;
1417 memcpy (p, raw, 8);
1418 }
1419 }
1420
1421 /* Check if any XMM or upper YMM registers are changed. */
1422 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1423 {
1424 for (i = I387_YMM16H_REGNUM (tdep);
1425 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1426 {
1427 regcache_raw_collect (regcache, i, raw);
1428 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1429 if (memcmp (raw, p, 16) != 0)
1430 {
1431 xstate_bv |= X86_XSTATE_ZMM;
1432 memcpy (p, raw, 16);
1433 }
1434 }
1435 for (i = I387_XMM16_REGNUM (tdep);
1436 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1437 {
1438 regcache_raw_collect (regcache, i, raw);
1439 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1440 if (memcmp (raw, p, 16) != 0)
1441 {
1442 xstate_bv |= X86_XSTATE_ZMM;
1443 memcpy (p, raw, 16);
1444 }
1445 }
1446 }
1447
1448 /* Check if any upper YMM registers are changed. */
1449 if ((tdep->xcr0 & X86_XSTATE_AVX))
1450 for (i = I387_YMM0H_REGNUM (tdep);
1451 i < I387_YMMENDH_REGNUM (tdep); i++)
1452 {
1453 regcache_raw_collect (regcache, i, raw);
1454 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1455 if (memcmp (raw, p, 16))
1456 {
1457 xstate_bv |= X86_XSTATE_AVX;
1458 memcpy (p, raw, 16);
1459 }
1460 }
1461 /* Check if any upper MPX registers are changed. */
1462 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1463 for (i = I387_BND0R_REGNUM (tdep);
1464 i < I387_BNDCFGU_REGNUM (tdep); i++)
1465 {
1466 regcache_raw_collect (regcache, i, raw);
1467 p = XSAVE_MPX_ADDR (tdep, regs, i);
1468 if (memcmp (raw, p, 16))
1469 {
1470 xstate_bv |= X86_XSTATE_BNDREGS;
1471 memcpy (p, raw, 16);
1472 }
1473 }
1474
1475 /* Check if any upper MPX registers are changed. */
1476 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1477 for (i = I387_BNDCFGU_REGNUM (tdep);
1478 i < I387_MPXEND_REGNUM (tdep); i++)
1479 {
1480 regcache_raw_collect (regcache, i, raw);
1481 p = XSAVE_MPX_ADDR (tdep, regs, i);
1482 if (memcmp (raw, p, 8))
1483 {
1484 xstate_bv |= X86_XSTATE_BNDCFG;
1485 memcpy (p, raw, 8);
1486 }
1487 }
1488
1489 /* Check if any SSE registers are changed. */
1490 if ((tdep->xcr0 & X86_XSTATE_SSE))
1491 for (i = I387_XMM0_REGNUM (tdep);
1492 i < I387_MXCSR_REGNUM (tdep); i++)
1493 {
1494 regcache_raw_collect (regcache, i, raw);
1495 p = FXSAVE_ADDR (tdep, regs, i);
1496 if (memcmp (raw, p, 16))
1497 {
1498 xstate_bv |= X86_XSTATE_SSE;
1499 memcpy (p, raw, 16);
1500 }
1501 }
1502
1503 /* Check if any X87 registers are changed. */
1504 if ((tdep->xcr0 & X86_XSTATE_X87))
1505 for (i = I387_ST0_REGNUM (tdep);
1506 i < I387_FCTRL_REGNUM (tdep); i++)
1507 {
1508 regcache_raw_collect (regcache, i, raw);
1509 p = FXSAVE_ADDR (tdep, regs, i);
1510 if (memcmp (raw, p, 10))
1511 {
1512 xstate_bv |= X86_XSTATE_X87;
1513 memcpy (p, raw, 10);
1514 }
1515 }
1516 }
1517 else
1518 {
1519 /* Check if REGNUM is changed. */
1520 regcache_raw_collect (regcache, regnum, raw);
1521
1522 switch (regclass)
1523 {
1524 default:
1525 internal_error (__FILE__, __LINE__,
1526 _("invalid i387 regclass"));
1527
1528 case avx512_zmm_h:
1529 /* This is a ZMM register. */
1530 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1531 if (memcmp (raw, p, 32) != 0)
1532 {
1533 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1534 memcpy (p, raw, 32);
1535 }
1536 break;
1537 case avx512_k:
1538 /* This is a AVX512 mask register. */
1539 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1540 if (memcmp (raw, p, 8) != 0)
1541 {
1542 xstate_bv |= X86_XSTATE_K;
1543 memcpy (p, raw, 8);
1544 }
1545 break;
1546
1547 case avx512_ymmh_avx512:
1548 /* This is an upper YMM16-31 register. */
1549 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1550 if (memcmp (raw, p, 16) != 0)
1551 {
1552 xstate_bv |= X86_XSTATE_ZMM;
1553 memcpy (p, raw, 16);
1554 }
1555 break;
1556
1557 case avx512_xmm_avx512:
1558 /* This is an upper XMM16-31 register. */
1559 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1560 if (memcmp (raw, p, 16) != 0)
1561 {
1562 xstate_bv |= X86_XSTATE_ZMM;
1563 memcpy (p, raw, 16);
1564 }
1565 break;
1566
1567 case avxh:
1568 /* This is an upper YMM register. */
1569 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1570 if (memcmp (raw, p, 16))
1571 {
1572 xstate_bv |= X86_XSTATE_AVX;
1573 memcpy (p, raw, 16);
1574 }
1575 break;
1576
1577 case mpx:
1578 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1579 {
1580 regcache_raw_collect (regcache, regnum, raw);
1581 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1582 if (memcmp (raw, p, 16))
1583 {
1584 xstate_bv |= X86_XSTATE_BNDREGS;
1585 memcpy (p, raw, 16);
1586 }
1587 }
1588 else
1589 {
1590 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1591 xstate_bv |= X86_XSTATE_BNDCFG;
1592 memcpy (p, raw, 8);
1593 }
1594 break;
1595
1596 case sse:
1597 /* This is an SSE register. */
1598 p = FXSAVE_ADDR (tdep, regs, regnum);
1599 if (memcmp (raw, p, 16))
1600 {
1601 xstate_bv |= X86_XSTATE_SSE;
1602 memcpy (p, raw, 16);
1603 }
1604 break;
1605
1606 case x87:
1607 /* This is an x87 register. */
1608 p = FXSAVE_ADDR (tdep, regs, regnum);
1609 if (memcmp (raw, p, 10))
1610 {
1611 xstate_bv |= X86_XSTATE_X87;
1612 memcpy (p, raw, 10);
1613 }
1614 break;
1615 }
1616 }
1617
1618 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1619 registers are changed. */
1620 if (xstate_bv)
1621 {
1622 /* The supported bits in `xstat_bv' are 1 byte. */
1623 *xstate_bv_p |= (gdb_byte) xstate_bv;
1624
1625 switch (regclass)
1626 {
1627 default:
1628 internal_error (__FILE__, __LINE__,
1629 _("invalid i387 regclass"));
1630
1631 case all:
1632 break;
1633
1634 case x87:
1635 case sse:
1636 case avxh:
1637 case mpx:
1638 case avx512_k:
1639 case avx512_zmm_h:
1640 case avx512_ymmh_avx512:
1641 case avx512_xmm_avx512:
1642 /* Register REGNUM has been updated. Return. */
1643 return;
1644 }
1645 }
1646 else
1647 {
1648 /* Return if REGNUM isn't changed. */
1649 if (regclass != all)
1650 return;
1651 }
1652 }
1653
1654 /* Only handle x87 control registers. */
1655 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1656 if (regnum == -1 || regnum == i)
1657 {
1658 /* Most of the FPU control registers occupy only 16 bits in
1659 the xsave extended state. Give those a special treatment. */
1660 if (i != I387_FIOFF_REGNUM (tdep)
1661 && i != I387_FOOFF_REGNUM (tdep))
1662 {
1663 gdb_byte buf[4];
1664
1665 regcache_raw_collect (regcache, i, buf);
1666
1667 if (i == I387_FOP_REGNUM (tdep))
1668 {
1669 /* The opcode occupies only 11 bits. Make sure we
1670 don't touch the other bits. */
1671 buf[1] &= ((1 << 3) - 1);
1672 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1673 }
1674 else if (i == I387_FTAG_REGNUM (tdep))
1675 {
1676 /* Converting back is much easier. */
1677
1678 unsigned short ftag;
1679 int fpreg;
1680
1681 ftag = (buf[1] << 8) | buf[0];
1682 buf[0] = 0;
1683 buf[1] = 0;
1684
1685 for (fpreg = 7; fpreg >= 0; fpreg--)
1686 {
1687 int tag = (ftag >> (fpreg * 2)) & 3;
1688
1689 if (tag != 3)
1690 buf[0] |= (1 << fpreg);
1691 }
1692 }
1693 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1694 }
1695 else
1696 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1697 }
1698
1699 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1700 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1701 FXSAVE_MXCSR_ADDR (regs));
1702 }
1703
1704 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1705 *RAW. */
1706
1707 static int
1708 i387_tag (const gdb_byte *raw)
1709 {
1710 int integer;
1711 unsigned int exponent;
1712 unsigned long fraction[2];
1713
1714 integer = raw[7] & 0x80;
1715 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1716 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1717 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1718 | (raw[5] << 8) | raw[4]);
1719
1720 if (exponent == 0x7fff)
1721 {
1722 /* Special. */
1723 return (2);
1724 }
1725 else if (exponent == 0x0000)
1726 {
1727 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1728 {
1729 /* Zero. */
1730 return (1);
1731 }
1732 else
1733 {
1734 /* Special. */
1735 return (2);
1736 }
1737 }
1738 else
1739 {
1740 if (integer)
1741 {
1742 /* Valid. */
1743 return (0);
1744 }
1745 else
1746 {
1747 /* Special. */
1748 return (2);
1749 }
1750 }
1751 }
1752
1753 /* Prepare the FPU stack in REGCACHE for a function return. */
1754
1755 void
1756 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1757 {
1758 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1759 ULONGEST fstat;
1760
1761 /* Set the top of the floating-point register stack to 7. The
1762 actual value doesn't really matter, but 7 is what a normal
1763 function return would end up with if the program started out with
1764 a freshly initialized FPU. */
1765 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1766 fstat |= (7 << 11);
1767 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1768
1769 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1770 floating-point register stack to 7, the appropriate value for the
1771 tag word is 0x3fff. */
1772 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1773
1774 }
GDB Binutils - Deliverables
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