1 /* i80960 instruction disassembler for GDB.
2 Copyright 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
24 static FILE *stream
; /* Output goes here */
25 static void print_addr();
33 static void invalid();
35 static void put_abs();
38 /* Print the i960 instruction at address 'memaddr' in debugged memory,
39 on stream 's'. Returns length of the instruction, in bytes. */
41 print_insn( memaddr
, s
)
45 unsigned int word1
, word2
;
48 word1
= read_memory_integer( memaddr
, 4 );
49 word2
= read_memory_integer( memaddr
+4, 4 );
50 return pinsn( memaddr
, word1
, word2
);
54 /* Read the i960 instruction at 'memaddr' and return the address of
55 the next instruction after that, or 0 if 'memaddr' is not the
56 address of a valid instruction. The first word of the instruction
57 is stored at 'pword1', and the second word, if any, is stored at
61 next_insn (memaddr
, pword1
, pword2
)
62 unsigned long *pword1
, *pword2
;
68 /* Read the two (potential) words of the instruction at once,
69 to eliminate the overhead of two calls to read_memory ().
70 TODO: read more instructions at once and cache them. */
72 read_memory (memaddr
, buf
, sizeof (buf
));
74 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
76 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
78 /* Divide instruction set into classes based on high 4 bits of opcode*/
80 switch ((*pword1
>> 28) & 0xf)
99 len
= mem (memaddr
, *pword1
, *pword2
, 1);
102 default: /* invalid instruction */
108 return memaddr
+ len
;
115 /*****************************************************************************
116 * All code below this point should be identical with that of
117 * the disassembler in gdmp960.
118 *****************************************************************************/
126 pinsn( memaddr
, word1
, word2
)
127 unsigned long memaddr
;
128 unsigned long word1
, word2
;
133 put_abs( word1
, word2
);
135 /* Divide instruction set into classes based on high 4 bits of opcode*/
137 switch ( (word1
>> 28) & 0xf ){
140 ctrl( memaddr
, word1
, word2
);
144 cobr( memaddr
, word1
, word2
);
156 instr_len
= mem( memaddr
, word1
, word2
, 0 );
159 /* invalid instruction, print as data word */
166 /****************************************/
168 /****************************************/
170 ctrl( memaddr
, word1
, word2
)
171 unsigned long memaddr
;
172 unsigned long word1
, word2
;
175 static struct tabent ctrl_tab
[] = {
185 "call", 1, /* 0x09 */
200 "faultno", 0, /* 0x18 */
201 "faultg", 0, /* 0x19 */
202 "faulte", 0, /* 0x1a */
203 "faultge", 0, /* 0x1b */
204 "faultl", 0, /* 0x1c */
205 "faultne", 0, /* 0x1d */
206 "faultle", 0, /* 0x1e */
207 "faulto", 0, /* 0x1f */
210 i
= (word1
>> 24) & 0xff;
211 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
216 fputs( ctrl_tab
[i
].name
, stream
);
217 if ( word1
& 2 ){ /* Predicts branch not taken */
218 fputs( ".f", stream
);
221 if ( ctrl_tab
[i
].numops
== 1 ){
222 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
224 if ( word1
& 0x00800000 ){ /* Sign bit is set */
225 word1
|= (-1 & ~0xffffff); /* Sign extend */
227 putc( '\t', stream
);
228 print_addr( word1
+ memaddr
);
232 /****************************************/
234 /****************************************/
236 cobr( memaddr
, word1
, word2
)
237 unsigned long memaddr
;
238 unsigned long word1
, word2
;
244 static struct tabent cobr_tab
[] = {
245 "testno", 1, /* 0x20 */
246 "testg", 1, /* 0x21 */
247 "teste", 1, /* 0x22 */
248 "testge", 1, /* 0x23 */
249 "testl", 1, /* 0x24 */
250 "testne", 1, /* 0x25 */
251 "testle", 1, /* 0x26 */
252 "testo", 1, /* 0x27 */
262 "cmpobg", 3, /* 0x31 */
263 "cmpobe", 3, /* 0x32 */
264 "cmpobge", 3, /* 0x33 */
265 "cmpobl", 3, /* 0x34 */
266 "cmpobne", 3, /* 0x35 */
267 "cmpoble", 3, /* 0x36 */
269 "cmpibno", 3, /* 0x38 */
270 "cmpibg", 3, /* 0x39 */
271 "cmpibe", 3, /* 0x3a */
272 "cmpibge", 3, /* 0x3b */
273 "cmpibl", 3, /* 0x3c */
274 "cmpibne", 3, /* 0x3d */
275 "cmpible", 3, /* 0x3e */
276 "cmpibo", 3, /* 0x3f */
279 i
= ((word1
>> 24) & 0xff) - 0x20;
280 if ( cobr_tab
[i
].name
== NULL
){
285 fputs( cobr_tab
[i
].name
, stream
);
286 if ( word1
& 2 ){ /* Predicts branch not taken */
287 fputs( ".f", stream
);
289 putc( '\t', stream
);
291 src1
= (word1
>> 19) & 0x1f;
292 src2
= (word1
>> 14) & 0x1f;
294 if ( word1
& 0x02000 ){ /* M1 is 1 */
295 fprintf( stream
, "%d", src1
);
296 } else { /* M1 is 0 */
297 fputs( reg_names
[src1
], stream
);
300 if ( cobr_tab
[i
].numops
> 1 ){
301 if ( word1
& 1 ){ /* S2 is 1 */
302 fprintf( stream
, ",sf%d,", src2
);
303 } else { /* S1 is 0 */
304 fprintf( stream
, ",%s,", reg_names
[src2
] );
307 /* Extract displacement and convert to address
310 if ( word1
& 0x00001000 ){ /* Negative displacement */
311 word1
|= (-1 & ~0x1fff); /* Sign extend */
313 print_addr( memaddr
+ word1
);
317 /****************************************/
319 /****************************************/
320 static int /* returns instruction length: 4 or 8 */
321 mem( memaddr
, word1
, word2
, noprint
)
322 unsigned long memaddr
;
323 unsigned long word1
, word2
;
324 int noprint
; /* If TRUE, return instruction length, but
325 don't output any text. */
331 CONST
char *reg1
, *reg2
, *reg3
;
333 /* This lookup table is too sparse to make it worth typing in, but not
334 * so large as to make a sparse array necessary. We allocate the
335 * table at runtime, initialize all entries to empty, and copy the
336 * real ones in from an initialization table.
338 * NOTE: In this table, the meaning of 'numops' is:
340 * 2: 2 operands, load instruction
341 * -2: 2 operands, store instruction
343 static struct tabent
*mem_tab
= NULL
;
344 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
367 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
371 if ( mem_tab
== NULL
){
372 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
373 bzero( mem_tab
, MEM_SIZ
);
374 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
375 j
= mem_init
[i
].opcode
- MEM_MIN
;
376 mem_tab
[j
].name
= mem_init
[i
].name
;
377 mem_tab
[j
].numops
= mem_init
[i
].numops
;
381 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
382 mode
= (word1
>> 10) & 0xf;
384 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
385 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
395 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
400 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
402 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
403 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
404 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
405 offset
= word1
& 0xfff; /* MEMA only */
407 switch ( mem_tab
[i
].numops
){
409 case 2: /* LOAD INSTRUCTION */
410 if ( mode
& 4 ){ /* MEMB FORMAT */
411 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
412 fprintf( stream
, ",%s", reg1
);
413 } else { /* MEMA FORMAT */
414 fprintf( stream
, "0x%x", offset
);
416 fprintf( stream
, "(%s)", reg2
);
418 fprintf( stream
, ",%s", reg1
);
422 case -2: /* STORE INSTRUCTION */
423 if ( mode
& 4 ){ /* MEMB FORMAT */
424 fprintf( stream
, "%s,", reg1
);
425 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
426 } else { /* MEMA FORMAT */
427 fprintf( stream
, "%s,0x%x", reg1
, offset
);
429 fprintf( stream
, "(%s)", reg2
);
434 case 1: /* BX/CALLX INSTRUCTION */
435 if ( mode
& 4 ){ /* MEMB FORMAT */
436 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
437 } else { /* MEMA FORMAT */
438 fprintf( stream
, "0x%x", offset
);
440 fprintf( stream
, "(%s)", reg2
);
449 /****************************************/
451 /****************************************/
464 /* This lookup table is too sparse to make it worth typing in, but not
465 * so large as to make a sparse array necessary. We allocate the
466 * table at runtime, initialize all entries to empty, and copy the
467 * real ones in from an initialization table.
469 * NOTE: In this table, the meaning of 'numops' is:
470 * 1: single operand, which is NOT a destination.
471 * -1: single operand, which IS a destination.
472 * 2: 2 operands, the 2nd of which is NOT a destination.
473 * -2: 2 operands, the 2nd of which IS a destination.
476 * If an opcode mnemonic begins with "F", it is a floating-point
477 * opcode (the "F" is not printed).
480 static struct tabent
*reg_tab
= NULL
;
481 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
482 #define REG_MIN 0x580
497 0x58f, "alterbit", 3,
516 0x5ac, "scanbyte", 2,
533 0x613, "inspacc", -2,
539 0x640, "spanbit", -2,
540 0x641, "scanbit", -2,
545 0x646, "condrec", -2,
550 0x656, "receive", -2,
554 0x663, "sendserv", 1,
555 0x664, "resumprcs", 1,
556 0x665, "schedprcs", 1,
557 0x666, "saveprcs", 0,
558 0x668, "condwait", 1,
563 0x66d, "flushreg", 0,
569 0x675, "Fcvtilr", -2,
570 0x676, "Fscalerl", 3,
580 0x68a, "Flogbnr", -2,
581 0x68b, "Froundr", -2,
587 0x691, "Flogeprl", 3,
592 0x698, "Fsqrtrl", -2,
594 0x69a, "Flogbnrl", -2,
595 0x69b, "Froundrl", -2,
599 0x69f, "Fclassrl", 1,
601 0x6c1, "Fcvtril", -2,
602 0x6c2, "Fcvtzri", -2,
603 0x6c3, "Fcvtzril", -2,
608 0x6e3, "Fcpyrsre", 3,
624 #define REG_MAX 0x79f
625 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
629 if ( reg_tab
== NULL
){
630 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
631 bzero( reg_tab
, REG_SIZ
);
632 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
633 j
= reg_init
[i
].opcode
- REG_MIN
;
634 reg_tab
[j
].name
= reg_init
[i
].name
;
635 reg_tab
[j
].numops
= reg_init
[i
].numops
;
639 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
640 i
= opcode
- REG_MIN
;
642 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
647 mnemp
= reg_tab
[i
].name
;
648 if ( *mnemp
== 'F' ){
655 fputs( mnemp
, stream
);
657 s1
= (word1
>> 5) & 1;
658 s2
= (word1
>> 6) & 1;
659 m1
= (word1
>> 11) & 1;
660 m2
= (word1
>> 12) & 1;
661 m3
= (word1
>> 13) & 1;
663 src2
= (word1
>> 14) & 0x1f;
664 dst
= (word1
>> 19) & 0x1f;
666 if ( reg_tab
[i
].numops
!= 0 ){
667 putc( '\t', stream
);
669 switch ( reg_tab
[i
].numops
){
671 regop( m1
, s1
, src
, fp
);
674 dstop( m3
, dst
, fp
);
677 regop( m1
, s1
, src
, fp
);
679 regop( m2
, s2
, src2
, fp
);
682 regop( m1
, s1
, src
, fp
);
684 dstop( m3
, dst
, fp
);
687 regop( m1
, s1
, src
, fp
);
689 regop( m2
, s2
, src2
, fp
);
691 dstop( m3
, dst
, fp
);
699 * Print out effective address for memb instructions.
702 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
703 unsigned long memaddr
;
709 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
711 scale
= (word1
>> 7) & 0x07;
712 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
716 scale
= scale_tab
[scale
];
720 fprintf( stream
, "(%s)", reg2
);
722 case 5: /* displ+8(ip) */
723 print_addr( word2
+8+memaddr
);
725 case 7: /* (reg)[index*scale] */
727 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
729 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
732 case 12: /* displacement */
735 case 13: /* displ(reg) */
737 fprintf( stream
, "(%s)", reg2
);
739 case 14: /* displ[index*scale] */
742 fprintf( stream
, "[%s]", reg3
);
744 fprintf( stream
, "[%s*%d]", reg3
, scale
);
747 case 15: /* displ(reg)[index*scale] */
750 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
752 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
762 /************************************************/
763 /* Register Instruction Operand */
764 /************************************************/
766 regop( mode
, spec
, reg
, fp
)
767 int mode
, spec
, reg
, fp
;
769 if ( fp
){ /* FLOATING POINT INSTRUCTION */
770 if ( mode
== 1 ){ /* FP operand */
772 case 0: fputs( "fp0", stream
); break;
773 case 1: fputs( "fp1", stream
); break;
774 case 2: fputs( "fp2", stream
); break;
775 case 3: fputs( "fp3", stream
); break;
776 case 16: fputs( "0f0.0", stream
); break;
777 case 22: fputs( "0f1.0", stream
); break;
778 default: putc( '?', stream
); break;
780 } else { /* Non-FP register */
781 fputs( reg_names
[reg
], stream
);
783 } else { /* NOT FLOATING POINT */
784 if ( mode
== 1 ){ /* Literal */
785 fprintf( stream
, "%d", reg
);
786 } else { /* Register */
788 fputs( reg_names
[reg
], stream
);
790 fprintf( stream
, "sf%d", reg
);
796 /************************************************/
797 /* Register Instruction Destination Operand */
798 /************************************************/
800 dstop( mode
, reg
, fp
)
803 /* 'dst' operand can't be a literal. On non-FP instructions, register
804 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
805 * sf registers are not allowed so m3 acts normally.
808 regop( mode
, 0, reg
, fp
);
810 regop( 0, mode
, reg
, fp
);
819 fprintf( stream
, ".word\t0x%08x", word1
);
825 print_address (a
, stream
);
829 put_abs( word1
, word2
)
830 unsigned long word1
, word2
;
837 switch ( (word1
>> 28) & 0xf ){
843 /* MEM format instruction */
844 len
= mem( 0, word1
, word2
, 1 );
852 fprintf( stream
, "%08x %08x\t", word1
, word2
);
854 fprintf( stream
, "%08x \t", word1
);
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