1 /* i80960 instruction disassembler for GDB.
2 Copyright (C) 1990-1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
26 extern char *reg_names
[];
28 static FILE *stream
; /* Output goes here */
29 static void print_addr();
37 static void invalid();
39 static void put_abs();
42 /* Print the i960 instruction at address 'memaddr' in debugged memory,
43 on stream 's'. Returns length of the instruction, in bytes. */
45 print_insn( memaddr
, s
)
49 unsigned int word1
, word2
;
52 word1
= read_memory_integer( memaddr
, 4 );
53 word2
= read_memory_integer( memaddr
+4, 4 );
54 return pinsn( memaddr
, word1
, word2
);
58 /* Read the i960 instruction at 'memaddr' and return the address of
59 the next instruction after that, or 0 if 'memaddr' is not the
60 address of a valid instruction. The first word of the instruction
61 is stored at 'pword1', and the second word, if any, is stored at
65 next_insn (memaddr
, pword1
, pword2
)
66 unsigned long *pword1
, *pword2
;
72 /* Read the two (potential) words of the instruction at once,
73 to eliminate the overhead of two calls to read_memory ().
74 TODO: read more instructions at once and cache them. */
76 read_memory (memaddr
, buf
, sizeof (buf
));
78 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
80 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
82 /* Divide instruction set into classes based on high 4 bits of opcode*/
84 switch ((*pword1
>> 28) & 0xf)
103 len
= mem (memaddr
, *pword1
, *pword2
, 1);
106 default: /* invalid instruction */
112 return memaddr
+ len
;
119 /*****************************************************************************
120 * All code below this point should be identical with that of
121 * the disassembler in gdmp960.
122 *****************************************************************************/
130 pinsn( memaddr
, word1
, word2
)
131 unsigned long memaddr
;
132 unsigned long word1
, word2
;
137 put_abs( word1
, word2
);
139 /* Divide instruction set into classes based on high 4 bits of opcode*/
141 switch ( (word1
>> 28) & 0xf ){
144 ctrl( memaddr
, word1
, word2
);
148 cobr( memaddr
, word1
, word2
);
160 instr_len
= mem( memaddr
, word1
, word2
, 0 );
163 /* invalid instruction, print as data word */
170 /****************************************/
172 /****************************************/
174 ctrl( memaddr
, word1
, word2
)
175 unsigned long memaddr
;
176 unsigned long word1
, word2
;
179 static struct tabent ctrl_tab
[] = {
189 "call", 1, /* 0x09 */
204 "faultno", 0, /* 0x18 */
205 "faultg", 0, /* 0x19 */
206 "faulte", 0, /* 0x1a */
207 "faultge", 0, /* 0x1b */
208 "faultl", 0, /* 0x1c */
209 "faultne", 0, /* 0x1d */
210 "faultle", 0, /* 0x1e */
211 "faulto", 0, /* 0x1f */
214 i
= (word1
>> 24) & 0xff;
215 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
220 fputs( ctrl_tab
[i
].name
, stream
);
221 if ( word1
& 2 ){ /* Predicts branch not taken */
222 fputs( ".f", stream
);
225 if ( ctrl_tab
[i
].numops
== 1 ){
226 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
228 if ( word1
& 0x00800000 ){ /* Sign bit is set */
229 word1
|= (-1 & ~0xffffff); /* Sign extend */
231 putc( '\t', stream
);
232 print_addr( word1
+ memaddr
);
236 /****************************************/
238 /****************************************/
240 cobr( memaddr
, word1
, word2
)
241 unsigned long memaddr
;
242 unsigned long word1
, word2
;
248 static struct tabent cobr_tab
[] = {
249 "testno", 1, /* 0x20 */
250 "testg", 1, /* 0x21 */
251 "teste", 1, /* 0x22 */
252 "testge", 1, /* 0x23 */
253 "testl", 1, /* 0x24 */
254 "testne", 1, /* 0x25 */
255 "testle", 1, /* 0x26 */
256 "testo", 1, /* 0x27 */
266 "cmpobg", 3, /* 0x31 */
267 "cmpobe", 3, /* 0x32 */
268 "cmpobge", 3, /* 0x33 */
269 "cmpobl", 3, /* 0x34 */
270 "cmpobne", 3, /* 0x35 */
271 "cmpoble", 3, /* 0x36 */
273 "cmpibno", 3, /* 0x38 */
274 "cmpibg", 3, /* 0x39 */
275 "cmpibe", 3, /* 0x3a */
276 "cmpibge", 3, /* 0x3b */
277 "cmpibl", 3, /* 0x3c */
278 "cmpibne", 3, /* 0x3d */
279 "cmpible", 3, /* 0x3e */
280 "cmpibo", 3, /* 0x3f */
283 i
= ((word1
>> 24) & 0xff) - 0x20;
284 if ( cobr_tab
[i
].name
== NULL
){
289 fputs( cobr_tab
[i
].name
, stream
);
290 if ( word1
& 2 ){ /* Predicts branch not taken */
291 fputs( ".f", stream
);
293 putc( '\t', stream
);
295 src1
= (word1
>> 19) & 0x1f;
296 src2
= (word1
>> 14) & 0x1f;
298 if ( word1
& 0x02000 ){ /* M1 is 1 */
299 fprintf( stream
, "%d", src1
);
300 } else { /* M1 is 0 */
301 fputs( reg_names
[src1
], stream
);
304 if ( cobr_tab
[i
].numops
> 1 ){
305 if ( word1
& 1 ){ /* S2 is 1 */
306 fprintf( stream
, ",sf%d,", src2
);
307 } else { /* S1 is 0 */
308 fprintf( stream
, ",%s,", reg_names
[src2
] );
311 /* Extract displacement and convert to address
314 if ( word1
& 0x00001000 ){ /* Negative displacement */
315 word1
|= (-1 & ~0x1fff); /* Sign extend */
317 print_addr( memaddr
+ word1
);
321 /****************************************/
323 /****************************************/
324 static int /* returns instruction length: 4 or 8 */
325 mem( memaddr
, word1
, word2
, noprint
)
326 unsigned long memaddr
;
327 unsigned long word1
, word2
;
328 int noprint
; /* If TRUE, return instruction length, but
329 don't output any text. */
335 char *reg1
, *reg2
, *reg3
;
337 /* This lookup table is too sparse to make it worth typing in, but not
338 * so large as to make a sparse array necessary. We allocate the
339 * table at runtime, initialize all entries to empty, and copy the
340 * real ones in from an initialization table.
342 * NOTE: In this table, the meaning of 'numops' is:
344 * 2: 2 operands, load instruction
345 * -2: 2 operands, store instruction
347 static struct tabent
*mem_tab
= NULL
;
348 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
371 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
375 if ( mem_tab
== NULL
){
376 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
377 bzero( mem_tab
, MEM_SIZ
);
378 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
379 j
= mem_init
[i
].opcode
- MEM_MIN
;
380 mem_tab
[j
].name
= mem_init
[i
].name
;
381 mem_tab
[j
].numops
= mem_init
[i
].numops
;
385 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
386 mode
= (word1
>> 10) & 0xf;
388 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
389 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
399 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
404 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
406 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
407 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
408 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
409 offset
= word1
& 0xfff; /* MEMA only */
411 switch ( mem_tab
[i
].numops
){
413 case 2: /* LOAD INSTRUCTION */
414 if ( mode
& 4 ){ /* MEMB FORMAT */
415 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
416 fprintf( stream
, ",%s", reg1
);
417 } else { /* MEMA FORMAT */
418 fprintf( stream
, "0x%x", offset
);
420 fprintf( stream
, "(%s)", reg2
);
422 fprintf( stream
, ",%s", reg1
);
426 case -2: /* STORE INSTRUCTION */
427 if ( mode
& 4 ){ /* MEMB FORMAT */
428 fprintf( stream
, "%s,", reg1
);
429 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
430 } else { /* MEMA FORMAT */
431 fprintf( stream
, "%s,0x%x", reg1
, offset
);
433 fprintf( stream
, "(%s)", reg2
);
438 case 1: /* BX/CALLX INSTRUCTION */
439 if ( mode
& 4 ){ /* MEMB FORMAT */
440 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
441 } else { /* MEMA FORMAT */
442 fprintf( stream
, "0x%x", offset
);
444 fprintf( stream
, "(%s)", reg2
);
453 /****************************************/
455 /****************************************/
468 /* This lookup table is too sparse to make it worth typing in, but not
469 * so large as to make a sparse array necessary. We allocate the
470 * table at runtime, initialize all entries to empty, and copy the
471 * real ones in from an initialization table.
473 * NOTE: In this table, the meaning of 'numops' is:
474 * 1: single operand, which is NOT a destination.
475 * -1: single operand, which IS a destination.
476 * 2: 2 operands, the 2nd of which is NOT a destination.
477 * -2: 2 operands, the 2nd of which IS a destination.
480 * If an opcode mnemonic begins with "F", it is a floating-point
481 * opcode (the "F" is not printed).
484 static struct tabent
*reg_tab
= NULL
;
485 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
486 #define REG_MIN 0x580
501 0x58f, "alterbit", 3,
520 0x5ac, "scanbyte", 2,
537 0x613, "inspacc", -2,
543 0x640, "spanbit", -2,
544 0x641, "scanbit", -2,
549 0x646, "condrec", -2,
554 0x656, "receive", -2,
558 0x663, "sendserv", 1,
559 0x664, "resumprcs", 1,
560 0x665, "schedprcs", 1,
561 0x666, "saveprcs", 0,
562 0x668, "condwait", 1,
567 0x66d, "flushreg", 0,
573 0x675, "Fcvtilr", -2,
574 0x676, "Fscalerl", 3,
584 0x68a, "Flogbnr", -2,
585 0x68b, "Froundr", -2,
591 0x691, "Flogeprl", 3,
596 0x698, "Fsqrtrl", -2,
598 0x69a, "Flogbnrl", -2,
599 0x69b, "Froundrl", -2,
603 0x69f, "Fclassrl", 1,
605 0x6c1, "Fcvtril", -2,
606 0x6c2, "Fcvtzri", -2,
607 0x6c3, "Fcvtzril", -2,
612 0x6e3, "Fcpyrsre", 3,
628 #define REG_MAX 0x79f
629 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
633 if ( reg_tab
== NULL
){
634 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
635 bzero( reg_tab
, REG_SIZ
);
636 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
637 j
= reg_init
[i
].opcode
- REG_MIN
;
638 reg_tab
[j
].name
= reg_init
[i
].name
;
639 reg_tab
[j
].numops
= reg_init
[i
].numops
;
643 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
644 i
= opcode
- REG_MIN
;
646 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
651 mnemp
= reg_tab
[i
].name
;
652 if ( *mnemp
== 'F' ){
659 fputs( mnemp
, stream
);
661 s1
= (word1
>> 5) & 1;
662 s2
= (word1
>> 6) & 1;
663 m1
= (word1
>> 11) & 1;
664 m2
= (word1
>> 12) & 1;
665 m3
= (word1
>> 13) & 1;
667 src2
= (word1
>> 14) & 0x1f;
668 dst
= (word1
>> 19) & 0x1f;
670 if ( reg_tab
[i
].numops
!= 0 ){
671 putc( '\t', stream
);
673 switch ( reg_tab
[i
].numops
){
675 regop( m1
, s1
, src
, fp
);
678 dstop( m3
, dst
, fp
);
681 regop( m1
, s1
, src
, fp
);
683 regop( m2
, s2
, src2
, fp
);
686 regop( m1
, s1
, src
, fp
);
688 dstop( m3
, dst
, fp
);
691 regop( m1
, s1
, src
, fp
);
693 regop( m2
, s2
, src2
, fp
);
695 dstop( m3
, dst
, fp
);
703 * Print out effective address for memb instructions.
706 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
707 unsigned long memaddr
;
713 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
715 scale
= (word1
>> 7) & 0x07;
716 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
720 scale
= scale_tab
[scale
];
724 fprintf( stream
, "(%s)", reg2
);
726 case 5: /* displ+8(ip) */
727 print_addr( word2
+8+memaddr
);
729 case 7: /* (reg)[index*scale] */
731 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
733 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
736 case 12: /* displacement */
739 case 13: /* displ(reg) */
741 fprintf( stream
, "(%s)", reg2
);
743 case 14: /* displ[index*scale] */
746 fprintf( stream
, "[%s]", reg3
);
748 fprintf( stream
, "[%s*%d]", reg3
, scale
);
751 case 15: /* displ(reg)[index*scale] */
754 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
756 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
766 /************************************************/
767 /* Register Instruction Operand */
768 /************************************************/
770 regop( mode
, spec
, reg
, fp
)
771 int mode
, spec
, reg
, fp
;
773 if ( fp
){ /* FLOATING POINT INSTRUCTION */
774 if ( mode
== 1 ){ /* FP operand */
776 case 0: fputs( "fp0", stream
); break;
777 case 1: fputs( "fp1", stream
); break;
778 case 2: fputs( "fp2", stream
); break;
779 case 3: fputs( "fp3", stream
); break;
780 case 16: fputs( "0f0.0", stream
); break;
781 case 22: fputs( "0f1.0", stream
); break;
782 default: putc( '?', stream
); break;
784 } else { /* Non-FP register */
785 fputs( reg_names
[reg
], stream
);
787 } else { /* NOT FLOATING POINT */
788 if ( mode
== 1 ){ /* Literal */
789 fprintf( stream
, "%d", reg
);
790 } else { /* Register */
792 fputs( reg_names
[reg
], stream
);
794 fprintf( stream
, "sf%d", reg
);
800 /************************************************/
801 /* Register Instruction Destination Operand */
802 /************************************************/
804 dstop( mode
, reg
, fp
)
807 /* 'dst' operand can't be a literal. On non-FP instructions, register
808 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
809 * sf registers are not allowed so m3 acts normally.
812 regop( mode
, 0, reg
, fp
);
814 regop( 0, mode
, reg
, fp
);
823 fprintf( stream
, ".word\t0x%08x", word1
);
829 fprintf( stream
, "0x%x", a
);
833 put_abs( word1
, word2
)
834 unsigned long word1
, word2
;
841 switch ( (word1
>> 28) & 0xf ){
847 /* MEM format instruction */
848 len
= mem( 0, word1
, word2
, 1 );
856 fprintf( stream
, "%08x %08x\t", word1
, word2
);
858 fprintf( stream
, "%08x \t", word1
);
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