1 /* Target-machine dependent code for the Intel 960
2 Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Intel Corporation.
4 examine_prologue and other parts contributed by Wind River Systems.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "floatformat.h"
32 static CORE_ADDR next_insn
PARAMS ((CORE_ADDR memaddr
,
34 unsigned int *pword2
));
36 /* Does the specified function use the "struct returning" convention
37 or the "value returning" convention? The "value returning" convention
38 almost invariably returns the entire value in registers. The
39 "struct returning" convention often returns the entire value in
40 memory, and passes a pointer (out of or into the function) saying
41 where the value (is or should go).
43 Since this sometimes depends on whether it was compiled with GCC,
44 this is also an argument. This is used in call_function to build a
45 stack, and in value_being_returned to print return values.
47 On i960, a structure is returned in registers g0-g3, if it will fit.
48 If it's more than 16 bytes long, g13 pointed to it on entry. */
51 i960_use_struct_convention (gcc_p
, type
)
55 return (TYPE_LENGTH (type
) > 16);
58 /* gdb960 is always running on a non-960 host. Check its characteristics.
59 This routine must be called as part of gdb initialization. */
66 static struct typestruct
68 int hostsize
; /* Size of type on host */
69 int i960size
; /* Size of type on i960 */
70 char *typename
; /* Name of type, for error msg */
75 sizeof (short), 2, "short"
79 sizeof (int), 4, "int"
83 sizeof (long), 4, "long"
87 sizeof (float), 4, "float"
91 sizeof (double), 8, "double"
95 sizeof (char *), 4, "pointer"
99 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
101 /* Make sure that host type sizes are same as i960
103 for (i
= 0; i
< TYPELEN
; i
++)
105 if (types
[i
].hostsize
!= types
[i
].i960size
)
107 printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
108 types
[i
].typename
, types
[i
].i960size
);
114 /* Examine an i960 function prologue, recording the addresses at which
115 registers are saved explicitly by the prologue code, and returning
116 the address of the first instruction after the prologue (but not
117 after the instruction at address LIMIT, as explained below).
119 LIMIT places an upper bound on addresses of the instructions to be
120 examined. If the prologue code scan reaches LIMIT, the scan is
121 aborted and LIMIT is returned. This is used, when examining the
122 prologue for the current frame, to keep examine_prologue () from
123 claiming that a given register has been saved when in fact the
124 instruction that saves it has not yet been executed. LIMIT is used
125 at other times to stop the scan when we hit code after the true
126 function prologue (e.g. for the first source line) which might
127 otherwise be mistaken for function prologue.
129 The format of the function prologue matched by this routine is
130 derived from examination of the source to gcc960 1.21, particularly
131 the routine i960_function_prologue (). A "regular expression" for
132 the function prologue is given below:
136 (mov 0, g14) | (lda 0, g14))?
138 (mov[qtl]? g[0-15], r[4-15])*
139 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
140 (st[qtl]? g[0-15], n(fp))*
153 /* Macros for extracting fields from i960 instructions. */
155 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
156 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
158 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
159 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
160 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
161 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
162 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
164 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
165 is not the address of a valid instruction, the address of the next
166 instruction beyond ADDR otherwise. *PWORD1 receives the first word
167 of the instruction, and (for two-word instructions), *PWORD2 receives
170 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
171 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
174 examine_prologue (ip
, limit
, frame_addr
, fsr
)
175 register CORE_ADDR ip
;
176 register CORE_ADDR limit
;
177 CORE_ADDR frame_addr
;
178 struct frame_saved_regs
*fsr
;
180 register CORE_ADDR next_ip
;
181 register int src
, dst
;
182 register unsigned int *pcode
;
183 unsigned int insn1
, insn2
;
185 int within_leaf_prologue
;
187 static unsigned int varargs_prologue_code
[] =
189 0x3507a00c, /* cmpobne 0x0, g14, LFn */
190 0x5cf01601, /* mov sp, g14 */
191 0x8c086030, /* lda 0x30(sp), sp */
192 0xb2879000, /* LFn: stq g0, (g14) */
193 0xb2a7a010, /* stq g4, 0x10(g14) */
194 0xb2c7a020 /* stq g8, 0x20(g14) */
197 /* Accept a leaf procedure prologue code fragment if present.
198 Note that ip might point to either the leaf or non-leaf
199 entry point; we look for the non-leaf entry point first: */
201 within_leaf_prologue
= 0;
202 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
203 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
204 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
206 within_leaf_prologue
= 1;
207 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
210 /* Now look for the prologue code at a leaf entry point: */
213 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
214 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
216 within_leaf_prologue
= 1;
217 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
218 && (insn1
== 0x8cf00000 /* lda 0, g14 */
219 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
222 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
223 within_leaf_prologue
= 0;
227 /* If something that looks like the beginning of a leaf prologue
228 has been seen, but the remainder of the prologue is missing, bail.
229 We don't know what we've got. */
231 if (within_leaf_prologue
)
234 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
235 This may cause us to mistake the moving of a register
236 parameter to a local register for the saving of a callee-saved
237 register, but that can't be helped, since with the
238 "-fcall-saved" flag, any register can be made callee-saved. */
241 && (insn1
& 0xfc802fb0) == 0x5c000610
242 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
244 src
= REG_SRC1 (insn1
);
245 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
246 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
249 fsr
->regs
[src
++] = save_addr
;
253 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
256 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
259 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
260 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
261 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
264 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
267 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
268 This may cause us to mistake the copying of a register
269 parameter to the frame for the saving of a callee-saved
270 register, but that can't be helped, since with the
271 "-fcall-saved" flag, any register can be made callee-saved.
272 We can, however, refuse to accept a save of register g14,
273 since that is matched explicitly below. */
276 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
277 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
278 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
279 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
280 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
282 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
283 ? insn2
: MEMA_OFFSET (insn1
));
284 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
285 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
288 fsr
->regs
[src
++] = save_addr
;
292 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
295 /* Accept the varargs prologue code if present. */
297 size
= sizeof (varargs_prologue_code
) / sizeof (int);
298 pcode
= varargs_prologue_code
;
299 while (size
-- && next_ip
&& *pcode
++ == insn1
)
302 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
305 /* Accept an optional "st g14, n(fp)". */
308 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
309 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
311 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
312 ? insn2
: MEMA_OFFSET (insn1
));
314 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
317 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
318 This is saving the address where a struct should be returned. */
321 && (insn1
& 0xff802fbf) == 0x5c00061d
322 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
324 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
325 fsr
->regs
[G0_REGNUM
+ 13] = save_addr
;
327 #if 0 /* We'll need this once there is a subsequent instruction examined. */
328 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
335 /* Given an ip value corresponding to the start of a function,
336 return the ip of the first instruction after the function
340 i960_skip_prologue (ip
)
343 struct frame_saved_regs saved_regs_dummy
;
344 struct symtab_and_line sal
;
347 sal
= find_pc_line (ip
, 0);
348 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
350 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
353 /* Put here the code to store, into a struct frame_saved_regs,
354 the addresses of the saved registers of frame described by FRAME_INFO.
355 This includes special registers such as pc and fp saved in special
356 ways in the stack frame. sp is even more special:
357 the address we return for it IS the sp for the next frame.
359 We cache the result of doing this in the frame_obstack, since it is
363 frame_find_saved_regs (fi
, fsr
)
364 struct frame_info
*fi
;
365 struct frame_saved_regs
*fsr
;
367 register CORE_ADDR next_addr
;
368 register CORE_ADDR
*saved_regs
;
370 register struct frame_saved_regs
*cache_fsr
;
372 struct symtab_and_line sal
;
377 cache_fsr
= (struct frame_saved_regs
*)
378 frame_obstack_alloc (sizeof (struct frame_saved_regs
));
379 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
382 /* Find the start and end of the function prologue. If the PC
383 is in the function prologue, we only consider the part that
384 has executed already. */
386 ip
= get_pc_function_start (fi
->pc
);
387 sal
= find_pc_line (ip
, 0);
388 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
390 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
392 /* Record the addresses at which the local registers are saved.
393 Strictly speaking, we should only do this for non-leaf procedures,
394 but no one will ever look at these values if it is a leaf procedure,
395 since local registers are always caller-saved. */
397 next_addr
= (CORE_ADDR
) fi
->frame
;
398 saved_regs
= cache_fsr
->regs
;
399 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
401 *saved_regs
++ = next_addr
;
405 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
410 /* Fetch the value of the sp from memory every time, since it
411 is conceivable that it has changed since the cache was flushed.
412 This unfortunately undoes much of the savings from caching the
413 saved register values. I suggest adding an argument to
414 get_frame_saved_regs () specifying the register number we're
415 interested in (or -1 for all registers). This would be passed
416 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
417 computation of saved register addresses (e.g., on the i960,
418 we don't have to examine the prologue to find local registers).
420 FIXME, we don't need to refetch this, since the cache is cleared
421 every time the child process is restarted. If GDB itself
422 modifies SP, it has to clear the cache by hand (does it?). -gnu */
424 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
427 /* Return the address of the argument block for the frame
428 described by FI. Returns 0 if the address is unknown. */
431 frame_args_address (fi
, must_be_correct
)
432 struct frame_info
*fi
;
434 struct frame_saved_regs fsr
;
437 /* If g14 was saved in the frame by the function prologue code, return
438 the saved value. If the frame is current and we are being sloppy,
439 return the value of g14. Otherwise, return zero. */
441 get_frame_saved_regs (fi
, &fsr
);
442 if (fsr
.regs
[G14_REGNUM
])
443 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
], 4);
447 return 0; /* Don't cache this result */
448 if (get_next_frame (fi
))
451 ap
= read_register (G14_REGNUM
);
455 fi
->arg_pointer
= ap
; /* Cache it for next time */
459 /* Return the address of the return struct for the frame
460 described by FI. Returns 0 if the address is unknown. */
463 frame_struct_result_address (fi
)
464 struct frame_info
*fi
;
466 struct frame_saved_regs fsr
;
469 /* If the frame is non-current, check to see if g14 was saved in the
470 frame by the function prologue code; return the saved value if so,
471 zero otherwise. If the frame is current, return the value of g14.
473 FIXME, shouldn't this use the saved value as long as we are past
474 the function prologue, and only use the current value if we have
475 no saved value and are at TOS? -- gnu@cygnus.com */
477 if (get_next_frame (fi
))
479 get_frame_saved_regs (fi
, &fsr
);
480 if (fsr
.regs
[G13_REGNUM
])
481 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
], 4);
486 ap
= read_register (G13_REGNUM
);
491 /* Return address to which the currently executing leafproc will return,
492 or 0 if ip is not in a leafproc (or if we can't tell if it is).
494 Do this by finding the starting address of the routine in which ip lies.
495 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
496 is a leafproc and the return address is in register gx. Well, this is
497 true unless the return address points at a RET instruction in the current
498 procedure, which indicates that we have a 'dual entry' routine that
499 has been entered through the CALL entry point. */
503 CORE_ADDR ip
; /* ip from currently executing function */
505 register struct minimal_symbol
*msymbol
;
508 unsigned int insn1
, insn2
;
509 CORE_ADDR return_addr
;
511 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
513 if ((p
= strchr (SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
515 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
516 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
517 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
519 /* Get the return address. If the "mov g14, gx"
520 instruction hasn't been executed yet, read
521 the return address from g14; otherwise, read it
522 from the register into which g14 was moved. */
525 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
528 /* We know we are in a leaf procedure, but we don't know
529 whether the caller actually did a "bal" to the ".lf"
530 entry point, or a normal "call" to the non-leaf entry
531 point one instruction before. In the latter case, the
532 return address will be the address of a "ret"
533 instruction within the procedure itself. We test for
536 if (!next_insn (return_addr
, &insn1
, &insn2
)
537 || (insn1
& 0xff000000) != 0xa000000 /* ret */
538 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
539 return (return_addr
);
547 /* Immediately after a function call, return the saved pc.
548 Can't go through the frames for this because on some machines
549 the new frame is not set up until the new function executes
551 On the i960, the frame *is* set up immediately after the call,
552 unless the function is a leaf procedure. */
555 saved_pc_after_call (frame
)
556 struct frame_info
*frame
;
560 saved_pc
= leafproc_return (get_frame_pc (frame
));
562 saved_pc
= FRAME_SAVED_PC (frame
);
567 /* Discard from the stack the innermost frame,
568 restoring all saved registers. */
571 i960_pop_frame (void)
573 register struct frame_info
*current_fi
, *prev_fi
;
576 CORE_ADDR leaf_return_addr
;
577 struct frame_saved_regs fsr
;
578 char local_regs_buf
[16 * 4];
580 current_fi
= get_current_frame ();
582 /* First, undo what the hardware does when we return.
583 If this is a non-leaf procedure, restore local registers from
584 the save area in the calling frame. Otherwise, load the return
585 address obtained from leafproc_return () into the rip. */
587 leaf_return_addr
= leafproc_return (current_fi
->pc
);
588 if (!leaf_return_addr
)
590 /* Non-leaf procedure. Restore local registers, incl IP. */
591 prev_fi
= get_prev_frame (current_fi
);
592 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
593 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
594 sizeof (local_regs_buf
));
596 /* Restore frame pointer. */
597 write_register (FP_REGNUM
, prev_fi
->frame
);
601 /* Leaf procedure. Just restore the return address into the IP. */
602 write_register (RIP_REGNUM
, leaf_return_addr
);
605 /* Now restore any global regs that the current function had saved. */
606 get_frame_saved_regs (current_fi
, &fsr
);
607 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
609 save_addr
= fsr
.regs
[i
];
611 write_register (i
, read_memory_integer (save_addr
, 4));
614 /* Flush the frame cache, create a frame for the new innermost frame,
615 and make it the current frame. */
617 flush_cached_frames ();
620 /* Given a 960 stop code (fault or trace), return the signal which
624 i960_fault_to_signal (fault
)
630 return TARGET_SIGNAL_BUS
; /* parallel fault */
632 return TARGET_SIGNAL_UNKNOWN
;
634 return TARGET_SIGNAL_ILL
; /* operation fault */
636 return TARGET_SIGNAL_FPE
; /* arithmetic fault */
638 return TARGET_SIGNAL_FPE
; /* floating point fault */
640 /* constraint fault. This appears not to distinguish between
641 a range constraint fault (which should be SIGFPE) and a privileged
642 fault (which should be SIGILL). */
644 return TARGET_SIGNAL_ILL
;
647 return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
649 /* protection fault. This is for an out-of-range argument to
650 "calls". I guess it also could be SIGILL. */
652 return TARGET_SIGNAL_SEGV
;
655 return TARGET_SIGNAL_BUS
; /* machine fault */
657 return TARGET_SIGNAL_BUS
; /* structural fault */
659 return TARGET_SIGNAL_ILL
; /* type fault */
661 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
663 return TARGET_SIGNAL_BUS
; /* process fault */
665 return TARGET_SIGNAL_SEGV
; /* descriptor fault */
667 return TARGET_SIGNAL_BUS
; /* event fault */
669 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
671 return TARGET_SIGNAL_TRAP
; /* single-step trace */
673 return TARGET_SIGNAL_TRAP
; /* branch trace */
675 return TARGET_SIGNAL_TRAP
; /* call trace */
677 return TARGET_SIGNAL_TRAP
; /* return trace */
679 return TARGET_SIGNAL_TRAP
; /* pre-return trace */
681 return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
683 return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
685 return TARGET_SIGNAL_UNKNOWN
;
689 /****************************************/
691 /****************************************/
699 static int /* returns instruction length: 4 or 8 */
700 mem (memaddr
, word1
, word2
, noprint
)
701 unsigned long memaddr
;
702 unsigned long word1
, word2
;
703 int noprint
; /* If TRUE, return instruction length, but
704 don't output any text. */
710 const char *reg1
, *reg2
, *reg3
;
712 /* This lookup table is too sparse to make it worth typing in, but not
713 * so large as to make a sparse array necessary. We allocate the
714 * table at runtime, initialize all entries to empty, and copy the
715 * real ones in from an initialization table.
717 * NOTE: In this table, the meaning of 'numops' is:
719 * 2: 2 operands, load instruction
720 * -2: 2 operands, store instruction
722 static struct tabent
*mem_tab
= NULL
;
723 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
726 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
761 mem_tab
= (struct tabent
*) xmalloc (MEM_SIZ
);
762 memset (mem_tab
, '\0', MEM_SIZ
);
763 for (i
= 0; mem_init
[i
].opcode
!= 0; i
++)
765 j
= mem_init
[i
].opcode
- MEM_MIN
;
766 mem_tab
[j
].name
= mem_init
[i
].name
;
767 mem_tab
[j
].numops
= mem_init
[i
].numops
;
771 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
772 mode
= (word1
>> 10) & 0xf;
774 if ((mem_tab
[i
].name
!= NULL
) /* Valid instruction */
775 && ((mode
== 5) || (mode
>= 12)))
776 { /* With 32-bit displacement */
791 /* Read the i960 instruction at 'memaddr' and return the address of
792 the next instruction after that, or 0 if 'memaddr' is not the
793 address of a valid instruction. The first word of the instruction
794 is stored at 'pword1', and the second word, if any, is stored at
798 next_insn (memaddr
, pword1
, pword2
)
799 unsigned int *pword1
, *pword2
;
805 /* Read the two (potential) words of the instruction at once,
806 to eliminate the overhead of two calls to read_memory ().
807 FIXME: Loses if the first one is readable but the second is not
808 (e.g. last word of the segment). */
810 read_memory (memaddr
, buf
, 8);
811 *pword1
= extract_unsigned_integer (buf
, 4);
812 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
814 /* Divide instruction set into classes based on high 4 bits of opcode */
816 switch ((*pword1
>> 28) & 0xf)
835 len
= mem (memaddr
, *pword1
, *pword2
, 1);
838 default: /* invalid instruction */
844 return memaddr
+ len
;
849 /* 'start_frame' is a variable in the MON960 runtime startup routine
850 that contains the frame pointer of the 'start' routine (the routine
851 that calls 'main'). By reading its contents out of remote memory,
852 we can tell where the frame chain ends: backtraces should halt before
853 they display this frame. */
856 mon960_frame_chain_valid (chain
, curframe
)
858 struct frame_info
*curframe
;
861 struct minimal_symbol
*msymbol
;
863 /* crtmon960.o is an assembler module that is assumed to be linked
864 * first in an i80960 executable. It contains the true entry point;
865 * it performs startup up initialization and then calls 'main'.
867 * 'sf' is the name of a variable in crtmon960.o that is set
868 * during startup to the address of the first frame.
870 * 'a' is the address of that variable in 80960 memory.
872 static char sf
[] = "start_frame";
876 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
877 contain return status info in them. */
883 sym
= lookup_symbol (sf
, 0, VAR_NAMESPACE
, (int *) NULL
,
884 (struct symtab
**) NULL
);
887 a
= SYMBOL_VALUE (sym
);
891 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
894 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
897 return (chain
!= read_memory_integer (a
, 4));
902 _initialize_i960_tdep ()
906 tm_print_insn
= print_insn_i960
;