gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation,
   5    Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #include "defs.h"
  25 #include "gdb_string.h"
  26 #include "inferior.h"
  27 #include "target.h"
  28 #include "gdbcore.h"
  29 #include "regcache.h"
  30
  31 #include <signal.h>
  32 #include <sys/ptrace.h>
  33 #include "gdb_wait.h"
  34 #ifdef HAVE_SYS_REG_H
  35 #include <sys/reg.h>
  36 #endif
  37 #include <sys/syscall.h>
  38 #include <sys/user.h>
  39
  40 #include <asm/ptrace_offsets.h>
  41 #include <sys/procfs.h>
  42
  43 /* Prototypes for supply_gregset etc. */
  44 #include "gregset.h"
  45
  46 /* These must match the order of the register names.
  47
  48    Some sort of lookup table is needed because the offsets associated
  49    with the registers are all over the board.  */
  50
  51 static int u_offsets[] =
  52   {
  53     /* general registers */
  54     -1,         /* gr0 not available; i.e, it's always zero */
  55     PT_R1,
  56     PT_R2,
  57     PT_R3,
  58     PT_R4,
  59     PT_R5,
  60     PT_R6,
  61     PT_R7,
  62     PT_R8,
  63     PT_R9,
  64     PT_R10,
  65     PT_R11,
  66     PT_R12,
  67     PT_R13,
  68     PT_R14,
  69     PT_R15,
  70     PT_R16,
  71     PT_R17,
  72     PT_R18,
  73     PT_R19,
  74     PT_R20,
  75     PT_R21,
  76     PT_R22,
  77     PT_R23,
  78     PT_R24,
  79     PT_R25,
  80     PT_R26,
  81     PT_R27,
  82     PT_R28,
  83     PT_R29,
  84     PT_R30,
  85     PT_R31,
  86     /* gr32 through gr127 not directly available via the ptrace interface */
  87     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  88     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  89     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  90     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  91     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  92     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  93     /* Floating point registers */
  94     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
  95     PT_F2,
  96     PT_F3,
  97     PT_F4,
  98     PT_F5,
  99     PT_F6,
 100     PT_F7,
 101     PT_F8,
 102     PT_F9,
 103     PT_F10,
 104     PT_F11,
 105     PT_F12,
 106     PT_F13,
 107     PT_F14,
 108     PT_F15,
 109     PT_F16,
 110     PT_F17,
 111     PT_F18,
 112     PT_F19,
 113     PT_F20,
 114     PT_F21,
 115     PT_F22,
 116     PT_F23,
 117     PT_F24,
 118     PT_F25,
 119     PT_F26,
 120     PT_F27,
 121     PT_F28,
 122     PT_F29,
 123     PT_F30,
 124     PT_F31,
 125     PT_F32,
 126     PT_F33,
 127     PT_F34,
 128     PT_F35,
 129     PT_F36,
 130     PT_F37,
 131     PT_F38,
 132     PT_F39,
 133     PT_F40,
 134     PT_F41,
 135     PT_F42,
 136     PT_F43,
 137     PT_F44,
 138     PT_F45,
 139     PT_F46,
 140     PT_F47,
 141     PT_F48,
 142     PT_F49,
 143     PT_F50,
 144     PT_F51,
 145     PT_F52,
 146     PT_F53,
 147     PT_F54,
 148     PT_F55,
 149     PT_F56,
 150     PT_F57,
 151     PT_F58,
 152     PT_F59,
 153     PT_F60,
 154     PT_F61,
 155     PT_F62,
 156     PT_F63,
 157     PT_F64,
 158     PT_F65,
 159     PT_F66,
 160     PT_F67,
 161     PT_F68,
 162     PT_F69,
 163     PT_F70,
 164     PT_F71,
 165     PT_F72,
 166     PT_F73,
 167     PT_F74,
 168     PT_F75,
 169     PT_F76,
 170     PT_F77,
 171     PT_F78,
 172     PT_F79,
 173     PT_F80,
 174     PT_F81,
 175     PT_F82,
 176     PT_F83,
 177     PT_F84,
 178     PT_F85,
 179     PT_F86,
 180     PT_F87,
 181     PT_F88,
 182     PT_F89,
 183     PT_F90,
 184     PT_F91,
 185     PT_F92,
 186     PT_F93,
 187     PT_F94,
 188     PT_F95,
 189     PT_F96,
 190     PT_F97,
 191     PT_F98,
 192     PT_F99,
 193     PT_F100,
 194     PT_F101,
 195     PT_F102,
 196     PT_F103,
 197     PT_F104,
 198     PT_F105,
 199     PT_F106,
 200     PT_F107,
 201     PT_F108,
 202     PT_F109,
 203     PT_F110,
 204     PT_F111,
 205     PT_F112,
 206     PT_F113,
 207     PT_F114,
 208     PT_F115,
 209     PT_F116,
 210     PT_F117,
 211     PT_F118,
 212     PT_F119,
 213     PT_F120,
 214     PT_F121,
 215     PT_F122,
 216     PT_F123,
 217     PT_F124,
 218     PT_F125,
 219     PT_F126,
 220     PT_F127,
 221     /* predicate registers - we don't fetch these individually */
 222     -1, -1, -1, -1, -1, -1, -1, -1,
 223     -1, -1, -1, -1, -1, -1, -1, -1,
 224     -1, -1, -1, -1, -1, -1, -1, -1,
 225     -1, -1, -1, -1, -1, -1, -1, -1,
 226     -1, -1, -1, -1, -1, -1, -1, -1,
 227     -1, -1, -1, -1, -1, -1, -1, -1,
 228     -1, -1, -1, -1, -1, -1, -1, -1,
 229     -1, -1, -1, -1, -1, -1, -1, -1,
 230     /* branch registers */
 231     PT_B0,
 232     PT_B1,
 233     PT_B2,
 234     PT_B3,
 235     PT_B4,
 236     PT_B5,
 237     PT_B6,
 238     PT_B7,
 239     /* virtual frame pointer and virtual return address pointer */
 240     -1, -1,
 241     /* other registers */
 242     PT_PR,
 243     PT_CR_IIP,  /* ip */
 244     PT_CR_IPSR, /* psr */
 245     PT_CFM,     /* cfm */
 246     /* kernel registers not visible via ptrace interface (?) */
 247     -1, -1, -1, -1, -1, -1, -1, -1,
 248     /* hole */
 249     -1, -1, -1, -1, -1, -1, -1, -1,
 250     PT_AR_RSC,
 251     PT_AR_BSP,
 252     PT_AR_BSPSTORE,
 253     PT_AR_RNAT,
 254     -1,
 255     -1,         /* Not available: FCR, IA32 floating control register */
 256     -1, -1,
 257     -1,         /* Not available: EFLAG */
 258     -1,         /* Not available: CSD */
 259     -1,         /* Not available: SSD */
 260     -1,         /* Not available: CFLG */
 261     -1,         /* Not available: FSR */
 262     -1,         /* Not available: FIR */
 263     -1,         /* Not available: FDR */
 264     -1,
 265     PT_AR_CCV,
 266     -1, -1, -1,
 267     PT_AR_UNAT,
 268     -1, -1, -1,
 269     PT_AR_FPSR,
 270     -1, -1, -1,
 271     -1,         /* Not available: ITC */
 272     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 273     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 274     PT_AR_PFS,
 275     PT_AR_LC,
 276     -1,         /* Not available: EC, the Epilog Count register */
 277     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 278     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 279     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 280     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 281     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 282     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 283     -1,
 284     /* nat bits - not fetched directly; instead we obtain these bits from
 285        either rnat or unat or from memory. */
 286     -1, -1, -1, -1, -1, -1, -1, -1,
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296     -1, -1, -1, -1, -1, -1, -1, -1,
 297     -1, -1, -1, -1, -1, -1, -1, -1,
 298     -1, -1, -1, -1, -1, -1, -1, -1,
 299     -1, -1, -1, -1, -1, -1, -1, -1,
 300     -1, -1, -1, -1, -1, -1, -1, -1,
 301     -1, -1, -1, -1, -1, -1, -1, -1,
 302   };
 303
 304 CORE_ADDR
 305 register_addr (int regno, CORE_ADDR blockend)
 306 {
 307   CORE_ADDR addr;
 308
 309   if (regno < 0 || regno >= NUM_REGS)
 310     error ("Invalid register number %d.", regno);
 311
 312   if (u_offsets[regno] == -1)
 313     addr = 0;
 314   else
 315     addr = (CORE_ADDR) u_offsets[regno];
 316
 317   return addr;
 318 }
 319
 320 int ia64_cannot_fetch_register (regno)
 321      int regno;
 322 {
 323   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
 324 }
 325
 326 int ia64_cannot_store_register (regno)
 327      int regno;
 328 {
 329   /* Rationale behind not permitting stores to bspstore...
 330
 331      The IA-64 architecture provides bspstore and bsp which refer
 332      memory locations in the RSE's backing store.  bspstore is the
 333      next location which will be written when the RSE needs to write
 334      to memory.  bsp is the address at which r32 in the current frame
 335      would be found if it were written to the backing store.
 336
 337      The IA-64 architecture provides read-only access to bsp and
 338      read/write access to bspstore (but only when the RSE is in
 339      the enforced lazy mode).  It should be noted that stores
 340      to bspstore also affect the value of bsp.  Changing bspstore
 341      does not affect the number of dirty entries between bspstore
 342      and bsp, so changing bspstore by N words will also cause bsp
 343      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 344      depending upon where the NaT collection bits fall.)
 345
 346      OTOH, the Linux kernel provides read/write access to bsp (and
 347      currently read/write access to bspstore as well).  But it
 348      is definitely the case that if you change one, the other
 349      will change at the same time.  It is more useful to gdb to
 350      be able to change bsp.  So in order to prevent strange and
 351      undesirable things from happening when a dummy stack frame
 352      is popped (after calling an inferior function), we allow
 353      bspstore to be read, but not written.  (Note that popping
 354      a (generic) dummy stack frame causes all registers that
 355      were previously read from the inferior process to be written
 356      back.)  */
 357
 358   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
 359          || regno == IA64_BSPSTORE_REGNUM;
 360 }
 361
 362 void
 363 supply_gregset (gregset_t *gregsetp)
 364 {
 365   int regi;
 366   greg_t *regp = (greg_t *) gregsetp;
 367
 368   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 369     {
 370       supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
 371     }
 372
 373   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 374      somehow... */
 375
 376   supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
 377
 378   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 379     {
 380       supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
 381     }
 382
 383   supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
 384   supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
 385   supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
 386   supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
 387   supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
 388   supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
 389   supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
 390   supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
 391   supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
 392   supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
 393   supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
 394   supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
 395   supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
 396 }
 397
 398 void
 399 fill_gregset (gregset_t *gregsetp, int regno)
 400 {
 401   int regi;
 402   greg_t *regp = (greg_t *) gregsetp;
 403
 404 #define COPY_REG(_idx_,_regi_) \
 405   if ((regno == -1) || regno == _regi_) \
 406     memcpy (regp + _idx_, &deprecated_registers[DEPRECATED_REGISTER_BYTE (_regi_)], \
 407             DEPRECATED_REGISTER_RAW_SIZE (_regi_))
 408
 409   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 410     {
 411       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 412     }
 413
 414   /* FIXME: NAT collection bits at index 32? */
 415
 416   COPY_REG (33, IA64_PR_REGNUM);
 417
 418   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 419     {
 420       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 421     }
 422
 423   COPY_REG (42, IA64_IP_REGNUM);
 424   COPY_REG (43, IA64_CFM_REGNUM);
 425   COPY_REG (44, IA64_PSR_REGNUM);
 426   COPY_REG (45, IA64_RSC_REGNUM);
 427   COPY_REG (46, IA64_BSP_REGNUM);
 428   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 429   COPY_REG (48, IA64_RNAT_REGNUM);
 430   COPY_REG (49, IA64_CCV_REGNUM);
 431   COPY_REG (50, IA64_UNAT_REGNUM);
 432   COPY_REG (51, IA64_FPSR_REGNUM);
 433   COPY_REG (52, IA64_PFS_REGNUM);
 434   COPY_REG (53, IA64_LC_REGNUM);
 435   COPY_REG (54, IA64_EC_REGNUM);
 436 }
 437
 438 /*  Given a pointer to a floating point register set in /proc format
 439    (fpregset_t *), unpack the register contents and supply them as gdb's
 440    idea of the current floating point register values. */
 441
 442 void
 443 supply_fpregset (fpregset_t *fpregsetp)
 444 {
 445   int regi;
 446   char *from;
 447
 448   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 449     {
 450       from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 451       supply_register (regi, from);
 452     }
 453 }
 454
 455 /*  Given a pointer to a floating point register set in /proc format
 456    (fpregset_t *), update the register specified by REGNO from gdb's idea
 457    of the current floating point register set.  If REGNO is -1, update
 458    them all. */
 459
 460 void
 461 fill_fpregset (fpregset_t *fpregsetp, int regno)
 462 {
 463   int regi;
 464   char *to;
 465   char *from;
 466
 467   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 468     {
 469       if ((regno == -1) || (regno == regi))
 470         {
 471           from = (char *) &deprecated_registers[DEPRECATED_REGISTER_BYTE (regi)];
 472           to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 473           memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (regi));
 474         }
 475     }
 476 }
 477
 478 #define IA64_PSR_DB (1UL << 24)
 479 #define IA64_PSR_DD (1UL << 39)
 480
 481 static void
 482 enable_watchpoints_in_psr (ptid_t ptid)
 483 {
 484   CORE_ADDR psr;
 485
 486   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 487   if (!(psr & IA64_PSR_DB))
 488     {
 489       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 490                                    watchpoints and breakpoints. */
 491       write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 492     }
 493 }
 494
 495 static long
 496 fetch_debug_register (ptid_t ptid, int idx)
 497 {
 498   long val;
 499   int tid;
 500
 501   tid = TIDGET (ptid);
 502   if (tid == 0)
 503     tid = PIDGET (ptid);
 504
 505   val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);
 506
 507   return val;
 508 }
 509
 510 static void
 511 store_debug_register (ptid_t ptid, int idx, long val)
 512 {
 513   int tid;
 514
 515   tid = TIDGET (ptid);
 516   if (tid == 0)
 517     tid = PIDGET (ptid);
 518
 519   (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
 520 }
 521
 522 static void
 523 fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 524 {
 525   if (dbr_addr)
 526     *dbr_addr = fetch_debug_register (ptid, 2 * idx);
 527   if (dbr_mask)
 528     *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
 529 }
 530
 531 static void
 532 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 533 {
 534   if (dbr_addr)
 535     store_debug_register (ptid, 2 * idx, *dbr_addr);
 536   if (dbr_mask)
 537     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 538 }
 539
 540 static int
 541 is_power_of_2 (int val)
 542 {
 543   int i, onecount;
 544
 545   onecount = 0;
 546   for (i = 0; i < 8 * sizeof (val); i++)
 547     if (val & (1 << i))
 548       onecount++;
 549
 550   return onecount <= 1;
 551 }
 552
 553 int
 554 ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
 555 {
 556   int idx;
 557   long dbr_addr, dbr_mask;
 558   int max_watchpoints = 4;
 559
 560   if (len <= 0 || !is_power_of_2 (len))
 561     return -1;
 562
 563   for (idx = 0; idx < max_watchpoints; idx++)
 564     {
 565       fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
 566       if ((dbr_mask & (0x3UL << 62)) == 0)
 567         {
 568           /* Exit loop if both r and w bits clear */
 569           break;
 570         }
 571     }
 572
 573   if (idx == max_watchpoints)
 574     return -1;
 575
 576   dbr_addr = (long) addr;
 577   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 578   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 579   switch (rw)
 580     {
 581     case hw_write:
 582       dbr_mask |= (1L << 62);                   /* Set w bit */
 583       break;
 584     case hw_read:
 585       dbr_mask |= (1L << 63);                   /* Set r bit */
 586       break;
 587     case hw_access:
 588       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 589       break;
 590     default:
 591       return -1;
 592     }
 593
 594   store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 595   enable_watchpoints_in_psr (ptid);
 596
 597   return 0;
 598 }
 599
 600 int
 601 ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
 602 {
 603   int idx;
 604   long dbr_addr, dbr_mask;
 605   int max_watchpoints = 4;
 606
 607   if (len <= 0 || !is_power_of_2 (len))
 608     return -1;
 609
 610   for (idx = 0; idx < max_watchpoints; idx++)
 611     {
 612       fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 613       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 614         {
 615           dbr_addr = 0;
 616           dbr_mask = 0;
 617           store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 618           return 0;
 619         }
 620     }
 621   return -1;
 622 }
 623
 624 CORE_ADDR
 625 ia64_linux_stopped_by_watchpoint (ptid_t ptid)
 626 {
 627   CORE_ADDR psr;
 628   int tid;
 629   struct siginfo siginfo;
 630
 631   tid = TIDGET(ptid);
 632   if (tid == 0)
 633     tid = PIDGET (ptid);
 634
 635   errno = 0;
 636   ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);
 637
 638   if (errno != 0 || siginfo.si_signo != SIGTRAP ||
 639       (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 640     return 0;
 641
 642   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 643   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 644                            for the next instruction */
 645   write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 646
 647   return (CORE_ADDR) siginfo.si_addr;
 648 }
 649
 650 LONGEST
 651 ia64_linux_xfer_unwind_table (struct target_ops *ops,
 652                               enum target_object object,
 653                               const char *annex,
 654                               void *readbuf, const void *writebuf,
 655                               ULONGEST offset, LONGEST len)
 656 {
 657   return syscall (__NR_getunwind, readbuf, len);
 658 }