gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "inferior.h"
  25 #include "target.h"
  26 #include "gdbcore.h"
  27 #include "regcache.h"
  28
  29 #include <signal.h>
  30 #include <sys/ptrace.h>
  31 #include <sys/wait.h>
  32 #ifdef HAVE_SYS_REG_H
  33 #include <sys/reg.h>
  34 #endif
  35 #include <sys/user.h>
  36
  37 #include <asm/ptrace_offsets.h>
  38 #include <sys/procfs.h>
  39
  40 /* Prototypes for supply_gregset etc. */
  41 #include "gregset.h"
  42
  43 /* These must match the order of the register names.
  44
  45    Some sort of lookup table is needed because the offsets associated
  46    with the registers are all over the board.  */
  47
  48 static int u_offsets[] =
  49   {
  50     /* general registers */
  51     -1,         /* gr0 not available; i.e, it's always zero */
  52     PT_R1,
  53     PT_R2,
  54     PT_R3,
  55     PT_R4,
  56     PT_R5,
  57     PT_R6,
  58     PT_R7,
  59     PT_R8,
  60     PT_R9,
  61     PT_R10,
  62     PT_R11,
  63     PT_R12,
  64     PT_R13,
  65     PT_R14,
  66     PT_R15,
  67     PT_R16,
  68     PT_R17,
  69     PT_R18,
  70     PT_R19,
  71     PT_R20,
  72     PT_R21,
  73     PT_R22,
  74     PT_R23,
  75     PT_R24,
  76     PT_R25,
  77     PT_R26,
  78     PT_R27,
  79     PT_R28,
  80     PT_R29,
  81     PT_R30,
  82     PT_R31,
  83     /* gr32 through gr127 not directly available via the ptrace interface */
  84     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  85     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  86     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  87     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  88     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  89     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  90     /* Floating point registers */
  91     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
  92     PT_F2,
  93     PT_F3,
  94     PT_F4,
  95     PT_F5,
  96     PT_F6,
  97     PT_F7,
  98     PT_F8,
  99     PT_F9,
 100     PT_F10,
 101     PT_F11,
 102     PT_F12,
 103     PT_F13,
 104     PT_F14,
 105     PT_F15,
 106     PT_F16,
 107     PT_F17,
 108     PT_F18,
 109     PT_F19,
 110     PT_F20,
 111     PT_F21,
 112     PT_F22,
 113     PT_F23,
 114     PT_F24,
 115     PT_F25,
 116     PT_F26,
 117     PT_F27,
 118     PT_F28,
 119     PT_F29,
 120     PT_F30,
 121     PT_F31,
 122     PT_F32,
 123     PT_F33,
 124     PT_F34,
 125     PT_F35,
 126     PT_F36,
 127     PT_F37,
 128     PT_F38,
 129     PT_F39,
 130     PT_F40,
 131     PT_F41,
 132     PT_F42,
 133     PT_F43,
 134     PT_F44,
 135     PT_F45,
 136     PT_F46,
 137     PT_F47,
 138     PT_F48,
 139     PT_F49,
 140     PT_F50,
 141     PT_F51,
 142     PT_F52,
 143     PT_F53,
 144     PT_F54,
 145     PT_F55,
 146     PT_F56,
 147     PT_F57,
 148     PT_F58,
 149     PT_F59,
 150     PT_F60,
 151     PT_F61,
 152     PT_F62,
 153     PT_F63,
 154     PT_F64,
 155     PT_F65,
 156     PT_F66,
 157     PT_F67,
 158     PT_F68,
 159     PT_F69,
 160     PT_F70,
 161     PT_F71,
 162     PT_F72,
 163     PT_F73,
 164     PT_F74,
 165     PT_F75,
 166     PT_F76,
 167     PT_F77,
 168     PT_F78,
 169     PT_F79,
 170     PT_F80,
 171     PT_F81,
 172     PT_F82,
 173     PT_F83,
 174     PT_F84,
 175     PT_F85,
 176     PT_F86,
 177     PT_F87,
 178     PT_F88,
 179     PT_F89,
 180     PT_F90,
 181     PT_F91,
 182     PT_F92,
 183     PT_F93,
 184     PT_F94,
 185     PT_F95,
 186     PT_F96,
 187     PT_F97,
 188     PT_F98,
 189     PT_F99,
 190     PT_F100,
 191     PT_F101,
 192     PT_F102,
 193     PT_F103,
 194     PT_F104,
 195     PT_F105,
 196     PT_F106,
 197     PT_F107,
 198     PT_F108,
 199     PT_F109,
 200     PT_F110,
 201     PT_F111,
 202     PT_F112,
 203     PT_F113,
 204     PT_F114,
 205     PT_F115,
 206     PT_F116,
 207     PT_F117,
 208     PT_F118,
 209     PT_F119,
 210     PT_F120,
 211     PT_F121,
 212     PT_F122,
 213     PT_F123,
 214     PT_F124,
 215     PT_F125,
 216     PT_F126,
 217     PT_F127,
 218     /* predicate registers - we don't fetch these individually */
 219     -1, -1, -1, -1, -1, -1, -1, -1,
 220     -1, -1, -1, -1, -1, -1, -1, -1,
 221     -1, -1, -1, -1, -1, -1, -1, -1,
 222     -1, -1, -1, -1, -1, -1, -1, -1,
 223     -1, -1, -1, -1, -1, -1, -1, -1,
 224     -1, -1, -1, -1, -1, -1, -1, -1,
 225     -1, -1, -1, -1, -1, -1, -1, -1,
 226     -1, -1, -1, -1, -1, -1, -1, -1,
 227     /* branch registers */
 228     PT_B0,
 229     PT_B1,
 230     PT_B2,
 231     PT_B3,
 232     PT_B4,
 233     PT_B5,
 234     PT_B6,
 235     PT_B7,
 236     /* virtual frame pointer and virtual return address pointer */
 237     -1, -1,
 238     /* other registers */
 239     PT_PR,
 240     PT_CR_IIP,  /* ip */
 241     PT_CR_IPSR, /* psr */
 242     PT_CFM,     /* cfm */
 243     /* kernel registers not visible via ptrace interface (?) */
 244     -1, -1, -1, -1, -1, -1, -1, -1,
 245     /* hole */
 246     -1, -1, -1, -1, -1, -1, -1, -1,
 247     PT_AR_RSC,
 248     PT_AR_BSP,
 249     PT_AR_BSPSTORE,
 250     PT_AR_RNAT,
 251     -1,
 252     -1,         /* Not available: FCR, IA32 floating control register */
 253     -1, -1,
 254     -1,         /* Not available: EFLAG */
 255     -1,         /* Not available: CSD */
 256     -1,         /* Not available: SSD */
 257     -1,         /* Not available: CFLG */
 258     -1,         /* Not available: FSR */
 259     -1,         /* Not available: FIR */
 260     -1,         /* Not available: FDR */
 261     -1,
 262     PT_AR_CCV,
 263     -1, -1, -1,
 264     PT_AR_UNAT,
 265     -1, -1, -1,
 266     PT_AR_FPSR,
 267     -1, -1, -1,
 268     -1,         /* Not available: ITC */
 269     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 270     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 271     PT_AR_PFS,
 272     PT_AR_LC,
 273     -1,         /* Not available: EC, the Epilog Count register */
 274     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 275     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 276     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 277     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 278     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 279     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 280     -1,
 281     /* nat bits - not fetched directly; instead we obtain these bits from
 282        either rnat or unat or from memory. */
 283     -1, -1, -1, -1, -1, -1, -1, -1,
 284     -1, -1, -1, -1, -1, -1, -1, -1,
 285     -1, -1, -1, -1, -1, -1, -1, -1,
 286     -1, -1, -1, -1, -1, -1, -1, -1,
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296     -1, -1, -1, -1, -1, -1, -1, -1,
 297     -1, -1, -1, -1, -1, -1, -1, -1,
 298     -1, -1, -1, -1, -1, -1, -1, -1,
 299   };
 300
 301 CORE_ADDR
 302 register_addr (int regno, CORE_ADDR blockend)
 303 {
 304   CORE_ADDR addr;
 305
 306   if (regno < 0 || regno >= NUM_REGS)
 307     error ("Invalid register number %d.", regno);
 308
 309   if (u_offsets[regno] == -1)
 310     addr = 0;
 311   else
 312     addr = (CORE_ADDR) u_offsets[regno];
 313
 314   return addr;
 315 }
 316
 317 int ia64_cannot_fetch_register (regno)
 318      int regno;
 319 {
 320   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
 321 }
 322
 323 int ia64_cannot_store_register (regno)
 324      int regno;
 325 {
 326   /* Rationale behind not permitting stores to bspstore...
 327
 328      The IA-64 architecture provides bspstore and bsp which refer
 329      memory locations in the RSE's backing store.  bspstore is the
 330      next location which will be written when the RSE needs to write
 331      to memory.  bsp is the address at which r32 in the current frame
 332      would be found if it were written to the backing store.
 333
 334      The IA-64 architecture provides read-only access to bsp and
 335      read/write access to bspstore (but only when the RSE is in
 336      the enforced lazy mode).  It should be noted that stores
 337      to bspstore also affect the value of bsp.  Changing bspstore
 338      does not affect the number of dirty entries between bspstore
 339      and bsp, so changing bspstore by N words will also cause bsp
 340      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 341      depending upon where the NaT collection bits fall.)
 342
 343      OTOH, the Linux kernel provides read/write access to bsp (and
 344      currently read/write access to bspstore as well).  But it
 345      is definitely the case that if you change one, the other
 346      will change at the same time.  It is more useful to gdb to
 347      be able to change bsp.  So in order to prevent strange and
 348      undesirable things from happening when a dummy stack frame
 349      is popped (after calling an inferior function), we allow
 350      bspstore to be read, but not written.  (Note that popping
 351      a (generic) dummy stack frame causes all registers that
 352      were previously read from the inferior process to be written
 353      back.)  */
 354
 355   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
 356          || regno == IA64_BSPSTORE_REGNUM;
 357 }
 358
 359 void
 360 supply_gregset (gregset_t *gregsetp)
 361 {
 362   int regi;
 363   greg_t *regp = (greg_t *) gregsetp;
 364
 365   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 366     {
 367       supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
 368     }
 369
 370   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 371      somehow... */
 372
 373   supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
 374
 375   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 376     {
 377       supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
 378     }
 379
 380   supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
 381   supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
 382   supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
 383   supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
 384   supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
 385   supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
 386   supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
 387   supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
 388   supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
 389   supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
 390   supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
 391   supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
 392   supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
 393 }
 394
 395 void
 396 fill_gregset (gregset_t *gregsetp, int regno)
 397 {
 398   int regi;
 399   greg_t *regp = (greg_t *) gregsetp;
 400
 401 #define COPY_REG(_idx_,_regi_) \
 402   if ((regno == -1) || regno == _regi_) \
 403     memcpy (regp + _idx_, &registers[REGISTER_BYTE (_regi_)], \
 404             REGISTER_RAW_SIZE (_regi_))
 405
 406   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 407     {
 408       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 409     }
 410
 411   /* FIXME: NAT collection bits at index 32? */
 412
 413   COPY_REG (33, IA64_PR_REGNUM);
 414
 415   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 416     {
 417       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 418     }
 419
 420   COPY_REG (42, IA64_IP_REGNUM);
 421   COPY_REG (43, IA64_CFM_REGNUM);
 422   COPY_REG (44, IA64_PSR_REGNUM);
 423   COPY_REG (45, IA64_RSC_REGNUM);
 424   COPY_REG (46, IA64_BSP_REGNUM);
 425   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 426   COPY_REG (48, IA64_RNAT_REGNUM);
 427   COPY_REG (49, IA64_CCV_REGNUM);
 428   COPY_REG (50, IA64_UNAT_REGNUM);
 429   COPY_REG (51, IA64_FPSR_REGNUM);
 430   COPY_REG (52, IA64_PFS_REGNUM);
 431   COPY_REG (53, IA64_LC_REGNUM);
 432   COPY_REG (54, IA64_EC_REGNUM);
 433 }
 434
 435 /*  Given a pointer to a floating point register set in /proc format
 436    (fpregset_t *), unpack the register contents and supply them as gdb's
 437    idea of the current floating point register values. */
 438
 439 void
 440 supply_fpregset (fpregset_t *fpregsetp)
 441 {
 442   register int regi;
 443   char *from;
 444
 445   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 446     {
 447       from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 448       supply_register (regi, from);
 449     }
 450 }
 451
 452 /*  Given a pointer to a floating point register set in /proc format
 453    (fpregset_t *), update the register specified by REGNO from gdb's idea
 454    of the current floating point register set.  If REGNO is -1, update
 455    them all. */
 456
 457 void
 458 fill_fpregset (fpregset_t *fpregsetp, int regno)
 459 {
 460   int regi;
 461   char *to;
 462   char *from;
 463
 464   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 465     {
 466       if ((regno == -1) || (regno == regi))
 467         {
 468           from = (char *) &registers[REGISTER_BYTE (regi)];
 469           to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 470           memcpy (to, from, REGISTER_RAW_SIZE (regi));
 471         }
 472     }
 473 }
 474
 475 #define IA64_PSR_DB (1UL << 24)
 476 #define IA64_PSR_DD (1UL << 39)
 477
 478 static void
 479 enable_watchpoints_in_psr (ptid_t ptid)
 480 {
 481   CORE_ADDR psr;
 482
 483   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 484   if (!(psr & IA64_PSR_DB))
 485     {
 486       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 487                                    watchpoints and breakpoints. */
 488       write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 489     }
 490 }
 491
 492 static long
 493 fetch_debug_register (ptid_t ptid, int idx)
 494 {
 495   long val;
 496   int tid;
 497
 498   tid = TIDGET (ptid);
 499   if (tid == 0)
 500     tid = PIDGET (ptid);
 501
 502   val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);
 503
 504   return val;
 505 }
 506
 507 static void
 508 store_debug_register (ptid_t ptid, int idx, long val)
 509 {
 510   int tid;
 511
 512   tid = TIDGET (ptid);
 513   if (tid == 0)
 514     tid = PIDGET (ptid);
 515
 516   (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
 517 }
 518
 519 static void
 520 fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 521 {
 522   if (dbr_addr)
 523     *dbr_addr = fetch_debug_register (ptid, 2 * idx);
 524   if (dbr_mask)
 525     *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
 526 }
 527
 528 static void
 529 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 530 {
 531   if (dbr_addr)
 532     store_debug_register (ptid, 2 * idx, *dbr_addr);
 533   if (dbr_mask)
 534     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 535 }
 536
 537 static int
 538 is_power_of_2 (int val)
 539 {
 540   int i, onecount;
 541
 542   onecount = 0;
 543   for (i = 0; i < 8 * sizeof (val); i++)
 544     if (val & (1 << i))
 545       onecount++;
 546
 547   return onecount <= 1;
 548 }
 549
 550 int
 551 ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
 552 {
 553   int idx;
 554   long dbr_addr, dbr_mask;
 555   int max_watchpoints = 4;
 556
 557   if (len <= 0 || !is_power_of_2 (len))
 558     return -1;
 559
 560   for (idx = 0; idx < max_watchpoints; idx++)
 561     {
 562       fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
 563       if ((dbr_mask & (0x3UL << 62)) == 0)
 564         {
 565           /* Exit loop if both r and w bits clear */
 566           break;
 567         }
 568     }
 569
 570   if (idx == max_watchpoints)
 571     return -1;
 572
 573   dbr_addr = (long) addr;
 574   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 575   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 576   switch (rw)
 577     {
 578     case hw_write:
 579       dbr_mask |= (1L << 62);                   /* Set w bit */
 580       break;
 581     case hw_read:
 582       dbr_mask |= (1L << 63);                   /* Set r bit */
 583       break;
 584     case hw_access:
 585       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 586       break;
 587     default:
 588       return -1;
 589     }
 590
 591   store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 592   enable_watchpoints_in_psr (ptid);
 593
 594   return 0;
 595 }
 596
 597 int
 598 ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
 599 {
 600   int idx;
 601   long dbr_addr, dbr_mask;
 602   int max_watchpoints = 4;
 603
 604   if (len <= 0 || !is_power_of_2 (len))
 605     return -1;
 606
 607   for (idx = 0; idx < max_watchpoints; idx++)
 608     {
 609       fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 610       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 611         {
 612           dbr_addr = 0;
 613           dbr_mask = 0;
 614           store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 615           return 0;
 616         }
 617     }
 618   return -1;
 619 }
 620
 621 CORE_ADDR
 622 ia64_linux_stopped_by_watchpoint (ptid_t ptid)
 623 {
 624   CORE_ADDR psr;
 625   int tid;
 626   struct siginfo siginfo;
 627
 628   tid = TIDGET(ptid);
 629   if (tid == 0)
 630     tid = PIDGET (ptid);
 631
 632   errno = 0;
 633   ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);
 634
 635   if (errno != 0 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 636     return 0;
 637
 638   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 639   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 640                            for the next instruction */
 641   write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 642
 643   return (CORE_ADDR) siginfo.si_addr;
 644 }