1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999-2018 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "ia64-tdep.h"
27 #include "linux-nat.h"
30 #include "nat/gdb_ptrace.h"
35 #include <sys/syscall.h>
38 #include <asm/ptrace_offsets.h>
39 #include <sys/procfs.h>
41 /* Prototypes for supply_gregset etc. */
44 #include "inf-ptrace.h"
46 class ia64_linux_nat_target final
: public linux_nat_target
49 /* Add our register access methods. */
50 void fetch_registers (struct regcache
*, int) override
;
51 void store_registers (struct regcache
*, int) override
;
53 enum target_xfer_status
xfer_partial (enum target_object object
,
56 const gdb_byte
*writebuf
,
57 ULONGEST offset
, ULONGEST len
,
58 ULONGEST
*xfered_len
) override
;
60 const struct target_desc
*read_description () override
;
62 /* Override watchpoint routines. */
64 /* The IA-64 architecture can step over a watch point (without
65 triggering it again) if the "dd" (data debug fault disable) bit
66 in the processor status word is set.
68 This PSR bit is set in
69 ia64_linux_nat_target::stopped_by_watchpoint when the code there
70 has determined that a hardware watchpoint has indeed been hit.
71 The CPU will then be able to execute one instruction without
72 triggering a watchpoint. */
73 bool have_steppable_watchpoint () { return 1; }
75 int can_use_hw_breakpoint (enum bptype
, int, int) override
;
76 bool stopped_by_watchpoint () override
;
77 bool stopped_data_address (CORE_ADDR
*) override
;
78 int insert_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
79 struct expression
*) override
;
80 int remove_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
81 struct expression
*) override
;
84 static ia64_linux_nat_target the_ia64_linux_nat_target
;
86 /* These must match the order of the register names.
88 Some sort of lookup table is needed because the offsets associated
89 with the registers are all over the board. */
91 static int u_offsets
[] =
93 /* general registers */
94 -1, /* gr0 not available; i.e, it's always zero. */
126 /* gr32 through gr127 not directly available via the ptrace interface. */
127 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
128 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
129 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
130 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
133 /* Floating point registers */
134 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
261 /* Predicate registers - we don't fetch these individually. */
262 -1, -1, -1, -1, -1, -1, -1, -1,
263 -1, -1, -1, -1, -1, -1, -1, -1,
264 -1, -1, -1, -1, -1, -1, -1, -1,
265 -1, -1, -1, -1, -1, -1, -1, -1,
266 -1, -1, -1, -1, -1, -1, -1, -1,
267 -1, -1, -1, -1, -1, -1, -1, -1,
268 -1, -1, -1, -1, -1, -1, -1, -1,
269 -1, -1, -1, -1, -1, -1, -1, -1,
270 /* branch registers */
279 /* Virtual frame pointer and virtual return address pointer. */
281 /* other registers */
284 PT_CR_IPSR
, /* psr */
286 /* kernel registers not visible via ptrace interface (?) */
287 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, /* Not available: FCR, IA32 floating control register. */
297 -1, /* Not available: EFLAG */
298 -1, /* Not available: CSD */
299 -1, /* Not available: SSD */
300 -1, /* Not available: CFLG */
301 -1, /* Not available: FSR */
302 -1, /* Not available: FIR */
303 -1, /* Not available: FDR */
311 -1, /* Not available: ITC */
312 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
313 -1, -1, -1, -1, -1, -1, -1, -1, -1,
317 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
318 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
319 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
320 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
322 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
324 /* nat bits - not fetched directly; instead we obtain these bits from
325 either rnat or unat or from memory. */
326 -1, -1, -1, -1, -1, -1, -1, -1,
327 -1, -1, -1, -1, -1, -1, -1, -1,
328 -1, -1, -1, -1, -1, -1, -1, -1,
329 -1, -1, -1, -1, -1, -1, -1, -1,
330 -1, -1, -1, -1, -1, -1, -1, -1,
331 -1, -1, -1, -1, -1, -1, -1, -1,
332 -1, -1, -1, -1, -1, -1, -1, -1,
333 -1, -1, -1, -1, -1, -1, -1, -1,
334 -1, -1, -1, -1, -1, -1, -1, -1,
335 -1, -1, -1, -1, -1, -1, -1, -1,
336 -1, -1, -1, -1, -1, -1, -1, -1,
337 -1, -1, -1, -1, -1, -1, -1, -1,
338 -1, -1, -1, -1, -1, -1, -1, -1,
339 -1, -1, -1, -1, -1, -1, -1, -1,
340 -1, -1, -1, -1, -1, -1, -1, -1,
341 -1, -1, -1, -1, -1, -1, -1, -1,
345 ia64_register_addr (struct gdbarch
*gdbarch
, int regno
)
349 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
350 error (_("Invalid register number %d."), regno
);
352 if (u_offsets
[regno
] == -1)
355 addr
= (CORE_ADDR
) u_offsets
[regno
];
361 ia64_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
364 || regno
>= gdbarch_num_regs (gdbarch
)
365 || u_offsets
[regno
] == -1;
369 ia64_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
371 /* Rationale behind not permitting stores to bspstore...
373 The IA-64 architecture provides bspstore and bsp which refer
374 memory locations in the RSE's backing store. bspstore is the
375 next location which will be written when the RSE needs to write
376 to memory. bsp is the address at which r32 in the current frame
377 would be found if it were written to the backing store.
379 The IA-64 architecture provides read-only access to bsp and
380 read/write access to bspstore (but only when the RSE is in
381 the enforced lazy mode). It should be noted that stores
382 to bspstore also affect the value of bsp. Changing bspstore
383 does not affect the number of dirty entries between bspstore
384 and bsp, so changing bspstore by N words will also cause bsp
385 to be changed by (roughly) N as well. (It could be N-1 or N+1
386 depending upon where the NaT collection bits fall.)
388 OTOH, the Linux kernel provides read/write access to bsp (and
389 currently read/write access to bspstore as well). But it
390 is definitely the case that if you change one, the other
391 will change at the same time. It is more useful to gdb to
392 be able to change bsp. So in order to prevent strange and
393 undesirable things from happening when a dummy stack frame
394 is popped (after calling an inferior function), we allow
395 bspstore to be read, but not written. (Note that popping
396 a (generic) dummy stack frame causes all registers that
397 were previously read from the inferior process to be written
401 || regno
>= gdbarch_num_regs (gdbarch
)
402 || u_offsets
[regno
] == -1
403 || regno
== IA64_BSPSTORE_REGNUM
;
407 supply_gregset (struct regcache
*regcache
, const gregset_t
*gregsetp
)
410 const greg_t
*regp
= (const greg_t
*) gregsetp
;
412 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
414 regcache_raw_supply (regcache
, regi
, regp
+ (regi
- IA64_GR0_REGNUM
));
417 /* FIXME: NAT collection bits are at index 32; gotta deal with these
420 regcache_raw_supply (regcache
, IA64_PR_REGNUM
, regp
+ 33);
422 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
424 regcache_raw_supply (regcache
, regi
,
425 regp
+ 34 + (regi
- IA64_BR0_REGNUM
));
428 regcache_raw_supply (regcache
, IA64_IP_REGNUM
, regp
+ 42);
429 regcache_raw_supply (regcache
, IA64_CFM_REGNUM
, regp
+ 43);
430 regcache_raw_supply (regcache
, IA64_PSR_REGNUM
, regp
+ 44);
431 regcache_raw_supply (regcache
, IA64_RSC_REGNUM
, regp
+ 45);
432 regcache_raw_supply (regcache
, IA64_BSP_REGNUM
, regp
+ 46);
433 regcache_raw_supply (regcache
, IA64_BSPSTORE_REGNUM
, regp
+ 47);
434 regcache_raw_supply (regcache
, IA64_RNAT_REGNUM
, regp
+ 48);
435 regcache_raw_supply (regcache
, IA64_CCV_REGNUM
, regp
+ 49);
436 regcache_raw_supply (regcache
, IA64_UNAT_REGNUM
, regp
+ 50);
437 regcache_raw_supply (regcache
, IA64_FPSR_REGNUM
, regp
+ 51);
438 regcache_raw_supply (regcache
, IA64_PFS_REGNUM
, regp
+ 52);
439 regcache_raw_supply (regcache
, IA64_LC_REGNUM
, regp
+ 53);
440 regcache_raw_supply (regcache
, IA64_EC_REGNUM
, regp
+ 54);
444 fill_gregset (const struct regcache
*regcache
, gregset_t
*gregsetp
, int regno
)
447 greg_t
*regp
= (greg_t
*) gregsetp
;
449 #define COPY_REG(_idx_,_regi_) \
450 if ((regno == -1) || regno == _regi_) \
451 regcache_raw_collect (regcache, _regi_, regp + _idx_)
453 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
455 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
458 /* FIXME: NAT collection bits at index 32? */
460 COPY_REG (33, IA64_PR_REGNUM
);
462 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
464 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
467 COPY_REG (42, IA64_IP_REGNUM
);
468 COPY_REG (43, IA64_CFM_REGNUM
);
469 COPY_REG (44, IA64_PSR_REGNUM
);
470 COPY_REG (45, IA64_RSC_REGNUM
);
471 COPY_REG (46, IA64_BSP_REGNUM
);
472 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
473 COPY_REG (48, IA64_RNAT_REGNUM
);
474 COPY_REG (49, IA64_CCV_REGNUM
);
475 COPY_REG (50, IA64_UNAT_REGNUM
);
476 COPY_REG (51, IA64_FPSR_REGNUM
);
477 COPY_REG (52, IA64_PFS_REGNUM
);
478 COPY_REG (53, IA64_LC_REGNUM
);
479 COPY_REG (54, IA64_EC_REGNUM
);
482 /* Given a pointer to a floating point register set in /proc format
483 (fpregset_t *), unpack the register contents and supply them as gdb's
484 idea of the current floating point register values. */
487 supply_fpregset (struct regcache
*regcache
, const fpregset_t
*fpregsetp
)
491 const gdb_byte f_zero
[16] = { 0 };
492 const gdb_byte f_one
[16] =
493 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
495 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
496 did the same. So ignore whatever might be recorded in fpregset_t
497 for fr0/fr1 and always supply their expected values. */
499 /* fr0 is always read as zero. */
500 regcache_raw_supply (regcache
, IA64_FR0_REGNUM
, f_zero
);
501 /* fr1 is always read as one (1.0). */
502 regcache_raw_supply (regcache
, IA64_FR1_REGNUM
, f_one
);
504 for (regi
= IA64_FR2_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
506 from
= (const char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
507 regcache_raw_supply (regcache
, regi
, from
);
511 /* Given a pointer to a floating point register set in /proc format
512 (fpregset_t *), update the register specified by REGNO from gdb's idea
513 of the current floating point register set. If REGNO is -1, update
517 fill_fpregset (const struct regcache
*regcache
,
518 fpregset_t
*fpregsetp
, int regno
)
522 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
524 if ((regno
== -1) || (regno
== regi
))
525 regcache_raw_collect (regcache
, regi
,
526 &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]));
530 #define IA64_PSR_DB (1UL << 24)
531 #define IA64_PSR_DD (1UL << 39)
534 enable_watchpoints_in_psr (ptid_t ptid
)
536 struct regcache
*regcache
= get_thread_regcache (ptid
);
539 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
540 if (!(psr
& IA64_PSR_DB
))
542 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
543 watchpoints and breakpoints. */
544 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
548 static long debug_registers
[8];
551 store_debug_register (ptid_t ptid
, int idx
, long val
)
555 tid
= ptid_get_lwp (ptid
);
557 tid
= ptid_get_pid (ptid
);
559 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), val
);
563 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
,
567 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
569 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
573 is_power_of_2 (int val
)
578 for (i
= 0; i
< 8 * sizeof (val
); i
++)
582 return onecount
<= 1;
586 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr
, int len
,
587 enum target_hw_bp_type type
,
588 struct expression
*cond
)
592 long dbr_addr
, dbr_mask
;
593 int max_watchpoints
= 4;
595 if (len
<= 0 || !is_power_of_2 (len
))
598 for (idx
= 0; idx
< max_watchpoints
; idx
++)
600 dbr_mask
= debug_registers
[idx
* 2 + 1];
601 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
603 /* Exit loop if both r and w bits clear. */
608 if (idx
== max_watchpoints
)
611 dbr_addr
= (long) addr
;
612 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
613 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
617 dbr_mask
|= (1L << 62); /* Set w bit */
620 dbr_mask
|= (1L << 63); /* Set r bit */
623 dbr_mask
|= (3L << 62); /* Set both r and w bits */
629 debug_registers
[2 * idx
] = dbr_addr
;
630 debug_registers
[2 * idx
+ 1] = dbr_mask
;
633 store_debug_register_pair (lp
->ptid
, idx
, &dbr_addr
, &dbr_mask
);
634 enable_watchpoints_in_psr (lp
->ptid
);
641 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr
, int len
,
642 enum target_hw_bp_type type
,
643 struct expression
*cond
)
646 long dbr_addr
, dbr_mask
;
647 int max_watchpoints
= 4;
649 if (len
<= 0 || !is_power_of_2 (len
))
652 for (idx
= 0; idx
< max_watchpoints
; idx
++)
654 dbr_addr
= debug_registers
[2 * idx
];
655 dbr_mask
= debug_registers
[2 * idx
+ 1];
656 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
660 debug_registers
[2 * idx
] = 0;
661 debug_registers
[2 * idx
+ 1] = 0;
666 store_debug_register_pair (lp
->ptid
, idx
, &dbr_addr
, &dbr_mask
);
675 ia64_linux_new_thread (struct lwp_info
*lp
)
680 for (i
= 0; i
< 8; i
++)
682 if (debug_registers
[i
] != 0)
684 store_debug_register (lp
->ptid
, i
, debug_registers
[i
]);
688 enable_watchpoints_in_psr (lp
->ptid
);
692 ia64_linux_nat_target::stopped_data_address (CORE_ADDR
*addr_p
)
696 struct regcache
*regcache
= get_current_regcache ();
698 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
701 if (siginfo
.si_signo
!= SIGTRAP
702 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
705 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
706 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
707 for the next instruction. */
708 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
710 *addr_p
= (CORE_ADDR
) siginfo
.si_addr
;
715 ia64_linux_nat_target::stopped_by_watchpoint ()
718 return stopped_data_address (&addr
);
722 ia64_linux_can_use_hw_breakpoint (struct target_ops
*self
,
724 int cnt
, int othertype
)
730 /* Fetch register REGNUM from the inferior. */
733 ia64_linux_fetch_register (struct regcache
*regcache
, int regnum
)
735 struct gdbarch
*gdbarch
= regcache
->arch ();
738 PTRACE_TYPE_RET
*buf
;
742 /* r0 cannot be fetched but is always zero. */
743 if (regnum
== IA64_GR0_REGNUM
)
745 const gdb_byte zero
[8] = { 0 };
747 gdb_assert (sizeof (zero
) == register_size (gdbarch
, regnum
));
748 regcache_raw_supply (regcache
, regnum
, zero
);
752 /* fr0 cannot be fetched but is always zero. */
753 if (regnum
== IA64_FR0_REGNUM
)
755 const gdb_byte f_zero
[16] = { 0 };
757 gdb_assert (sizeof (f_zero
) == register_size (gdbarch
, regnum
));
758 regcache_raw_supply (regcache
, regnum
, f_zero
);
762 /* fr1 cannot be fetched but is always one (1.0). */
763 if (regnum
== IA64_FR1_REGNUM
)
765 const gdb_byte f_one
[16] =
766 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
768 gdb_assert (sizeof (f_one
) == register_size (gdbarch
, regnum
));
769 regcache_raw_supply (regcache
, regnum
, f_one
);
773 if (ia64_cannot_fetch_register (gdbarch
, regnum
))
775 regcache_raw_supply (regcache
, regnum
, NULL
);
779 pid
= get_ptrace_pid (regcache_get_ptid (regcache
));
781 /* This isn't really an address, but ptrace thinks of it as one. */
782 addr
= ia64_register_addr (gdbarch
, regnum
);
783 size
= register_size (gdbarch
, regnum
);
785 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
786 buf
= (PTRACE_TYPE_RET
*) alloca (size
);
788 /* Read the register contents from the inferior a chunk at a time. */
789 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
792 buf
[i
] = ptrace (PT_READ_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, 0);
794 error (_("Couldn't read register %s (#%d): %s."),
795 gdbarch_register_name (gdbarch
, regnum
),
796 regnum
, safe_strerror (errno
));
798 addr
+= sizeof (PTRACE_TYPE_RET
);
800 regcache_raw_supply (regcache
, regnum
, buf
);
803 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
804 for all registers. */
807 ia64_linux_nat_target::fetch_registers (struct regcache
*regcache
, int regnum
)
811 regnum
< gdbarch_num_regs (regcache
->arch ());
813 ia64_linux_fetch_register (regcache
, regnum
);
815 ia64_linux_fetch_register (regcache
, regnum
);
818 /* Store register REGNUM into the inferior. */
821 ia64_linux_store_register (const struct regcache
*regcache
, int regnum
)
823 struct gdbarch
*gdbarch
= regcache
->arch ();
826 PTRACE_TYPE_RET
*buf
;
830 if (ia64_cannot_store_register (gdbarch
, regnum
))
833 pid
= get_ptrace_pid (regcache_get_ptid (regcache
));
835 /* This isn't really an address, but ptrace thinks of it as one. */
836 addr
= ia64_register_addr (gdbarch
, regnum
);
837 size
= register_size (gdbarch
, regnum
);
839 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
840 buf
= (PTRACE_TYPE_RET
*) alloca (size
);
842 /* Write the register contents into the inferior a chunk at a time. */
843 regcache_raw_collect (regcache
, regnum
, buf
);
844 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
847 ptrace (PT_WRITE_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, buf
[i
]);
849 error (_("Couldn't write register %s (#%d): %s."),
850 gdbarch_register_name (gdbarch
, regnum
),
851 regnum
, safe_strerror (errno
));
853 addr
+= sizeof (PTRACE_TYPE_RET
);
857 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
858 this for all registers. */
861 ia64_linux_nat_target::store_registers (struct regcache
*regcache
, int regnum
)
865 regnum
< gdbarch_num_regs (regcache
->arch ());
867 ia64_linux_store_register (regcache
, regnum
);
869 ia64_linux_store_register (regcache
, regnum
);
872 /* Implement the xfer_partial target_ops method. */
874 enum target_xfer_status
875 ia64_linux_nat_target::xfer_partial (enum target_object object
,
877 gdb_byte
*readbuf
, const gdb_byte
*writebuf
,
878 ULONGEST offset
, ULONGEST len
,
879 ULONGEST
*xfered_len
)
881 if (object
== TARGET_OBJECT_UNWIND_TABLE
&& readbuf
!= NULL
)
883 static long gate_table_size
;
887 /* Probe for the table size once. */
888 if (gate_table_size
== 0)
889 gate_table_size
= syscall (__NR_getunwind
, NULL
, 0);
890 if (gate_table_size
< 0)
891 return TARGET_XFER_E_IO
;
893 if (offset
>= gate_table_size
)
894 return TARGET_XFER_EOF
;
896 tmp_buf
= (gdb_byte
*) alloca (gate_table_size
);
897 res
= syscall (__NR_getunwind
, tmp_buf
, gate_table_size
);
899 return TARGET_XFER_E_IO
;
900 gdb_assert (res
== gate_table_size
);
902 if (offset
+ len
> gate_table_size
)
903 len
= gate_table_size
- offset
;
905 memcpy (readbuf
, tmp_buf
+ offset
, len
);
907 return TARGET_XFER_OK
;
910 return linux_nat_target::xfer_partial (object
, annex
, readbuf
, writebuf
,
911 offset
, len
, xfered_len
);
914 /* For break.b instruction ia64 CPU forgets the immediate value and generates
915 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
916 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
917 difference for the signals here. */
920 ia64_linux_status_is_event (int status
)
922 return WIFSTOPPED (status
) && (WSTOPSIG (status
) == SIGTRAP
923 || WSTOPSIG (status
) == SIGILL
);
927 _initialize_ia64_linux_nat (void)
929 struct target_ops
*t
= &the_ia64_linux_nat_target
;
931 /* Register the target. */
932 linux_target
= &the_ia64_linux_nat_target
;
934 linux_nat_set_new_thread (t
, ia64_linux_new_thread
);
935 linux_nat_set_status_is_event (t
, ia64_linux_status_is_event
);