gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
   5    Free Software Foundation, Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #include "defs.h"
  25 #include "gdb_string.h"
  26 #include "inferior.h"
  27 #include "target.h"
  28 #include "gdbcore.h"
  29 #include "regcache.h"
  30 #include "ia64-tdep.h"
  31
  32 #include <signal.h>
  33 #include <sys/ptrace.h>
  34 #include "gdb_wait.h"
  35 #ifdef HAVE_SYS_REG_H
  36 #include <sys/reg.h>
  37 #endif
  38 #include <sys/syscall.h>
  39 #include <sys/user.h>
  40
  41 #include <asm/ptrace_offsets.h>
  42 #include <sys/procfs.h>
  43
  44 /* Prototypes for supply_gregset etc. */
  45 #include "gregset.h"
  46
  47 /* These must match the order of the register names.
  48
  49    Some sort of lookup table is needed because the offsets associated
  50    with the registers are all over the board.  */
  51
  52 static int u_offsets[] =
  53   {
  54     /* general registers */
  55     -1,         /* gr0 not available; i.e, it's always zero */
  56     PT_R1,
  57     PT_R2,
  58     PT_R3,
  59     PT_R4,
  60     PT_R5,
  61     PT_R6,
  62     PT_R7,
  63     PT_R8,
  64     PT_R9,
  65     PT_R10,
  66     PT_R11,
  67     PT_R12,
  68     PT_R13,
  69     PT_R14,
  70     PT_R15,
  71     PT_R16,
  72     PT_R17,
  73     PT_R18,
  74     PT_R19,
  75     PT_R20,
  76     PT_R21,
  77     PT_R22,
  78     PT_R23,
  79     PT_R24,
  80     PT_R25,
  81     PT_R26,
  82     PT_R27,
  83     PT_R28,
  84     PT_R29,
  85     PT_R30,
  86     PT_R31,
  87     /* gr32 through gr127 not directly available via the ptrace interface */
  88     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  89     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  90     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  91     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  92     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  93     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  94     /* Floating point registers */
  95     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
  96     PT_F2,
  97     PT_F3,
  98     PT_F4,
  99     PT_F5,
 100     PT_F6,
 101     PT_F7,
 102     PT_F8,
 103     PT_F9,
 104     PT_F10,
 105     PT_F11,
 106     PT_F12,
 107     PT_F13,
 108     PT_F14,
 109     PT_F15,
 110     PT_F16,
 111     PT_F17,
 112     PT_F18,
 113     PT_F19,
 114     PT_F20,
 115     PT_F21,
 116     PT_F22,
 117     PT_F23,
 118     PT_F24,
 119     PT_F25,
 120     PT_F26,
 121     PT_F27,
 122     PT_F28,
 123     PT_F29,
 124     PT_F30,
 125     PT_F31,
 126     PT_F32,
 127     PT_F33,
 128     PT_F34,
 129     PT_F35,
 130     PT_F36,
 131     PT_F37,
 132     PT_F38,
 133     PT_F39,
 134     PT_F40,
 135     PT_F41,
 136     PT_F42,
 137     PT_F43,
 138     PT_F44,
 139     PT_F45,
 140     PT_F46,
 141     PT_F47,
 142     PT_F48,
 143     PT_F49,
 144     PT_F50,
 145     PT_F51,
 146     PT_F52,
 147     PT_F53,
 148     PT_F54,
 149     PT_F55,
 150     PT_F56,
 151     PT_F57,
 152     PT_F58,
 153     PT_F59,
 154     PT_F60,
 155     PT_F61,
 156     PT_F62,
 157     PT_F63,
 158     PT_F64,
 159     PT_F65,
 160     PT_F66,
 161     PT_F67,
 162     PT_F68,
 163     PT_F69,
 164     PT_F70,
 165     PT_F71,
 166     PT_F72,
 167     PT_F73,
 168     PT_F74,
 169     PT_F75,
 170     PT_F76,
 171     PT_F77,
 172     PT_F78,
 173     PT_F79,
 174     PT_F80,
 175     PT_F81,
 176     PT_F82,
 177     PT_F83,
 178     PT_F84,
 179     PT_F85,
 180     PT_F86,
 181     PT_F87,
 182     PT_F88,
 183     PT_F89,
 184     PT_F90,
 185     PT_F91,
 186     PT_F92,
 187     PT_F93,
 188     PT_F94,
 189     PT_F95,
 190     PT_F96,
 191     PT_F97,
 192     PT_F98,
 193     PT_F99,
 194     PT_F100,
 195     PT_F101,
 196     PT_F102,
 197     PT_F103,
 198     PT_F104,
 199     PT_F105,
 200     PT_F106,
 201     PT_F107,
 202     PT_F108,
 203     PT_F109,
 204     PT_F110,
 205     PT_F111,
 206     PT_F112,
 207     PT_F113,
 208     PT_F114,
 209     PT_F115,
 210     PT_F116,
 211     PT_F117,
 212     PT_F118,
 213     PT_F119,
 214     PT_F120,
 215     PT_F121,
 216     PT_F122,
 217     PT_F123,
 218     PT_F124,
 219     PT_F125,
 220     PT_F126,
 221     PT_F127,
 222     /* predicate registers - we don't fetch these individually */
 223     -1, -1, -1, -1, -1, -1, -1, -1,
 224     -1, -1, -1, -1, -1, -1, -1, -1,
 225     -1, -1, -1, -1, -1, -1, -1, -1,
 226     -1, -1, -1, -1, -1, -1, -1, -1,
 227     -1, -1, -1, -1, -1, -1, -1, -1,
 228     -1, -1, -1, -1, -1, -1, -1, -1,
 229     -1, -1, -1, -1, -1, -1, -1, -1,
 230     -1, -1, -1, -1, -1, -1, -1, -1,
 231     /* branch registers */
 232     PT_B0,
 233     PT_B1,
 234     PT_B2,
 235     PT_B3,
 236     PT_B4,
 237     PT_B5,
 238     PT_B6,
 239     PT_B7,
 240     /* virtual frame pointer and virtual return address pointer */
 241     -1, -1,
 242     /* other registers */
 243     PT_PR,
 244     PT_CR_IIP,  /* ip */
 245     PT_CR_IPSR, /* psr */
 246     PT_CFM,     /* cfm */
 247     /* kernel registers not visible via ptrace interface (?) */
 248     -1, -1, -1, -1, -1, -1, -1, -1,
 249     /* hole */
 250     -1, -1, -1, -1, -1, -1, -1, -1,
 251     PT_AR_RSC,
 252     PT_AR_BSP,
 253     PT_AR_BSPSTORE,
 254     PT_AR_RNAT,
 255     -1,
 256     -1,         /* Not available: FCR, IA32 floating control register */
 257     -1, -1,
 258     -1,         /* Not available: EFLAG */
 259     -1,         /* Not available: CSD */
 260     -1,         /* Not available: SSD */
 261     -1,         /* Not available: CFLG */
 262     -1,         /* Not available: FSR */
 263     -1,         /* Not available: FIR */
 264     -1,         /* Not available: FDR */
 265     -1,
 266     PT_AR_CCV,
 267     -1, -1, -1,
 268     PT_AR_UNAT,
 269     -1, -1, -1,
 270     PT_AR_FPSR,
 271     -1, -1, -1,
 272     -1,         /* Not available: ITC */
 273     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 274     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 275     PT_AR_PFS,
 276     PT_AR_LC,
 277     -1,         /* Not available: EC, the Epilog Count register */
 278     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 279     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 280     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 281     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 282     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 283     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 284     -1,
 285     /* nat bits - not fetched directly; instead we obtain these bits from
 286        either rnat or unat or from memory. */
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296     -1, -1, -1, -1, -1, -1, -1, -1,
 297     -1, -1, -1, -1, -1, -1, -1, -1,
 298     -1, -1, -1, -1, -1, -1, -1, -1,
 299     -1, -1, -1, -1, -1, -1, -1, -1,
 300     -1, -1, -1, -1, -1, -1, -1, -1,
 301     -1, -1, -1, -1, -1, -1, -1, -1,
 302     -1, -1, -1, -1, -1, -1, -1, -1,
 303   };
 304
 305 CORE_ADDR
 306 register_addr (int regno, CORE_ADDR blockend)
 307 {
 308   CORE_ADDR addr;
 309
 310   if (regno < 0 || regno >= NUM_REGS)
 311     error ("Invalid register number %d.", regno);
 312
 313   if (u_offsets[regno] == -1)
 314     addr = 0;
 315   else
 316     addr = (CORE_ADDR) u_offsets[regno];
 317
 318   return addr;
 319 }
 320
 321 int ia64_cannot_fetch_register (regno)
 322      int regno;
 323 {
 324   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
 325 }
 326
 327 int ia64_cannot_store_register (regno)
 328      int regno;
 329 {
 330   /* Rationale behind not permitting stores to bspstore...
 331
 332      The IA-64 architecture provides bspstore and bsp which refer
 333      memory locations in the RSE's backing store.  bspstore is the
 334      next location which will be written when the RSE needs to write
 335      to memory.  bsp is the address at which r32 in the current frame
 336      would be found if it were written to the backing store.
 337
 338      The IA-64 architecture provides read-only access to bsp and
 339      read/write access to bspstore (but only when the RSE is in
 340      the enforced lazy mode).  It should be noted that stores
 341      to bspstore also affect the value of bsp.  Changing bspstore
 342      does not affect the number of dirty entries between bspstore
 343      and bsp, so changing bspstore by N words will also cause bsp
 344      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 345      depending upon where the NaT collection bits fall.)
 346
 347      OTOH, the Linux kernel provides read/write access to bsp (and
 348      currently read/write access to bspstore as well).  But it
 349      is definitely the case that if you change one, the other
 350      will change at the same time.  It is more useful to gdb to
 351      be able to change bsp.  So in order to prevent strange and
 352      undesirable things from happening when a dummy stack frame
 353      is popped (after calling an inferior function), we allow
 354      bspstore to be read, but not written.  (Note that popping
 355      a (generic) dummy stack frame causes all registers that
 356      were previously read from the inferior process to be written
 357      back.)  */
 358
 359   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
 360          || regno == IA64_BSPSTORE_REGNUM;
 361 }
 362
 363 void
 364 supply_gregset (gregset_t *gregsetp)
 365 {
 366   int regi;
 367   greg_t *regp = (greg_t *) gregsetp;
 368
 369   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 370     {
 371       regcache_raw_supply (current_regcache, regi,
 372                            (char *) (regp + (regi - IA64_GR0_REGNUM)));
 373     }
 374
 375   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 376      somehow... */
 377
 378   regcache_raw_supply (current_regcache, IA64_PR_REGNUM, (char *) (regp + 33));
 379
 380   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 381     {
 382       regcache_raw_supply (current_regcache, regi,
 383                            (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
 384     }
 385
 386   regcache_raw_supply (current_regcache, IA64_IP_REGNUM,
 387                        (char *) (regp + 42));
 388   regcache_raw_supply (current_regcache, IA64_CFM_REGNUM,
 389                        (char *) (regp + 43));
 390   regcache_raw_supply (current_regcache, IA64_PSR_REGNUM,
 391                        (char *) (regp + 44));
 392   regcache_raw_supply (current_regcache, IA64_RSC_REGNUM,
 393                        (char *) (regp + 45));
 394   regcache_raw_supply (current_regcache, IA64_BSP_REGNUM,
 395                        (char *) (regp + 46));
 396   regcache_raw_supply (current_regcache, IA64_BSPSTORE_REGNUM,
 397                        (char *) (regp + 47));
 398   regcache_raw_supply (current_regcache, IA64_RNAT_REGNUM,
 399                        (char *) (regp + 48));
 400   regcache_raw_supply (current_regcache, IA64_CCV_REGNUM,
 401                        (char *) (regp + 49));
 402   regcache_raw_supply (current_regcache, IA64_UNAT_REGNUM,
 403                        (char *) (regp + 50));
 404   regcache_raw_supply (current_regcache, IA64_FPSR_REGNUM,
 405                        (char *) (regp + 51));
 406   regcache_raw_supply (current_regcache, IA64_PFS_REGNUM,
 407                        (char *) (regp + 52));
 408   regcache_raw_supply (current_regcache, IA64_LC_REGNUM,
 409                        (char *) (regp + 53));
 410   regcache_raw_supply (current_regcache, IA64_EC_REGNUM,
 411                        (char *) (regp + 54));
 412 }
 413
 414 void
 415 fill_gregset (gregset_t *gregsetp, int regno)
 416 {
 417   int regi;
 418   greg_t *regp = (greg_t *) gregsetp;
 419
 420 #define COPY_REG(_idx_,_regi_) \
 421   if ((regno == -1) || regno == _regi_) \
 422     regcache_raw_collect (current_regcache, _regi_, regp + _idx_)
 423
 424   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 425     {
 426       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 427     }
 428
 429   /* FIXME: NAT collection bits at index 32? */
 430
 431   COPY_REG (33, IA64_PR_REGNUM);
 432
 433   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 434     {
 435       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 436     }
 437
 438   COPY_REG (42, IA64_IP_REGNUM);
 439   COPY_REG (43, IA64_CFM_REGNUM);
 440   COPY_REG (44, IA64_PSR_REGNUM);
 441   COPY_REG (45, IA64_RSC_REGNUM);
 442   COPY_REG (46, IA64_BSP_REGNUM);
 443   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 444   COPY_REG (48, IA64_RNAT_REGNUM);
 445   COPY_REG (49, IA64_CCV_REGNUM);
 446   COPY_REG (50, IA64_UNAT_REGNUM);
 447   COPY_REG (51, IA64_FPSR_REGNUM);
 448   COPY_REG (52, IA64_PFS_REGNUM);
 449   COPY_REG (53, IA64_LC_REGNUM);
 450   COPY_REG (54, IA64_EC_REGNUM);
 451 }
 452
 453 /*  Given a pointer to a floating point register set in /proc format
 454    (fpregset_t *), unpack the register contents and supply them as gdb's
 455    idea of the current floating point register values. */
 456
 457 void
 458 supply_fpregset (fpregset_t *fpregsetp)
 459 {
 460   int regi;
 461   char *from;
 462
 463   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 464     {
 465       from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 466       regcache_raw_supply (current_regcache, regi, from);
 467     }
 468 }
 469
 470 /*  Given a pointer to a floating point register set in /proc format
 471    (fpregset_t *), update the register specified by REGNO from gdb's idea
 472    of the current floating point register set.  If REGNO is -1, update
 473    them all. */
 474
 475 void
 476 fill_fpregset (fpregset_t *fpregsetp, int regno)
 477 {
 478   int regi;
 479
 480   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 481     {
 482       if ((regno == -1) || (regno == regi))
 483         regcache_raw_collect (current_regcache, regi,
 484                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 485     }
 486 }
 487
 488 #define IA64_PSR_DB (1UL << 24)
 489 #define IA64_PSR_DD (1UL << 39)
 490
 491 static void
 492 enable_watchpoints_in_psr (ptid_t ptid)
 493 {
 494   CORE_ADDR psr;
 495
 496   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 497   if (!(psr & IA64_PSR_DB))
 498     {
 499       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 500                                    watchpoints and breakpoints. */
 501       write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 502     }
 503 }
 504
 505 static long
 506 fetch_debug_register (ptid_t ptid, int idx)
 507 {
 508   long val;
 509   int tid;
 510
 511   tid = TIDGET (ptid);
 512   if (tid == 0)
 513     tid = PIDGET (ptid);
 514
 515   val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);
 516
 517   return val;
 518 }
 519
 520 static void
 521 store_debug_register (ptid_t ptid, int idx, long val)
 522 {
 523   int tid;
 524
 525   tid = TIDGET (ptid);
 526   if (tid == 0)
 527     tid = PIDGET (ptid);
 528
 529   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 530 }
 531
 532 static void
 533 fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 534 {
 535   if (dbr_addr)
 536     *dbr_addr = fetch_debug_register (ptid, 2 * idx);
 537   if (dbr_mask)
 538     *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
 539 }
 540
 541 static void
 542 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 543 {
 544   if (dbr_addr)
 545     store_debug_register (ptid, 2 * idx, *dbr_addr);
 546   if (dbr_mask)
 547     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 548 }
 549
 550 static int
 551 is_power_of_2 (int val)
 552 {
 553   int i, onecount;
 554
 555   onecount = 0;
 556   for (i = 0; i < 8 * sizeof (val); i++)
 557     if (val & (1 << i))
 558       onecount++;
 559
 560   return onecount <= 1;
 561 }
 562
 563 int
 564 ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
 565 {
 566   int idx;
 567   long dbr_addr, dbr_mask;
 568   int max_watchpoints = 4;
 569
 570   if (len <= 0 || !is_power_of_2 (len))
 571     return -1;
 572
 573   for (idx = 0; idx < max_watchpoints; idx++)
 574     {
 575       fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
 576       if ((dbr_mask & (0x3UL << 62)) == 0)
 577         {
 578           /* Exit loop if both r and w bits clear */
 579           break;
 580         }
 581     }
 582
 583   if (idx == max_watchpoints)
 584     return -1;
 585
 586   dbr_addr = (long) addr;
 587   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 588   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 589   switch (rw)
 590     {
 591     case hw_write:
 592       dbr_mask |= (1L << 62);                   /* Set w bit */
 593       break;
 594     case hw_read:
 595       dbr_mask |= (1L << 63);                   /* Set r bit */
 596       break;
 597     case hw_access:
 598       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 599       break;
 600     default:
 601       return -1;
 602     }
 603
 604   store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 605   enable_watchpoints_in_psr (ptid);
 606
 607   return 0;
 608 }
 609
 610 int
 611 ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
 612 {
 613   int idx;
 614   long dbr_addr, dbr_mask;
 615   int max_watchpoints = 4;
 616
 617   if (len <= 0 || !is_power_of_2 (len))
 618     return -1;
 619
 620   for (idx = 0; idx < max_watchpoints; idx++)
 621     {
 622       fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 623       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 624         {
 625           dbr_addr = 0;
 626           dbr_mask = 0;
 627           store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 628           return 0;
 629         }
 630     }
 631   return -1;
 632 }
 633
 634 int
 635 ia64_linux_stopped_data_address (CORE_ADDR *addr_p)
 636 {
 637   CORE_ADDR psr;
 638   int tid;
 639   struct siginfo siginfo;
 640   ptid_t ptid = inferior_ptid;
 641
 642   tid = TIDGET(ptid);
 643   if (tid == 0)
 644     tid = PIDGET (ptid);
 645
 646   errno = 0;
 647   ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
 648
 649   if (errno != 0 || siginfo.si_signo != SIGTRAP ||
 650       (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 651     return 0;
 652
 653   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 654   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 655                            for the next instruction */
 656   write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 657
 658   *addr_p = (CORE_ADDR)siginfo.si_addr;
 659   return 1;
 660 }
 661
 662 int
 663 ia64_linux_stopped_by_watchpoint (void)
 664 {
 665   CORE_ADDR addr;
 666   return ia64_linux_stopped_data_address (&addr);
 667 }
 668
 669 LONGEST
 670 ia64_linux_xfer_unwind_table (struct target_ops *ops,
 671                               enum target_object object,
 672                               const char *annex,
 673                               void *readbuf, const void *writebuf,
 674                               ULONGEST offset, LONGEST len)
 675 {
 676   return syscall (__NR_getunwind, readbuf, len);
 677 }