1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "symfile.h" /* for entry_point_address */
26 #include "arch-utils.h"
27 #include "floatformat.h"
29 #include "reggroups.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
35 #include "gdb_assert.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
40 /* Hook for determining the global pointer when calling functions in
41 the inferior under AIX. The initialization code in ia64-aix-nat.c
42 sets this hook to the address of a function which will find the
43 global pointer for a given address.
45 The generic code which uses the dynamic section in the inferior for
46 finding the global pointer is not of much use on AIX since the
47 values obtained from the inferior have not been relocated. */
49 CORE_ADDR (*native_find_global_pointer
) (CORE_ADDR
) = 0;
51 /* An enumeration of the different IA-64 instruction types. */
53 typedef enum instruction_type
55 A
, /* Integer ALU ; I-unit or M-unit */
56 I
, /* Non-ALU integer; I-unit */
57 M
, /* Memory ; M-unit */
58 F
, /* Floating-point ; F-unit */
59 B
, /* Branch ; B-unit */
60 L
, /* Extended (L+X) ; I-unit */
61 X
, /* Extended (L+X) ; I-unit */
62 undefined
/* undefined or reserved */
65 /* We represent IA-64 PC addresses as the value of the instruction
66 pointer or'd with some bit combination in the low nibble which
67 represents the slot number in the bundle addressed by the
68 instruction pointer. The problem is that the Linux kernel
69 multiplies its slot numbers (for exceptions) by one while the
70 disassembler multiplies its slot numbers by 6. In addition, I've
71 heard it said that the simulator uses 1 as the multiplier.
73 I've fixed the disassembler so that the bytes_per_line field will
74 be the slot multiplier. If bytes_per_line comes in as zero, it
75 is set to six (which is how it was set up initially). -- objdump
76 displays pretty disassembly dumps with this value. For our purposes,
77 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
78 never want to also display the raw bytes the way objdump does. */
80 #define SLOT_MULTIPLIER 1
82 /* Length in bytes of an instruction bundle */
86 /* FIXME: These extern declarations should go in ia64-tdep.h. */
87 extern CORE_ADDR
ia64_linux_sigcontext_register_address (CORE_ADDR
, int);
88 extern CORE_ADDR
ia64_aix_sigcontext_register_address (CORE_ADDR
, int);
90 static gdbarch_init_ftype ia64_gdbarch_init
;
92 static gdbarch_register_name_ftype ia64_register_name
;
93 static gdbarch_register_type_ftype ia64_register_type
;
94 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc
;
95 static gdbarch_skip_prologue_ftype ia64_skip_prologue
;
96 static gdbarch_extract_return_value_ftype ia64_extract_return_value
;
97 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address
;
98 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention
;
99 static struct type
*is_float_or_hfa_type (struct type
*t
);
101 static struct type
*builtin_type_ia64_ext
;
103 #define NUM_IA64_RAW_REGS 462
105 static int sp_regnum
= IA64_GR12_REGNUM
;
106 static int fp_regnum
= IA64_VFP_REGNUM
;
107 static int lr_regnum
= IA64_VRAP_REGNUM
;
109 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
110 they are in memory and must be calculated via the bsp register. */
111 enum pseudo_regs
{ FIRST_PSEUDO_REGNUM
= NUM_IA64_RAW_REGS
, VBOF_REGNUM
= IA64_NAT127_REGNUM
+ 1, V32_REGNUM
,
112 V127_REGNUM
= V32_REGNUM
+ 95,
113 VP0_REGNUM
, VP16_REGNUM
= VP0_REGNUM
+ 16, VP63_REGNUM
= VP0_REGNUM
+ 63, LAST_PSEUDO_REGNUM
};
115 /* Array of register names; There should be ia64_num_regs strings in
118 static char *ia64_register_names
[] =
119 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
136 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
137 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
138 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
139 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
140 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
141 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
142 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
143 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
144 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
145 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
146 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
147 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
148 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
149 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
150 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
151 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
162 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
166 "pr", "ip", "psr", "cfm",
168 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
169 "", "", "", "", "", "", "", "",
170 "rsc", "bsp", "bspstore", "rnat",
172 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
173 "ccv", "", "", "", "unat", "", "", "",
174 "fpsr", "", "", "", "itc",
175 "", "", "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
185 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
186 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
187 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
188 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
189 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
190 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
191 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
192 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
193 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
194 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
195 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
196 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
197 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
198 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
199 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
200 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
204 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
205 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
206 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
207 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
208 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
209 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
210 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
211 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
212 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
213 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
214 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
215 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
217 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
218 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
219 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
220 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
221 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
222 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
223 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
224 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
227 struct ia64_frame_cache
229 CORE_ADDR base
; /* frame pointer base for frame */
230 CORE_ADDR pc
; /* function start pc for frame */
231 CORE_ADDR saved_sp
; /* stack pointer for frame */
232 CORE_ADDR bsp
; /* points at r32 for the current frame */
233 CORE_ADDR cfm
; /* cfm value for current frame */
235 int sof
; /* Size of frame (decoded from cfm value) */
236 int sol
; /* Size of locals (decoded from cfm value) */
237 int sor
; /* Number of rotating registers. (decoded from cfm value) */
238 CORE_ADDR after_prologue
;
239 /* Address of first instruction after the last
240 prologue instruction; Note that there may
241 be instructions from the function's body
242 intermingled with the prologue. */
243 int mem_stack_frame_size
;
244 /* Size of the memory stack frame (may be zero),
245 or -1 if it has not been determined yet. */
246 int fp_reg
; /* Register number (if any) used a frame pointer
247 for this frame. 0 if no register is being used
248 as the frame pointer. */
250 /* Saved registers. */
251 CORE_ADDR saved_regs
[NUM_IA64_RAW_REGS
];
257 int os_ident
; /* From the ELF header, one of the ELFOSABI_
258 constants: ELFOSABI_LINUX, ELFOSABI_AIX,
260 CORE_ADDR (*sigcontext_register_address
) (CORE_ADDR
, int);
261 /* OS specific function which, given a frame address
262 and register number, returns the offset to the
263 given register from the start of the frame. */
264 CORE_ADDR (*find_global_pointer
) (CORE_ADDR
);
267 #define SIGCONTEXT_REGISTER_ADDRESS \
268 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
269 #define FIND_GLOBAL_POINTER \
270 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
273 ia64_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
274 struct reggroup
*group
)
279 if (group
== all_reggroup
)
281 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
282 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
283 raw_p
= regnum
< NUM_IA64_RAW_REGS
;
284 if (group
== float_reggroup
)
286 if (group
== vector_reggroup
)
288 if (group
== general_reggroup
)
289 return (!vector_p
&& !float_p
);
290 if (group
== save_reggroup
|| group
== restore_reggroup
)
296 ia64_register_name (int reg
)
298 return ia64_register_names
[reg
];
302 ia64_register_type (struct gdbarch
*arch
, int reg
)
304 if (reg
>= IA64_FR0_REGNUM
&& reg
<= IA64_FR127_REGNUM
)
305 return builtin_type_ia64_ext
;
307 return builtin_type_long
;
311 ia64_dwarf_reg_to_regnum (int reg
)
313 if (reg
>= IA64_GR32_REGNUM
&& reg
<= IA64_GR127_REGNUM
)
314 return V32_REGNUM
+ (reg
- IA64_GR32_REGNUM
);
318 const struct floatformat floatformat_ia64_ext
=
320 floatformat_little
, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
321 floatformat_intbit_yes
325 /* Read the given register from a sigcontext structure in the
329 read_sigcontext_register (struct frame_info
*frame
, int regnum
)
334 internal_error (__FILE__
, __LINE__
,
335 "read_sigcontext_register: NULL frame");
336 if (!(get_frame_type (frame
) == SIGTRAMP_FRAME
))
337 internal_error (__FILE__
, __LINE__
,
338 "read_sigcontext_register: frame not a signal trampoline");
339 if (SIGCONTEXT_REGISTER_ADDRESS
== 0)
340 internal_error (__FILE__
, __LINE__
,
341 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
343 regaddr
= SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame
), regnum
);
345 return read_memory_integer (regaddr
, REGISTER_RAW_SIZE (regnum
));
347 internal_error (__FILE__
, __LINE__
,
348 "read_sigcontext_register: Register %d not in struct sigcontext", regnum
);
351 /* Extract ``len'' bits from an instruction bundle starting at
355 extract_bit_field (char *bundle
, int from
, int len
)
357 long long result
= 0LL;
359 int from_byte
= from
/ 8;
360 int to_byte
= to
/ 8;
361 unsigned char *b
= (unsigned char *) bundle
;
367 if (from_byte
== to_byte
)
368 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
369 result
= c
>> (from
% 8);
370 lshift
= 8 - (from
% 8);
372 for (i
= from_byte
+1; i
< to_byte
; i
++)
374 result
|= ((long long) b
[i
]) << lshift
;
378 if (from_byte
< to_byte
&& (to
% 8 != 0))
381 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
382 result
|= ((long long) c
) << lshift
;
388 /* Replace the specified bits in an instruction bundle */
391 replace_bit_field (char *bundle
, long long val
, int from
, int len
)
394 int from_byte
= from
/ 8;
395 int to_byte
= to
/ 8;
396 unsigned char *b
= (unsigned char *) bundle
;
399 if (from_byte
== to_byte
)
401 unsigned char left
, right
;
403 left
= (c
>> (to
% 8)) << (to
% 8);
404 right
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
405 c
= (unsigned char) (val
& 0xff);
406 c
= (unsigned char) (c
<< (from
% 8 + 8 - to
% 8)) >> (8 - to
% 8);
414 c
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
415 c
= c
| (val
<< (from
% 8));
417 val
>>= 8 - from
% 8;
419 for (i
= from_byte
+1; i
< to_byte
; i
++)
428 unsigned char cv
= (unsigned char) val
;
430 c
= c
>> (to
% 8) << (to
% 8);
431 c
|= ((unsigned char) (cv
<< (8 - to
% 8))) >> (8 - to
% 8);
437 /* Return the contents of slot N (for N = 0, 1, or 2) in
438 and instruction bundle */
441 slotN_contents (char *bundle
, int slotnum
)
443 return extract_bit_field (bundle
, 5+41*slotnum
, 41);
446 /* Store an instruction in an instruction bundle */
449 replace_slotN_contents (char *bundle
, long long instr
, int slotnum
)
451 replace_bit_field (bundle
, instr
, 5+41*slotnum
, 41);
454 static enum instruction_type template_encoding_table
[32][3] =
456 { M
, I
, I
}, /* 00 */
457 { M
, I
, I
}, /* 01 */
458 { M
, I
, I
}, /* 02 */
459 { M
, I
, I
}, /* 03 */
460 { M
, L
, X
}, /* 04 */
461 { M
, L
, X
}, /* 05 */
462 { undefined
, undefined
, undefined
}, /* 06 */
463 { undefined
, undefined
, undefined
}, /* 07 */
464 { M
, M
, I
}, /* 08 */
465 { M
, M
, I
}, /* 09 */
466 { M
, M
, I
}, /* 0A */
467 { M
, M
, I
}, /* 0B */
468 { M
, F
, I
}, /* 0C */
469 { M
, F
, I
}, /* 0D */
470 { M
, M
, F
}, /* 0E */
471 { M
, M
, F
}, /* 0F */
472 { M
, I
, B
}, /* 10 */
473 { M
, I
, B
}, /* 11 */
474 { M
, B
, B
}, /* 12 */
475 { M
, B
, B
}, /* 13 */
476 { undefined
, undefined
, undefined
}, /* 14 */
477 { undefined
, undefined
, undefined
}, /* 15 */
478 { B
, B
, B
}, /* 16 */
479 { B
, B
, B
}, /* 17 */
480 { M
, M
, B
}, /* 18 */
481 { M
, M
, B
}, /* 19 */
482 { undefined
, undefined
, undefined
}, /* 1A */
483 { undefined
, undefined
, undefined
}, /* 1B */
484 { M
, F
, B
}, /* 1C */
485 { M
, F
, B
}, /* 1D */
486 { undefined
, undefined
, undefined
}, /* 1E */
487 { undefined
, undefined
, undefined
}, /* 1F */
490 /* Fetch and (partially) decode an instruction at ADDR and return the
491 address of the next instruction to fetch. */
494 fetch_instruction (CORE_ADDR addr
, instruction_type
*it
, long long *instr
)
496 char bundle
[BUNDLE_LEN
];
497 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
501 /* Warn about slot numbers greater than 2. We used to generate
502 an error here on the assumption that the user entered an invalid
503 address. But, sometimes GDB itself requests an invalid address.
504 This can (easily) happen when execution stops in a function for
505 which there are no symbols. The prologue scanner will attempt to
506 find the beginning of the function - if the nearest symbol
507 happens to not be aligned on a bundle boundary (16 bytes), the
508 resulting starting address will cause GDB to think that the slot
511 So we warn about it and set the slot number to zero. It is
512 not necessarily a fatal condition, particularly if debugging
513 at the assembly language level. */
516 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
517 "Using slot 0 instead");
523 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
528 *instr
= slotN_contents (bundle
, slotnum
);
529 template = extract_bit_field (bundle
, 0, 5);
530 *it
= template_encoding_table
[(int)template][slotnum
];
532 if (slotnum
== 2 || (slotnum
== 1 && *it
== L
))
535 addr
+= (slotnum
+ 1) * SLOT_MULTIPLIER
;
540 /* There are 5 different break instructions (break.i, break.b,
541 break.m, break.f, and break.x), but they all have the same
542 encoding. (The five bit template in the low five bits of the
543 instruction bundle distinguishes one from another.)
545 The runtime architecture manual specifies that break instructions
546 used for debugging purposes must have the upper two bits of the 21
547 bit immediate set to a 0 and a 1 respectively. A breakpoint
548 instruction encodes the most significant bit of its 21 bit
549 immediate at bit 36 of the 41 bit instruction. The penultimate msb
550 is at bit 25 which leads to the pattern below.
552 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
553 it turns out that 0x80000 was used as the syscall break in the early
554 simulators. So I changed the pattern slightly to do "break.i 0x080001"
555 instead. But that didn't work either (I later found out that this
556 pattern was used by the simulator that I was using.) So I ended up
557 using the pattern seen below. */
560 #define IA64_BREAKPOINT 0x00002000040LL
562 #define IA64_BREAKPOINT 0x00003333300LL
565 ia64_memory_insert_breakpoint (CORE_ADDR addr
, char *contents_cache
)
567 char bundle
[BUNDLE_LEN
];
568 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
574 error("Can't insert breakpoint for slot numbers greater than 2.");
578 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
580 /* Check for L type instruction in 2nd slot, if present then
581 bump up the slot number to the 3rd slot */
582 template = extract_bit_field (bundle
, 0, 5);
583 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
588 instr
= slotN_contents (bundle
, slotnum
);
589 memcpy(contents_cache
, &instr
, sizeof(instr
));
590 replace_slotN_contents (bundle
, IA64_BREAKPOINT
, slotnum
);
592 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
598 ia64_memory_remove_breakpoint (CORE_ADDR addr
, char *contents_cache
)
600 char bundle
[BUNDLE_LEN
];
601 int slotnum
= (addr
& 0x0f) / SLOT_MULTIPLIER
;
608 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
610 /* Check for L type instruction in 2nd slot, if present then
611 bump up the slot number to the 3rd slot */
612 template = extract_bit_field (bundle
, 0, 5);
613 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
618 memcpy (&instr
, contents_cache
, sizeof instr
);
619 replace_slotN_contents (bundle
, instr
, slotnum
);
621 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
626 /* We don't really want to use this, but remote.c needs to call it in order
627 to figure out if Z-packets are supported or not. Oh, well. */
628 const unsigned char *
629 ia64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
631 static unsigned char breakpoint
[] =
632 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
633 *lenptr
= sizeof (breakpoint
);
643 /* We won't necessarily have a frame pointer and even if we do, it
644 winds up being extraordinarly messy when attempting to find the
645 frame chain. So for the purposes of creating frames (which is
646 all deprecated_read_fp() is used for), simply use the stack
647 pointer value instead. */
648 gdb_assert (SP_REGNUM
>= 0);
649 return read_register (SP_REGNUM
);
653 ia64_read_pc (ptid_t ptid
)
655 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
656 CORE_ADDR pc_value
= read_register_pid (IA64_IP_REGNUM
, ptid
);
657 int slot_num
= (psr_value
>> 41) & 3;
659 return pc_value
| (slot_num
* SLOT_MULTIPLIER
);
663 ia64_write_pc (CORE_ADDR new_pc
, ptid_t ptid
)
665 int slot_num
= (int) (new_pc
& 0xf) / SLOT_MULTIPLIER
;
666 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
667 psr_value
&= ~(3LL << 41);
668 psr_value
|= (CORE_ADDR
)(slot_num
& 0x3) << 41;
672 write_register_pid (IA64_PSR_REGNUM
, psr_value
, ptid
);
673 write_register_pid (IA64_IP_REGNUM
, new_pc
, ptid
);
676 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
678 /* Returns the address of the slot that's NSLOTS slots away from
679 the address ADDR. NSLOTS may be positive or negative. */
681 rse_address_add(CORE_ADDR addr
, int nslots
)
684 int mandatory_nat_slots
= nslots
/ 63;
685 int direction
= nslots
< 0 ? -1 : 1;
687 new_addr
= addr
+ 8 * (nslots
+ mandatory_nat_slots
);
689 if ((new_addr
>> 9) != ((addr
+ 8 * 64 * mandatory_nat_slots
) >> 9))
690 new_addr
+= 8 * direction
;
692 if (IS_NaT_COLLECTION_ADDR(new_addr
))
693 new_addr
+= 8 * direction
;
699 ia64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
700 int regnum
, void *buf
)
702 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
707 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
708 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
710 /* The bsp points at the end of the register frame so we
711 subtract the size of frame from it to get start of register frame. */
712 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
714 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
716 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
717 reg
= read_memory_integer ((CORE_ADDR
)reg_addr
, 8);
718 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), reg
);
721 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), 0);
723 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
727 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
728 unatN_val
= (unat
& (1LL << (regnum
- IA64_NAT0_REGNUM
))) != 0;
729 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), unatN_val
);
731 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
733 ULONGEST natN_val
= 0;
736 CORE_ADDR gr_addr
= 0;
737 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
738 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
740 /* The bsp points at the end of the register frame so we
741 subtract the size of frame from it to get start of register frame. */
742 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
744 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
745 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
749 /* Compute address of nat collection bits. */
750 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
751 CORE_ADDR nat_collection
;
753 /* If our nat collection address is bigger than bsp, we have to get
754 the nat collection from rnat. Otherwise, we fetch the nat
755 collection from the computed address. */
757 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
759 nat_collection
= read_memory_integer (nat_addr
, 8);
760 nat_bit
= (gr_addr
>> 3) & 0x3f;
761 natN_val
= (nat_collection
>> nat_bit
) & 1;
764 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), natN_val
);
766 else if (regnum
== VBOF_REGNUM
)
768 /* A virtual register frame start is provided for user convenience.
769 It can be calculated as the bsp - sof (sizeof frame). */
773 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
774 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
776 /* The bsp points at the end of the register frame so we
777 subtract the size of frame from it to get beginning of frame. */
778 vbsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
779 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), vbsp
);
781 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
787 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
788 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
790 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
792 /* Fetch predicate register rename base from current frame
793 marker for this frame. */
794 int rrb_pr
= (cfm
>> 32) & 0x3f;
796 /* Adjust the register number to account for register rotation. */
798 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
800 prN_val
= (pr
& (1LL << (regnum
- VP0_REGNUM
))) != 0;
801 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), prN_val
);
804 memset (buf
, 0, REGISTER_RAW_SIZE (regnum
));
808 ia64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
809 int regnum
, const void *buf
)
811 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
816 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
817 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
819 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
821 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
823 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
824 write_memory (reg_addr
, (void *)buf
, 8);
827 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
829 ULONGEST unatN_val
, unat
, unatN_mask
;
830 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
831 unatN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
832 unatN_mask
= (1LL << (regnum
- IA64_NAT0_REGNUM
));
835 else if (unatN_val
== 1)
837 regcache_cooked_write_unsigned (regcache
, IA64_UNAT_REGNUM
, unat
);
839 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
844 CORE_ADDR gr_addr
= 0;
845 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
846 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
848 /* The bsp points at the end of the register frame so we
849 subtract the size of frame from it to get start of register frame. */
850 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
852 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
853 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
855 natN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
857 if (gr_addr
!= 0 && (natN_val
== 0 || natN_val
== 1))
859 /* Compute address of nat collection bits. */
860 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
861 CORE_ADDR nat_collection
;
862 int natN_bit
= (gr_addr
>> 3) & 0x3f;
863 ULONGEST natN_mask
= (1LL << natN_bit
);
864 /* If our nat collection address is bigger than bsp, we have to get
865 the nat collection from rnat. Otherwise, we fetch the nat
866 collection from the computed address. */
869 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
871 nat_collection
|= natN_mask
;
873 nat_collection
&= ~natN_mask
;
874 regcache_cooked_write_unsigned (regcache
, IA64_RNAT_REGNUM
, nat_collection
);
879 nat_collection
= read_memory_integer (nat_addr
, 8);
881 nat_collection
|= natN_mask
;
883 nat_collection
&= ~natN_mask
;
884 store_unsigned_integer (nat_buf
, REGISTER_RAW_SIZE (regnum
), nat_collection
);
885 write_memory (nat_addr
, nat_buf
, 8);
889 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
896 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
897 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
899 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
901 /* Fetch predicate register rename base from current frame
902 marker for this frame. */
903 int rrb_pr
= (cfm
>> 32) & 0x3f;
905 /* Adjust the register number to account for register rotation. */
907 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
909 prN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
910 prN_mask
= (1LL << (regnum
- VP0_REGNUM
));
913 else if (prN_val
== 1)
915 regcache_cooked_write_unsigned (regcache
, IA64_PR_REGNUM
, pr
);
919 /* The ia64 needs to convert between various ieee floating-point formats
920 and the special ia64 floating point register format. */
923 ia64_convert_register_p (int regno
, struct type
*type
)
925 return (regno
>= IA64_FR0_REGNUM
&& regno
<= IA64_FR127_REGNUM
);
929 ia64_register_to_value (struct frame_info
*frame
, int regnum
,
930 struct type
*valtype
, void *out
)
932 char in
[MAX_REGISTER_SIZE
];
933 frame_register_read (frame
, regnum
, in
);
934 convert_typed_floating (in
, builtin_type_ia64_ext
, out
, valtype
);
938 ia64_value_to_register (struct frame_info
*frame
, int regnum
,
939 struct type
*valtype
, const void *in
)
941 char out
[MAX_REGISTER_SIZE
];
942 convert_typed_floating (in
, valtype
, out
, builtin_type_ia64_ext
);
943 put_frame_register (frame
, regnum
, out
);
947 /* Limit the number of skipped non-prologue instructions since examining
948 of the prologue is expensive. */
949 static int max_skip_non_prologue_insns
= 40;
951 /* Given PC representing the starting address of a function, and
952 LIM_PC which is the (sloppy) limit to which to scan when looking
953 for a prologue, attempt to further refine this limit by using
954 the line data in the symbol table. If successful, a better guess
955 on where the prologue ends is returned, otherwise the previous
956 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
957 which will be set to indicate whether the returned limit may be
958 used with no further scanning in the event that the function is
962 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
, int *trust_limit
)
964 struct symtab_and_line prologue_sal
;
965 CORE_ADDR start_pc
= pc
;
967 /* Start off not trusting the limit. */
970 prologue_sal
= find_pc_line (pc
, 0);
971 if (prologue_sal
.line
!= 0)
974 CORE_ADDR addr
= prologue_sal
.end
;
976 /* Handle the case in which compiler's optimizer/scheduler
977 has moved instructions into the prologue. We scan ahead
978 in the function looking for address ranges whose corresponding
979 line number is less than or equal to the first one that we
980 found for the function. (It can be less than when the
981 scheduler puts a body instruction before the first prologue
983 for (i
= 2 * max_skip_non_prologue_insns
;
984 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
987 struct symtab_and_line sal
;
989 sal
= find_pc_line (addr
, 0);
992 if (sal
.line
<= prologue_sal
.line
993 && sal
.symtab
== prologue_sal
.symtab
)
1000 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
1002 lim_pc
= prologue_sal
.end
;
1003 if (start_pc
== get_pc_function_start (lim_pc
))
1010 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1011 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1012 || (14 <= (_regnum_) && (_regnum_) <= 31))
1013 #define imm9(_instr_) \
1014 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1015 | (((_instr_) & 0x00008000000LL) >> 20) \
1016 | (((_instr_) & 0x00000001fc0LL) >> 6))
1018 /* Allocate and initialize a frame cache. */
1020 static struct ia64_frame_cache
*
1021 ia64_alloc_frame_cache (void)
1023 struct ia64_frame_cache
*cache
;
1026 cache
= FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache
);
1037 cache
->frameless
= 1;
1039 for (i
= 0; i
< NUM_IA64_RAW_REGS
; i
++)
1040 cache
->saved_regs
[i
] = 0;
1046 examine_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct frame_info
*next_frame
, struct ia64_frame_cache
*cache
)
1049 CORE_ADDR last_prologue_pc
= pc
;
1050 instruction_type it
;
1055 int unat_save_reg
= 0;
1056 int pr_save_reg
= 0;
1057 int mem_stack_frame_size
= 0;
1059 CORE_ADDR spill_addr
= 0;
1062 char reg_contents
[256];
1068 CORE_ADDR bof
, sor
, sol
, sof
, cfm
, rrb_gr
;
1070 memset (instores
, 0, sizeof instores
);
1071 memset (infpstores
, 0, sizeof infpstores
);
1072 memset (reg_contents
, 0, sizeof reg_contents
);
1074 if (cache
->after_prologue
!= 0
1075 && cache
->after_prologue
<= lim_pc
)
1076 return cache
->after_prologue
;
1078 lim_pc
= refine_prologue_limit (pc
, lim_pc
, &trust_limit
);
1079 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1081 /* We want to check if we have a recognizable function start before we
1082 look ahead for a prologue. */
1083 if (pc
< lim_pc
&& next_pc
1084 && it
== M
&& ((instr
& 0x1ee0000003fLL
) == 0x02c00000000LL
))
1086 /* alloc - start of a regular function. */
1087 int sor
= (int) ((instr
& 0x00078000000LL
) >> 27);
1088 int sol
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1089 int sof
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1090 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1092 /* Verify that the current cfm matches what we think is the
1093 function start. If we have somehow jumped within a function,
1094 we do not want to interpret the prologue and calculate the
1095 addresses of various registers such as the return address.
1096 We will instead treat the frame as frameless. */
1098 (sof
== (cache
->cfm
& 0x7f) &&
1099 sol
== ((cache
->cfm
>> 7) & 0x7f)))
1103 last_prologue_pc
= next_pc
;
1108 /* Look for a leaf routine. */
1109 if (pc
< lim_pc
&& next_pc
1110 && (it
== I
|| it
== M
)
1111 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1113 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1114 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1115 | ((instr
& 0x001f8000000LL
) >> 20)
1116 | ((instr
& 0x000000fe000LL
) >> 13));
1117 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1118 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1119 int qp
= (int) (instr
& 0x0000000003fLL
);
1120 if (qp
== 0 && rN
== 2 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1122 /* mov r2, r12 - beginning of leaf routine */
1124 last_prologue_pc
= next_pc
;
1128 /* If we don't recognize a regular function or leaf routine, we are
1134 last_prologue_pc
= lim_pc
;
1138 /* Loop, looking for prologue instructions, keeping track of
1139 where preserved registers were spilled. */
1142 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1146 if (it
== B
&& ((instr
& 0x1e1f800003f) != 0x04000000000))
1148 /* Exit loop upon hitting a non-nop branch instruction. */
1153 else if (((instr
& 0x3fLL
) != 0LL) &&
1154 (frameless
|| ret_reg
!= 0))
1156 /* Exit loop upon hitting a predicated instruction if
1157 we already have the return register or if we are frameless. */
1162 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00188000000LL
))
1165 int b2
= (int) ((instr
& 0x0000000e000LL
) >> 13);
1166 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1167 int qp
= (int) (instr
& 0x0000000003f);
1169 if (qp
== 0 && b2
== 0 && rN
>= 32 && ret_reg
== 0)
1172 last_prologue_pc
= next_pc
;
1175 else if ((it
== I
|| it
== M
)
1176 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1178 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1179 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1180 | ((instr
& 0x001f8000000LL
) >> 20)
1181 | ((instr
& 0x000000fe000LL
) >> 13));
1182 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1183 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1184 int qp
= (int) (instr
& 0x0000000003fLL
);
1186 if (qp
== 0 && rN
>= 32 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1190 last_prologue_pc
= next_pc
;
1192 else if (qp
== 0 && rN
== 12 && rM
== 12)
1194 /* adds r12, -mem_stack_frame_size, r12 */
1195 mem_stack_frame_size
-= imm
;
1196 last_prologue_pc
= next_pc
;
1198 else if (qp
== 0 && rN
== 2
1199 && ((rM
== fp_reg
&& fp_reg
!= 0) || rM
== 12))
1201 char buf
[MAX_REGISTER_SIZE
];
1202 CORE_ADDR saved_sp
= 0;
1203 /* adds r2, spilloffset, rFramePointer
1205 adds r2, spilloffset, r12
1207 Get ready for stf.spill or st8.spill instructions.
1208 The address to start spilling at is loaded into r2.
1209 FIXME: Why r2? That's what gcc currently uses; it
1210 could well be different for other compilers. */
1212 /* Hmm... whether or not this will work will depend on
1213 where the pc is. If it's still early in the prologue
1214 this'll be wrong. FIXME */
1217 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1218 saved_sp
= extract_unsigned_integer (buf
, 8);
1220 spill_addr
= saved_sp
1221 + (rM
== 12 ? 0 : mem_stack_frame_size
)
1224 last_prologue_pc
= next_pc
;
1226 else if (qp
== 0 && rM
>= 32 && rM
< 40 && !instores
[rM
] &&
1227 rN
< 256 && imm
== 0)
1229 /* mov rN, rM where rM is an input register */
1230 reg_contents
[rN
] = rM
;
1231 last_prologue_pc
= next_pc
;
1233 else if (frameless
&& qp
== 0 && rN
== fp_reg
&& imm
== 0 &&
1237 last_prologue_pc
= next_pc
;
1242 && ( ((instr
& 0x1efc0000000LL
) == 0x0eec0000000LL
)
1243 || ((instr
& 0x1ffc8000000LL
) == 0x0cec0000000LL
) ))
1245 /* stf.spill [rN] = fM, imm9
1247 stf.spill [rN] = fM */
1249 int imm
= imm9(instr
);
1250 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1251 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1252 int qp
= (int) (instr
& 0x0000000003fLL
);
1253 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1254 && ((2 <= fM
&& fM
<= 5) || (16 <= fM
&& fM
<= 31)))
1256 cache
->saved_regs
[IA64_FR0_REGNUM
+ fM
] = spill_addr
;
1258 if ((instr
& 0x1efc0000000) == 0x0eec0000000)
1261 spill_addr
= 0; /* last one; must be done */
1262 last_prologue_pc
= next_pc
;
1265 else if ((it
== M
&& ((instr
& 0x1eff8000000LL
) == 0x02110000000LL
))
1266 || (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00050000000LL
)) )
1272 int arM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1273 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1274 int qp
= (int) (instr
& 0x0000000003fLL
);
1275 if (qp
== 0 && isScratch (rN
) && arM
== 36 /* ar.unat */)
1277 /* We have something like "mov.m r3 = ar.unat". Remember the
1278 r3 (or whatever) and watch for a store of this register... */
1280 last_prologue_pc
= next_pc
;
1283 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00198000000LL
))
1286 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1287 int qp
= (int) (instr
& 0x0000000003fLL
);
1288 if (qp
== 0 && isScratch (rN
))
1291 last_prologue_pc
= next_pc
;
1295 && ( ((instr
& 0x1ffc8000000LL
) == 0x08cc0000000LL
)
1296 || ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)))
1300 st8 [rN] = rM, imm9 */
1301 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1302 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1303 int qp
= (int) (instr
& 0x0000000003fLL
);
1304 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1305 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1306 && (rM
== unat_save_reg
|| rM
== pr_save_reg
))
1308 /* We've found a spill of either the UNAT register or the PR
1309 register. (Well, not exactly; what we've actually found is
1310 a spill of the register that UNAT or PR was moved to).
1311 Record that fact and move on... */
1312 if (rM
== unat_save_reg
)
1314 /* Track UNAT register */
1315 cache
->saved_regs
[IA64_UNAT_REGNUM
] = spill_addr
;
1320 /* Track PR register */
1321 cache
->saved_regs
[IA64_PR_REGNUM
] = spill_addr
;
1324 if ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)
1325 /* st8 [rN] = rM, imm9 */
1326 spill_addr
+= imm9(instr
);
1328 spill_addr
= 0; /* must be done spilling */
1329 last_prologue_pc
= next_pc
;
1331 else if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1333 /* Allow up to one store of each input register. */
1334 instores
[rM
-32] = 1;
1335 last_prologue_pc
= next_pc
;
1337 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1338 !instores
[indirect
-32])
1340 /* Allow an indirect store of an input register. */
1341 instores
[indirect
-32] = 1;
1342 last_prologue_pc
= next_pc
;
1345 else if (it
== M
&& ((instr
& 0x1ff08000000LL
) == 0x08c00000000LL
))
1352 Note that the st8 case is handled in the clause above.
1354 Advance over stores of input registers. One store per input
1355 register is permitted. */
1356 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1357 int qp
= (int) (instr
& 0x0000000003fLL
);
1358 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1359 if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1361 instores
[rM
-32] = 1;
1362 last_prologue_pc
= next_pc
;
1364 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1365 !instores
[indirect
-32])
1367 /* Allow an indirect store of an input register. */
1368 instores
[indirect
-32] = 1;
1369 last_prologue_pc
= next_pc
;
1372 else if (it
== M
&& ((instr
& 0x1ff88000000LL
) == 0x0cc80000000LL
))
1379 Advance over stores of floating point input registers. Again
1380 one store per register is permitted */
1381 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1382 int qp
= (int) (instr
& 0x0000000003fLL
);
1383 if (qp
== 0 && 8 <= fM
&& fM
< 16 && !infpstores
[fM
- 8])
1385 infpstores
[fM
-8] = 1;
1386 last_prologue_pc
= next_pc
;
1390 && ( ((instr
& 0x1ffc8000000LL
) == 0x08ec0000000LL
)
1391 || ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)))
1393 /* st8.spill [rN] = rM
1395 st8.spill [rN] = rM, imm9 */
1396 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1397 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1398 int qp
= (int) (instr
& 0x0000000003fLL
);
1399 if (qp
== 0 && rN
== spill_reg
&& 4 <= rM
&& rM
<= 7)
1401 /* We've found a spill of one of the preserved general purpose
1402 regs. Record the spill address and advance the spill
1403 register if appropriate. */
1404 cache
->saved_regs
[IA64_GR0_REGNUM
+ rM
] = spill_addr
;
1405 if ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)
1406 /* st8.spill [rN] = rM, imm9 */
1407 spill_addr
+= imm9(instr
);
1409 spill_addr
= 0; /* Done spilling */
1410 last_prologue_pc
= next_pc
;
1417 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1418 registers for the previous frame which will be needed later. */
1420 if (!frameless
&& next_frame
)
1422 /* Extract the size of the rotating portion of the stack
1423 frame and the register rename base from the current
1429 rrb_gr
= (cfm
>> 18) & 0x7f;
1431 /* Find the bof (beginning of frame). */
1432 bof
= rse_address_add (cache
->bsp
, -sof
);
1434 for (i
= 0, addr
= bof
;
1438 if (IS_NaT_COLLECTION_ADDR (addr
))
1442 if (i
+32 == cfm_reg
)
1443 cache
->saved_regs
[IA64_CFM_REGNUM
] = addr
;
1444 if (i
+32 == ret_reg
)
1445 cache
->saved_regs
[IA64_VRAP_REGNUM
] = addr
;
1447 cache
->saved_regs
[IA64_VFP_REGNUM
] = addr
;
1450 /* For the previous argument registers we require the previous bof.
1451 If we can't find the previous cfm, then we can do nothing. */
1452 if (cache
->saved_regs
[IA64_CFM_REGNUM
] != 0)
1454 cfm
= read_memory_integer (cache
->saved_regs
[IA64_CFM_REGNUM
], 8);
1455 sor
= ((cfm
>> 14) & 0xf) * 8;
1457 sol
= (cfm
>> 7) & 0x7f;
1458 rrb_gr
= (cfm
>> 18) & 0x7f;
1460 /* The previous bof only requires subtraction of the sol (size of locals)
1461 due to the overlap between output and input of subsequent frames. */
1462 bof
= rse_address_add (bof
, -sol
);
1464 for (i
= 0, addr
= bof
;
1468 if (IS_NaT_COLLECTION_ADDR (addr
))
1473 cache
->saved_regs
[IA64_GR32_REGNUM
+ ((i
+ (sor
- rrb_gr
)) % sor
)]
1476 cache
->saved_regs
[IA64_GR32_REGNUM
+ i
] = addr
;
1482 /* Try and trust the lim_pc value whenever possible. */
1483 if (trust_limit
&& lim_pc
>= last_prologue_pc
)
1484 last_prologue_pc
= lim_pc
;
1486 cache
->frameless
= frameless
;
1487 cache
->after_prologue
= last_prologue_pc
;
1488 cache
->mem_stack_frame_size
= mem_stack_frame_size
;
1489 cache
->fp_reg
= fp_reg
;
1491 return last_prologue_pc
;
1495 ia64_skip_prologue (CORE_ADDR pc
)
1497 struct ia64_frame_cache cache
;
1499 cache
.after_prologue
= 0;
1503 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1504 return examine_prologue (pc
, pc
+1024, 0, &cache
);
1508 /* Normal frames. */
1510 static struct ia64_frame_cache
*
1511 ia64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1513 struct ia64_frame_cache
*cache
;
1515 CORE_ADDR cfm
, sof
, sol
, bsp
, psr
;
1521 cache
= ia64_alloc_frame_cache ();
1522 *this_cache
= cache
;
1524 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1525 cache
->saved_sp
= extract_unsigned_integer (buf
, 8);
1527 /* We always want the bsp to point to the end of frame.
1528 This way, we can always get the beginning of frame (bof)
1529 by subtracting frame size. */
1530 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1531 cache
->bsp
= extract_unsigned_integer (buf
, 8);
1533 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1534 psr
= extract_unsigned_integer (buf
, 8);
1536 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
1537 cfm
= extract_unsigned_integer (buf
, 8);
1539 cache
->sof
= (cfm
& 0x7f);
1540 cache
->sol
= (cfm
>> 7) & 0x7f;
1541 cache
->sor
= ((cfm
>> 14) & 0xf) * 8;
1545 cache
->pc
= frame_func_unwind (next_frame
);
1548 examine_prologue (cache
->pc
, frame_pc_unwind (next_frame
), next_frame
, cache
);
1550 cache
->base
= cache
->saved_sp
+ cache
->mem_stack_frame_size
;
1556 ia64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1557 struct frame_id
*this_id
)
1559 struct ia64_frame_cache
*cache
=
1560 ia64_frame_cache (next_frame
, this_cache
);
1562 /* This marks the outermost frame. */
1563 if (cache
->base
== 0)
1566 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1570 ia64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1571 int regnum
, int *optimizedp
,
1572 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1573 int *realnump
, void *valuep
)
1575 struct ia64_frame_cache
*cache
=
1576 ia64_frame_cache (next_frame
, this_cache
);
1577 char dummy_valp
[MAX_REGISTER_SIZE
];
1580 gdb_assert (regnum
>= 0);
1582 if (!target_has_registers
)
1583 error ("No registers.");
1590 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1591 when valuep is not supplied. */
1593 valuep
= dummy_valp
;
1595 memset (valuep
, 0, REGISTER_RAW_SIZE (regnum
));
1597 if (regnum
== SP_REGNUM
)
1599 /* Handle SP values for all frames but the topmost. */
1600 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1603 else if (regnum
== IA64_BSP_REGNUM
)
1605 char cfm_valuep
[MAX_REGISTER_SIZE
];
1608 enum lval_type cfm_lval
;
1610 CORE_ADDR bsp
, prev_cfm
, prev_bsp
;
1612 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1613 This corresponds to what the hardware bsp register will be if we pop the frame
1614 back which is why we might have been called. We know the beginning of the current
1615 frame is cache->bsp - cache->sof. This value in the previous frame points to
1616 the start of the output registers. We can calculate the end of that frame by adding
1617 the size of output (sof (size of frame) - sol (size of locals)). */
1618 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1619 &cfm_optim
, &cfm_lval
, &cfm_addr
, &cfm_realnum
, cfm_valuep
);
1620 prev_cfm
= extract_unsigned_integer (cfm_valuep
, 8);
1622 bsp
= rse_address_add (cache
->bsp
, -(cache
->sof
));
1623 prev_bsp
= rse_address_add (bsp
, (prev_cfm
& 0x7f) - ((prev_cfm
>> 7) & 0x7f));
1625 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1628 else if (regnum
== IA64_CFM_REGNUM
)
1632 if (cache
->frameless
)
1635 frame_unwind_register (next_frame
, IA64_PFS_REGNUM
, valuep
);
1639 addr
= cache
->saved_regs
[IA64_CFM_REGNUM
];
1641 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1644 else if (regnum
== IA64_VFP_REGNUM
)
1646 /* If the function in question uses an automatic register (r32-r127)
1647 for the frame pointer, it'll be found by ia64_find_saved_register()
1648 above. If the function lacks one of these frame pointers, we can
1649 still provide a value since we know the size of the frame. */
1650 CORE_ADDR vfp
= cache
->base
;
1651 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (IA64_VFP_REGNUM
), vfp
);
1653 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1655 char pr_valuep
[MAX_REGISTER_SIZE
];
1658 enum lval_type pr_lval
;
1661 ia64_frame_prev_register (next_frame
, this_cache
, IA64_PR_REGNUM
,
1662 &pr_optim
, &pr_lval
, &pr_addr
, &pr_realnum
, pr_valuep
);
1663 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1665 /* Fetch predicate register rename base from current frame
1666 marker for this frame. */
1667 int rrb_pr
= (cache
->cfm
>> 32) & 0x3f;
1669 /* Adjust the register number to account for register rotation. */
1670 regnum
= VP16_REGNUM
1671 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
1673 prN_val
= extract_bit_field ((unsigned char *) pr_valuep
,
1674 regnum
- VP0_REGNUM
, 1);
1675 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
), prN_val
);
1677 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
1679 char unat_valuep
[MAX_REGISTER_SIZE
];
1682 enum lval_type unat_lval
;
1683 CORE_ADDR unat_addr
;
1685 ia64_frame_prev_register (next_frame
, this_cache
, IA64_UNAT_REGNUM
,
1686 &unat_optim
, &unat_lval
, &unat_addr
, &unat_realnum
, unat_valuep
);
1687 unatN_val
= extract_bit_field ((unsigned char *) unat_valuep
,
1688 regnum
- IA64_NAT0_REGNUM
, 1);
1689 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1692 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
1695 /* Find address of general register corresponding to nat bit we're
1699 gr_addr
= cache
->saved_regs
[regnum
- IA64_NAT0_REGNUM
1703 /* Compute address of nat collection bits. */
1704 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
1706 CORE_ADDR nat_collection
;
1708 /* If our nat collection address is bigger than bsp, we have to get
1709 the nat collection from rnat. Otherwise, we fetch the nat
1710 collection from the computed address. */
1711 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1712 bsp
= extract_unsigned_integer (buf
, 8);
1713 if (nat_addr
>= bsp
)
1715 frame_unwind_register (next_frame
, IA64_RNAT_REGNUM
, buf
);
1716 nat_collection
= extract_unsigned_integer (buf
, 8);
1719 nat_collection
= read_memory_integer (nat_addr
, 8);
1720 nat_bit
= (gr_addr
>> 3) & 0x3f;
1721 natval
= (nat_collection
>> nat_bit
) & 1;
1724 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
), natval
);
1726 else if (regnum
== IA64_IP_REGNUM
)
1730 if (cache
->frameless
)
1732 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1733 pc
= extract_unsigned_integer (buf
, 8);
1737 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1740 read_memory (addr
, buf
, REGISTER_RAW_SIZE (IA64_IP_REGNUM
));
1741 pc
= extract_unsigned_integer (buf
, 8);
1745 store_unsigned_integer (valuep
, 8, pc
);
1747 else if (regnum
== IA64_PSR_REGNUM
)
1749 ULONGEST slot_num
= 0;
1753 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1754 psr
= extract_unsigned_integer (buf
, 8);
1756 if (cache
->frameless
)
1759 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1760 pc
= extract_unsigned_integer (buf
, 8);
1764 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1767 read_memory (addr
, buf
, REGISTER_RAW_SIZE (IA64_IP_REGNUM
));
1768 pc
= extract_unsigned_integer (buf
, 8);
1771 psr
&= ~(3LL << 41);
1772 slot_num
= pc
& 0x3LL
;
1773 psr
|= (CORE_ADDR
)slot_num
<< 41;
1774 store_unsigned_integer (valuep
, 8, psr
);
1776 else if ((regnum
>= IA64_GR32_REGNUM
&& regnum
<= IA64_GR127_REGNUM
) ||
1777 (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
))
1780 if (regnum
>= V32_REGNUM
)
1781 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1782 addr
= cache
->saved_regs
[regnum
];
1785 *lvalp
= lval_memory
;
1787 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1789 else if (cache
->frameless
)
1791 char r_valuep
[MAX_REGISTER_SIZE
];
1794 enum lval_type r_lval
;
1796 CORE_ADDR prev_cfm
, prev_bsp
, prev_bof
;
1798 if (regnum
>= V32_REGNUM
)
1799 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1800 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1801 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1802 prev_cfm
= extract_unsigned_integer (r_valuep
, 8);
1803 ia64_frame_prev_register (next_frame
, this_cache
, IA64_BSP_REGNUM
,
1804 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1805 prev_bsp
= extract_unsigned_integer (r_valuep
, 8);
1806 prev_bof
= rse_address_add (prev_bsp
, -(prev_cfm
& 0x7f));
1808 addr
= rse_address_add (prev_bof
, (regnum
- IA64_GR32_REGNUM
));
1809 *lvalp
= lval_memory
;
1811 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1817 if (IA64_FR32_REGNUM
<= regnum
&& regnum
<= IA64_FR127_REGNUM
)
1819 /* Fetch floating point register rename base from current
1820 frame marker for this frame. */
1821 int rrb_fr
= (cache
->cfm
>> 25) & 0x7f;
1823 /* Adjust the floating point register number to account for
1824 register rotation. */
1825 regnum
= IA64_FR32_REGNUM
1826 + ((regnum
- IA64_FR32_REGNUM
) + rrb_fr
) % 96;
1829 /* If we have stored a memory address, access the register. */
1830 addr
= cache
->saved_regs
[regnum
];
1833 *lvalp
= lval_memory
;
1835 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1837 /* Otherwise, punt and get the current value of the register. */
1839 frame_unwind_register (next_frame
, regnum
, valuep
);
1843 static const struct frame_unwind ia64_frame_unwind
=
1846 &ia64_frame_this_id
,
1847 &ia64_frame_prev_register
1850 static const struct frame_unwind
*
1851 ia64_frame_sniffer (struct frame_info
*next_frame
)
1853 return &ia64_frame_unwind
;
1856 /* Signal trampolines. */
1859 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache
*cache
)
1861 if (SIGCONTEXT_REGISTER_ADDRESS
)
1865 cache
->saved_regs
[IA64_VRAP_REGNUM
] =
1866 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_IP_REGNUM
);
1867 cache
->saved_regs
[IA64_CFM_REGNUM
] =
1868 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CFM_REGNUM
);
1869 cache
->saved_regs
[IA64_PSR_REGNUM
] =
1870 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PSR_REGNUM
);
1872 cache
->saved_regs
[IA64_BSP_REGNUM
] =
1873 SIGCONTEXT_REGISTER_ADDRESS (frame
->frame
, IA64_BSP_REGNUM
);
1875 cache
->saved_regs
[IA64_RNAT_REGNUM
] =
1876 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_RNAT_REGNUM
);
1877 cache
->saved_regs
[IA64_CCV_REGNUM
] =
1878 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CCV_REGNUM
);
1879 cache
->saved_regs
[IA64_UNAT_REGNUM
] =
1880 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_UNAT_REGNUM
);
1881 cache
->saved_regs
[IA64_FPSR_REGNUM
] =
1882 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_FPSR_REGNUM
);
1883 cache
->saved_regs
[IA64_PFS_REGNUM
] =
1884 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PFS_REGNUM
);
1885 cache
->saved_regs
[IA64_LC_REGNUM
] =
1886 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_LC_REGNUM
);
1887 for (regno
= IA64_GR1_REGNUM
; regno
<= IA64_GR31_REGNUM
; regno
++)
1888 if (regno
!= sp_regnum
)
1889 cache
->saved_regs
[regno
] =
1890 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1891 for (regno
= IA64_BR0_REGNUM
; regno
<= IA64_BR7_REGNUM
; regno
++)
1892 cache
->saved_regs
[regno
] =
1893 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1894 for (regno
= IA64_FR2_REGNUM
; regno
<= IA64_BR7_REGNUM
; regno
++)
1895 cache
->saved_regs
[regno
] =
1896 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1900 static struct ia64_frame_cache
*
1901 ia64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1903 struct ia64_frame_cache
*cache
;
1911 cache
= ia64_alloc_frame_cache ();
1913 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1914 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->mem_stack_frame_size
;
1916 ia64_sigtramp_frame_init_saved_regs (cache
);
1918 *this_cache
= cache
;
1923 ia64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
1924 void **this_cache
, struct frame_id
*this_id
)
1926 struct ia64_frame_cache
*cache
=
1927 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1929 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
1933 ia64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
1935 int regnum
, int *optimizedp
,
1936 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1937 int *realnump
, void *valuep
)
1939 /* Make sure we've initialized the cache. */
1940 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1942 ia64_frame_prev_register (next_frame
, this_cache
, regnum
,
1943 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1946 static const struct frame_unwind ia64_sigtramp_frame_unwind
=
1949 ia64_sigtramp_frame_this_id
,
1950 ia64_sigtramp_frame_prev_register
1953 static const struct frame_unwind
*
1954 ia64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
1957 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1959 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1960 if (PC_IN_SIGTRAMP (pc
, name
))
1961 return &ia64_sigtramp_frame_unwind
;
1968 ia64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1970 struct ia64_frame_cache
*cache
=
1971 ia64_frame_cache (next_frame
, this_cache
);
1976 static const struct frame_base ia64_frame_base
=
1979 ia64_frame_base_address
,
1980 ia64_frame_base_address
,
1981 ia64_frame_base_address
1984 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
1985 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
1986 and TYPE is the type (which is known to be struct, union or array). */
1988 ia64_use_struct_convention (int gcc_p
, struct type
*type
)
1990 struct type
*float_elt_type
;
1992 /* HFAs are structures (or arrays) consisting entirely of floating
1993 point values of the same length. Up to 8 of these are returned
1994 in registers. Don't use the struct convention when this is the
1996 float_elt_type
= is_float_or_hfa_type (type
);
1997 if (float_elt_type
!= NULL
1998 && TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
) <= 8)
2001 /* Other structs of length 32 or less are returned in r8-r11.
2002 Don't use the struct convention for those either. */
2003 return TYPE_LENGTH (type
) > 32;
2007 ia64_extract_return_value (struct type
*type
, struct regcache
*regcache
, void *valbuf
)
2009 struct type
*float_elt_type
;
2011 float_elt_type
= is_float_or_hfa_type (type
);
2012 if (float_elt_type
!= NULL
)
2014 char from
[MAX_REGISTER_SIZE
];
2016 int regnum
= IA64_FR8_REGNUM
;
2017 int n
= TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
);
2021 regcache_cooked_read (regcache
, regnum
, from
);
2022 convert_typed_floating (from
, builtin_type_ia64_ext
,
2023 (char *)valbuf
+ offset
, float_elt_type
);
2024 offset
+= TYPE_LENGTH (float_elt_type
);
2032 int regnum
= IA64_GR8_REGNUM
;
2033 int reglen
= TYPE_LENGTH (ia64_register_type (NULL
, IA64_GR8_REGNUM
));
2034 int n
= TYPE_LENGTH (type
) / reglen
;
2035 int m
= TYPE_LENGTH (type
) % reglen
;
2040 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2041 memcpy ((char *)valbuf
+ offset
, &val
, reglen
);
2048 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2049 memcpy ((char *)valbuf
+ offset
, &val
, m
);
2055 ia64_extract_struct_value_address (struct regcache
*regcache
)
2057 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2063 is_float_or_hfa_type_recurse (struct type
*t
, struct type
**etp
)
2065 switch (TYPE_CODE (t
))
2069 return TYPE_LENGTH (*etp
) == TYPE_LENGTH (t
);
2076 case TYPE_CODE_ARRAY
:
2078 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t
)),
2081 case TYPE_CODE_STRUCT
:
2085 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2086 if (!is_float_or_hfa_type_recurse
2087 (check_typedef (TYPE_FIELD_TYPE (t
, i
)), etp
))
2098 /* Determine if the given type is one of the floating point types or
2099 and HFA (which is a struct, array, or combination thereof whose
2100 bottom-most elements are all of the same floating point type). */
2102 static struct type
*
2103 is_float_or_hfa_type (struct type
*t
)
2105 struct type
*et
= 0;
2107 return is_float_or_hfa_type_recurse (t
, &et
) ? et
: 0;
2111 /* Return 1 if the alignment of T is such that the next even slot
2112 should be used. Return 0, if the next available slot should
2113 be used. (See section 8.5.1 of the IA-64 Software Conventions
2114 and Runtime manual). */
2117 slot_alignment_is_next_even (struct type
*t
)
2119 switch (TYPE_CODE (t
))
2123 if (TYPE_LENGTH (t
) > 8)
2127 case TYPE_CODE_ARRAY
:
2129 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t
)));
2130 case TYPE_CODE_STRUCT
:
2134 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2135 if (slot_alignment_is_next_even
2136 (check_typedef (TYPE_FIELD_TYPE (t
, i
))))
2145 /* Attempt to find (and return) the global pointer for the given
2148 This is a rather nasty bit of code searchs for the .dynamic section
2149 in the objfile corresponding to the pc of the function we're trying
2150 to call. Once it finds the addresses at which the .dynamic section
2151 lives in the child process, it scans the Elf64_Dyn entries for a
2152 DT_PLTGOT tag. If it finds one of these, the corresponding
2153 d_un.d_ptr value is the global pointer. */
2156 generic_elf_find_global_pointer (CORE_ADDR faddr
)
2158 struct obj_section
*faddr_sect
;
2160 faddr_sect
= find_pc_section (faddr
);
2161 if (faddr_sect
!= NULL
)
2163 struct obj_section
*osect
;
2165 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2167 if (strcmp (osect
->the_bfd_section
->name
, ".dynamic") == 0)
2171 if (osect
< faddr_sect
->objfile
->sections_end
)
2176 while (addr
< osect
->endaddr
)
2182 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2185 tag
= extract_signed_integer (buf
, sizeof (buf
));
2187 if (tag
== DT_PLTGOT
)
2189 CORE_ADDR global_pointer
;
2191 status
= target_read_memory (addr
+ 8, buf
, sizeof (buf
));
2194 global_pointer
= extract_unsigned_integer (buf
, sizeof (buf
));
2197 return global_pointer
;
2210 /* Given a function's address, attempt to find (and return) the
2211 corresponding (canonical) function descriptor. Return 0 if
2214 find_extant_func_descr (CORE_ADDR faddr
)
2216 struct obj_section
*faddr_sect
;
2218 /* Return early if faddr is already a function descriptor. */
2219 faddr_sect
= find_pc_section (faddr
);
2220 if (faddr_sect
&& strcmp (faddr_sect
->the_bfd_section
->name
, ".opd") == 0)
2223 if (faddr_sect
!= NULL
)
2225 struct obj_section
*osect
;
2226 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2228 if (strcmp (osect
->the_bfd_section
->name
, ".opd") == 0)
2232 if (osect
< faddr_sect
->objfile
->sections_end
)
2237 while (addr
< osect
->endaddr
)
2243 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2246 faddr2
= extract_signed_integer (buf
, sizeof (buf
));
2248 if (faddr
== faddr2
)
2258 /* Attempt to find a function descriptor corresponding to the
2259 given address. If none is found, construct one on the
2260 stack using the address at fdaptr. */
2263 find_func_descr (CORE_ADDR faddr
, CORE_ADDR
*fdaptr
)
2267 fdesc
= find_extant_func_descr (faddr
);
2271 CORE_ADDR global_pointer
;
2277 global_pointer
= FIND_GLOBAL_POINTER (faddr
);
2279 if (global_pointer
== 0)
2280 global_pointer
= read_register (IA64_GR1_REGNUM
);
2282 store_unsigned_integer (buf
, 8, faddr
);
2283 store_unsigned_integer (buf
+ 8, 8, global_pointer
);
2285 write_memory (fdesc
, buf
, 16);
2291 /* Use the following routine when printing out function pointers
2292 so the user can see the function address rather than just the
2293 function descriptor. */
2295 ia64_convert_from_func_ptr_addr (CORE_ADDR addr
)
2297 struct obj_section
*s
;
2299 s
= find_pc_section (addr
);
2301 /* check if ADDR points to a function descriptor. */
2302 if (s
&& strcmp (s
->the_bfd_section
->name
, ".opd") == 0)
2303 return read_memory_unsigned_integer (addr
, 8);
2309 ia64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2315 ia64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2316 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2317 int nargs
, struct value
**args
, CORE_ADDR sp
,
2318 int struct_return
, CORE_ADDR struct_addr
)
2324 int nslots
, rseslots
, memslots
, slotnum
, nfuncargs
;
2326 CORE_ADDR bsp
, cfm
, pfs
, new_bsp
, funcdescaddr
, pc
, global_pointer
;
2330 /* Count the number of slots needed for the arguments. */
2331 for (argno
= 0; argno
< nargs
; argno
++)
2334 type
= check_typedef (VALUE_TYPE (arg
));
2335 len
= TYPE_LENGTH (type
);
2337 if ((nslots
& 1) && slot_alignment_is_next_even (type
))
2340 if (TYPE_CODE (type
) == TYPE_CODE_FUNC
)
2343 nslots
+= (len
+ 7) / 8;
2346 /* Divvy up the slots between the RSE and the memory stack. */
2347 rseslots
= (nslots
> 8) ? 8 : nslots
;
2348 memslots
= nslots
- rseslots
;
2350 /* Allocate a new RSE frame. */
2351 cfm
= read_register (IA64_CFM_REGNUM
);
2353 bsp
= read_register (IA64_BSP_REGNUM
);
2354 new_bsp
= rse_address_add (bsp
, rseslots
);
2355 write_register (IA64_BSP_REGNUM
, new_bsp
);
2357 pfs
= read_register (IA64_PFS_REGNUM
);
2358 pfs
&= 0xc000000000000000LL
;
2359 pfs
|= (cfm
& 0xffffffffffffLL
);
2360 write_register (IA64_PFS_REGNUM
, pfs
);
2362 cfm
&= 0xc000000000000000LL
;
2364 write_register (IA64_CFM_REGNUM
, cfm
);
2366 /* We will attempt to find function descriptors in the .opd segment,
2367 but if we can't we'll construct them ourselves. That being the
2368 case, we'll need to reserve space on the stack for them. */
2369 funcdescaddr
= sp
- nfuncargs
* 16;
2370 funcdescaddr
&= ~0xfLL
;
2372 /* Adjust the stack pointer to it's new value. The calling conventions
2373 require us to have 16 bytes of scratch, plus whatever space is
2374 necessary for the memory slots and our function descriptors. */
2375 sp
= sp
- 16 - (memslots
+ nfuncargs
) * 8;
2376 sp
&= ~0xfLL
; /* Maintain 16 byte alignment. */
2378 /* Place the arguments where they belong. The arguments will be
2379 either placed in the RSE backing store or on the memory stack.
2380 In addition, floating point arguments or HFAs are placed in
2381 floating point registers. */
2383 floatreg
= IA64_FR8_REGNUM
;
2384 for (argno
= 0; argno
< nargs
; argno
++)
2386 struct type
*float_elt_type
;
2389 type
= check_typedef (VALUE_TYPE (arg
));
2390 len
= TYPE_LENGTH (type
);
2392 /* Special handling for function parameters. */
2394 && TYPE_CODE (type
) == TYPE_CODE_PTR
2395 && TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
)
2399 store_unsigned_integer (val_buf
, 8,
2400 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg
), 8),
2402 if (slotnum
< rseslots
)
2403 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
2405 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
2412 /* Skip odd slot if necessary... */
2413 if ((slotnum
& 1) && slot_alignment_is_next_even (type
))
2421 memset (val_buf
, 0, 8);
2422 memcpy (val_buf
, VALUE_CONTENTS (arg
) + argoffset
, (len
> 8) ? 8 : len
);
2424 if (slotnum
< rseslots
)
2425 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
2427 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
2434 /* Handle floating point types (including HFAs). */
2435 float_elt_type
= is_float_or_hfa_type (type
);
2436 if (float_elt_type
!= NULL
)
2439 len
= TYPE_LENGTH (type
);
2440 while (len
> 0 && floatreg
< IA64_FR16_REGNUM
)
2442 char to
[MAX_REGISTER_SIZE
];
2443 convert_typed_floating (VALUE_CONTENTS (arg
) + argoffset
, float_elt_type
,
2444 to
, builtin_type_ia64_ext
);
2445 regcache_cooked_write (regcache
, floatreg
, (void *)to
);
2447 argoffset
+= TYPE_LENGTH (float_elt_type
);
2448 len
-= TYPE_LENGTH (float_elt_type
);
2453 /* Store the struct return value in r8 if necessary. */
2456 regcache_cooked_write_unsigned (regcache
, IA64_GR8_REGNUM
, (ULONGEST
)struct_addr
);
2459 global_pointer
= FIND_GLOBAL_POINTER (func_addr
);
2461 if (global_pointer
!= 0)
2462 write_register (IA64_GR1_REGNUM
, global_pointer
);
2464 write_register (IA64_BR0_REGNUM
, bp_addr
);
2466 write_register (sp_regnum
, sp
);
2471 static struct frame_id
2472 ia64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2477 frame_unwind_register (next_frame
, sp_regnum
, buf
);
2478 sp
= extract_unsigned_integer (buf
, 8);
2480 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
2484 ia64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2487 CORE_ADDR ip
, psr
, pc
;
2489 frame_unwind_register (next_frame
, IA64_IP_REGNUM
, buf
);
2490 ip
= extract_unsigned_integer (buf
, 8);
2491 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
2492 psr
= extract_unsigned_integer (buf
, 8);
2494 pc
= (ip
& ~0xf) | ((psr
>> 41) & 3);
2499 ia64_store_return_value (struct type
*type
, struct regcache
*regcache
, const void *valbuf
)
2501 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2503 char to
[MAX_REGISTER_SIZE
];
2504 convert_typed_floating (valbuf
, type
, to
, builtin_type_ia64_ext
);
2505 regcache_cooked_write (regcache
, IA64_FR8_REGNUM
, (void *)to
);
2506 target_store_registers (IA64_FR8_REGNUM
);
2509 regcache_cooked_write (regcache
, IA64_GR8_REGNUM
, valbuf
);
2513 ia64_remote_translate_xfer_address (struct gdbarch
*gdbarch
,
2514 struct regcache
*regcache
,
2515 CORE_ADDR memaddr
, int nr_bytes
,
2516 CORE_ADDR
*targ_addr
, int *targ_len
)
2518 *targ_addr
= memaddr
;
2519 *targ_len
= nr_bytes
;
2523 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
2525 int *os_ident_ptr
= obj
;
2527 unsigned int sectsize
;
2529 name
= bfd_get_section_name (abfd
, sect
);
2530 sectsize
= bfd_section_size (abfd
, sect
);
2531 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
2533 unsigned int name_length
, data_length
, note_type
;
2534 char *note
= alloca (sectsize
);
2536 bfd_get_section_contents (abfd
, sect
, note
,
2537 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2539 name_length
= bfd_h_get_32 (abfd
, note
);
2540 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
2541 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2543 if (name_length
== 4 && data_length
== 16 && note_type
== 1
2544 && strcmp (note
+ 12, "GNU") == 0)
2546 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
2548 /* The case numbers are from abi-tags in glibc. */
2552 *os_ident_ptr
= ELFOSABI_LINUX
;
2555 *os_ident_ptr
= ELFOSABI_HURD
;
2558 *os_ident_ptr
= ELFOSABI_SOLARIS
;
2561 internal_error (__FILE__
, __LINE__
,
2562 "process_note_abi_sections: unknown OS number %d", os_number
);
2570 ia64_print_insn (bfd_vma memaddr
, struct disassemble_info
*info
)
2572 info
->bytes_per_line
= SLOT_MULTIPLIER
;
2573 return print_insn_ia64 (memaddr
, info
);
2576 static struct gdbarch
*
2577 ia64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2579 struct gdbarch
*gdbarch
;
2580 struct gdbarch_tdep
*tdep
;
2583 if (info
.abfd
!= NULL
2584 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2586 os_ident
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2588 /* If os_ident is 0, it is not necessarily the case that we're
2589 on a SYSV system. (ELFOSABI_NONE is defined to be 0.)
2590 GNU/Linux uses a note section to record OS/ABI info, but
2591 leaves e_ident[EI_OSABI] zero. So we have to check for note
2595 bfd_map_over_sections (info
.abfd
,
2596 process_note_abi_tag_sections
,
2603 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2605 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2607 tdep
= gdbarch_tdep (arches
->gdbarch
);
2608 if (tdep
&&tdep
->os_ident
== os_ident
)
2609 return arches
->gdbarch
;
2612 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2613 gdbarch
= gdbarch_alloc (&info
, tdep
);
2614 tdep
->os_ident
= os_ident
;
2616 /* Set the method of obtaining the sigcontext addresses at which
2617 registers are saved. The method of checking to see if
2618 native_find_global_pointer is nonzero to indicate that we're
2619 on AIX is kind of hokey, but I can't think of a better way
2621 if (os_ident
== ELFOSABI_LINUX
)
2622 tdep
->sigcontext_register_address
= ia64_linux_sigcontext_register_address
;
2623 else if (native_find_global_pointer
!= 0)
2624 tdep
->sigcontext_register_address
= ia64_aix_sigcontext_register_address
;
2626 tdep
->sigcontext_register_address
= 0;
2628 /* We know that GNU/Linux won't have to resort to the
2629 native_find_global_pointer hackery. But that's the only one we
2630 know about so far, so if native_find_global_pointer is set to
2631 something non-zero, then use it. Otherwise fall back to using
2632 generic_elf_find_global_pointer. This arrangement should (in
2633 theory) allow us to cross debug GNU/Linux binaries from an AIX
2635 if (os_ident
== ELFOSABI_LINUX
)
2636 tdep
->find_global_pointer
= generic_elf_find_global_pointer
;
2637 else if (native_find_global_pointer
!= 0)
2638 tdep
->find_global_pointer
= native_find_global_pointer
;
2640 tdep
->find_global_pointer
= generic_elf_find_global_pointer
;
2642 /* Define the ia64 floating-point format to gdb. */
2643 builtin_type_ia64_ext
=
2644 init_type (TYPE_CODE_FLT
, 128 / 8,
2645 0, "builtin_type_ia64_ext", NULL
);
2646 TYPE_FLOATFORMAT (builtin_type_ia64_ext
) = &floatformat_ia64_ext
;
2648 set_gdbarch_short_bit (gdbarch
, 16);
2649 set_gdbarch_int_bit (gdbarch
, 32);
2650 set_gdbarch_long_bit (gdbarch
, 64);
2651 set_gdbarch_long_long_bit (gdbarch
, 64);
2652 set_gdbarch_float_bit (gdbarch
, 32);
2653 set_gdbarch_double_bit (gdbarch
, 64);
2654 set_gdbarch_long_double_bit (gdbarch
, 128);
2655 set_gdbarch_ptr_bit (gdbarch
, 64);
2657 set_gdbarch_num_regs (gdbarch
, NUM_IA64_RAW_REGS
);
2658 set_gdbarch_num_pseudo_regs (gdbarch
, LAST_PSEUDO_REGNUM
- FIRST_PSEUDO_REGNUM
);
2659 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
2660 set_gdbarch_fp0_regnum (gdbarch
, IA64_FR0_REGNUM
);
2662 set_gdbarch_register_name (gdbarch
, ia64_register_name
);
2663 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2664 gets a number of extra failures. */
2665 set_gdbarch_deprecated_register_size (gdbarch
, 8);
2666 set_gdbarch_register_type (gdbarch
, ia64_register_type
);
2668 set_gdbarch_pseudo_register_read (gdbarch
, ia64_pseudo_register_read
);
2669 set_gdbarch_pseudo_register_write (gdbarch
, ia64_pseudo_register_write
);
2670 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, ia64_dwarf_reg_to_regnum
);
2671 set_gdbarch_register_reggroup_p (gdbarch
, ia64_register_reggroup_p
);
2672 set_gdbarch_convert_register_p (gdbarch
, ia64_convert_register_p
);
2673 set_gdbarch_register_to_value (gdbarch
, ia64_register_to_value
);
2674 set_gdbarch_value_to_register (gdbarch
, ia64_value_to_register
);
2676 set_gdbarch_skip_prologue (gdbarch
, ia64_skip_prologue
);
2678 set_gdbarch_use_struct_convention (gdbarch
, ia64_use_struct_convention
);
2679 set_gdbarch_extract_return_value (gdbarch
, ia64_extract_return_value
);
2681 set_gdbarch_store_return_value (gdbarch
, ia64_store_return_value
);
2682 set_gdbarch_extract_struct_value_address (gdbarch
, ia64_extract_struct_value_address
);
2684 set_gdbarch_memory_insert_breakpoint (gdbarch
, ia64_memory_insert_breakpoint
);
2685 set_gdbarch_memory_remove_breakpoint (gdbarch
, ia64_memory_remove_breakpoint
);
2686 set_gdbarch_breakpoint_from_pc (gdbarch
, ia64_breakpoint_from_pc
);
2687 set_gdbarch_read_pc (gdbarch
, ia64_read_pc
);
2688 set_gdbarch_write_pc (gdbarch
, ia64_write_pc
);
2690 /* Settings for calling functions in the inferior. */
2691 set_gdbarch_push_dummy_call (gdbarch
, ia64_push_dummy_call
);
2692 set_gdbarch_frame_align (gdbarch
, ia64_frame_align
);
2693 set_gdbarch_unwind_dummy_id (gdbarch
, ia64_unwind_dummy_id
);
2695 set_gdbarch_unwind_pc (gdbarch
, ia64_unwind_pc
);
2696 frame_unwind_append_sniffer (gdbarch
, ia64_sigtramp_frame_sniffer
);
2697 frame_unwind_append_sniffer (gdbarch
, ia64_frame_sniffer
);
2698 frame_base_set_default (gdbarch
, &ia64_frame_base
);
2700 /* Settings that should be unnecessary. */
2701 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2703 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2704 set_gdbarch_function_start_offset (gdbarch
, 0);
2705 set_gdbarch_frame_args_skip (gdbarch
, 0);
2707 set_gdbarch_remote_translate_xfer_address (
2708 gdbarch
, ia64_remote_translate_xfer_address
);
2710 set_gdbarch_print_insn (gdbarch
, ia64_print_insn
);
2711 set_gdbarch_convert_from_func_ptr_addr (gdbarch
, ia64_convert_from_func_ptr_addr
);
2716 extern initialize_file_ftype _initialize_ia64_tdep
; /* -Wmissing-prototypes */
2719 _initialize_ia64_tdep (void)
2721 register_gdbarch_init (bfd_arch_ia64
, ia64_gdbarch_init
);