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2003-09-04 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23 #include "inferior.h"
24 #include "symfile.h" /* for entry_point_address */
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39 #include "dis-asm.h"
40
41 /* Hook for determining the global pointer when calling functions in
42 the inferior under AIX. The initialization code in ia64-aix-nat.c
43 sets this hook to the address of a function which will find the
44 global pointer for a given address.
45
46 The generic code which uses the dynamic section in the inferior for
47 finding the global pointer is not of much use on AIX since the
48 values obtained from the inferior have not been relocated. */
49
50 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
51
52 /* An enumeration of the different IA-64 instruction types. */
53
54 typedef enum instruction_type
55 {
56 A, /* Integer ALU ; I-unit or M-unit */
57 I, /* Non-ALU integer; I-unit */
58 M, /* Memory ; M-unit */
59 F, /* Floating-point ; F-unit */
60 B, /* Branch ; B-unit */
61 L, /* Extended (L+X) ; I-unit */
62 X, /* Extended (L+X) ; I-unit */
63 undefined /* undefined or reserved */
64 } instruction_type;
65
66 /* We represent IA-64 PC addresses as the value of the instruction
67 pointer or'd with some bit combination in the low nibble which
68 represents the slot number in the bundle addressed by the
69 instruction pointer. The problem is that the Linux kernel
70 multiplies its slot numbers (for exceptions) by one while the
71 disassembler multiplies its slot numbers by 6. In addition, I've
72 heard it said that the simulator uses 1 as the multiplier.
73
74 I've fixed the disassembler so that the bytes_per_line field will
75 be the slot multiplier. If bytes_per_line comes in as zero, it
76 is set to six (which is how it was set up initially). -- objdump
77 displays pretty disassembly dumps with this value. For our purposes,
78 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
79 never want to also display the raw bytes the way objdump does. */
80
81 #define SLOT_MULTIPLIER 1
82
83 /* Length in bytes of an instruction bundle */
84
85 #define BUNDLE_LEN 16
86
87 /* FIXME: These extern declarations should go in ia64-tdep.h. */
88 extern CORE_ADDR ia64_linux_sigcontext_register_address (CORE_ADDR, int);
89 extern CORE_ADDR ia64_aix_sigcontext_register_address (CORE_ADDR, int);
90
91 static gdbarch_init_ftype ia64_gdbarch_init;
92
93 static gdbarch_register_name_ftype ia64_register_name;
94 static gdbarch_register_type_ftype ia64_register_type;
95 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
96 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
97 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
98 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
99 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
100 static struct type *is_float_or_hfa_type (struct type *t);
101
102 static struct type *builtin_type_ia64_ext;
103
104 #define NUM_IA64_RAW_REGS 462
105
106 static int sp_regnum = IA64_GR12_REGNUM;
107 static int fp_regnum = IA64_VFP_REGNUM;
108 static int lr_regnum = IA64_VRAP_REGNUM;
109
110 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
111 they are in memory and must be calculated via the bsp register. */
112 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
113 V127_REGNUM = V32_REGNUM + 95,
114 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
115
116 /* Array of register names; There should be ia64_num_regs strings in
117 the initializer. */
118
119 static char *ia64_register_names[] =
120 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136
137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
141 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
142 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
143 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
144 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
145 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
146 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
147 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
148 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
149 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
150 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
151 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
152 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
153
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162
163 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
164
165 "vfp", "vrap",
166
167 "pr", "ip", "psr", "cfm",
168
169 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
170 "", "", "", "", "", "", "", "",
171 "rsc", "bsp", "bspstore", "rnat",
172 "", "fcr", "", "",
173 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
174 "ccv", "", "", "", "unat", "", "", "",
175 "fpsr", "", "", "", "itc",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "",
178 "pfs", "lc", "ec",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "",
186 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
187 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
188 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
189 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
190 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
191 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
192 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
193 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
194 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
195 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
196 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
197 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
198 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
199 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
200 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
201 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
202
203 "bof",
204
205 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
206 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
207 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
208 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
209 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
210 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
211 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
212 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
213 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
214 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
215 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
216 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
217
218 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
219 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
220 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
221 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
222 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
223 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
224 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
225 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
226 };
227
228 struct ia64_frame_cache
229 {
230 CORE_ADDR base; /* frame pointer base for frame */
231 CORE_ADDR pc; /* function start pc for frame */
232 CORE_ADDR saved_sp; /* stack pointer for frame */
233 CORE_ADDR bsp; /* points at r32 for the current frame */
234 CORE_ADDR cfm; /* cfm value for current frame */
235 int frameless;
236 int sof; /* Size of frame (decoded from cfm value) */
237 int sol; /* Size of locals (decoded from cfm value) */
238 int sor; /* Number of rotating registers. (decoded from cfm value) */
239 CORE_ADDR after_prologue;
240 /* Address of first instruction after the last
241 prologue instruction; Note that there may
242 be instructions from the function's body
243 intermingled with the prologue. */
244 int mem_stack_frame_size;
245 /* Size of the memory stack frame (may be zero),
246 or -1 if it has not been determined yet. */
247 int fp_reg; /* Register number (if any) used a frame pointer
248 for this frame. 0 if no register is being used
249 as the frame pointer. */
250
251 /* Saved registers. */
252 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
253
254 };
255
256 struct gdbarch_tdep
257 {
258 int os_ident; /* From the ELF header, one of the ELFOSABI_
259 constants: ELFOSABI_LINUX, ELFOSABI_AIX,
260 etc. */
261 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
262 /* OS specific function which, given a frame address
263 and register number, returns the offset to the
264 given register from the start of the frame. */
265 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
266 };
267
268 #define SIGCONTEXT_REGISTER_ADDRESS \
269 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
270 #define FIND_GLOBAL_POINTER \
271 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
272
273 int
274 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
275 struct reggroup *group)
276 {
277 int vector_p;
278 int float_p;
279 int raw_p;
280 if (group == all_reggroup)
281 return 1;
282 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
283 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
284 raw_p = regnum < NUM_IA64_RAW_REGS;
285 if (group == float_reggroup)
286 return float_p;
287 if (group == vector_reggroup)
288 return vector_p;
289 if (group == general_reggroup)
290 return (!vector_p && !float_p);
291 if (group == save_reggroup || group == restore_reggroup)
292 return raw_p;
293 return 0;
294 }
295
296 static const char *
297 ia64_register_name (int reg)
298 {
299 return ia64_register_names[reg];
300 }
301
302 struct type *
303 ia64_register_type (struct gdbarch *arch, int reg)
304 {
305 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
306 return builtin_type_ia64_ext;
307 else
308 return builtin_type_long;
309 }
310
311 static int
312 ia64_dwarf_reg_to_regnum (int reg)
313 {
314 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
315 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
316 return reg;
317 }
318
319 const struct floatformat floatformat_ia64_ext =
320 {
321 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
322 floatformat_intbit_yes
323 };
324
325
326 /* Read the given register from a sigcontext structure in the
327 specified frame. */
328
329 static CORE_ADDR
330 read_sigcontext_register (struct frame_info *frame, int regnum)
331 {
332 CORE_ADDR regaddr;
333
334 if (frame == NULL)
335 internal_error (__FILE__, __LINE__,
336 "read_sigcontext_register: NULL frame");
337 if (!(get_frame_type (frame) == SIGTRAMP_FRAME))
338 internal_error (__FILE__, __LINE__,
339 "read_sigcontext_register: frame not a signal trampoline");
340 if (SIGCONTEXT_REGISTER_ADDRESS == 0)
341 internal_error (__FILE__, __LINE__,
342 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
343
344 regaddr = SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame), regnum);
345 if (regaddr)
346 return read_memory_integer (regaddr, REGISTER_RAW_SIZE (regnum));
347 else
348 internal_error (__FILE__, __LINE__,
349 "read_sigcontext_register: Register %d not in struct sigcontext", regnum);
350 }
351
352 /* Extract ``len'' bits from an instruction bundle starting at
353 bit ``from''. */
354
355 static long long
356 extract_bit_field (char *bundle, int from, int len)
357 {
358 long long result = 0LL;
359 int to = from + len;
360 int from_byte = from / 8;
361 int to_byte = to / 8;
362 unsigned char *b = (unsigned char *) bundle;
363 unsigned char c;
364 int lshift;
365 int i;
366
367 c = b[from_byte];
368 if (from_byte == to_byte)
369 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
370 result = c >> (from % 8);
371 lshift = 8 - (from % 8);
372
373 for (i = from_byte+1; i < to_byte; i++)
374 {
375 result |= ((long long) b[i]) << lshift;
376 lshift += 8;
377 }
378
379 if (from_byte < to_byte && (to % 8 != 0))
380 {
381 c = b[to_byte];
382 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
383 result |= ((long long) c) << lshift;
384 }
385
386 return result;
387 }
388
389 /* Replace the specified bits in an instruction bundle */
390
391 static void
392 replace_bit_field (char *bundle, long long val, int from, int len)
393 {
394 int to = from + len;
395 int from_byte = from / 8;
396 int to_byte = to / 8;
397 unsigned char *b = (unsigned char *) bundle;
398 unsigned char c;
399
400 if (from_byte == to_byte)
401 {
402 unsigned char left, right;
403 c = b[from_byte];
404 left = (c >> (to % 8)) << (to % 8);
405 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
406 c = (unsigned char) (val & 0xff);
407 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
408 c |= right | left;
409 b[from_byte] = c;
410 }
411 else
412 {
413 int i;
414 c = b[from_byte];
415 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
416 c = c | (val << (from % 8));
417 b[from_byte] = c;
418 val >>= 8 - from % 8;
419
420 for (i = from_byte+1; i < to_byte; i++)
421 {
422 c = val & 0xff;
423 val >>= 8;
424 b[i] = c;
425 }
426
427 if (to % 8 != 0)
428 {
429 unsigned char cv = (unsigned char) val;
430 c = b[to_byte];
431 c = c >> (to % 8) << (to % 8);
432 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
433 b[to_byte] = c;
434 }
435 }
436 }
437
438 /* Return the contents of slot N (for N = 0, 1, or 2) in
439 and instruction bundle */
440
441 static long long
442 slotN_contents (char *bundle, int slotnum)
443 {
444 return extract_bit_field (bundle, 5+41*slotnum, 41);
445 }
446
447 /* Store an instruction in an instruction bundle */
448
449 static void
450 replace_slotN_contents (char *bundle, long long instr, int slotnum)
451 {
452 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
453 }
454
455 static enum instruction_type template_encoding_table[32][3] =
456 {
457 { M, I, I }, /* 00 */
458 { M, I, I }, /* 01 */
459 { M, I, I }, /* 02 */
460 { M, I, I }, /* 03 */
461 { M, L, X }, /* 04 */
462 { M, L, X }, /* 05 */
463 { undefined, undefined, undefined }, /* 06 */
464 { undefined, undefined, undefined }, /* 07 */
465 { M, M, I }, /* 08 */
466 { M, M, I }, /* 09 */
467 { M, M, I }, /* 0A */
468 { M, M, I }, /* 0B */
469 { M, F, I }, /* 0C */
470 { M, F, I }, /* 0D */
471 { M, M, F }, /* 0E */
472 { M, M, F }, /* 0F */
473 { M, I, B }, /* 10 */
474 { M, I, B }, /* 11 */
475 { M, B, B }, /* 12 */
476 { M, B, B }, /* 13 */
477 { undefined, undefined, undefined }, /* 14 */
478 { undefined, undefined, undefined }, /* 15 */
479 { B, B, B }, /* 16 */
480 { B, B, B }, /* 17 */
481 { M, M, B }, /* 18 */
482 { M, M, B }, /* 19 */
483 { undefined, undefined, undefined }, /* 1A */
484 { undefined, undefined, undefined }, /* 1B */
485 { M, F, B }, /* 1C */
486 { M, F, B }, /* 1D */
487 { undefined, undefined, undefined }, /* 1E */
488 { undefined, undefined, undefined }, /* 1F */
489 };
490
491 /* Fetch and (partially) decode an instruction at ADDR and return the
492 address of the next instruction to fetch. */
493
494 static CORE_ADDR
495 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
496 {
497 char bundle[BUNDLE_LEN];
498 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
499 long long template;
500 int val;
501
502 /* Warn about slot numbers greater than 2. We used to generate
503 an error here on the assumption that the user entered an invalid
504 address. But, sometimes GDB itself requests an invalid address.
505 This can (easily) happen when execution stops in a function for
506 which there are no symbols. The prologue scanner will attempt to
507 find the beginning of the function - if the nearest symbol
508 happens to not be aligned on a bundle boundary (16 bytes), the
509 resulting starting address will cause GDB to think that the slot
510 number is too large.
511
512 So we warn about it and set the slot number to zero. It is
513 not necessarily a fatal condition, particularly if debugging
514 at the assembly language level. */
515 if (slotnum > 2)
516 {
517 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
518 "Using slot 0 instead");
519 slotnum = 0;
520 }
521
522 addr &= ~0x0f;
523
524 val = target_read_memory (addr, bundle, BUNDLE_LEN);
525
526 if (val != 0)
527 return 0;
528
529 *instr = slotN_contents (bundle, slotnum);
530 template = extract_bit_field (bundle, 0, 5);
531 *it = template_encoding_table[(int)template][slotnum];
532
533 if (slotnum == 2 || (slotnum == 1 && *it == L))
534 addr += 16;
535 else
536 addr += (slotnum + 1) * SLOT_MULTIPLIER;
537
538 return addr;
539 }
540
541 /* There are 5 different break instructions (break.i, break.b,
542 break.m, break.f, and break.x), but they all have the same
543 encoding. (The five bit template in the low five bits of the
544 instruction bundle distinguishes one from another.)
545
546 The runtime architecture manual specifies that break instructions
547 used for debugging purposes must have the upper two bits of the 21
548 bit immediate set to a 0 and a 1 respectively. A breakpoint
549 instruction encodes the most significant bit of its 21 bit
550 immediate at bit 36 of the 41 bit instruction. The penultimate msb
551 is at bit 25 which leads to the pattern below.
552
553 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
554 it turns out that 0x80000 was used as the syscall break in the early
555 simulators. So I changed the pattern slightly to do "break.i 0x080001"
556 instead. But that didn't work either (I later found out that this
557 pattern was used by the simulator that I was using.) So I ended up
558 using the pattern seen below. */
559
560 #if 0
561 #define IA64_BREAKPOINT 0x00002000040LL
562 #endif
563 #define IA64_BREAKPOINT 0x00003333300LL
564
565 static int
566 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
567 {
568 char bundle[BUNDLE_LEN];
569 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
570 long long instr;
571 int val;
572 int template;
573
574 if (slotnum > 2)
575 error("Can't insert breakpoint for slot numbers greater than 2.");
576
577 addr &= ~0x0f;
578
579 val = target_read_memory (addr, bundle, BUNDLE_LEN);
580
581 /* Check for L type instruction in 2nd slot, if present then
582 bump up the slot number to the 3rd slot */
583 template = extract_bit_field (bundle, 0, 5);
584 if (slotnum == 1 && template_encoding_table[template][1] == L)
585 {
586 slotnum = 2;
587 }
588
589 instr = slotN_contents (bundle, slotnum);
590 memcpy(contents_cache, &instr, sizeof(instr));
591 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
592 if (val == 0)
593 target_write_memory (addr, bundle, BUNDLE_LEN);
594
595 return val;
596 }
597
598 static int
599 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
600 {
601 char bundle[BUNDLE_LEN];
602 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
603 long long instr;
604 int val;
605 int template;
606
607 addr &= ~0x0f;
608
609 val = target_read_memory (addr, bundle, BUNDLE_LEN);
610
611 /* Check for L type instruction in 2nd slot, if present then
612 bump up the slot number to the 3rd slot */
613 template = extract_bit_field (bundle, 0, 5);
614 if (slotnum == 1 && template_encoding_table[template][1] == L)
615 {
616 slotnum = 2;
617 }
618
619 memcpy (&instr, contents_cache, sizeof instr);
620 replace_slotN_contents (bundle, instr, slotnum);
621 if (val == 0)
622 target_write_memory (addr, bundle, BUNDLE_LEN);
623
624 return val;
625 }
626
627 /* We don't really want to use this, but remote.c needs to call it in order
628 to figure out if Z-packets are supported or not. Oh, well. */
629 const unsigned char *
630 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
631 {
632 static unsigned char breakpoint[] =
633 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
634 *lenptr = sizeof (breakpoint);
635 #if 0
636 *pcptr &= ~0x0f;
637 #endif
638 return breakpoint;
639 }
640
641 static CORE_ADDR
642 ia64_read_fp (void)
643 {
644 /* We won't necessarily have a frame pointer and even if we do, it
645 winds up being extraordinarly messy when attempting to find the
646 frame chain. So for the purposes of creating frames (which is
647 all deprecated_read_fp() is used for), simply use the stack
648 pointer value instead. */
649 gdb_assert (SP_REGNUM >= 0);
650 return read_register (SP_REGNUM);
651 }
652
653 static CORE_ADDR
654 ia64_read_pc (ptid_t ptid)
655 {
656 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
657 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
658 int slot_num = (psr_value >> 41) & 3;
659
660 return pc_value | (slot_num * SLOT_MULTIPLIER);
661 }
662
663 static void
664 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
665 {
666 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
667 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
668 psr_value &= ~(3LL << 41);
669 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
670
671 new_pc &= ~0xfLL;
672
673 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
674 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
675 }
676
677 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
678
679 /* Returns the address of the slot that's NSLOTS slots away from
680 the address ADDR. NSLOTS may be positive or negative. */
681 static CORE_ADDR
682 rse_address_add(CORE_ADDR addr, int nslots)
683 {
684 CORE_ADDR new_addr;
685 int mandatory_nat_slots = nslots / 63;
686 int direction = nslots < 0 ? -1 : 1;
687
688 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
689
690 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
691 new_addr += 8 * direction;
692
693 if (IS_NaT_COLLECTION_ADDR(new_addr))
694 new_addr += 8 * direction;
695
696 return new_addr;
697 }
698
699 static void
700 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
701 int regnum, void *buf)
702 {
703 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
704 {
705 ULONGEST bsp;
706 ULONGEST cfm;
707 CORE_ADDR reg;
708 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
709 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
710
711 /* The bsp points at the end of the register frame so we
712 subtract the size of frame from it to get start of register frame. */
713 bsp = rse_address_add (bsp, -(cfm & 0x7f));
714
715 if ((cfm & 0x7f) > regnum - V32_REGNUM)
716 {
717 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
718 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
719 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), reg);
720 }
721 else
722 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), 0);
723 }
724 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
725 {
726 ULONGEST unatN_val;
727 ULONGEST unat;
728 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
729 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
730 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), unatN_val);
731 }
732 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
733 {
734 ULONGEST natN_val = 0;
735 ULONGEST bsp;
736 ULONGEST cfm;
737 CORE_ADDR gr_addr = 0;
738 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
739 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
740
741 /* The bsp points at the end of the register frame so we
742 subtract the size of frame from it to get start of register frame. */
743 bsp = rse_address_add (bsp, -(cfm & 0x7f));
744
745 if ((cfm & 0x7f) > regnum - V32_REGNUM)
746 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
747
748 if (gr_addr != 0)
749 {
750 /* Compute address of nat collection bits. */
751 CORE_ADDR nat_addr = gr_addr | 0x1f8;
752 CORE_ADDR nat_collection;
753 int nat_bit;
754 /* If our nat collection address is bigger than bsp, we have to get
755 the nat collection from rnat. Otherwise, we fetch the nat
756 collection from the computed address. */
757 if (nat_addr >= bsp)
758 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
759 else
760 nat_collection = read_memory_integer (nat_addr, 8);
761 nat_bit = (gr_addr >> 3) & 0x3f;
762 natN_val = (nat_collection >> nat_bit) & 1;
763 }
764
765 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), natN_val);
766 }
767 else if (regnum == VBOF_REGNUM)
768 {
769 /* A virtual register frame start is provided for user convenience.
770 It can be calculated as the bsp - sof (sizeof frame). */
771 ULONGEST bsp, vbsp;
772 ULONGEST cfm;
773 CORE_ADDR reg;
774 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
775 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
776
777 /* The bsp points at the end of the register frame so we
778 subtract the size of frame from it to get beginning of frame. */
779 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
780 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), vbsp);
781 }
782 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
783 {
784 ULONGEST pr;
785 ULONGEST cfm;
786 ULONGEST prN_val;
787 CORE_ADDR reg;
788 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
789 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
790
791 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
792 {
793 /* Fetch predicate register rename base from current frame
794 marker for this frame. */
795 int rrb_pr = (cfm >> 32) & 0x3f;
796
797 /* Adjust the register number to account for register rotation. */
798 regnum = VP16_REGNUM
799 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
800 }
801 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
802 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), prN_val);
803 }
804 else
805 memset (buf, 0, REGISTER_RAW_SIZE (regnum));
806 }
807
808 static void
809 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
810 int regnum, const void *buf)
811 {
812 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
813 {
814 ULONGEST bsp;
815 ULONGEST cfm;
816 CORE_ADDR reg;
817 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
818 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
819
820 bsp = rse_address_add (bsp, -(cfm & 0x7f));
821
822 if ((cfm & 0x7f) > regnum - V32_REGNUM)
823 {
824 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
825 write_memory (reg_addr, (void *)buf, 8);
826 }
827 }
828 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
829 {
830 ULONGEST unatN_val, unat, unatN_mask;
831 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
832 unatN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
833 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
834 if (unatN_val == 0)
835 unat &= ~unatN_mask;
836 else if (unatN_val == 1)
837 unat |= unatN_mask;
838 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
839 }
840 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
841 {
842 ULONGEST natN_val;
843 ULONGEST bsp;
844 ULONGEST cfm;
845 CORE_ADDR gr_addr = 0;
846 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
847 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
848
849 /* The bsp points at the end of the register frame so we
850 subtract the size of frame from it to get start of register frame. */
851 bsp = rse_address_add (bsp, -(cfm & 0x7f));
852
853 if ((cfm & 0x7f) > regnum - V32_REGNUM)
854 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
855
856 natN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
857
858 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
859 {
860 /* Compute address of nat collection bits. */
861 CORE_ADDR nat_addr = gr_addr | 0x1f8;
862 CORE_ADDR nat_collection;
863 int natN_bit = (gr_addr >> 3) & 0x3f;
864 ULONGEST natN_mask = (1LL << natN_bit);
865 /* If our nat collection address is bigger than bsp, we have to get
866 the nat collection from rnat. Otherwise, we fetch the nat
867 collection from the computed address. */
868 if (nat_addr >= bsp)
869 {
870 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
871 if (natN_val)
872 nat_collection |= natN_mask;
873 else
874 nat_collection &= ~natN_mask;
875 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
876 }
877 else
878 {
879 char nat_buf[8];
880 nat_collection = read_memory_integer (nat_addr, 8);
881 if (natN_val)
882 nat_collection |= natN_mask;
883 else
884 nat_collection &= ~natN_mask;
885 store_unsigned_integer (nat_buf, REGISTER_RAW_SIZE (regnum), nat_collection);
886 write_memory (nat_addr, nat_buf, 8);
887 }
888 }
889 }
890 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
891 {
892 ULONGEST pr;
893 ULONGEST cfm;
894 ULONGEST prN_val;
895 ULONGEST prN_mask;
896
897 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
898 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
899
900 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
901 {
902 /* Fetch predicate register rename base from current frame
903 marker for this frame. */
904 int rrb_pr = (cfm >> 32) & 0x3f;
905
906 /* Adjust the register number to account for register rotation. */
907 regnum = VP16_REGNUM
908 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
909 }
910 prN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
911 prN_mask = (1LL << (regnum - VP0_REGNUM));
912 if (prN_val == 0)
913 pr &= ~prN_mask;
914 else if (prN_val == 1)
915 pr |= prN_mask;
916 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
917 }
918 }
919
920 /* The ia64 needs to convert between various ieee floating-point formats
921 and the special ia64 floating point register format. */
922
923 static int
924 ia64_convert_register_p (int regno, struct type *type)
925 {
926 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
927 }
928
929 static void
930 ia64_register_to_value (struct frame_info *frame, int regnum,
931 struct type *valtype, void *out)
932 {
933 char in[MAX_REGISTER_SIZE];
934 frame_register_read (frame, regnum, in);
935 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
936 }
937
938 static void
939 ia64_value_to_register (struct frame_info *frame, int regnum,
940 struct type *valtype, const void *in)
941 {
942 char out[MAX_REGISTER_SIZE];
943 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
944 put_frame_register (frame, regnum, out);
945 }
946
947
948 /* Limit the number of skipped non-prologue instructions since examining
949 of the prologue is expensive. */
950 static int max_skip_non_prologue_insns = 40;
951
952 /* Given PC representing the starting address of a function, and
953 LIM_PC which is the (sloppy) limit to which to scan when looking
954 for a prologue, attempt to further refine this limit by using
955 the line data in the symbol table. If successful, a better guess
956 on where the prologue ends is returned, otherwise the previous
957 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
958 which will be set to indicate whether the returned limit may be
959 used with no further scanning in the event that the function is
960 frameless. */
961
962 static CORE_ADDR
963 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
964 {
965 struct symtab_and_line prologue_sal;
966 CORE_ADDR start_pc = pc;
967
968 /* Start off not trusting the limit. */
969 *trust_limit = 0;
970
971 prologue_sal = find_pc_line (pc, 0);
972 if (prologue_sal.line != 0)
973 {
974 int i;
975 CORE_ADDR addr = prologue_sal.end;
976
977 /* Handle the case in which compiler's optimizer/scheduler
978 has moved instructions into the prologue. We scan ahead
979 in the function looking for address ranges whose corresponding
980 line number is less than or equal to the first one that we
981 found for the function. (It can be less than when the
982 scheduler puts a body instruction before the first prologue
983 instruction.) */
984 for (i = 2 * max_skip_non_prologue_insns;
985 i > 0 && (lim_pc == 0 || addr < lim_pc);
986 i--)
987 {
988 struct symtab_and_line sal;
989
990 sal = find_pc_line (addr, 0);
991 if (sal.line == 0)
992 break;
993 if (sal.line <= prologue_sal.line
994 && sal.symtab == prologue_sal.symtab)
995 {
996 prologue_sal = sal;
997 }
998 addr = sal.end;
999 }
1000
1001 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1002 {
1003 lim_pc = prologue_sal.end;
1004 if (start_pc == get_pc_function_start (lim_pc))
1005 *trust_limit = 1;
1006 }
1007 }
1008 return lim_pc;
1009 }
1010
1011 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1012 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1013 || (14 <= (_regnum_) && (_regnum_) <= 31))
1014 #define imm9(_instr_) \
1015 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1016 | (((_instr_) & 0x00008000000LL) >> 20) \
1017 | (((_instr_) & 0x00000001fc0LL) >> 6))
1018
1019 /* Allocate and initialize a frame cache. */
1020
1021 static struct ia64_frame_cache *
1022 ia64_alloc_frame_cache (void)
1023 {
1024 struct ia64_frame_cache *cache;
1025 int i;
1026
1027 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1028
1029 /* Base address. */
1030 cache->base = 0;
1031 cache->pc = 0;
1032 cache->cfm = 0;
1033 cache->sof = 0;
1034 cache->sol = 0;
1035 cache->sor = 0;
1036 cache->bsp = 0;
1037 cache->fp_reg = 0;
1038 cache->frameless = 1;
1039
1040 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1041 cache->saved_regs[i] = 0;
1042
1043 return cache;
1044 }
1045
1046 static CORE_ADDR
1047 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1048 {
1049 CORE_ADDR next_pc;
1050 CORE_ADDR last_prologue_pc = pc;
1051 instruction_type it;
1052 long long instr;
1053 int cfm_reg = 0;
1054 int ret_reg = 0;
1055 int fp_reg = 0;
1056 int unat_save_reg = 0;
1057 int pr_save_reg = 0;
1058 int mem_stack_frame_size = 0;
1059 int spill_reg = 0;
1060 CORE_ADDR spill_addr = 0;
1061 char instores[8];
1062 char infpstores[8];
1063 char reg_contents[256];
1064 int trust_limit;
1065 int frameless = 1;
1066 int i;
1067 CORE_ADDR addr;
1068 char buf[8];
1069 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1070
1071 memset (instores, 0, sizeof instores);
1072 memset (infpstores, 0, sizeof infpstores);
1073 memset (reg_contents, 0, sizeof reg_contents);
1074
1075 if (cache->after_prologue != 0
1076 && cache->after_prologue <= lim_pc)
1077 return cache->after_prologue;
1078
1079 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1080 next_pc = fetch_instruction (pc, &it, &instr);
1081
1082 /* We want to check if we have a recognizable function start before we
1083 look ahead for a prologue. */
1084 if (pc < lim_pc && next_pc
1085 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1086 {
1087 /* alloc - start of a regular function. */
1088 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1089 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1090 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1091 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1092
1093 /* Verify that the current cfm matches what we think is the
1094 function start. If we have somehow jumped within a function,
1095 we do not want to interpret the prologue and calculate the
1096 addresses of various registers such as the return address.
1097 We will instead treat the frame as frameless. */
1098 if (!next_frame ||
1099 (sof == (cache->cfm & 0x7f) &&
1100 sol == ((cache->cfm >> 7) & 0x7f)))
1101 frameless = 0;
1102
1103 cfm_reg = rN;
1104 last_prologue_pc = next_pc;
1105 pc = next_pc;
1106 }
1107 else
1108 {
1109 /* Look for a leaf routine. */
1110 if (pc < lim_pc && next_pc
1111 && (it == I || it == M)
1112 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1113 {
1114 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1115 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1116 | ((instr & 0x001f8000000LL) >> 20)
1117 | ((instr & 0x000000fe000LL) >> 13));
1118 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1119 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1120 int qp = (int) (instr & 0x0000000003fLL);
1121 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1122 {
1123 /* mov r2, r12 - beginning of leaf routine */
1124 fp_reg = rN;
1125 last_prologue_pc = next_pc;
1126 }
1127 }
1128
1129 /* If we don't recognize a regular function or leaf routine, we are
1130 done. */
1131 if (!fp_reg)
1132 {
1133 pc = lim_pc;
1134 if (trust_limit)
1135 last_prologue_pc = lim_pc;
1136 }
1137 }
1138
1139 /* Loop, looking for prologue instructions, keeping track of
1140 where preserved registers were spilled. */
1141 while (pc < lim_pc)
1142 {
1143 next_pc = fetch_instruction (pc, &it, &instr);
1144 if (next_pc == 0)
1145 break;
1146
1147 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000))
1148 {
1149 /* Exit loop upon hitting a non-nop branch instruction. */
1150 if (trust_limit)
1151 lim_pc = pc;
1152 break;
1153 }
1154 else if (((instr & 0x3fLL) != 0LL) &&
1155 (frameless || ret_reg != 0))
1156 {
1157 /* Exit loop upon hitting a predicated instruction if
1158 we already have the return register or if we are frameless. */
1159 if (trust_limit)
1160 lim_pc = pc;
1161 break;
1162 }
1163 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1164 {
1165 /* Move from BR */
1166 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1167 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1168 int qp = (int) (instr & 0x0000000003f);
1169
1170 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1171 {
1172 ret_reg = rN;
1173 last_prologue_pc = next_pc;
1174 }
1175 }
1176 else if ((it == I || it == M)
1177 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1178 {
1179 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1180 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1181 | ((instr & 0x001f8000000LL) >> 20)
1182 | ((instr & 0x000000fe000LL) >> 13));
1183 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1184 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1185 int qp = (int) (instr & 0x0000000003fLL);
1186
1187 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1188 {
1189 /* mov rN, r12 */
1190 fp_reg = rN;
1191 last_prologue_pc = next_pc;
1192 }
1193 else if (qp == 0 && rN == 12 && rM == 12)
1194 {
1195 /* adds r12, -mem_stack_frame_size, r12 */
1196 mem_stack_frame_size -= imm;
1197 last_prologue_pc = next_pc;
1198 }
1199 else if (qp == 0 && rN == 2
1200 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1201 {
1202 char buf[MAX_REGISTER_SIZE];
1203 CORE_ADDR saved_sp = 0;
1204 /* adds r2, spilloffset, rFramePointer
1205 or
1206 adds r2, spilloffset, r12
1207
1208 Get ready for stf.spill or st8.spill instructions.
1209 The address to start spilling at is loaded into r2.
1210 FIXME: Why r2? That's what gcc currently uses; it
1211 could well be different for other compilers. */
1212
1213 /* Hmm... whether or not this will work will depend on
1214 where the pc is. If it's still early in the prologue
1215 this'll be wrong. FIXME */
1216 if (next_frame)
1217 {
1218 frame_unwind_register (next_frame, sp_regnum, buf);
1219 saved_sp = extract_unsigned_integer (buf, 8);
1220 }
1221 spill_addr = saved_sp
1222 + (rM == 12 ? 0 : mem_stack_frame_size)
1223 + imm;
1224 spill_reg = rN;
1225 last_prologue_pc = next_pc;
1226 }
1227 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1228 rN < 256 && imm == 0)
1229 {
1230 /* mov rN, rM where rM is an input register */
1231 reg_contents[rN] = rM;
1232 last_prologue_pc = next_pc;
1233 }
1234 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1235 rM == 2)
1236 {
1237 /* mov r12, r2 */
1238 last_prologue_pc = next_pc;
1239 break;
1240 }
1241 }
1242 else if (it == M
1243 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1244 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1245 {
1246 /* stf.spill [rN] = fM, imm9
1247 or
1248 stf.spill [rN] = fM */
1249
1250 int imm = imm9(instr);
1251 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1252 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1253 int qp = (int) (instr & 0x0000000003fLL);
1254 if (qp == 0 && rN == spill_reg && spill_addr != 0
1255 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1256 {
1257 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1258
1259 if ((instr & 0x1efc0000000) == 0x0eec0000000)
1260 spill_addr += imm;
1261 else
1262 spill_addr = 0; /* last one; must be done */
1263 last_prologue_pc = next_pc;
1264 }
1265 }
1266 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1267 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1268 {
1269 /* mov.m rN = arM
1270 or
1271 mov.i rN = arM */
1272
1273 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1274 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1275 int qp = (int) (instr & 0x0000000003fLL);
1276 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1277 {
1278 /* We have something like "mov.m r3 = ar.unat". Remember the
1279 r3 (or whatever) and watch for a store of this register... */
1280 unat_save_reg = rN;
1281 last_prologue_pc = next_pc;
1282 }
1283 }
1284 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1285 {
1286 /* mov rN = pr */
1287 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1288 int qp = (int) (instr & 0x0000000003fLL);
1289 if (qp == 0 && isScratch (rN))
1290 {
1291 pr_save_reg = rN;
1292 last_prologue_pc = next_pc;
1293 }
1294 }
1295 else if (it == M
1296 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1297 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1298 {
1299 /* st8 [rN] = rM
1300 or
1301 st8 [rN] = rM, imm9 */
1302 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1303 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1304 int qp = (int) (instr & 0x0000000003fLL);
1305 int indirect = rM < 256 ? reg_contents[rM] : 0;
1306 if (qp == 0 && rN == spill_reg && spill_addr != 0
1307 && (rM == unat_save_reg || rM == pr_save_reg))
1308 {
1309 /* We've found a spill of either the UNAT register or the PR
1310 register. (Well, not exactly; what we've actually found is
1311 a spill of the register that UNAT or PR was moved to).
1312 Record that fact and move on... */
1313 if (rM == unat_save_reg)
1314 {
1315 /* Track UNAT register */
1316 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1317 unat_save_reg = 0;
1318 }
1319 else
1320 {
1321 /* Track PR register */
1322 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1323 pr_save_reg = 0;
1324 }
1325 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1326 /* st8 [rN] = rM, imm9 */
1327 spill_addr += imm9(instr);
1328 else
1329 spill_addr = 0; /* must be done spilling */
1330 last_prologue_pc = next_pc;
1331 }
1332 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1333 {
1334 /* Allow up to one store of each input register. */
1335 instores[rM-32] = 1;
1336 last_prologue_pc = next_pc;
1337 }
1338 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1339 !instores[indirect-32])
1340 {
1341 /* Allow an indirect store of an input register. */
1342 instores[indirect-32] = 1;
1343 last_prologue_pc = next_pc;
1344 }
1345 }
1346 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1347 {
1348 /* One of
1349 st1 [rN] = rM
1350 st2 [rN] = rM
1351 st4 [rN] = rM
1352 st8 [rN] = rM
1353 Note that the st8 case is handled in the clause above.
1354
1355 Advance over stores of input registers. One store per input
1356 register is permitted. */
1357 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1358 int qp = (int) (instr & 0x0000000003fLL);
1359 int indirect = rM < 256 ? reg_contents[rM] : 0;
1360 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1361 {
1362 instores[rM-32] = 1;
1363 last_prologue_pc = next_pc;
1364 }
1365 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1366 !instores[indirect-32])
1367 {
1368 /* Allow an indirect store of an input register. */
1369 instores[indirect-32] = 1;
1370 last_prologue_pc = next_pc;
1371 }
1372 }
1373 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1374 {
1375 /* Either
1376 stfs [rN] = fM
1377 or
1378 stfd [rN] = fM
1379
1380 Advance over stores of floating point input registers. Again
1381 one store per register is permitted */
1382 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1383 int qp = (int) (instr & 0x0000000003fLL);
1384 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1385 {
1386 infpstores[fM-8] = 1;
1387 last_prologue_pc = next_pc;
1388 }
1389 }
1390 else if (it == M
1391 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1392 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1393 {
1394 /* st8.spill [rN] = rM
1395 or
1396 st8.spill [rN] = rM, imm9 */
1397 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1398 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1399 int qp = (int) (instr & 0x0000000003fLL);
1400 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1401 {
1402 /* We've found a spill of one of the preserved general purpose
1403 regs. Record the spill address and advance the spill
1404 register if appropriate. */
1405 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1406 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1407 /* st8.spill [rN] = rM, imm9 */
1408 spill_addr += imm9(instr);
1409 else
1410 spill_addr = 0; /* Done spilling */
1411 last_prologue_pc = next_pc;
1412 }
1413 }
1414
1415 pc = next_pc;
1416 }
1417
1418 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1419 registers for the previous frame which will be needed later. */
1420
1421 if (!frameless && next_frame)
1422 {
1423 /* Extract the size of the rotating portion of the stack
1424 frame and the register rename base from the current
1425 frame marker. */
1426 cfm = cache->cfm;
1427 sor = cache->sor;
1428 sof = cache->sof;
1429 sol = cache->sol;
1430 rrb_gr = (cfm >> 18) & 0x7f;
1431
1432 /* Find the bof (beginning of frame). */
1433 bof = rse_address_add (cache->bsp, -sof);
1434
1435 for (i = 0, addr = bof;
1436 i < sof;
1437 i++, addr += 8)
1438 {
1439 if (IS_NaT_COLLECTION_ADDR (addr))
1440 {
1441 addr += 8;
1442 }
1443 if (i+32 == cfm_reg)
1444 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1445 if (i+32 == ret_reg)
1446 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1447 if (i+32 == fp_reg)
1448 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1449 }
1450
1451 /* For the previous argument registers we require the previous bof.
1452 If we can't find the previous cfm, then we can do nothing. */
1453 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1454 {
1455 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1456 sor = ((cfm >> 14) & 0xf) * 8;
1457 sof = (cfm & 0x7f);
1458 sol = (cfm >> 7) & 0x7f;
1459 rrb_gr = (cfm >> 18) & 0x7f;
1460
1461 /* The previous bof only requires subtraction of the sol (size of locals)
1462 due to the overlap between output and input of subsequent frames. */
1463 bof = rse_address_add (bof, -sol);
1464
1465 for (i = 0, addr = bof;
1466 i < sof;
1467 i++, addr += 8)
1468 {
1469 if (IS_NaT_COLLECTION_ADDR (addr))
1470 {
1471 addr += 8;
1472 }
1473 if (i < sor)
1474 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1475 = addr;
1476 else
1477 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1478 }
1479
1480 }
1481 }
1482
1483 /* Try and trust the lim_pc value whenever possible. */
1484 if (trust_limit && lim_pc >= last_prologue_pc)
1485 last_prologue_pc = lim_pc;
1486
1487 cache->frameless = frameless;
1488 cache->after_prologue = last_prologue_pc;
1489 cache->mem_stack_frame_size = mem_stack_frame_size;
1490 cache->fp_reg = fp_reg;
1491
1492 return last_prologue_pc;
1493 }
1494
1495 CORE_ADDR
1496 ia64_skip_prologue (CORE_ADDR pc)
1497 {
1498 struct ia64_frame_cache cache;
1499 cache.base = 0;
1500 cache.after_prologue = 0;
1501 cache.cfm = 0;
1502 cache.bsp = 0;
1503
1504 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1505 return examine_prologue (pc, pc+1024, 0, &cache);
1506 }
1507
1508
1509 /* Normal frames. */
1510
1511 static struct ia64_frame_cache *
1512 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1513 {
1514 struct ia64_frame_cache *cache;
1515 char buf[8];
1516 CORE_ADDR cfm, sof, sol, bsp, psr;
1517 int i;
1518
1519 if (*this_cache)
1520 return *this_cache;
1521
1522 cache = ia64_alloc_frame_cache ();
1523 *this_cache = cache;
1524
1525 frame_unwind_register (next_frame, sp_regnum, buf);
1526 cache->saved_sp = extract_unsigned_integer (buf, 8);
1527
1528 /* We always want the bsp to point to the end of frame.
1529 This way, we can always get the beginning of frame (bof)
1530 by subtracting frame size. */
1531 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1532 cache->bsp = extract_unsigned_integer (buf, 8);
1533
1534 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1535 psr = extract_unsigned_integer (buf, 8);
1536
1537 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1538 cfm = extract_unsigned_integer (buf, 8);
1539
1540 cache->sof = (cfm & 0x7f);
1541 cache->sol = (cfm >> 7) & 0x7f;
1542 cache->sor = ((cfm >> 14) & 0xf) * 8;
1543
1544 cache->cfm = cfm;
1545
1546 cache->pc = frame_func_unwind (next_frame);
1547
1548 if (cache->pc != 0)
1549 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1550
1551 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1552
1553 return cache;
1554 }
1555
1556 static void
1557 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1558 struct frame_id *this_id)
1559 {
1560 struct ia64_frame_cache *cache =
1561 ia64_frame_cache (next_frame, this_cache);
1562
1563 /* This marks the outermost frame. */
1564 if (cache->base == 0)
1565 return;
1566
1567 (*this_id) = frame_id_build (cache->base, cache->pc);
1568 }
1569
1570 static void
1571 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1572 int regnum, int *optimizedp,
1573 enum lval_type *lvalp, CORE_ADDR *addrp,
1574 int *realnump, void *valuep)
1575 {
1576 struct ia64_frame_cache *cache =
1577 ia64_frame_cache (next_frame, this_cache);
1578 char dummy_valp[MAX_REGISTER_SIZE];
1579 char buf[8];
1580
1581 gdb_assert (regnum >= 0);
1582
1583 if (!target_has_registers)
1584 error ("No registers.");
1585
1586 *optimizedp = 0;
1587 *addrp = 0;
1588 *lvalp = not_lval;
1589 *realnump = -1;
1590
1591 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1592 when valuep is not supplied. */
1593 if (!valuep)
1594 valuep = dummy_valp;
1595
1596 memset (valuep, 0, REGISTER_RAW_SIZE (regnum));
1597
1598 if (regnum == SP_REGNUM)
1599 {
1600 /* Handle SP values for all frames but the topmost. */
1601 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1602 cache->base);
1603 }
1604 else if (regnum == IA64_BSP_REGNUM)
1605 {
1606 char cfm_valuep[MAX_REGISTER_SIZE];
1607 int cfm_optim;
1608 int cfm_realnum;
1609 enum lval_type cfm_lval;
1610 CORE_ADDR cfm_addr;
1611 CORE_ADDR bsp, prev_cfm, prev_bsp;
1612
1613 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1614 This corresponds to what the hardware bsp register will be if we pop the frame
1615 back which is why we might have been called. We know the beginning of the current
1616 frame is cache->bsp - cache->sof. This value in the previous frame points to
1617 the start of the output registers. We can calculate the end of that frame by adding
1618 the size of output (sof (size of frame) - sol (size of locals)). */
1619 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1620 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1621 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1622
1623 bsp = rse_address_add (cache->bsp, -(cache->sof));
1624 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1625
1626 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1627 prev_bsp);
1628 }
1629 else if (regnum == IA64_CFM_REGNUM)
1630 {
1631 CORE_ADDR addr = 0;
1632
1633 if (cache->frameless)
1634 {
1635 CORE_ADDR cfm = 0;
1636 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1637 }
1638 else
1639 {
1640 addr = cache->saved_regs[IA64_CFM_REGNUM];
1641 if (addr != 0)
1642 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1643 }
1644 }
1645 else if (regnum == IA64_VFP_REGNUM)
1646 {
1647 /* If the function in question uses an automatic register (r32-r127)
1648 for the frame pointer, it'll be found by ia64_find_saved_register()
1649 above. If the function lacks one of these frame pointers, we can
1650 still provide a value since we know the size of the frame. */
1651 CORE_ADDR vfp = cache->base;
1652 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (IA64_VFP_REGNUM), vfp);
1653 }
1654 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1655 {
1656 char pr_valuep[MAX_REGISTER_SIZE];
1657 int pr_optim;
1658 int pr_realnum;
1659 enum lval_type pr_lval;
1660 CORE_ADDR pr_addr;
1661 ULONGEST prN_val;
1662 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1663 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1664 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1665 {
1666 /* Fetch predicate register rename base from current frame
1667 marker for this frame. */
1668 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1669
1670 /* Adjust the register number to account for register rotation. */
1671 regnum = VP16_REGNUM
1672 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1673 }
1674 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1675 regnum - VP0_REGNUM, 1);
1676 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum), prN_val);
1677 }
1678 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1679 {
1680 char unat_valuep[MAX_REGISTER_SIZE];
1681 int unat_optim;
1682 int unat_realnum;
1683 enum lval_type unat_lval;
1684 CORE_ADDR unat_addr;
1685 ULONGEST unatN_val;
1686 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1687 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1688 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1689 regnum - IA64_NAT0_REGNUM, 1);
1690 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1691 unatN_val);
1692 }
1693 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1694 {
1695 int natval = 0;
1696 /* Find address of general register corresponding to nat bit we're
1697 interested in. */
1698 CORE_ADDR gr_addr;
1699
1700 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1701 + IA64_GR0_REGNUM];
1702 if (gr_addr != 0)
1703 {
1704 /* Compute address of nat collection bits. */
1705 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1706 CORE_ADDR bsp;
1707 CORE_ADDR nat_collection;
1708 int nat_bit;
1709 /* If our nat collection address is bigger than bsp, we have to get
1710 the nat collection from rnat. Otherwise, we fetch the nat
1711 collection from the computed address. */
1712 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1713 bsp = extract_unsigned_integer (buf, 8);
1714 if (nat_addr >= bsp)
1715 {
1716 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1717 nat_collection = extract_unsigned_integer (buf, 8);
1718 }
1719 else
1720 nat_collection = read_memory_integer (nat_addr, 8);
1721 nat_bit = (gr_addr >> 3) & 0x3f;
1722 natval = (nat_collection >> nat_bit) & 1;
1723 }
1724
1725 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum), natval);
1726 }
1727 else if (regnum == IA64_IP_REGNUM)
1728 {
1729 CORE_ADDR pc = 0;
1730
1731 if (cache->frameless)
1732 {
1733 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1734 pc = extract_unsigned_integer (buf, 8);
1735 }
1736 else
1737 {
1738 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1739 if (addr != 0)
1740 {
1741 read_memory (addr, buf, REGISTER_RAW_SIZE (IA64_IP_REGNUM));
1742 pc = extract_unsigned_integer (buf, 8);
1743 }
1744 }
1745 pc &= ~0xf;
1746 store_unsigned_integer (valuep, 8, pc);
1747 }
1748 else if (regnum == IA64_PSR_REGNUM)
1749 {
1750 ULONGEST slot_num = 0;
1751 CORE_ADDR pc= 0;
1752 CORE_ADDR psr = 0;
1753
1754 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1755 psr = extract_unsigned_integer (buf, 8);
1756
1757 if (cache->frameless)
1758 {
1759 CORE_ADDR pc;
1760 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1761 pc = extract_unsigned_integer (buf, 8);
1762 }
1763 else
1764 {
1765 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1766 if (addr != 0)
1767 {
1768 read_memory (addr, buf, REGISTER_RAW_SIZE (IA64_IP_REGNUM));
1769 pc = extract_unsigned_integer (buf, 8);
1770 }
1771 }
1772 psr &= ~(3LL << 41);
1773 slot_num = pc & 0x3LL;
1774 psr |= (CORE_ADDR)slot_num << 41;
1775 store_unsigned_integer (valuep, 8, psr);
1776 }
1777 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1778 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1779 {
1780 CORE_ADDR addr = 0;
1781 if (regnum >= V32_REGNUM)
1782 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1783 addr = cache->saved_regs[regnum];
1784 if (addr != 0)
1785 {
1786 *lvalp = lval_memory;
1787 *addrp = addr;
1788 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1789 }
1790 else if (cache->frameless)
1791 {
1792 char r_valuep[MAX_REGISTER_SIZE];
1793 int r_optim;
1794 int r_realnum;
1795 enum lval_type r_lval;
1796 CORE_ADDR r_addr;
1797 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1798 CORE_ADDR addr = 0;
1799 if (regnum >= V32_REGNUM)
1800 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1801 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1802 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1803 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1804 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1805 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1806 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1807 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1808
1809 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1810 *lvalp = lval_memory;
1811 *addrp = addr;
1812 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1813 }
1814 }
1815 else
1816 {
1817 CORE_ADDR addr = 0;
1818 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1819 {
1820 /* Fetch floating point register rename base from current
1821 frame marker for this frame. */
1822 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1823
1824 /* Adjust the floating point register number to account for
1825 register rotation. */
1826 regnum = IA64_FR32_REGNUM
1827 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1828 }
1829
1830 /* If we have stored a memory address, access the register. */
1831 addr = cache->saved_regs[regnum];
1832 if (addr != 0)
1833 {
1834 *lvalp = lval_memory;
1835 *addrp = addr;
1836 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1837 }
1838 /* Otherwise, punt and get the current value of the register. */
1839 else
1840 frame_unwind_register (next_frame, regnum, valuep);
1841 }
1842 }
1843
1844 static const struct frame_unwind ia64_frame_unwind =
1845 {
1846 NORMAL_FRAME,
1847 &ia64_frame_this_id,
1848 &ia64_frame_prev_register
1849 };
1850
1851 static const struct frame_unwind *
1852 ia64_frame_sniffer (struct frame_info *next_frame)
1853 {
1854 return &ia64_frame_unwind;
1855 }
1856
1857 /* Signal trampolines. */
1858
1859 static void
1860 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1861 {
1862 if (SIGCONTEXT_REGISTER_ADDRESS)
1863 {
1864 int regno;
1865
1866 cache->saved_regs[IA64_VRAP_REGNUM] =
1867 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1868 cache->saved_regs[IA64_CFM_REGNUM] =
1869 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1870 cache->saved_regs[IA64_PSR_REGNUM] =
1871 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1872 #if 0
1873 cache->saved_regs[IA64_BSP_REGNUM] =
1874 SIGCONTEXT_REGISTER_ADDRESS (frame->frame, IA64_BSP_REGNUM);
1875 #endif
1876 cache->saved_regs[IA64_RNAT_REGNUM] =
1877 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1878 cache->saved_regs[IA64_CCV_REGNUM] =
1879 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1880 cache->saved_regs[IA64_UNAT_REGNUM] =
1881 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1882 cache->saved_regs[IA64_FPSR_REGNUM] =
1883 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1884 cache->saved_regs[IA64_PFS_REGNUM] =
1885 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1886 cache->saved_regs[IA64_LC_REGNUM] =
1887 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1888 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1889 if (regno != sp_regnum)
1890 cache->saved_regs[regno] =
1891 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1892 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1893 cache->saved_regs[regno] =
1894 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1895 for (regno = IA64_FR2_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1896 cache->saved_regs[regno] =
1897 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1898 }
1899 }
1900
1901 static struct ia64_frame_cache *
1902 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1903 {
1904 struct ia64_frame_cache *cache;
1905 CORE_ADDR addr;
1906 char buf[8];
1907 int i;
1908
1909 if (*this_cache)
1910 return *this_cache;
1911
1912 cache = ia64_alloc_frame_cache ();
1913
1914 frame_unwind_register (next_frame, sp_regnum, buf);
1915 cache->base = extract_unsigned_integer (buf, 8) + cache->mem_stack_frame_size;
1916
1917 ia64_sigtramp_frame_init_saved_regs (cache);
1918
1919 *this_cache = cache;
1920 return cache;
1921 }
1922
1923 static void
1924 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1925 void **this_cache, struct frame_id *this_id)
1926 {
1927 struct ia64_frame_cache *cache =
1928 ia64_sigtramp_frame_cache (next_frame, this_cache);
1929
1930 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
1931 }
1932
1933 static void
1934 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1935 void **this_cache,
1936 int regnum, int *optimizedp,
1937 enum lval_type *lvalp, CORE_ADDR *addrp,
1938 int *realnump, void *valuep)
1939 {
1940 /* Make sure we've initialized the cache. */
1941 ia64_sigtramp_frame_cache (next_frame, this_cache);
1942
1943 ia64_frame_prev_register (next_frame, this_cache, regnum,
1944 optimizedp, lvalp, addrp, realnump, valuep);
1945 }
1946
1947 static const struct frame_unwind ia64_sigtramp_frame_unwind =
1948 {
1949 SIGTRAMP_FRAME,
1950 ia64_sigtramp_frame_this_id,
1951 ia64_sigtramp_frame_prev_register
1952 };
1953
1954 static const struct frame_unwind *
1955 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
1956 {
1957 char *name;
1958 CORE_ADDR pc = frame_pc_unwind (next_frame);
1959
1960 find_pc_partial_function (pc, &name, NULL, NULL);
1961 if (PC_IN_SIGTRAMP (pc, name))
1962 return &ia64_sigtramp_frame_unwind;
1963
1964 return NULL;
1965 }
1966 \f
1967
1968 static CORE_ADDR
1969 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1970 {
1971 struct ia64_frame_cache *cache =
1972 ia64_frame_cache (next_frame, this_cache);
1973
1974 return cache->base;
1975 }
1976
1977 static const struct frame_base ia64_frame_base =
1978 {
1979 &ia64_frame_unwind,
1980 ia64_frame_base_address,
1981 ia64_frame_base_address,
1982 ia64_frame_base_address
1983 };
1984
1985 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
1986 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
1987 and TYPE is the type (which is known to be struct, union or array). */
1988 int
1989 ia64_use_struct_convention (int gcc_p, struct type *type)
1990 {
1991 struct type *float_elt_type;
1992
1993 /* HFAs are structures (or arrays) consisting entirely of floating
1994 point values of the same length. Up to 8 of these are returned
1995 in registers. Don't use the struct convention when this is the
1996 case. */
1997 float_elt_type = is_float_or_hfa_type (type);
1998 if (float_elt_type != NULL
1999 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2000 return 0;
2001
2002 /* Other structs of length 32 or less are returned in r8-r11.
2003 Don't use the struct convention for those either. */
2004 return TYPE_LENGTH (type) > 32;
2005 }
2006
2007 void
2008 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2009 {
2010 struct type *float_elt_type;
2011
2012 float_elt_type = is_float_or_hfa_type (type);
2013 if (float_elt_type != NULL)
2014 {
2015 char from[MAX_REGISTER_SIZE];
2016 int offset = 0;
2017 int regnum = IA64_FR8_REGNUM;
2018 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2019
2020 while (n-- > 0)
2021 {
2022 regcache_cooked_read (regcache, regnum, from);
2023 convert_typed_floating (from, builtin_type_ia64_ext,
2024 (char *)valbuf + offset, float_elt_type);
2025 offset += TYPE_LENGTH (float_elt_type);
2026 regnum++;
2027 }
2028 }
2029 else
2030 {
2031 ULONGEST val;
2032 int offset = 0;
2033 int regnum = IA64_GR8_REGNUM;
2034 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2035 int n = TYPE_LENGTH (type) / reglen;
2036 int m = TYPE_LENGTH (type) % reglen;
2037
2038 while (n-- > 0)
2039 {
2040 ULONGEST val;
2041 regcache_cooked_read_unsigned (regcache, regnum, &val);
2042 memcpy ((char *)valbuf + offset, &val, reglen);
2043 offset += reglen;
2044 regnum++;
2045 }
2046
2047 if (m)
2048 {
2049 regcache_cooked_read_unsigned (regcache, regnum, &val);
2050 memcpy ((char *)valbuf + offset, &val, m);
2051 }
2052 }
2053 }
2054
2055 CORE_ADDR
2056 ia64_extract_struct_value_address (struct regcache *regcache)
2057 {
2058 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2059 return 0;
2060 }
2061
2062
2063 static int
2064 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2065 {
2066 switch (TYPE_CODE (t))
2067 {
2068 case TYPE_CODE_FLT:
2069 if (*etp)
2070 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2071 else
2072 {
2073 *etp = t;
2074 return 1;
2075 }
2076 break;
2077 case TYPE_CODE_ARRAY:
2078 return
2079 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2080 etp);
2081 break;
2082 case TYPE_CODE_STRUCT:
2083 {
2084 int i;
2085
2086 for (i = 0; i < TYPE_NFIELDS (t); i++)
2087 if (!is_float_or_hfa_type_recurse
2088 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2089 return 0;
2090 return 1;
2091 }
2092 break;
2093 default:
2094 return 0;
2095 break;
2096 }
2097 }
2098
2099 /* Determine if the given type is one of the floating point types or
2100 and HFA (which is a struct, array, or combination thereof whose
2101 bottom-most elements are all of the same floating point type). */
2102
2103 static struct type *
2104 is_float_or_hfa_type (struct type *t)
2105 {
2106 struct type *et = 0;
2107
2108 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2109 }
2110
2111
2112 /* Return 1 if the alignment of T is such that the next even slot
2113 should be used. Return 0, if the next available slot should
2114 be used. (See section 8.5.1 of the IA-64 Software Conventions
2115 and Runtime manual). */
2116
2117 static int
2118 slot_alignment_is_next_even (struct type *t)
2119 {
2120 switch (TYPE_CODE (t))
2121 {
2122 case TYPE_CODE_INT:
2123 case TYPE_CODE_FLT:
2124 if (TYPE_LENGTH (t) > 8)
2125 return 1;
2126 else
2127 return 0;
2128 case TYPE_CODE_ARRAY:
2129 return
2130 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2131 case TYPE_CODE_STRUCT:
2132 {
2133 int i;
2134
2135 for (i = 0; i < TYPE_NFIELDS (t); i++)
2136 if (slot_alignment_is_next_even
2137 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2138 return 1;
2139 return 0;
2140 }
2141 default:
2142 return 0;
2143 }
2144 }
2145
2146 /* Attempt to find (and return) the global pointer for the given
2147 function.
2148
2149 This is a rather nasty bit of code searchs for the .dynamic section
2150 in the objfile corresponding to the pc of the function we're trying
2151 to call. Once it finds the addresses at which the .dynamic section
2152 lives in the child process, it scans the Elf64_Dyn entries for a
2153 DT_PLTGOT tag. If it finds one of these, the corresponding
2154 d_un.d_ptr value is the global pointer. */
2155
2156 static CORE_ADDR
2157 generic_elf_find_global_pointer (CORE_ADDR faddr)
2158 {
2159 struct obj_section *faddr_sect;
2160
2161 faddr_sect = find_pc_section (faddr);
2162 if (faddr_sect != NULL)
2163 {
2164 struct obj_section *osect;
2165
2166 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2167 {
2168 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2169 break;
2170 }
2171
2172 if (osect < faddr_sect->objfile->sections_end)
2173 {
2174 CORE_ADDR addr;
2175
2176 addr = osect->addr;
2177 while (addr < osect->endaddr)
2178 {
2179 int status;
2180 LONGEST tag;
2181 char buf[8];
2182
2183 status = target_read_memory (addr, buf, sizeof (buf));
2184 if (status != 0)
2185 break;
2186 tag = extract_signed_integer (buf, sizeof (buf));
2187
2188 if (tag == DT_PLTGOT)
2189 {
2190 CORE_ADDR global_pointer;
2191
2192 status = target_read_memory (addr + 8, buf, sizeof (buf));
2193 if (status != 0)
2194 break;
2195 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2196
2197 /* The payoff... */
2198 return global_pointer;
2199 }
2200
2201 if (tag == DT_NULL)
2202 break;
2203
2204 addr += 16;
2205 }
2206 }
2207 }
2208 return 0;
2209 }
2210
2211 /* Given a function's address, attempt to find (and return) the
2212 corresponding (canonical) function descriptor. Return 0 if
2213 not found. */
2214 static CORE_ADDR
2215 find_extant_func_descr (CORE_ADDR faddr)
2216 {
2217 struct obj_section *faddr_sect;
2218
2219 /* Return early if faddr is already a function descriptor. */
2220 faddr_sect = find_pc_section (faddr);
2221 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2222 return faddr;
2223
2224 if (faddr_sect != NULL)
2225 {
2226 struct obj_section *osect;
2227 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2228 {
2229 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2230 break;
2231 }
2232
2233 if (osect < faddr_sect->objfile->sections_end)
2234 {
2235 CORE_ADDR addr;
2236
2237 addr = osect->addr;
2238 while (addr < osect->endaddr)
2239 {
2240 int status;
2241 LONGEST faddr2;
2242 char buf[8];
2243
2244 status = target_read_memory (addr, buf, sizeof (buf));
2245 if (status != 0)
2246 break;
2247 faddr2 = extract_signed_integer (buf, sizeof (buf));
2248
2249 if (faddr == faddr2)
2250 return addr;
2251
2252 addr += 16;
2253 }
2254 }
2255 }
2256 return 0;
2257 }
2258
2259 /* Attempt to find a function descriptor corresponding to the
2260 given address. If none is found, construct one on the
2261 stack using the address at fdaptr. */
2262
2263 static CORE_ADDR
2264 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2265 {
2266 CORE_ADDR fdesc;
2267
2268 fdesc = find_extant_func_descr (faddr);
2269
2270 if (fdesc == 0)
2271 {
2272 CORE_ADDR global_pointer;
2273 char buf[16];
2274
2275 fdesc = *fdaptr;
2276 *fdaptr += 16;
2277
2278 global_pointer = FIND_GLOBAL_POINTER (faddr);
2279
2280 if (global_pointer == 0)
2281 global_pointer = read_register (IA64_GR1_REGNUM);
2282
2283 store_unsigned_integer (buf, 8, faddr);
2284 store_unsigned_integer (buf + 8, 8, global_pointer);
2285
2286 write_memory (fdesc, buf, 16);
2287 }
2288
2289 return fdesc;
2290 }
2291
2292 /* Use the following routine when printing out function pointers
2293 so the user can see the function address rather than just the
2294 function descriptor. */
2295 static CORE_ADDR
2296 ia64_convert_from_func_ptr_addr (CORE_ADDR addr)
2297 {
2298 struct obj_section *s;
2299
2300 s = find_pc_section (addr);
2301
2302 /* check if ADDR points to a function descriptor. */
2303 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2304 return read_memory_unsigned_integer (addr, 8);
2305
2306 return addr;
2307 }
2308
2309 static CORE_ADDR
2310 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2311 {
2312 return sp & ~0xfLL;
2313 }
2314
2315 static CORE_ADDR
2316 ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2317 struct regcache *regcache, CORE_ADDR bp_addr,
2318 int nargs, struct value **args, CORE_ADDR sp,
2319 int struct_return, CORE_ADDR struct_addr)
2320 {
2321 int argno;
2322 struct value *arg;
2323 struct type *type;
2324 int len, argoffset;
2325 int nslots, rseslots, memslots, slotnum, nfuncargs;
2326 int floatreg;
2327 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
2328
2329 nslots = 0;
2330 nfuncargs = 0;
2331 /* Count the number of slots needed for the arguments. */
2332 for (argno = 0; argno < nargs; argno++)
2333 {
2334 arg = args[argno];
2335 type = check_typedef (VALUE_TYPE (arg));
2336 len = TYPE_LENGTH (type);
2337
2338 if ((nslots & 1) && slot_alignment_is_next_even (type))
2339 nslots++;
2340
2341 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
2342 nfuncargs++;
2343
2344 nslots += (len + 7) / 8;
2345 }
2346
2347 /* Divvy up the slots between the RSE and the memory stack. */
2348 rseslots = (nslots > 8) ? 8 : nslots;
2349 memslots = nslots - rseslots;
2350
2351 /* Allocate a new RSE frame. */
2352 cfm = read_register (IA64_CFM_REGNUM);
2353
2354 bsp = read_register (IA64_BSP_REGNUM);
2355 new_bsp = rse_address_add (bsp, rseslots);
2356 write_register (IA64_BSP_REGNUM, new_bsp);
2357
2358 pfs = read_register (IA64_PFS_REGNUM);
2359 pfs &= 0xc000000000000000LL;
2360 pfs |= (cfm & 0xffffffffffffLL);
2361 write_register (IA64_PFS_REGNUM, pfs);
2362
2363 cfm &= 0xc000000000000000LL;
2364 cfm |= rseslots;
2365 write_register (IA64_CFM_REGNUM, cfm);
2366
2367 /* We will attempt to find function descriptors in the .opd segment,
2368 but if we can't we'll construct them ourselves. That being the
2369 case, we'll need to reserve space on the stack for them. */
2370 funcdescaddr = sp - nfuncargs * 16;
2371 funcdescaddr &= ~0xfLL;
2372
2373 /* Adjust the stack pointer to it's new value. The calling conventions
2374 require us to have 16 bytes of scratch, plus whatever space is
2375 necessary for the memory slots and our function descriptors. */
2376 sp = sp - 16 - (memslots + nfuncargs) * 8;
2377 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
2378
2379 /* Place the arguments where they belong. The arguments will be
2380 either placed in the RSE backing store or on the memory stack.
2381 In addition, floating point arguments or HFAs are placed in
2382 floating point registers. */
2383 slotnum = 0;
2384 floatreg = IA64_FR8_REGNUM;
2385 for (argno = 0; argno < nargs; argno++)
2386 {
2387 struct type *float_elt_type;
2388
2389 arg = args[argno];
2390 type = check_typedef (VALUE_TYPE (arg));
2391 len = TYPE_LENGTH (type);
2392
2393 /* Special handling for function parameters. */
2394 if (len == 8
2395 && TYPE_CODE (type) == TYPE_CODE_PTR
2396 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
2397 {
2398 char val_buf[8];
2399
2400 store_unsigned_integer (val_buf, 8,
2401 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
2402 &funcdescaddr));
2403 if (slotnum < rseslots)
2404 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2405 else
2406 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2407 slotnum++;
2408 continue;
2409 }
2410
2411 /* Normal slots. */
2412
2413 /* Skip odd slot if necessary... */
2414 if ((slotnum & 1) && slot_alignment_is_next_even (type))
2415 slotnum++;
2416
2417 argoffset = 0;
2418 while (len > 0)
2419 {
2420 char val_buf[8];
2421
2422 memset (val_buf, 0, 8);
2423 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
2424
2425 if (slotnum < rseslots)
2426 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2427 else
2428 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2429
2430 argoffset += 8;
2431 len -= 8;
2432 slotnum++;
2433 }
2434
2435 /* Handle floating point types (including HFAs). */
2436 float_elt_type = is_float_or_hfa_type (type);
2437 if (float_elt_type != NULL)
2438 {
2439 argoffset = 0;
2440 len = TYPE_LENGTH (type);
2441 while (len > 0 && floatreg < IA64_FR16_REGNUM)
2442 {
2443 char to[MAX_REGISTER_SIZE];
2444 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
2445 to, builtin_type_ia64_ext);
2446 regcache_cooked_write (regcache, floatreg, (void *)to);
2447 floatreg++;
2448 argoffset += TYPE_LENGTH (float_elt_type);
2449 len -= TYPE_LENGTH (float_elt_type);
2450 }
2451 }
2452 }
2453
2454 /* Store the struct return value in r8 if necessary. */
2455 if (struct_return)
2456 {
2457 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
2458 }
2459
2460 global_pointer = FIND_GLOBAL_POINTER (func_addr);
2461
2462 if (global_pointer != 0)
2463 write_register (IA64_GR1_REGNUM, global_pointer);
2464
2465 write_register (IA64_BR0_REGNUM, bp_addr);
2466
2467 write_register (sp_regnum, sp);
2468
2469 return sp;
2470 }
2471
2472 static struct frame_id
2473 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2474 {
2475 char buf[8];
2476 CORE_ADDR sp;
2477
2478 frame_unwind_register (next_frame, sp_regnum, buf);
2479 sp = extract_unsigned_integer (buf, 8);
2480
2481 return frame_id_build (sp, frame_pc_unwind (next_frame));
2482 }
2483
2484 static CORE_ADDR
2485 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2486 {
2487 char buf[8];
2488 CORE_ADDR ip, psr, pc;
2489
2490 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2491 ip = extract_unsigned_integer (buf, 8);
2492 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2493 psr = extract_unsigned_integer (buf, 8);
2494
2495 pc = (ip & ~0xf) | ((psr >> 41) & 3);
2496 return pc;
2497 }
2498
2499 static void
2500 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
2501 {
2502 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2503 {
2504 char to[MAX_REGISTER_SIZE];
2505 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
2506 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
2507 target_store_registers (IA64_FR8_REGNUM);
2508 }
2509 else
2510 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
2511 }
2512
2513 static void
2514 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
2515 struct regcache *regcache,
2516 CORE_ADDR memaddr, int nr_bytes,
2517 CORE_ADDR *targ_addr, int *targ_len)
2518 {
2519 *targ_addr = memaddr;
2520 *targ_len = nr_bytes;
2521 }
2522
2523 static void
2524 process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2525 {
2526 int *os_ident_ptr = obj;
2527 const char *name;
2528 unsigned int sectsize;
2529
2530 name = bfd_get_section_name (abfd, sect);
2531 sectsize = bfd_section_size (abfd, sect);
2532 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2533 {
2534 unsigned int name_length, data_length, note_type;
2535 char *note = alloca (sectsize);
2536
2537 bfd_get_section_contents (abfd, sect, note,
2538 (file_ptr) 0, (bfd_size_type) sectsize);
2539
2540 name_length = bfd_h_get_32 (abfd, note);
2541 data_length = bfd_h_get_32 (abfd, note + 4);
2542 note_type = bfd_h_get_32 (abfd, note + 8);
2543
2544 if (name_length == 4 && data_length == 16 && note_type == 1
2545 && strcmp (note + 12, "GNU") == 0)
2546 {
2547 int os_number = bfd_h_get_32 (abfd, note + 16);
2548
2549 /* The case numbers are from abi-tags in glibc. */
2550 switch (os_number)
2551 {
2552 case 0 :
2553 *os_ident_ptr = ELFOSABI_LINUX;
2554 break;
2555 case 1 :
2556 *os_ident_ptr = ELFOSABI_HURD;
2557 break;
2558 case 2 :
2559 *os_ident_ptr = ELFOSABI_SOLARIS;
2560 break;
2561 default :
2562 internal_error (__FILE__, __LINE__,
2563 "process_note_abi_sections: unknown OS number %d", os_number);
2564 break;
2565 }
2566 }
2567 }
2568 }
2569
2570 static int
2571 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
2572 {
2573 info->bytes_per_line = SLOT_MULTIPLIER;
2574 return print_insn_ia64 (memaddr, info);
2575 }
2576
2577 static struct gdbarch *
2578 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2579 {
2580 struct gdbarch *gdbarch;
2581 struct gdbarch_tdep *tdep;
2582 int os_ident;
2583
2584 if (info.abfd != NULL
2585 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2586 {
2587 os_ident = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2588
2589 /* If os_ident is 0, it is not necessarily the case that we're
2590 on a SYSV system. (ELFOSABI_NONE is defined to be 0.)
2591 GNU/Linux uses a note section to record OS/ABI info, but
2592 leaves e_ident[EI_OSABI] zero. So we have to check for note
2593 sections too. */
2594 if (os_ident == 0)
2595 {
2596 bfd_map_over_sections (info.abfd,
2597 process_note_abi_tag_sections,
2598 &os_ident);
2599 }
2600 }
2601 else
2602 os_ident = -1;
2603
2604 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2605 arches != NULL;
2606 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2607 {
2608 tdep = gdbarch_tdep (arches->gdbarch);
2609 if (tdep &&tdep->os_ident == os_ident)
2610 return arches->gdbarch;
2611 }
2612
2613 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2614 gdbarch = gdbarch_alloc (&info, tdep);
2615 tdep->os_ident = os_ident;
2616
2617 /* Set the method of obtaining the sigcontext addresses at which
2618 registers are saved. The method of checking to see if
2619 native_find_global_pointer is nonzero to indicate that we're
2620 on AIX is kind of hokey, but I can't think of a better way
2621 to do it. */
2622 if (os_ident == ELFOSABI_LINUX)
2623 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
2624 else if (native_find_global_pointer != 0)
2625 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
2626 else
2627 tdep->sigcontext_register_address = 0;
2628
2629 /* We know that GNU/Linux won't have to resort to the
2630 native_find_global_pointer hackery. But that's the only one we
2631 know about so far, so if native_find_global_pointer is set to
2632 something non-zero, then use it. Otherwise fall back to using
2633 generic_elf_find_global_pointer. This arrangement should (in
2634 theory) allow us to cross debug GNU/Linux binaries from an AIX
2635 machine. */
2636 if (os_ident == ELFOSABI_LINUX)
2637 tdep->find_global_pointer = generic_elf_find_global_pointer;
2638 else if (native_find_global_pointer != 0)
2639 tdep->find_global_pointer = native_find_global_pointer;
2640 else
2641 tdep->find_global_pointer = generic_elf_find_global_pointer;
2642
2643 /* Define the ia64 floating-point format to gdb. */
2644 builtin_type_ia64_ext =
2645 init_type (TYPE_CODE_FLT, 128 / 8,
2646 0, "builtin_type_ia64_ext", NULL);
2647 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
2648
2649 set_gdbarch_short_bit (gdbarch, 16);
2650 set_gdbarch_int_bit (gdbarch, 32);
2651 set_gdbarch_long_bit (gdbarch, 64);
2652 set_gdbarch_long_long_bit (gdbarch, 64);
2653 set_gdbarch_float_bit (gdbarch, 32);
2654 set_gdbarch_double_bit (gdbarch, 64);
2655 set_gdbarch_long_double_bit (gdbarch, 128);
2656 set_gdbarch_ptr_bit (gdbarch, 64);
2657
2658 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
2659 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
2660 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
2661 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
2662
2663 set_gdbarch_register_name (gdbarch, ia64_register_name);
2664 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2665 gets a number of extra failures. */
2666 set_gdbarch_deprecated_register_size (gdbarch, 8);
2667 set_gdbarch_register_type (gdbarch, ia64_register_type);
2668
2669 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
2670 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
2671 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
2672 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
2673 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
2674 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
2675 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
2676
2677 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
2678
2679 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
2680 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
2681
2682 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
2683 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
2684
2685 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
2686 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
2687 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
2688 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
2689 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
2690
2691 /* Settings for calling functions in the inferior. */
2692 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
2693 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
2694 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
2695
2696 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
2697 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
2698 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
2699 frame_base_set_default (gdbarch, &ia64_frame_base);
2700
2701 /* Settings that should be unnecessary. */
2702 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2703
2704 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2705 set_gdbarch_function_start_offset (gdbarch, 0);
2706 set_gdbarch_frame_args_skip (gdbarch, 0);
2707
2708 set_gdbarch_remote_translate_xfer_address (
2709 gdbarch, ia64_remote_translate_xfer_address);
2710
2711 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
2712 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
2713
2714 return gdbarch;
2715 }
2716
2717 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
2718
2719 void
2720 _initialize_ia64_tdep (void)
2721 {
2722 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
2723 }
GDB Binutils - Deliverables
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