1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "arch-utils.h"
27 #include "floatformat.h"
29 #include "reggroups.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
35 #include "gdb_assert.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
42 #include "ia64-tdep.h"
44 #ifdef HAVE_LIBUNWIND_IA64_H
45 #include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
46 #include "libunwind-frame.h"
47 #include "libunwind-ia64.h"
50 /* An enumeration of the different IA-64 instruction types. */
52 typedef enum instruction_type
54 A
, /* Integer ALU ; I-unit or M-unit */
55 I
, /* Non-ALU integer; I-unit */
56 M
, /* Memory ; M-unit */
57 F
, /* Floating-point ; F-unit */
58 B
, /* Branch ; B-unit */
59 L
, /* Extended (L+X) ; I-unit */
60 X
, /* Extended (L+X) ; I-unit */
61 undefined
/* undefined or reserved */
64 /* We represent IA-64 PC addresses as the value of the instruction
65 pointer or'd with some bit combination in the low nibble which
66 represents the slot number in the bundle addressed by the
67 instruction pointer. The problem is that the Linux kernel
68 multiplies its slot numbers (for exceptions) by one while the
69 disassembler multiplies its slot numbers by 6. In addition, I've
70 heard it said that the simulator uses 1 as the multiplier.
72 I've fixed the disassembler so that the bytes_per_line field will
73 be the slot multiplier. If bytes_per_line comes in as zero, it
74 is set to six (which is how it was set up initially). -- objdump
75 displays pretty disassembly dumps with this value. For our purposes,
76 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
77 never want to also display the raw bytes the way objdump does. */
79 #define SLOT_MULTIPLIER 1
81 /* Length in bytes of an instruction bundle */
85 static gdbarch_init_ftype ia64_gdbarch_init
;
87 static gdbarch_register_name_ftype ia64_register_name
;
88 static gdbarch_register_type_ftype ia64_register_type
;
89 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc
;
90 static gdbarch_skip_prologue_ftype ia64_skip_prologue
;
91 static struct type
*is_float_or_hfa_type (struct type
*t
);
92 static CORE_ADDR
ia64_find_global_pointer (CORE_ADDR faddr
);
94 static struct type
*builtin_type_ia64_ext
;
96 #define NUM_IA64_RAW_REGS 462
98 static int sp_regnum
= IA64_GR12_REGNUM
;
99 static int fp_regnum
= IA64_VFP_REGNUM
;
100 static int lr_regnum
= IA64_VRAP_REGNUM
;
102 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
103 they may not be accessible via the ptrace register get/set interfaces. */
104 enum pseudo_regs
{ FIRST_PSEUDO_REGNUM
= NUM_IA64_RAW_REGS
, VBOF_REGNUM
= IA64_NAT127_REGNUM
+ 1, V32_REGNUM
,
105 V127_REGNUM
= V32_REGNUM
+ 95,
106 VP0_REGNUM
, VP16_REGNUM
= VP0_REGNUM
+ 16, VP63_REGNUM
= VP0_REGNUM
+ 63, LAST_PSEUDO_REGNUM
};
108 /* Array of register names; There should be ia64_num_regs strings in
111 static char *ia64_register_names
[] =
112 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
113 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
114 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
115 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
116 "", "", "", "", "", "", "", "",
117 "", "", "", "", "", "", "", "",
118 "", "", "", "", "", "", "", "",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
129 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
130 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
131 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
132 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
133 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
134 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
135 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
136 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
137 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
138 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
139 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
140 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
141 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
142 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
143 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
144 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
155 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
159 "pr", "ip", "psr", "cfm",
161 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
162 "", "", "", "", "", "", "", "",
163 "rsc", "bsp", "bspstore", "rnat",
165 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
166 "ccv", "", "", "", "unat", "", "", "",
167 "fpsr", "", "", "", "itc",
168 "", "", "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "", "", "",
174 "", "", "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "", "", "",
178 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
179 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
180 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
181 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
182 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
183 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
184 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
185 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
186 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
187 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
188 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
189 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
190 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
191 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
192 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
193 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
197 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
198 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
199 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
200 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
201 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
202 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
203 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
204 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
205 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
206 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
207 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
208 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
210 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
211 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
212 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
213 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
214 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
215 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
216 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
217 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
220 struct ia64_frame_cache
222 CORE_ADDR base
; /* frame pointer base for frame */
223 CORE_ADDR pc
; /* function start pc for frame */
224 CORE_ADDR saved_sp
; /* stack pointer for frame */
225 CORE_ADDR bsp
; /* points at r32 for the current frame */
226 CORE_ADDR cfm
; /* cfm value for current frame */
227 CORE_ADDR prev_cfm
; /* cfm value for previous frame */
229 int sof
; /* Size of frame (decoded from cfm value) */
230 int sol
; /* Size of locals (decoded from cfm value) */
231 int sor
; /* Number of rotating registers. (decoded from cfm value) */
232 CORE_ADDR after_prologue
;
233 /* Address of first instruction after the last
234 prologue instruction; Note that there may
235 be instructions from the function's body
236 intermingled with the prologue. */
237 int mem_stack_frame_size
;
238 /* Size of the memory stack frame (may be zero),
239 or -1 if it has not been determined yet. */
240 int fp_reg
; /* Register number (if any) used a frame pointer
241 for this frame. 0 if no register is being used
242 as the frame pointer. */
244 /* Saved registers. */
245 CORE_ADDR saved_regs
[NUM_IA64_RAW_REGS
];
249 #define SIGCONTEXT_REGISTER_ADDRESS \
250 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
253 ia64_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
254 struct reggroup
*group
)
259 if (group
== all_reggroup
)
261 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
262 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
263 raw_p
= regnum
< NUM_IA64_RAW_REGS
;
264 if (group
== float_reggroup
)
266 if (group
== vector_reggroup
)
268 if (group
== general_reggroup
)
269 return (!vector_p
&& !float_p
);
270 if (group
== save_reggroup
|| group
== restore_reggroup
)
276 ia64_register_name (int reg
)
278 return ia64_register_names
[reg
];
282 ia64_register_type (struct gdbarch
*arch
, int reg
)
284 if (reg
>= IA64_FR0_REGNUM
&& reg
<= IA64_FR127_REGNUM
)
285 return builtin_type_ia64_ext
;
287 return builtin_type_long
;
291 ia64_dwarf_reg_to_regnum (int reg
)
293 if (reg
>= IA64_GR32_REGNUM
&& reg
<= IA64_GR127_REGNUM
)
294 return V32_REGNUM
+ (reg
- IA64_GR32_REGNUM
);
299 floatformat_valid (const struct floatformat
*fmt
, const char *from
)
304 const struct floatformat floatformat_ia64_ext
=
306 floatformat_little
, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
307 floatformat_intbit_yes
, "floatformat_ia64_ext", floatformat_valid
311 /* Extract ``len'' bits from an instruction bundle starting at
315 extract_bit_field (char *bundle
, int from
, int len
)
317 long long result
= 0LL;
319 int from_byte
= from
/ 8;
320 int to_byte
= to
/ 8;
321 unsigned char *b
= (unsigned char *) bundle
;
327 if (from_byte
== to_byte
)
328 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
329 result
= c
>> (from
% 8);
330 lshift
= 8 - (from
% 8);
332 for (i
= from_byte
+1; i
< to_byte
; i
++)
334 result
|= ((long long) b
[i
]) << lshift
;
338 if (from_byte
< to_byte
&& (to
% 8 != 0))
341 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
342 result
|= ((long long) c
) << lshift
;
348 /* Replace the specified bits in an instruction bundle */
351 replace_bit_field (char *bundle
, long long val
, int from
, int len
)
354 int from_byte
= from
/ 8;
355 int to_byte
= to
/ 8;
356 unsigned char *b
= (unsigned char *) bundle
;
359 if (from_byte
== to_byte
)
361 unsigned char left
, right
;
363 left
= (c
>> (to
% 8)) << (to
% 8);
364 right
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
365 c
= (unsigned char) (val
& 0xff);
366 c
= (unsigned char) (c
<< (from
% 8 + 8 - to
% 8)) >> (8 - to
% 8);
374 c
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
375 c
= c
| (val
<< (from
% 8));
377 val
>>= 8 - from
% 8;
379 for (i
= from_byte
+1; i
< to_byte
; i
++)
388 unsigned char cv
= (unsigned char) val
;
390 c
= c
>> (to
% 8) << (to
% 8);
391 c
|= ((unsigned char) (cv
<< (8 - to
% 8))) >> (8 - to
% 8);
397 /* Return the contents of slot N (for N = 0, 1, or 2) in
398 and instruction bundle */
401 slotN_contents (char *bundle
, int slotnum
)
403 return extract_bit_field (bundle
, 5+41*slotnum
, 41);
406 /* Store an instruction in an instruction bundle */
409 replace_slotN_contents (char *bundle
, long long instr
, int slotnum
)
411 replace_bit_field (bundle
, instr
, 5+41*slotnum
, 41);
414 static enum instruction_type template_encoding_table
[32][3] =
416 { M
, I
, I
}, /* 00 */
417 { M
, I
, I
}, /* 01 */
418 { M
, I
, I
}, /* 02 */
419 { M
, I
, I
}, /* 03 */
420 { M
, L
, X
}, /* 04 */
421 { M
, L
, X
}, /* 05 */
422 { undefined
, undefined
, undefined
}, /* 06 */
423 { undefined
, undefined
, undefined
}, /* 07 */
424 { M
, M
, I
}, /* 08 */
425 { M
, M
, I
}, /* 09 */
426 { M
, M
, I
}, /* 0A */
427 { M
, M
, I
}, /* 0B */
428 { M
, F
, I
}, /* 0C */
429 { M
, F
, I
}, /* 0D */
430 { M
, M
, F
}, /* 0E */
431 { M
, M
, F
}, /* 0F */
432 { M
, I
, B
}, /* 10 */
433 { M
, I
, B
}, /* 11 */
434 { M
, B
, B
}, /* 12 */
435 { M
, B
, B
}, /* 13 */
436 { undefined
, undefined
, undefined
}, /* 14 */
437 { undefined
, undefined
, undefined
}, /* 15 */
438 { B
, B
, B
}, /* 16 */
439 { B
, B
, B
}, /* 17 */
440 { M
, M
, B
}, /* 18 */
441 { M
, M
, B
}, /* 19 */
442 { undefined
, undefined
, undefined
}, /* 1A */
443 { undefined
, undefined
, undefined
}, /* 1B */
444 { M
, F
, B
}, /* 1C */
445 { M
, F
, B
}, /* 1D */
446 { undefined
, undefined
, undefined
}, /* 1E */
447 { undefined
, undefined
, undefined
}, /* 1F */
450 /* Fetch and (partially) decode an instruction at ADDR and return the
451 address of the next instruction to fetch. */
454 fetch_instruction (CORE_ADDR addr
, instruction_type
*it
, long long *instr
)
456 char bundle
[BUNDLE_LEN
];
457 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
461 /* Warn about slot numbers greater than 2. We used to generate
462 an error here on the assumption that the user entered an invalid
463 address. But, sometimes GDB itself requests an invalid address.
464 This can (easily) happen when execution stops in a function for
465 which there are no symbols. The prologue scanner will attempt to
466 find the beginning of the function - if the nearest symbol
467 happens to not be aligned on a bundle boundary (16 bytes), the
468 resulting starting address will cause GDB to think that the slot
471 So we warn about it and set the slot number to zero. It is
472 not necessarily a fatal condition, particularly if debugging
473 at the assembly language level. */
476 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
477 "Using slot 0 instead"));
483 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
488 *instr
= slotN_contents (bundle
, slotnum
);
489 template = extract_bit_field (bundle
, 0, 5);
490 *it
= template_encoding_table
[(int)template][slotnum
];
492 if (slotnum
== 2 || (slotnum
== 1 && *it
== L
))
495 addr
+= (slotnum
+ 1) * SLOT_MULTIPLIER
;
500 /* There are 5 different break instructions (break.i, break.b,
501 break.m, break.f, and break.x), but they all have the same
502 encoding. (The five bit template in the low five bits of the
503 instruction bundle distinguishes one from another.)
505 The runtime architecture manual specifies that break instructions
506 used for debugging purposes must have the upper two bits of the 21
507 bit immediate set to a 0 and a 1 respectively. A breakpoint
508 instruction encodes the most significant bit of its 21 bit
509 immediate at bit 36 of the 41 bit instruction. The penultimate msb
510 is at bit 25 which leads to the pattern below.
512 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
513 it turns out that 0x80000 was used as the syscall break in the early
514 simulators. So I changed the pattern slightly to do "break.i 0x080001"
515 instead. But that didn't work either (I later found out that this
516 pattern was used by the simulator that I was using.) So I ended up
517 using the pattern seen below. */
520 #define IA64_BREAKPOINT 0x00002000040LL
522 #define IA64_BREAKPOINT 0x00003333300LL
525 ia64_memory_insert_breakpoint (CORE_ADDR addr
, bfd_byte
*contents_cache
)
527 char bundle
[BUNDLE_LEN
];
528 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
534 error (_("Can't insert breakpoint for slot numbers greater than 2."));
538 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
540 /* Check for L type instruction in 2nd slot, if present then
541 bump up the slot number to the 3rd slot */
542 template = extract_bit_field (bundle
, 0, 5);
543 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
548 instr
= slotN_contents (bundle
, slotnum
);
549 memcpy(contents_cache
, &instr
, sizeof(instr
));
550 replace_slotN_contents (bundle
, IA64_BREAKPOINT
, slotnum
);
552 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
558 ia64_memory_remove_breakpoint (CORE_ADDR addr
, bfd_byte
*contents_cache
)
560 char bundle
[BUNDLE_LEN
];
561 int slotnum
= (addr
& 0x0f) / SLOT_MULTIPLIER
;
568 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
570 /* Check for L type instruction in 2nd slot, if present then
571 bump up the slot number to the 3rd slot */
572 template = extract_bit_field (bundle
, 0, 5);
573 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
578 memcpy (&instr
, contents_cache
, sizeof instr
);
579 replace_slotN_contents (bundle
, instr
, slotnum
);
581 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
586 /* We don't really want to use this, but remote.c needs to call it in order
587 to figure out if Z-packets are supported or not. Oh, well. */
588 const unsigned char *
589 ia64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
591 static unsigned char breakpoint
[] =
592 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
593 *lenptr
= sizeof (breakpoint
);
601 ia64_read_pc (ptid_t ptid
)
603 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
604 CORE_ADDR pc_value
= read_register_pid (IA64_IP_REGNUM
, ptid
);
605 int slot_num
= (psr_value
>> 41) & 3;
607 return pc_value
| (slot_num
* SLOT_MULTIPLIER
);
611 ia64_write_pc (CORE_ADDR new_pc
, ptid_t ptid
)
613 int slot_num
= (int) (new_pc
& 0xf) / SLOT_MULTIPLIER
;
614 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
615 psr_value
&= ~(3LL << 41);
616 psr_value
|= (CORE_ADDR
)(slot_num
& 0x3) << 41;
620 write_register_pid (IA64_PSR_REGNUM
, psr_value
, ptid
);
621 write_register_pid (IA64_IP_REGNUM
, new_pc
, ptid
);
624 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
626 /* Returns the address of the slot that's NSLOTS slots away from
627 the address ADDR. NSLOTS may be positive or negative. */
629 rse_address_add(CORE_ADDR addr
, int nslots
)
632 int mandatory_nat_slots
= nslots
/ 63;
633 int direction
= nslots
< 0 ? -1 : 1;
635 new_addr
= addr
+ 8 * (nslots
+ mandatory_nat_slots
);
637 if ((new_addr
>> 9) != ((addr
+ 8 * 64 * mandatory_nat_slots
) >> 9))
638 new_addr
+= 8 * direction
;
640 if (IS_NaT_COLLECTION_ADDR(new_addr
))
641 new_addr
+= 8 * direction
;
647 ia64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
648 int regnum
, void *buf
)
650 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
655 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
656 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
658 /* The bsp points at the end of the register frame so we
659 subtract the size of frame from it to get start of register frame. */
660 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
662 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
664 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
665 reg
= read_memory_integer ((CORE_ADDR
)reg_addr
, 8);
666 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), reg
);
669 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), 0);
671 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
675 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
676 unatN_val
= (unat
& (1LL << (regnum
- IA64_NAT0_REGNUM
))) != 0;
677 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), unatN_val
);
679 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
681 ULONGEST natN_val
= 0;
684 CORE_ADDR gr_addr
= 0;
685 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
686 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
688 /* The bsp points at the end of the register frame so we
689 subtract the size of frame from it to get start of register frame. */
690 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
692 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
693 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
697 /* Compute address of nat collection bits. */
698 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
699 CORE_ADDR nat_collection
;
701 /* If our nat collection address is bigger than bsp, we have to get
702 the nat collection from rnat. Otherwise, we fetch the nat
703 collection from the computed address. */
705 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
707 nat_collection
= read_memory_integer (nat_addr
, 8);
708 nat_bit
= (gr_addr
>> 3) & 0x3f;
709 natN_val
= (nat_collection
>> nat_bit
) & 1;
712 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), natN_val
);
714 else if (regnum
== VBOF_REGNUM
)
716 /* A virtual register frame start is provided for user convenience.
717 It can be calculated as the bsp - sof (sizeof frame). */
721 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
722 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
724 /* The bsp points at the end of the register frame so we
725 subtract the size of frame from it to get beginning of frame. */
726 vbsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
727 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), vbsp
);
729 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
735 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
736 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
738 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
740 /* Fetch predicate register rename base from current frame
741 marker for this frame. */
742 int rrb_pr
= (cfm
>> 32) & 0x3f;
744 /* Adjust the register number to account for register rotation. */
746 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
748 prN_val
= (pr
& (1LL << (regnum
- VP0_REGNUM
))) != 0;
749 store_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
), prN_val
);
752 memset (buf
, 0, register_size (current_gdbarch
, regnum
));
756 ia64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
757 int regnum
, const void *buf
)
759 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
764 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
765 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
767 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
769 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
771 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
772 write_memory (reg_addr
, (void *)buf
, 8);
775 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
777 ULONGEST unatN_val
, unat
, unatN_mask
;
778 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
779 unatN_val
= extract_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
));
780 unatN_mask
= (1LL << (regnum
- IA64_NAT0_REGNUM
));
783 else if (unatN_val
== 1)
785 regcache_cooked_write_unsigned (regcache
, IA64_UNAT_REGNUM
, unat
);
787 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
792 CORE_ADDR gr_addr
= 0;
793 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
794 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
796 /* The bsp points at the end of the register frame so we
797 subtract the size of frame from it to get start of register frame. */
798 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
800 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
801 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
803 natN_val
= extract_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
));
805 if (gr_addr
!= 0 && (natN_val
== 0 || natN_val
== 1))
807 /* Compute address of nat collection bits. */
808 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
809 CORE_ADDR nat_collection
;
810 int natN_bit
= (gr_addr
>> 3) & 0x3f;
811 ULONGEST natN_mask
= (1LL << natN_bit
);
812 /* If our nat collection address is bigger than bsp, we have to get
813 the nat collection from rnat. Otherwise, we fetch the nat
814 collection from the computed address. */
817 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
819 nat_collection
|= natN_mask
;
821 nat_collection
&= ~natN_mask
;
822 regcache_cooked_write_unsigned (regcache
, IA64_RNAT_REGNUM
, nat_collection
);
827 nat_collection
= read_memory_integer (nat_addr
, 8);
829 nat_collection
|= natN_mask
;
831 nat_collection
&= ~natN_mask
;
832 store_unsigned_integer (nat_buf
, register_size (current_gdbarch
, regnum
), nat_collection
);
833 write_memory (nat_addr
, nat_buf
, 8);
837 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
844 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
845 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
847 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
849 /* Fetch predicate register rename base from current frame
850 marker for this frame. */
851 int rrb_pr
= (cfm
>> 32) & 0x3f;
853 /* Adjust the register number to account for register rotation. */
855 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
857 prN_val
= extract_unsigned_integer (buf
, register_size (current_gdbarch
, regnum
));
858 prN_mask
= (1LL << (regnum
- VP0_REGNUM
));
861 else if (prN_val
== 1)
863 regcache_cooked_write_unsigned (regcache
, IA64_PR_REGNUM
, pr
);
867 /* The ia64 needs to convert between various ieee floating-point formats
868 and the special ia64 floating point register format. */
871 ia64_convert_register_p (int regno
, struct type
*type
)
873 return (regno
>= IA64_FR0_REGNUM
&& regno
<= IA64_FR127_REGNUM
);
877 ia64_register_to_value (struct frame_info
*frame
, int regnum
,
878 struct type
*valtype
, void *out
)
880 char in
[MAX_REGISTER_SIZE
];
881 frame_register_read (frame
, regnum
, in
);
882 convert_typed_floating (in
, builtin_type_ia64_ext
, out
, valtype
);
886 ia64_value_to_register (struct frame_info
*frame
, int regnum
,
887 struct type
*valtype
, const void *in
)
889 char out
[MAX_REGISTER_SIZE
];
890 convert_typed_floating (in
, valtype
, out
, builtin_type_ia64_ext
);
891 put_frame_register (frame
, regnum
, out
);
895 /* Limit the number of skipped non-prologue instructions since examining
896 of the prologue is expensive. */
897 static int max_skip_non_prologue_insns
= 40;
899 /* Given PC representing the starting address of a function, and
900 LIM_PC which is the (sloppy) limit to which to scan when looking
901 for a prologue, attempt to further refine this limit by using
902 the line data in the symbol table. If successful, a better guess
903 on where the prologue ends is returned, otherwise the previous
904 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
905 which will be set to indicate whether the returned limit may be
906 used with no further scanning in the event that the function is
909 /* FIXME: cagney/2004-02-14: This function and logic have largely been
910 superseded by skip_prologue_using_sal. */
913 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
, int *trust_limit
)
915 struct symtab_and_line prologue_sal
;
916 CORE_ADDR start_pc
= pc
;
918 /* Start off not trusting the limit. */
921 prologue_sal
= find_pc_line (pc
, 0);
922 if (prologue_sal
.line
!= 0)
925 CORE_ADDR addr
= prologue_sal
.end
;
927 /* Handle the case in which compiler's optimizer/scheduler
928 has moved instructions into the prologue. We scan ahead
929 in the function looking for address ranges whose corresponding
930 line number is less than or equal to the first one that we
931 found for the function. (It can be less than when the
932 scheduler puts a body instruction before the first prologue
934 for (i
= 2 * max_skip_non_prologue_insns
;
935 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
938 struct symtab_and_line sal
;
940 sal
= find_pc_line (addr
, 0);
943 if (sal
.line
<= prologue_sal
.line
944 && sal
.symtab
== prologue_sal
.symtab
)
951 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
953 lim_pc
= prologue_sal
.end
;
954 if (start_pc
== get_pc_function_start (lim_pc
))
961 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
962 || (8 <= (_regnum_) && (_regnum_) <= 11) \
963 || (14 <= (_regnum_) && (_regnum_) <= 31))
964 #define imm9(_instr_) \
965 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
966 | (((_instr_) & 0x00008000000LL) >> 20) \
967 | (((_instr_) & 0x00000001fc0LL) >> 6))
969 /* Allocate and initialize a frame cache. */
971 static struct ia64_frame_cache
*
972 ia64_alloc_frame_cache (void)
974 struct ia64_frame_cache
*cache
;
977 cache
= FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache
);
989 cache
->frameless
= 1;
991 for (i
= 0; i
< NUM_IA64_RAW_REGS
; i
++)
992 cache
->saved_regs
[i
] = 0;
998 examine_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct frame_info
*next_frame
, struct ia64_frame_cache
*cache
)
1001 CORE_ADDR last_prologue_pc
= pc
;
1002 instruction_type it
;
1007 int unat_save_reg
= 0;
1008 int pr_save_reg
= 0;
1009 int mem_stack_frame_size
= 0;
1011 CORE_ADDR spill_addr
= 0;
1014 char reg_contents
[256];
1020 CORE_ADDR bof
, sor
, sol
, sof
, cfm
, rrb_gr
;
1022 memset (instores
, 0, sizeof instores
);
1023 memset (infpstores
, 0, sizeof infpstores
);
1024 memset (reg_contents
, 0, sizeof reg_contents
);
1026 if (cache
->after_prologue
!= 0
1027 && cache
->after_prologue
<= lim_pc
)
1028 return cache
->after_prologue
;
1030 lim_pc
= refine_prologue_limit (pc
, lim_pc
, &trust_limit
);
1031 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1033 /* We want to check if we have a recognizable function start before we
1034 look ahead for a prologue. */
1035 if (pc
< lim_pc
&& next_pc
1036 && it
== M
&& ((instr
& 0x1ee0000003fLL
) == 0x02c00000000LL
))
1038 /* alloc - start of a regular function. */
1039 int sor
= (int) ((instr
& 0x00078000000LL
) >> 27);
1040 int sol
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1041 int sof
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1042 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1044 /* Verify that the current cfm matches what we think is the
1045 function start. If we have somehow jumped within a function,
1046 we do not want to interpret the prologue and calculate the
1047 addresses of various registers such as the return address.
1048 We will instead treat the frame as frameless. */
1050 (sof
== (cache
->cfm
& 0x7f) &&
1051 sol
== ((cache
->cfm
>> 7) & 0x7f)))
1055 last_prologue_pc
= next_pc
;
1060 /* Look for a leaf routine. */
1061 if (pc
< lim_pc
&& next_pc
1062 && (it
== I
|| it
== M
)
1063 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1065 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1066 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1067 | ((instr
& 0x001f8000000LL
) >> 20)
1068 | ((instr
& 0x000000fe000LL
) >> 13));
1069 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1070 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1071 int qp
= (int) (instr
& 0x0000000003fLL
);
1072 if (qp
== 0 && rN
== 2 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1074 /* mov r2, r12 - beginning of leaf routine */
1076 last_prologue_pc
= next_pc
;
1080 /* If we don't recognize a regular function or leaf routine, we are
1086 last_prologue_pc
= lim_pc
;
1090 /* Loop, looking for prologue instructions, keeping track of
1091 where preserved registers were spilled. */
1094 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1098 if (it
== B
&& ((instr
& 0x1e1f800003fLL
) != 0x04000000000LL
))
1100 /* Exit loop upon hitting a non-nop branch instruction. */
1105 else if (((instr
& 0x3fLL
) != 0LL) &&
1106 (frameless
|| ret_reg
!= 0))
1108 /* Exit loop upon hitting a predicated instruction if
1109 we already have the return register or if we are frameless. */
1114 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00188000000LL
))
1117 int b2
= (int) ((instr
& 0x0000000e000LL
) >> 13);
1118 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1119 int qp
= (int) (instr
& 0x0000000003f);
1121 if (qp
== 0 && b2
== 0 && rN
>= 32 && ret_reg
== 0)
1124 last_prologue_pc
= next_pc
;
1127 else if ((it
== I
|| it
== M
)
1128 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1130 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1131 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1132 | ((instr
& 0x001f8000000LL
) >> 20)
1133 | ((instr
& 0x000000fe000LL
) >> 13));
1134 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1135 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1136 int qp
= (int) (instr
& 0x0000000003fLL
);
1138 if (qp
== 0 && rN
>= 32 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1142 last_prologue_pc
= next_pc
;
1144 else if (qp
== 0 && rN
== 12 && rM
== 12)
1146 /* adds r12, -mem_stack_frame_size, r12 */
1147 mem_stack_frame_size
-= imm
;
1148 last_prologue_pc
= next_pc
;
1150 else if (qp
== 0 && rN
== 2
1151 && ((rM
== fp_reg
&& fp_reg
!= 0) || rM
== 12))
1153 char buf
[MAX_REGISTER_SIZE
];
1154 CORE_ADDR saved_sp
= 0;
1155 /* adds r2, spilloffset, rFramePointer
1157 adds r2, spilloffset, r12
1159 Get ready for stf.spill or st8.spill instructions.
1160 The address to start spilling at is loaded into r2.
1161 FIXME: Why r2? That's what gcc currently uses; it
1162 could well be different for other compilers. */
1164 /* Hmm... whether or not this will work will depend on
1165 where the pc is. If it's still early in the prologue
1166 this'll be wrong. FIXME */
1169 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1170 saved_sp
= extract_unsigned_integer (buf
, 8);
1172 spill_addr
= saved_sp
1173 + (rM
== 12 ? 0 : mem_stack_frame_size
)
1176 last_prologue_pc
= next_pc
;
1178 else if (qp
== 0 && rM
>= 32 && rM
< 40 && !instores
[rM
] &&
1179 rN
< 256 && imm
== 0)
1181 /* mov rN, rM where rM is an input register */
1182 reg_contents
[rN
] = rM
;
1183 last_prologue_pc
= next_pc
;
1185 else if (frameless
&& qp
== 0 && rN
== fp_reg
&& imm
== 0 &&
1189 last_prologue_pc
= next_pc
;
1194 && ( ((instr
& 0x1efc0000000LL
) == 0x0eec0000000LL
)
1195 || ((instr
& 0x1ffc8000000LL
) == 0x0cec0000000LL
) ))
1197 /* stf.spill [rN] = fM, imm9
1199 stf.spill [rN] = fM */
1201 int imm
= imm9(instr
);
1202 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1203 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1204 int qp
= (int) (instr
& 0x0000000003fLL
);
1205 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1206 && ((2 <= fM
&& fM
<= 5) || (16 <= fM
&& fM
<= 31)))
1208 cache
->saved_regs
[IA64_FR0_REGNUM
+ fM
] = spill_addr
;
1210 if ((instr
& 0x1efc0000000LL
) == 0x0eec0000000LL
)
1213 spill_addr
= 0; /* last one; must be done */
1214 last_prologue_pc
= next_pc
;
1217 else if ((it
== M
&& ((instr
& 0x1eff8000000LL
) == 0x02110000000LL
))
1218 || (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00050000000LL
)) )
1224 int arM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1225 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1226 int qp
= (int) (instr
& 0x0000000003fLL
);
1227 if (qp
== 0 && isScratch (rN
) && arM
== 36 /* ar.unat */)
1229 /* We have something like "mov.m r3 = ar.unat". Remember the
1230 r3 (or whatever) and watch for a store of this register... */
1232 last_prologue_pc
= next_pc
;
1235 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00198000000LL
))
1238 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1239 int qp
= (int) (instr
& 0x0000000003fLL
);
1240 if (qp
== 0 && isScratch (rN
))
1243 last_prologue_pc
= next_pc
;
1247 && ( ((instr
& 0x1ffc8000000LL
) == 0x08cc0000000LL
)
1248 || ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)))
1252 st8 [rN] = rM, imm9 */
1253 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1254 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1255 int qp
= (int) (instr
& 0x0000000003fLL
);
1256 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1257 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1258 && (rM
== unat_save_reg
|| rM
== pr_save_reg
))
1260 /* We've found a spill of either the UNAT register or the PR
1261 register. (Well, not exactly; what we've actually found is
1262 a spill of the register that UNAT or PR was moved to).
1263 Record that fact and move on... */
1264 if (rM
== unat_save_reg
)
1266 /* Track UNAT register */
1267 cache
->saved_regs
[IA64_UNAT_REGNUM
] = spill_addr
;
1272 /* Track PR register */
1273 cache
->saved_regs
[IA64_PR_REGNUM
] = spill_addr
;
1276 if ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)
1277 /* st8 [rN] = rM, imm9 */
1278 spill_addr
+= imm9(instr
);
1280 spill_addr
= 0; /* must be done spilling */
1281 last_prologue_pc
= next_pc
;
1283 else if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1285 /* Allow up to one store of each input register. */
1286 instores
[rM
-32] = 1;
1287 last_prologue_pc
= next_pc
;
1289 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1290 !instores
[indirect
-32])
1292 /* Allow an indirect store of an input register. */
1293 instores
[indirect
-32] = 1;
1294 last_prologue_pc
= next_pc
;
1297 else if (it
== M
&& ((instr
& 0x1ff08000000LL
) == 0x08c00000000LL
))
1304 Note that the st8 case is handled in the clause above.
1306 Advance over stores of input registers. One store per input
1307 register is permitted. */
1308 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1309 int qp
= (int) (instr
& 0x0000000003fLL
);
1310 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1311 if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1313 instores
[rM
-32] = 1;
1314 last_prologue_pc
= next_pc
;
1316 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1317 !instores
[indirect
-32])
1319 /* Allow an indirect store of an input register. */
1320 instores
[indirect
-32] = 1;
1321 last_prologue_pc
= next_pc
;
1324 else if (it
== M
&& ((instr
& 0x1ff88000000LL
) == 0x0cc80000000LL
))
1331 Advance over stores of floating point input registers. Again
1332 one store per register is permitted */
1333 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1334 int qp
= (int) (instr
& 0x0000000003fLL
);
1335 if (qp
== 0 && 8 <= fM
&& fM
< 16 && !infpstores
[fM
- 8])
1337 infpstores
[fM
-8] = 1;
1338 last_prologue_pc
= next_pc
;
1342 && ( ((instr
& 0x1ffc8000000LL
) == 0x08ec0000000LL
)
1343 || ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)))
1345 /* st8.spill [rN] = rM
1347 st8.spill [rN] = rM, imm9 */
1348 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1349 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1350 int qp
= (int) (instr
& 0x0000000003fLL
);
1351 if (qp
== 0 && rN
== spill_reg
&& 4 <= rM
&& rM
<= 7)
1353 /* We've found a spill of one of the preserved general purpose
1354 regs. Record the spill address and advance the spill
1355 register if appropriate. */
1356 cache
->saved_regs
[IA64_GR0_REGNUM
+ rM
] = spill_addr
;
1357 if ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)
1358 /* st8.spill [rN] = rM, imm9 */
1359 spill_addr
+= imm9(instr
);
1361 spill_addr
= 0; /* Done spilling */
1362 last_prologue_pc
= next_pc
;
1369 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1370 registers for the previous frame which will be needed later. */
1372 if (!frameless
&& next_frame
)
1374 /* Extract the size of the rotating portion of the stack
1375 frame and the register rename base from the current
1381 rrb_gr
= (cfm
>> 18) & 0x7f;
1383 /* Find the bof (beginning of frame). */
1384 bof
= rse_address_add (cache
->bsp
, -sof
);
1386 for (i
= 0, addr
= bof
;
1390 if (IS_NaT_COLLECTION_ADDR (addr
))
1394 if (i
+32 == cfm_reg
)
1395 cache
->saved_regs
[IA64_CFM_REGNUM
] = addr
;
1396 if (i
+32 == ret_reg
)
1397 cache
->saved_regs
[IA64_VRAP_REGNUM
] = addr
;
1399 cache
->saved_regs
[IA64_VFP_REGNUM
] = addr
;
1402 /* For the previous argument registers we require the previous bof.
1403 If we can't find the previous cfm, then we can do nothing. */
1405 if (cache
->saved_regs
[IA64_CFM_REGNUM
] != 0)
1407 cfm
= read_memory_integer (cache
->saved_regs
[IA64_CFM_REGNUM
], 8);
1409 else if (cfm_reg
!= 0)
1411 frame_unwind_register (next_frame
, cfm_reg
, buf
);
1412 cfm
= extract_unsigned_integer (buf
, 8);
1414 cache
->prev_cfm
= cfm
;
1418 sor
= ((cfm
>> 14) & 0xf) * 8;
1420 sol
= (cfm
>> 7) & 0x7f;
1421 rrb_gr
= (cfm
>> 18) & 0x7f;
1423 /* The previous bof only requires subtraction of the sol (size of locals)
1424 due to the overlap between output and input of subsequent frames. */
1425 bof
= rse_address_add (bof
, -sol
);
1427 for (i
= 0, addr
= bof
;
1431 if (IS_NaT_COLLECTION_ADDR (addr
))
1436 cache
->saved_regs
[IA64_GR32_REGNUM
+ ((i
+ (sor
- rrb_gr
)) % sor
)]
1439 cache
->saved_regs
[IA64_GR32_REGNUM
+ i
] = addr
;
1445 /* Try and trust the lim_pc value whenever possible. */
1446 if (trust_limit
&& lim_pc
>= last_prologue_pc
)
1447 last_prologue_pc
= lim_pc
;
1449 cache
->frameless
= frameless
;
1450 cache
->after_prologue
= last_prologue_pc
;
1451 cache
->mem_stack_frame_size
= mem_stack_frame_size
;
1452 cache
->fp_reg
= fp_reg
;
1454 return last_prologue_pc
;
1458 ia64_skip_prologue (CORE_ADDR pc
)
1460 struct ia64_frame_cache cache
;
1462 cache
.after_prologue
= 0;
1466 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1467 return examine_prologue (pc
, pc
+1024, 0, &cache
);
1471 /* Normal frames. */
1473 static struct ia64_frame_cache
*
1474 ia64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1476 struct ia64_frame_cache
*cache
;
1478 CORE_ADDR cfm
, sof
, sol
, bsp
, psr
;
1484 cache
= ia64_alloc_frame_cache ();
1485 *this_cache
= cache
;
1487 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1488 cache
->saved_sp
= extract_unsigned_integer (buf
, 8);
1490 /* We always want the bsp to point to the end of frame.
1491 This way, we can always get the beginning of frame (bof)
1492 by subtracting frame size. */
1493 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1494 cache
->bsp
= extract_unsigned_integer (buf
, 8);
1496 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1497 psr
= extract_unsigned_integer (buf
, 8);
1499 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
1500 cfm
= extract_unsigned_integer (buf
, 8);
1502 cache
->sof
= (cfm
& 0x7f);
1503 cache
->sol
= (cfm
>> 7) & 0x7f;
1504 cache
->sor
= ((cfm
>> 14) & 0xf) * 8;
1508 cache
->pc
= frame_func_unwind (next_frame
);
1511 examine_prologue (cache
->pc
, frame_pc_unwind (next_frame
), next_frame
, cache
);
1513 cache
->base
= cache
->saved_sp
+ cache
->mem_stack_frame_size
;
1519 ia64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1520 struct frame_id
*this_id
)
1522 struct ia64_frame_cache
*cache
=
1523 ia64_frame_cache (next_frame
, this_cache
);
1525 /* This marks the outermost frame. */
1526 if (cache
->base
== 0)
1529 (*this_id
) = frame_id_build_special (cache
->base
, cache
->pc
, cache
->bsp
);
1530 if (gdbarch_debug
>= 1)
1531 fprintf_unfiltered (gdb_stdlog
,
1532 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1533 paddr_nz (this_id
->code_addr
),
1534 paddr_nz (this_id
->stack_addr
),
1535 paddr_nz (cache
->bsp
), next_frame
);
1539 ia64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1540 int regnum
, int *optimizedp
,
1541 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1542 int *realnump
, void *valuep
)
1544 struct ia64_frame_cache
*cache
=
1545 ia64_frame_cache (next_frame
, this_cache
);
1546 char dummy_valp
[MAX_REGISTER_SIZE
];
1549 gdb_assert (regnum
>= 0);
1551 if (!target_has_registers
)
1552 error (_("No registers."));
1559 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1560 when valuep is not supplied. */
1562 valuep
= dummy_valp
;
1564 memset (valuep
, 0, register_size (current_gdbarch
, regnum
));
1566 if (regnum
== SP_REGNUM
)
1568 /* Handle SP values for all frames but the topmost. */
1569 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
),
1572 else if (regnum
== IA64_BSP_REGNUM
)
1574 char cfm_valuep
[MAX_REGISTER_SIZE
];
1577 enum lval_type cfm_lval
;
1579 CORE_ADDR bsp
, prev_cfm
, prev_bsp
;
1581 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1582 This corresponds to what the hardware bsp register will be if we pop the frame
1583 back which is why we might have been called. We know the beginning of the current
1584 frame is cache->bsp - cache->sof. This value in the previous frame points to
1585 the start of the output registers. We can calculate the end of that frame by adding
1586 the size of output (sof (size of frame) - sol (size of locals)). */
1587 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1588 &cfm_optim
, &cfm_lval
, &cfm_addr
, &cfm_realnum
, cfm_valuep
);
1589 prev_cfm
= extract_unsigned_integer (cfm_valuep
, 8);
1591 bsp
= rse_address_add (cache
->bsp
, -(cache
->sof
));
1592 prev_bsp
= rse_address_add (bsp
, (prev_cfm
& 0x7f) - ((prev_cfm
>> 7) & 0x7f));
1594 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
),
1597 else if (regnum
== IA64_CFM_REGNUM
)
1599 CORE_ADDR addr
= cache
->saved_regs
[IA64_CFM_REGNUM
];
1603 *lvalp
= lval_memory
;
1605 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
1607 else if (cache
->prev_cfm
)
1608 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
), cache
->prev_cfm
);
1609 else if (cache
->frameless
)
1612 frame_unwind_register (next_frame
, IA64_PFS_REGNUM
, valuep
);
1615 else if (regnum
== IA64_VFP_REGNUM
)
1617 /* If the function in question uses an automatic register (r32-r127)
1618 for the frame pointer, it'll be found by ia64_find_saved_register()
1619 above. If the function lacks one of these frame pointers, we can
1620 still provide a value since we know the size of the frame. */
1621 CORE_ADDR vfp
= cache
->base
;
1622 store_unsigned_integer (valuep
, register_size (current_gdbarch
, IA64_VFP_REGNUM
), vfp
);
1624 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1626 char pr_valuep
[MAX_REGISTER_SIZE
];
1629 enum lval_type pr_lval
;
1632 ia64_frame_prev_register (next_frame
, this_cache
, IA64_PR_REGNUM
,
1633 &pr_optim
, &pr_lval
, &pr_addr
, &pr_realnum
, pr_valuep
);
1634 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1636 /* Fetch predicate register rename base from current frame
1637 marker for this frame. */
1638 int rrb_pr
= (cache
->cfm
>> 32) & 0x3f;
1640 /* Adjust the register number to account for register rotation. */
1641 regnum
= VP16_REGNUM
1642 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
1644 prN_val
= extract_bit_field ((unsigned char *) pr_valuep
,
1645 regnum
- VP0_REGNUM
, 1);
1646 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
), prN_val
);
1648 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
1650 char unat_valuep
[MAX_REGISTER_SIZE
];
1653 enum lval_type unat_lval
;
1654 CORE_ADDR unat_addr
;
1656 ia64_frame_prev_register (next_frame
, this_cache
, IA64_UNAT_REGNUM
,
1657 &unat_optim
, &unat_lval
, &unat_addr
, &unat_realnum
, unat_valuep
);
1658 unatN_val
= extract_bit_field ((unsigned char *) unat_valuep
,
1659 regnum
- IA64_NAT0_REGNUM
, 1);
1660 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
),
1663 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
1666 /* Find address of general register corresponding to nat bit we're
1670 gr_addr
= cache
->saved_regs
[regnum
- IA64_NAT0_REGNUM
1674 /* Compute address of nat collection bits. */
1675 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
1677 CORE_ADDR nat_collection
;
1679 /* If our nat collection address is bigger than bsp, we have to get
1680 the nat collection from rnat. Otherwise, we fetch the nat
1681 collection from the computed address. */
1682 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1683 bsp
= extract_unsigned_integer (buf
, 8);
1684 if (nat_addr
>= bsp
)
1686 frame_unwind_register (next_frame
, IA64_RNAT_REGNUM
, buf
);
1687 nat_collection
= extract_unsigned_integer (buf
, 8);
1690 nat_collection
= read_memory_integer (nat_addr
, 8);
1691 nat_bit
= (gr_addr
>> 3) & 0x3f;
1692 natval
= (nat_collection
>> nat_bit
) & 1;
1695 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
), natval
);
1697 else if (regnum
== IA64_IP_REGNUM
)
1700 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1704 *lvalp
= lval_memory
;
1706 read_memory (addr
, buf
, register_size (current_gdbarch
, IA64_IP_REGNUM
));
1707 pc
= extract_unsigned_integer (buf
, 8);
1709 else if (cache
->frameless
)
1711 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1712 pc
= extract_unsigned_integer (buf
, 8);
1715 store_unsigned_integer (valuep
, 8, pc
);
1717 else if (regnum
== IA64_PSR_REGNUM
)
1719 /* We don't know how to get the complete previous PSR, but we need it for
1720 the slot information when we unwind the pc (pc is formed of IP register
1721 plus slot information from PSR). To get the previous slot information,
1722 we mask it off the return address. */
1723 ULONGEST slot_num
= 0;
1726 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1728 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1729 psr
= extract_unsigned_integer (buf
, 8);
1733 *lvalp
= lval_memory
;
1735 read_memory (addr
, buf
, register_size (current_gdbarch
, IA64_IP_REGNUM
));
1736 pc
= extract_unsigned_integer (buf
, 8);
1738 else if (cache
->frameless
)
1741 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1742 pc
= extract_unsigned_integer (buf
, 8);
1744 psr
&= ~(3LL << 41);
1745 slot_num
= pc
& 0x3LL
;
1746 psr
|= (CORE_ADDR
)slot_num
<< 41;
1747 store_unsigned_integer (valuep
, 8, psr
);
1749 else if (regnum
== IA64_BR0_REGNUM
)
1752 CORE_ADDR addr
= cache
->saved_regs
[IA64_BR0_REGNUM
];
1755 *lvalp
= lval_memory
;
1757 read_memory (addr
, buf
, register_size (current_gdbarch
, IA64_BR0_REGNUM
));
1758 br0
= extract_unsigned_integer (buf
, 8);
1760 store_unsigned_integer (valuep
, 8, br0
);
1762 else if ((regnum
>= IA64_GR32_REGNUM
&& regnum
<= IA64_GR127_REGNUM
) ||
1763 (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
))
1766 if (regnum
>= V32_REGNUM
)
1767 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1768 addr
= cache
->saved_regs
[regnum
];
1771 *lvalp
= lval_memory
;
1773 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
1775 else if (cache
->frameless
)
1777 char r_valuep
[MAX_REGISTER_SIZE
];
1780 enum lval_type r_lval
;
1782 CORE_ADDR prev_cfm
, prev_bsp
, prev_bof
;
1784 if (regnum
>= V32_REGNUM
)
1785 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1786 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1787 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1788 prev_cfm
= extract_unsigned_integer (r_valuep
, 8);
1789 ia64_frame_prev_register (next_frame
, this_cache
, IA64_BSP_REGNUM
,
1790 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1791 prev_bsp
= extract_unsigned_integer (r_valuep
, 8);
1792 prev_bof
= rse_address_add (prev_bsp
, -(prev_cfm
& 0x7f));
1794 addr
= rse_address_add (prev_bof
, (regnum
- IA64_GR32_REGNUM
));
1795 *lvalp
= lval_memory
;
1797 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
1803 if (IA64_FR32_REGNUM
<= regnum
&& regnum
<= IA64_FR127_REGNUM
)
1805 /* Fetch floating point register rename base from current
1806 frame marker for this frame. */
1807 int rrb_fr
= (cache
->cfm
>> 25) & 0x7f;
1809 /* Adjust the floating point register number to account for
1810 register rotation. */
1811 regnum
= IA64_FR32_REGNUM
1812 + ((regnum
- IA64_FR32_REGNUM
) + rrb_fr
) % 96;
1815 /* If we have stored a memory address, access the register. */
1816 addr
= cache
->saved_regs
[regnum
];
1819 *lvalp
= lval_memory
;
1821 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
1823 /* Otherwise, punt and get the current value of the register. */
1825 frame_unwind_register (next_frame
, regnum
, valuep
);
1828 if (gdbarch_debug
>= 1)
1829 fprintf_unfiltered (gdb_stdlog
,
1830 "regular prev register <%d> <%s> is 0x%s\n", regnum
,
1831 (((unsigned) regnum
<= IA64_NAT127_REGNUM
)
1832 ? ia64_register_names
[regnum
] : "r??"),
1833 paddr_nz (extract_unsigned_integer (valuep
, 8)));
1836 static const struct frame_unwind ia64_frame_unwind
=
1839 &ia64_frame_this_id
,
1840 &ia64_frame_prev_register
1843 static const struct frame_unwind
*
1844 ia64_frame_sniffer (struct frame_info
*next_frame
)
1846 return &ia64_frame_unwind
;
1849 /* Signal trampolines. */
1852 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache
*cache
)
1854 if (SIGCONTEXT_REGISTER_ADDRESS
)
1858 cache
->saved_regs
[IA64_VRAP_REGNUM
] =
1859 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_IP_REGNUM
);
1860 cache
->saved_regs
[IA64_CFM_REGNUM
] =
1861 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CFM_REGNUM
);
1862 cache
->saved_regs
[IA64_PSR_REGNUM
] =
1863 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PSR_REGNUM
);
1864 cache
->saved_regs
[IA64_BSP_REGNUM
] =
1865 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_BSP_REGNUM
);
1866 cache
->saved_regs
[IA64_RNAT_REGNUM
] =
1867 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_RNAT_REGNUM
);
1868 cache
->saved_regs
[IA64_CCV_REGNUM
] =
1869 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CCV_REGNUM
);
1870 cache
->saved_regs
[IA64_UNAT_REGNUM
] =
1871 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_UNAT_REGNUM
);
1872 cache
->saved_regs
[IA64_FPSR_REGNUM
] =
1873 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_FPSR_REGNUM
);
1874 cache
->saved_regs
[IA64_PFS_REGNUM
] =
1875 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PFS_REGNUM
);
1876 cache
->saved_regs
[IA64_LC_REGNUM
] =
1877 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_LC_REGNUM
);
1878 for (regno
= IA64_GR1_REGNUM
; regno
<= IA64_GR31_REGNUM
; regno
++)
1879 cache
->saved_regs
[regno
] =
1880 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1881 for (regno
= IA64_BR0_REGNUM
; regno
<= IA64_BR7_REGNUM
; regno
++)
1882 cache
->saved_regs
[regno
] =
1883 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1884 for (regno
= IA64_FR2_REGNUM
; regno
<= IA64_FR31_REGNUM
; regno
++)
1885 cache
->saved_regs
[regno
] =
1886 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1890 static struct ia64_frame_cache
*
1891 ia64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1893 struct ia64_frame_cache
*cache
;
1901 cache
= ia64_alloc_frame_cache ();
1903 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1904 /* Note that frame size is hard-coded below. We cannot calculate it
1905 via prologue examination. */
1906 cache
->base
= extract_unsigned_integer (buf
, 8) + 16;
1908 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1909 cache
->bsp
= extract_unsigned_integer (buf
, 8);
1911 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
1912 cache
->cfm
= extract_unsigned_integer (buf
, 8);
1913 cache
->sof
= cache
->cfm
& 0x7f;
1915 ia64_sigtramp_frame_init_saved_regs (cache
);
1917 *this_cache
= cache
;
1922 ia64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
1923 void **this_cache
, struct frame_id
*this_id
)
1925 struct ia64_frame_cache
*cache
=
1926 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1928 (*this_id
) = frame_id_build_special (cache
->base
, frame_pc_unwind (next_frame
), cache
->bsp
);
1929 if (gdbarch_debug
>= 1)
1930 fprintf_unfiltered (gdb_stdlog
,
1931 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1932 paddr_nz (this_id
->code_addr
),
1933 paddr_nz (this_id
->stack_addr
),
1934 paddr_nz (cache
->bsp
), next_frame
);
1938 ia64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
1940 int regnum
, int *optimizedp
,
1941 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1942 int *realnump
, void *valuep
)
1944 char dummy_valp
[MAX_REGISTER_SIZE
];
1945 char buf
[MAX_REGISTER_SIZE
];
1947 struct ia64_frame_cache
*cache
=
1948 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1950 gdb_assert (regnum
>= 0);
1952 if (!target_has_registers
)
1953 error (_("No registers."));
1960 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1961 when valuep is not supplied. */
1963 valuep
= dummy_valp
;
1965 memset (valuep
, 0, register_size (current_gdbarch
, regnum
));
1967 if (regnum
== IA64_IP_REGNUM
)
1970 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1974 *lvalp
= lval_memory
;
1976 read_memory (addr
, buf
, register_size (current_gdbarch
, IA64_IP_REGNUM
));
1977 pc
= extract_unsigned_integer (buf
, 8);
1980 store_unsigned_integer (valuep
, 8, pc
);
1982 else if ((regnum
>= IA64_GR32_REGNUM
&& regnum
<= IA64_GR127_REGNUM
) ||
1983 (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
))
1986 if (regnum
>= V32_REGNUM
)
1987 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1988 addr
= cache
->saved_regs
[regnum
];
1991 *lvalp
= lval_memory
;
1993 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
1998 /* All other registers not listed above. */
1999 CORE_ADDR addr
= cache
->saved_regs
[regnum
];
2002 *lvalp
= lval_memory
;
2004 read_memory (addr
, valuep
, register_size (current_gdbarch
, regnum
));
2008 if (gdbarch_debug
>= 1)
2009 fprintf_unfiltered (gdb_stdlog
,
2010 "sigtramp prev register <%s> is 0x%s\n",
2011 (((unsigned) regnum
<= IA64_NAT127_REGNUM
)
2012 ? ia64_register_names
[regnum
] : "r??"),
2013 paddr_nz (extract_unsigned_integer (valuep
, 8)));
2016 static const struct frame_unwind ia64_sigtramp_frame_unwind
=
2019 ia64_sigtramp_frame_this_id
,
2020 ia64_sigtramp_frame_prev_register
2023 static const struct frame_unwind
*
2024 ia64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
2027 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2029 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2030 if (legacy_pc_in_sigtramp (pc
, name
))
2031 return &ia64_sigtramp_frame_unwind
;
2038 ia64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
2040 struct ia64_frame_cache
*cache
=
2041 ia64_frame_cache (next_frame
, this_cache
);
2046 static const struct frame_base ia64_frame_base
=
2049 ia64_frame_base_address
,
2050 ia64_frame_base_address
,
2051 ia64_frame_base_address
2054 #ifdef HAVE_LIBUNWIND_IA64_H
2056 struct ia64_unwind_table_entry
2058 unw_word_t start_offset
;
2059 unw_word_t end_offset
;
2060 unw_word_t info_offset
;
2063 static __inline__
uint64_t
2064 ia64_rse_slot_num (uint64_t addr
)
2066 return (addr
>> 3) & 0x3f;
2069 /* Skip over a designated number of registers in the backing
2070 store, remembering every 64th position is for NAT. */
2071 static __inline__
uint64_t
2072 ia64_rse_skip_regs (uint64_t addr
, long num_regs
)
2074 long delta
= ia64_rse_slot_num(addr
) + num_regs
;
2078 return addr
+ ((num_regs
+ delta
/0x3f) << 3);
2081 /* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2082 number to a libunwind register number. */
2084 ia64_gdb2uw_regnum (int regnum
)
2086 if (regnum
== sp_regnum
)
2088 else if (regnum
== IA64_BSP_REGNUM
)
2089 return UNW_IA64_BSP
;
2090 else if ((unsigned) (regnum
- IA64_GR0_REGNUM
) < 128)
2091 return UNW_IA64_GR
+ (regnum
- IA64_GR0_REGNUM
);
2092 else if ((unsigned) (regnum
- V32_REGNUM
) < 95)
2093 return UNW_IA64_GR
+ 32 + (regnum
- V32_REGNUM
);
2094 else if ((unsigned) (regnum
- IA64_FR0_REGNUM
) < 128)
2095 return UNW_IA64_FR
+ (regnum
- IA64_FR0_REGNUM
);
2096 else if ((unsigned) (regnum
- IA64_PR0_REGNUM
) < 64)
2098 else if ((unsigned) (regnum
- IA64_BR0_REGNUM
) < 8)
2099 return UNW_IA64_BR
+ (regnum
- IA64_BR0_REGNUM
);
2100 else if (regnum
== IA64_PR_REGNUM
)
2102 else if (regnum
== IA64_IP_REGNUM
)
2104 else if (regnum
== IA64_CFM_REGNUM
)
2105 return UNW_IA64_CFM
;
2106 else if ((unsigned) (regnum
- IA64_AR0_REGNUM
) < 128)
2107 return UNW_IA64_AR
+ (regnum
- IA64_AR0_REGNUM
);
2108 else if ((unsigned) (regnum
- IA64_NAT0_REGNUM
) < 128)
2109 return UNW_IA64_NAT
+ (regnum
- IA64_NAT0_REGNUM
);
2114 /* Gdb libunwind-frame callback function to convert from a libunwind register
2115 number to a ia64 gdb register number. */
2117 ia64_uw2gdb_regnum (int uw_regnum
)
2119 if (uw_regnum
== UNW_IA64_SP
)
2121 else if (uw_regnum
== UNW_IA64_BSP
)
2122 return IA64_BSP_REGNUM
;
2123 else if ((unsigned) (uw_regnum
- UNW_IA64_GR
) < 32)
2124 return IA64_GR0_REGNUM
+ (uw_regnum
- UNW_IA64_GR
);
2125 else if ((unsigned) (uw_regnum
- UNW_IA64_GR
) < 128)
2126 return V32_REGNUM
+ (uw_regnum
- (IA64_GR0_REGNUM
+ 32));
2127 else if ((unsigned) (uw_regnum
- UNW_IA64_FR
) < 128)
2128 return IA64_FR0_REGNUM
+ (uw_regnum
- UNW_IA64_FR
);
2129 else if ((unsigned) (uw_regnum
- UNW_IA64_BR
) < 8)
2130 return IA64_BR0_REGNUM
+ (uw_regnum
- UNW_IA64_BR
);
2131 else if (uw_regnum
== UNW_IA64_PR
)
2132 return IA64_PR_REGNUM
;
2133 else if (uw_regnum
== UNW_REG_IP
)
2134 return IA64_IP_REGNUM
;
2135 else if (uw_regnum
== UNW_IA64_CFM
)
2136 return IA64_CFM_REGNUM
;
2137 else if ((unsigned) (uw_regnum
- UNW_IA64_AR
) < 128)
2138 return IA64_AR0_REGNUM
+ (uw_regnum
- UNW_IA64_AR
);
2139 else if ((unsigned) (uw_regnum
- UNW_IA64_NAT
) < 128)
2140 return IA64_NAT0_REGNUM
+ (uw_regnum
- UNW_IA64_NAT
);
2145 /* Gdb libunwind-frame callback function to reveal if register is a float
2148 ia64_is_fpreg (int uw_regnum
)
2150 return unw_is_fpreg (uw_regnum
);
2153 /* Libunwind callback accessor function for general registers. */
2155 ia64_access_reg (unw_addr_space_t as
, unw_regnum_t uw_regnum
, unw_word_t
*val
,
2156 int write
, void *arg
)
2158 int regnum
= ia64_uw2gdb_regnum (uw_regnum
);
2159 unw_word_t bsp
, sof
, sol
, cfm
, psr
, ip
;
2160 struct frame_info
*next_frame
= arg
;
2161 long new_sof
, old_sof
;
2162 char buf
[MAX_REGISTER_SIZE
];
2167 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2173 ia64_write_pc (*val
, inferior_ptid
);
2176 case UNW_IA64_AR_BSPSTORE
:
2177 write_register (IA64_BSP_REGNUM
, *val
);
2180 case UNW_IA64_AR_BSP
:
2182 /* Account for the fact that ptrace() expects bsp to point
2183 after the current register frame. */
2184 cfm
= read_register (IA64_CFM_REGNUM
);
2186 bsp
= ia64_rse_skip_regs (*val
, sof
);
2187 write_register (IA64_BSP_REGNUM
, bsp
);
2191 /* If we change CFM, we need to adjust ptrace's notion of
2192 bsp accordingly, so that the real bsp remains
2194 bsp
= read_register (IA64_BSP_REGNUM
);
2195 cfm
= read_register (IA64_CFM_REGNUM
);
2196 old_sof
= (cfm
& 0x7f);
2197 new_sof
= (*val
& 0x7f);
2198 if (old_sof
!= new_sof
)
2200 bsp
= ia64_rse_skip_regs (bsp
, -old_sof
+ new_sof
);
2201 write_register (IA64_BSP_REGNUM
, bsp
);
2203 write_register (IA64_CFM_REGNUM
, *val
);
2207 write_register (regnum
, *val
);
2210 if (gdbarch_debug
>= 1)
2211 fprintf_unfiltered (gdb_stdlog
,
2212 " access_reg: to cache: %4s=0x%s\n",
2213 (((unsigned) regnum
<= IA64_NAT127_REGNUM
)
2214 ? ia64_register_names
[regnum
] : "r??"),
2222 /* Libunwind expects to see the pc value which means the slot number
2223 from the psr must be merged with the ip word address. */
2224 frame_unwind_register (next_frame
, IA64_IP_REGNUM
, buf
);
2225 ip
= extract_unsigned_integer (buf
, 8);
2226 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
2227 psr
= extract_unsigned_integer (buf
, 8);
2228 *val
= ip
| ((psr
>> 41) & 0x3);
2231 case UNW_IA64_AR_BSP
:
2232 /* Libunwind expects to see the beginning of the current register
2233 frame so we must account for the fact that ptrace() will return a value
2234 for bsp that points *after* the current register frame. */
2235 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
2236 bsp
= extract_unsigned_integer (buf
, 8);
2237 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
2238 cfm
= extract_unsigned_integer (buf
, 8);
2240 *val
= ia64_rse_skip_regs (bsp
, -sof
);
2243 case UNW_IA64_AR_BSPSTORE
:
2244 /* Libunwind wants bspstore to be after the current register frame.
2245 This is what ptrace() and gdb treats as the regular bsp value. */
2246 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
2247 *val
= extract_unsigned_integer (buf
, 8);
2251 /* For all other registers, just unwind the value directly. */
2252 frame_unwind_register (next_frame
, regnum
, buf
);
2253 *val
= extract_unsigned_integer (buf
, 8);
2257 if (gdbarch_debug
>= 1)
2258 fprintf_unfiltered (gdb_stdlog
,
2259 " access_reg: from cache: %4s=0x%s\n",
2260 (((unsigned) regnum
<= IA64_NAT127_REGNUM
)
2261 ? ia64_register_names
[regnum
] : "r??"),
2267 /* Libunwind callback accessor function for floating-point registers. */
2269 ia64_access_fpreg (unw_addr_space_t as
, unw_regnum_t uw_regnum
, unw_fpreg_t
*val
,
2270 int write
, void *arg
)
2272 int regnum
= ia64_uw2gdb_regnum (uw_regnum
);
2275 regcache_cooked_write (current_regcache
, regnum
, (char *) val
);
2277 regcache_cooked_read (current_regcache
, regnum
, (char *) val
);
2281 /* Libunwind callback accessor function for accessing memory. */
2283 ia64_access_mem (unw_addr_space_t as
,
2284 unw_word_t addr
, unw_word_t
*val
,
2285 int write
, void *arg
)
2287 /* XXX do we need to normalize byte-order here? */
2289 return target_write_memory (addr
, (char *) val
, sizeof (unw_word_t
));
2291 return target_read_memory (addr
, (char *) val
, sizeof (unw_word_t
));
2294 /* Call low-level function to access the kernel unwind table. */
2296 getunwind_table (void *buf
, size_t len
)
2299 x
= target_read_partial (¤t_target
, TARGET_OBJECT_UNWIND_TABLE
, NULL
,
2305 /* Get the kernel unwind table. */
2307 get_kernel_table (unw_word_t ip
, unw_dyn_info_t
*di
)
2310 struct ia64_table_entry
2312 uint64_t start_offset
;
2313 uint64_t end_offset
;
2314 uint64_t info_offset
;
2316 static struct ia64_table_entry
*ktab
= NULL
, *etab
;
2320 size
= getunwind_table (NULL
, 0);
2322 return -UNW_ENOINFO
;
2323 ktab
= xmalloc (size
);
2324 getunwind_table (ktab
, size
);
2326 /* Determine length of kernel's unwind table and relocate
2328 for (etab
= ktab
; etab
->start_offset
; ++etab
)
2329 etab
->info_offset
+= (uint64_t) ktab
;
2332 if (ip
< ktab
[0].start_offset
|| ip
>= etab
[-1].end_offset
)
2333 return -UNW_ENOINFO
;
2335 di
->format
= UNW_INFO_FORMAT_TABLE
;
2337 di
->start_ip
= ktab
[0].start_offset
;
2338 di
->end_ip
= etab
[-1].end_offset
;
2339 di
->u
.ti
.name_ptr
= (unw_word_t
) "<kernel>";
2340 di
->u
.ti
.segbase
= 0;
2341 di
->u
.ti
.table_len
= ((char *) etab
- (char *) ktab
) / sizeof (unw_word_t
);
2342 di
->u
.ti
.table_data
= (unw_word_t
*) ktab
;
2344 if (gdbarch_debug
>= 1)
2345 fprintf_unfiltered (gdb_stdlog
, "get_kernel_table: found table `%s': "
2346 "segbase=0x%s, length=%s, gp=0x%s\n",
2347 (char *) di
->u
.ti
.name_ptr
,
2348 paddr_nz (di
->u
.ti
.segbase
),
2349 paddr_u (di
->u
.ti
.table_len
),
2354 /* Find the unwind table entry for a specified address. */
2356 ia64_find_unwind_table (struct objfile
*objfile
, unw_word_t ip
,
2357 unw_dyn_info_t
*dip
, void **buf
)
2359 Elf_Internal_Phdr
*phdr
, *p_text
= NULL
, *p_unwind
= NULL
;
2360 Elf_Internal_Ehdr
*ehdr
;
2361 unw_word_t segbase
= 0;
2362 CORE_ADDR load_base
;
2366 bfd
= objfile
->obfd
;
2368 ehdr
= elf_tdata (bfd
)->elf_header
;
2369 phdr
= elf_tdata (bfd
)->phdr
;
2371 load_base
= ANOFFSET (objfile
->section_offsets
, SECT_OFF_TEXT (objfile
));
2373 for (i
= 0; i
< ehdr
->e_phnum
; ++i
)
2375 switch (phdr
[i
].p_type
)
2378 if ((unw_word_t
) (ip
- load_base
- phdr
[i
].p_vaddr
)
2383 case PT_IA_64_UNWIND
:
2384 p_unwind
= phdr
+ i
;
2392 if (!p_text
|| !p_unwind
2393 /* Verify that the segment that contains the IP also contains
2394 the static unwind table. If not, we are dealing with
2395 runtime-generated code, for which we have no info here. */
2396 || (p_unwind
->p_vaddr
- p_text
->p_vaddr
) >= p_text
->p_memsz
)
2397 return -UNW_ENOINFO
;
2399 segbase
= p_text
->p_vaddr
+ load_base
;
2401 dip
->start_ip
= segbase
;
2402 dip
->end_ip
= dip
->start_ip
+ p_text
->p_memsz
;
2403 dip
->gp
= ia64_find_global_pointer (ip
);
2404 dip
->format
= UNW_INFO_FORMAT_REMOTE_TABLE
;
2405 dip
->u
.rti
.name_ptr
= (unw_word_t
) bfd_get_filename (bfd
);
2406 dip
->u
.rti
.segbase
= segbase
;
2407 dip
->u
.rti
.table_len
= p_unwind
->p_memsz
/ sizeof (unw_word_t
);
2408 dip
->u
.rti
.table_data
= p_unwind
->p_vaddr
+ load_base
;
2413 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2415 ia64_find_proc_info_x (unw_addr_space_t as
, unw_word_t ip
, unw_proc_info_t
*pi
,
2416 int need_unwind_info
, void *arg
)
2418 struct obj_section
*sec
= find_pc_section (ip
);
2425 /* XXX This only works if the host and the target architecture are
2426 both ia64 and if the have (more or less) the same kernel
2428 if (get_kernel_table (ip
, &di
) < 0)
2429 return -UNW_ENOINFO
;
2431 if (gdbarch_debug
>= 1)
2432 fprintf_unfiltered (gdb_stdlog
, "ia64_find_proc_info_x: 0x%s -> "
2433 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2434 "length=%s,data=0x%s)\n",
2435 paddr_nz (ip
), (char *)di
.u
.ti
.name_ptr
,
2436 paddr_nz (di
.u
.ti
.segbase
),
2437 paddr_nz (di
.start_ip
), paddr_nz (di
.end_ip
),
2439 paddr_u (di
.u
.ti
.table_len
),
2440 paddr_nz ((CORE_ADDR
)di
.u
.ti
.table_data
));
2444 ret
= ia64_find_unwind_table (sec
->objfile
, ip
, &di
, &buf
);
2448 if (gdbarch_debug
>= 1)
2449 fprintf_unfiltered (gdb_stdlog
, "ia64_find_proc_info_x: 0x%s -> "
2450 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2451 "length=%s,data=0x%s)\n",
2452 paddr_nz (ip
), (char *)di
.u
.rti
.name_ptr
,
2453 paddr_nz (di
.u
.rti
.segbase
),
2454 paddr_nz (di
.start_ip
), paddr_nz (di
.end_ip
),
2456 paddr_u (di
.u
.rti
.table_len
),
2457 paddr_nz (di
.u
.rti
.table_data
));
2460 ret
= libunwind_search_unwind_table (&as
, ip
, &di
, pi
, need_unwind_info
,
2463 /* We no longer need the dyn info storage so free it. */
2469 /* Libunwind callback accessor function for cleanup. */
2471 ia64_put_unwind_info (unw_addr_space_t as
,
2472 unw_proc_info_t
*pip
, void *arg
)
2474 /* Nothing required for now. */
2477 /* Libunwind callback accessor function to get head of the dynamic
2478 unwind-info registration list. */
2480 ia64_get_dyn_info_list (unw_addr_space_t as
,
2481 unw_word_t
*dilap
, void *arg
)
2483 struct obj_section
*text_sec
;
2484 struct objfile
*objfile
;
2485 unw_word_t ip
, addr
;
2489 if (!libunwind_is_initialized ())
2490 return -UNW_ENOINFO
;
2492 for (objfile
= object_files
; objfile
; objfile
= objfile
->next
)
2496 text_sec
= objfile
->sections
+ SECT_OFF_TEXT (objfile
);
2497 ip
= text_sec
->addr
;
2498 ret
= ia64_find_unwind_table (objfile
, ip
, &di
, &buf
);
2501 addr
= libunwind_find_dyn_list (as
, &di
, arg
);
2502 /* We no longer need the dyn info storage so free it. */
2507 if (gdbarch_debug
>= 1)
2508 fprintf_unfiltered (gdb_stdlog
,
2509 "dynamic unwind table in objfile %s "
2510 "at 0x%s (gp=0x%s)\n",
2511 bfd_get_filename (objfile
->obfd
),
2512 paddr_nz (addr
), paddr_nz (di
.gp
));
2518 return -UNW_ENOINFO
;
2522 /* Frame interface functions for libunwind. */
2525 ia64_libunwind_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2526 struct frame_id
*this_id
)
2532 libunwind_frame_this_id (next_frame
, this_cache
, &id
);
2534 /* We must add the bsp as the special address for frame comparison purposes. */
2535 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
2536 bsp
= extract_unsigned_integer (buf
, 8);
2538 (*this_id
) = frame_id_build_special (id
.stack_addr
, id
.code_addr
, bsp
);
2540 if (gdbarch_debug
>= 1)
2541 fprintf_unfiltered (gdb_stdlog
,
2542 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2543 paddr_nz (id
.code_addr
), paddr_nz (id
.stack_addr
),
2544 paddr_nz (bsp
), next_frame
);
2548 ia64_libunwind_frame_prev_register (struct frame_info
*next_frame
,
2550 int regnum
, int *optimizedp
,
2551 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2552 int *realnump
, void *valuep
)
2556 if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
2557 reg
= IA64_PR_REGNUM
;
2558 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
2559 reg
= IA64_UNAT_REGNUM
;
2561 /* Let libunwind do most of the work. */
2562 libunwind_frame_prev_register (next_frame
, this_cache
, reg
,
2563 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2565 /* No more to do if the value is not supposed to be supplied. */
2569 if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
2573 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
2577 unsigned char buf
[MAX_REGISTER_SIZE
];
2579 /* Fetch predicate register rename base from current frame
2580 marker for this frame. */
2581 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
2582 cfm
= extract_unsigned_integer (buf
, 8);
2583 rrb_pr
= (cfm
>> 32) & 0x3f;
2585 /* Adjust the register number to account for register rotation. */
2586 regnum
= VP16_REGNUM
2587 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
2589 prN_val
= extract_bit_field ((unsigned char *) valuep
,
2590 regnum
- VP0_REGNUM
, 1);
2591 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
), prN_val
);
2593 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
2597 unatN_val
= extract_bit_field ((unsigned char *) valuep
,
2598 regnum
- IA64_NAT0_REGNUM
, 1);
2599 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
),
2602 else if (regnum
== IA64_BSP_REGNUM
)
2604 char cfm_valuep
[MAX_REGISTER_SIZE
];
2607 enum lval_type cfm_lval
;
2609 CORE_ADDR bsp
, prev_cfm
, prev_bsp
;
2611 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2612 This corresponds to what the hardware bsp register will be if we pop the frame
2613 back which is why we might have been called. We know that libunwind will pass us back
2614 the beginning of the current frame so we should just add sof to it. */
2615 prev_bsp
= extract_unsigned_integer (valuep
, 8);
2616 libunwind_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
2617 &cfm_optim
, &cfm_lval
, &cfm_addr
, &cfm_realnum
, cfm_valuep
);
2618 prev_cfm
= extract_unsigned_integer (cfm_valuep
, 8);
2619 prev_bsp
= rse_address_add (prev_bsp
, (prev_cfm
& 0x7f));
2621 store_unsigned_integer (valuep
, register_size (current_gdbarch
, regnum
),
2625 if (gdbarch_debug
>= 1)
2626 fprintf_unfiltered (gdb_stdlog
,
2627 "libunwind prev register <%s> is 0x%s\n",
2628 (((unsigned) regnum
<= IA64_NAT127_REGNUM
)
2629 ? ia64_register_names
[regnum
] : "r??"),
2630 paddr_nz (extract_unsigned_integer (valuep
, 8)));
2633 static const struct frame_unwind ia64_libunwind_frame_unwind
=
2636 ia64_libunwind_frame_this_id
,
2637 ia64_libunwind_frame_prev_register
2640 static const struct frame_unwind
*
2641 ia64_libunwind_frame_sniffer (struct frame_info
*next_frame
)
2643 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame
))
2644 return &ia64_libunwind_frame_unwind
;
2649 /* Set of libunwind callback acccessor functions. */
2650 static unw_accessors_t ia64_unw_accessors
=
2652 ia64_find_proc_info_x
,
2653 ia64_put_unwind_info
,
2654 ia64_get_dyn_info_list
,
2662 /* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2663 static struct libunwind_descr ia64_libunwind_descr
=
2668 &ia64_unw_accessors
,
2671 #endif /* HAVE_LIBUNWIND_IA64_H */
2673 /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2674 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2675 is the type (which is known to be struct, union or array). */
2677 ia64_use_struct_convention (int gcc_p
, struct type
*type
)
2679 struct type
*float_elt_type
;
2681 /* HFAs are structures (or arrays) consisting entirely of floating
2682 point values of the same length. Up to 8 of these are returned
2683 in registers. Don't use the struct convention when this is the
2685 float_elt_type
= is_float_or_hfa_type (type
);
2686 if (float_elt_type
!= NULL
2687 && TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
) <= 8)
2690 /* Other structs of length 32 or less are returned in r8-r11.
2691 Don't use the struct convention for those either. */
2692 return TYPE_LENGTH (type
) > 32;
2696 ia64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
2699 struct type
*float_elt_type
;
2701 float_elt_type
= is_float_or_hfa_type (type
);
2702 if (float_elt_type
!= NULL
)
2704 char from
[MAX_REGISTER_SIZE
];
2706 int regnum
= IA64_FR8_REGNUM
;
2707 int n
= TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
);
2711 regcache_cooked_read (regcache
, regnum
, from
);
2712 convert_typed_floating (from
, builtin_type_ia64_ext
,
2713 (char *)valbuf
+ offset
, float_elt_type
);
2714 offset
+= TYPE_LENGTH (float_elt_type
);
2722 int regnum
= IA64_GR8_REGNUM
;
2723 int reglen
= TYPE_LENGTH (ia64_register_type (NULL
, IA64_GR8_REGNUM
));
2724 int n
= TYPE_LENGTH (type
) / reglen
;
2725 int m
= TYPE_LENGTH (type
) % reglen
;
2730 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2731 memcpy ((char *)valbuf
+ offset
, &val
, reglen
);
2738 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2739 memcpy ((char *)valbuf
+ offset
, &val
, m
);
2745 ia64_extract_struct_value_address (struct regcache
*regcache
)
2747 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
2753 is_float_or_hfa_type_recurse (struct type
*t
, struct type
**etp
)
2755 switch (TYPE_CODE (t
))
2759 return TYPE_LENGTH (*etp
) == TYPE_LENGTH (t
);
2766 case TYPE_CODE_ARRAY
:
2768 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t
)),
2771 case TYPE_CODE_STRUCT
:
2775 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2776 if (!is_float_or_hfa_type_recurse
2777 (check_typedef (TYPE_FIELD_TYPE (t
, i
)), etp
))
2788 /* Determine if the given type is one of the floating point types or
2789 and HFA (which is a struct, array, or combination thereof whose
2790 bottom-most elements are all of the same floating point type). */
2792 static struct type
*
2793 is_float_or_hfa_type (struct type
*t
)
2795 struct type
*et
= 0;
2797 return is_float_or_hfa_type_recurse (t
, &et
) ? et
: 0;
2801 /* Return 1 if the alignment of T is such that the next even slot
2802 should be used. Return 0, if the next available slot should
2803 be used. (See section 8.5.1 of the IA-64 Software Conventions
2804 and Runtime manual). */
2807 slot_alignment_is_next_even (struct type
*t
)
2809 switch (TYPE_CODE (t
))
2813 if (TYPE_LENGTH (t
) > 8)
2817 case TYPE_CODE_ARRAY
:
2819 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t
)));
2820 case TYPE_CODE_STRUCT
:
2824 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2825 if (slot_alignment_is_next_even
2826 (check_typedef (TYPE_FIELD_TYPE (t
, i
))))
2835 /* Attempt to find (and return) the global pointer for the given
2838 This is a rather nasty bit of code searchs for the .dynamic section
2839 in the objfile corresponding to the pc of the function we're trying
2840 to call. Once it finds the addresses at which the .dynamic section
2841 lives in the child process, it scans the Elf64_Dyn entries for a
2842 DT_PLTGOT tag. If it finds one of these, the corresponding
2843 d_un.d_ptr value is the global pointer. */
2846 ia64_find_global_pointer (CORE_ADDR faddr
)
2848 struct obj_section
*faddr_sect
;
2850 faddr_sect
= find_pc_section (faddr
);
2851 if (faddr_sect
!= NULL
)
2853 struct obj_section
*osect
;
2855 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2857 if (strcmp (osect
->the_bfd_section
->name
, ".dynamic") == 0)
2861 if (osect
< faddr_sect
->objfile
->sections_end
)
2866 while (addr
< osect
->endaddr
)
2872 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2875 tag
= extract_signed_integer (buf
, sizeof (buf
));
2877 if (tag
== DT_PLTGOT
)
2879 CORE_ADDR global_pointer
;
2881 status
= target_read_memory (addr
+ 8, buf
, sizeof (buf
));
2884 global_pointer
= extract_unsigned_integer (buf
, sizeof (buf
));
2887 return global_pointer
;
2900 /* Given a function's address, attempt to find (and return) the
2901 corresponding (canonical) function descriptor. Return 0 if
2904 find_extant_func_descr (CORE_ADDR faddr
)
2906 struct obj_section
*faddr_sect
;
2908 /* Return early if faddr is already a function descriptor. */
2909 faddr_sect
= find_pc_section (faddr
);
2910 if (faddr_sect
&& strcmp (faddr_sect
->the_bfd_section
->name
, ".opd") == 0)
2913 if (faddr_sect
!= NULL
)
2915 struct obj_section
*osect
;
2916 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2918 if (strcmp (osect
->the_bfd_section
->name
, ".opd") == 0)
2922 if (osect
< faddr_sect
->objfile
->sections_end
)
2927 while (addr
< osect
->endaddr
)
2933 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2936 faddr2
= extract_signed_integer (buf
, sizeof (buf
));
2938 if (faddr
== faddr2
)
2948 /* Attempt to find a function descriptor corresponding to the
2949 given address. If none is found, construct one on the
2950 stack using the address at fdaptr. */
2953 find_func_descr (CORE_ADDR faddr
, CORE_ADDR
*fdaptr
)
2957 fdesc
= find_extant_func_descr (faddr
);
2961 CORE_ADDR global_pointer
;
2967 global_pointer
= ia64_find_global_pointer (faddr
);
2969 if (global_pointer
== 0)
2970 global_pointer
= read_register (IA64_GR1_REGNUM
);
2972 store_unsigned_integer (buf
, 8, faddr
);
2973 store_unsigned_integer (buf
+ 8, 8, global_pointer
);
2975 write_memory (fdesc
, buf
, 16);
2981 /* Use the following routine when printing out function pointers
2982 so the user can see the function address rather than just the
2983 function descriptor. */
2985 ia64_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
2986 struct target_ops
*targ
)
2988 struct obj_section
*s
;
2990 s
= find_pc_section (addr
);
2992 /* check if ADDR points to a function descriptor. */
2993 if (s
&& strcmp (s
->the_bfd_section
->name
, ".opd") == 0)
2994 return read_memory_unsigned_integer (addr
, 8);
3000 ia64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3006 ia64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3007 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3008 int nargs
, struct value
**args
, CORE_ADDR sp
,
3009 int struct_return
, CORE_ADDR struct_addr
)
3015 int nslots
, rseslots
, memslots
, slotnum
, nfuncargs
;
3017 CORE_ADDR bsp
, cfm
, pfs
, new_bsp
, funcdescaddr
, pc
, global_pointer
;
3018 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3022 /* Count the number of slots needed for the arguments. */
3023 for (argno
= 0; argno
< nargs
; argno
++)
3026 type
= check_typedef (value_type (arg
));
3027 len
= TYPE_LENGTH (type
);
3029 if ((nslots
& 1) && slot_alignment_is_next_even (type
))
3032 if (TYPE_CODE (type
) == TYPE_CODE_FUNC
)
3035 nslots
+= (len
+ 7) / 8;
3038 /* Divvy up the slots between the RSE and the memory stack. */
3039 rseslots
= (nslots
> 8) ? 8 : nslots
;
3040 memslots
= nslots
- rseslots
;
3042 /* Allocate a new RSE frame. */
3043 cfm
= read_register (IA64_CFM_REGNUM
);
3045 bsp
= read_register (IA64_BSP_REGNUM
);
3046 new_bsp
= rse_address_add (bsp
, rseslots
);
3047 write_register (IA64_BSP_REGNUM
, new_bsp
);
3049 pfs
= read_register (IA64_PFS_REGNUM
);
3050 pfs
&= 0xc000000000000000LL
;
3051 pfs
|= (cfm
& 0xffffffffffffLL
);
3052 write_register (IA64_PFS_REGNUM
, pfs
);
3054 cfm
&= 0xc000000000000000LL
;
3056 write_register (IA64_CFM_REGNUM
, cfm
);
3058 /* We will attempt to find function descriptors in the .opd segment,
3059 but if we can't we'll construct them ourselves. That being the
3060 case, we'll need to reserve space on the stack for them. */
3061 funcdescaddr
= sp
- nfuncargs
* 16;
3062 funcdescaddr
&= ~0xfLL
;
3064 /* Adjust the stack pointer to it's new value. The calling conventions
3065 require us to have 16 bytes of scratch, plus whatever space is
3066 necessary for the memory slots and our function descriptors. */
3067 sp
= sp
- 16 - (memslots
+ nfuncargs
) * 8;
3068 sp
&= ~0xfLL
; /* Maintain 16 byte alignment. */
3070 /* Place the arguments where they belong. The arguments will be
3071 either placed in the RSE backing store or on the memory stack.
3072 In addition, floating point arguments or HFAs are placed in
3073 floating point registers. */
3075 floatreg
= IA64_FR8_REGNUM
;
3076 for (argno
= 0; argno
< nargs
; argno
++)
3078 struct type
*float_elt_type
;
3081 type
= check_typedef (value_type (arg
));
3082 len
= TYPE_LENGTH (type
);
3084 /* Special handling for function parameters. */
3086 && TYPE_CODE (type
) == TYPE_CODE_PTR
3087 && TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
)
3091 store_unsigned_integer (val_buf
, 8,
3092 find_func_descr (extract_unsigned_integer (value_contents (arg
), 8),
3094 if (slotnum
< rseslots
)
3095 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
3097 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
3104 /* Skip odd slot if necessary... */
3105 if ((slotnum
& 1) && slot_alignment_is_next_even (type
))
3113 memset (val_buf
, 0, 8);
3114 memcpy (val_buf
, value_contents (arg
) + argoffset
, (len
> 8) ? 8 : len
);
3116 if (slotnum
< rseslots
)
3117 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
3119 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
3126 /* Handle floating point types (including HFAs). */
3127 float_elt_type
= is_float_or_hfa_type (type
);
3128 if (float_elt_type
!= NULL
)
3131 len
= TYPE_LENGTH (type
);
3132 while (len
> 0 && floatreg
< IA64_FR16_REGNUM
)
3134 char to
[MAX_REGISTER_SIZE
];
3135 convert_typed_floating (value_contents (arg
) + argoffset
, float_elt_type
,
3136 to
, builtin_type_ia64_ext
);
3137 regcache_cooked_write (regcache
, floatreg
, (void *)to
);
3139 argoffset
+= TYPE_LENGTH (float_elt_type
);
3140 len
-= TYPE_LENGTH (float_elt_type
);
3145 /* Store the struct return value in r8 if necessary. */
3148 regcache_cooked_write_unsigned (regcache
, IA64_GR8_REGNUM
, (ULONGEST
)struct_addr
);
3151 global_pointer
= ia64_find_global_pointer (func_addr
);
3153 if (global_pointer
!= 0)
3154 write_register (IA64_GR1_REGNUM
, global_pointer
);
3156 write_register (IA64_BR0_REGNUM
, bp_addr
);
3158 write_register (sp_regnum
, sp
);
3163 static struct frame_id
3164 ia64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3169 frame_unwind_register (next_frame
, sp_regnum
, buf
);
3170 sp
= extract_unsigned_integer (buf
, 8);
3172 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
3173 bsp
= extract_unsigned_integer (buf
, 8);
3175 if (gdbarch_debug
>= 1)
3176 fprintf_unfiltered (gdb_stdlog
,
3177 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3178 paddr_nz (frame_pc_unwind (next_frame
)),
3179 paddr_nz (sp
), paddr_nz (bsp
));
3181 return frame_id_build_special (sp
, frame_pc_unwind (next_frame
), bsp
);
3185 ia64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3188 CORE_ADDR ip
, psr
, pc
;
3190 frame_unwind_register (next_frame
, IA64_IP_REGNUM
, buf
);
3191 ip
= extract_unsigned_integer (buf
, 8);
3192 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
3193 psr
= extract_unsigned_integer (buf
, 8);
3195 pc
= (ip
& ~0xf) | ((psr
>> 41) & 3);
3200 ia64_store_return_value (struct type
*type
, struct regcache
*regcache
, const void *valbuf
)
3202 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3204 char to
[MAX_REGISTER_SIZE
];
3205 convert_typed_floating (valbuf
, type
, to
, builtin_type_ia64_ext
);
3206 regcache_cooked_write (regcache
, IA64_FR8_REGNUM
, (void *)to
);
3207 target_store_registers (IA64_FR8_REGNUM
);
3210 regcache_cooked_write (regcache
, IA64_GR8_REGNUM
, valbuf
);
3214 ia64_remote_translate_xfer_address (struct gdbarch
*gdbarch
,
3215 struct regcache
*regcache
,
3216 CORE_ADDR memaddr
, int nr_bytes
,
3217 CORE_ADDR
*targ_addr
, int *targ_len
)
3219 *targ_addr
= memaddr
;
3220 *targ_len
= nr_bytes
;
3224 ia64_print_insn (bfd_vma memaddr
, struct disassemble_info
*info
)
3226 info
->bytes_per_line
= SLOT_MULTIPLIER
;
3227 return print_insn_ia64 (memaddr
, info
);
3230 static struct gdbarch
*
3231 ia64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3233 struct gdbarch
*gdbarch
;
3234 struct gdbarch_tdep
*tdep
;
3236 /* If there is already a candidate, use it. */
3237 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3239 return arches
->gdbarch
;
3241 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
3242 gdbarch
= gdbarch_alloc (&info
, tdep
);
3244 tdep
->sigcontext_register_address
= 0;
3246 /* Define the ia64 floating-point format to gdb. */
3247 builtin_type_ia64_ext
=
3248 init_type (TYPE_CODE_FLT
, 128 / 8,
3249 0, "builtin_type_ia64_ext", NULL
);
3250 TYPE_FLOATFORMAT (builtin_type_ia64_ext
) = &floatformat_ia64_ext
;
3252 /* According to the ia64 specs, instructions that store long double
3253 floats in memory use a long-double format different than that
3254 used in the floating registers. The memory format matches the
3255 x86 extended float format which is 80 bits. An OS may choose to
3256 use this format (e.g. GNU/Linux) or choose to use a different
3257 format for storing long doubles (e.g. HPUX). In the latter case,
3258 the setting of the format may be moved/overridden in an
3259 OS-specific tdep file. */
3260 set_gdbarch_long_double_format (gdbarch
, &floatformat_i387_ext
);
3262 set_gdbarch_short_bit (gdbarch
, 16);
3263 set_gdbarch_int_bit (gdbarch
, 32);
3264 set_gdbarch_long_bit (gdbarch
, 64);
3265 set_gdbarch_long_long_bit (gdbarch
, 64);
3266 set_gdbarch_float_bit (gdbarch
, 32);
3267 set_gdbarch_double_bit (gdbarch
, 64);
3268 set_gdbarch_long_double_bit (gdbarch
, 128);
3269 set_gdbarch_ptr_bit (gdbarch
, 64);
3271 set_gdbarch_num_regs (gdbarch
, NUM_IA64_RAW_REGS
);
3272 set_gdbarch_num_pseudo_regs (gdbarch
, LAST_PSEUDO_REGNUM
- FIRST_PSEUDO_REGNUM
);
3273 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
3274 set_gdbarch_fp0_regnum (gdbarch
, IA64_FR0_REGNUM
);
3276 set_gdbarch_register_name (gdbarch
, ia64_register_name
);
3277 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3278 gets a number of extra failures. */
3279 set_gdbarch_deprecated_register_size (gdbarch
, 8);
3280 set_gdbarch_register_type (gdbarch
, ia64_register_type
);
3282 set_gdbarch_pseudo_register_read (gdbarch
, ia64_pseudo_register_read
);
3283 set_gdbarch_pseudo_register_write (gdbarch
, ia64_pseudo_register_write
);
3284 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, ia64_dwarf_reg_to_regnum
);
3285 set_gdbarch_register_reggroup_p (gdbarch
, ia64_register_reggroup_p
);
3286 set_gdbarch_convert_register_p (gdbarch
, ia64_convert_register_p
);
3287 set_gdbarch_register_to_value (gdbarch
, ia64_register_to_value
);
3288 set_gdbarch_value_to_register (gdbarch
, ia64_value_to_register
);
3290 set_gdbarch_skip_prologue (gdbarch
, ia64_skip_prologue
);
3292 set_gdbarch_deprecated_use_struct_convention (gdbarch
, ia64_use_struct_convention
);
3293 set_gdbarch_extract_return_value (gdbarch
, ia64_extract_return_value
);
3295 set_gdbarch_store_return_value (gdbarch
, ia64_store_return_value
);
3296 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, ia64_extract_struct_value_address
);
3298 set_gdbarch_memory_insert_breakpoint (gdbarch
, ia64_memory_insert_breakpoint
);
3299 set_gdbarch_memory_remove_breakpoint (gdbarch
, ia64_memory_remove_breakpoint
);
3300 set_gdbarch_breakpoint_from_pc (gdbarch
, ia64_breakpoint_from_pc
);
3301 set_gdbarch_read_pc (gdbarch
, ia64_read_pc
);
3302 set_gdbarch_write_pc (gdbarch
, ia64_write_pc
);
3304 /* Settings for calling functions in the inferior. */
3305 set_gdbarch_push_dummy_call (gdbarch
, ia64_push_dummy_call
);
3306 set_gdbarch_frame_align (gdbarch
, ia64_frame_align
);
3307 set_gdbarch_unwind_dummy_id (gdbarch
, ia64_unwind_dummy_id
);
3309 set_gdbarch_unwind_pc (gdbarch
, ia64_unwind_pc
);
3310 frame_unwind_append_sniffer (gdbarch
, ia64_sigtramp_frame_sniffer
);
3311 #ifdef HAVE_LIBUNWIND_IA64_H
3312 frame_unwind_append_sniffer (gdbarch
, ia64_libunwind_frame_sniffer
);
3313 libunwind_frame_set_descr (gdbarch
, &ia64_libunwind_descr
);
3315 frame_unwind_append_sniffer (gdbarch
, ia64_frame_sniffer
);
3316 frame_base_set_default (gdbarch
, &ia64_frame_base
);
3318 /* Settings that should be unnecessary. */
3319 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3321 set_gdbarch_remote_translate_xfer_address (
3322 gdbarch
, ia64_remote_translate_xfer_address
);
3324 set_gdbarch_print_insn (gdbarch
, ia64_print_insn
);
3325 set_gdbarch_convert_from_func_ptr_addr (gdbarch
, ia64_convert_from_func_ptr_addr
);
3327 /* Hook in ABI-specific overrides, if they have been registered. */
3328 gdbarch_init_osabi (info
, gdbarch
);
3333 extern initialize_file_ftype _initialize_ia64_tdep
; /* -Wmissing-prototypes */
3336 _initialize_ia64_tdep (void)
3338 gdbarch_register (bfd_arch_ia64
, ia64_gdbarch_init
, NULL
);