2004-06-06 Randolph Chung <tausq@debian.org>
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software
4 Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "defs.h"
24 #include "inferior.h"
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39 #include "dis-asm.h"
40 #include "infcall.h"
41 #include "ia64-tdep.h"
42
43 #ifdef HAVE_LIBUNWIND_IA64_H
44 #include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
45 #include "libunwind-frame.h"
46 #include "libunwind-ia64.h"
47 #endif
48
49 /* Hook for determining the global pointer when calling functions in
50 the inferior under AIX. The initialization code in ia64-aix-nat.c
51 sets this hook to the address of a function which will find the
52 global pointer for a given address.
53
54 The generic code which uses the dynamic section in the inferior for
55 finding the global pointer is not of much use on AIX since the
56 values obtained from the inferior have not been relocated. */
57
58 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
59
60 /* An enumeration of the different IA-64 instruction types. */
61
62 typedef enum instruction_type
63 {
64 A, /* Integer ALU ; I-unit or M-unit */
65 I, /* Non-ALU integer; I-unit */
66 M, /* Memory ; M-unit */
67 F, /* Floating-point ; F-unit */
68 B, /* Branch ; B-unit */
69 L, /* Extended (L+X) ; I-unit */
70 X, /* Extended (L+X) ; I-unit */
71 undefined /* undefined or reserved */
72 } instruction_type;
73
74 /* We represent IA-64 PC addresses as the value of the instruction
75 pointer or'd with some bit combination in the low nibble which
76 represents the slot number in the bundle addressed by the
77 instruction pointer. The problem is that the Linux kernel
78 multiplies its slot numbers (for exceptions) by one while the
79 disassembler multiplies its slot numbers by 6. In addition, I've
80 heard it said that the simulator uses 1 as the multiplier.
81
82 I've fixed the disassembler so that the bytes_per_line field will
83 be the slot multiplier. If bytes_per_line comes in as zero, it
84 is set to six (which is how it was set up initially). -- objdump
85 displays pretty disassembly dumps with this value. For our purposes,
86 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
87 never want to also display the raw bytes the way objdump does. */
88
89 #define SLOT_MULTIPLIER 1
90
91 /* Length in bytes of an instruction bundle */
92
93 #define BUNDLE_LEN 16
94
95 static gdbarch_init_ftype ia64_gdbarch_init;
96
97 static gdbarch_register_name_ftype ia64_register_name;
98 static gdbarch_register_type_ftype ia64_register_type;
99 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
100 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
101 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
102 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
103 static struct type *is_float_or_hfa_type (struct type *t);
104
105 static struct type *builtin_type_ia64_ext;
106
107 #define NUM_IA64_RAW_REGS 462
108
109 static int sp_regnum = IA64_GR12_REGNUM;
110 static int fp_regnum = IA64_VFP_REGNUM;
111 static int lr_regnum = IA64_VRAP_REGNUM;
112
113 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
114 they may not be accessible via the ptrace register get/set interfaces. */
115 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
116 V127_REGNUM = V32_REGNUM + 95,
117 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
118
119 /* Array of register names; There should be ia64_num_regs strings in
120 the initializer. */
121
122 static char *ia64_register_names[] =
123 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
126 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136 "", "", "", "", "", "", "", "",
137 "", "", "", "", "", "", "", "",
138 "", "", "", "", "", "", "", "",
139
140 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
141 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
142 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
143 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
144 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
145 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
146 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
147 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
148 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
149 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
150 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
151 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
152 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
153 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
154 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
155 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
156
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
165
166 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
167
168 "vfp", "vrap",
169
170 "pr", "ip", "psr", "cfm",
171
172 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
173 "", "", "", "", "", "", "", "",
174 "rsc", "bsp", "bspstore", "rnat",
175 "", "fcr", "", "",
176 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
177 "ccv", "", "", "", "unat", "", "", "",
178 "fpsr", "", "", "", "itc",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "",
181 "pfs", "lc", "ec",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "", "", "",
186 "", "", "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "", "", "",
188 "",
189 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
190 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
191 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
192 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
193 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
194 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
195 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
196 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
197 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
198 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
199 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
200 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
201 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
202 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
203 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
204 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
205
206 "bof",
207
208 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
209 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
210 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
211 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
212 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
213 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
214 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
215 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
216 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
217 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
218 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
219 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
220
221 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
222 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
223 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
224 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
225 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
226 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
227 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
228 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
229 };
230
231 struct ia64_frame_cache
232 {
233 CORE_ADDR base; /* frame pointer base for frame */
234 CORE_ADDR pc; /* function start pc for frame */
235 CORE_ADDR saved_sp; /* stack pointer for frame */
236 CORE_ADDR bsp; /* points at r32 for the current frame */
237 CORE_ADDR cfm; /* cfm value for current frame */
238 CORE_ADDR prev_cfm; /* cfm value for previous frame */
239 int frameless;
240 int sof; /* Size of frame (decoded from cfm value) */
241 int sol; /* Size of locals (decoded from cfm value) */
242 int sor; /* Number of rotating registers. (decoded from cfm value) */
243 CORE_ADDR after_prologue;
244 /* Address of first instruction after the last
245 prologue instruction; Note that there may
246 be instructions from the function's body
247 intermingled with the prologue. */
248 int mem_stack_frame_size;
249 /* Size of the memory stack frame (may be zero),
250 or -1 if it has not been determined yet. */
251 int fp_reg; /* Register number (if any) used a frame pointer
252 for this frame. 0 if no register is being used
253 as the frame pointer. */
254
255 /* Saved registers. */
256 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
257
258 };
259
260 struct gdbarch_tdep
261 {
262 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
263 /* OS specific function which, given a frame address
264 and register number, returns the offset to the
265 given register from the start of the frame. */
266 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
267 };
268
269 #define SIGCONTEXT_REGISTER_ADDRESS \
270 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
271 #define FIND_GLOBAL_POINTER \
272 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
273
274 int
275 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
276 struct reggroup *group)
277 {
278 int vector_p;
279 int float_p;
280 int raw_p;
281 if (group == all_reggroup)
282 return 1;
283 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
284 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
285 raw_p = regnum < NUM_IA64_RAW_REGS;
286 if (group == float_reggroup)
287 return float_p;
288 if (group == vector_reggroup)
289 return vector_p;
290 if (group == general_reggroup)
291 return (!vector_p && !float_p);
292 if (group == save_reggroup || group == restore_reggroup)
293 return raw_p;
294 return 0;
295 }
296
297 static const char *
298 ia64_register_name (int reg)
299 {
300 return ia64_register_names[reg];
301 }
302
303 struct type *
304 ia64_register_type (struct gdbarch *arch, int reg)
305 {
306 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
307 return builtin_type_ia64_ext;
308 else
309 return builtin_type_long;
310 }
311
312 static int
313 ia64_dwarf_reg_to_regnum (int reg)
314 {
315 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
316 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
317 return reg;
318 }
319
320 static int
321 floatformat_valid (const struct floatformat *fmt, const char *from)
322 {
323 return 1;
324 }
325
326 const struct floatformat floatformat_ia64_ext =
327 {
328 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
329 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
330 };
331
332
333 /* Extract ``len'' bits from an instruction bundle starting at
334 bit ``from''. */
335
336 static long long
337 extract_bit_field (char *bundle, int from, int len)
338 {
339 long long result = 0LL;
340 int to = from + len;
341 int from_byte = from / 8;
342 int to_byte = to / 8;
343 unsigned char *b = (unsigned char *) bundle;
344 unsigned char c;
345 int lshift;
346 int i;
347
348 c = b[from_byte];
349 if (from_byte == to_byte)
350 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
351 result = c >> (from % 8);
352 lshift = 8 - (from % 8);
353
354 for (i = from_byte+1; i < to_byte; i++)
355 {
356 result |= ((long long) b[i]) << lshift;
357 lshift += 8;
358 }
359
360 if (from_byte < to_byte && (to % 8 != 0))
361 {
362 c = b[to_byte];
363 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
364 result |= ((long long) c) << lshift;
365 }
366
367 return result;
368 }
369
370 /* Replace the specified bits in an instruction bundle */
371
372 static void
373 replace_bit_field (char *bundle, long long val, int from, int len)
374 {
375 int to = from + len;
376 int from_byte = from / 8;
377 int to_byte = to / 8;
378 unsigned char *b = (unsigned char *) bundle;
379 unsigned char c;
380
381 if (from_byte == to_byte)
382 {
383 unsigned char left, right;
384 c = b[from_byte];
385 left = (c >> (to % 8)) << (to % 8);
386 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
387 c = (unsigned char) (val & 0xff);
388 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
389 c |= right | left;
390 b[from_byte] = c;
391 }
392 else
393 {
394 int i;
395 c = b[from_byte];
396 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
397 c = c | (val << (from % 8));
398 b[from_byte] = c;
399 val >>= 8 - from % 8;
400
401 for (i = from_byte+1; i < to_byte; i++)
402 {
403 c = val & 0xff;
404 val >>= 8;
405 b[i] = c;
406 }
407
408 if (to % 8 != 0)
409 {
410 unsigned char cv = (unsigned char) val;
411 c = b[to_byte];
412 c = c >> (to % 8) << (to % 8);
413 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
414 b[to_byte] = c;
415 }
416 }
417 }
418
419 /* Return the contents of slot N (for N = 0, 1, or 2) in
420 and instruction bundle */
421
422 static long long
423 slotN_contents (char *bundle, int slotnum)
424 {
425 return extract_bit_field (bundle, 5+41*slotnum, 41);
426 }
427
428 /* Store an instruction in an instruction bundle */
429
430 static void
431 replace_slotN_contents (char *bundle, long long instr, int slotnum)
432 {
433 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
434 }
435
436 static enum instruction_type template_encoding_table[32][3] =
437 {
438 { M, I, I }, /* 00 */
439 { M, I, I }, /* 01 */
440 { M, I, I }, /* 02 */
441 { M, I, I }, /* 03 */
442 { M, L, X }, /* 04 */
443 { M, L, X }, /* 05 */
444 { undefined, undefined, undefined }, /* 06 */
445 { undefined, undefined, undefined }, /* 07 */
446 { M, M, I }, /* 08 */
447 { M, M, I }, /* 09 */
448 { M, M, I }, /* 0A */
449 { M, M, I }, /* 0B */
450 { M, F, I }, /* 0C */
451 { M, F, I }, /* 0D */
452 { M, M, F }, /* 0E */
453 { M, M, F }, /* 0F */
454 { M, I, B }, /* 10 */
455 { M, I, B }, /* 11 */
456 { M, B, B }, /* 12 */
457 { M, B, B }, /* 13 */
458 { undefined, undefined, undefined }, /* 14 */
459 { undefined, undefined, undefined }, /* 15 */
460 { B, B, B }, /* 16 */
461 { B, B, B }, /* 17 */
462 { M, M, B }, /* 18 */
463 { M, M, B }, /* 19 */
464 { undefined, undefined, undefined }, /* 1A */
465 { undefined, undefined, undefined }, /* 1B */
466 { M, F, B }, /* 1C */
467 { M, F, B }, /* 1D */
468 { undefined, undefined, undefined }, /* 1E */
469 { undefined, undefined, undefined }, /* 1F */
470 };
471
472 /* Fetch and (partially) decode an instruction at ADDR and return the
473 address of the next instruction to fetch. */
474
475 static CORE_ADDR
476 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
477 {
478 char bundle[BUNDLE_LEN];
479 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
480 long long template;
481 int val;
482
483 /* Warn about slot numbers greater than 2. We used to generate
484 an error here on the assumption that the user entered an invalid
485 address. But, sometimes GDB itself requests an invalid address.
486 This can (easily) happen when execution stops in a function for
487 which there are no symbols. The prologue scanner will attempt to
488 find the beginning of the function - if the nearest symbol
489 happens to not be aligned on a bundle boundary (16 bytes), the
490 resulting starting address will cause GDB to think that the slot
491 number is too large.
492
493 So we warn about it and set the slot number to zero. It is
494 not necessarily a fatal condition, particularly if debugging
495 at the assembly language level. */
496 if (slotnum > 2)
497 {
498 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
499 "Using slot 0 instead");
500 slotnum = 0;
501 }
502
503 addr &= ~0x0f;
504
505 val = target_read_memory (addr, bundle, BUNDLE_LEN);
506
507 if (val != 0)
508 return 0;
509
510 *instr = slotN_contents (bundle, slotnum);
511 template = extract_bit_field (bundle, 0, 5);
512 *it = template_encoding_table[(int)template][slotnum];
513
514 if (slotnum == 2 || (slotnum == 1 && *it == L))
515 addr += 16;
516 else
517 addr += (slotnum + 1) * SLOT_MULTIPLIER;
518
519 return addr;
520 }
521
522 /* There are 5 different break instructions (break.i, break.b,
523 break.m, break.f, and break.x), but they all have the same
524 encoding. (The five bit template in the low five bits of the
525 instruction bundle distinguishes one from another.)
526
527 The runtime architecture manual specifies that break instructions
528 used for debugging purposes must have the upper two bits of the 21
529 bit immediate set to a 0 and a 1 respectively. A breakpoint
530 instruction encodes the most significant bit of its 21 bit
531 immediate at bit 36 of the 41 bit instruction. The penultimate msb
532 is at bit 25 which leads to the pattern below.
533
534 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
535 it turns out that 0x80000 was used as the syscall break in the early
536 simulators. So I changed the pattern slightly to do "break.i 0x080001"
537 instead. But that didn't work either (I later found out that this
538 pattern was used by the simulator that I was using.) So I ended up
539 using the pattern seen below. */
540
541 #if 0
542 #define IA64_BREAKPOINT 0x00002000040LL
543 #endif
544 #define IA64_BREAKPOINT 0x00003333300LL
545
546 static int
547 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
548 {
549 char bundle[BUNDLE_LEN];
550 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
551 long long instr;
552 int val;
553 int template;
554
555 if (slotnum > 2)
556 error("Can't insert breakpoint for slot numbers greater than 2.");
557
558 addr &= ~0x0f;
559
560 val = target_read_memory (addr, bundle, BUNDLE_LEN);
561
562 /* Check for L type instruction in 2nd slot, if present then
563 bump up the slot number to the 3rd slot */
564 template = extract_bit_field (bundle, 0, 5);
565 if (slotnum == 1 && template_encoding_table[template][1] == L)
566 {
567 slotnum = 2;
568 }
569
570 instr = slotN_contents (bundle, slotnum);
571 memcpy(contents_cache, &instr, sizeof(instr));
572 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
573 if (val == 0)
574 target_write_memory (addr, bundle, BUNDLE_LEN);
575
576 return val;
577 }
578
579 static int
580 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
581 {
582 char bundle[BUNDLE_LEN];
583 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
584 long long instr;
585 int val;
586 int template;
587
588 addr &= ~0x0f;
589
590 val = target_read_memory (addr, bundle, BUNDLE_LEN);
591
592 /* Check for L type instruction in 2nd slot, if present then
593 bump up the slot number to the 3rd slot */
594 template = extract_bit_field (bundle, 0, 5);
595 if (slotnum == 1 && template_encoding_table[template][1] == L)
596 {
597 slotnum = 2;
598 }
599
600 memcpy (&instr, contents_cache, sizeof instr);
601 replace_slotN_contents (bundle, instr, slotnum);
602 if (val == 0)
603 target_write_memory (addr, bundle, BUNDLE_LEN);
604
605 return val;
606 }
607
608 /* We don't really want to use this, but remote.c needs to call it in order
609 to figure out if Z-packets are supported or not. Oh, well. */
610 const unsigned char *
611 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
612 {
613 static unsigned char breakpoint[] =
614 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
615 *lenptr = sizeof (breakpoint);
616 #if 0
617 *pcptr &= ~0x0f;
618 #endif
619 return breakpoint;
620 }
621
622 static CORE_ADDR
623 ia64_read_pc (ptid_t ptid)
624 {
625 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
626 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
627 int slot_num = (psr_value >> 41) & 3;
628
629 return pc_value | (slot_num * SLOT_MULTIPLIER);
630 }
631
632 void
633 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
634 {
635 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
636 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
637 psr_value &= ~(3LL << 41);
638 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
639
640 new_pc &= ~0xfLL;
641
642 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
643 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
644 }
645
646 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
647
648 /* Returns the address of the slot that's NSLOTS slots away from
649 the address ADDR. NSLOTS may be positive or negative. */
650 static CORE_ADDR
651 rse_address_add(CORE_ADDR addr, int nslots)
652 {
653 CORE_ADDR new_addr;
654 int mandatory_nat_slots = nslots / 63;
655 int direction = nslots < 0 ? -1 : 1;
656
657 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
658
659 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
660 new_addr += 8 * direction;
661
662 if (IS_NaT_COLLECTION_ADDR(new_addr))
663 new_addr += 8 * direction;
664
665 return new_addr;
666 }
667
668 static void
669 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
670 int regnum, void *buf)
671 {
672 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
673 {
674 ULONGEST bsp;
675 ULONGEST cfm;
676 CORE_ADDR reg;
677 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
678 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
679
680 /* The bsp points at the end of the register frame so we
681 subtract the size of frame from it to get start of register frame. */
682 bsp = rse_address_add (bsp, -(cfm & 0x7f));
683
684 if ((cfm & 0x7f) > regnum - V32_REGNUM)
685 {
686 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
687 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
688 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
689 }
690 else
691 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
692 }
693 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
694 {
695 ULONGEST unatN_val;
696 ULONGEST unat;
697 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
698 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
699 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
700 }
701 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
702 {
703 ULONGEST natN_val = 0;
704 ULONGEST bsp;
705 ULONGEST cfm;
706 CORE_ADDR gr_addr = 0;
707 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
708 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
709
710 /* The bsp points at the end of the register frame so we
711 subtract the size of frame from it to get start of register frame. */
712 bsp = rse_address_add (bsp, -(cfm & 0x7f));
713
714 if ((cfm & 0x7f) > regnum - V32_REGNUM)
715 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
716
717 if (gr_addr != 0)
718 {
719 /* Compute address of nat collection bits. */
720 CORE_ADDR nat_addr = gr_addr | 0x1f8;
721 CORE_ADDR nat_collection;
722 int nat_bit;
723 /* If our nat collection address is bigger than bsp, we have to get
724 the nat collection from rnat. Otherwise, we fetch the nat
725 collection from the computed address. */
726 if (nat_addr >= bsp)
727 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
728 else
729 nat_collection = read_memory_integer (nat_addr, 8);
730 nat_bit = (gr_addr >> 3) & 0x3f;
731 natN_val = (nat_collection >> nat_bit) & 1;
732 }
733
734 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
735 }
736 else if (regnum == VBOF_REGNUM)
737 {
738 /* A virtual register frame start is provided for user convenience.
739 It can be calculated as the bsp - sof (sizeof frame). */
740 ULONGEST bsp, vbsp;
741 ULONGEST cfm;
742 CORE_ADDR reg;
743 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
744 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
745
746 /* The bsp points at the end of the register frame so we
747 subtract the size of frame from it to get beginning of frame. */
748 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
749 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
750 }
751 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
752 {
753 ULONGEST pr;
754 ULONGEST cfm;
755 ULONGEST prN_val;
756 CORE_ADDR reg;
757 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
758 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
759
760 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
761 {
762 /* Fetch predicate register rename base from current frame
763 marker for this frame. */
764 int rrb_pr = (cfm >> 32) & 0x3f;
765
766 /* Adjust the register number to account for register rotation. */
767 regnum = VP16_REGNUM
768 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
769 }
770 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
771 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
772 }
773 else
774 memset (buf, 0, register_size (current_gdbarch, regnum));
775 }
776
777 static void
778 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
779 int regnum, const void *buf)
780 {
781 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
782 {
783 ULONGEST bsp;
784 ULONGEST cfm;
785 CORE_ADDR reg;
786 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
787 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
788
789 bsp = rse_address_add (bsp, -(cfm & 0x7f));
790
791 if ((cfm & 0x7f) > regnum - V32_REGNUM)
792 {
793 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
794 write_memory (reg_addr, (void *)buf, 8);
795 }
796 }
797 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
798 {
799 ULONGEST unatN_val, unat, unatN_mask;
800 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
801 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
802 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
803 if (unatN_val == 0)
804 unat &= ~unatN_mask;
805 else if (unatN_val == 1)
806 unat |= unatN_mask;
807 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
808 }
809 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
810 {
811 ULONGEST natN_val;
812 ULONGEST bsp;
813 ULONGEST cfm;
814 CORE_ADDR gr_addr = 0;
815 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
816 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
817
818 /* The bsp points at the end of the register frame so we
819 subtract the size of frame from it to get start of register frame. */
820 bsp = rse_address_add (bsp, -(cfm & 0x7f));
821
822 if ((cfm & 0x7f) > regnum - V32_REGNUM)
823 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
824
825 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
826
827 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
828 {
829 /* Compute address of nat collection bits. */
830 CORE_ADDR nat_addr = gr_addr | 0x1f8;
831 CORE_ADDR nat_collection;
832 int natN_bit = (gr_addr >> 3) & 0x3f;
833 ULONGEST natN_mask = (1LL << natN_bit);
834 /* If our nat collection address is bigger than bsp, we have to get
835 the nat collection from rnat. Otherwise, we fetch the nat
836 collection from the computed address. */
837 if (nat_addr >= bsp)
838 {
839 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
840 if (natN_val)
841 nat_collection |= natN_mask;
842 else
843 nat_collection &= ~natN_mask;
844 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
845 }
846 else
847 {
848 char nat_buf[8];
849 nat_collection = read_memory_integer (nat_addr, 8);
850 if (natN_val)
851 nat_collection |= natN_mask;
852 else
853 nat_collection &= ~natN_mask;
854 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
855 write_memory (nat_addr, nat_buf, 8);
856 }
857 }
858 }
859 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
860 {
861 ULONGEST pr;
862 ULONGEST cfm;
863 ULONGEST prN_val;
864 ULONGEST prN_mask;
865
866 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
867 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
868
869 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
870 {
871 /* Fetch predicate register rename base from current frame
872 marker for this frame. */
873 int rrb_pr = (cfm >> 32) & 0x3f;
874
875 /* Adjust the register number to account for register rotation. */
876 regnum = VP16_REGNUM
877 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
878 }
879 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
880 prN_mask = (1LL << (regnum - VP0_REGNUM));
881 if (prN_val == 0)
882 pr &= ~prN_mask;
883 else if (prN_val == 1)
884 pr |= prN_mask;
885 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
886 }
887 }
888
889 /* The ia64 needs to convert between various ieee floating-point formats
890 and the special ia64 floating point register format. */
891
892 static int
893 ia64_convert_register_p (int regno, struct type *type)
894 {
895 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
896 }
897
898 static void
899 ia64_register_to_value (struct frame_info *frame, int regnum,
900 struct type *valtype, void *out)
901 {
902 char in[MAX_REGISTER_SIZE];
903 frame_register_read (frame, regnum, in);
904 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
905 }
906
907 static void
908 ia64_value_to_register (struct frame_info *frame, int regnum,
909 struct type *valtype, const void *in)
910 {
911 char out[MAX_REGISTER_SIZE];
912 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
913 put_frame_register (frame, regnum, out);
914 }
915
916
917 /* Limit the number of skipped non-prologue instructions since examining
918 of the prologue is expensive. */
919 static int max_skip_non_prologue_insns = 40;
920
921 /* Given PC representing the starting address of a function, and
922 LIM_PC which is the (sloppy) limit to which to scan when looking
923 for a prologue, attempt to further refine this limit by using
924 the line data in the symbol table. If successful, a better guess
925 on where the prologue ends is returned, otherwise the previous
926 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
927 which will be set to indicate whether the returned limit may be
928 used with no further scanning in the event that the function is
929 frameless. */
930
931 /* FIXME: cagney/2004-02-14: This function and logic have largely been
932 superseded by skip_prologue_using_sal. */
933
934 static CORE_ADDR
935 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
936 {
937 struct symtab_and_line prologue_sal;
938 CORE_ADDR start_pc = pc;
939
940 /* Start off not trusting the limit. */
941 *trust_limit = 0;
942
943 prologue_sal = find_pc_line (pc, 0);
944 if (prologue_sal.line != 0)
945 {
946 int i;
947 CORE_ADDR addr = prologue_sal.end;
948
949 /* Handle the case in which compiler's optimizer/scheduler
950 has moved instructions into the prologue. We scan ahead
951 in the function looking for address ranges whose corresponding
952 line number is less than or equal to the first one that we
953 found for the function. (It can be less than when the
954 scheduler puts a body instruction before the first prologue
955 instruction.) */
956 for (i = 2 * max_skip_non_prologue_insns;
957 i > 0 && (lim_pc == 0 || addr < lim_pc);
958 i--)
959 {
960 struct symtab_and_line sal;
961
962 sal = find_pc_line (addr, 0);
963 if (sal.line == 0)
964 break;
965 if (sal.line <= prologue_sal.line
966 && sal.symtab == prologue_sal.symtab)
967 {
968 prologue_sal = sal;
969 }
970 addr = sal.end;
971 }
972
973 if (lim_pc == 0 || prologue_sal.end < lim_pc)
974 {
975 lim_pc = prologue_sal.end;
976 if (start_pc == get_pc_function_start (lim_pc))
977 *trust_limit = 1;
978 }
979 }
980 return lim_pc;
981 }
982
983 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
984 || (8 <= (_regnum_) && (_regnum_) <= 11) \
985 || (14 <= (_regnum_) && (_regnum_) <= 31))
986 #define imm9(_instr_) \
987 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
988 | (((_instr_) & 0x00008000000LL) >> 20) \
989 | (((_instr_) & 0x00000001fc0LL) >> 6))
990
991 /* Allocate and initialize a frame cache. */
992
993 static struct ia64_frame_cache *
994 ia64_alloc_frame_cache (void)
995 {
996 struct ia64_frame_cache *cache;
997 int i;
998
999 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1000
1001 /* Base address. */
1002 cache->base = 0;
1003 cache->pc = 0;
1004 cache->cfm = 0;
1005 cache->prev_cfm = 0;
1006 cache->sof = 0;
1007 cache->sol = 0;
1008 cache->sor = 0;
1009 cache->bsp = 0;
1010 cache->fp_reg = 0;
1011 cache->frameless = 1;
1012
1013 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1014 cache->saved_regs[i] = 0;
1015
1016 return cache;
1017 }
1018
1019 static CORE_ADDR
1020 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1021 {
1022 CORE_ADDR next_pc;
1023 CORE_ADDR last_prologue_pc = pc;
1024 instruction_type it;
1025 long long instr;
1026 int cfm_reg = 0;
1027 int ret_reg = 0;
1028 int fp_reg = 0;
1029 int unat_save_reg = 0;
1030 int pr_save_reg = 0;
1031 int mem_stack_frame_size = 0;
1032 int spill_reg = 0;
1033 CORE_ADDR spill_addr = 0;
1034 char instores[8];
1035 char infpstores[8];
1036 char reg_contents[256];
1037 int trust_limit;
1038 int frameless = 1;
1039 int i;
1040 CORE_ADDR addr;
1041 char buf[8];
1042 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1043
1044 memset (instores, 0, sizeof instores);
1045 memset (infpstores, 0, sizeof infpstores);
1046 memset (reg_contents, 0, sizeof reg_contents);
1047
1048 if (cache->after_prologue != 0
1049 && cache->after_prologue <= lim_pc)
1050 return cache->after_prologue;
1051
1052 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1053 next_pc = fetch_instruction (pc, &it, &instr);
1054
1055 /* We want to check if we have a recognizable function start before we
1056 look ahead for a prologue. */
1057 if (pc < lim_pc && next_pc
1058 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1059 {
1060 /* alloc - start of a regular function. */
1061 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1062 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1063 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1064 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1065
1066 /* Verify that the current cfm matches what we think is the
1067 function start. If we have somehow jumped within a function,
1068 we do not want to interpret the prologue and calculate the
1069 addresses of various registers such as the return address.
1070 We will instead treat the frame as frameless. */
1071 if (!next_frame ||
1072 (sof == (cache->cfm & 0x7f) &&
1073 sol == ((cache->cfm >> 7) & 0x7f)))
1074 frameless = 0;
1075
1076 cfm_reg = rN;
1077 last_prologue_pc = next_pc;
1078 pc = next_pc;
1079 }
1080 else
1081 {
1082 /* Look for a leaf routine. */
1083 if (pc < lim_pc && next_pc
1084 && (it == I || it == M)
1085 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1086 {
1087 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1088 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1089 | ((instr & 0x001f8000000LL) >> 20)
1090 | ((instr & 0x000000fe000LL) >> 13));
1091 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1092 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1093 int qp = (int) (instr & 0x0000000003fLL);
1094 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1095 {
1096 /* mov r2, r12 - beginning of leaf routine */
1097 fp_reg = rN;
1098 last_prologue_pc = next_pc;
1099 }
1100 }
1101
1102 /* If we don't recognize a regular function or leaf routine, we are
1103 done. */
1104 if (!fp_reg)
1105 {
1106 pc = lim_pc;
1107 if (trust_limit)
1108 last_prologue_pc = lim_pc;
1109 }
1110 }
1111
1112 /* Loop, looking for prologue instructions, keeping track of
1113 where preserved registers were spilled. */
1114 while (pc < lim_pc)
1115 {
1116 next_pc = fetch_instruction (pc, &it, &instr);
1117 if (next_pc == 0)
1118 break;
1119
1120 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
1121 {
1122 /* Exit loop upon hitting a non-nop branch instruction. */
1123 if (trust_limit)
1124 lim_pc = pc;
1125 break;
1126 }
1127 else if (((instr & 0x3fLL) != 0LL) &&
1128 (frameless || ret_reg != 0))
1129 {
1130 /* Exit loop upon hitting a predicated instruction if
1131 we already have the return register or if we are frameless. */
1132 if (trust_limit)
1133 lim_pc = pc;
1134 break;
1135 }
1136 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1137 {
1138 /* Move from BR */
1139 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1140 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1141 int qp = (int) (instr & 0x0000000003f);
1142
1143 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1144 {
1145 ret_reg = rN;
1146 last_prologue_pc = next_pc;
1147 }
1148 }
1149 else if ((it == I || it == M)
1150 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1151 {
1152 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1153 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1154 | ((instr & 0x001f8000000LL) >> 20)
1155 | ((instr & 0x000000fe000LL) >> 13));
1156 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1157 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1158 int qp = (int) (instr & 0x0000000003fLL);
1159
1160 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1161 {
1162 /* mov rN, r12 */
1163 fp_reg = rN;
1164 last_prologue_pc = next_pc;
1165 }
1166 else if (qp == 0 && rN == 12 && rM == 12)
1167 {
1168 /* adds r12, -mem_stack_frame_size, r12 */
1169 mem_stack_frame_size -= imm;
1170 last_prologue_pc = next_pc;
1171 }
1172 else if (qp == 0 && rN == 2
1173 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1174 {
1175 char buf[MAX_REGISTER_SIZE];
1176 CORE_ADDR saved_sp = 0;
1177 /* adds r2, spilloffset, rFramePointer
1178 or
1179 adds r2, spilloffset, r12
1180
1181 Get ready for stf.spill or st8.spill instructions.
1182 The address to start spilling at is loaded into r2.
1183 FIXME: Why r2? That's what gcc currently uses; it
1184 could well be different for other compilers. */
1185
1186 /* Hmm... whether or not this will work will depend on
1187 where the pc is. If it's still early in the prologue
1188 this'll be wrong. FIXME */
1189 if (next_frame)
1190 {
1191 frame_unwind_register (next_frame, sp_regnum, buf);
1192 saved_sp = extract_unsigned_integer (buf, 8);
1193 }
1194 spill_addr = saved_sp
1195 + (rM == 12 ? 0 : mem_stack_frame_size)
1196 + imm;
1197 spill_reg = rN;
1198 last_prologue_pc = next_pc;
1199 }
1200 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1201 rN < 256 && imm == 0)
1202 {
1203 /* mov rN, rM where rM is an input register */
1204 reg_contents[rN] = rM;
1205 last_prologue_pc = next_pc;
1206 }
1207 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1208 rM == 2)
1209 {
1210 /* mov r12, r2 */
1211 last_prologue_pc = next_pc;
1212 break;
1213 }
1214 }
1215 else if (it == M
1216 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1217 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1218 {
1219 /* stf.spill [rN] = fM, imm9
1220 or
1221 stf.spill [rN] = fM */
1222
1223 int imm = imm9(instr);
1224 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1225 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1226 int qp = (int) (instr & 0x0000000003fLL);
1227 if (qp == 0 && rN == spill_reg && spill_addr != 0
1228 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1229 {
1230 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1231
1232 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1233 spill_addr += imm;
1234 else
1235 spill_addr = 0; /* last one; must be done */
1236 last_prologue_pc = next_pc;
1237 }
1238 }
1239 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1240 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1241 {
1242 /* mov.m rN = arM
1243 or
1244 mov.i rN = arM */
1245
1246 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1247 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1248 int qp = (int) (instr & 0x0000000003fLL);
1249 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1250 {
1251 /* We have something like "mov.m r3 = ar.unat". Remember the
1252 r3 (or whatever) and watch for a store of this register... */
1253 unat_save_reg = rN;
1254 last_prologue_pc = next_pc;
1255 }
1256 }
1257 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1258 {
1259 /* mov rN = pr */
1260 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1261 int qp = (int) (instr & 0x0000000003fLL);
1262 if (qp == 0 && isScratch (rN))
1263 {
1264 pr_save_reg = rN;
1265 last_prologue_pc = next_pc;
1266 }
1267 }
1268 else if (it == M
1269 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1270 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1271 {
1272 /* st8 [rN] = rM
1273 or
1274 st8 [rN] = rM, imm9 */
1275 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1276 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1277 int qp = (int) (instr & 0x0000000003fLL);
1278 int indirect = rM < 256 ? reg_contents[rM] : 0;
1279 if (qp == 0 && rN == spill_reg && spill_addr != 0
1280 && (rM == unat_save_reg || rM == pr_save_reg))
1281 {
1282 /* We've found a spill of either the UNAT register or the PR
1283 register. (Well, not exactly; what we've actually found is
1284 a spill of the register that UNAT or PR was moved to).
1285 Record that fact and move on... */
1286 if (rM == unat_save_reg)
1287 {
1288 /* Track UNAT register */
1289 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1290 unat_save_reg = 0;
1291 }
1292 else
1293 {
1294 /* Track PR register */
1295 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1296 pr_save_reg = 0;
1297 }
1298 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1299 /* st8 [rN] = rM, imm9 */
1300 spill_addr += imm9(instr);
1301 else
1302 spill_addr = 0; /* must be done spilling */
1303 last_prologue_pc = next_pc;
1304 }
1305 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1306 {
1307 /* Allow up to one store of each input register. */
1308 instores[rM-32] = 1;
1309 last_prologue_pc = next_pc;
1310 }
1311 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1312 !instores[indirect-32])
1313 {
1314 /* Allow an indirect store of an input register. */
1315 instores[indirect-32] = 1;
1316 last_prologue_pc = next_pc;
1317 }
1318 }
1319 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1320 {
1321 /* One of
1322 st1 [rN] = rM
1323 st2 [rN] = rM
1324 st4 [rN] = rM
1325 st8 [rN] = rM
1326 Note that the st8 case is handled in the clause above.
1327
1328 Advance over stores of input registers. One store per input
1329 register is permitted. */
1330 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1331 int qp = (int) (instr & 0x0000000003fLL);
1332 int indirect = rM < 256 ? reg_contents[rM] : 0;
1333 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1334 {
1335 instores[rM-32] = 1;
1336 last_prologue_pc = next_pc;
1337 }
1338 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1339 !instores[indirect-32])
1340 {
1341 /* Allow an indirect store of an input register. */
1342 instores[indirect-32] = 1;
1343 last_prologue_pc = next_pc;
1344 }
1345 }
1346 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1347 {
1348 /* Either
1349 stfs [rN] = fM
1350 or
1351 stfd [rN] = fM
1352
1353 Advance over stores of floating point input registers. Again
1354 one store per register is permitted */
1355 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1356 int qp = (int) (instr & 0x0000000003fLL);
1357 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1358 {
1359 infpstores[fM-8] = 1;
1360 last_prologue_pc = next_pc;
1361 }
1362 }
1363 else if (it == M
1364 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1365 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1366 {
1367 /* st8.spill [rN] = rM
1368 or
1369 st8.spill [rN] = rM, imm9 */
1370 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1371 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1372 int qp = (int) (instr & 0x0000000003fLL);
1373 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1374 {
1375 /* We've found a spill of one of the preserved general purpose
1376 regs. Record the spill address and advance the spill
1377 register if appropriate. */
1378 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1379 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1380 /* st8.spill [rN] = rM, imm9 */
1381 spill_addr += imm9(instr);
1382 else
1383 spill_addr = 0; /* Done spilling */
1384 last_prologue_pc = next_pc;
1385 }
1386 }
1387
1388 pc = next_pc;
1389 }
1390
1391 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1392 registers for the previous frame which will be needed later. */
1393
1394 if (!frameless && next_frame)
1395 {
1396 /* Extract the size of the rotating portion of the stack
1397 frame and the register rename base from the current
1398 frame marker. */
1399 cfm = cache->cfm;
1400 sor = cache->sor;
1401 sof = cache->sof;
1402 sol = cache->sol;
1403 rrb_gr = (cfm >> 18) & 0x7f;
1404
1405 /* Find the bof (beginning of frame). */
1406 bof = rse_address_add (cache->bsp, -sof);
1407
1408 for (i = 0, addr = bof;
1409 i < sof;
1410 i++, addr += 8)
1411 {
1412 if (IS_NaT_COLLECTION_ADDR (addr))
1413 {
1414 addr += 8;
1415 }
1416 if (i+32 == cfm_reg)
1417 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1418 if (i+32 == ret_reg)
1419 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1420 if (i+32 == fp_reg)
1421 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1422 }
1423
1424 /* For the previous argument registers we require the previous bof.
1425 If we can't find the previous cfm, then we can do nothing. */
1426 cfm = 0;
1427 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1428 {
1429 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1430 }
1431 else if (cfm_reg != 0)
1432 {
1433 frame_unwind_register (next_frame, cfm_reg, buf);
1434 cfm = extract_unsigned_integer (buf, 8);
1435 }
1436 cache->prev_cfm = cfm;
1437
1438 if (cfm != 0)
1439 {
1440 sor = ((cfm >> 14) & 0xf) * 8;
1441 sof = (cfm & 0x7f);
1442 sol = (cfm >> 7) & 0x7f;
1443 rrb_gr = (cfm >> 18) & 0x7f;
1444
1445 /* The previous bof only requires subtraction of the sol (size of locals)
1446 due to the overlap between output and input of subsequent frames. */
1447 bof = rse_address_add (bof, -sol);
1448
1449 for (i = 0, addr = bof;
1450 i < sof;
1451 i++, addr += 8)
1452 {
1453 if (IS_NaT_COLLECTION_ADDR (addr))
1454 {
1455 addr += 8;
1456 }
1457 if (i < sor)
1458 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1459 = addr;
1460 else
1461 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1462 }
1463
1464 }
1465 }
1466
1467 /* Try and trust the lim_pc value whenever possible. */
1468 if (trust_limit && lim_pc >= last_prologue_pc)
1469 last_prologue_pc = lim_pc;
1470
1471 cache->frameless = frameless;
1472 cache->after_prologue = last_prologue_pc;
1473 cache->mem_stack_frame_size = mem_stack_frame_size;
1474 cache->fp_reg = fp_reg;
1475
1476 return last_prologue_pc;
1477 }
1478
1479 CORE_ADDR
1480 ia64_skip_prologue (CORE_ADDR pc)
1481 {
1482 struct ia64_frame_cache cache;
1483 cache.base = 0;
1484 cache.after_prologue = 0;
1485 cache.cfm = 0;
1486 cache.bsp = 0;
1487
1488 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1489 return examine_prologue (pc, pc+1024, 0, &cache);
1490 }
1491
1492
1493 /* Normal frames. */
1494
1495 static struct ia64_frame_cache *
1496 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1497 {
1498 struct ia64_frame_cache *cache;
1499 char buf[8];
1500 CORE_ADDR cfm, sof, sol, bsp, psr;
1501 int i;
1502
1503 if (*this_cache)
1504 return *this_cache;
1505
1506 cache = ia64_alloc_frame_cache ();
1507 *this_cache = cache;
1508
1509 frame_unwind_register (next_frame, sp_regnum, buf);
1510 cache->saved_sp = extract_unsigned_integer (buf, 8);
1511
1512 /* We always want the bsp to point to the end of frame.
1513 This way, we can always get the beginning of frame (bof)
1514 by subtracting frame size. */
1515 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1516 cache->bsp = extract_unsigned_integer (buf, 8);
1517
1518 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1519 psr = extract_unsigned_integer (buf, 8);
1520
1521 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1522 cfm = extract_unsigned_integer (buf, 8);
1523
1524 cache->sof = (cfm & 0x7f);
1525 cache->sol = (cfm >> 7) & 0x7f;
1526 cache->sor = ((cfm >> 14) & 0xf) * 8;
1527
1528 cache->cfm = cfm;
1529
1530 cache->pc = frame_func_unwind (next_frame);
1531
1532 if (cache->pc != 0)
1533 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1534
1535 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1536
1537 return cache;
1538 }
1539
1540 static void
1541 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1542 struct frame_id *this_id)
1543 {
1544 struct ia64_frame_cache *cache =
1545 ia64_frame_cache (next_frame, this_cache);
1546
1547 /* This marks the outermost frame. */
1548 if (cache->base == 0)
1549 return;
1550
1551 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1552 if (gdbarch_debug >= 1)
1553 fprintf_unfiltered (gdb_stdlog,
1554 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1555 paddr_nz (this_id->code_addr),
1556 paddr_nz (this_id->stack_addr),
1557 paddr_nz (cache->bsp), next_frame);
1558 }
1559
1560 static void
1561 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1562 int regnum, int *optimizedp,
1563 enum lval_type *lvalp, CORE_ADDR *addrp,
1564 int *realnump, void *valuep)
1565 {
1566 struct ia64_frame_cache *cache =
1567 ia64_frame_cache (next_frame, this_cache);
1568 char dummy_valp[MAX_REGISTER_SIZE];
1569 char buf[8];
1570
1571 gdb_assert (regnum >= 0);
1572
1573 if (!target_has_registers)
1574 error ("No registers.");
1575
1576 *optimizedp = 0;
1577 *addrp = 0;
1578 *lvalp = not_lval;
1579 *realnump = -1;
1580
1581 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1582 when valuep is not supplied. */
1583 if (!valuep)
1584 valuep = dummy_valp;
1585
1586 memset (valuep, 0, register_size (current_gdbarch, regnum));
1587
1588 if (regnum == SP_REGNUM)
1589 {
1590 /* Handle SP values for all frames but the topmost. */
1591 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1592 cache->base);
1593 }
1594 else if (regnum == IA64_BSP_REGNUM)
1595 {
1596 char cfm_valuep[MAX_REGISTER_SIZE];
1597 int cfm_optim;
1598 int cfm_realnum;
1599 enum lval_type cfm_lval;
1600 CORE_ADDR cfm_addr;
1601 CORE_ADDR bsp, prev_cfm, prev_bsp;
1602
1603 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1604 This corresponds to what the hardware bsp register will be if we pop the frame
1605 back which is why we might have been called. We know the beginning of the current
1606 frame is cache->bsp - cache->sof. This value in the previous frame points to
1607 the start of the output registers. We can calculate the end of that frame by adding
1608 the size of output (sof (size of frame) - sol (size of locals)). */
1609 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1610 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1611 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1612
1613 bsp = rse_address_add (cache->bsp, -(cache->sof));
1614 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1615
1616 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1617 prev_bsp);
1618 }
1619 else if (regnum == IA64_CFM_REGNUM)
1620 {
1621 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1622
1623 if (addr != 0)
1624 {
1625 *lvalp = lval_memory;
1626 *addrp = addr;
1627 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1628 }
1629 else if (cache->prev_cfm)
1630 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1631 else if (cache->frameless)
1632 {
1633 CORE_ADDR cfm = 0;
1634 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1635 }
1636 }
1637 else if (regnum == IA64_VFP_REGNUM)
1638 {
1639 /* If the function in question uses an automatic register (r32-r127)
1640 for the frame pointer, it'll be found by ia64_find_saved_register()
1641 above. If the function lacks one of these frame pointers, we can
1642 still provide a value since we know the size of the frame. */
1643 CORE_ADDR vfp = cache->base;
1644 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
1645 }
1646 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1647 {
1648 char pr_valuep[MAX_REGISTER_SIZE];
1649 int pr_optim;
1650 int pr_realnum;
1651 enum lval_type pr_lval;
1652 CORE_ADDR pr_addr;
1653 ULONGEST prN_val;
1654 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1655 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1656 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1657 {
1658 /* Fetch predicate register rename base from current frame
1659 marker for this frame. */
1660 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1661
1662 /* Adjust the register number to account for register rotation. */
1663 regnum = VP16_REGNUM
1664 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1665 }
1666 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1667 regnum - VP0_REGNUM, 1);
1668 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
1669 }
1670 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1671 {
1672 char unat_valuep[MAX_REGISTER_SIZE];
1673 int unat_optim;
1674 int unat_realnum;
1675 enum lval_type unat_lval;
1676 CORE_ADDR unat_addr;
1677 ULONGEST unatN_val;
1678 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1679 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1680 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1681 regnum - IA64_NAT0_REGNUM, 1);
1682 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1683 unatN_val);
1684 }
1685 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1686 {
1687 int natval = 0;
1688 /* Find address of general register corresponding to nat bit we're
1689 interested in. */
1690 CORE_ADDR gr_addr;
1691
1692 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1693 + IA64_GR0_REGNUM];
1694 if (gr_addr != 0)
1695 {
1696 /* Compute address of nat collection bits. */
1697 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1698 CORE_ADDR bsp;
1699 CORE_ADDR nat_collection;
1700 int nat_bit;
1701 /* If our nat collection address is bigger than bsp, we have to get
1702 the nat collection from rnat. Otherwise, we fetch the nat
1703 collection from the computed address. */
1704 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1705 bsp = extract_unsigned_integer (buf, 8);
1706 if (nat_addr >= bsp)
1707 {
1708 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1709 nat_collection = extract_unsigned_integer (buf, 8);
1710 }
1711 else
1712 nat_collection = read_memory_integer (nat_addr, 8);
1713 nat_bit = (gr_addr >> 3) & 0x3f;
1714 natval = (nat_collection >> nat_bit) & 1;
1715 }
1716
1717 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
1718 }
1719 else if (regnum == IA64_IP_REGNUM)
1720 {
1721 CORE_ADDR pc = 0;
1722 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1723
1724 if (addr != 0)
1725 {
1726 *lvalp = lval_memory;
1727 *addrp = addr;
1728 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1729 pc = extract_unsigned_integer (buf, 8);
1730 }
1731 else if (cache->frameless)
1732 {
1733 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1734 pc = extract_unsigned_integer (buf, 8);
1735 }
1736 pc &= ~0xf;
1737 store_unsigned_integer (valuep, 8, pc);
1738 }
1739 else if (regnum == IA64_PSR_REGNUM)
1740 {
1741 /* We don't know how to get the complete previous PSR, but we need it for
1742 the slot information when we unwind the pc (pc is formed of IP register
1743 plus slot information from PSR). To get the previous slot information,
1744 we mask it off the return address. */
1745 ULONGEST slot_num = 0;
1746 CORE_ADDR pc= 0;
1747 CORE_ADDR psr = 0;
1748 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1749
1750 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1751 psr = extract_unsigned_integer (buf, 8);
1752
1753 if (addr != 0)
1754 {
1755 *lvalp = lval_memory;
1756 *addrp = addr;
1757 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1758 pc = extract_unsigned_integer (buf, 8);
1759 }
1760 else if (cache->frameless)
1761 {
1762 CORE_ADDR pc;
1763 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1764 pc = extract_unsigned_integer (buf, 8);
1765 }
1766 psr &= ~(3LL << 41);
1767 slot_num = pc & 0x3LL;
1768 psr |= (CORE_ADDR)slot_num << 41;
1769 store_unsigned_integer (valuep, 8, psr);
1770 }
1771 else if (regnum == IA64_BR0_REGNUM)
1772 {
1773 CORE_ADDR br0 = 0;
1774 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1775 if (addr != 0)
1776 {
1777 *lvalp = lval_memory;
1778 *addrp = addr;
1779 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1780 br0 = extract_unsigned_integer (buf, 8);
1781 }
1782 store_unsigned_integer (valuep, 8, br0);
1783 }
1784 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1785 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1786 {
1787 CORE_ADDR addr = 0;
1788 if (regnum >= V32_REGNUM)
1789 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1790 addr = cache->saved_regs[regnum];
1791 if (addr != 0)
1792 {
1793 *lvalp = lval_memory;
1794 *addrp = addr;
1795 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1796 }
1797 else if (cache->frameless)
1798 {
1799 char r_valuep[MAX_REGISTER_SIZE];
1800 int r_optim;
1801 int r_realnum;
1802 enum lval_type r_lval;
1803 CORE_ADDR r_addr;
1804 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1805 CORE_ADDR addr = 0;
1806 if (regnum >= V32_REGNUM)
1807 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1808 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1809 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1810 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1811 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1812 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1813 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1814 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1815
1816 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1817 *lvalp = lval_memory;
1818 *addrp = addr;
1819 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1820 }
1821 }
1822 else
1823 {
1824 CORE_ADDR addr = 0;
1825 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1826 {
1827 /* Fetch floating point register rename base from current
1828 frame marker for this frame. */
1829 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1830
1831 /* Adjust the floating point register number to account for
1832 register rotation. */
1833 regnum = IA64_FR32_REGNUM
1834 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1835 }
1836
1837 /* If we have stored a memory address, access the register. */
1838 addr = cache->saved_regs[regnum];
1839 if (addr != 0)
1840 {
1841 *lvalp = lval_memory;
1842 *addrp = addr;
1843 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1844 }
1845 /* Otherwise, punt and get the current value of the register. */
1846 else
1847 frame_unwind_register (next_frame, regnum, valuep);
1848 }
1849
1850 if (gdbarch_debug >= 1)
1851 fprintf_unfiltered (gdb_stdlog,
1852 "regular prev register <%d> <%s> is 0x%s\n", regnum,
1853 (((unsigned) regnum <= IA64_NAT127_REGNUM)
1854 ? ia64_register_names[regnum] : "r??"),
1855 paddr_nz (extract_unsigned_integer (valuep, 8)));
1856 }
1857
1858 static const struct frame_unwind ia64_frame_unwind =
1859 {
1860 NORMAL_FRAME,
1861 &ia64_frame_this_id,
1862 &ia64_frame_prev_register
1863 };
1864
1865 static const struct frame_unwind *
1866 ia64_frame_sniffer (struct frame_info *next_frame)
1867 {
1868 return &ia64_frame_unwind;
1869 }
1870
1871 /* Signal trampolines. */
1872
1873 static void
1874 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1875 {
1876 if (SIGCONTEXT_REGISTER_ADDRESS)
1877 {
1878 int regno;
1879
1880 cache->saved_regs[IA64_VRAP_REGNUM] =
1881 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1882 cache->saved_regs[IA64_CFM_REGNUM] =
1883 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1884 cache->saved_regs[IA64_PSR_REGNUM] =
1885 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1886 cache->saved_regs[IA64_BSP_REGNUM] =
1887 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
1888 cache->saved_regs[IA64_RNAT_REGNUM] =
1889 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1890 cache->saved_regs[IA64_CCV_REGNUM] =
1891 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1892 cache->saved_regs[IA64_UNAT_REGNUM] =
1893 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1894 cache->saved_regs[IA64_FPSR_REGNUM] =
1895 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1896 cache->saved_regs[IA64_PFS_REGNUM] =
1897 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1898 cache->saved_regs[IA64_LC_REGNUM] =
1899 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1900 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1901 cache->saved_regs[regno] =
1902 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1903 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1904 cache->saved_regs[regno] =
1905 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1906 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
1907 cache->saved_regs[regno] =
1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1909 }
1910 }
1911
1912 static struct ia64_frame_cache *
1913 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1914 {
1915 struct ia64_frame_cache *cache;
1916 CORE_ADDR addr;
1917 char buf[8];
1918 int i;
1919
1920 if (*this_cache)
1921 return *this_cache;
1922
1923 cache = ia64_alloc_frame_cache ();
1924
1925 frame_unwind_register (next_frame, sp_regnum, buf);
1926 /* Note that frame size is hard-coded below. We cannot calculate it
1927 via prologue examination. */
1928 cache->base = extract_unsigned_integer (buf, 8) + 16;
1929
1930 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1931 cache->bsp = extract_unsigned_integer (buf, 8);
1932
1933 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1934 cache->cfm = extract_unsigned_integer (buf, 8);
1935 cache->sof = cache->cfm & 0x7f;
1936
1937 ia64_sigtramp_frame_init_saved_regs (cache);
1938
1939 *this_cache = cache;
1940 return cache;
1941 }
1942
1943 static void
1944 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1945 void **this_cache, struct frame_id *this_id)
1946 {
1947 struct ia64_frame_cache *cache =
1948 ia64_sigtramp_frame_cache (next_frame, this_cache);
1949
1950 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1951 if (gdbarch_debug >= 1)
1952 fprintf_unfiltered (gdb_stdlog,
1953 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1954 paddr_nz (this_id->code_addr),
1955 paddr_nz (this_id->stack_addr),
1956 paddr_nz (cache->bsp), next_frame);
1957 }
1958
1959 static void
1960 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1961 void **this_cache,
1962 int regnum, int *optimizedp,
1963 enum lval_type *lvalp, CORE_ADDR *addrp,
1964 int *realnump, void *valuep)
1965 {
1966 char dummy_valp[MAX_REGISTER_SIZE];
1967 char buf[MAX_REGISTER_SIZE];
1968
1969 struct ia64_frame_cache *cache =
1970 ia64_sigtramp_frame_cache (next_frame, this_cache);
1971
1972 gdb_assert (regnum >= 0);
1973
1974 if (!target_has_registers)
1975 error ("No registers.");
1976
1977 *optimizedp = 0;
1978 *addrp = 0;
1979 *lvalp = not_lval;
1980 *realnump = -1;
1981
1982 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1983 when valuep is not supplied. */
1984 if (!valuep)
1985 valuep = dummy_valp;
1986
1987 memset (valuep, 0, register_size (current_gdbarch, regnum));
1988
1989 if (regnum == IA64_IP_REGNUM)
1990 {
1991 CORE_ADDR pc = 0;
1992 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1993
1994 if (addr != 0)
1995 {
1996 *lvalp = lval_memory;
1997 *addrp = addr;
1998 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1999 pc = extract_unsigned_integer (buf, 8);
2000 }
2001 pc &= ~0xf;
2002 store_unsigned_integer (valuep, 8, pc);
2003 }
2004 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2005 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2006 {
2007 CORE_ADDR addr = 0;
2008 if (regnum >= V32_REGNUM)
2009 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2010 addr = cache->saved_regs[regnum];
2011 if (addr != 0)
2012 {
2013 *lvalp = lval_memory;
2014 *addrp = addr;
2015 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2016 }
2017 }
2018 else
2019 {
2020 /* All other registers not listed above. */
2021 CORE_ADDR addr = cache->saved_regs[regnum];
2022 if (addr != 0)
2023 {
2024 *lvalp = lval_memory;
2025 *addrp = addr;
2026 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2027 }
2028 }
2029
2030 if (gdbarch_debug >= 1)
2031 fprintf_unfiltered (gdb_stdlog,
2032 "sigtramp prev register <%s> is 0x%s\n",
2033 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2034 ? ia64_register_names[regnum] : "r??"),
2035 paddr_nz (extract_unsigned_integer (valuep, 8)));
2036 }
2037
2038 static const struct frame_unwind ia64_sigtramp_frame_unwind =
2039 {
2040 SIGTRAMP_FRAME,
2041 ia64_sigtramp_frame_this_id,
2042 ia64_sigtramp_frame_prev_register
2043 };
2044
2045 static const struct frame_unwind *
2046 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2047 {
2048 char *name;
2049 CORE_ADDR pc = frame_pc_unwind (next_frame);
2050
2051 find_pc_partial_function (pc, &name, NULL, NULL);
2052 if (legacy_pc_in_sigtramp (pc, name))
2053 return &ia64_sigtramp_frame_unwind;
2054
2055 return NULL;
2056 }
2057 \f
2058
2059 static CORE_ADDR
2060 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2061 {
2062 struct ia64_frame_cache *cache =
2063 ia64_frame_cache (next_frame, this_cache);
2064
2065 return cache->base;
2066 }
2067
2068 static const struct frame_base ia64_frame_base =
2069 {
2070 &ia64_frame_unwind,
2071 ia64_frame_base_address,
2072 ia64_frame_base_address,
2073 ia64_frame_base_address
2074 };
2075
2076 #ifdef HAVE_LIBUNWIND_IA64_H
2077
2078 struct ia64_unwind_table_entry
2079 {
2080 unw_word_t start_offset;
2081 unw_word_t end_offset;
2082 unw_word_t info_offset;
2083 };
2084
2085 static __inline__ uint64_t
2086 ia64_rse_slot_num (uint64_t addr)
2087 {
2088 return (addr >> 3) & 0x3f;
2089 }
2090
2091 /* Skip over a designated number of registers in the backing
2092 store, remembering every 64th position is for NAT. */
2093 static __inline__ uint64_t
2094 ia64_rse_skip_regs (uint64_t addr, long num_regs)
2095 {
2096 long delta = ia64_rse_slot_num(addr) + num_regs;
2097
2098 if (num_regs < 0)
2099 delta -= 0x3e;
2100 return addr + ((num_regs + delta/0x3f) << 3);
2101 }
2102
2103 /* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2104 number to a libunwind register number. */
2105 static int
2106 ia64_gdb2uw_regnum (int regnum)
2107 {
2108 if (regnum == sp_regnum)
2109 return UNW_IA64_SP;
2110 else if (regnum == IA64_BSP_REGNUM)
2111 return UNW_IA64_BSP;
2112 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2113 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2114 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2115 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2116 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2117 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2118 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2119 return -1;
2120 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2121 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2122 else if (regnum == IA64_PR_REGNUM)
2123 return UNW_IA64_PR;
2124 else if (regnum == IA64_IP_REGNUM)
2125 return UNW_REG_IP;
2126 else if (regnum == IA64_CFM_REGNUM)
2127 return UNW_IA64_CFM;
2128 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2129 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2130 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2131 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2132 else
2133 return -1;
2134 }
2135
2136 /* Gdb libunwind-frame callback function to convert from a libunwind register
2137 number to a ia64 gdb register number. */
2138 static int
2139 ia64_uw2gdb_regnum (int uw_regnum)
2140 {
2141 if (uw_regnum == UNW_IA64_SP)
2142 return sp_regnum;
2143 else if (uw_regnum == UNW_IA64_BSP)
2144 return IA64_BSP_REGNUM;
2145 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2146 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2147 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2148 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2149 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2150 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2151 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2152 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2153 else if (uw_regnum == UNW_IA64_PR)
2154 return IA64_PR_REGNUM;
2155 else if (uw_regnum == UNW_REG_IP)
2156 return IA64_IP_REGNUM;
2157 else if (uw_regnum == UNW_IA64_CFM)
2158 return IA64_CFM_REGNUM;
2159 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2160 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2161 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2162 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2163 else
2164 return -1;
2165 }
2166
2167 /* Gdb libunwind-frame callback function to reveal if register is a float
2168 register or not. */
2169 static int
2170 ia64_is_fpreg (int uw_regnum)
2171 {
2172 return unw_is_fpreg (uw_regnum);
2173 }
2174
2175 /* Libunwind callback accessor function for general registers. */
2176 static int
2177 ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2178 int write, void *arg)
2179 {
2180 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2181 unw_word_t bsp, sof, sol, cfm, psr, ip;
2182 struct frame_info *next_frame = arg;
2183 long new_sof, old_sof;
2184 char buf[MAX_REGISTER_SIZE];
2185
2186 if (write)
2187 {
2188 if (regnum < 0)
2189 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2190 return 0;
2191
2192 switch (uw_regnum)
2193 {
2194 case UNW_REG_IP:
2195 ia64_write_pc (*val, inferior_ptid);
2196 break;
2197
2198 case UNW_IA64_AR_BSPSTORE:
2199 write_register (IA64_BSP_REGNUM, *val);
2200 break;
2201
2202 case UNW_IA64_AR_BSP:
2203 case UNW_IA64_BSP:
2204 /* Account for the fact that ptrace() expects bsp to point
2205 after the current register frame. */
2206 cfm = read_register (IA64_CFM_REGNUM);
2207 sof = (cfm & 0x7f);
2208 bsp = ia64_rse_skip_regs (*val, sof);
2209 write_register (IA64_BSP_REGNUM, bsp);
2210 break;
2211
2212 case UNW_IA64_CFM:
2213 /* If we change CFM, we need to adjust ptrace's notion of
2214 bsp accordingly, so that the real bsp remains
2215 unchanged. */
2216 bsp = read_register (IA64_BSP_REGNUM);
2217 cfm = read_register (IA64_CFM_REGNUM);
2218 old_sof = (cfm & 0x7f);
2219 new_sof = (*val & 0x7f);
2220 if (old_sof != new_sof)
2221 {
2222 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2223 write_register (IA64_BSP_REGNUM, bsp);
2224 }
2225 write_register (IA64_CFM_REGNUM, *val);
2226 break;
2227
2228 default:
2229 write_register (regnum, *val);
2230 break;
2231 }
2232 if (gdbarch_debug >= 1)
2233 fprintf_unfiltered (gdb_stdlog,
2234 " access_reg: to cache: %4s=0x%s\n",
2235 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2236 ? ia64_register_names[regnum] : "r??"),
2237 paddr_nz (*val));
2238 }
2239 else
2240 {
2241 switch (uw_regnum)
2242 {
2243 case UNW_REG_IP:
2244 /* Libunwind expects to see the pc value which means the slot number
2245 from the psr must be merged with the ip word address. */
2246 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2247 ip = extract_unsigned_integer (buf, 8);
2248 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2249 psr = extract_unsigned_integer (buf, 8);
2250 *val = ip | ((psr >> 41) & 0x3);
2251 break;
2252
2253 case UNW_IA64_AR_BSP:
2254 /* Libunwind expects to see the beginning of the current register
2255 frame so we must account for the fact that ptrace() will return a value
2256 for bsp that points *after* the current register frame. */
2257 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2258 bsp = extract_unsigned_integer (buf, 8);
2259 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2260 cfm = extract_unsigned_integer (buf, 8);
2261 sof = (cfm & 0x7f);
2262 *val = ia64_rse_skip_regs (bsp, -sof);
2263 break;
2264
2265 case UNW_IA64_AR_BSPSTORE:
2266 /* Libunwind wants bspstore to be after the current register frame.
2267 This is what ptrace() and gdb treats as the regular bsp value. */
2268 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2269 *val = extract_unsigned_integer (buf, 8);
2270 break;
2271
2272 default:
2273 /* For all other registers, just unwind the value directly. */
2274 frame_unwind_register (next_frame, regnum, buf);
2275 *val = extract_unsigned_integer (buf, 8);
2276 break;
2277 }
2278
2279 if (gdbarch_debug >= 1)
2280 fprintf_unfiltered (gdb_stdlog,
2281 " access_reg: from cache: %4s=0x%s\n",
2282 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2283 ? ia64_register_names[regnum] : "r??"),
2284 paddr_nz (*val));
2285 }
2286 return 0;
2287 }
2288
2289 /* Libunwind callback accessor function for floating-point registers. */
2290 static int
2291 ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2292 int write, void *arg)
2293 {
2294 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2295
2296 if (write)
2297 regcache_cooked_write (current_regcache, regnum, (char *) val);
2298 else
2299 regcache_cooked_read (current_regcache, regnum, (char *) val);
2300 return 0;
2301 }
2302
2303 /* Libunwind callback accessor function for accessing memory. */
2304 static int
2305 ia64_access_mem (unw_addr_space_t as,
2306 unw_word_t addr, unw_word_t *val,
2307 int write, void *arg)
2308 {
2309 /* XXX do we need to normalize byte-order here? */
2310 if (write)
2311 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2312 else
2313 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2314 }
2315
2316 /* Call low-level function to access the kernel unwind table. */
2317 static int
2318 getunwind_table (void *buf, size_t len)
2319 {
2320 LONGEST x;
2321 x = target_read_partial (&current_target, TARGET_OBJECT_UNWIND_TABLE, NULL,
2322 buf, 0, len);
2323
2324 return (int)x;
2325 }
2326
2327 /* Get the kernel unwind table. */
2328 static int
2329 get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2330 {
2331 size_t size;
2332 struct ia64_table_entry
2333 {
2334 uint64_t start_offset;
2335 uint64_t end_offset;
2336 uint64_t info_offset;
2337 };
2338 static struct ia64_table_entry *ktab = NULL, *etab;
2339
2340 if (!ktab)
2341 {
2342 size = getunwind_table (NULL, 0);
2343 if ((int)size < 0)
2344 return -UNW_ENOINFO;
2345 ktab = xmalloc (size);
2346 getunwind_table (ktab, size);
2347
2348 /* Determine length of kernel's unwind table and relocate
2349 it's entries. */
2350 for (etab = ktab; etab->start_offset; ++etab)
2351 etab->info_offset += (uint64_t) ktab;
2352 }
2353
2354 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2355 return -UNW_ENOINFO;
2356
2357 di->format = UNW_INFO_FORMAT_TABLE;
2358 di->gp = 0;
2359 di->start_ip = ktab[0].start_offset;
2360 di->end_ip = etab[-1].end_offset;
2361 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2362 di->u.ti.segbase = 0;
2363 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2364 di->u.ti.table_data = (unw_word_t *) ktab;
2365
2366 if (gdbarch_debug >= 1)
2367 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
2368 "segbase=0x%s, length=%s, gp=0x%s\n",
2369 (char *) di->u.ti.name_ptr,
2370 paddr_nz (di->u.ti.segbase),
2371 paddr_u (di->u.ti.table_len),
2372 paddr_nz (di->gp));
2373 return 0;
2374 }
2375
2376 /* Find the unwind table entry for a specified address. */
2377 static int
2378 ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2379 unw_dyn_info_t *dip, void **buf)
2380 {
2381 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2382 Elf_Internal_Ehdr *ehdr;
2383 unw_word_t segbase = 0;
2384 CORE_ADDR load_base;
2385 bfd *bfd;
2386 int i;
2387
2388 bfd = objfile->obfd;
2389
2390 ehdr = elf_tdata (bfd)->elf_header;
2391 phdr = elf_tdata (bfd)->phdr;
2392
2393 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2394
2395 for (i = 0; i < ehdr->e_phnum; ++i)
2396 {
2397 switch (phdr[i].p_type)
2398 {
2399 case PT_LOAD:
2400 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2401 < phdr[i].p_memsz)
2402 p_text = phdr + i;
2403 break;
2404
2405 case PT_IA_64_UNWIND:
2406 p_unwind = phdr + i;
2407 break;
2408
2409 default:
2410 break;
2411 }
2412 }
2413
2414 if (!p_text || !p_unwind
2415 /* Verify that the segment that contains the IP also contains
2416 the static unwind table. If not, we are dealing with
2417 runtime-generated code, for which we have no info here. */
2418 || (p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2419 return -UNW_ENOINFO;
2420
2421 segbase = p_text->p_vaddr + load_base;
2422
2423 dip->start_ip = segbase;
2424 dip->end_ip = dip->start_ip + p_text->p_memsz;
2425 dip->gp = FIND_GLOBAL_POINTER (ip);
2426 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2427 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2428 dip->u.rti.segbase = segbase;
2429 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2430 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
2431
2432 return 0;
2433 }
2434
2435 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2436 static int
2437 ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2438 int need_unwind_info, void *arg)
2439 {
2440 struct obj_section *sec = find_pc_section (ip);
2441 unw_dyn_info_t di;
2442 int ret;
2443 void *buf = NULL;
2444
2445 if (!sec)
2446 {
2447 /* XXX This only works if the host and the target architecture are
2448 both ia64 and if the have (more or less) the same kernel
2449 version. */
2450 if (get_kernel_table (ip, &di) < 0)
2451 return -UNW_ENOINFO;
2452
2453 if (gdbarch_debug >= 1)
2454 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2455 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2456 "length=%s,data=0x%s)\n",
2457 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2458 paddr_nz (di.u.ti.segbase),
2459 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2460 paddr_nz (di.gp),
2461 paddr_u (di.u.ti.table_len),
2462 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
2463 }
2464 else
2465 {
2466 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2467 if (ret < 0)
2468 return ret;
2469
2470 if (gdbarch_debug >= 1)
2471 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2472 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2473 "length=%s,data=0x%s)\n",
2474 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2475 paddr_nz (di.u.rti.segbase),
2476 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2477 paddr_nz (di.gp),
2478 paddr_u (di.u.rti.table_len),
2479 paddr_nz (di.u.rti.table_data));
2480 }
2481
2482 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2483 arg);
2484
2485 /* We no longer need the dyn info storage so free it. */
2486 xfree (buf);
2487
2488 return ret;
2489 }
2490
2491 /* Libunwind callback accessor function for cleanup. */
2492 static void
2493 ia64_put_unwind_info (unw_addr_space_t as,
2494 unw_proc_info_t *pip, void *arg)
2495 {
2496 /* Nothing required for now. */
2497 }
2498
2499 /* Libunwind callback accessor function to get head of the dynamic
2500 unwind-info registration list. */
2501 static int
2502 ia64_get_dyn_info_list (unw_addr_space_t as,
2503 unw_word_t *dilap, void *arg)
2504 {
2505 struct obj_section *text_sec;
2506 struct objfile *objfile;
2507 unw_word_t ip, addr;
2508 unw_dyn_info_t di;
2509 int ret;
2510
2511 if (!libunwind_is_initialized ())
2512 return -UNW_ENOINFO;
2513
2514 for (objfile = object_files; objfile; objfile = objfile->next)
2515 {
2516 void *buf = NULL;
2517
2518 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2519 ip = text_sec->addr;
2520 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2521 if (ret >= 0)
2522 {
2523 addr = libunwind_find_dyn_list (as, &di, arg);
2524 /* We no longer need the dyn info storage so free it. */
2525 xfree (buf);
2526
2527 if (addr)
2528 {
2529 if (gdbarch_debug >= 1)
2530 fprintf_unfiltered (gdb_stdlog,
2531 "dynamic unwind table in objfile %s "
2532 "at 0x%s (gp=0x%s)\n",
2533 bfd_get_filename (objfile->obfd),
2534 paddr_nz (addr), paddr_nz (di.gp));
2535 *dilap = addr;
2536 return 0;
2537 }
2538 }
2539 }
2540 return -UNW_ENOINFO;
2541 }
2542
2543
2544 /* Frame interface functions for libunwind. */
2545
2546 static void
2547 ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
2548 struct frame_id *this_id)
2549 {
2550 char buf[8];
2551 CORE_ADDR bsp;
2552 struct frame_id id;
2553
2554 libunwind_frame_this_id (next_frame, this_cache, &id);
2555
2556 /* We must add the bsp as the special address for frame comparison purposes. */
2557 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2558 bsp = extract_unsigned_integer (buf, 8);
2559
2560 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2561
2562 if (gdbarch_debug >= 1)
2563 fprintf_unfiltered (gdb_stdlog,
2564 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2565 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2566 paddr_nz (bsp), next_frame);
2567 }
2568
2569 static void
2570 ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2571 void **this_cache,
2572 int regnum, int *optimizedp,
2573 enum lval_type *lvalp, CORE_ADDR *addrp,
2574 int *realnump, void *valuep)
2575 {
2576 int reg = regnum;
2577
2578 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2579 reg = IA64_PR_REGNUM;
2580 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2581 reg = IA64_UNAT_REGNUM;
2582
2583 /* Let libunwind do most of the work. */
2584 libunwind_frame_prev_register (next_frame, this_cache, reg,
2585 optimizedp, lvalp, addrp, realnump, valuep);
2586
2587 /* No more to do if the value is not supposed to be supplied. */
2588 if (!valuep)
2589 return;
2590
2591 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2592 {
2593 ULONGEST prN_val;
2594
2595 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2596 {
2597 int rrb_pr = 0;
2598 ULONGEST cfm;
2599 unsigned char buf[MAX_REGISTER_SIZE];
2600
2601 /* Fetch predicate register rename base from current frame
2602 marker for this frame. */
2603 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2604 cfm = extract_unsigned_integer (buf, 8);
2605 rrb_pr = (cfm >> 32) & 0x3f;
2606
2607 /* Adjust the register number to account for register rotation. */
2608 regnum = VP16_REGNUM
2609 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2610 }
2611 prN_val = extract_bit_field ((unsigned char *) valuep,
2612 regnum - VP0_REGNUM, 1);
2613 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2614 }
2615 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2616 {
2617 ULONGEST unatN_val;
2618
2619 unatN_val = extract_bit_field ((unsigned char *) valuep,
2620 regnum - IA64_NAT0_REGNUM, 1);
2621 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2622 unatN_val);
2623 }
2624 else if (regnum == IA64_BSP_REGNUM)
2625 {
2626 char cfm_valuep[MAX_REGISTER_SIZE];
2627 int cfm_optim;
2628 int cfm_realnum;
2629 enum lval_type cfm_lval;
2630 CORE_ADDR cfm_addr;
2631 CORE_ADDR bsp, prev_cfm, prev_bsp;
2632
2633 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2634 This corresponds to what the hardware bsp register will be if we pop the frame
2635 back which is why we might have been called. We know that libunwind will pass us back
2636 the beginning of the current frame so we should just add sof to it. */
2637 prev_bsp = extract_unsigned_integer (valuep, 8);
2638 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2639 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2640 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2641 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2642
2643 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2644 prev_bsp);
2645 }
2646
2647 if (gdbarch_debug >= 1)
2648 fprintf_unfiltered (gdb_stdlog,
2649 "libunwind prev register <%s> is 0x%s\n",
2650 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2651 ? ia64_register_names[regnum] : "r??"),
2652 paddr_nz (extract_unsigned_integer (valuep, 8)));
2653 }
2654
2655 static const struct frame_unwind ia64_libunwind_frame_unwind =
2656 {
2657 NORMAL_FRAME,
2658 ia64_libunwind_frame_this_id,
2659 ia64_libunwind_frame_prev_register
2660 };
2661
2662 static const struct frame_unwind *
2663 ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2664 {
2665 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2666 return &ia64_libunwind_frame_unwind;
2667
2668 return NULL;
2669 }
2670
2671 /* Set of libunwind callback acccessor functions. */
2672 static unw_accessors_t ia64_unw_accessors =
2673 {
2674 ia64_find_proc_info_x,
2675 ia64_put_unwind_info,
2676 ia64_get_dyn_info_list,
2677 ia64_access_mem,
2678 ia64_access_reg,
2679 ia64_access_fpreg,
2680 /* resume */
2681 /* get_proc_name */
2682 };
2683
2684 /* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2685 static struct libunwind_descr ia64_libunwind_descr =
2686 {
2687 ia64_gdb2uw_regnum,
2688 ia64_uw2gdb_regnum,
2689 ia64_is_fpreg,
2690 &ia64_unw_accessors,
2691 };
2692
2693 #endif /* HAVE_LIBUNWIND_IA64_H */
2694
2695 /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2696 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2697 is the type (which is known to be struct, union or array). */
2698 int
2699 ia64_use_struct_convention (int gcc_p, struct type *type)
2700 {
2701 struct type *float_elt_type;
2702
2703 /* HFAs are structures (or arrays) consisting entirely of floating
2704 point values of the same length. Up to 8 of these are returned
2705 in registers. Don't use the struct convention when this is the
2706 case. */
2707 float_elt_type = is_float_or_hfa_type (type);
2708 if (float_elt_type != NULL
2709 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2710 return 0;
2711
2712 /* Other structs of length 32 or less are returned in r8-r11.
2713 Don't use the struct convention for those either. */
2714 return TYPE_LENGTH (type) > 32;
2715 }
2716
2717 void
2718 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2719 {
2720 struct type *float_elt_type;
2721
2722 float_elt_type = is_float_or_hfa_type (type);
2723 if (float_elt_type != NULL)
2724 {
2725 char from[MAX_REGISTER_SIZE];
2726 int offset = 0;
2727 int regnum = IA64_FR8_REGNUM;
2728 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2729
2730 while (n-- > 0)
2731 {
2732 regcache_cooked_read (regcache, regnum, from);
2733 convert_typed_floating (from, builtin_type_ia64_ext,
2734 (char *)valbuf + offset, float_elt_type);
2735 offset += TYPE_LENGTH (float_elt_type);
2736 regnum++;
2737 }
2738 }
2739 else
2740 {
2741 ULONGEST val;
2742 int offset = 0;
2743 int regnum = IA64_GR8_REGNUM;
2744 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2745 int n = TYPE_LENGTH (type) / reglen;
2746 int m = TYPE_LENGTH (type) % reglen;
2747
2748 while (n-- > 0)
2749 {
2750 ULONGEST val;
2751 regcache_cooked_read_unsigned (regcache, regnum, &val);
2752 memcpy ((char *)valbuf + offset, &val, reglen);
2753 offset += reglen;
2754 regnum++;
2755 }
2756
2757 if (m)
2758 {
2759 regcache_cooked_read_unsigned (regcache, regnum, &val);
2760 memcpy ((char *)valbuf + offset, &val, m);
2761 }
2762 }
2763 }
2764
2765 CORE_ADDR
2766 ia64_extract_struct_value_address (struct regcache *regcache)
2767 {
2768 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2769 return 0;
2770 }
2771
2772
2773 static int
2774 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2775 {
2776 switch (TYPE_CODE (t))
2777 {
2778 case TYPE_CODE_FLT:
2779 if (*etp)
2780 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2781 else
2782 {
2783 *etp = t;
2784 return 1;
2785 }
2786 break;
2787 case TYPE_CODE_ARRAY:
2788 return
2789 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2790 etp);
2791 break;
2792 case TYPE_CODE_STRUCT:
2793 {
2794 int i;
2795
2796 for (i = 0; i < TYPE_NFIELDS (t); i++)
2797 if (!is_float_or_hfa_type_recurse
2798 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2799 return 0;
2800 return 1;
2801 }
2802 break;
2803 default:
2804 return 0;
2805 break;
2806 }
2807 }
2808
2809 /* Determine if the given type is one of the floating point types or
2810 and HFA (which is a struct, array, or combination thereof whose
2811 bottom-most elements are all of the same floating point type). */
2812
2813 static struct type *
2814 is_float_or_hfa_type (struct type *t)
2815 {
2816 struct type *et = 0;
2817
2818 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2819 }
2820
2821
2822 /* Return 1 if the alignment of T is such that the next even slot
2823 should be used. Return 0, if the next available slot should
2824 be used. (See section 8.5.1 of the IA-64 Software Conventions
2825 and Runtime manual). */
2826
2827 static int
2828 slot_alignment_is_next_even (struct type *t)
2829 {
2830 switch (TYPE_CODE (t))
2831 {
2832 case TYPE_CODE_INT:
2833 case TYPE_CODE_FLT:
2834 if (TYPE_LENGTH (t) > 8)
2835 return 1;
2836 else
2837 return 0;
2838 case TYPE_CODE_ARRAY:
2839 return
2840 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2841 case TYPE_CODE_STRUCT:
2842 {
2843 int i;
2844
2845 for (i = 0; i < TYPE_NFIELDS (t); i++)
2846 if (slot_alignment_is_next_even
2847 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2848 return 1;
2849 return 0;
2850 }
2851 default:
2852 return 0;
2853 }
2854 }
2855
2856 /* Attempt to find (and return) the global pointer for the given
2857 function.
2858
2859 This is a rather nasty bit of code searchs for the .dynamic section
2860 in the objfile corresponding to the pc of the function we're trying
2861 to call. Once it finds the addresses at which the .dynamic section
2862 lives in the child process, it scans the Elf64_Dyn entries for a
2863 DT_PLTGOT tag. If it finds one of these, the corresponding
2864 d_un.d_ptr value is the global pointer. */
2865
2866 static CORE_ADDR
2867 generic_elf_find_global_pointer (CORE_ADDR faddr)
2868 {
2869 struct obj_section *faddr_sect;
2870
2871 faddr_sect = find_pc_section (faddr);
2872 if (faddr_sect != NULL)
2873 {
2874 struct obj_section *osect;
2875
2876 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2877 {
2878 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2879 break;
2880 }
2881
2882 if (osect < faddr_sect->objfile->sections_end)
2883 {
2884 CORE_ADDR addr;
2885
2886 addr = osect->addr;
2887 while (addr < osect->endaddr)
2888 {
2889 int status;
2890 LONGEST tag;
2891 char buf[8];
2892
2893 status = target_read_memory (addr, buf, sizeof (buf));
2894 if (status != 0)
2895 break;
2896 tag = extract_signed_integer (buf, sizeof (buf));
2897
2898 if (tag == DT_PLTGOT)
2899 {
2900 CORE_ADDR global_pointer;
2901
2902 status = target_read_memory (addr + 8, buf, sizeof (buf));
2903 if (status != 0)
2904 break;
2905 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2906
2907 /* The payoff... */
2908 return global_pointer;
2909 }
2910
2911 if (tag == DT_NULL)
2912 break;
2913
2914 addr += 16;
2915 }
2916 }
2917 }
2918 return 0;
2919 }
2920
2921 /* Given a function's address, attempt to find (and return) the
2922 corresponding (canonical) function descriptor. Return 0 if
2923 not found. */
2924 static CORE_ADDR
2925 find_extant_func_descr (CORE_ADDR faddr)
2926 {
2927 struct obj_section *faddr_sect;
2928
2929 /* Return early if faddr is already a function descriptor. */
2930 faddr_sect = find_pc_section (faddr);
2931 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2932 return faddr;
2933
2934 if (faddr_sect != NULL)
2935 {
2936 struct obj_section *osect;
2937 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2938 {
2939 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2940 break;
2941 }
2942
2943 if (osect < faddr_sect->objfile->sections_end)
2944 {
2945 CORE_ADDR addr;
2946
2947 addr = osect->addr;
2948 while (addr < osect->endaddr)
2949 {
2950 int status;
2951 LONGEST faddr2;
2952 char buf[8];
2953
2954 status = target_read_memory (addr, buf, sizeof (buf));
2955 if (status != 0)
2956 break;
2957 faddr2 = extract_signed_integer (buf, sizeof (buf));
2958
2959 if (faddr == faddr2)
2960 return addr;
2961
2962 addr += 16;
2963 }
2964 }
2965 }
2966 return 0;
2967 }
2968
2969 /* Attempt to find a function descriptor corresponding to the
2970 given address. If none is found, construct one on the
2971 stack using the address at fdaptr. */
2972
2973 static CORE_ADDR
2974 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2975 {
2976 CORE_ADDR fdesc;
2977
2978 fdesc = find_extant_func_descr (faddr);
2979
2980 if (fdesc == 0)
2981 {
2982 CORE_ADDR global_pointer;
2983 char buf[16];
2984
2985 fdesc = *fdaptr;
2986 *fdaptr += 16;
2987
2988 global_pointer = FIND_GLOBAL_POINTER (faddr);
2989
2990 if (global_pointer == 0)
2991 global_pointer = read_register (IA64_GR1_REGNUM);
2992
2993 store_unsigned_integer (buf, 8, faddr);
2994 store_unsigned_integer (buf + 8, 8, global_pointer);
2995
2996 write_memory (fdesc, buf, 16);
2997 }
2998
2999 return fdesc;
3000 }
3001
3002 /* Use the following routine when printing out function pointers
3003 so the user can see the function address rather than just the
3004 function descriptor. */
3005 static CORE_ADDR
3006 ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3007 struct target_ops *targ)
3008 {
3009 struct obj_section *s;
3010
3011 s = find_pc_section (addr);
3012
3013 /* check if ADDR points to a function descriptor. */
3014 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3015 return read_memory_unsigned_integer (addr, 8);
3016
3017 return addr;
3018 }
3019
3020 static CORE_ADDR
3021 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3022 {
3023 return sp & ~0xfLL;
3024 }
3025
3026 static CORE_ADDR
3027 ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3028 struct regcache *regcache, CORE_ADDR bp_addr,
3029 int nargs, struct value **args, CORE_ADDR sp,
3030 int struct_return, CORE_ADDR struct_addr)
3031 {
3032 int argno;
3033 struct value *arg;
3034 struct type *type;
3035 int len, argoffset;
3036 int nslots, rseslots, memslots, slotnum, nfuncargs;
3037 int floatreg;
3038 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
3039 CORE_ADDR func_addr = find_function_addr (function, NULL);
3040
3041 nslots = 0;
3042 nfuncargs = 0;
3043 /* Count the number of slots needed for the arguments. */
3044 for (argno = 0; argno < nargs; argno++)
3045 {
3046 arg = args[argno];
3047 type = check_typedef (VALUE_TYPE (arg));
3048 len = TYPE_LENGTH (type);
3049
3050 if ((nslots & 1) && slot_alignment_is_next_even (type))
3051 nslots++;
3052
3053 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3054 nfuncargs++;
3055
3056 nslots += (len + 7) / 8;
3057 }
3058
3059 /* Divvy up the slots between the RSE and the memory stack. */
3060 rseslots = (nslots > 8) ? 8 : nslots;
3061 memslots = nslots - rseslots;
3062
3063 /* Allocate a new RSE frame. */
3064 cfm = read_register (IA64_CFM_REGNUM);
3065
3066 bsp = read_register (IA64_BSP_REGNUM);
3067 new_bsp = rse_address_add (bsp, rseslots);
3068 write_register (IA64_BSP_REGNUM, new_bsp);
3069
3070 pfs = read_register (IA64_PFS_REGNUM);
3071 pfs &= 0xc000000000000000LL;
3072 pfs |= (cfm & 0xffffffffffffLL);
3073 write_register (IA64_PFS_REGNUM, pfs);
3074
3075 cfm &= 0xc000000000000000LL;
3076 cfm |= rseslots;
3077 write_register (IA64_CFM_REGNUM, cfm);
3078
3079 /* We will attempt to find function descriptors in the .opd segment,
3080 but if we can't we'll construct them ourselves. That being the
3081 case, we'll need to reserve space on the stack for them. */
3082 funcdescaddr = sp - nfuncargs * 16;
3083 funcdescaddr &= ~0xfLL;
3084
3085 /* Adjust the stack pointer to it's new value. The calling conventions
3086 require us to have 16 bytes of scratch, plus whatever space is
3087 necessary for the memory slots and our function descriptors. */
3088 sp = sp - 16 - (memslots + nfuncargs) * 8;
3089 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
3090
3091 /* Place the arguments where they belong. The arguments will be
3092 either placed in the RSE backing store or on the memory stack.
3093 In addition, floating point arguments or HFAs are placed in
3094 floating point registers. */
3095 slotnum = 0;
3096 floatreg = IA64_FR8_REGNUM;
3097 for (argno = 0; argno < nargs; argno++)
3098 {
3099 struct type *float_elt_type;
3100
3101 arg = args[argno];
3102 type = check_typedef (VALUE_TYPE (arg));
3103 len = TYPE_LENGTH (type);
3104
3105 /* Special handling for function parameters. */
3106 if (len == 8
3107 && TYPE_CODE (type) == TYPE_CODE_PTR
3108 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3109 {
3110 char val_buf[8];
3111
3112 store_unsigned_integer (val_buf, 8,
3113 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
3114 &funcdescaddr));
3115 if (slotnum < rseslots)
3116 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3117 else
3118 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3119 slotnum++;
3120 continue;
3121 }
3122
3123 /* Normal slots. */
3124
3125 /* Skip odd slot if necessary... */
3126 if ((slotnum & 1) && slot_alignment_is_next_even (type))
3127 slotnum++;
3128
3129 argoffset = 0;
3130 while (len > 0)
3131 {
3132 char val_buf[8];
3133
3134 memset (val_buf, 0, 8);
3135 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
3136
3137 if (slotnum < rseslots)
3138 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3139 else
3140 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3141
3142 argoffset += 8;
3143 len -= 8;
3144 slotnum++;
3145 }
3146
3147 /* Handle floating point types (including HFAs). */
3148 float_elt_type = is_float_or_hfa_type (type);
3149 if (float_elt_type != NULL)
3150 {
3151 argoffset = 0;
3152 len = TYPE_LENGTH (type);
3153 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3154 {
3155 char to[MAX_REGISTER_SIZE];
3156 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
3157 to, builtin_type_ia64_ext);
3158 regcache_cooked_write (regcache, floatreg, (void *)to);
3159 floatreg++;
3160 argoffset += TYPE_LENGTH (float_elt_type);
3161 len -= TYPE_LENGTH (float_elt_type);
3162 }
3163 }
3164 }
3165
3166 /* Store the struct return value in r8 if necessary. */
3167 if (struct_return)
3168 {
3169 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
3170 }
3171
3172 global_pointer = FIND_GLOBAL_POINTER (func_addr);
3173
3174 if (global_pointer != 0)
3175 write_register (IA64_GR1_REGNUM, global_pointer);
3176
3177 write_register (IA64_BR0_REGNUM, bp_addr);
3178
3179 write_register (sp_regnum, sp);
3180
3181 return sp;
3182 }
3183
3184 static struct frame_id
3185 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
3186 {
3187 char buf[8];
3188 CORE_ADDR sp, bsp;
3189
3190 frame_unwind_register (next_frame, sp_regnum, buf);
3191 sp = extract_unsigned_integer (buf, 8);
3192
3193 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3194 bsp = extract_unsigned_integer (buf, 8);
3195
3196 if (gdbarch_debug >= 1)
3197 fprintf_unfiltered (gdb_stdlog,
3198 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3199 paddr_nz (frame_pc_unwind (next_frame)),
3200 paddr_nz (sp), paddr_nz (bsp));
3201
3202 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
3203 }
3204
3205 static CORE_ADDR
3206 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3207 {
3208 char buf[8];
3209 CORE_ADDR ip, psr, pc;
3210
3211 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3212 ip = extract_unsigned_integer (buf, 8);
3213 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3214 psr = extract_unsigned_integer (buf, 8);
3215
3216 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3217 return pc;
3218 }
3219
3220 static void
3221 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
3222 {
3223 if (TYPE_CODE (type) == TYPE_CODE_FLT)
3224 {
3225 char to[MAX_REGISTER_SIZE];
3226 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3227 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3228 target_store_registers (IA64_FR8_REGNUM);
3229 }
3230 else
3231 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
3232 }
3233
3234 static void
3235 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3236 struct regcache *regcache,
3237 CORE_ADDR memaddr, int nr_bytes,
3238 CORE_ADDR *targ_addr, int *targ_len)
3239 {
3240 *targ_addr = memaddr;
3241 *targ_len = nr_bytes;
3242 }
3243
3244 static int
3245 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3246 {
3247 info->bytes_per_line = SLOT_MULTIPLIER;
3248 return print_insn_ia64 (memaddr, info);
3249 }
3250
3251 static struct gdbarch *
3252 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3253 {
3254 struct gdbarch *gdbarch;
3255 struct gdbarch_tdep *tdep;
3256
3257 /* If there is already a candidate, use it. */
3258 arches = gdbarch_list_lookup_by_info (arches, &info);
3259 if (arches != NULL)
3260 return arches->gdbarch;
3261
3262 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3263 gdbarch = gdbarch_alloc (&info, tdep);
3264
3265 /* Set the method of obtaining the sigcontext addresses at which
3266 registers are saved. The method of checking to see if
3267 native_find_global_pointer is nonzero to indicate that we're
3268 on AIX is kind of hokey, but I can't think of a better way
3269 to do it. */
3270 if (info.osabi == GDB_OSABI_LINUX)
3271 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
3272 else if (native_find_global_pointer != 0)
3273 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
3274 else
3275 tdep->sigcontext_register_address = 0;
3276
3277 /* We know that GNU/Linux won't have to resort to the
3278 native_find_global_pointer hackery. But that's the only one we
3279 know about so far, so if native_find_global_pointer is set to
3280 something non-zero, then use it. Otherwise fall back to using
3281 generic_elf_find_global_pointer. This arrangement should (in
3282 theory) allow us to cross debug GNU/Linux binaries from an AIX
3283 machine. */
3284 if (info.osabi == GDB_OSABI_LINUX)
3285 tdep->find_global_pointer = generic_elf_find_global_pointer;
3286 else if (native_find_global_pointer != 0)
3287 tdep->find_global_pointer = native_find_global_pointer;
3288 else
3289 tdep->find_global_pointer = generic_elf_find_global_pointer;
3290
3291 /* Define the ia64 floating-point format to gdb. */
3292 builtin_type_ia64_ext =
3293 init_type (TYPE_CODE_FLT, 128 / 8,
3294 0, "builtin_type_ia64_ext", NULL);
3295 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3296
3297 /* According to the ia64 specs, instructions that store long double
3298 floats in memory use a long-double format different than that
3299 used in the floating registers. The memory format matches the
3300 x86 extended float format which is 80 bits. An OS may choose to
3301 use this format (e.g. GNU/Linux) or choose to use a different
3302 format for storing long doubles (e.g. HPUX). In the latter case,
3303 the setting of the format may be moved/overridden in an
3304 OS-specific tdep file. */
3305 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3306
3307 set_gdbarch_short_bit (gdbarch, 16);
3308 set_gdbarch_int_bit (gdbarch, 32);
3309 set_gdbarch_long_bit (gdbarch, 64);
3310 set_gdbarch_long_long_bit (gdbarch, 64);
3311 set_gdbarch_float_bit (gdbarch, 32);
3312 set_gdbarch_double_bit (gdbarch, 64);
3313 set_gdbarch_long_double_bit (gdbarch, 128);
3314 set_gdbarch_ptr_bit (gdbarch, 64);
3315
3316 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3317 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
3318 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
3319 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
3320
3321 set_gdbarch_register_name (gdbarch, ia64_register_name);
3322 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3323 gets a number of extra failures. */
3324 set_gdbarch_deprecated_register_size (gdbarch, 8);
3325 set_gdbarch_register_type (gdbarch, ia64_register_type);
3326
3327 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3328 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3329 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3330 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3331 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3332 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3333 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
3334
3335 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
3336
3337 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
3338 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
3339
3340 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
3341 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
3342
3343 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3344 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3345 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3346 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
3347 if (info.osabi == GDB_OSABI_LINUX)
3348 set_gdbarch_write_pc (gdbarch, ia64_linux_write_pc);
3349 else
3350 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
3351
3352 /* Settings for calling functions in the inferior. */
3353 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
3354 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3355 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
3356
3357 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
3358 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
3359 #ifdef HAVE_LIBUNWIND_IA64_H
3360 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3361 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
3362 #endif
3363 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3364 frame_base_set_default (gdbarch, &ia64_frame_base);
3365
3366 /* Settings that should be unnecessary. */
3367 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3368
3369 set_gdbarch_remote_translate_xfer_address (
3370 gdbarch, ia64_remote_translate_xfer_address);
3371
3372 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
3373 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
3374
3375 return gdbarch;
3376 }
3377
3378 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3379
3380 void
3381 _initialize_ia64_tdep (void)
3382 {
3383 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
3384 }
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