gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "sim-regno.h"
  34 #include "arch-utils.h"
  35 #include "regcache.h"
  36 #include "trad-frame.h"
  37 #include "reggroups.h"
  38 #include "opcodes/lm32-desc.h"
  39
  40 #include "gdb_string.h"
  41
  42 /* Macros to extract fields from an instruction.  */
  43 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  44 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  45 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  46 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  47 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  48
  49 struct gdbarch_tdep
  50 {
  51   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  52 };
  53
  54 struct lm32_frame_cache
  55 {
  56   /* The frame's base.  Used when constructing a frame ID.  */
  57   CORE_ADDR base;
  58   CORE_ADDR pc;
  59   /* Size of frame.  */
  60   int size;
  61   /* Table indicating the location of each and every register.  */
  62   struct trad_frame_saved_reg *saved_regs;
  63 };
  64
  65 /* Add the available register groups.  */
  66
  67 static void
  68 lm32_add_reggroups (struct gdbarch *gdbarch)
  69 {
  70   reggroup_add (gdbarch, general_reggroup);
  71   reggroup_add (gdbarch, all_reggroup);
  72   reggroup_add (gdbarch, system_reggroup);
  73 }
  74
  75 /* Return whether a given register is in a given group.  */
  76
  77 static int
  78 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  79                           struct reggroup *group)
  80 {
  81   if (group == general_reggroup)
  82     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  83       || (regnum == SIM_LM32_PC_REGNUM);
  84   else if (group == system_reggroup)
  85     return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
  86       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  87   return default_register_reggroup_p (gdbarch, regnum, group);
  88 }
  89
  90 /* Return a name that corresponds to the given register number.  */
  91
  92 static const char *
  93 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  94 {
  95   static char *register_names[] = {
  96     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  97     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  98     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  99     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
 100     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
 101   };
 102
 103   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
 104     return NULL;
 105   else
 106     return register_names[reg_nr];
 107 }
 108
 109 /* Return type of register.  */
 110
 111 static struct type *
 112 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 113 {
 114   return builtin_type (gdbarch)->builtin_int32;
 115 }
 116
 117 /* Return non-zero if a register can't be written.  */
 118
 119 static int
 120 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 121 {
 122   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 123 }
 124
 125 /* Analyze a function's prologue.  */
 126
 127 static CORE_ADDR
 128 lm32_analyze_prologue (struct gdbarch *gdbarch,
 129                        CORE_ADDR pc, CORE_ADDR limit,
 130                        struct lm32_frame_cache *info)
 131 {
 132   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 133   unsigned long instruction;
 134
 135   /* Keep reading though instructions, until we come across an instruction
 136      that isn't likely to be part of the prologue.  */
 137   info->size = 0;
 138   for (; pc < limit; pc += 4)
 139     {
 140
 141       /* Read an instruction.  */
 142       instruction = read_memory_integer (pc, 4, byte_order);
 143
 144       if ((LM32_OPCODE (instruction) == OP_SW)
 145           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 146         {
 147           /* Any stack displaced store is likely part of the prologue.
 148              Record that the register is being saved, and the offset
 149              into the stack.  */
 150           info->saved_regs[LM32_REG1 (instruction)].addr =
 151             LM32_IMM16 (instruction);
 152         }
 153       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 154                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 155         {
 156           /* An add to the SP is likely to be part of the prologue.
 157              Adjust stack size by whatever the instruction adds to the sp.  */
 158           info->size -= LM32_IMM16 (instruction);
 159         }
 160       else if (                 /* add fp,fp,sp */
 161                 ((LM32_OPCODE (instruction) == OP_ADD)
 162                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 163                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 164                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 165                 /* mv fp,imm */
 166                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 167                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 168                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 169         {
 170           /* Likely to be in the prologue for functions that require
 171              a frame pointer.  */
 172         }
 173       else
 174         {
 175           /* Any other instruction is likely not to be part of the
 176              prologue.  */
 177           break;
 178         }
 179     }
 180
 181   return pc;
 182 }
 183
 184 /* Return PC of first non prologue instruction, for the function at the
 185    specified address.  */
 186
 187 static CORE_ADDR
 188 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 189 {
 190   CORE_ADDR func_addr, limit_pc;
 191   struct symtab_and_line sal;
 192   struct lm32_frame_cache frame_info;
 193   struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 194
 195   /* See if we can determine the end of the prologue via the symbol table.
 196      If so, then return either PC, or the PC after the prologue, whichever
 197      is greater.  */
 198   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 199     {
 200       CORE_ADDR post_prologue_pc
 201         = skip_prologue_using_sal (gdbarch, func_addr);
 202       if (post_prologue_pc != 0)
 203         return max (pc, post_prologue_pc);
 204     }
 205
 206   /* Can't determine prologue from the symbol table, need to examine
 207      instructions.  */
 208
 209   /* Find an upper limit on the function prologue using the debug
 210      information.  If the debug information could not be used to provide
 211      that bound, then use an arbitrary large number as the upper bound.  */
 212   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 213   if (limit_pc == 0)
 214     limit_pc = pc + 100;        /* Magic.  */
 215
 216   frame_info.saved_regs = saved_regs;
 217   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 218 }
 219
 220 /* Create a breakpoint instruction.  */
 221
 222 static const gdb_byte *
 223 lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
 224                          int *lenptr)
 225 {
 226   static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };
 227
 228   *lenptr = sizeof (breakpoint);
 229   return breakpoint;
 230 }
 231
 232 /* Setup registers and stack for faking a call to a function in the
 233    inferior.  */
 234
 235 static CORE_ADDR
 236 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 237                       struct regcache *regcache, CORE_ADDR bp_addr,
 238                       int nargs, struct value **args, CORE_ADDR sp,
 239                       int struct_return, CORE_ADDR struct_addr)
 240 {
 241   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 242   int first_arg_reg = SIM_LM32_R1_REGNUM;
 243   int num_arg_regs = 8;
 244   int i;
 245
 246   /* Set the return address.  */
 247   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 248
 249   /* If we're returning a large struct, a pointer to the address to
 250      store it at is passed as a first hidden parameter.  */
 251   if (struct_return)
 252     {
 253       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 254       first_arg_reg++;
 255       num_arg_regs--;
 256       sp -= 4;
 257     }
 258
 259   /* Setup parameters.  */
 260   for (i = 0; i < nargs; i++)
 261     {
 262       struct value *arg = args[i];
 263       struct type *arg_type = check_typedef (value_type (arg));
 264       gdb_byte *contents;
 265       int len;
 266       int j;
 267       int reg;
 268       ULONGEST val;
 269
 270       /* Promote small integer types to int.  */
 271       switch (TYPE_CODE (arg_type))
 272         {
 273         case TYPE_CODE_INT:
 274         case TYPE_CODE_BOOL:
 275         case TYPE_CODE_CHAR:
 276         case TYPE_CODE_RANGE:
 277         case TYPE_CODE_ENUM:
 278           if (TYPE_LENGTH (arg_type) < 4)
 279             {
 280               arg_type = builtin_type (gdbarch)->builtin_int32;
 281               arg = value_cast (arg_type, arg);
 282             }
 283           break;
 284         }
 285
 286       /* FIXME: Handle structures.  */
 287
 288       contents = (gdb_byte *) value_contents (arg);
 289       len = TYPE_LENGTH (arg_type);
 290       val = extract_unsigned_integer (contents, len, byte_order);
 291
 292       /* First num_arg_regs parameters are passed by registers,
 293          and the rest are passed on the stack.  */
 294       if (i < num_arg_regs)
 295         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 296       else
 297         {
 298           write_memory (sp, (void *) &val, len);
 299           sp -= 4;
 300         }
 301     }
 302
 303   /* Update stack pointer.  */
 304   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 305
 306   /* Return adjusted stack pointer.  */
 307   return sp;
 308 }
 309
 310 /* Extract return value after calling a function in the inferior.  */
 311
 312 static void
 313 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 314                            gdb_byte *valbuf)
 315 {
 316   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 317   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 318   int offset;
 319   ULONGEST l;
 320   CORE_ADDR return_buffer;
 321
 322   if (TYPE_CODE (type) != TYPE_CODE_STRUCT
 323       && TYPE_CODE (type) != TYPE_CODE_UNION
 324       && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 325     {
 326       /* Return value is returned in a single register.  */
 327       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 328       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 329     }
 330   else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 331     {
 332       /* 64-bit values are returned in a register pair.  */
 333       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 334       memcpy (valbuf, &l, 4);
 335       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 336       memcpy (valbuf + 4, &l, 4);
 337     }
 338   else
 339     {
 340       /* Aggregate types greater than a single register are returned
 341          in memory.  FIXME: Unless they are only 2 regs?.  */
 342       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 343       return_buffer = l;
 344       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 345     }
 346 }
 347
 348 /* Write into appropriate registers a function return value of type
 349    TYPE, given in virtual format.  */
 350 static void
 351 lm32_store_return_value (struct type *type, struct regcache *regcache,
 352                          const gdb_byte *valbuf)
 353 {
 354   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 355   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 356   ULONGEST val;
 357   int len = TYPE_LENGTH (type);
 358
 359   if (len <= 4)
 360     {
 361       val = extract_unsigned_integer (valbuf, len, byte_order);
 362       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 363     }
 364   else if (len <= 8)
 365     {
 366       val = extract_unsigned_integer (valbuf, 4, byte_order);
 367       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 368       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 369       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 370     }
 371   else
 372     error (_("lm32_store_return_value: type length too large."));
 373 }
 374
 375 /* Determine whether a functions return value is in a register or memory.  */
 376 static enum return_value_convention
 377 lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,
 378                    struct type *valtype, struct regcache *regcache,
 379                    gdb_byte *readbuf, const gdb_byte *writebuf)
 380 {
 381   enum type_code code = TYPE_CODE (valtype);
 382
 383   if (code == TYPE_CODE_STRUCT
 384       || code == TYPE_CODE_UNION
 385       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 386     return RETURN_VALUE_STRUCT_CONVENTION;
 387
 388   if (readbuf)
 389     lm32_extract_return_value (valtype, regcache, readbuf);
 390   if (writebuf)
 391     lm32_store_return_value (valtype, regcache, writebuf);
 392
 393   return RETURN_VALUE_REGISTER_CONVENTION;
 394 }
 395
 396 static CORE_ADDR
 397 lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 398 {
 399   return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
 400 }
 401
 402 static CORE_ADDR
 403 lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 404 {
 405   return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
 406 }
 407
 408 static struct frame_id
 409 lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
 410 {
 411   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 412
 413   return frame_id_build (sp, get_frame_pc (this_frame));
 414 }
 415
 416 /* Put here the code to store, into fi->saved_regs, the addresses of
 417    the saved registers of frame described by FRAME_INFO.  This
 418    includes special registers such as pc and fp saved in special ways
 419    in the stack frame.  sp is even more special: the address we return
 420    for it IS the sp for the next frame.  */
 421
 422 static struct lm32_frame_cache *
 423 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 424 {
 425   CORE_ADDR prologue_pc;
 426   CORE_ADDR current_pc;
 427   ULONGEST prev_sp;
 428   ULONGEST this_base;
 429   struct lm32_frame_cache *info;
 430   int prefixed;
 431   unsigned long instruction;
 432   int op;
 433   int offsets[32];
 434   int i;
 435   long immediate;
 436
 437   if ((*this_prologue_cache))
 438     return (*this_prologue_cache);
 439
 440   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 441   (*this_prologue_cache) = info;
 442   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 443
 444   info->pc = get_frame_func (this_frame);
 445   current_pc = get_frame_pc (this_frame);
 446   lm32_analyze_prologue (get_frame_arch (this_frame),
 447                          info->pc, current_pc, info);
 448
 449   /* Compute the frame's base, and the previous frame's SP.  */
 450   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 451   prev_sp = this_base + info->size;
 452   info->base = this_base;
 453
 454   /* Convert callee save offsets into addresses.  */
 455   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 456     {
 457       if (trad_frame_addr_p (info->saved_regs, i))
 458         info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
 459     }
 460
 461   /* The call instruction moves the caller's PC in the callee's RA register.
 462      Since this is an unwind, do the reverse.  Copy the location of RA register
 463      into PC (the address / regnum) so that a request for PC will be
 464      converted into a request for the RA register.  */
 465   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 466
 467   /* The previous frame's SP needed to be computed.  Save the computed
 468      value.  */
 469   trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
 470
 471   return info;
 472 }
 473
 474 static void
 475 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 476                     struct frame_id *this_id)
 477 {
 478   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 479
 480   /* This marks the outermost frame.  */
 481   if (cache->base == 0)
 482     return;
 483
 484   (*this_id) = frame_id_build (cache->base, cache->pc);
 485 }
 486
 487 static struct value *
 488 lm32_frame_prev_register (struct frame_info *this_frame,
 489                           void **this_prologue_cache, int regnum)
 490 {
 491   struct lm32_frame_cache *info;
 492
 493   info = lm32_frame_cache (this_frame, this_prologue_cache);
 494   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 495 }
 496
 497 static const struct frame_unwind lm32_frame_unwind = {
 498   NORMAL_FRAME,
 499   lm32_frame_this_id,
 500   lm32_frame_prev_register,
 501   NULL,
 502   default_frame_sniffer
 503 };
 504
 505 static CORE_ADDR
 506 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 507 {
 508   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 509
 510   return info->base;
 511 }
 512
 513 static const struct frame_base lm32_frame_base = {
 514   &lm32_frame_unwind,
 515   lm32_frame_base_address,
 516   lm32_frame_base_address,
 517   lm32_frame_base_address
 518 };
 519
 520 static CORE_ADDR
 521 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 522 {
 523   /* Align to the size of an instruction (so that they can safely be
 524      pushed onto the stack.  */
 525   return sp & ~3;
 526 }
 527
 528 static struct gdbarch *
 529 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 530 {
 531   struct gdbarch *gdbarch;
 532   struct gdbarch_tdep *tdep;
 533
 534   /* If there is already a candidate, use it.  */
 535   arches = gdbarch_list_lookup_by_info (arches, &info);
 536   if (arches != NULL)
 537     return arches->gdbarch;
 538
 539   /* None found, create a new architecture from the information provided.  */
 540   tdep = XMALLOC (struct gdbarch_tdep);
 541   gdbarch = gdbarch_alloc (&info, tdep);
 542
 543   /* Type sizes.  */
 544   set_gdbarch_short_bit (gdbarch, 16);
 545   set_gdbarch_int_bit (gdbarch, 32);
 546   set_gdbarch_long_bit (gdbarch, 32);
 547   set_gdbarch_long_long_bit (gdbarch, 64);
 548   set_gdbarch_float_bit (gdbarch, 32);
 549   set_gdbarch_double_bit (gdbarch, 64);
 550   set_gdbarch_long_double_bit (gdbarch, 64);
 551   set_gdbarch_ptr_bit (gdbarch, 32);
 552
 553   /* Register info.  */
 554   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 555   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 556   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 557   set_gdbarch_register_name (gdbarch, lm32_register_name);
 558   set_gdbarch_register_type (gdbarch, lm32_register_type);
 559   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 560
 561   /* Frame info.  */
 562   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 563   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 564   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 565   set_gdbarch_frame_args_skip (gdbarch, 0);
 566
 567   /* Frame unwinding.  */
 568   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 569   frame_base_set_default (gdbarch, &lm32_frame_base);
 570   set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
 571   set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
 572   set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
 573   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 574
 575   /* Breakpoints.  */
 576   set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
 577   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 578
 579   /* Calling functions in the inferior.  */
 580   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 581   set_gdbarch_return_value (gdbarch, lm32_return_value);
 582
 583   /* Instruction disassembler.  */
 584   set_gdbarch_print_insn (gdbarch, print_insn_lm32);
 585
 586   lm32_add_reggroups (gdbarch);
 587   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 588
 589   return gdbarch;
 590 }
 591
 592 void
 593 _initialize_lm32_tdep (void)
 594 {
 595   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 596 }