gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009, 2010 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "sim-regno.h"
  34 #include "arch-utils.h"
  35 #include "regcache.h"
  36 #include "trad-frame.h"
  37 #include "reggroups.h"
  38 #include "opcodes/lm32-desc.h"
  39
  40 #include "gdb_string.h"
  41
  42 /* Macros to extract fields from an instruction.  */
  43 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  44 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  45 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  46 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  47 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  48
  49 struct gdbarch_tdep
  50 {
  51   /* gdbarch target dependent data here. Currently unused for LM32.  */
  52 };
  53
  54 struct lm32_frame_cache
  55 {
  56   /* The frame's base.  Used when constructing a frame ID.  */
  57   CORE_ADDR base;
  58   CORE_ADDR pc;
  59   /* Size of frame.  */
  60   int size;
  61   /* Table indicating the location of each and every register.  */
  62   struct trad_frame_saved_reg *saved_regs;
  63 };
  64
  65 /* Add the available register groups.  */
  66
  67 static void
  68 lm32_add_reggroups (struct gdbarch *gdbarch)
  69 {
  70   reggroup_add (gdbarch, general_reggroup);
  71   reggroup_add (gdbarch, all_reggroup);
  72   reggroup_add (gdbarch, system_reggroup);
  73 }
  74
  75 /* Return whether a given register is in a given group.  */
  76
  77 static int
  78 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  79                           struct reggroup *group)
  80 {
  81   if (group == general_reggroup)
  82     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  83       || (regnum == SIM_LM32_PC_REGNUM);
  84   else if (group == system_reggroup)
  85     return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
  86       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  87   return default_register_reggroup_p (gdbarch, regnum, group);
  88 }
  89
  90 /* Return a name that corresponds to the given register number.  */
  91
  92 static const char *
  93 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  94 {
  95   static char *register_names[] = {
  96     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  97     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  98     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  99     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
 100     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
 101   };
 102
 103   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
 104     return NULL;
 105   else
 106     return register_names[reg_nr];
 107 }
 108
 109 /* Return type of register.  */
 110
 111 static struct type *
 112 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 113 {
 114   return builtin_type (gdbarch)->builtin_int32;
 115 }
 116
 117 /* Return non-zero if a register can't be written.  */
 118
 119 static int
 120 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 121 {
 122   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 123 }
 124
 125 /* Analyze a function's prologue.  */
 126
 127 static CORE_ADDR
 128 lm32_analyze_prologue (struct gdbarch *gdbarch,
 129                        CORE_ADDR pc, CORE_ADDR limit,
 130                        struct lm32_frame_cache *info)
 131 {
 132   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 133   unsigned long instruction;
 134
 135   /* Keep reading though instructions, until we come across an instruction
 136      that isn't likely to be part of the prologue.  */
 137   info->size = 0;
 138   for (; pc < limit; pc += 4)
 139     {
 140
 141       /* Read an instruction.  */
 142       instruction = read_memory_integer (pc, 4, byte_order);
 143
 144       if ((LM32_OPCODE (instruction) == OP_SW)
 145           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 146         {
 147           /* Any stack displaced store is likely part of the prologue.
 148              Record that the register is being saved, and the offset
 149              into the stack.  */
 150           info->saved_regs[LM32_REG1 (instruction)].addr =
 151             LM32_IMM16 (instruction);
 152         }
 153       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 154                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 155         {
 156           /* An add to the SP is likely to be part of the prologue.
 157              Adjust stack size by whatever the instruction adds to the sp.  */
 158           info->size -= LM32_IMM16 (instruction);
 159         }
 160       else if (                 /* add fp,fp,sp */
 161                 ((LM32_OPCODE (instruction) == OP_ADD)
 162                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 163                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 164                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 165                 /* mv fp,imm */
 166                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 167                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 168                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 169         {
 170           /* Likely to be in the prologue for functions that require
 171              a frame pointer.  */
 172         }
 173       else
 174         {
 175           /* Any other instruction is likely not to be part of the prologue.  */
 176           break;
 177         }
 178     }
 179
 180   return pc;
 181 }
 182
 183 /* Return PC of first non prologue instruction, for the function at the
 184    specified address.  */
 185
 186 static CORE_ADDR
 187 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 188 {
 189   CORE_ADDR func_addr, limit_pc;
 190   struct symtab_and_line sal;
 191   struct lm32_frame_cache frame_info;
 192   struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 193
 194   /* See if we can determine the end of the prologue via the symbol table.
 195      If so, then return either PC, or the PC after the prologue, whichever
 196      is greater.  */
 197   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 198     {
 199       CORE_ADDR post_prologue_pc
 200         = skip_prologue_using_sal (gdbarch, func_addr);
 201       if (post_prologue_pc != 0)
 202         return max (pc, post_prologue_pc);
 203     }
 204
 205   /* Can't determine prologue from the symbol table, need to examine
 206      instructions.  */
 207
 208   /* Find an upper limit on the function prologue using the debug
 209      information.  If the debug information could not be used to provide
 210      that bound, then use an arbitrary large number as the upper bound.  */
 211   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 212   if (limit_pc == 0)
 213     limit_pc = pc + 100;        /* Magic.  */
 214
 215   frame_info.saved_regs = saved_regs;
 216   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 217 }
 218
 219 /* Create a breakpoint instruction.  */
 220
 221 static const gdb_byte *
 222 lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
 223                          int *lenptr)
 224 {
 225   static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };
 226
 227   *lenptr = sizeof (breakpoint);
 228   return breakpoint;
 229 }
 230
 231 /* Setup registers and stack for faking a call to a function in the
 232    inferior.  */
 233
 234 static CORE_ADDR
 235 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 236                       struct regcache *regcache, CORE_ADDR bp_addr,
 237                       int nargs, struct value **args, CORE_ADDR sp,
 238                       int struct_return, CORE_ADDR struct_addr)
 239 {
 240   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 241   int first_arg_reg = SIM_LM32_R1_REGNUM;
 242   int num_arg_regs = 8;
 243   int i;
 244
 245   /* Set the return address.  */
 246   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 247
 248   /* If we're returning a large struct, a pointer to the address to
 249      store it at is passed as a first hidden parameter.  */
 250   if (struct_return)
 251     {
 252       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 253       first_arg_reg++;
 254       num_arg_regs--;
 255       sp -= 4;
 256     }
 257
 258   /* Setup parameters.  */
 259   for (i = 0; i < nargs; i++)
 260     {
 261       struct value *arg = args[i];
 262       struct type *arg_type = check_typedef (value_type (arg));
 263       gdb_byte *contents;
 264       int len;
 265       int j;
 266       int reg;
 267       ULONGEST val;
 268
 269       /* Promote small integer types to int.  */
 270       switch (TYPE_CODE (arg_type))
 271         {
 272         case TYPE_CODE_INT:
 273         case TYPE_CODE_BOOL:
 274         case TYPE_CODE_CHAR:
 275         case TYPE_CODE_RANGE:
 276         case TYPE_CODE_ENUM:
 277           if (TYPE_LENGTH (arg_type) < 4)
 278             {
 279               arg_type = builtin_type (gdbarch)->builtin_int32;
 280               arg = value_cast (arg_type, arg);
 281             }
 282           break;
 283         }
 284
 285       /* FIXME: Handle structures.  */
 286
 287       contents = (gdb_byte *) value_contents (arg);
 288       len = TYPE_LENGTH (arg_type);
 289       val = extract_unsigned_integer (contents, len, byte_order);
 290
 291       /* First num_arg_regs parameters are passed by registers,
 292          and the rest are passed on the stack.  */
 293       if (i < num_arg_regs)
 294         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 295       else
 296         {
 297           write_memory (sp, (void *) &val, len);
 298           sp -= 4;
 299         }
 300     }
 301
 302   /* Update stack pointer.  */
 303   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 304
 305   /* Return adjusted stack pointer.  */
 306   return sp;
 307 }
 308
 309 /* Extract return value after calling a function in the inferior.  */
 310
 311 static void
 312 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 313                            gdb_byte *valbuf)
 314 {
 315   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 316   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 317   int offset;
 318   ULONGEST l;
 319   CORE_ADDR return_buffer;
 320
 321   if (TYPE_CODE (type) != TYPE_CODE_STRUCT
 322       && TYPE_CODE (type) != TYPE_CODE_UNION
 323       && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 324     {
 325       /* Return value is returned in a single register.  */
 326       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 327       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 328     }
 329   else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 330     {
 331       /* 64-bit values are returned in a register pair.  */
 332       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 333       memcpy (valbuf, &l, 4);
 334       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 335       memcpy (valbuf + 4, &l, 4);
 336     }
 337   else
 338     {
 339       /* Aggregate types greater than a single register are returned in memory.
 340          FIXME: Unless they are only 2 regs?.  */
 341       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 342       return_buffer = l;
 343       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 344     }
 345 }
 346
 347 /* Write into appropriate registers a function return value of type
 348    TYPE, given in virtual format.  */
 349 static void
 350 lm32_store_return_value (struct type *type, struct regcache *regcache,
 351                          const gdb_byte *valbuf)
 352 {
 353   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 354   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 355   ULONGEST val;
 356   int len = TYPE_LENGTH (type);
 357
 358   if (len <= 4)
 359     {
 360       val = extract_unsigned_integer (valbuf, len, byte_order);
 361       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 362     }
 363   else if (len <= 8)
 364     {
 365       val = extract_unsigned_integer (valbuf, 4, byte_order);
 366       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 367       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 368       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 369     }
 370   else
 371     error (_("lm32_store_return_value: type length too large."));
 372 }
 373
 374 /* Determine whether a functions return value is in a register or memory.  */
 375 static enum return_value_convention
 376 lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,
 377                    struct type *valtype, struct regcache *regcache,
 378                    gdb_byte *readbuf, const gdb_byte *writebuf)
 379 {
 380   enum type_code code = TYPE_CODE (valtype);
 381
 382   if (code == TYPE_CODE_STRUCT
 383       || code == TYPE_CODE_UNION
 384       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 385     return RETURN_VALUE_STRUCT_CONVENTION;
 386
 387   if (readbuf)
 388     lm32_extract_return_value (valtype, regcache, readbuf);
 389   if (writebuf)
 390     lm32_store_return_value (valtype, regcache, writebuf);
 391
 392   return RETURN_VALUE_REGISTER_CONVENTION;
 393 }
 394
 395 static CORE_ADDR
 396 lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 397 {
 398   return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
 399 }
 400
 401 static CORE_ADDR
 402 lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 403 {
 404   return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
 405 }
 406
 407 static struct frame_id
 408 lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
 409 {
 410   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 411
 412   return frame_id_build (sp, get_frame_pc (this_frame));
 413 }
 414
 415 /* Put here the code to store, into fi->saved_regs, the addresses of
 416    the saved registers of frame described by FRAME_INFO.  This
 417    includes special registers such as pc and fp saved in special ways
 418    in the stack frame.  sp is even more special: the address we return
 419    for it IS the sp for the next frame.  */
 420
 421 static struct lm32_frame_cache *
 422 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 423 {
 424   CORE_ADDR prologue_pc;
 425   CORE_ADDR current_pc;
 426   ULONGEST prev_sp;
 427   ULONGEST this_base;
 428   struct lm32_frame_cache *info;
 429   int prefixed;
 430   unsigned long instruction;
 431   int op;
 432   int offsets[32];
 433   int i;
 434   long immediate;
 435
 436   if ((*this_prologue_cache))
 437     return (*this_prologue_cache);
 438
 439   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 440   (*this_prologue_cache) = info;
 441   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 442
 443   info->pc = get_frame_func (this_frame);
 444   current_pc = get_frame_pc (this_frame);
 445   lm32_analyze_prologue (get_frame_arch (this_frame),
 446                          info->pc, current_pc, info);
 447
 448   /* Compute the frame's base, and the previous frame's SP.  */
 449   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 450   prev_sp = this_base + info->size;
 451   info->base = this_base;
 452
 453   /* Convert callee save offsets into addresses.  */
 454   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 455     {
 456       if (trad_frame_addr_p (info->saved_regs, i))
 457         info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
 458     }
 459
 460   /* The call instruction moves the caller's PC in the callee's RA register.
 461      Since this is an unwind, do the reverse.  Copy the location of RA register
 462      into PC (the address / regnum) so that a request for PC will be
 463      converted into a request for the RA register.  */
 464   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 465
 466   /* The previous frame's SP needed to be computed.  Save the computed value. */
 467   trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
 468
 469   return info;
 470 }
 471
 472 static void
 473 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 474                     struct frame_id *this_id)
 475 {
 476   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 477
 478   /* This marks the outermost frame.  */
 479   if (cache->base == 0)
 480     return;
 481
 482   (*this_id) = frame_id_build (cache->base, cache->pc);
 483 }
 484
 485 static struct value *
 486 lm32_frame_prev_register (struct frame_info *this_frame,
 487                           void **this_prologue_cache, int regnum)
 488 {
 489   struct lm32_frame_cache *info;
 490
 491   info = lm32_frame_cache (this_frame, this_prologue_cache);
 492   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 493 }
 494
 495 static const struct frame_unwind lm32_frame_unwind = {
 496   NORMAL_FRAME,
 497   lm32_frame_this_id,
 498   lm32_frame_prev_register,
 499   NULL,
 500   default_frame_sniffer
 501 };
 502
 503 static CORE_ADDR
 504 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 505 {
 506   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 507
 508   return info->base;
 509 }
 510
 511 static const struct frame_base lm32_frame_base = {
 512   &lm32_frame_unwind,
 513   lm32_frame_base_address,
 514   lm32_frame_base_address,
 515   lm32_frame_base_address
 516 };
 517
 518 static CORE_ADDR
 519 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 520 {
 521   /* Align to the size of an instruction (so that they can safely be
 522      pushed onto the stack.  */
 523   return sp & ~3;
 524 }
 525
 526 static struct gdbarch *
 527 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 528 {
 529   struct gdbarch *gdbarch;
 530   struct gdbarch_tdep *tdep;
 531
 532   /* If there is already a candidate, use it.  */
 533   arches = gdbarch_list_lookup_by_info (arches, &info);
 534   if (arches != NULL)
 535     return arches->gdbarch;
 536
 537   /* None found, create a new architecture from the information provided.  */
 538   tdep = XMALLOC (struct gdbarch_tdep);
 539   gdbarch = gdbarch_alloc (&info, tdep);
 540
 541   /* Type sizes.  */
 542   set_gdbarch_short_bit (gdbarch, 16);
 543   set_gdbarch_int_bit (gdbarch, 32);
 544   set_gdbarch_long_bit (gdbarch, 32);
 545   set_gdbarch_long_long_bit (gdbarch, 64);
 546   set_gdbarch_float_bit (gdbarch, 32);
 547   set_gdbarch_double_bit (gdbarch, 64);
 548   set_gdbarch_long_double_bit (gdbarch, 64);
 549   set_gdbarch_ptr_bit (gdbarch, 32);
 550
 551   /* Register info.  */
 552   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 553   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 554   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 555   set_gdbarch_register_name (gdbarch, lm32_register_name);
 556   set_gdbarch_register_type (gdbarch, lm32_register_type);
 557   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 558
 559   /* Frame info.  */
 560   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 561   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 562   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 563   set_gdbarch_frame_args_skip (gdbarch, 0);
 564
 565   /* Frame unwinding.  */
 566   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 567   frame_base_set_default (gdbarch, &lm32_frame_base);
 568   set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
 569   set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
 570   set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
 571   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 572
 573   /* Breakpoints.  */
 574   set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
 575   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 576
 577   /* Calling functions in the inferior.  */
 578   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 579   set_gdbarch_return_value (gdbarch, lm32_return_value);
 580
 581   /* Instruction disassembler.  */
 582   set_gdbarch_print_insn (gdbarch, print_insn_lm32);
 583
 584   lm32_add_reggroups (gdbarch);
 585   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 586
 587   return gdbarch;
 588 }
 589
 590 void
 591 _initialize_lm32_tdep (void)
 592 {
 593   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 594 }