gdb/m32r-tdep.c

   1 /* Target-dependent code for Renesas M32R, for GDB.
   2
   3    Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
   4    Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "frame.h"
  25 #include "frame-unwind.h"
  26 #include "frame-base.h"
  27 #include "symtab.h"
  28 #include "gdbtypes.h"
  29 #include "gdbcmd.h"
  30 #include "gdbcore.h"
  31 #include "gdb_string.h"
  32 #include "value.h"
  33 #include "inferior.h"
  34 #include "symfile.h"
  35 #include "objfiles.h"
  36 #include "language.h"
  37 #include "arch-utils.h"
  38 #include "regcache.h"
  39 #include "trad-frame.h"
  40
  41 #include "gdb_assert.h"
  42
  43 struct gdbarch_tdep
  44 {
  45   /* gdbarch target dependent data here. Currently unused for M32R. */
  46 };
  47
  48 /* m32r register names. */
  49
  50 enum
  51 {
  52   R0_REGNUM = 0,
  53   R3_REGNUM = 3,
  54   M32R_FP_REGNUM = 13,
  55   LR_REGNUM = 14,
  56   M32R_SP_REGNUM = 15,
  57   PSW_REGNUM = 16,
  58   M32R_PC_REGNUM = 21,
  59   /* m32r calling convention. */
  60   ARG1_REGNUM = R0_REGNUM,
  61   ARGN_REGNUM = R3_REGNUM,
  62   RET1_REGNUM = R0_REGNUM,
  63 };
  64
  65 /* Local functions */
  66
  67 extern void _initialize_m32r_tdep (void);
  68
  69 static CORE_ADDR
  70 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  71 {
  72   /* Align to the size of an instruction (so that they can safely be
  73      pushed onto the stack.  */
  74   return sp & ~3;
  75 }
  76
  77 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
  78    EXTRACT_RETURN_VALUE?  GCC_P is true if compiled with gcc
  79    and TYPE is the type (which is known to be struct, union or array).
  80
  81    The m32r returns anything less than 8 bytes in size in
  82    registers. */
  83
  84 static int
  85 m32r_use_struct_convention (int gcc_p, struct type *type)
  86 {
  87   return (TYPE_LENGTH (type) > 8);
  88 }
  89
  90
  91 /* BREAKPOINT */
  92 #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00}
  93 #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70}
  94 #define M32R_BE_BREAKPOINT16 {0x10, 0xf1}
  95 #define M32R_LE_BREAKPOINT16 {0xf1, 0x10}
  96
  97 static int
  98 m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
  99 {
 100   int val;
 101   unsigned char *bp;
 102   int bplen;
 103
 104   bplen = (addr & 3) ? 2 : 4;
 105
 106   /* Save the memory contents.  */
 107   val = target_read_memory (addr, contents_cache, bplen);
 108   if (val != 0)
 109     return val;                 /* return error */
 110
 111   /* Determine appropriate breakpoint contents and size for this address.  */
 112   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 113     {
 114       if (((addr & 3) == 0)
 115           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
 116         {
 117           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 118           bp = insn;
 119           bplen = sizeof (insn);
 120         }
 121       else
 122         {
 123           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 124           bp = insn;
 125           bplen = sizeof (insn);
 126         }
 127     }
 128   else
 129     {                           /* little-endian */
 130       if (((addr & 3) == 0)
 131           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 132         {
 133           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 134           bp = insn;
 135           bplen = sizeof (insn);
 136         }
 137       else
 138         {
 139           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 140           bp = insn;
 141           bplen = sizeof (insn);
 142         }
 143     }
 144
 145   /* Write the breakpoint.  */
 146   val = target_write_memory (addr, (char *) bp, bplen);
 147   return val;
 148 }
 149
 150 static int
 151 m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
 152 {
 153   int val;
 154   int bplen;
 155
 156   /* Determine appropriate breakpoint contents and size for this address.  */
 157   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 158     {
 159       if (((addr & 3) == 0)
 160           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
 161         {
 162           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 163           bplen = sizeof (insn);
 164         }
 165       else
 166         {
 167           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 168           bplen = sizeof (insn);
 169         }
 170     }
 171   else
 172     {
 173       /* little-endian */
 174       if (((addr & 3) == 0)
 175           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 176         {
 177           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 178           bplen = sizeof (insn);
 179         }
 180       else
 181         {
 182           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 183           bplen = sizeof (insn);
 184         }
 185     }
 186
 187   /* Write contents.  */
 188   val = target_write_memory (addr, contents_cache, bplen);
 189   return val;
 190 }
 191
 192 static const unsigned char *
 193 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 194 {
 195   unsigned char *bp;
 196
 197   /* Determine appropriate breakpoint.  */
 198   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 199     {
 200       if ((*pcptr & 3) == 0)
 201         {
 202           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 203           bp = insn;
 204           *lenptr = sizeof (insn);
 205         }
 206       else
 207         {
 208           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 209           bp = insn;
 210           *lenptr = sizeof (insn);
 211         }
 212     }
 213   else
 214     {
 215       if ((*pcptr & 3) == 0)
 216         {
 217           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 218           bp = insn;
 219           *lenptr = sizeof (insn);
 220         }
 221       else
 222         {
 223           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 224           bp = insn;
 225           *lenptr = sizeof (insn);
 226         }
 227     }
 228
 229   return bp;
 230 }
 231
 232
 233 char *m32r_register_names[] = {
 234   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 235   "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
 236   "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
 237   "evb"
 238 };
 239
 240 static int
 241 m32r_num_regs (void)
 242 {
 243   return (sizeof (m32r_register_names) / sizeof (m32r_register_names[0]));
 244 }
 245
 246 static const char *
 247 m32r_register_name (int reg_nr)
 248 {
 249   if (reg_nr < 0)
 250     return NULL;
 251   if (reg_nr >= m32r_num_regs ())
 252     return NULL;
 253   return m32r_register_names[reg_nr];
 254 }
 255
 256
 257 /* Return the GDB type object for the "standard" data type
 258    of data in register N.  */
 259
 260 static struct type *
 261 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
 262 {
 263   if (reg_nr == M32R_PC_REGNUM)
 264     return builtin_type_void_func_ptr;
 265   else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
 266     return builtin_type_void_data_ptr;
 267   else
 268     return builtin_type_int32;
 269 }
 270
 271
 272 /* Write into appropriate registers a function return value
 273    of type TYPE, given in virtual format.
 274
 275    Things always get returned in RET1_REGNUM, RET2_REGNUM. */
 276
 277 static void
 278 m32r_store_return_value (struct type *type, struct regcache *regcache,
 279                          const void *valbuf)
 280 {
 281   CORE_ADDR regval;
 282   int len = TYPE_LENGTH (type);
 283
 284   regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
 285   regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
 286
 287   if (len > 4)
 288     {
 289       regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4);
 290       regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
 291     }
 292 }
 293
 294 /* Extract from an array REGBUF containing the (raw) register state
 295    the address in which a function should return its structure value,
 296    as a CORE_ADDR (or an expression that can be used as one).  */
 297
 298 static CORE_ADDR
 299 m32r_extract_struct_value_address (struct regcache *regcache)
 300 {
 301   ULONGEST addr;
 302   regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr);
 303   return addr;
 304 }
 305
 306
 307 /* This is required by skip_prologue. The results of decoding a prologue
 308    should be cached because this thrashing is getting nuts.  */
 309
 310 static void
 311 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
 312                  CORE_ADDR *pl_endptr)
 313 {
 314   unsigned long framesize;
 315   int insn;
 316   int op1;
 317   int maybe_one_more = 0;
 318   CORE_ADDR after_prologue = 0;
 319   CORE_ADDR after_stack_adjust = 0;
 320   CORE_ADDR current_pc;
 321
 322   framesize = 0;
 323   after_prologue = 0;
 324
 325   for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
 326     {
 327       insn = read_memory_unsigned_integer (current_pc, 2);
 328
 329       /* If this is a 32 bit instruction, we dont want to examine its
 330          immediate data as though it were an instruction */
 331       if (current_pc & 0x02)
 332         {
 333           /* Clear the parallel execution bit from 16 bit instruction */
 334           if (maybe_one_more)
 335             {
 336               /* The last instruction was a branch, usually terminates
 337                  the series, but if this is a parallel instruction,
 338                  it may be a stack framing instruction */
 339               if (!(insn & 0x8000))
 340                 {
 341                   /* nope, we are really done */
 342                   break;
 343                 }
 344             }
 345           /* decode this instruction further */
 346           insn &= 0x7fff;
 347         }
 348       else
 349         {
 350           if (maybe_one_more)
 351             break;              /* This isnt the one more */
 352           if (insn & 0x8000)
 353             {
 354               if (current_pc == scan_limit)
 355                 scan_limit += 2;        /* extend the search */
 356               current_pc += 2;  /* skip the immediate data */
 357               if (insn == 0x8faf)       /* add3 sp, sp, xxxx */
 358                 /* add 16 bit sign-extended offset */
 359                 {
 360                   framesize +=
 361                     -((short) read_memory_unsigned_integer (current_pc, 2));
 362                 }
 363               else
 364                 {
 365                   if (((insn >> 8) == 0xe4)     /* ld24 r4, xxxxxx; sub sp, r4 */
 366                       && read_memory_unsigned_integer (current_pc + 2,
 367                                                        2) == 0x0f24)
 368                     /* subtract 24 bit sign-extended negative-offset */
 369                     {
 370                       insn = read_memory_unsigned_integer (current_pc - 2, 4);
 371                       if (insn & 0x00800000)    /* sign extend */
 372                         insn |= 0xff000000;     /* negative */
 373                       else
 374                         insn &= 0x00ffffff;     /* positive */
 375                       framesize += insn;
 376                     }
 377                 }
 378               after_prologue = current_pc;
 379               continue;
 380             }
 381         }
 382       op1 = insn & 0xf000;      /* isolate just the first nibble */
 383
 384       if ((insn & 0xf0ff) == 0x207f)
 385         {                       /* st reg, @-sp */
 386           int regno;
 387           framesize += 4;
 388           regno = ((insn >> 8) & 0xf);
 389           after_prologue = 0;
 390           continue;
 391         }
 392       if ((insn >> 8) == 0x4f)  /* addi sp, xx */
 393         /* add 8 bit sign-extended offset */
 394         {
 395           int stack_adjust = (char) (insn & 0xff);
 396
 397           /* there are probably two of these stack adjustments:
 398              1) A negative one in the prologue, and
 399              2) A positive one in the epilogue.
 400              We are only interested in the first one.  */
 401
 402           if (stack_adjust < 0)
 403             {
 404               framesize -= stack_adjust;
 405               after_prologue = 0;
 406               /* A frameless function may have no "mv fp, sp".
 407                  In that case, this is the end of the prologue.  */
 408               after_stack_adjust = current_pc + 2;
 409             }
 410           continue;
 411         }
 412       if (insn == 0x1d8f)
 413         {                       /* mv fp, sp */
 414           after_prologue = current_pc + 2;
 415           break;                /* end of stack adjustments */
 416         }
 417       /* Nop looks like a branch, continue explicitly */
 418       if (insn == 0x7000)
 419         {
 420           after_prologue = current_pc + 2;
 421           continue;             /* nop occurs between pushes */
 422         }
 423       /* End of prolog if any of these are branch instructions */
 424       if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
 425         {
 426           after_prologue = current_pc;
 427           maybe_one_more = 1;
 428           continue;
 429         }
 430       /* Some of the branch instructions are mixed with other types */
 431       if (op1 == 0x1000)
 432         {
 433           int subop = insn & 0x0ff0;
 434           if ((subop == 0x0ec0) || (subop == 0x0fc0))
 435             {
 436               after_prologue = current_pc;
 437               maybe_one_more = 1;
 438               continue;         /* jmp , jl */
 439             }
 440         }
 441     }
 442
 443   if (current_pc >= scan_limit)
 444     {
 445       if (pl_endptr)
 446         {
 447           if (after_stack_adjust != 0)
 448             /* We did not find a "mv fp,sp", but we DID find
 449                a stack_adjust.  Is it safe to use that as the
 450                end of the prologue?  I just don't know. */
 451             {
 452               *pl_endptr = after_stack_adjust;
 453             }
 454           else
 455             /* We reached the end of the loop without finding the end
 456                of the prologue.  No way to win -- we should report failure.
 457                The way we do that is to return the original start_pc.
 458                GDB will set a breakpoint at the start of the function (etc.) */
 459             *pl_endptr = start_pc;
 460         }
 461       return;
 462     }
 463   if (after_prologue == 0)
 464     after_prologue = current_pc;
 465
 466   if (pl_endptr)
 467     *pl_endptr = after_prologue;
 468 }                               /*  decode_prologue */
 469
 470 /* Function: skip_prologue
 471    Find end of function prologue */
 472
 473 #define DEFAULT_SEARCH_LIMIT 44
 474
 475 CORE_ADDR
 476 m32r_skip_prologue (CORE_ADDR pc)
 477 {
 478   CORE_ADDR func_addr, func_end;
 479   struct symtab_and_line sal;
 480
 481   /* See what the symbol table says */
 482
 483   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 484     {
 485       sal = find_pc_line (func_addr, 0);
 486
 487       if (sal.line != 0 && sal.end <= func_end)
 488         {
 489           func_end = sal.end;
 490         }
 491       else
 492         /* Either there's no line info, or the line after the prologue is after
 493            the end of the function.  In this case, there probably isn't a
 494            prologue.  */
 495         {
 496           func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
 497         }
 498     }
 499   else
 500     func_end = pc + DEFAULT_SEARCH_LIMIT;
 501   decode_prologue (pc, func_end, &sal.end);
 502   return sal.end;
 503 }
 504
 505
 506 struct m32r_unwind_cache
 507 {
 508   /* The previous frame's inner most stack address.  Used as this
 509      frame ID's stack_addr.  */
 510   CORE_ADDR prev_sp;
 511   /* The frame's base, optionally used by the high-level debug info.  */
 512   CORE_ADDR base;
 513   int size;
 514   /* How far the SP and r13 (FP) have been offset from the start of
 515      the stack frame (as defined by the previous frame's stack
 516      pointer).  */
 517   LONGEST sp_offset;
 518   LONGEST r13_offset;
 519   int uses_frame;
 520   /* Table indicating the location of each and every register.  */
 521   struct trad_frame_saved_reg *saved_regs;
 522 };
 523
 524 /* Put here the code to store, into fi->saved_regs, the addresses of
 525    the saved registers of frame described by FRAME_INFO.  This
 526    includes special registers such as pc and fp saved in special ways
 527    in the stack frame.  sp is even more special: the address we return
 528    for it IS the sp for the next frame. */
 529
 530 static struct m32r_unwind_cache *
 531 m32r_frame_unwind_cache (struct frame_info *next_frame,
 532                          void **this_prologue_cache)
 533 {
 534   CORE_ADDR pc;
 535   ULONGEST prev_sp;
 536   ULONGEST this_base;
 537   unsigned long op;
 538   int i;
 539   struct m32r_unwind_cache *info;
 540
 541   if ((*this_prologue_cache))
 542     return (*this_prologue_cache);
 543
 544   info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
 545   (*this_prologue_cache) = info;
 546   info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
 547
 548   info->size = 0;
 549   info->sp_offset = 0;
 550
 551   info->uses_frame = 0;
 552   for (pc = frame_func_unwind (next_frame);
 553        pc > 0 && pc < frame_pc_unwind (next_frame); pc += 2)
 554     {
 555       if ((pc & 2) == 0)
 556         {
 557           op = get_frame_memory_unsigned (next_frame, pc, 4);
 558           if ((op & 0x80000000) == 0x80000000)
 559             {
 560               /* 32-bit instruction */
 561               if ((op & 0xffff0000) == 0x8faf0000)
 562                 {
 563                   /* add3 sp,sp,xxxx */
 564                   short n = op & 0xffff;
 565                   info->sp_offset += n;
 566                 }
 567               else if (((op >> 8) == 0xe4)      /* ld24 r4, xxxxxx; sub sp, r4 */
 568                        && get_frame_memory_unsigned (next_frame, pc + 4,
 569                                                      2) == 0x0f24)
 570                 {
 571                   unsigned long n = op & 0xffffff;
 572                   info->sp_offset += n;
 573                   pc += 2;
 574                 }
 575               else
 576                 break;
 577
 578               pc += 2;
 579               continue;
 580             }
 581         }
 582
 583       /* 16-bit instructions */
 584       op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
 585       if ((op & 0xf0ff) == 0x207f)
 586         {
 587           /* st rn, @-sp */
 588           int regno = ((op >> 8) & 0xf);
 589           info->sp_offset -= 4;
 590           info->saved_regs[regno].addr = info->sp_offset;
 591         }
 592       else if ((op & 0xff00) == 0x4f00)
 593         {
 594           /* addi sp, xx */
 595           int n = (char) (op & 0xff);
 596           info->sp_offset += n;
 597         }
 598       else if (op == 0x1d8f)
 599         {
 600           /* mv fp, sp */
 601           info->uses_frame = 1;
 602           info->r13_offset = info->sp_offset;
 603         }
 604       else if (op == 0x7000)
 605         /* nop */
 606         continue;
 607       else
 608         break;
 609     }
 610
 611   info->size = -info->sp_offset;
 612
 613   /* Compute the previous frame's stack pointer (which is also the
 614      frame's ID's stack address), and this frame's base pointer.  */
 615   if (info->uses_frame)
 616     {
 617       /* The SP was moved to the FP.  This indicates that a new frame
 618          was created.  Get THIS frame's FP value by unwinding it from
 619          the next frame.  */
 620       this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
 621       /* The FP points at the last saved register.  Adjust the FP back
 622          to before the first saved register giving the SP.  */
 623       prev_sp = this_base + info->size;
 624     }
 625   else
 626     {
 627       /* Assume that the FP is this frame's SP but with that pushed
 628          stack space added back.  */
 629       this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 630       prev_sp = this_base + info->size;
 631     }
 632
 633   /* Convert that SP/BASE into real addresses.  */
 634   info->prev_sp = prev_sp;
 635   info->base = this_base;
 636
 637   /* Adjust all the saved registers so that they contain addresses and
 638      not offsets.  */
 639   for (i = 0; i < NUM_REGS - 1; i++)
 640     if (trad_frame_addr_p (info->saved_regs, i))
 641       info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
 642
 643   /* The call instruction moves the caller's PC in the callee's LR.
 644      Since this is an unwind, do the reverse.  Copy the location of LR
 645      into PC (the address / regnum) so that a request for PC will be
 646      converted into a request for the LR.  */
 647   info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
 648
 649   /* The previous frame's SP needed to be computed.  Save the computed
 650      value.  */
 651   trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
 652
 653   return info;
 654 }
 655
 656 static CORE_ADDR
 657 m32r_read_pc (ptid_t ptid)
 658 {
 659   ptid_t save_ptid;
 660   ULONGEST pc;
 661
 662   save_ptid = inferior_ptid;
 663   inferior_ptid = ptid;
 664   regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc);
 665   inferior_ptid = save_ptid;
 666   return pc;
 667 }
 668
 669 static void
 670 m32r_write_pc (CORE_ADDR val, ptid_t ptid)
 671 {
 672   ptid_t save_ptid;
 673
 674   save_ptid = inferior_ptid;
 675   inferior_ptid = ptid;
 676   write_register (M32R_PC_REGNUM, val);
 677   inferior_ptid = save_ptid;
 678 }
 679
 680 static CORE_ADDR
 681 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 682 {
 683   return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 684 }
 685
 686
 687 static CORE_ADDR
 688 m32r_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
 689                       struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
 690                       struct value **args, CORE_ADDR sp, int struct_return,
 691                       CORE_ADDR struct_addr)
 692 {
 693   int stack_offset, stack_alloc;
 694   int argreg = ARG1_REGNUM;
 695   int argnum;
 696   struct type *type;
 697   enum type_code typecode;
 698   CORE_ADDR regval;
 699   char *val;
 700   char valbuf[MAX_REGISTER_SIZE];
 701   int len;
 702   int odd_sized_struct;
 703
 704   /* first force sp to a 4-byte alignment */
 705   sp = sp & ~3;
 706
 707   /* Set the return address.  For the m32r, the return breakpoint is
 708      always at BP_ADDR.  */
 709   regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
 710
 711   /* If STRUCT_RETURN is true, then the struct return address (in
 712      STRUCT_ADDR) will consume the first argument-passing register.
 713      Both adjust the register count and store that value.  */
 714   if (struct_return)
 715     {
 716       regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
 717       argreg++;
 718     }
 719
 720   /* Now make sure there's space on the stack */
 721   for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
 722     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
 723   sp -= stack_alloc;            /* make room on stack for args */
 724
 725   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 726     {
 727       type = VALUE_TYPE (args[argnum]);
 728       typecode = TYPE_CODE (type);
 729       len = TYPE_LENGTH (type);
 730
 731       memset (valbuf, 0, sizeof (valbuf));
 732
 733       /* Passes structures that do not fit in 2 registers by reference.  */
 734       if (len > 8
 735           && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
 736         {
 737           store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
 738           typecode = TYPE_CODE_PTR;
 739           len = 4;
 740           val = valbuf;
 741         }
 742       else if (len < 4)
 743         {
 744           /* value gets right-justified in the register or stack word */
 745           memcpy (valbuf + (register_size (gdbarch, argreg) - len),
 746                   (char *) VALUE_CONTENTS (args[argnum]), len);
 747           val = valbuf;
 748         }
 749       else
 750         val = (char *) VALUE_CONTENTS (args[argnum]);
 751
 752       while (len > 0)
 753         {
 754           if (argreg > ARGN_REGNUM)
 755             {
 756               /* must go on the stack */
 757               write_memory (sp + stack_offset, val, 4);
 758               stack_offset += 4;
 759             }
 760           else if (argreg <= ARGN_REGNUM)
 761             {
 762               /* there's room in a register */
 763               regval =
 764                 extract_unsigned_integer (val,
 765                                           register_size (gdbarch, argreg));
 766               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 767             }
 768
 769           /* Store the value 4 bytes at a time.  This means that things
 770              larger than 4 bytes may go partly in registers and partly
 771              on the stack.  */
 772           len -= register_size (gdbarch, argreg);
 773           val += register_size (gdbarch, argreg);
 774         }
 775     }
 776
 777   /* Finally, update the SP register.  */
 778   regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
 779
 780   return sp;
 781 }
 782
 783
 784 /* Given a return value in `regbuf' with a type `valtype',
 785    extract and copy its value into `valbuf'.  */
 786
 787 static void
 788 m32r_extract_return_value (struct type *type, struct regcache *regcache,
 789                            void *dst)
 790 {
 791   bfd_byte *valbuf = dst;
 792   int len = TYPE_LENGTH (type);
 793   ULONGEST tmp;
 794
 795   /* By using store_unsigned_integer we avoid having to do
 796      anything special for small big-endian values.  */
 797   regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
 798   store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
 799
 800   /* Ignore return values more than 8 bytes in size because the m32r
 801      returns anything more than 8 bytes in the stack. */
 802   if (len > 4)
 803     {
 804       regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
 805       store_unsigned_integer (valbuf + len - 4, 4, tmp);
 806     }
 807 }
 808
 809
 810 static CORE_ADDR
 811 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 812 {
 813   return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
 814 }
 815
 816 /* Given a GDB frame, determine the address of the calling function's
 817    frame.  This will be used to create a new GDB frame struct.  */
 818
 819 static void
 820 m32r_frame_this_id (struct frame_info *next_frame,
 821                     void **this_prologue_cache, struct frame_id *this_id)
 822 {
 823   struct m32r_unwind_cache *info
 824     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 825   CORE_ADDR base;
 826   CORE_ADDR func;
 827   struct minimal_symbol *msym_stack;
 828   struct frame_id id;
 829
 830   /* The FUNC is easy.  */
 831   func = frame_func_unwind (next_frame);
 832
 833   /* This is meant to halt the backtrace at "_start".  Make sure we
 834      don't halt it at a generic dummy frame. */
 835   if (inside_entry_file (func))
 836     return;
 837
 838   /* Check if the stack is empty.  */
 839   msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
 840   if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
 841     return;
 842
 843   /* Hopefully the prologue analysis either correctly determined the
 844      frame's base (which is the SP from the previous frame), or set
 845      that base to "NULL".  */
 846   base = info->prev_sp;
 847   if (base == 0)
 848     return;
 849
 850   id = frame_id_build (base, func);
 851
 852   /* Check that we're not going round in circles with the same frame
 853      ID (but avoid applying the test to sentinel frames which do go
 854      round in circles).  Can't use frame_id_eq() as that doesn't yet
 855      compare the frame's PC value.  */
 856   if (frame_relative_level (next_frame) >= 0
 857       && get_frame_type (next_frame) != DUMMY_FRAME
 858       && frame_id_eq (get_frame_id (next_frame), id))
 859     return;
 860
 861   (*this_id) = id;
 862 }
 863
 864 static void
 865 m32r_frame_prev_register (struct frame_info *next_frame,
 866                           void **this_prologue_cache,
 867                           int regnum, int *optimizedp,
 868                           enum lval_type *lvalp, CORE_ADDR *addrp,
 869                           int *realnump, void *bufferp)
 870 {
 871   struct m32r_unwind_cache *info
 872     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 873   trad_frame_prev_register (next_frame, info->saved_regs, regnum,
 874                             optimizedp, lvalp, addrp, realnump, bufferp);
 875 }
 876
 877 static const struct frame_unwind m32r_frame_unwind = {
 878   NORMAL_FRAME,
 879   m32r_frame_this_id,
 880   m32r_frame_prev_register
 881 };
 882
 883 static const struct frame_unwind *
 884 m32r_frame_sniffer (struct frame_info *next_frame)
 885 {
 886   return &m32r_frame_unwind;
 887 }
 888
 889 static CORE_ADDR
 890 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
 891 {
 892   struct m32r_unwind_cache *info
 893     = m32r_frame_unwind_cache (next_frame, this_cache);
 894   return info->base;
 895 }
 896
 897 static const struct frame_base m32r_frame_base = {
 898   &m32r_frame_unwind,
 899   m32r_frame_base_address,
 900   m32r_frame_base_address,
 901   m32r_frame_base_address
 902 };
 903
 904 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
 905    dummy frame.  The frame ID's base needs to match the TOS value
 906    saved by save_dummy_frame_tos(), and the PC match the dummy frame's
 907    breakpoint.  */
 908
 909 static struct frame_id
 910 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
 911 {
 912   return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
 913                          frame_pc_unwind (next_frame));
 914 }
 915
 916
 917 static gdbarch_init_ftype m32r_gdbarch_init;
 918
 919 static struct gdbarch *
 920 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 921 {
 922   struct gdbarch *gdbarch;
 923   struct gdbarch_tdep *tdep;
 924
 925   /* If there is already a candidate, use it.  */
 926   arches = gdbarch_list_lookup_by_info (arches, &info);
 927   if (arches != NULL)
 928     return arches->gdbarch;
 929
 930   /* Allocate space for the new architecture.  */
 931   tdep = XMALLOC (struct gdbarch_tdep);
 932   gdbarch = gdbarch_alloc (&info, tdep);
 933
 934   set_gdbarch_read_pc (gdbarch, m32r_read_pc);
 935   set_gdbarch_write_pc (gdbarch, m32r_write_pc);
 936   set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
 937
 938   set_gdbarch_num_regs (gdbarch, m32r_num_regs ());
 939   set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
 940   set_gdbarch_register_name (gdbarch, m32r_register_name);
 941   set_gdbarch_register_type (gdbarch, m32r_register_type);
 942
 943   set_gdbarch_extract_return_value (gdbarch, m32r_extract_return_value);
 944   set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
 945   set_gdbarch_store_return_value (gdbarch, m32r_store_return_value);
 946   set_gdbarch_extract_struct_value_address (gdbarch,
 947                                             m32r_extract_struct_value_address);
 948   set_gdbarch_use_struct_convention (gdbarch, m32r_use_struct_convention);
 949
 950   set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
 951   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 952   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 953   set_gdbarch_function_start_offset (gdbarch, 0);
 954   set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
 955   set_gdbarch_memory_insert_breakpoint (gdbarch,
 956                                         m32r_memory_insert_breakpoint);
 957   set_gdbarch_memory_remove_breakpoint (gdbarch,
 958                                         m32r_memory_remove_breakpoint);
 959
 960   set_gdbarch_frame_args_skip (gdbarch, 0);
 961   set_gdbarch_frameless_function_invocation (gdbarch,
 962                                              frameless_look_for_prologue);
 963
 964   set_gdbarch_frame_align (gdbarch, m32r_frame_align);
 965
 966   frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
 967   frame_base_set_default (gdbarch, &m32r_frame_base);
 968
 969   /* Methods for saving / extracting a dummy frame's ID.  The ID's
 970      stack address must match the SP value returned by
 971      PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos.  */
 972   set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
 973
 974   /* Return the unwound PC value.  */
 975   set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
 976
 977   set_gdbarch_print_insn (gdbarch, print_insn_m32r);
 978
 979   return gdbarch;
 980 }
 981
 982 void
 983 _initialize_m32r_tdep (void)
 984 {
 985   register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);
 986 }