gdb/microblaze-tdep.c

   1 /* Target-dependent code for Xilinx MicroBlaze.
   2
   3    Copyright 2009 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "defs.h"
  21 #include "arch-utils.h"
  22 #include "dis-asm.h"
  23 #include "frame.h"
  24 #include "trad-frame.h"
  25 #include "symtab.h"
  26 #include "value.h"
  27 #include "gdbcmd.h"
  28 #include "breakpoint.h"
  29 #include "inferior.h"
  30 #include "regcache.h"
  31 #include "target.h"
  32 #include "frame.h"
  33 #include "frame-base.h"
  34 #include "frame-unwind.h"
  35 #include "dwarf2-frame.h"
  36 #include "osabi.h"
  37
  38 #include "gdb_assert.h"
  39 #include "gdb_string.h"
  40 #include "target-descriptions.h"
  41 #include "opcodes/microblaze-opcm.h"
  42 #include "opcodes/microblaze-dis.h"
  43 #include "microblaze-tdep.h"
  44 \f
  45 /* Instruction macros used for analyzing the prologue.  */
  46 /* This set of instruction macros need to be changed whenever the
  47    prologue generated by the compiler could have more instructions or
  48    different type of instructions.
  49    This set also needs to be verified if it is complete.  */
  50 #define IS_RETURN(op) (op == rtsd || op == rtid)
  51 #define IS_UPDATE_SP(op, rd, ra) \
  52         ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP)
  53 #define IS_SPILL_SP(op, rd, ra) \
  54         ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP)
  55 #define IS_SPILL_REG(op, rd, ra) \
  56         ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP)
  57 #define IS_ALSO_SPILL_REG(op, rd, ra, rb) \
  58         ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP)
  59 #define IS_SETUP_FP(op, ra, rb) \
  60         ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0)
  61 #define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \
  62         ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0)
  63 #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
  64         ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
  65
  66 /* All registers are 32 bits.  */
  67 #define MICROBLAZE_REGISTER_SIZE 4
  68
  69 /* The registers of the Xilinx microblaze processor.  */
  70
  71 static const char *microblaze_register_names[] =
  72 {
  73   "r0",   "r1",  "r2",    "r3",   "r4",   "r5",   "r6",   "r7",
  74   "r8",   "r9",  "r10",   "r11",  "r12",  "r13",  "r14",  "r15",
  75   "r16",  "r17", "r18",   "r19",  "r20",  "r21",  "r22",  "r23",
  76   "r24",  "r25", "r26",   "r27",  "r28",  "r29",  "r30",  "r31",
  77   "rpc",  "rmsr", "rear", "resr", "rfsr", "rbtr",
  78   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
  79   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
  80   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
  81 };
  82
  83 #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
  84 \f
  85 static int microblaze_debug_flag = 0;
  86
  87 void
  88 microblaze_debug (const char *fmt, ...)
  89 {
  90   if (microblaze_debug_flag)
  91     {
  92        va_list args;
  93
  94        va_start (args, fmt);
  95        printf_unfiltered ("MICROBLAZE: ");
  96        vprintf_unfiltered (fmt, args);
  97        va_end (args);
  98     }
  99 }
 100 \f
 101 /* Return the name of register REGNUM.  */
 102
 103 static const char *
 104 microblaze_register_name (struct gdbarch *gdbarch, int regnum)
 105 {
 106   if (regnum >= 0 && regnum < MICROBLAZE_NUM_REGS)
 107     return microblaze_register_names[regnum];
 108   return NULL;
 109 }
 110
 111 static struct type *
 112 microblaze_register_type (struct gdbarch *gdbarch, int regnum)
 113 {
 114   if (regnum == MICROBLAZE_SP_REGNUM)
 115     return builtin_type (gdbarch)->builtin_data_ptr;
 116
 117   if (regnum == MICROBLAZE_PC_REGNUM)
 118     return builtin_type (gdbarch)->builtin_func_ptr;
 119
 120   return builtin_type (gdbarch)->builtin_int;
 121 }
 122
 123 \f
 124 /* Fetch the instruction at PC.  */
 125
 126 unsigned long
 127 microblaze_fetch_instruction (CORE_ADDR pc)
 128 {
 129   enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch);
 130   gdb_byte buf[4];
 131
 132   /* If we can't read the instruction at PC, return zero.  */
 133   if (target_read_memory (pc, buf, sizeof (buf)))
 134     return 0;
 135
 136   return extract_unsigned_integer (buf, 4, byte_order);
 137 }
 138 \f
 139
 140 static CORE_ADDR
 141 microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
 142                             CORE_ADDR funcaddr,
 143                             struct value **args, int nargs,
 144                             struct type *value_type,
 145                             CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
 146                             struct regcache *regcache)
 147 {
 148   error (_("push_dummy_code not implemented"));
 149   return sp;
 150 }
 151
 152
 153 static CORE_ADDR
 154 microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 155                             struct regcache *regcache, CORE_ADDR bp_addr,
 156                             int nargs, struct value **args, CORE_ADDR sp,
 157                             int struct_return, CORE_ADDR struct_addr)
 158 {
 159   error (_("store_arguments not implemented"));
 160   return sp;
 161 }
 162
 163 static const gdb_byte *
 164 microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
 165                                int *len)
 166 {
 167   static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
 168
 169   *len = sizeof (break_insn);
 170   return break_insn;
 171 }
 172 \f
 173 /* Allocate and initialize a frame cache.  */
 174
 175 static struct microblaze_frame_cache *
 176 microblaze_alloc_frame_cache (void)
 177 {
 178   struct microblaze_frame_cache *cache;
 179   int i;
 180
 181   cache = FRAME_OBSTACK_ZALLOC (struct microblaze_frame_cache);
 182
 183   /* Base address.  */
 184   cache->base = 0;
 185   cache->pc = 0;
 186
 187   /* Frameless until proven otherwise.  */
 188   cache->frameless_p = 1;
 189
 190   return cache;
 191 }
 192
 193 /* The base of the current frame is actually in the stack pointer.
 194    This happens when there is no frame pointer (microblaze ABI does not
 195    require a frame pointer) or when we're stopped in the prologue or
 196    epilogue itself.  In these cases, microblaze_analyze_prologue will need
 197    to update fi->frame before returning or analyzing the register
 198    save instructions.  */
 199 #define MICROBLAZE_MY_FRAME_IN_SP 0x1
 200
 201 /* The base of the current frame is in a frame pointer register.
 202    This register is noted in frame_extra_info->fp_regnum.
 203
 204    Note that the existance of an FP might also indicate that the
 205    function has called alloca.  */
 206 #define MICROBLAZE_MY_FRAME_IN_FP 0x2
 207
 208 /* Function prologues on the Xilinx microblaze processors consist of:
 209
 210    - adjustments to the stack pointer (r1) (addi r1, r1, imm)
 211    - making a copy of r1 into another register (a "frame" pointer)
 212      (add r?, r1, r0)
 213    - store word/multiples that use r1 or the frame pointer as the
 214      base address (swi r?, r1, imm OR swi r?, fp, imm)
 215
 216    Note that microblaze really doesn't have a real frame pointer.
 217    Instead, the compiler may copy the SP into a register (usually
 218    r19) to act as an arg pointer.  For our target-dependent purposes,
 219    the frame info's "frame" member will be the beginning of the
 220    frame.  The SP could, in fact, point below this.
 221
 222    The prologue ends when an instruction fails to meet either of
 223    these criteria.  */
 224
 225 /* Analyze the prologue to determine where registers are saved,
 226    the end of the prologue, etc.  Return the address of the first line
 227    of "real" code (i.e., the end of the prologue). */
 228
 229 static CORE_ADDR
 230 microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
 231                              CORE_ADDR current_pc,
 232                              struct microblaze_frame_cache *cache)
 233 {
 234   char *name;
 235   CORE_ADDR func_addr, func_end, addr, stop, prologue_end_addr = 0;
 236   unsigned long insn;
 237   int rn, rd, ra, rb, imm;
 238   enum microblaze_instr op;
 239   int flags = 0;
 240   int save_hidden_pointer_found = 0;
 241   int non_stack_instruction_found = 0;
 242
 243   /* Find the start of this function. */
 244   find_pc_partial_function (pc, &name, &func_addr, &func_end);
 245   if (func_addr < pc)
 246     pc = func_addr;
 247
 248   if (current_pc < pc)
 249     return current_pc;
 250
 251    /* Initialize info about frame.  */
 252    cache->framesize = 0;
 253    cache->fp_regnum = MICROBLAZE_SP_REGNUM;
 254    cache->frameless_p = 1;
 255
 256   /* Start decoding the prologue.  We start by checking two special cases:
 257
 258      1. We're about to return
 259      2. We're at the first insn of the prologue.
 260
 261      If we're about to return, our frame has already been deallocated.
 262      If we are stopped at the first instruction of a prologue,
 263      then our frame has not yet been set up. */
 264
 265   /* Get the first insn from memory.  */
 266
 267   insn = microblaze_fetch_instruction (pc);
 268   op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
 269
 270   if (IS_RETURN(op))
 271     return pc;
 272
 273   /* Start at beginning of function and analyze until we get to the
 274      current pc, or the end of the function, whichever is first.  */
 275   stop = (current_pc < func_end ? current_pc : func_end);
 276
 277   microblaze_debug ("Scanning prologue: name=%s, func_addr=%s, stop=%s\n",
 278                     name, paddress (gdbarch, func_addr),
 279                     paddress (gdbarch, stop));
 280
 281   for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
 282     {
 283       insn = microblaze_fetch_instruction (addr);
 284       op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
 285       microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
 286
 287       /* This code is very sensitive to what functions are present in the
 288          prologue.  It assumes that the (addi, addik, swi, sw) can be the
 289          only instructions in the prologue.  */
 290       if (IS_UPDATE_SP(op, rd, ra))
 291         {
 292           microblaze_debug ("got addi r1,r1,%d; contnuing\n", imm);
 293           if (cache->framesize)
 294             break;      /* break if framesize already computed.  */
 295           cache->framesize = -imm; /* stack grows towards low memory.  */
 296           cache->frameless_p = 0; /* Frame found.  */
 297           save_hidden_pointer_found = 0;
 298           non_stack_instruction_found = 0;
 299           continue;
 300         }
 301       else if (IS_SPILL_SP(op, rd, ra))
 302         {
 303           /* Spill stack pointer.  */
 304           cache->register_offsets[rd] = imm; /* SP spilled before updating.  */
 305
 306           microblaze_debug ("swi r1 r1 %d, continuing\n", imm);
 307           save_hidden_pointer_found = 0;
 308           if (!cache->framesize)
 309             non_stack_instruction_found = 0;
 310           continue;
 311         }
 312       else if (IS_SPILL_REG(op, rd, ra))
 313         {
 314           /* Spill register.  */
 315           cache->register_offsets[rd] = imm - cache->framesize;
 316
 317           microblaze_debug ("swi %d r1 %d, continuing\n", rd, imm);
 318           save_hidden_pointer_found = 0;
 319           if (!cache->framesize)
 320             non_stack_instruction_found = 0;
 321           continue;
 322         }
 323       else if (IS_ALSO_SPILL_REG(op, rd, ra, rb))
 324         {
 325           /* Spill register.  */
 326           cache->register_offsets[rd] = 0 - cache->framesize;
 327
 328           microblaze_debug ("sw %d r0 r1, continuing\n", rd);
 329           save_hidden_pointer_found = 0;
 330           if (!cache->framesize)
 331             non_stack_instruction_found = 0;
 332           continue;
 333         }
 334       else if (IS_SETUP_FP(op, ra, rb))
 335         {
 336           /* We have a frame pointer.  Note the register which is
 337              acting as the frame pointer. */
 338           flags |= MICROBLAZE_MY_FRAME_IN_FP;
 339           flags &= ~MICROBLAZE_MY_FRAME_IN_SP;
 340           cache->fp_regnum = rd;
 341           microblaze_debug ("Found a frame pointer: r%d\n", cache->fp_regnum);
 342           save_hidden_pointer_found = 0;
 343           if (!cache->framesize)
 344             non_stack_instruction_found = 0;
 345           continue;
 346         }
 347       else if (IS_SPILL_REG_FP(op, rd, ra, cache->fp_regnum))
 348         {
 349           /* reg spilled after updating.  */
 350           cache->register_offsets[rd] = imm - cache->framesize;
 351
 352           microblaze_debug ("swi %d %d %d, continuing\n", rd, ra, imm);
 353           save_hidden_pointer_found = 0;
 354           if (!cache->framesize)
 355             non_stack_instruction_found = 0;
 356           continue;
 357         }
 358       else if (IS_SAVE_HIDDEN_PTR(op, rd, ra, rb))
 359         {
 360           /* If the first argument is a hidden pointer to the area where the
 361              return structure is to be saved, then it is saved as part of the
 362              prologue.  */
 363
 364           microblaze_debug ("add %d %d %d, continuing\n", rd, ra, rb);
 365           save_hidden_pointer_found = 1;
 366           if (!cache->framesize)
 367             non_stack_instruction_found = 0;
 368           continue;
 369         }
 370
 371       /* As a result of the modification in the next step where we continue
 372          to analyze the prologue till we reach a control flow instruction,
 373          we need another variable to store when exactly a non-stack
 374          instruction was encountered, which is the current definition
 375          of a prologue.  */
 376       if (!non_stack_instruction_found)
 377         prologue_end_addr = addr;
 378       non_stack_instruction_found = 1;
 379
 380       /* When optimizations are enabled, it is not guaranteed that prologue
 381          instructions are not mixed in with other instructions from the
 382          program. Some programs show this behavior at -O2. This can be
 383          avoided by adding -fno-schedule-insns2 switch as of now (edk 8.1)
 384          In such cases, we scan the function until we see the first control
 385          instruction.  */
 386
 387       {
 388         unsigned op = (unsigned)insn >> 26;
 389
 390         /* continue if not control flow (branch, return).  */
 391         if (op != 0x26 && op != 0x27 && op != 0x2d && op != 0x2e && op != 0x2f)
 392           continue;
 393         else if (op == 0x2c)
 394           continue;    /* continue if imm.  */
 395       }
 396
 397       /* This is not a prologue insn, so stop here. */
 398       microblaze_debug ("insn is not a prologue insn -- ending scan\n");
 399       break;
 400     }
 401
 402   microblaze_debug ("done analyzing prologue\n");
 403   microblaze_debug ("prologue end = 0x%x\n", (int) addr);
 404
 405   /* If the last instruction was an add rd, r5, r0 then don't count it as
 406      part of the prologue.  */
 407   if (save_hidden_pointer_found)
 408     prologue_end_addr -= INST_WORD_SIZE;
 409
 410   return prologue_end_addr;
 411 }
 412
 413 static CORE_ADDR
 414 microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 415 {
 416   gdb_byte buf[4];
 417   CORE_ADDR pc;
 418
 419   frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf);
 420   pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
 421   /* For sentinel frame, return address is actual PC.  For other frames,
 422      return address is pc+8.  This is a workaround because gcc does not
 423      generate correct return address in CIE.  */
 424   if (frame_relative_level (next_frame) >= 0)
 425     pc += 8;
 426   return pc;
 427 }
 428
 429 /* Return PC of first real instruction of the function starting at
 430    START_PC.  */
 431
 432 CORE_ADDR
 433 microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
 434 {
 435   struct symtab_and_line sal;
 436   CORE_ADDR func_start, func_end, ostart_pc;
 437   struct microblaze_frame_cache cache;
 438
 439   /* This is the preferred method, find the end of the prologue by
 440      using the debugging information.  Debugging info does not always
 441      give the right answer since parameters are stored on stack after this.
 442      Always analyze the prologue.  */
 443   if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
 444     {
 445       sal = find_pc_line (func_start, 0);
 446
 447       if (sal.end < func_end
 448           && start_pc <= sal.end)
 449         start_pc = sal.end;
 450     }
 451
 452   ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL,
 453                                            &cache);
 454
 455   if (ostart_pc > start_pc)
 456     return ostart_pc;
 457   return start_pc;
 458 }
 459
 460 /* Normal frames.  */
 461
 462 struct microblaze_frame_cache *
 463 microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
 464 {
 465   struct microblaze_frame_cache *cache;
 466   struct gdbarch *gdbarch = get_frame_arch (next_frame);
 467   CORE_ADDR func, pc, fp;
 468   int rn;
 469
 470   if (*this_cache)
 471     return *this_cache;
 472
 473   cache = microblaze_alloc_frame_cache ();
 474   *this_cache = cache;
 475   cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
 476
 477   /* Clear offsets to saved regs in frame.  */
 478   for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++)
 479     cache->register_offsets[rn] = -1;
 480
 481   func = get_frame_func (next_frame);
 482
 483   cache->pc = get_frame_address_in_block (next_frame);
 484
 485   return cache;
 486 }
 487
 488 static void
 489 microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
 490                        struct frame_id *this_id)
 491 {
 492   struct microblaze_frame_cache *cache =
 493     microblaze_frame_cache (next_frame, this_cache);
 494
 495   /* This marks the outermost frame.  */
 496   if (cache->base == 0)
 497     return;
 498
 499   (*this_id) = frame_id_build (cache->base, cache->pc);
 500 }
 501
 502 static struct value *
 503 microblaze_frame_prev_register (struct frame_info *this_frame,
 504                                  void **this_cache, int regnum)
 505 {
 506   struct microblaze_frame_cache *cache =
 507     microblaze_frame_cache (this_frame, this_cache);
 508
 509   if (cache->frameless_p)
 510     {
 511       if (regnum == MICROBLAZE_PC_REGNUM)
 512         regnum = 15;
 513       if (regnum == MICROBLAZE_SP_REGNUM)
 514         regnum = 1;
 515       return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
 516     }
 517   else
 518     return trad_frame_get_prev_register (this_frame, cache->saved_regs,
 519                                          regnum);
 520
 521 }
 522
 523 static const struct frame_unwind microblaze_frame_unwind =
 524 {
 525   NORMAL_FRAME,
 526   microblaze_frame_this_id,
 527   microblaze_frame_prev_register,
 528   NULL,
 529   default_frame_sniffer
 530 };
 531 \f
 532 static CORE_ADDR
 533 microblaze_frame_base_address (struct frame_info *next_frame, void **this_cache)
 534 {
 535   struct microblaze_frame_cache *cache =
 536     microblaze_frame_cache (next_frame, this_cache);
 537
 538   return cache->base;
 539 }
 540
 541 static const struct frame_base microblaze_frame_base =
 542 {
 543   &microblaze_frame_unwind,
 544   microblaze_frame_base_address,
 545   microblaze_frame_base_address,
 546   microblaze_frame_base_address
 547 };
 548 \f
 549 /* Extract from an array REGBUF containing the (raw) register state, a
 550    function return value of TYPE, and copy that into VALBUF.  */
 551 static void
 552 microblaze_extract_return_value (struct type *type, struct regcache *regcache,
 553                                  gdb_byte *valbuf)
 554 {
 555   gdb_byte buf[8];
 556
 557   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
 558   switch (TYPE_LENGTH (type))
 559     {
 560       case 1:   /* return last byte in the register.  */
 561         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 562         memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
 563         return;
 564       case 2:   /* return last 2 bytes in register.  */
 565         memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
 566         return;
 567       case 4:   /* for sizes 4 or 8, copy the required length.  */
 568       case 8:
 569         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 570         regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf+4);
 571         memcpy (valbuf, buf, TYPE_LENGTH (type));
 572         return;
 573       default:
 574         internal_error (__FILE__, __LINE__,
 575                         _("Unsupported return value size requested"));
 576     }
 577 }
 578
 579 /* Store the return value in VALBUF (of type TYPE) where the caller
 580    expects to see it.
 581
 582    Integers up to four bytes are stored in r3.
 583
 584    Longs are stored in r3 (most significant word) and r4 (least
 585    significant word).
 586
 587    Small structures are always returned on stack.
 588 */
 589
 590 static void
 591 microblaze_store_return_value (struct type *type, struct regcache *regcache,
 592                                const gdb_byte *valbuf)
 593 {
 594   int len = TYPE_LENGTH (type);
 595   gdb_byte buf[8];
 596
 597   memset (buf, 0, sizeof(buf));
 598
 599   /* Integral and pointer return values.  */
 600
 601   if (len > 4)
 602     {
 603        gdb_assert (len == 8);
 604        memcpy (buf, valbuf, 8);
 605        regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf + 4);
 606     }
 607   else
 608     /* ??? Do we need to do any sign-extension here?  */
 609     memcpy (buf + 4 - len, valbuf, len);
 610
 611   regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM, buf);
 612 }
 613
 614 static enum return_value_convention
 615 microblaze_return_value (struct gdbarch *gdbarch, struct type *func_type,
 616                          struct type *type, struct regcache *regcache,
 617                          gdb_byte *readbuf, const gdb_byte *writebuf)
 618 {
 619   if (readbuf)
 620     microblaze_extract_return_value (type, regcache, readbuf);
 621   if (writebuf)
 622     microblaze_store_return_value (type, regcache, writebuf);
 623
 624   return RETURN_VALUE_REGISTER_CONVENTION;
 625 }
 626
 627 static int
 628 microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
 629 {
 630   return (TYPE_LENGTH (type) == 16);
 631 }
 632
 633 static void
 634 microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
 635 {
 636   regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
 637 }
 638 \f
 639 static int dwarf2_to_reg_map[78] =
 640 { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
 641   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
 642   8  /* r8  */,   9  /* r9  */,  10  /* r10 */,  11  /* r11 */,  /*  8-11 */
 643   12 /* r12 */,  13  /* r13 */,  14  /* r14 */,  15  /* r15 */,  /* 12-15 */
 644   16 /* r16 */,  17  /* r17 */,  18  /* r18 */,  19  /* r19 */,  /* 16-19 */
 645   20 /* r20 */,  21  /* r21 */,  22  /* r22 */,  23  /* r23 */,  /* 20-23 */
 646   24 /* r24 */,  25  /* r25 */,  26  /* r26 */,  27  /* r27 */,  /* 24-25 */
 647   28 /* r28 */,  29  /* r29 */,  30  /* r30 */,  31  /* r31 */,  /* 28-31 */
 648   -1 /* $f0 */,  -1  /* $f1 */,  -1  /* $f2 */,  -1  /* $f3 */,  /* 32-35 */
 649   -1 /* $f4 */,  -1  /* $f5 */,  -1  /* $f6 */,  -1  /* $f7 */,  /* 36-39 */
 650   -1 /* $f8 */,  -1  /* $f9 */,  -1  /* $f10 */, -1  /* $f11 */, /* 40-43 */
 651   -1 /* $f12 */, -1  /* $f13 */, -1  /* $f14 */, -1  /* $f15 */, /* 44-47 */
 652   -1 /* $f16 */, -1  /* $f17 */, -1  /* $f18 */, -1  /* $f19 */, /* 48-51 */
 653   -1 /* $f20 */, -1  /* $f21 */, -1  /* $f22 */, -1  /* $f23 */, /* 52-55 */
 654   -1 /* $f24 */, -1  /* $f25 */, -1  /* $f26 */, -1  /* $f27 */, /* 56-59 */
 655   -1 /* $f28 */, -1  /* $f29 */, -1  /* $f30 */, -1  /* $f31 */, /* 60-63 */
 656   -1 /* hi   */, -1  /* lo   */, -1  /* accum*/, 33  /* rmsr */, /* 64-67 */
 657   -1 /* $fcc1*/, -1  /* $fcc2*/, -1  /* $fcc3*/, -1  /* $fcc4*/, /* 68-71 */
 658   -1 /* $fcc5*/, -1  /* $fcc6*/, -1  /* $fcc7*/, -1  /* $ap  */, /* 72-75 */
 659   -1 /* $rap */, -1  /* $frp */                                  /* 76-77 */
 660 };
 661
 662 static int
 663 microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 664 {
 665   gdb_assert (reg < sizeof (dwarf2_to_reg_map));
 666   return dwarf2_to_reg_map[reg];
 667 }
 668
 669 static struct gdbarch *
 670 microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 671 {
 672   struct gdbarch_tdep *tdep;
 673   struct gdbarch *gdbarch;
 674
 675   /* If there is already a candidate, use it.  */
 676   arches = gdbarch_list_lookup_by_info (arches, &info);
 677   if (arches != NULL)
 678     return arches->gdbarch;
 679
 680   /* Allocate space for the new architecture.  */
 681   tdep = XMALLOC (struct gdbarch_tdep);
 682   gdbarch = gdbarch_alloc (&info, tdep);
 683
 684   set_gdbarch_long_double_bit (gdbarch, 128);
 685
 686   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
 687   set_gdbarch_register_name (gdbarch, microblaze_register_name);
 688   set_gdbarch_register_type (gdbarch, microblaze_register_type);
 689
 690   /* Register numbers of various important registers.  */
 691   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM);
 692   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM);
 693
 694   /* Map Dwarf2 registers to GDB registers.  */
 695   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
 696
 697   /* Call dummy code.  */
 698   set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
 699   set_gdbarch_push_dummy_code (gdbarch, microblaze_push_dummy_code);
 700   set_gdbarch_push_dummy_call (gdbarch, microblaze_push_dummy_call);
 701
 702   set_gdbarch_return_value (gdbarch, microblaze_return_value);
 703   set_gdbarch_stabs_argument_has_addr
 704     (gdbarch, microblaze_stabs_argument_has_addr);
 705
 706   set_gdbarch_skip_prologue (gdbarch, microblaze_skip_prologue);
 707
 708   /* Stack grows downward.  */
 709   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 710
 711   set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
 712
 713   set_gdbarch_frame_args_skip (gdbarch, 8);
 714
 715   set_gdbarch_print_insn (gdbarch, print_insn_microblaze);
 716
 717   set_gdbarch_write_pc (gdbarch, microblaze_write_pc);
 718
 719   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
 720
 721   frame_base_set_default (gdbarch, &microblaze_frame_base);
 722
 723   /* Hook in ABI-specific overrides, if they have been registered.  */
 724   gdbarch_init_osabi (info, gdbarch);
 725
 726   /* Unwind the frame. */
 727   dwarf2_append_unwinders (gdbarch);
 728   frame_unwind_append_unwinder (gdbarch, &microblaze_frame_unwind);
 729   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
 730
 731   return gdbarch;
 732 }
 733
 734 /* Provide a prototype to silence -Wmissing-prototypes.  */
 735 void _initialize_microblaze_tdep (void);
 736
 737 void
 738 _initialize_microblaze_tdep (void)
 739 {
 740   register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init);
 741
 742   /* Debug this files internals.  */
 743   add_setshow_zinteger_cmd ("microblaze", class_maintenance,
 744                             &microblaze_debug_flag, _("\
 745 Set microblaze debugging."), _("\
 746 Show microblaze debugging."), _("\
 747 When non-zero, microblaze specific debugging is enabled."),
 748                             NULL,
 749                             NULL,
 750                             &setdebuglist, &showdebuglist);
 751
 752 }