1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_assert.h"
25 #include "mips-tdep.h"
28 #include "linux-nat.h"
29 #include "mips-linux-tdep.h"
30 #include "target-descriptions.h"
32 #include "gdb_proc_service.h"
36 #include <sys/ptrace.h>
37 #include <asm/ptrace.h>
39 #include "features/mips-linux.c"
40 #include "features/mips-dsp-linux.c"
41 #include "features/mips64-linux.c"
42 #include "features/mips64-dsp-linux.c"
44 #ifndef PTRACE_GET_THREAD_AREA
45 #define PTRACE_GET_THREAD_AREA 25
48 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
49 we'll clear this and use PTRACE_PEEKUSER instead. */
50 static int have_ptrace_regsets
= 1;
52 /* Whether or not to print the mirrored debug registers. */
54 static int maint_show_dr
;
56 /* Saved function pointers to fetch and store a single register using
57 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
59 static void (*super_fetch_registers
) (struct target_ops
*,
60 struct regcache
*, int);
61 static void (*super_store_registers
) (struct target_ops
*,
62 struct regcache
*, int);
64 static void (*super_close
) (void);
66 /* Map gdb internal register number to ptrace ``address''.
67 These ``addresses'' are normally defined in <asm/ptrace.h>.
69 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
70 and there's no point in reading or setting MIPS_ZERO_REGNUM.
71 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
74 mips_linux_register_addr (struct gdbarch
*gdbarch
, int regno
, int store
)
78 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
79 error (_("Bogon register number %d."), regno
);
81 if (regno
> MIPS_ZERO_REGNUM
&& regno
< MIPS_ZERO_REGNUM
+ 32)
83 else if ((regno
>= mips_regnum (gdbarch
)->fp0
)
84 && (regno
< mips_regnum (gdbarch
)->fp0
+ 32))
85 regaddr
= FPR_BASE
+ (regno
- mips_regnum (gdbarch
)->fp0
);
86 else if (regno
== mips_regnum (gdbarch
)->pc
)
88 else if (regno
== mips_regnum (gdbarch
)->cause
)
89 regaddr
= store
? (CORE_ADDR
) -1 : CAUSE
;
90 else if (regno
== mips_regnum (gdbarch
)->badvaddr
)
91 regaddr
= store
? (CORE_ADDR
) -1 : BADVADDR
;
92 else if (regno
== mips_regnum (gdbarch
)->lo
)
94 else if (regno
== mips_regnum (gdbarch
)->hi
)
96 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
98 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
99 regaddr
= store
? (CORE_ADDR
) -1 : FPC_EIR
;
100 else if (mips_regnum (gdbarch
)->dspacc
!= -1
101 && regno
>= mips_regnum (gdbarch
)->dspacc
102 && regno
< mips_regnum (gdbarch
)->dspacc
+ 6)
103 regaddr
= DSP_BASE
+ (regno
- mips_regnum (gdbarch
)->dspacc
);
104 else if (regno
== mips_regnum (gdbarch
)->dspctl
)
105 regaddr
= DSP_CONTROL
;
106 else if (mips_linux_restart_reg_p (gdbarch
) && regno
== MIPS_RESTART_REGNUM
)
109 regaddr
= (CORE_ADDR
) -1;
115 mips64_linux_register_addr (struct gdbarch
*gdbarch
, int regno
, int store
)
119 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
120 error (_("Bogon register number %d."), regno
);
122 if (regno
> MIPS_ZERO_REGNUM
&& regno
< MIPS_ZERO_REGNUM
+ 32)
124 else if ((regno
>= mips_regnum (gdbarch
)->fp0
)
125 && (regno
< mips_regnum (gdbarch
)->fp0
+ 32))
126 regaddr
= MIPS64_FPR_BASE
+ (regno
- gdbarch_fp0_regnum (gdbarch
));
127 else if (regno
== mips_regnum (gdbarch
)->pc
)
129 else if (regno
== mips_regnum (gdbarch
)->cause
)
130 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_CAUSE
;
131 else if (regno
== mips_regnum (gdbarch
)->badvaddr
)
132 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_BADVADDR
;
133 else if (regno
== mips_regnum (gdbarch
)->lo
)
134 regaddr
= MIPS64_MMLO
;
135 else if (regno
== mips_regnum (gdbarch
)->hi
)
136 regaddr
= MIPS64_MMHI
;
137 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
138 regaddr
= MIPS64_FPC_CSR
;
139 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
140 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_FPC_EIR
;
141 else if (mips_regnum (gdbarch
)->dspacc
!= -1
142 && regno
>= mips_regnum (gdbarch
)->dspacc
143 && regno
< mips_regnum (gdbarch
)->dspacc
+ 6)
144 regaddr
= DSP_BASE
+ (regno
- mips_regnum (gdbarch
)->dspacc
);
145 else if (regno
== mips_regnum (gdbarch
)->dspctl
)
146 regaddr
= DSP_CONTROL
;
147 else if (mips_linux_restart_reg_p (gdbarch
) && regno
== MIPS_RESTART_REGNUM
)
150 regaddr
= (CORE_ADDR
) -1;
155 /* Fetch the thread-local storage pointer for libthread_db. */
158 ps_get_thread_area (const struct ps_prochandle
*ph
,
159 lwpid_t lwpid
, int idx
, void **base
)
161 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
, NULL
, base
) != 0)
164 /* IDX is the bias from the thread pointer to the beginning of the
165 thread descriptor. It has to be subtracted due to implementation
166 quirks in libthread_db. */
167 *base
= (void *) ((char *)*base
- idx
);
172 /* Wrapper functions. These are only used by libthread_db. */
175 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
177 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
178 mips_supply_gregset (regcache
, (const mips_elf_gregset_t
*) gregsetp
);
180 mips64_supply_gregset (regcache
, (const mips64_elf_gregset_t
*) gregsetp
);
184 fill_gregset (const struct regcache
*regcache
,
185 gdb_gregset_t
*gregsetp
, int regno
)
187 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
188 mips_fill_gregset (regcache
, (mips_elf_gregset_t
*) gregsetp
, regno
);
190 mips64_fill_gregset (regcache
, (mips64_elf_gregset_t
*) gregsetp
, regno
);
194 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
196 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
197 mips_supply_fpregset (regcache
, (const mips_elf_fpregset_t
*) fpregsetp
);
199 mips64_supply_fpregset (regcache
,
200 (const mips64_elf_fpregset_t
*) fpregsetp
);
204 fill_fpregset (const struct regcache
*regcache
,
205 gdb_fpregset_t
*fpregsetp
, int regno
)
207 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
208 mips_fill_fpregset (regcache
, (mips_elf_fpregset_t
*) fpregsetp
, regno
);
210 mips64_fill_fpregset (regcache
,
211 (mips64_elf_fpregset_t
*) fpregsetp
, regno
);
215 /* Fetch REGNO (or all registers if REGNO == -1) from the target
216 using PTRACE_GETREGS et al. */
219 mips64_linux_regsets_fetch_registers (struct target_ops
*ops
,
220 struct regcache
*regcache
, int regno
)
222 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
228 if (regno
>= mips_regnum (gdbarch
)->fp0
229 && regno
<= mips_regnum (gdbarch
)->fp0
+ 32)
231 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
233 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
238 /* DSP registers are optional and not a part of any set. */
239 have_dsp
= mips_regnum (gdbarch
)->dspctl
!= -1;
242 else if (regno
>= mips_regnum (gdbarch
)->dspacc
243 && regno
< mips_regnum (gdbarch
)->dspacc
+ 6)
245 else if (regno
== mips_regnum (gdbarch
)->dspctl
)
250 tid
= ptid_get_lwp (inferior_ptid
);
252 tid
= ptid_get_pid (inferior_ptid
);
254 if (regno
== -1 || (!is_fp
&& !is_dsp
))
256 mips64_elf_gregset_t regs
;
258 if (ptrace (PTRACE_GETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
262 have_ptrace_regsets
= 0;
265 perror_with_name (_("Couldn't get registers"));
268 mips64_supply_gregset (regcache
,
269 (const mips64_elf_gregset_t
*) ®s
);
272 if (regno
== -1 || is_fp
)
274 mips64_elf_fpregset_t fp_regs
;
276 if (ptrace (PTRACE_GETFPREGS
, tid
, 0L,
277 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
281 have_ptrace_regsets
= 0;
284 perror_with_name (_("Couldn't get FP registers"));
287 mips64_supply_fpregset (regcache
,
288 (const mips64_elf_fpregset_t
*) &fp_regs
);
292 super_fetch_registers (ops
, regcache
, regno
);
293 else if (regno
== -1 && have_dsp
)
295 for (regi
= mips_regnum (gdbarch
)->dspacc
;
296 regi
< mips_regnum (gdbarch
)->dspacc
+ 6;
298 super_fetch_registers (ops
, regcache
, regi
);
299 super_fetch_registers (ops
, regcache
, mips_regnum (gdbarch
)->dspctl
);
303 /* Store REGNO (or all registers if REGNO == -1) to the target
304 using PTRACE_SETREGS et al. */
307 mips64_linux_regsets_store_registers (struct target_ops
*ops
,
308 struct regcache
*regcache
, int regno
)
310 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
316 if (regno
>= mips_regnum (gdbarch
)->fp0
317 && regno
<= mips_regnum (gdbarch
)->fp0
+ 32)
319 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
321 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
326 /* DSP registers are optional and not a part of any set. */
327 have_dsp
= mips_regnum (gdbarch
)->dspctl
!= -1;
330 else if (regno
>= mips_regnum (gdbarch
)->dspacc
331 && regno
< mips_regnum (gdbarch
)->dspacc
+ 6)
333 else if (regno
== mips_regnum (gdbarch
)->dspctl
)
338 tid
= ptid_get_lwp (inferior_ptid
);
340 tid
= ptid_get_pid (inferior_ptid
);
342 if (regno
== -1 || (!is_fp
&& !is_dsp
))
344 mips64_elf_gregset_t regs
;
346 if (ptrace (PTRACE_GETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
347 perror_with_name (_("Couldn't get registers"));
349 mips64_fill_gregset (regcache
, ®s
, regno
);
351 if (ptrace (PTRACE_SETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
352 perror_with_name (_("Couldn't set registers"));
355 if (regno
== -1 || is_fp
)
357 mips64_elf_fpregset_t fp_regs
;
359 if (ptrace (PTRACE_GETFPREGS
, tid
, 0L,
360 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
361 perror_with_name (_("Couldn't get FP registers"));
363 mips64_fill_fpregset (regcache
, &fp_regs
, regno
);
365 if (ptrace (PTRACE_SETFPREGS
, tid
, 0L,
366 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
367 perror_with_name (_("Couldn't set FP registers"));
371 super_store_registers (ops
, regcache
, regno
);
372 else if (regno
== -1 && have_dsp
)
374 for (regi
= mips_regnum (gdbarch
)->dspacc
;
375 regi
< mips_regnum (gdbarch
)->dspacc
+ 6;
377 super_store_registers (ops
, regcache
, regi
);
378 super_store_registers (ops
, regcache
, mips_regnum (gdbarch
)->dspctl
);
382 /* Fetch REGNO (or all registers if REGNO == -1) from the target
383 using any working method. */
386 mips64_linux_fetch_registers (struct target_ops
*ops
,
387 struct regcache
*regcache
, int regnum
)
389 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
390 if (have_ptrace_regsets
)
391 mips64_linux_regsets_fetch_registers (ops
, regcache
, regnum
);
393 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
394 back to PTRACE_PEEKUSER. */
395 if (!have_ptrace_regsets
)
396 super_fetch_registers (ops
, regcache
, regnum
);
399 /* Store REGNO (or all registers if REGNO == -1) to the target
400 using any working method. */
403 mips64_linux_store_registers (struct target_ops
*ops
,
404 struct regcache
*regcache
, int regnum
)
406 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
407 if (have_ptrace_regsets
)
408 mips64_linux_regsets_store_registers (ops
, regcache
, regnum
);
410 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
411 back to PTRACE_PEEKUSER. */
412 if (!have_ptrace_regsets
)
413 super_store_registers (ops
, regcache
, regnum
);
416 /* Return the address in the core dump or inferior of register
420 mips_linux_register_u_offset (struct gdbarch
*gdbarch
, int regno
, int store_p
)
422 if (mips_abi_regsize (gdbarch
) == 8)
423 return mips64_linux_register_addr (gdbarch
, regno
, store_p
);
425 return mips_linux_register_addr (gdbarch
, regno
, store_p
);
428 static const struct target_desc
*
429 mips_linux_read_description (struct target_ops
*ops
)
431 static int have_dsp
= -1;
437 tid
= ptid_get_lwp (inferior_ptid
);
439 tid
= ptid_get_pid (inferior_ptid
);
441 ptrace (PTRACE_PEEKUSER
, tid
, DSP_CONTROL
, 0);
451 perror_with_name (_("Couldn't check DSP support"));
456 /* Report that target registers are a size we know for sure
457 that we can get from ptrace. */
458 if (_MIPS_SIM
== _ABIO32
)
459 return have_dsp
? tdesc_mips_dsp_linux
: tdesc_mips_linux
;
461 return have_dsp
? tdesc_mips64_dsp_linux
: tdesc_mips64_linux
;
464 #define MAX_DEBUG_REGISTER 8
466 /* If macro PTRACE_GET_WATCH_REGS is not defined, kernel header doesn't
467 have hardware watchpoint-related structures. Define them below. */
469 #ifndef PTRACE_GET_WATCH_REGS
470 # define PTRACE_GET_WATCH_REGS 0xd0
471 # define PTRACE_SET_WATCH_REGS 0xd1
473 enum pt_watch_style
{
474 pt_watch_style_mips32
,
475 pt_watch_style_mips64
478 /* A value of zero in a watchlo indicates that it is available. */
480 struct mips32_watch_regs
482 uint32_t watchlo
[MAX_DEBUG_REGISTER
];
483 /* Lower 16 bits of watchhi. */
484 uint16_t watchhi
[MAX_DEBUG_REGISTER
];
485 /* Valid mask and I R W bits.
486 * bit 0 -- 1 if W bit is usable.
487 * bit 1 -- 1 if R bit is usable.
488 * bit 2 -- 1 if I bit is usable.
489 * bits 3 - 11 -- Valid watchhi mask bits.
491 uint16_t watch_masks
[MAX_DEBUG_REGISTER
];
492 /* The number of valid watch register pairs. */
494 /* There is confusion across gcc versions about structure alignment,
495 so we force 8 byte alignment for these structures so they match
496 the kernel even if it was build with a different gcc version. */
497 } __attribute__ ((aligned (8)));
499 struct mips64_watch_regs
501 uint64_t watchlo
[MAX_DEBUG_REGISTER
];
502 uint16_t watchhi
[MAX_DEBUG_REGISTER
];
503 uint16_t watch_masks
[MAX_DEBUG_REGISTER
];
505 } __attribute__ ((aligned (8)));
509 enum pt_watch_style style
;
512 struct mips32_watch_regs mips32
;
513 struct mips64_watch_regs mips64
;
517 #endif /* !PTRACE_GET_WATCH_REGS */
523 #define W_MASK (1 << W_BIT)
524 #define R_MASK (1 << R_BIT)
525 #define I_MASK (1 << I_BIT)
527 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
529 /* -1 if the kernel and/or CPU do not support watch registers.
530 1 if watch_readback is valid and we can read style, num_valid
532 0 if we need to read the watch_readback. */
534 static int watch_readback_valid
;
536 /* Cached watch register read values. */
538 static struct pt_watch_regs watch_readback
;
540 /* We keep list of all watchpoints we should install and calculate the
541 watch register values each time the list changes. This allows for
542 easy sharing of watch registers for more than one watchpoint. */
544 struct mips_watchpoint
549 struct mips_watchpoint
*next
;
552 static struct mips_watchpoint
*current_watches
;
554 /* The current set of watch register values for writing the
557 static struct pt_watch_regs watch_mirror
;
559 /* Assuming usable watch registers REGS, return the irw_mask of
563 mips_linux_watch_get_irw_mask (struct pt_watch_regs
*regs
, int n
)
567 case pt_watch_style_mips32
:
568 return regs
->mips32
.watch_masks
[n
] & IRW_MASK
;
569 case pt_watch_style_mips64
:
570 return regs
->mips64
.watch_masks
[n
] & IRW_MASK
;
572 internal_error (__FILE__
, __LINE__
,
573 _("Unrecognized watch register style"));
577 /* Assuming usable watch registers REGS, return the reg_mask of
581 get_reg_mask (struct pt_watch_regs
*regs
, int n
)
585 case pt_watch_style_mips32
:
586 return regs
->mips32
.watch_masks
[n
] & ~IRW_MASK
;
587 case pt_watch_style_mips64
:
588 return regs
->mips64
.watch_masks
[n
] & ~IRW_MASK
;
590 internal_error (__FILE__
, __LINE__
,
591 _("Unrecognized watch register style"));
595 /* Assuming usable watch registers REGS, return the num_valid. */
598 mips_linux_watch_get_num_valid (struct pt_watch_regs
*regs
)
602 case pt_watch_style_mips32
:
603 return regs
->mips32
.num_valid
;
604 case pt_watch_style_mips64
:
605 return regs
->mips64
.num_valid
;
607 internal_error (__FILE__
, __LINE__
,
608 _("Unrecognized watch register style"));
612 /* Assuming usable watch registers REGS, return the watchlo of
616 mips_linux_watch_get_watchlo (struct pt_watch_regs
*regs
, int n
)
620 case pt_watch_style_mips32
:
621 return regs
->mips32
.watchlo
[n
];
622 case pt_watch_style_mips64
:
623 return regs
->mips64
.watchlo
[n
];
625 internal_error (__FILE__
, __LINE__
,
626 _("Unrecognized watch register style"));
630 /* Assuming usable watch registers REGS, set watchlo of register N to
634 mips_linux_watch_set_watchlo (struct pt_watch_regs
*regs
, int n
,
639 case pt_watch_style_mips32
:
640 /* The cast will never throw away bits as 64 bit addresses can
641 never be used on a 32 bit kernel. */
642 regs
->mips32
.watchlo
[n
] = (uint32_t) value
;
644 case pt_watch_style_mips64
:
645 regs
->mips64
.watchlo
[n
] = value
;
648 internal_error (__FILE__
, __LINE__
,
649 _("Unrecognized watch register style"));
653 /* Assuming usable watch registers REGS, return the watchhi of
657 mips_linux_watch_get_watchhi (struct pt_watch_regs
*regs
, int n
)
661 case pt_watch_style_mips32
:
662 return regs
->mips32
.watchhi
[n
];
663 case pt_watch_style_mips64
:
664 return regs
->mips64
.watchhi
[n
];
666 internal_error (__FILE__
, __LINE__
,
667 _("Unrecognized watch register style"));
671 /* Assuming usable watch registers REGS, set watchhi of register N to
675 mips_linux_watch_set_watchhi (struct pt_watch_regs
*regs
, int n
,
680 case pt_watch_style_mips32
:
681 regs
->mips32
.watchhi
[n
] = value
;
683 case pt_watch_style_mips64
:
684 regs
->mips64
.watchhi
[n
] = value
;
687 internal_error (__FILE__
, __LINE__
,
688 _("Unrecognized watch register style"));
693 mips_show_dr (const char *func
, CORE_ADDR addr
,
694 int len
, enum target_hw_bp_type type
)
698 puts_unfiltered (func
);
700 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
701 paddress (target_gdbarch (), addr
), len
,
702 type
== hw_write
? "data-write"
703 : (type
== hw_read
? "data-read"
704 : (type
== hw_access
? "data-read/write"
705 : (type
== hw_execute
? "instruction-execute"
707 puts_unfiltered (":\n");
709 for (i
= 0; i
< MAX_DEBUG_REGISTER
; i
++)
710 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i
,
711 paddress (target_gdbarch (),
712 mips_linux_watch_get_watchlo (&watch_mirror
,
714 paddress (target_gdbarch (),
715 mips_linux_watch_get_watchhi (&watch_mirror
,
719 /* Read the watch registers of process LWPID and store it in
720 WATCH_READBACK. Save true to *WATCH_READBACK_VALID if watch
721 registers are valid. Return 1 if watch registers are usable.
722 Cached information is used unless FORCE is true. */
725 mips_linux_read_watch_registers (long lwpid
,
726 struct pt_watch_regs
*watch_readback
,
727 int *watch_readback_valid
, int force
)
729 if (force
|| *watch_readback_valid
== 0)
731 if (ptrace (PTRACE_GET_WATCH_REGS
, lwpid
, watch_readback
) == -1)
733 *watch_readback_valid
= -1;
736 switch (watch_readback
->style
)
738 case pt_watch_style_mips32
:
739 if (watch_readback
->mips32
.num_valid
== 0)
741 *watch_readback_valid
= -1;
745 case pt_watch_style_mips64
:
746 if (watch_readback
->mips64
.num_valid
== 0)
748 *watch_readback_valid
= -1;
753 *watch_readback_valid
= -1;
756 /* Watch registers appear to be usable. */
757 *watch_readback_valid
= 1;
759 return (*watch_readback_valid
== 1) ? 1 : 0;
762 /* Convert GDB's TYPE to an IRW mask. */
765 mips_linux_watch_type_to_irw (int type
)
774 return (W_MASK
| R_MASK
);
780 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
781 handle the specified watch type. */
784 mips_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
787 uint32_t wanted_mask
, irw_mask
;
789 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid
),
791 &watch_readback_valid
, 0))
796 case bp_hardware_watchpoint
:
797 wanted_mask
= W_MASK
;
799 case bp_read_watchpoint
:
800 wanted_mask
= R_MASK
;
802 case bp_access_watchpoint
:
803 wanted_mask
= R_MASK
| W_MASK
;
810 i
< mips_linux_watch_get_num_valid (&watch_readback
) && cnt
;
813 irw_mask
= mips_linux_watch_get_irw_mask (&watch_readback
, i
);
814 if ((irw_mask
& wanted_mask
) == wanted_mask
)
817 return (cnt
== 0) ? 1 : 0;
820 /* Target to_stopped_by_watchpoint implementation. Return 1 if
821 stopped by watchpoint. The watchhi R and W bits indicate the watch
822 register triggered. */
825 mips_linux_stopped_by_watchpoint (void)
830 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid
),
832 &watch_readback_valid
, 1))
835 num_valid
= mips_linux_watch_get_num_valid (&watch_readback
);
837 for (n
= 0; n
< MAX_DEBUG_REGISTER
&& n
< num_valid
; n
++)
838 if (mips_linux_watch_get_watchhi (&watch_readback
, n
) & (R_MASK
| W_MASK
))
844 /* Target to_stopped_data_address implementation. Set the address
845 where the watch triggered (if known). Return 1 if the address was
849 mips_linux_stopped_data_address (struct target_ops
*t
, CORE_ADDR
*paddr
)
851 /* On mips we don't know the low order 3 bits of the data address,
852 so we must return false. */
856 /* Set any low order bits in MASK that are not set. */
859 fill_mask (CORE_ADDR mask
)
863 while (f
&& f
< mask
)
871 /* Try to add a single watch to the specified registers REGS. The
872 address of added watch is ADDR, the length is LEN, and the mask
873 is IRW. Return 1 on success, 0 on failure. */
876 mips_linux_watch_try_one_watch (struct pt_watch_regs
*regs
,
877 CORE_ADDR addr
, int len
, uint32_t irw
)
879 CORE_ADDR base_addr
, last_byte
, break_addr
, segment_len
;
880 CORE_ADDR mask_bits
, t_low
;
883 struct pt_watch_regs regs_copy
;
888 last_byte
= addr
+ len
- 1;
889 mask_bits
= fill_mask (addr
^ last_byte
) | IRW_MASK
;
890 base_addr
= addr
& ~mask_bits
;
892 /* Check to see if it is covered by current registers. */
893 for (i
= 0; i
< mips_linux_watch_get_num_valid (regs
); i
++)
895 t_low
= mips_linux_watch_get_watchlo (regs
, i
);
896 if (t_low
!= 0 && irw
== ((uint32_t) t_low
& irw
))
898 t_hi
= mips_linux_watch_get_watchhi (regs
, i
) | IRW_MASK
;
899 t_low
&= ~(CORE_ADDR
) t_hi
;
900 if (addr
>= t_low
&& last_byte
<= (t_low
+ t_hi
))
904 /* Try to find an empty register. */
906 for (i
= 0; i
< mips_linux_watch_get_num_valid (regs
); i
++)
908 t_low
= mips_linux_watch_get_watchlo (regs
, i
);
910 && irw
== (mips_linux_watch_get_irw_mask (regs
, i
) & irw
))
912 if (mask_bits
<= (get_reg_mask (regs
, i
) | IRW_MASK
))
914 /* It fits, we'll take it. */
915 mips_linux_watch_set_watchlo (regs
, i
, base_addr
| irw
);
916 mips_linux_watch_set_watchhi (regs
, i
, mask_bits
& ~IRW_MASK
);
921 /* It doesn't fit, but has the proper IRW capabilities. */
926 if (free_watches
> 1)
928 /* Try to split it across several registers. */
930 for (i
= 0; i
< mips_linux_watch_get_num_valid (®s_copy
); i
++)
932 t_low
= mips_linux_watch_get_watchlo (®s_copy
, i
);
933 t_hi
= get_reg_mask (®s_copy
, i
) | IRW_MASK
;
934 if (t_low
== 0 && irw
== (t_hi
& irw
))
936 t_low
= addr
& ~(CORE_ADDR
) t_hi
;
937 break_addr
= t_low
+ t_hi
+ 1;
938 if (break_addr
>= addr
+ len
)
941 segment_len
= break_addr
- addr
;
942 mask_bits
= fill_mask (addr
^ (addr
+ segment_len
- 1));
943 mips_linux_watch_set_watchlo (®s_copy
, i
,
944 (addr
& ~mask_bits
) | irw
);
945 mips_linux_watch_set_watchhi (®s_copy
, i
,
946 mask_bits
& ~IRW_MASK
);
947 if (break_addr
>= addr
+ len
)
952 len
= addr
+ len
- break_addr
;
957 /* It didn't fit anywhere, we failed. */
961 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
962 the specified region can be covered by the watch registers. */
965 mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
967 struct pt_watch_regs dummy_regs
;
970 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid
),
972 &watch_readback_valid
, 0))
975 dummy_regs
= watch_readback
;
976 /* Clear them out. */
977 for (i
= 0; i
< mips_linux_watch_get_num_valid (&dummy_regs
); i
++)
978 mips_linux_watch_set_watchlo (&dummy_regs
, i
, 0);
979 return mips_linux_watch_try_one_watch (&dummy_regs
, addr
, len
, 0);
982 /* Write the mirrored watch register values for each thread. */
985 write_watchpoint_regs (void)
992 tid
= ptid_get_lwp (lp
->ptid
);
993 if (ptrace (PTRACE_SET_WATCH_REGS
, tid
, &watch_mirror
) == -1)
994 perror_with_name (_("Couldn't write debug register"));
999 /* linux_nat new_thread implementation. Write the mirrored watch
1000 register values for the new thread. */
1003 mips_linux_new_thread (struct lwp_info
*lp
)
1007 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid
),
1009 &watch_readback_valid
, 0))
1012 tid
= ptid_get_lwp (lp
->ptid
);
1013 if (ptrace (PTRACE_SET_WATCH_REGS
, tid
, &watch_mirror
) == -1)
1014 perror_with_name (_("Couldn't write debug register"));
1017 /* Fill in the watch registers REGS with the currently cached
1018 watches CURRENT_WATCHES. */
1021 mips_linux_watch_populate_regs (struct mips_watchpoint
*current_watches
,
1022 struct pt_watch_regs
*regs
)
1024 struct mips_watchpoint
*w
;
1027 /* Clear them out. */
1028 for (i
= 0; i
< mips_linux_watch_get_num_valid (regs
); i
++)
1030 mips_linux_watch_set_watchlo (regs
, i
, 0);
1031 mips_linux_watch_set_watchhi (regs
, i
, 0);
1034 w
= current_watches
;
1037 uint32_t irw
= mips_linux_watch_type_to_irw (w
->type
);
1039 i
= mips_linux_watch_try_one_watch (regs
, w
->addr
, w
->len
, irw
);
1040 /* They must all fit, because we previously calculated that they
1047 /* Target to_insert_watchpoint implementation. Try to insert a new
1048 watch. Return zero on success. */
1051 mips_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int type
,
1052 struct expression
*cond
)
1054 struct pt_watch_regs regs
;
1055 struct mips_watchpoint
*new_watch
;
1056 struct mips_watchpoint
**pw
;
1061 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid
),
1063 &watch_readback_valid
, 0))
1069 regs
= watch_readback
;
1070 /* Add the current watches. */
1071 mips_linux_watch_populate_regs (current_watches
, ®s
);
1073 /* Now try to add the new watch. */
1074 if (!mips_linux_watch_try_one_watch (®s
, addr
, len
,
1075 mips_linux_watch_type_to_irw (type
)))
1078 /* It fit. Stick it on the end of the list. */
1079 new_watch
= (struct mips_watchpoint
*)
1080 xmalloc (sizeof (struct mips_watchpoint
));
1081 new_watch
->addr
= addr
;
1082 new_watch
->len
= len
;
1083 new_watch
->type
= type
;
1084 new_watch
->next
= NULL
;
1086 pw
= ¤t_watches
;
1091 watch_mirror
= regs
;
1092 retval
= write_watchpoint_regs ();
1095 mips_show_dr ("insert_watchpoint", addr
, len
, type
);
1100 /* Target to_remove_watchpoint implementation. Try to remove a watch.
1101 Return zero on success. */
1104 mips_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int type
,
1105 struct expression
*cond
)
1110 struct mips_watchpoint
**pw
;
1111 struct mips_watchpoint
*w
;
1113 /* Search for a known watch that matches. Then unlink and free
1116 pw
= ¤t_watches
;
1119 if (w
->addr
== addr
&& w
->len
== len
&& w
->type
== type
)
1130 return -1; /* We don't know about it, fail doing nothing. */
1132 /* At this point watch_readback is known to be valid because we
1133 could not have added the watch without reading it. */
1134 gdb_assert (watch_readback_valid
== 1);
1136 watch_mirror
= watch_readback
;
1137 mips_linux_watch_populate_regs (current_watches
, &watch_mirror
);
1139 retval
= write_watchpoint_regs ();
1142 mips_show_dr ("remove_watchpoint", addr
, len
, type
);
1147 /* Target to_close implementation. Free any watches and call the
1148 super implementation. */
1151 mips_linux_close (void)
1153 struct mips_watchpoint
*w
;
1154 struct mips_watchpoint
*nw
;
1156 /* Clean out the current_watches list. */
1157 w
= current_watches
;
1164 current_watches
= NULL
;
1170 void _initialize_mips_linux_nat (void);
1173 _initialize_mips_linux_nat (void)
1175 struct target_ops
*t
;
1177 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
1178 &maint_show_dr
, _("\
1179 Set whether to show variables that mirror the mips debug registers."), _("\
1180 Show whether to show variables that mirror the mips debug registers."), _("\
1181 Use \"on\" to enable, \"off\" to disable.\n\
1182 If enabled, the debug registers values are shown when GDB inserts\n\
1183 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1184 triggers a breakpoint or watchpoint."),
1187 &maintenance_set_cmdlist
,
1188 &maintenance_show_cmdlist
);
1190 t
= linux_trad_target (mips_linux_register_u_offset
);
1192 super_close
= t
->to_close
;
1193 t
->to_close
= mips_linux_close
;
1195 super_fetch_registers
= t
->to_fetch_registers
;
1196 super_store_registers
= t
->to_store_registers
;
1198 t
->to_fetch_registers
= mips64_linux_fetch_registers
;
1199 t
->to_store_registers
= mips64_linux_store_registers
;
1201 t
->to_can_use_hw_breakpoint
= mips_linux_can_use_hw_breakpoint
;
1202 t
->to_remove_watchpoint
= mips_linux_remove_watchpoint
;
1203 t
->to_insert_watchpoint
= mips_linux_insert_watchpoint
;
1204 t
->to_stopped_by_watchpoint
= mips_linux_stopped_by_watchpoint
;
1205 t
->to_stopped_data_address
= mips_linux_stopped_data_address
;
1206 t
->to_region_ok_for_hw_watchpoint
= mips_linux_region_ok_for_hw_watchpoint
;
1208 t
->to_read_description
= mips_linux_read_description
;
1210 linux_nat_add_target (t
);
1211 linux_nat_set_new_thread (t
, mips_linux_new_thread
);
1213 /* Initialize the standard target descriptions. */
1214 initialize_tdesc_mips_linux ();
1215 initialize_tdesc_mips_dsp_linux ();
1216 initialize_tdesc_mips64_linux ();
1217 initialize_tdesc_mips64_dsp_linux ();