gdb/mips-linux-nat.c

   1 /* Native-dependent code for GNU/Linux on MIPS processors.
   2
   3    Copyright (C) 2001-2018 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "defs.h"
  21 #include "command.h"
  22 #include "gdbcmd.h"
  23 #include "inferior.h"
  24 #include "mips-tdep.h"
  25 #include "target.h"
  26 #include "regcache.h"
  27 #include "linux-nat-trad.h"
  28 #include "mips-linux-tdep.h"
  29 #include "target-descriptions.h"
  30
  31 #include "gdb_proc_service.h"
  32 #include "gregset.h"
  33
  34 #include <sgidefs.h>
  35 #include "nat/gdb_ptrace.h"
  36 #include <asm/ptrace.h>
  37 #include "inf-ptrace.h"
  38
  39 #include "nat/mips-linux-watch.h"
  40
  41 #ifndef PTRACE_GET_THREAD_AREA
  42 #define PTRACE_GET_THREAD_AREA 25
  43 #endif
  44
  45 class mips_linux_nat_target final : public linux_nat_trad_target
  46 {
  47 public:
  48   /* Add our register access methods.  */
  49   void fetch_registers (struct regcache *, int) override;
  50   void store_registers (struct regcache *, int) override;
  51
  52   void close () override;
  53
  54   int can_use_hw_breakpoint (enum bptype, int, int) override;
  55
  56   int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  57                          struct expression *) override;
  58
  59   int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  60                          struct expression *) override;
  61
  62   bool stopped_by_watchpoint () override;
  63
  64   bool stopped_data_address (CORE_ADDR *) override;
  65
  66   int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
  67
  68   const struct target_desc *read_description () override;
  69
  70 protected:
  71   /* Override linux_nat_trad_target methods.  */
  72   CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
  73                                int regno, int store_p) override;
  74
  75   /* Override linux_nat_target low methods.  */
  76   void low_new_thread (struct lwp_info *lp) override;
  77
  78 private:
  79   /* Helpers.  See definitions.  */
  80   void mips64_regsets_store_registers (struct regcache *regcache,
  81                                        int regno);
  82   void mips64_regsets_fetch_registers (struct regcache *regcache,
  83                                        int regno);
  84 };
  85
  86 static mips_linux_nat_target the_mips_linux_nat_target;
  87
  88 /* Assume that we have PTRACE_GETREGS et al. support.  If we do not,
  89    we'll clear this and use PTRACE_PEEKUSER instead.  */
  90 static int have_ptrace_regsets = 1;
  91
  92 /* Map gdb internal register number to ptrace ``address''.
  93    These ``addresses'' are normally defined in <asm/ptrace.h>.
  94
  95    ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
  96    and there's no point in reading or setting MIPS_ZERO_REGNUM.
  97    We also can not set BADVADDR, CAUSE, or FCRIR via ptrace().  */
  98
  99 static CORE_ADDR
 100 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
 101 {
 102   CORE_ADDR regaddr;
 103
 104   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 105     error (_("Bogon register number %d."), regno);
 106
 107   if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
 108     regaddr = regno;
 109   else if ((regno >= mips_regnum (gdbarch)->fp0)
 110            && (regno < mips_regnum (gdbarch)->fp0 + 32))
 111     regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
 112   else if (regno == mips_regnum (gdbarch)->pc)
 113     regaddr = PC;
 114   else if (regno == mips_regnum (gdbarch)->cause)
 115     regaddr = store? (CORE_ADDR) -1 : CAUSE;
 116   else if (regno == mips_regnum (gdbarch)->badvaddr)
 117     regaddr = store? (CORE_ADDR) -1 : BADVADDR;
 118   else if (regno == mips_regnum (gdbarch)->lo)
 119     regaddr = MMLO;
 120   else if (regno == mips_regnum (gdbarch)->hi)
 121     regaddr = MMHI;
 122   else if (regno == mips_regnum (gdbarch)->fp_control_status)
 123     regaddr = FPC_CSR;
 124   else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
 125     regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
 126   else if (mips_regnum (gdbarch)->dspacc != -1
 127            && regno >= mips_regnum (gdbarch)->dspacc
 128            && regno < mips_regnum (gdbarch)->dspacc + 6)
 129     regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
 130   else if (regno == mips_regnum (gdbarch)->dspctl)
 131     regaddr = DSP_CONTROL;
 132   else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
 133     regaddr = 0;
 134   else
 135     regaddr = (CORE_ADDR) -1;
 136
 137   return regaddr;
 138 }
 139
 140 static CORE_ADDR
 141 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
 142 {
 143   CORE_ADDR regaddr;
 144
 145   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 146     error (_("Bogon register number %d."), regno);
 147
 148   if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
 149     regaddr = regno;
 150   else if ((regno >= mips_regnum (gdbarch)->fp0)
 151            && (regno < mips_regnum (gdbarch)->fp0 + 32))
 152     regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
 153   else if (regno == mips_regnum (gdbarch)->pc)
 154     regaddr = MIPS64_PC;
 155   else if (regno == mips_regnum (gdbarch)->cause)
 156     regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
 157   else if (regno == mips_regnum (gdbarch)->badvaddr)
 158     regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
 159   else if (regno == mips_regnum (gdbarch)->lo)
 160     regaddr = MIPS64_MMLO;
 161   else if (regno == mips_regnum (gdbarch)->hi)
 162     regaddr = MIPS64_MMHI;
 163   else if (regno == mips_regnum (gdbarch)->fp_control_status)
 164     regaddr = MIPS64_FPC_CSR;
 165   else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
 166     regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
 167   else if (mips_regnum (gdbarch)->dspacc != -1
 168            && regno >= mips_regnum (gdbarch)->dspacc
 169            && regno < mips_regnum (gdbarch)->dspacc + 6)
 170     regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
 171   else if (regno == mips_regnum (gdbarch)->dspctl)
 172     regaddr = DSP_CONTROL;
 173   else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
 174     regaddr = 0;
 175   else
 176     regaddr = (CORE_ADDR) -1;
 177
 178   return regaddr;
 179 }
 180
 181 /* Fetch the thread-local storage pointer for libthread_db.  */
 182
 183 ps_err_e
 184 ps_get_thread_area (struct ps_prochandle *ph,
 185                     lwpid_t lwpid, int idx, void **base)
 186 {
 187   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 188     return PS_ERR;
 189
 190   /* IDX is the bias from the thread pointer to the beginning of the
 191      thread descriptor.  It has to be subtracted due to implementation
 192      quirks in libthread_db.  */
 193   *base = (void *) ((char *)*base - idx);
 194
 195   return PS_OK;
 196 }
 197
 198 /* Wrapper functions.  These are only used by libthread_db.  */
 199
 200 void
 201 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
 202 {
 203   if (mips_isa_regsize (regcache->arch ()) == 4)
 204     mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
 205   else
 206     mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
 207 }
 208
 209 void
 210 fill_gregset (const struct regcache *regcache,
 211               gdb_gregset_t *gregsetp, int regno)
 212 {
 213   if (mips_isa_regsize (regcache->arch ()) == 4)
 214     mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
 215   else
 216     mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
 217 }
 218
 219 void
 220 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
 221 {
 222   if (mips_isa_regsize (regcache->arch ()) == 4)
 223     mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
 224   else
 225     mips64_supply_fpregset (regcache,
 226                             (const mips64_elf_fpregset_t *) fpregsetp);
 227 }
 228
 229 void
 230 fill_fpregset (const struct regcache *regcache,
 231                gdb_fpregset_t *fpregsetp, int regno)
 232 {
 233   if (mips_isa_regsize (regcache->arch ()) == 4)
 234     mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
 235   else
 236     mips64_fill_fpregset (regcache,
 237                           (mips64_elf_fpregset_t *) fpregsetp, regno);
 238 }
 239
 240
 241 /* Fetch REGNO (or all registers if REGNO == -1) from the target
 242    using PTRACE_GETREGS et al.  */
 243
 244 void
 245 mips_linux_nat_target::mips64_regsets_fetch_registers
 246   (struct regcache *regcache, int regno)
 247 {
 248   struct gdbarch *gdbarch = regcache->arch ();
 249   int is_fp, is_dsp;
 250   int have_dsp;
 251   int regi;
 252   int tid;
 253
 254   if (regno >= mips_regnum (gdbarch)->fp0
 255       && regno <= mips_regnum (gdbarch)->fp0 + 32)
 256     is_fp = 1;
 257   else if (regno == mips_regnum (gdbarch)->fp_control_status)
 258     is_fp = 1;
 259   else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
 260     is_fp = 1;
 261   else
 262     is_fp = 0;
 263
 264   /* DSP registers are optional and not a part of any set.  */
 265   have_dsp = mips_regnum (gdbarch)->dspctl != -1;
 266   if (!have_dsp)
 267     is_dsp = 0;
 268   else if (regno >= mips_regnum (gdbarch)->dspacc
 269       && regno < mips_regnum (gdbarch)->dspacc + 6)
 270     is_dsp = 1;
 271   else if (regno == mips_regnum (gdbarch)->dspctl)
 272     is_dsp = 1;
 273   else
 274     is_dsp = 0;
 275
 276   tid = get_ptrace_pid (regcache_get_ptid (regcache));
 277
 278   if (regno == -1 || (!is_fp && !is_dsp))
 279     {
 280       mips64_elf_gregset_t regs;
 281
 282       if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
 283         {
 284           if (errno == EIO)
 285             {
 286               have_ptrace_regsets = 0;
 287               return;
 288             }
 289           perror_with_name (_("Couldn't get registers"));
 290         }
 291
 292       mips64_supply_gregset (regcache,
 293                              (const mips64_elf_gregset_t *) &regs);
 294     }
 295
 296   if (regno == -1 || is_fp)
 297     {
 298       mips64_elf_fpregset_t fp_regs;
 299
 300       if (ptrace (PTRACE_GETFPREGS, tid, 0L,
 301                   (PTRACE_TYPE_ARG3) &fp_regs) == -1)
 302         {
 303           if (errno == EIO)
 304             {
 305               have_ptrace_regsets = 0;
 306               return;
 307             }
 308           perror_with_name (_("Couldn't get FP registers"));
 309         }
 310
 311       mips64_supply_fpregset (regcache,
 312                               (const mips64_elf_fpregset_t *) &fp_regs);
 313     }
 314
 315   if (is_dsp)
 316     linux_nat_trad_target::fetch_registers (regcache, regno);
 317   else if (regno == -1 && have_dsp)
 318     {
 319       for (regi = mips_regnum (gdbarch)->dspacc;
 320            regi < mips_regnum (gdbarch)->dspacc + 6;
 321            regi++)
 322         linux_nat_trad_target::fetch_registers (regcache, regi);
 323       linux_nat_trad_target::fetch_registers (regcache,
 324                                               mips_regnum (gdbarch)->dspctl);
 325     }
 326 }
 327
 328 /* Store REGNO (or all registers if REGNO == -1) to the target
 329    using PTRACE_SETREGS et al.  */
 330
 331 void
 332 mips_linux_nat_target::mips64_regsets_store_registers
 333   (struct regcache *regcache, int regno)
 334 {
 335   struct gdbarch *gdbarch = regcache->arch ();
 336   int is_fp, is_dsp;
 337   int have_dsp;
 338   int regi;
 339   int tid;
 340
 341   if (regno >= mips_regnum (gdbarch)->fp0
 342       && regno <= mips_regnum (gdbarch)->fp0 + 32)
 343     is_fp = 1;
 344   else if (regno == mips_regnum (gdbarch)->fp_control_status)
 345     is_fp = 1;
 346   else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
 347     is_fp = 1;
 348   else
 349     is_fp = 0;
 350
 351   /* DSP registers are optional and not a part of any set.  */
 352   have_dsp = mips_regnum (gdbarch)->dspctl != -1;
 353   if (!have_dsp)
 354     is_dsp = 0;
 355   else if (regno >= mips_regnum (gdbarch)->dspacc
 356       && regno < mips_regnum (gdbarch)->dspacc + 6)
 357     is_dsp = 1;
 358   else if (regno == mips_regnum (gdbarch)->dspctl)
 359     is_dsp = 1;
 360   else
 361     is_dsp = 0;
 362
 363   tid = get_ptrace_pid (regcache_get_ptid (regcache));
 364
 365   if (regno == -1 || (!is_fp && !is_dsp))
 366     {
 367       mips64_elf_gregset_t regs;
 368
 369       if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
 370         perror_with_name (_("Couldn't get registers"));
 371
 372       mips64_fill_gregset (regcache, &regs, regno);
 373
 374       if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
 375         perror_with_name (_("Couldn't set registers"));
 376     }
 377
 378   if (regno == -1 || is_fp)
 379     {
 380       mips64_elf_fpregset_t fp_regs;
 381
 382       if (ptrace (PTRACE_GETFPREGS, tid, 0L,
 383                   (PTRACE_TYPE_ARG3) &fp_regs) == -1)
 384         perror_with_name (_("Couldn't get FP registers"));
 385
 386       mips64_fill_fpregset (regcache, &fp_regs, regno);
 387
 388       if (ptrace (PTRACE_SETFPREGS, tid, 0L,
 389                   (PTRACE_TYPE_ARG3) &fp_regs) == -1)
 390         perror_with_name (_("Couldn't set FP registers"));
 391     }
 392
 393   if (is_dsp)
 394     linux_nat_trad_target::store_registers (regcache, regno);
 395   else if (regno == -1 && have_dsp)
 396     {
 397       for (regi = mips_regnum (gdbarch)->dspacc;
 398            regi < mips_regnum (gdbarch)->dspacc + 6;
 399            regi++)
 400         linux_nat_trad_target::store_registers (regcache, regi);
 401       linux_nat_trad_target::store_registers (regcache,
 402                                               mips_regnum (gdbarch)->dspctl);
 403     }
 404 }
 405
 406 /* Fetch REGNO (or all registers if REGNO == -1) from the target
 407    using any working method.  */
 408
 409 void
 410 mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 411 {
 412   /* Unless we already know that PTRACE_GETREGS does not work, try it.  */
 413   if (have_ptrace_regsets)
 414     mips64_regsets_fetch_registers (regcache, regnum);
 415
 416   /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
 417      back to PTRACE_PEEKUSER.  */
 418   if (!have_ptrace_regsets)
 419     linux_nat_trad_target::fetch_registers (regcache, regnum);
 420 }
 421
 422 /* Store REGNO (or all registers if REGNO == -1) to the target
 423    using any working method.  */
 424
 425 void
 426 mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 427 {
 428   /* Unless we already know that PTRACE_GETREGS does not work, try it.  */
 429   if (have_ptrace_regsets)
 430     mips64_regsets_store_registers (regcache, regnum);
 431
 432   /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
 433      back to PTRACE_PEEKUSER.  */
 434   if (!have_ptrace_regsets)
 435     linux_nat_trad_target::store_registers (regcache, regnum);
 436 }
 437
 438 /* Return the address in the core dump or inferior of register
 439    REGNO.  */
 440
 441 CORE_ADDR
 442 mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch,
 443                                           int regno, int store_p)
 444 {
 445   if (mips_abi_regsize (gdbarch) == 8)
 446     return mips64_linux_register_addr (gdbarch, regno, store_p);
 447   else
 448     return mips_linux_register_addr (gdbarch, regno, store_p);
 449 }
 450
 451 const struct target_desc *
 452 mips_linux_nat_target::read_description ()
 453 {
 454   static int have_dsp = -1;
 455
 456   if (have_dsp < 0)
 457     {
 458       int tid;
 459
 460       tid = ptid_get_lwp (inferior_ptid);
 461       if (tid == 0)
 462         tid = ptid_get_pid (inferior_ptid);
 463
 464       errno = 0;
 465       ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
 466       switch (errno)
 467         {
 468         case 0:
 469           have_dsp = 1;
 470           break;
 471         case EIO:
 472           have_dsp = 0;
 473           break;
 474         default:
 475           perror_with_name (_("Couldn't check DSP support"));
 476           break;
 477         }
 478     }
 479
 480   /* Report that target registers are a size we know for sure
 481      that we can get from ptrace.  */
 482   if (_MIPS_SIM == _ABIO32)
 483     return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 484   else
 485     return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
 486 }
 487
 488 /* -1 if the kernel and/or CPU do not support watch registers.
 489     1 if watch_readback is valid and we can read style, num_valid
 490       and the masks.
 491     0 if we need to read the watch_readback.  */
 492
 493 static int watch_readback_valid;
 494
 495 /* Cached watch register read values.  */
 496
 497 static struct pt_watch_regs watch_readback;
 498
 499 static struct mips_watchpoint *current_watches;
 500
 501 /*  The current set of watch register values for writing the
 502     registers.  */
 503
 504 static struct pt_watch_regs watch_mirror;
 505
 506 static void
 507 mips_show_dr (const char *func, CORE_ADDR addr,
 508               int len, enum target_hw_bp_type type)
 509 {
 510   int i;
 511
 512   puts_unfiltered (func);
 513   if (addr || len)
 514     printf_unfiltered (" (addr=%s, len=%d, type=%s)",
 515                        paddress (target_gdbarch (), addr), len,
 516                        type == hw_write ? "data-write"
 517                        : (type == hw_read ? "data-read"
 518                           : (type == hw_access ? "data-read/write"
 519                              : (type == hw_execute ? "instruction-execute"
 520                                 : "??unknown??"))));
 521   puts_unfiltered (":\n");
 522
 523   for (i = 0; i < MAX_DEBUG_REGISTER; i++)
 524     printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
 525                        paddress (target_gdbarch (),
 526                                  mips_linux_watch_get_watchlo (&watch_mirror,
 527                                                                i)),
 528                        paddress (target_gdbarch (),
 529                                  mips_linux_watch_get_watchhi (&watch_mirror,
 530                                                                i)));
 531 }
 532
 533 /* Target to_can_use_hw_breakpoint implementation.  Return 1 if we can
 534    handle the specified watch type.  */
 535
 536 int
 537 mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
 538                                               int cnt, int ot)
 539 {
 540   int i;
 541   uint32_t wanted_mask, irw_mask;
 542
 543   if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
 544                                         &watch_readback,
 545                                         &watch_readback_valid, 0))
 546     return 0;
 547
 548    switch (type)
 549     {
 550     case bp_hardware_watchpoint:
 551       wanted_mask = W_MASK;
 552       break;
 553     case bp_read_watchpoint:
 554       wanted_mask = R_MASK;
 555       break;
 556     case bp_access_watchpoint:
 557       wanted_mask = R_MASK | W_MASK;
 558       break;
 559     default:
 560       return 0;
 561     }
 562
 563   for (i = 0;
 564        i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
 565        i++)
 566     {
 567       irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
 568       if ((irw_mask & wanted_mask) == wanted_mask)
 569         cnt--;
 570     }
 571   return (cnt == 0) ? 1 : 0;
 572 }
 573
 574 /* Target to_stopped_by_watchpoint implementation.  Return 1 if
 575    stopped by watchpoint.  The watchhi R and W bits indicate the watch
 576    register triggered.  */
 577
 578 bool
 579 mips_linux_nat_target::stopped_by_watchpoint ()
 580 {
 581   int n;
 582   int num_valid;
 583
 584   if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
 585                                         &watch_readback,
 586                                         &watch_readback_valid, 1))
 587     return false;
 588
 589   num_valid = mips_linux_watch_get_num_valid (&watch_readback);
 590
 591   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 592     if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
 593       return true;
 594
 595   return false;
 596 }
 597
 598 /* Target to_stopped_data_address implementation.  Set the address
 599    where the watch triggered (if known).  Return 1 if the address was
 600    known.  */
 601
 602 bool
 603 mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr)
 604 {
 605   /* On mips we don't know the low order 3 bits of the data address,
 606      so we must return false.  */
 607   return false;
 608 }
 609
 610 /* Target to_region_ok_for_hw_watchpoint implementation.  Return 1 if
 611    the specified region can be covered by the watch registers.  */
 612
 613 int
 614 mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
 615 {
 616   struct pt_watch_regs dummy_regs;
 617   int i;
 618
 619   if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
 620                                         &watch_readback,
 621                                         &watch_readback_valid, 0))
 622     return 0;
 623
 624   dummy_regs = watch_readback;
 625   /* Clear them out.  */
 626   for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
 627     mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
 628   return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
 629 }
 630
 631 /* Write the mirrored watch register values for each thread.  */
 632
 633 static int
 634 write_watchpoint_regs (void)
 635 {
 636   struct lwp_info *lp;
 637   int tid;
 638
 639   ALL_LWPS (lp)
 640     {
 641       tid = ptid_get_lwp (lp->ptid);
 642       if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
 643         perror_with_name (_("Couldn't write debug register"));
 644     }
 645   return 0;
 646 }
 647
 648 /* linux_nat_target::low_new_thread implementation.  Write the
 649    mirrored watch register values for the new thread.  */
 650
 651 void
 652 mips_linux_nat_target::low_new_thread (struct lwp_info *lp)
 653 {
 654   long tid = lp->ptid.lwp ();
 655
 656   if (!mips_linux_read_watch_registers (tid,
 657                                         &watch_readback,
 658                                         &watch_readback_valid, 0))
 659     return;
 660
 661   if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
 662     perror_with_name (_("Couldn't write debug register"));
 663 }
 664
 665 /* Target to_insert_watchpoint implementation.  Try to insert a new
 666    watch.  Return zero on success.  */
 667
 668 int
 669 mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
 670                                           enum target_hw_bp_type type,
 671                                           struct expression *cond)
 672 {
 673   struct pt_watch_regs regs;
 674   struct mips_watchpoint *new_watch;
 675   struct mips_watchpoint **pw;
 676
 677   int i;
 678   int retval;
 679
 680   if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
 681                                         &watch_readback,
 682                                         &watch_readback_valid, 0))
 683     return -1;
 684
 685   if (len <= 0)
 686     return -1;
 687
 688   regs = watch_readback;
 689   /* Add the current watches.  */
 690   mips_linux_watch_populate_regs (current_watches, &regs);
 691
 692   /* Now try to add the new watch.  */
 693   if (!mips_linux_watch_try_one_watch (&regs, addr, len,
 694                                        mips_linux_watch_type_to_irw (type)))
 695     return -1;
 696
 697   /* It fit.  Stick it on the end of the list.  */
 698   new_watch = XNEW (struct mips_watchpoint);
 699   new_watch->addr = addr;
 700   new_watch->len = len;
 701   new_watch->type = type;
 702   new_watch->next = NULL;
 703
 704   pw = &current_watches;
 705   while (*pw != NULL)
 706     pw = &(*pw)->next;
 707   *pw = new_watch;
 708
 709   watch_mirror = regs;
 710   retval = write_watchpoint_regs ();
 711
 712   if (show_debug_regs)
 713     mips_show_dr ("insert_watchpoint", addr, len, type);
 714
 715   return retval;
 716 }
 717
 718 /* Target to_remove_watchpoint implementation.  Try to remove a watch.
 719    Return zero on success.  */
 720
 721 int
 722 mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
 723                                           enum target_hw_bp_type type,
 724                                           struct expression *cond)
 725 {
 726   int retval;
 727   int deleted_one;
 728
 729   struct mips_watchpoint **pw;
 730   struct mips_watchpoint *w;
 731
 732   /* Search for a known watch that matches.  Then unlink and free
 733      it.  */
 734   deleted_one = 0;
 735   pw = &current_watches;
 736   while ((w = *pw))
 737     {
 738       if (w->addr == addr && w->len == len && w->type == type)
 739         {
 740           *pw = w->next;
 741           xfree (w);
 742           deleted_one = 1;
 743           break;
 744         }
 745       pw = &(w->next);
 746     }
 747
 748   if (!deleted_one)
 749     return -1;  /* We don't know about it, fail doing nothing.  */
 750
 751   /* At this point watch_readback is known to be valid because we
 752      could not have added the watch without reading it.  */
 753   gdb_assert (watch_readback_valid == 1);
 754
 755   watch_mirror = watch_readback;
 756   mips_linux_watch_populate_regs (current_watches, &watch_mirror);
 757
 758   retval = write_watchpoint_regs ();
 759
 760   if (show_debug_regs)
 761     mips_show_dr ("remove_watchpoint", addr, len, type);
 762
 763   return retval;
 764 }
 765
 766 /* Target to_close implementation.  Free any watches and call the
 767    super implementation.  */
 768
 769 void
 770 mips_linux_nat_target::close ()
 771 {
 772   struct mips_watchpoint *w;
 773   struct mips_watchpoint *nw;
 774
 775   /* Clean out the current_watches list.  */
 776   w = current_watches;
 777   while (w)
 778     {
 779       nw = w->next;
 780       xfree (w);
 781       w = nw;
 782     }
 783   current_watches = NULL;
 784
 785   linux_nat_trad_target::close ();
 786 }
 787
 788 void
 789 _initialize_mips_linux_nat (void)
 790 {
 791   add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
 792                            &show_debug_regs, _("\
 793 Set whether to show variables that mirror the mips debug registers."), _("\
 794 Show whether to show variables that mirror the mips debug registers."), _("\
 795 Use \"on\" to enable, \"off\" to disable.\n\
 796 If enabled, the debug registers values are shown when GDB inserts\n\
 797 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
 798 triggers a breakpoint or watchpoint."),
 799                            NULL,
 800                            NULL,
 801                            &maintenance_set_cmdlist,
 802                            &maintenance_show_cmdlist);
 803
 804   linux_target = &the_mips_linux_nat_target;
 805   add_target (&the_mips_linux_nat_target);
 806 }