1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
38 /* start-sanitize-carp start-sanitize-vr4xxx */
42 /* end-sanitize-carp end-sanitize-vr4xxx */
44 /* Some MIPS boards don't support floating point, so we permit the
45 user to turn it off. */
49 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
50 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
51 MIPS_FPU_NONE
/* No floating point. */
54 static int mips_fpu_type_auto
= 1;
55 #ifdef MIPS_DEFAULT_FPU_TYPE
56 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
58 static enum mips_fpu_type mips_fpu
= MIPS_FPU_DOUBLE
;
60 #define MIPS_FPU_TYPE mips_fpu_type
62 /* start-sanitize-carp start-sanitize-vr4xxx */
64 /* MIPS specific per-architecture information */
70 enum mips_fpu_type mips_fpu_type
;
71 int mips_last_arg_regnum
;
72 int mips_last_fp_arg_regnum
;
77 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi)
81 #undef MIPS_LAST_FP_ARG_REGNUM
82 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
86 #undef MIPS_LAST_ARG_REGNUM
87 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
92 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
95 /* end-sanitize-carp end-sanitize-vr4xxx */
97 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
99 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
100 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
103 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
106 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
108 static void mips_print_register
PARAMS ((int, int));
110 static mips_extra_func_info_t
111 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
113 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
115 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
117 void mips_set_processor_type_command
PARAMS ((char *, int));
119 int mips_set_processor_type
PARAMS ((char *));
121 static void mips_show_processor_type_command
PARAMS ((char *, int));
123 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
124 struct cmd_list_element
*));
126 static mips_extra_func_info_t
127 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
129 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
130 mips_extra_func_info_t proc_desc
));
132 /* This value is the model of MIPS in use. It is derived from the value
133 of the PrID register. */
135 char *mips_processor_type
;
137 char *tmp_mips_processor_type
;
139 /* A set of original names, to be used when restoring back to generic
140 registers from a specific set. */
142 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
144 /* Names of IDT R3041 registers. */
146 char *mips_r3041_reg_names
[] = {
147 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
148 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
149 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
150 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
151 "sr", "lo", "hi", "bad", "cause","pc",
152 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
153 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
154 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
155 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
156 "fsr", "fir", "fp", "",
157 "", "", "bus", "ccfg", "", "", "", "",
158 "", "", "port", "cmp", "", "", "epc", "prid",
161 /* Names of IDT R3051 registers. */
163 char *mips_r3051_reg_names
[] = {
164 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
165 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
166 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
167 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
168 "sr", "lo", "hi", "bad", "cause","pc",
169 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
170 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
171 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
172 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
173 "fsr", "fir", "fp", "",
174 "inx", "rand", "elo", "", "ctxt", "", "", "",
175 "", "", "ehi", "", "", "", "epc", "prid",
178 /* Names of IDT R3081 registers. */
180 char *mips_r3081_reg_names
[] = {
181 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
182 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
183 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
184 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
185 "sr", "lo", "hi", "bad", "cause","pc",
186 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
187 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
188 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
189 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
190 "fsr", "fir", "fp", "",
191 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
192 "", "", "ehi", "", "", "", "epc", "prid",
195 /* Names of LSI 33k registers. */
197 char *mips_lsi33k_reg_names
[] = {
198 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
199 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
200 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
201 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
202 "epc", "hi", "lo", "sr", "cause","badvaddr",
203 "dcic", "bpc", "bda", "", "", "", "", "",
204 "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "", "",
206 "", "", "", "", "", "", "", "",
208 "", "", "", "", "", "", "", "",
209 "", "", "", "", "", "", "", "",
215 } mips_processor_type_table
[] = {
216 { "generic", mips_generic_reg_names
},
217 { "r3041", mips_r3041_reg_names
},
218 { "r3051", mips_r3051_reg_names
},
219 { "r3071", mips_r3081_reg_names
},
220 { "r3081", mips_r3081_reg_names
},
221 { "lsi33k", mips_lsi33k_reg_names
},
225 /* Table to translate MIPS16 register field to actual register number. */
226 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
228 /* Heuristic_proc_start may hunt through the text section for a long
229 time across a 2400 baud serial line. Allows the user to limit this
232 static unsigned int heuristic_fence_post
= 0;
234 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
235 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
236 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
237 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
238 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
239 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
240 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
241 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
242 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
243 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
244 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
245 #define _PROC_MAGIC_ 0x0F0F0F0F
246 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
247 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
249 struct linked_proc_info
251 struct mips_extra_func_info info
;
252 struct linked_proc_info
*next
;
253 } *linked_proc_desc_table
= NULL
;
256 /* Should the upper word of 64-bit addresses be zeroed? */
257 static int mask_address_p
= 1;
259 /* Should call_function allocate stack space for a struct return? */
261 mips_use_struct_convention (gcc_p
, type
)
266 return (TYPE_LENGTH (type
) > 2 * MIPS_REGSIZE
);
268 return 1; /* Structures are returned by ref in extra arg0 */
271 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
274 pc_is_mips16 (bfd_vma memaddr
)
276 struct minimal_symbol
*sym
;
278 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
279 if (IS_MIPS16_ADDR (memaddr
))
282 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
283 the high bit of the info field. Use this to decide if the function is
284 MIPS16 or normal MIPS. */
285 sym
= lookup_minimal_symbol_by_pc (memaddr
);
287 return MSYMBOL_IS_SPECIAL (sym
);
293 /* This returns the PC of the first inst after the prologue. If we can't
294 find the prologue, then return 0. */
297 after_prologue (pc
, proc_desc
)
299 mips_extra_func_info_t proc_desc
;
301 struct symtab_and_line sal
;
302 CORE_ADDR func_addr
, func_end
;
305 proc_desc
= find_proc_desc (pc
, NULL
);
309 /* If function is frameless, then we need to do it the hard way. I
310 strongly suspect that frameless always means prologueless... */
311 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
312 && PROC_FRAME_OFFSET (proc_desc
) == 0)
316 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
317 return 0; /* Unknown */
319 sal
= find_pc_line (func_addr
, 0);
321 if (sal
.end
< func_end
)
324 /* The line after the prologue is after the end of the function. In this
325 case, tell the caller to find the prologue the hard way. */
330 /* Decode a MIPS32 instruction that saves a register in the stack, and
331 set the appropriate bit in the general register mask or float register mask
332 to indicate which register is saved. This is a helper function
333 for mips_find_saved_regs. */
336 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
338 unsigned long *gen_mask
;
339 unsigned long *float_mask
;
343 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
344 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
345 /* start-sanitize-r5900 */
346 || (inst
& 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */
347 /* end-sanitize-r5900 */
348 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
350 /* It might be possible to use the instruction to
351 find the offset, rather than the code below which
352 is based on things being in a certain order in the
353 frame, but figuring out what the instruction's offset
354 is relative to might be a little tricky. */
355 reg
= (inst
& 0x001f0000) >> 16;
356 *gen_mask
|= (1 << reg
);
358 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
359 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
360 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
363 reg
= ((inst
& 0x001f0000) >> 16);
364 *float_mask
|= (1 << reg
);
368 /* Decode a MIPS16 instruction that saves a register in the stack, and
369 set the appropriate bit in the general register or float register mask
370 to indicate which register is saved. This is a helper function
371 for mips_find_saved_regs. */
374 mips16_decode_reg_save (inst
, gen_mask
)
376 unsigned long *gen_mask
;
378 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
380 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
381 *gen_mask
|= (1 << reg
);
383 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
385 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
386 *gen_mask
|= (1 << reg
);
388 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
389 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
390 *gen_mask
|= (1 << RA_REGNUM
);
394 /* Fetch and return instruction from the specified location. If the PC
395 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
398 mips_fetch_instruction (addr
)
401 char buf
[MIPS_INSTLEN
];
405 if (pc_is_mips16 (addr
))
407 instlen
= MIPS16_INSTLEN
;
408 addr
= UNMAKE_MIPS16_ADDR (addr
);
411 instlen
= MIPS_INSTLEN
;
412 status
= read_memory_nobpt (addr
, buf
, instlen
);
414 memory_error (status
, addr
);
415 return extract_unsigned_integer (buf
, instlen
);
419 /* These the fields of 32 bit mips instructions */
420 #define mips32_op(x) (x >> 25)
421 #define itype_op(x) (x >> 25)
422 #define itype_rs(x) ((x >> 21)& 0x1f)
423 #define itype_rt(x) ((x >> 16) & 0x1f)
424 #define itype_immediate(x) ( x & 0xffff)
426 #define jtype_op(x) (x >> 25)
427 #define jtype_target(x) ( x & 0x03fffff)
429 #define rtype_op(x) (x >>25)
430 #define rtype_rs(x) ((x>>21) & 0x1f)
431 #define rtype_rt(x) ((x>>16) & 0x1f)
432 #define rtype_rd(x) ((x>>11) & 0x1f)
433 #define rtype_shamt(x) ((x>>6) & 0x1f)
434 #define rtype_funct(x) (x & 0x3f )
437 mips32_relative_offset(unsigned long inst
)
439 x
= itype_immediate(inst
) ;
440 if (x
& 0x8000) /* sign bit set */
442 x
|= 0xffff0000 ; /* sign extension */
448 /* Determine whate to set a single step breakpoint while considering
451 mips32_next_pc(CORE_ADDR pc
)
455 inst
= mips_fetch_instruction(pc
) ;
456 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
457 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
458 { op
= ((inst
>> 25) & 0x03) ;
461 case 0 : goto equal_branch
; /* BEQL */
462 case 1 : goto neq_branch
; /* BNEZ */
463 case 2 : goto less_branch
; /* BLEZ */
464 case 3 : goto greater_branch
; /* BGTZ */
468 else pc
+= 4 ; /* Not a branch, next instruction is easy */
471 { /* This gets way messy */
473 /* Further subdivide into SPECIAL, REGIMM and other */
474 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
476 case 0 : /* SPECIAL */
477 op
= rtype_funct(inst
) ;
482 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
487 break ; /* end special */
488 case 1 : /* REGIMM */
490 op
= jtype_op(inst
) ; /* branch condition */
491 switch (jtype_op(inst
))
495 case 16 : /* BLTZALL */
496 case 18 : /* BLTZALL */
498 if (read_register(itype_rs(inst
)) < 0)
499 pc
+= mips32_relative_offset(inst
) + 4 ;
500 else pc
+= 8 ; /* after the delay slot */
504 case 17 : /* BGEZAL */
505 case 19 : /* BGEZALL */
506 greater_equal_branch
:
507 if (read_register(itype_rs(inst
)) >= 0)
508 pc
+= mips32_relative_offset(inst
) + 4 ;
509 else pc
+= 8 ; /* after the delay slot */
511 /* All of the other intructions in the REGIMM catagory */
515 break ; /* end REGIMM */
518 { unsigned long reg
;
519 reg
= jtype_target(inst
) << 2 ;
520 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
521 /* Whats this mysterious 0xf000000 adjustment ??? */
524 /* FIXME case JALX :*/
525 { unsigned long reg
;
526 reg
= jtype_target(inst
) << 2 ;
527 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
528 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
530 break ; /* The new PC will be alternate mode */
531 case 4 : /* BEQ , BEQL */
533 if (read_register(itype_rs(inst
)) ==
534 read_register(itype_rt(inst
)))
535 pc
+= mips32_relative_offset(inst
) + 4 ;
538 case 5 : /* BNE , BNEL */
540 if (read_register(itype_rs(inst
)) !=
541 read_register(itype_rs(inst
)))
542 pc
+= mips32_relative_offset(inst
) + 4 ;
545 case 6 : /* BLEZ , BLEZL */
547 if (read_register(itype_rs(inst
) <= 0))
548 pc
+= mips32_relative_offset(inst
) + 4 ;
552 greater_branch
: /* BGTZ BGTZL */
553 if (read_register(itype_rs(inst
) > 0))
554 pc
+= mips32_relative_offset(inst
) + 4 ;
561 } /* mips32_next_pc */
563 /* Decoding the next place to set a breakpoint is irregular for the
564 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
565 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
566 We dont want to set a single step instruction on the extend instruction
570 /* Lots of mips16 instruction formats */
571 /* Predicting jumps requires itype,ritype,i8type
572 and their extensions extItype,extritype,extI8type
574 enum mips16_inst_fmts
576 itype
, /* 0 immediate 5,10 */
577 ritype
, /* 1 5,3,8 */
578 rrtype
, /* 2 5,3,3,5 */
579 rritype
, /* 3 5,3,3,5 */
580 rrrtype
, /* 4 5,3,3,3,2 */
581 rriatype
, /* 5 5,3,3,1,4 */
582 shifttype
, /* 6 5,3,3,3,2 */
583 i8type
, /* 7 5,3,8 */
584 i8movtype
, /* 8 5,3,3,5 */
585 i8mov32rtype
, /* 9 5,3,5,3 */
586 i64type
, /* 10 5,3,8 */
587 ri64type
, /* 11 5,3,3,5 */
588 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
589 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
590 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
591 extRRItype
, /* 15 5,5,5,5,3,3,5 */
592 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
593 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
594 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
595 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
596 extRi64type
, /* 20 5,6,5,5,3,3,5 */
597 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
599 /* I am heaping all the fields of the formats into one structure and then,
600 only the fields which are involved in instruction extension */
603 unsigned short inst
;
604 enum mips16_inst_fmts fmt
;
605 unsigned long offset
;
606 unsigned int regx
; /* Function in i8 type */
612 static void print_unpack(char * comment
,
613 struct upk_mips16
* u
)
615 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
616 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
619 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
620 format for the bits which make up the immediatate extension.
623 extended_offset(unsigned long extension
)
625 unsigned long value
;
626 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
628 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
630 value
|= extension
& 0x01f ; /* extract 4:0 */
634 /* Only call this function if you know that this is an extendable
635 instruction, It wont malfunction, but why make excess remote memory references?
636 If the immediate operands get sign extended or somthing, do it after
637 the extension is performed.
639 /* FIXME: Every one of these cases needs to worry about sign extension
640 when the offset is to be used in relative addressing */
643 static unsigned short fetch_mips_16(CORE_ADDR pc
)
646 pc
&= 0xfffffffe ; /* clear the low order bit */
647 target_read_memory(pc
,buf
,2) ;
648 return extract_unsigned_integer(buf
,2) ;
652 unpack_mips16(CORE_ADDR pc
,
653 struct upk_mips16
* upk
)
656 unsigned long extension
;
658 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
659 /* Decrement to previous address and loose the 16bit mode flag */
660 /* return if the instruction was extendable, but not actually extended */
661 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
662 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
667 unsigned long value
;
669 { value
= extended_offset(extension
) ;
670 value
= value
<< 11 ; /* rom for the original value */
671 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
674 { value
= upk
->inst
& 0x7ff ;
675 /* FIXME : Consider sign extension */
677 upk
->offset
= value
;
682 { /* A register identifier and an offset */
683 /* Most of the fields are the same as I type but the
684 immediate value is of a different length */
685 unsigned long value
;
688 value
= extended_offset(extension
) ;
689 value
= value
<< 8 ; /* from the original instruction */
690 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
691 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
692 if (value
& 0x4000) /* test the sign bit , bit 26 */
693 { value
&= ~ 0x3fff ; /* remove the sign bit */
698 value
= upk
->inst
& 0xff ; /* 8 bits */
699 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
700 /* FIXME: Do sign extension , this format needs it */
701 if (value
& 0x80) /* THIS CONFUSES ME */
702 { value
&= 0xef ; /* remove the sign bit */
707 upk
->offset
= value
;
712 unsigned long value
;
713 unsigned short nexthalf
;
714 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
715 value
= value
<< 16 ;
716 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
718 upk
->offset
= value
;
722 printf_filtered("Decoding unimplemented instruction format type\n") ;
725 /* print_unpack("UPK",upk) ; */
729 #define mips16_op(x) (x >> 11)
731 /* This is a map of the opcodes which ae known to perform branches */
732 static unsigned char map16
[32] =
739 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
741 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
747 static struct upk_mips16 upk
;
749 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
753 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
754 inst
= fetch_mips_16(pc
) ;
756 op
= mips16_op(upk
.inst
) ;
762 case 2 : /* Branch */
764 unpack_mips16(pc
,&upk
) ;
766 offset
= upk
.offset
;
771 pc
+= (offset
<< 1) + 2 ;
774 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
776 unpack_mips16(pc
,&upk
) ;
777 pc
= add_offset_16(pc
,upk
.offset
) ;
778 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
779 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
784 unpack_mips16(pc
,&upk
) ;
785 reg
= read_register(upk
.regx
) ;
787 pc
+= (upk
.offset
<< 1) + 2 ;
792 unpack_mips16(pc
,&upk
) ;
793 reg
= read_register(upk
.regx
) ;
795 pc
+= (upk
.offset
<< 1) + 2 ;
798 case 12 : /* I8 Formats btez btnez */
800 unpack_mips16(pc
,&upk
) ;
801 /* upk.regx contains the opcode */
802 reg
= read_register(24) ; /* Test register is 24 */
803 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
804 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
805 /* pc = add_offset_16(pc,upk.offset) ; */
806 pc
+= (upk
.offset
<< 1) + 2 ;
809 case 29 : /* RR Formats JR, JALR, JALR-RA */
811 op
= upk
.inst
& 0x1f ;
814 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
815 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
818 case 0 : reg
= upk
.regx
; break ;
819 case 1 : reg
= 31 ; break ; /* Function return instruction*/
820 case 2 : reg
= upk
.regx
; break ;
821 default: reg
= 31 ; break ; /* BOGUS Guess */
823 pc
= read_register(reg
) ;
827 case 30 : /* This is an extend instruction */
828 pc
+= 4 ; /* Dont be setting breakpints on the second half */
831 printf("Filtered - next PC probably incorrrect due to jump inst\n");
836 else pc
+= 2 ; /* just a good old instruction */
837 /* See if we CAN actually break on the next instruction */
838 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
840 } /* mips16_next_pc */
842 /* The mips_next_pc function supports single_tep when the remote target monitor or
843 stub is not developed enough to so a single_step.
844 It works by decoding the current instruction and predicting where a branch
845 will go. This isnt hard because all the data is available.
846 The MIPS32 and MIPS16 variants are quite different
848 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
851 /* inst = mips_fetch_instruction(pc) ; */
852 /* if (pc_is_mips16) <----- This is failing */
854 return mips16_next_pc(pc
) ;
855 else return mips32_next_pc(pc
) ;
858 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
862 mips_find_saved_regs (fci
)
863 struct frame_info
*fci
;
866 CORE_ADDR reg_position
;
867 /* r0 bit means kernel trap */
869 /* What registers have been saved? Bitmasks. */
870 unsigned long gen_mask
, float_mask
;
871 mips_extra_func_info_t proc_desc
;
874 frame_saved_regs_zalloc (fci
);
876 /* If it is the frame for sigtramp, the saved registers are located
877 in a sigcontext structure somewhere on the stack.
878 If the stack layout for sigtramp changes we might have to change these
879 constants and the companion fixup_sigtramp in mdebugread.c */
880 #ifndef SIGFRAME_BASE
881 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
882 above the sigtramp frame. */
883 #define SIGFRAME_BASE MIPS_REGSIZE
884 /* FIXME! Are these correct?? */
885 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
886 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
887 #define SIGFRAME_FPREGSAVE_OFF \
888 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
890 #ifndef SIGFRAME_REG_SIZE
891 /* FIXME! Is this correct?? */
892 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
894 if (fci
->signal_handler_caller
)
896 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
898 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
899 + ireg
* SIGFRAME_REG_SIZE
;
900 fci
->saved_regs
[ireg
] = reg_position
;
902 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
904 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
905 + ireg
* SIGFRAME_REG_SIZE
;
906 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
908 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
912 proc_desc
= fci
->proc_desc
;
913 if (proc_desc
== NULL
)
914 /* I'm not sure how/whether this can happen. Normally when we can't
915 find a proc_desc, we "synthesize" one using heuristic_proc_desc
916 and set the saved_regs right away. */
919 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
920 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
921 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
923 if (/* In any frame other than the innermost or a frame interrupted by
924 a signal, we assume that all registers have been saved.
925 This assumes that all register saves in a function happen before
926 the first function call. */
927 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
929 /* In a dummy frame we know exactly where things are saved. */
930 && !PROC_DESC_IS_DUMMY (proc_desc
)
932 /* Don't bother unless we are inside a function prologue. Outside the
933 prologue, we know where everything is. */
935 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
937 /* Not sure exactly what kernel_trap means, but if it means
938 the kernel saves the registers without a prologue doing it,
939 we better not examine the prologue to see whether registers
940 have been saved yet. */
943 /* We need to figure out whether the registers that the proc_desc
944 claims are saved have been saved yet. */
948 /* Bitmasks; set if we have found a save for the register. */
949 unsigned long gen_save_found
= 0;
950 unsigned long float_save_found
= 0;
953 /* If the address is odd, assume this is MIPS16 code. */
954 addr
= PROC_LOW_ADDR (proc_desc
);
955 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
957 /* Scan through this function's instructions preceding the current
958 PC, and look for those that save registers. */
959 while (addr
< fci
->pc
)
961 inst
= mips_fetch_instruction (addr
);
962 if (pc_is_mips16 (addr
))
963 mips16_decode_reg_save (inst
, &gen_save_found
);
965 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
968 gen_mask
= gen_save_found
;
969 float_mask
= float_save_found
;
972 /* Fill in the offsets for the registers which gen_mask says
974 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
975 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
976 if (gen_mask
& 0x80000000)
978 fci
->saved_regs
[ireg
] = reg_position
;
979 reg_position
-= MIPS_REGSIZE
;
980 /* start-sanitize-r5900 */
981 #ifdef R5900_128BIT_GPR_HACK
982 /* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is
983 still 64bits. See the comments in tm.h for a discussion of the
984 various problems this causes. */
985 if (ireg
<= RA_REGNUM
)
986 reg_position
-= MIPS_REGSIZE
;
988 /* end-sanitize-r5900 */
991 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
992 of that normally used by gcc. Therefore, we have to fetch the first
993 instruction of the function, and if it's an entry instruction that
994 saves $s0 or $s1, correct their saved addresses. */
995 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
997 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
998 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1001 int sreg_count
= (inst
>> 6) & 3;
1003 /* Check if the ra register was pushed on the stack. */
1004 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1006 reg_position
-= MIPS_REGSIZE
;
1008 /* Check if the s0 and s1 registers were pushed on the stack. */
1009 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1011 fci
->saved_regs
[reg
] = reg_position
;
1012 reg_position
-= MIPS_REGSIZE
;
1017 /* Fill in the offsets for the registers which float_mask says
1019 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1021 /* The freg_offset points to where the first *double* register
1022 is saved. So skip to the high-order word. */
1023 if (! GDB_TARGET_IS_MIPS64
)
1024 reg_position
+= MIPS_REGSIZE
;
1026 /* Fill in the offsets for the float registers which float_mask says
1028 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
1029 if (float_mask
& 0x80000000)
1031 fci
->saved_regs
[FP0_REGNUM
+ireg
] = reg_position
;
1032 reg_position
-= MIPS_REGSIZE
;
1035 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1039 read_next_frame_reg(fi
, regno
)
1040 struct frame_info
*fi
;
1043 for (; fi
; fi
= fi
->next
)
1045 /* We have to get the saved sp from the sigcontext
1046 if it is a signal handler frame. */
1047 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1051 if (fi
->saved_regs
== NULL
)
1052 mips_find_saved_regs (fi
);
1053 if (fi
->saved_regs
[regno
])
1054 return read_memory_integer(fi
->saved_regs
[regno
], MIPS_REGSIZE
);
1057 return read_register (regno
);
1060 /* mips_addr_bits_remove - remove useless address bits */
1063 mips_addr_bits_remove (addr
)
1066 #if GDB_TARGET_IS_MIPS64
1067 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1069 /* This hack is a work-around for existing boards using PMON,
1070 the simulator, and any other 64-bit targets that doesn't have
1071 true 64-bit addressing. On these targets, the upper 32 bits
1072 of addresses are ignored by the hardware. Thus, the PC or SP
1073 are likely to have been sign extended to all 1s by instruction
1074 sequences that load 32-bit addresses. For example, a typical
1075 piece of code that loads an address is this:
1076 lui $r2, <upper 16 bits>
1077 ori $r2, <lower 16 bits>
1078 But the lui sign-extends the value such that the upper 32 bits
1079 may be all 1s. The workaround is simply to mask off these bits.
1080 In the future, gcc may be changed to support true 64-bit
1081 addressing, and this masking will have to be disabled. */
1082 addr
&= (CORE_ADDR
)0xffffffff;
1085 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1086 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1087 So we still have to mask off useless bits from addresses. */
1088 addr
&= (CORE_ADDR
)0xffffffff;
1095 mips_init_frame_pc_first (fromleaf
, prev
)
1097 struct frame_info
*prev
;
1101 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1102 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1103 tmp
= mips_skip_stub (pc
);
1104 prev
->pc
= tmp
? tmp
: pc
;
1109 mips_frame_saved_pc(frame
)
1110 struct frame_info
*frame
;
1113 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1114 /* We have to get the saved pc from the sigcontext
1115 if it is a signal handler frame. */
1116 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1117 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1119 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1120 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1122 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1124 return ADDR_BITS_REMOVE (saved_pc
);
1127 static struct mips_extra_func_info temp_proc_desc
;
1128 static struct frame_saved_regs temp_saved_regs
;
1130 /* Set a register's saved stack address in temp_saved_regs. If an address
1131 has already been set for this register, do nothing; this way we will
1132 only recognize the first save of a given register in a function prologue.
1133 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1136 set_reg_offset (regno
, offset
)
1140 if (temp_saved_regs
.regs
[regno
] == 0)
1141 temp_saved_regs
.regs
[regno
] = offset
;
1145 /* Test whether the PC points to the return instruction at the
1146 end of a function. */
1149 mips_about_to_return (pc
)
1152 if (pc_is_mips16 (pc
))
1153 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1154 generates a "jr $ra"; other times it generates code to load
1155 the return address from the stack to an accessible register (such
1156 as $a3), then a "jr" using that register. This second case
1157 is almost impossible to distinguish from an indirect jump
1158 used for switch statements, so we don't even try. */
1159 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1161 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1165 /* This fencepost looks highly suspicious to me. Removing it also
1166 seems suspicious as it could affect remote debugging across serial
1170 heuristic_proc_start (pc
)
1178 pc
= ADDR_BITS_REMOVE (pc
);
1180 fence
= start_pc
- heuristic_fence_post
;
1181 if (start_pc
== 0) return 0;
1183 if (heuristic_fence_post
== UINT_MAX
1184 || fence
< VM_MIN_ADDRESS
)
1185 fence
= VM_MIN_ADDRESS
;
1187 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1189 /* search back for previous return */
1190 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1191 if (start_pc
< fence
)
1193 /* It's not clear to me why we reach this point when
1194 stop_soon_quietly, but with this test, at least we
1195 don't print out warnings for every child forked (eg, on
1196 decstation). 22apr93 rich@cygnus.com. */
1197 if (!stop_soon_quietly
)
1199 static int blurb_printed
= 0;
1201 if (fence
== VM_MIN_ADDRESS
)
1202 warning("Hit beginning of text section without finding");
1204 warning("Hit heuristic-fence-post without finding");
1206 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1210 This warning occurs if you are debugging a function without any symbols\n\
1211 (for example, in a stripped executable). In that case, you may wish to\n\
1212 increase the size of the search with the `set heuristic-fence-post' command.\n\
1214 Otherwise, you told GDB there was a function where there isn't one, or\n\
1215 (more likely) you have encountered a bug in GDB.\n");
1222 else if (pc_is_mips16 (start_pc
))
1224 unsigned short inst
;
1226 /* On MIPS16, any one of the following is likely to be the
1227 start of a function:
1231 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1232 inst
= mips_fetch_instruction (start_pc
);
1233 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1234 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1235 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1236 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1238 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1239 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1244 else if (mips_about_to_return (start_pc
))
1246 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1251 /* skip nops (usually 1) 0 - is this */
1252 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1253 start_pc
+= MIPS_INSTLEN
;
1258 /* Fetch the immediate value from a MIPS16 instruction.
1259 If the previous instruction was an EXTEND, use it to extend
1260 the upper bits of the immediate value. This is a helper function
1261 for mips16_heuristic_proc_desc. */
1264 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1265 unsigned short prev_inst
; /* previous instruction */
1266 unsigned short inst
; /* current instruction */
1267 int nbits
; /* number of bits in imm field */
1268 int scale
; /* scale factor to be applied to imm */
1269 int is_signed
; /* is the imm field signed? */
1273 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1275 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1276 if (offset
& 0x8000) /* check for negative extend */
1277 offset
= 0 - (0x10000 - (offset
& 0xffff));
1278 return offset
| (inst
& 0x1f);
1282 int max_imm
= 1 << nbits
;
1283 int mask
= max_imm
- 1;
1284 int sign_bit
= max_imm
>> 1;
1286 offset
= inst
& mask
;
1287 if (is_signed
&& (offset
& sign_bit
))
1288 offset
= 0 - (max_imm
- offset
);
1289 return offset
* scale
;
1294 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1295 stream from start_pc to limit_pc. */
1298 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1299 CORE_ADDR start_pc
, limit_pc
;
1300 struct frame_info
*next_frame
;
1304 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1305 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1306 unsigned inst
= 0; /* current instruction */
1307 unsigned entry_inst
= 0; /* the entry instruction */
1310 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1311 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1313 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1315 /* Save the previous instruction. If it's an EXTEND, we'll extract
1316 the immediate offset extension from it in mips16_get_imm. */
1319 /* Fetch and decode the instruction. */
1320 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1321 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1322 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1324 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1325 if (offset
< 0) /* negative stack adjustment? */
1326 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1328 /* Exit loop if a positive stack adjustment is found, which
1329 usually means that the stack cleanup code in the function
1330 epilogue is reached. */
1333 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1335 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1336 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1337 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1338 set_reg_offset (reg
, sp
+ offset
);
1340 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1342 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1343 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1344 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1345 set_reg_offset (reg
, sp
+ offset
);
1347 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1349 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1350 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1351 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1353 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1355 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1356 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1357 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1359 else if (inst
== 0x673d) /* move $s1, $sp */
1362 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1364 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1366 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1367 frame_addr
= sp
+ offset
;
1368 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1369 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1371 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1373 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1374 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1375 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1376 set_reg_offset (reg
, frame_addr
+ offset
);
1378 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1380 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1381 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1382 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1383 set_reg_offset (reg
, frame_addr
+ offset
);
1385 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1386 entry_inst
= inst
; /* save for later processing */
1387 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1388 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1391 /* The entry instruction is typically the first instruction in a function,
1392 and it stores registers at offsets relative to the value of the old SP
1393 (before the prologue). But the value of the sp parameter to this
1394 function is the new SP (after the prologue has been executed). So we
1395 can't calculate those offsets until we've seen the entire prologue,
1396 and can calculate what the old SP must have been. */
1397 if (entry_inst
!= 0)
1399 int areg_count
= (entry_inst
>> 8) & 7;
1400 int sreg_count
= (entry_inst
>> 6) & 3;
1402 /* The entry instruction always subtracts 32 from the SP. */
1403 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1405 /* Now we can calculate what the SP must have been at the
1406 start of the function prologue. */
1407 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1409 /* Check if a0-a3 were saved in the caller's argument save area. */
1410 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1412 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1413 set_reg_offset (reg
, sp
+ offset
);
1414 offset
+= MIPS_REGSIZE
;
1417 /* Check if the ra register was pushed on the stack. */
1419 if (entry_inst
& 0x20)
1421 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1422 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1423 offset
-= MIPS_REGSIZE
;
1426 /* Check if the s0 and s1 registers were pushed on the stack. */
1427 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1429 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1430 set_reg_offset (reg
, sp
+ offset
);
1431 offset
-= MIPS_REGSIZE
;
1437 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1438 CORE_ADDR start_pc
, limit_pc
;
1439 struct frame_info
*next_frame
;
1443 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1445 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1446 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1447 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1448 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1450 unsigned long inst
, high_word
, low_word
;
1453 /* Fetch the instruction. */
1454 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1456 /* Save some code by pre-extracting some useful fields. */
1457 high_word
= (inst
>> 16) & 0xffff;
1458 low_word
= inst
& 0xffff;
1459 reg
= high_word
& 0x1f;
1461 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1462 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1463 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1465 if (low_word
& 0x8000) /* negative stack adjustment? */
1466 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1468 /* Exit loop if a positive stack adjustment is found, which
1469 usually means that the stack cleanup code in the function
1470 epilogue is reached. */
1473 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1475 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1476 set_reg_offset (reg
, sp
+ low_word
);
1478 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1480 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1481 but the register size used is only 32 bits. Make the address
1482 for the saved register point to the lower 32 bits. */
1483 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1484 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1486 /* start-sanitize-r5900 */
1487 else if ((high_word
& 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */
1489 /* I don't think we have to worry about the Irix 6.2 N32 ABI
1490 issue noted int he sd reg, offset($sp) case above. */
1491 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1492 set_reg_offset (reg
, sp
+ low_word
);
1494 /* end-sanitize-r5900 */
1495 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1497 /* Old gcc frame, r30 is virtual frame pointer. */
1498 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1499 frame_addr
= sp
+ low_word
;
1500 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1502 unsigned alloca_adjust
;
1503 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1504 frame_addr
= read_next_frame_reg(next_frame
, 30);
1505 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1506 if (alloca_adjust
> 0)
1508 /* FP > SP + frame_size. This may be because
1509 * of an alloca or somethings similar.
1510 * Fix sp to "pre-alloca" value, and try again.
1512 sp
+= alloca_adjust
;
1517 /* move $30,$sp. With different versions of gas this will be either
1518 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1519 Accept any one of these. */
1520 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1522 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1523 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1525 unsigned alloca_adjust
;
1526 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1527 frame_addr
= read_next_frame_reg(next_frame
, 30);
1528 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1529 if (alloca_adjust
> 0)
1531 /* FP > SP + frame_size. This may be because
1532 * of an alloca or somethings similar.
1533 * Fix sp to "pre-alloca" value, and try again.
1535 sp
+= alloca_adjust
;
1540 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1542 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1543 set_reg_offset (reg
, frame_addr
+ low_word
);
1548 static mips_extra_func_info_t
1549 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1550 CORE_ADDR start_pc
, limit_pc
;
1551 struct frame_info
*next_frame
;
1553 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1555 if (start_pc
== 0) return NULL
;
1556 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1557 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1558 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1559 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1560 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1562 if (start_pc
+ 200 < limit_pc
)
1563 limit_pc
= start_pc
+ 200;
1564 if (pc_is_mips16 (start_pc
))
1565 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1567 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1568 return &temp_proc_desc
;
1571 static mips_extra_func_info_t
1572 non_heuristic_proc_desc (pc
, addrptr
)
1576 CORE_ADDR startaddr
;
1577 mips_extra_func_info_t proc_desc
;
1578 struct block
*b
= block_for_pc(pc
);
1581 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1583 *addrptr
= startaddr
;
1584 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1588 if (startaddr
> BLOCK_START (b
))
1589 /* This is the "pathological" case referred to in a comment in
1590 print_frame_info. It might be better to move this check into
1594 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1597 /* If we never found a PDR for this function in symbol reading, then
1598 examine prologues to find the information. */
1601 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1602 if (PROC_FRAME_REG (proc_desc
) == -1)
1612 static mips_extra_func_info_t
1613 find_proc_desc (pc
, next_frame
)
1615 struct frame_info
*next_frame
;
1617 mips_extra_func_info_t proc_desc
;
1618 CORE_ADDR startaddr
;
1620 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1624 /* IF this is the topmost frame AND
1625 * (this proc does not have debugging information OR
1626 * the PC is in the procedure prologue)
1627 * THEN create a "heuristic" proc_desc (by analyzing
1628 * the actual code) to replace the "official" proc_desc.
1630 if (next_frame
== NULL
)
1632 struct symtab_and_line val
;
1633 struct symbol
*proc_symbol
=
1634 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1638 val
= find_pc_line (BLOCK_START
1639 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1641 val
.pc
= val
.end
? val
.end
: pc
;
1643 if (!proc_symbol
|| pc
< val
.pc
)
1645 mips_extra_func_info_t found_heuristic
=
1646 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1648 if (found_heuristic
)
1649 proc_desc
= found_heuristic
;
1655 /* Is linked_proc_desc_table really necessary? It only seems to be used
1656 by procedure call dummys. However, the procedures being called ought
1657 to have their own proc_descs, and even if they don't,
1658 heuristic_proc_desc knows how to create them! */
1660 register struct linked_proc_info
*link
;
1662 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1663 if (PROC_LOW_ADDR(&link
->info
) <= pc
1664 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1668 startaddr
= heuristic_proc_start (pc
);
1671 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1677 get_frame_pointer(frame
, proc_desc
)
1678 struct frame_info
*frame
;
1679 mips_extra_func_info_t proc_desc
;
1681 return ADDR_BITS_REMOVE (
1682 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1683 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1686 mips_extra_func_info_t cached_proc_desc
;
1689 mips_frame_chain(frame
)
1690 struct frame_info
*frame
;
1692 mips_extra_func_info_t proc_desc
;
1694 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1696 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1699 /* Check if the PC is inside a call stub. If it is, fetch the
1700 PC of the caller of that stub. */
1701 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1704 /* Look up the procedure descriptor for this PC. */
1705 proc_desc
= find_proc_desc(saved_pc
, frame
);
1709 cached_proc_desc
= proc_desc
;
1711 /* If no frame pointer and frame size is zero, we must be at end
1712 of stack (or otherwise hosed). If we don't check frame size,
1713 we loop forever if we see a zero size frame. */
1714 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1715 && PROC_FRAME_OFFSET (proc_desc
) == 0
1716 /* The previous frame from a sigtramp frame might be frameless
1717 and have frame size zero. */
1718 && !frame
->signal_handler_caller
)
1721 return get_frame_pointer (frame
, proc_desc
);
1725 init_extra_frame_info(fci
)
1726 struct frame_info
*fci
;
1730 /* Use proc_desc calculated in frame_chain */
1731 mips_extra_func_info_t proc_desc
=
1732 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1734 fci
->saved_regs
= NULL
;
1736 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1739 /* Fixup frame-pointer - only needed for top frame */
1740 /* This may not be quite right, if proc has a real frame register.
1741 Get the value of the frame relative sp, procedure might have been
1742 interrupted by a signal at it's very start. */
1743 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1744 && !PROC_DESC_IS_DUMMY (proc_desc
))
1745 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1747 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1749 if (proc_desc
== &temp_proc_desc
)
1753 /* Do not set the saved registers for a sigtramp frame,
1754 mips_find_saved_registers will do that for us.
1755 We can't use fci->signal_handler_caller, it is not yet set. */
1756 find_pc_partial_function (fci
->pc
, &name
,
1757 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1758 if (!IN_SIGTRAMP (fci
->pc
, name
))
1760 fci
->saved_regs
= (CORE_ADDR
*)
1761 frame_obstack_alloc (SIZEOF_FRAME_SAVED_REGS
);
1762 memcpy (fci
->saved_regs
, temp_saved_regs
.regs
, SIZEOF_FRAME_SAVED_REGS
);
1763 fci
->saved_regs
[PC_REGNUM
]
1764 = fci
->saved_regs
[RA_REGNUM
];
1768 /* hack: if argument regs are saved, guess these contain args */
1769 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1770 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1772 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1774 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1781 /* MIPS stack frames are almost impenetrable. When execution stops,
1782 we basically have to look at symbol information for the function
1783 that we stopped in, which tells us *which* register (if any) is
1784 the base of the frame pointer, and what offset from that register
1785 the frame itself is at.
1787 This presents a problem when trying to examine a stack in memory
1788 (that isn't executing at the moment), using the "frame" command. We
1789 don't have a PC, nor do we have any registers except SP.
1791 This routine takes two arguments, SP and PC, and tries to make the
1792 cached frames look as if these two arguments defined a frame on the
1793 cache. This allows the rest of info frame to extract the important
1794 arguments without difficulty. */
1797 setup_arbitrary_frame (argc
, argv
)
1802 error ("MIPS frame specifications require two arguments: sp and pc");
1804 return create_new_frame (argv
[0], argv
[1]);
1808 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1810 * For n32 ABI, eight.
1811 * For all others, he same as the size of a general register.
1813 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1814 #define MIPS_NABI32 1
1815 #define STACK_ARGSIZE 8
1817 #define MIPS_NABI32 0
1818 #define STACK_ARGSIZE MIPS_REGSIZE
1822 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1827 CORE_ADDR struct_addr
;
1833 int stack_offset
= 0;
1835 /* Macros to round N up or down to the next A boundary; A must be
1837 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1838 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1840 /* First ensure that the stack and structure return address (if any)
1841 are properly aligned. The stack has to be at least 64-bit aligned
1842 even on 32-bit machines, because doubles must be 64-bit aligned.
1843 On at least one MIPS variant, stack frames need to be 128-bit
1844 aligned, so we round to this widest known alignment. */
1845 sp
= ROUND_DOWN (sp
, 16);
1846 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1848 /* Now make space on the stack for the args. We allocate more
1849 than necessary for EABI, because the first few arguments are
1850 passed in registers, but that's OK. */
1851 for (argnum
= 0; argnum
< nargs
; argnum
++)
1852 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1853 sp
-= ROUND_UP (len
, 16);
1855 /* Initialize the integer and float register pointers. */
1857 float_argreg
= FPA0_REGNUM
;
1859 /* the struct_return pointer occupies the first parameter-passing reg */
1861 write_register (argreg
++, struct_addr
);
1863 /* Now load as many as possible of the first arguments into
1864 registers, and push the rest onto the stack. Loop thru args
1865 from first to last. */
1866 for (argnum
= 0; argnum
< nargs
; argnum
++)
1869 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1870 value_ptr arg
= args
[argnum
];
1871 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1872 int len
= TYPE_LENGTH (arg_type
);
1873 enum type_code typecode
= TYPE_CODE (arg_type
);
1875 /* The EABI passes structures that do not fit in a register by
1876 reference. In all other cases, pass the structure by value. */
1877 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1878 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1880 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1881 typecode
= TYPE_CODE_PTR
;
1886 val
= (char *)VALUE_CONTENTS (arg
);
1888 /* 32-bit ABIs always start floating point arguments in an
1889 even-numbered floating point register. */
1890 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1891 && (float_argreg
& 1))
1894 /* Floating point arguments passed in registers have to be
1895 treated specially. On 32-bit architectures, doubles
1896 are passed in register pairs; the even register gets
1897 the low word, and the odd register gets the high word.
1898 On non-EABI processors, the first two floating point arguments are
1899 also copied to general registers, because MIPS16 functions
1900 don't use float registers for arguments. This duplication of
1901 arguments in general registers can't hurt non-MIPS16 functions
1902 because those registers are normally skipped. */
1903 if (typecode
== TYPE_CODE_FLT
1904 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1905 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
1907 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1909 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1910 unsigned long regval
;
1912 /* Write the low word of the double to the even register(s). */
1913 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1914 write_register (float_argreg
++, regval
);
1916 write_register (argreg
+1, regval
);
1918 /* Write the high word of the double to the odd register(s). */
1919 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1920 write_register (float_argreg
++, regval
);
1923 write_register (argreg
, regval
);
1930 /* This is a floating point value that fits entirely
1931 in a single register. */
1932 CORE_ADDR regval
= extract_address (val
, len
);
1933 write_register (float_argreg
++, regval
);
1936 write_register (argreg
, regval
);
1937 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1943 /* Copy the argument to general registers or the stack in
1944 register-sized pieces. Large arguments are split between
1945 registers and stack. */
1946 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1947 are treated specially: Irix cc passes them in registers
1948 where gcc sometimes puts them on the stack. For maximum
1949 compatibility, we will put them in both places. */
1951 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1952 (len
% MIPS_REGSIZE
!= 0));
1955 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1957 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1959 /* Write this portion of the argument to the stack. */
1960 /* Should shorter than int integer values be
1961 promoted to int before being stored? */
1963 int longword_offset
= 0;
1964 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1965 if (STACK_ARGSIZE
== 8 &&
1966 (typecode
== TYPE_CODE_INT
||
1967 typecode
== TYPE_CODE_PTR
||
1968 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1969 longword_offset
= STACK_ARGSIZE
- len
;
1970 else if ((typecode
== TYPE_CODE_STRUCT
||
1971 typecode
== TYPE_CODE_UNION
) &&
1972 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1973 longword_offset
= STACK_ARGSIZE
- len
;
1975 write_memory (sp
+ stack_offset
+ longword_offset
,
1979 /* Note!!! This is NOT an else clause.
1980 Odd sized structs may go thru BOTH paths. */
1981 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1983 CORE_ADDR regval
= extract_address (val
, partial_len
);
1985 /* A non-floating-point argument being passed in a
1986 general register. If a struct or union, and if
1987 the remaining length is smaller than the register
1988 size, we have to adjust the register value on
1991 It does not seem to be necessary to do the
1992 same for integral types.
1994 Also don't do this adjustment on EABI and O64
1998 && (MIPS_REGSIZE
< 8)
1999 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2000 && (partial_len
< MIPS_REGSIZE
)
2001 && (typecode
== TYPE_CODE_STRUCT
||
2002 typecode
== TYPE_CODE_UNION
))
2003 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
2006 write_register (argreg
, regval
);
2009 /* If this is the old ABI, prevent subsequent floating
2010 point arguments from being passed in floating point
2013 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2019 /* The offset onto the stack at which we will start
2020 copying parameters (after the registers are used up)
2021 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2022 leaves room for the "home" area for register parameters.
2024 In the new EABI (and the NABI32), the 8 register parameters
2025 do not have "home" stack space reserved for them, so the
2026 stack offset does not get incremented until after
2027 we have used up the 8 parameter registers. */
2029 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2031 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2036 /* Set the return address register to point to the entry
2037 point of the program, where a breakpoint lies in wait. */
2038 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
2040 /* Return adjusted stack pointer. */
2045 mips_push_register(CORE_ADDR
*sp
, int regno
)
2047 char buffer
[MAX_REGISTER_RAW_SIZE
];
2048 int regsize
= REGISTER_RAW_SIZE (regno
);
2051 read_register_gen (regno
, buffer
);
2052 write_memory (*sp
, buffer
, regsize
);
2055 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2056 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2059 mips_push_dummy_frame()
2062 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2063 xmalloc(sizeof(struct linked_proc_info
));
2064 mips_extra_func_info_t proc_desc
= &link
->info
;
2065 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2066 CORE_ADDR old_sp
= sp
;
2067 link
->next
= linked_proc_desc_table
;
2068 linked_proc_desc_table
= link
;
2070 /* FIXME! are these correct ? */
2071 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2072 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2073 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2074 #define FLOAT_SINGLE_REG_SAVE_MASK \
2075 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2077 * The registers we must save are all those not preserved across
2078 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2079 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2080 * and FP Control/Status registers.
2083 * Dummy frame layout:
2086 * Saved MMHI, MMLO, FPC_CSR
2091 * Saved D18 (i.e. F19, F18)
2093 * Saved D0 (i.e. F1, F0)
2094 * Argument build area and stack arguments written via mips_push_arguments
2098 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2099 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2100 PROC_FRAME_OFFSET(proc_desc
) = 0;
2101 PROC_FRAME_ADJUST(proc_desc
) = 0;
2102 mips_push_register (&sp
, PC_REGNUM
);
2103 mips_push_register (&sp
, HI_REGNUM
);
2104 mips_push_register (&sp
, LO_REGNUM
);
2105 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2107 /* Save general CPU registers */
2108 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2109 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2110 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_REGSIZE
;
2111 for (ireg
= 32; --ireg
>= 0; )
2112 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2113 mips_push_register (&sp
, ireg
);
2115 /* Save floating point registers starting with high order word */
2116 PROC_FREG_MASK(proc_desc
) =
2117 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2118 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2119 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2121 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2122 for (ireg
= 32; --ireg
>= 0; )
2123 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2124 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2126 /* Update the frame pointer for the call dummy and the stack pointer.
2127 Set the procedure's starting and ending addresses to point to the
2128 call dummy address at the entry point. */
2129 write_register (PUSH_FP_REGNUM
, old_sp
);
2130 write_register (SP_REGNUM
, sp
);
2131 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2132 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2133 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2134 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2140 register int regnum
;
2141 struct frame_info
*frame
= get_current_frame ();
2142 CORE_ADDR new_sp
= FRAME_FP (frame
);
2144 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2146 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2147 if (frame
->saved_regs
== NULL
)
2148 mips_find_saved_regs (frame
);
2149 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2151 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2152 && frame
->saved_regs
[regnum
])
2153 write_register (regnum
,
2154 read_memory_integer (frame
->saved_regs
[regnum
],
2157 write_register (SP_REGNUM
, new_sp
);
2158 flush_cached_frames ();
2160 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2162 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2164 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2166 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2168 if (&pi_ptr
->info
== proc_desc
)
2173 error ("Can't locate dummy extra frame info\n");
2175 if (prev_ptr
!= NULL
)
2176 prev_ptr
->next
= pi_ptr
->next
;
2178 linked_proc_desc_table
= pi_ptr
->next
;
2182 write_register (HI_REGNUM
,
2183 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2184 write_register (LO_REGNUM
,
2185 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2186 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2187 write_register (FCRCS_REGNUM
,
2188 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2193 mips_print_register (regnum
, all
)
2196 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2198 /* Get the data in raw format. */
2199 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2201 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2205 /* If an even floating point register, also print as double. */
2206 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2207 && !((regnum
-FP0_REGNUM
) & 1))
2208 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2210 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2212 read_relative_register_raw_bytes (regnum
, dbuffer
);
2213 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2214 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2216 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2217 val_print (builtin_type_double
, dbuffer
, 0,
2218 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2219 printf_filtered ("); ");
2221 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2223 /* The problem with printing numeric register names (r26, etc.) is that
2224 the user can't use them on input. Probably the best solution is to
2225 fix it so that either the numeric or the funky (a2, etc.) names
2226 are accepted on input. */
2227 if (regnum
< MIPS_NUMREGS
)
2228 printf_filtered ("(r%d): ", regnum
);
2230 printf_filtered (": ");
2232 /* If virtual format is floating, print it that way. */
2233 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2234 if (FP_REGISTER_DOUBLE
)
2235 { /* show 8-byte floats as float AND double: */
2236 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2238 printf_filtered (" (float) ");
2239 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
2240 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2241 printf_filtered (", (double) ");
2242 val_print (builtin_type_double
, raw_buffer
, 0,
2243 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2246 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
2247 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2248 /* Else print as integer in hex. */
2250 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2251 'x', 0, gdb_stdout
);
2254 /* Replacement for generic do_registers_info.
2255 Print regs in pretty columns. */
2258 do_fp_register_row (regnum
)
2260 { /* do values for FP (float) regs */
2261 char *raw_buffer
[2];
2263 /* use HI and LO to control the order of combining two flt regs */
2264 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2265 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2266 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2267 int inv1
, inv2
, inv3
;
2269 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2270 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2271 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2273 /* Get the data in raw format. */
2274 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2275 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2276 if (REGISTER_RAW_SIZE(regnum
) == 4)
2278 /* 4-byte registers: we can fit two registers per row. */
2279 /* Also print every pair of 4-byte regs as an 8-byte double. */
2280 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2281 error ("can't read register %d (%s)",
2282 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2284 /* copy the two floats into one double, and unpack both */
2285 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2286 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2287 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2288 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2290 printf_filtered (inv1
? " %-5s: <invalid float>" :
2291 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2292 printf_filtered (inv2
? " %-5s: <invalid float>" :
2293 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2294 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2295 " dbl: %-24.17g\n", doub
);
2296 /* may want to do hex display here (future enhancement) */
2300 { /* eight byte registers: print each one as float AND as double. */
2301 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2303 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2304 flt1
= unpack_double (builtin_type_float
,
2305 &raw_buffer
[HI
][offset
], &inv1
);
2306 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2308 printf_filtered (inv1
? " %-5s: <invalid float>" :
2309 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2310 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2311 " dbl: %-24.17g\n", doub
);
2312 /* may want to do hex display here (future enhancement) */
2318 /* Print a row's worth of GP (int) registers, with name labels above */
2321 do_gp_register_row (regnum
)
2324 /* do values for GP (int) regs */
2325 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2326 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2328 int start_regnum
= regnum
;
2329 int numregs
= NUM_REGS
;
2331 /* start-sanitize-sky */
2332 #ifdef NUM_CORE_REGS
2333 numregs
= NUM_CORE_REGS
;
2335 /* end-sanitize-sky */
2337 /* For GP registers, we print a separate row of names above the vals */
2338 printf_filtered (" ");
2339 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2341 if (*REGISTER_NAME (regnum
) == '\0')
2342 continue; /* unused register */
2343 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2344 break; /* end the row: reached FP register */
2345 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2346 REGISTER_NAME (regnum
));
2349 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2350 start_regnum
); /* print the R0 to R31 names */
2352 regnum
= start_regnum
; /* go back to start of row */
2353 /* now print the values in hex, 4 or 8 to the row */
2354 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2356 if (*REGISTER_NAME (regnum
) == '\0')
2357 continue; /* unused register */
2358 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2359 break; /* end row: reached FP register */
2360 /* OK: get the data in raw format. */
2361 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2362 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2363 /* pad small registers */
2364 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2365 printf_filtered (" ");
2366 /* Now print the register value in hex, endian order. */
2367 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2368 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2369 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2371 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2372 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2373 printf_filtered (" ");
2376 if (col
> 0) /* ie. if we actually printed anything... */
2377 printf_filtered ("\n");
2382 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2385 mips_do_registers_info (regnum
, fpregs
)
2389 if (regnum
!= -1) /* do one specified register */
2391 if (*(REGISTER_NAME (regnum
)) == '\0')
2392 error ("Not a valid register for the current processor type");
2394 mips_print_register (regnum
, 0);
2395 printf_filtered ("\n");
2397 else /* do all (or most) registers */
2400 while (regnum
< NUM_REGS
)
2402 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2403 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2404 regnum
= do_fp_register_row (regnum
); /* FP regs */
2406 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2408 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2409 /* start-sanitize-sky */
2410 #ifdef NUM_CORE_REGS
2411 /* For the sky project, NUM_REGS includes the vector slaves,
2412 which are handled elsewhere */
2413 if (regnum
>= NUM_CORE_REGS
)
2416 /* end-sanitize-sky */
2421 /* Return number of args passed to a frame. described by FIP.
2422 Can return -1, meaning no way to tell. */
2425 mips_frame_num_args (frame
)
2426 struct frame_info
*frame
;
2428 #if 0 /* FIXME Use or lose this! */
2429 struct chain_info_t
*p
;
2431 p
= mips_find_cached_frame (FRAME_FP (frame
));
2433 return p
->the_info
.numargs
;
2438 /* Is this a branch with a delay slot? */
2440 static int is_delayed
PARAMS ((unsigned long));
2447 for (i
= 0; i
< NUMOPCODES
; ++i
)
2448 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2449 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2451 return (i
< NUMOPCODES
2452 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2453 | INSN_COND_BRANCH_DELAY
2454 | INSN_COND_BRANCH_LIKELY
)));
2458 mips_step_skips_delay (pc
)
2461 char buf
[MIPS_INSTLEN
];
2463 /* There is no branch delay slot on MIPS16. */
2464 if (pc_is_mips16 (pc
))
2467 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2468 /* If error reading memory, guess that it is not a delayed branch. */
2470 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2474 /* Skip the PC past function prologue instructions (32-bit version).
2475 This is a helper function for mips_skip_prologue. */
2478 mips32_skip_prologue (pc
, lenient
)
2479 CORE_ADDR pc
; /* starting PC to search from */
2484 int seen_sp_adjust
= 0;
2485 int load_immediate_bytes
= 0;
2487 /* Skip the typical prologue instructions. These are the stack adjustment
2488 instruction and the instructions that save registers on the stack
2489 or in the gcc frame. */
2490 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2492 unsigned long high_word
;
2494 inst
= mips_fetch_instruction (pc
);
2495 high_word
= (inst
>> 16) & 0xffff;
2498 if (lenient
&& is_delayed (inst
))
2502 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2503 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2505 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2506 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2508 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2509 /* start-sanitize-r5900 */
2510 || (inst
& 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */
2511 /* end-sanitize-r5900 */
2512 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2513 && (inst
& 0x001F0000)) /* reg != $zero */
2516 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2518 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2520 continue; /* reg != $zero */
2522 /* move $s8,$sp. With different versions of gas this will be either
2523 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2524 Accept any one of these. */
2525 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2528 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2530 else if (high_word
== 0x3c1c) /* lui $gp,n */
2532 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2534 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2535 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2537 /* The following instructions load $at or $t0 with an immediate
2538 value in preparation for a stack adjustment via
2539 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2540 a local variable, so we accept them only before a stack adjustment
2541 instruction was seen. */
2542 else if (!seen_sp_adjust
)
2544 if (high_word
== 0x3c01 || /* lui $at,n */
2545 high_word
== 0x3c08) /* lui $t0,n */
2547 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2550 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2551 high_word
== 0x3508 || /* ori $t0,$t0,n */
2552 high_word
== 0x3401 || /* ori $at,$zero,n */
2553 high_word
== 0x3408) /* ori $t0,$zero,n */
2555 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2565 /* In a frameless function, we might have incorrectly
2566 skipped some load immediate instructions. Undo the skipping
2567 if the load immediate was not followed by a stack adjustment. */
2568 if (load_immediate_bytes
&& !seen_sp_adjust
)
2569 pc
-= load_immediate_bytes
;
2573 /* Skip the PC past function prologue instructions (16-bit version).
2574 This is a helper function for mips_skip_prologue. */
2577 mips16_skip_prologue (pc
, lenient
)
2578 CORE_ADDR pc
; /* starting PC to search from */
2582 int extend_bytes
= 0;
2583 int prev_extend_bytes
;
2585 /* Table of instructions likely to be found in a function prologue. */
2588 unsigned short inst
;
2589 unsigned short mask
;
2592 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2593 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2594 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2595 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2596 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2597 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2598 { 0x673d, 0xffff }, /* move $s1,sp */
2599 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2600 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2601 { 0xe809, 0xf81f }, /* entry pseudo-op */
2602 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2603 { 0, 0 } /* end of table marker */
2606 /* Skip the typical prologue instructions. These are the stack adjustment
2607 instruction and the instructions that save registers on the stack
2608 or in the gcc frame. */
2609 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2611 unsigned short inst
;
2614 inst
= mips_fetch_instruction (pc
);
2616 /* Normally we ignore an extend instruction. However, if it is
2617 not followed by a valid prologue instruction, we must adjust
2618 the pc back over the extend so that it won't be considered
2619 part of the prologue. */
2620 if ((inst
& 0xf800) == 0xf000) /* extend */
2622 extend_bytes
= MIPS16_INSTLEN
;
2625 prev_extend_bytes
= extend_bytes
;
2628 /* Check for other valid prologue instructions besides extend. */
2629 for (i
= 0; table
[i
].mask
!= 0; i
++)
2630 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2632 if (table
[i
].mask
!= 0) /* it was in table? */
2633 continue; /* ignore it */
2634 else /* non-prologue */
2636 /* Return the current pc, adjusted backwards by 2 if
2637 the previous instruction was an extend. */
2638 return pc
- prev_extend_bytes
;
2644 /* To skip prologues, I use this predicate. Returns either PC itself
2645 if the code at PC does not look like a function prologue; otherwise
2646 returns an address that (if we're lucky) follows the prologue. If
2647 LENIENT, then we must skip everything which is involved in setting
2648 up the frame (it's OK to skip more, just so long as we don't skip
2649 anything which might clobber the registers which are being saved.
2650 We must skip more in the case where part of the prologue is in the
2651 delay slot of a non-prologue instruction). */
2654 mips_skip_prologue (pc
, lenient
)
2658 /* See if we can determine the end of the prologue via the symbol table.
2659 If so, then return either PC, or the PC after the prologue, whichever
2662 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2664 if (post_prologue_pc
!= 0)
2665 return max (pc
, post_prologue_pc
);
2667 /* Can't determine prologue from the symbol table, need to examine
2670 if (pc_is_mips16 (pc
))
2671 return mips16_skip_prologue (pc
, lenient
);
2673 return mips32_skip_prologue (pc
, lenient
);
2677 /* The lenient prologue stuff should be superseded by the code in
2678 init_extra_frame_info which looks to see whether the stores mentioned
2679 in the proc_desc have actually taken place. */
2681 /* Is address PC in the prologue (loosely defined) for function at
2685 mips_in_lenient_prologue (startaddr
, pc
)
2686 CORE_ADDR startaddr
;
2689 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2690 return pc
>= startaddr
&& pc
< end_prologue
;
2694 /* Given a return value in `regbuf' with a type `valtype',
2695 extract and copy its value into `valbuf'. */
2697 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2698 struct type
*valtype
;
2699 char regbuf
[REGISTER_BYTES
];
2704 int len
= TYPE_LENGTH (valtype
);
2707 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2708 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2709 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2710 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2711 regnum
= FP0_REGNUM
;
2713 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2714 { /* "un-left-justify" the value from the register */
2715 if (len
< REGISTER_RAW_SIZE (regnum
))
2716 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2717 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2718 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2719 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2720 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2721 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2723 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2724 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2727 /* Given a return value in `regbuf' with a type `valtype',
2728 write it's value into the appropriate register. */
2730 mips_store_return_value (valtype
, valbuf
)
2731 struct type
*valtype
;
2736 int len
= TYPE_LENGTH (valtype
);
2737 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2740 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2741 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2742 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2743 && len
<= MIPS_REGSIZE
)))
2744 regnum
= FP0_REGNUM
;
2746 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2747 { /* "left-justify" the value in the register */
2748 if (len
< REGISTER_RAW_SIZE (regnum
))
2749 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2750 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2751 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2752 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2753 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2754 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2756 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2757 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2758 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2759 len
> REGISTER_RAW_SIZE (regnum
) ?
2760 len
: REGISTER_RAW_SIZE (regnum
));
2763 /* Exported procedure: Is PC in the signal trampoline code */
2766 in_sigtramp (pc
, ignore
)
2768 char *ignore
; /* function name */
2770 if (sigtramp_address
== 0)
2772 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2775 /* Commands to show/set the MIPS FPU type. */
2777 static void show_mipsfpu_command
PARAMS ((char *, int));
2779 show_mipsfpu_command (args
, from_tty
)
2785 switch (MIPS_FPU_TYPE
)
2787 case MIPS_FPU_SINGLE
:
2788 fpu
= "single-precision";
2790 case MIPS_FPU_DOUBLE
:
2791 fpu
= "double-precision";
2794 fpu
= "absent (none)";
2797 if (mips_fpu_type_auto
)
2798 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
2801 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
2806 static void set_mipsfpu_command
PARAMS ((char *, int));
2808 set_mipsfpu_command (args
, from_tty
)
2812 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
2813 show_mipsfpu_command (args
, from_tty
);
2816 static void set_mipsfpu_single_command
PARAMS ((char *, int));
2818 set_mipsfpu_single_command (args
, from_tty
)
2822 mips_fpu_type
= MIPS_FPU_SINGLE
;
2823 mips_fpu_type_auto
= 0;
2824 /* start-sanitize-carp start-sanitize-vr4xxx */
2827 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
2829 /* end-sanitize-carp end-sanitize-vr4xxx */
2832 static void set_mipsfpu_double_command
PARAMS ((char *, int));
2834 set_mipsfpu_double_command (args
, from_tty
)
2838 mips_fpu_type
= MIPS_FPU_DOUBLE
;
2839 mips_fpu_type_auto
= 0;
2840 /* start-sanitize-carp start-sanitize-vr4xxx */
2843 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
2845 /* end-sanitize-carp end-sanitize-vr4xxx */
2848 static void set_mipsfpu_none_command
PARAMS ((char *, int));
2850 set_mipsfpu_none_command (args
, from_tty
)
2854 mips_fpu_type
= MIPS_FPU_NONE
;
2855 mips_fpu_type_auto
= 0;
2856 /* start-sanitize-carp start-sanitize-vr4xxx */
2859 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
2861 /* end-sanitize-carp end-sanitize-vr4xxx */
2864 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
2866 set_mipsfpu_auto_command (args
, from_tty
)
2870 mips_fpu_type_auto
= 1;
2873 /* Command to set the processor type. */
2876 mips_set_processor_type_command (args
, from_tty
)
2882 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2884 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2885 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2886 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2888 /* Restore the value. */
2889 tmp_mips_processor_type
= strsave (mips_processor_type
);
2894 if (!mips_set_processor_type (tmp_mips_processor_type
))
2896 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2897 /* Restore its value. */
2898 tmp_mips_processor_type
= strsave (mips_processor_type
);
2903 mips_show_processor_type_command (args
, from_tty
)
2909 /* Modify the actual processor type. */
2912 mips_set_processor_type (str
)
2920 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2922 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2924 mips_processor_type
= str
;
2926 for (j
= 0; j
< NUM_REGS
; ++j
)
2927 /* FIXME - MIPS should be defining REGISTER_NAME() instead */
2928 gdb_register_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2932 /* FIXME tweak fpu flag too */
2939 /* Attempt to identify the particular processor model by reading the
2943 mips_read_processor_type ()
2947 prid
= read_register (PRID_REGNUM
);
2949 if ((prid
& ~0xf) == 0x700)
2950 return savestring ("r3041", strlen("r3041"));
2955 /* Just like reinit_frame_cache, but with the right arguments to be
2956 callable as an sfunc. */
2959 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2962 struct cmd_list_element
*c
;
2964 reinit_frame_cache ();
2968 gdb_print_insn_mips (memaddr
, info
)
2970 disassemble_info
*info
;
2972 mips_extra_func_info_t proc_desc
;
2974 /* Search for the function containing this address. Set the low bit
2975 of the address when searching, in case we were given an even address
2976 that is the start of a 16-bit function. If we didn't do this,
2977 the search would fail because the symbol table says the function
2978 starts at an odd address, i.e. 1 byte past the given address. */
2979 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2980 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2982 /* Make an attempt to determine if this is a 16-bit function. If
2983 the procedure descriptor exists and the address therein is odd,
2984 it's definitely a 16-bit function. Otherwise, we have to just
2985 guess that if the address passed in is odd, it's 16-bits. */
2987 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2989 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2991 /* Round down the instruction address to the appropriate boundary. */
2992 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2994 /* Call the appropriate disassembler based on the target endian-ness. */
2995 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2996 return print_insn_big_mips (memaddr
, info
);
2998 return print_insn_little_mips (memaddr
, info
);
3001 /* Old-style breakpoint macros.
3002 The IDT board uses an unusual breakpoint value, and sometimes gets
3003 confused when it sees the usual MIPS breakpoint instruction. */
3005 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3006 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3007 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3008 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3009 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3010 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3011 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3012 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3014 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3015 counter value to determine whether a 16- or 32-bit breakpoint should be
3016 used. It returns a pointer to a string of bytes that encode a breakpoint
3017 instruction, stores the length of the string to *lenptr, and adjusts pc
3018 (if necessary) to point to the actual memory location where the
3019 breakpoint should be inserted. */
3021 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
3025 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3027 if (pc_is_mips16 (*pcptr
))
3029 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3030 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3031 *lenptr
= sizeof(mips16_big_breakpoint
);
3032 return mips16_big_breakpoint
;
3036 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3037 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3038 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3040 *lenptr
= sizeof(big_breakpoint
);
3042 if (strcmp (target_shortname
, "mips") == 0)
3043 return idt_big_breakpoint
;
3044 else if (strcmp (target_shortname
, "ddb") == 0
3045 || strcmp (target_shortname
, "pmon") == 0
3046 || strcmp (target_shortname
, "lsi") == 0)
3047 return pmon_big_breakpoint
;
3049 return big_breakpoint
;
3054 if (pc_is_mips16 (*pcptr
))
3056 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3057 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3058 *lenptr
= sizeof(mips16_little_breakpoint
);
3059 return mips16_little_breakpoint
;
3063 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3064 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3065 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3067 *lenptr
= sizeof(little_breakpoint
);
3069 if (strcmp (target_shortname
, "mips") == 0)
3070 return idt_little_breakpoint
;
3071 else if (strcmp (target_shortname
, "ddb") == 0
3072 || strcmp (target_shortname
, "pmon") == 0
3073 || strcmp (target_shortname
, "lsi") == 0)
3074 return pmon_little_breakpoint
;
3076 return little_breakpoint
;
3081 /* If PC is in a mips16 call or return stub, return the address of the target
3082 PC, which is either the callee or the caller. There are several
3083 cases which must be handled:
3085 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3086 target PC is in $31 ($ra).
3087 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3088 and the target PC is in $2.
3089 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3090 before the jal instruction, this is effectively a call stub
3091 and the the target PC is in $2. Otherwise this is effectively
3092 a return stub and the target PC is in $18.
3094 See the source code for the stubs in gcc/config/mips/mips16.S for
3097 This function implements the SKIP_TRAMPOLINE_CODE macro.
3105 CORE_ADDR start_addr
;
3107 /* Find the starting address and name of the function containing the PC. */
3108 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3111 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3112 target PC is in $31 ($ra). */
3113 if (strcmp (name
, "__mips16_ret_sf") == 0
3114 || strcmp (name
, "__mips16_ret_df") == 0)
3115 return read_register (RA_REGNUM
);
3117 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3119 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3120 and the target PC is in $2. */
3121 if (name
[19] >= '0' && name
[19] <= '9')
3122 return read_register (2);
3124 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3125 before the jal instruction, this is effectively a call stub
3126 and the the target PC is in $2. Otherwise this is effectively
3127 a return stub and the target PC is in $18. */
3128 else if (name
[19] == 's' || name
[19] == 'd')
3130 if (pc
== start_addr
)
3132 /* Check if the target of the stub is a compiler-generated
3133 stub. Such a stub for a function bar might have a name
3134 like __fn_stub_bar, and might look like this:
3139 la $1,bar (becomes a lui/addiu pair)
3141 So scan down to the lui/addi and extract the target
3142 address from those two instructions. */
3144 CORE_ADDR target_pc
= read_register (2);
3148 /* See if the name of the target function is __fn_stub_*. */
3149 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3151 if (strncmp (name
, "__fn_stub_", 10) != 0
3152 && strcmp (name
, "etext") != 0
3153 && strcmp (name
, "_etext") != 0)
3156 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3157 The limit on the search is arbitrarily set to 20
3158 instructions. FIXME. */
3159 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3161 inst
= mips_fetch_instruction (target_pc
);
3162 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3163 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3164 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3165 return pc
| (inst
& 0xffff); /* low word */
3168 /* Couldn't find the lui/addui pair, so return stub address. */
3172 /* This is the 'return' part of a call stub. The return
3173 address is in $r18. */
3174 return read_register (18);
3177 return 0; /* not a stub */
3181 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3182 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3185 mips_in_call_stub (pc
, name
)
3189 CORE_ADDR start_addr
;
3191 /* Find the starting address of the function containing the PC. If the
3192 caller didn't give us a name, look it up at the same time. */
3193 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3196 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3198 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3199 if (name
[19] >= '0' && name
[19] <= '9')
3201 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3202 before the jal instruction, this is effectively a call stub. */
3203 else if (name
[19] == 's' || name
[19] == 'd')
3204 return pc
== start_addr
;
3207 return 0; /* not a stub */
3211 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3212 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3215 mips_in_return_stub (pc
, name
)
3219 CORE_ADDR start_addr
;
3221 /* Find the starting address of the function containing the PC. */
3222 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3225 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3226 if (strcmp (name
, "__mips16_ret_sf") == 0
3227 || strcmp (name
, "__mips16_ret_df") == 0)
3230 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3231 i.e. after the jal instruction, this is effectively a return stub. */
3232 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3233 && (name
[19] == 's' || name
[19] == 'd')
3234 && pc
!= start_addr
)
3237 return 0; /* not a stub */
3241 /* Return non-zero if the PC is in a library helper function that should
3242 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3245 mips_ignore_helper (pc
)
3250 /* Find the starting address and name of the function containing the PC. */
3251 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3254 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3255 that we want to ignore. */
3256 return (strcmp (name
, "__mips16_ret_sf") == 0
3257 || strcmp (name
, "__mips16_ret_df") == 0);
3261 /* Return a location where we can set a breakpoint that will be hit
3262 when an inferior function call returns. This is normally the
3263 program's entry point. Executables that don't have an entry
3264 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3265 whose address is the location where the breakpoint should be placed. */
3268 mips_call_dummy_address ()
3270 struct minimal_symbol
*sym
;
3272 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3274 return SYMBOL_VALUE_ADDRESS (sym
);
3276 return entry_point_address ();
3279 /* start-sanitize-carp start-sanitize-vr4xxx */
3281 static gdbarch_init_ftype mips_gdbarch_init
;
3282 static struct gdbarch
*
3283 mips_gdbarch_init (info
, arches
)
3284 struct gdbarch_info info
;
3285 struct gdbarch_list
*arches
;
3287 struct gdbarch
*gdbarch
;
3288 struct gdbarch_tdep
*tdep
;
3292 /* find a default for ELF_ABI */
3293 if (info
.abfd
!= NULL
)
3294 elf_abi
= elf_elfheader (info
.abfd
)->e_flags
& EF_MIPS_ABI
;
3295 else if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_mips
)
3296 elf_abi
= gdbarch_tdep (current_gdbarch
)->elf_abi
;
3300 /* try to find a pre-existing architecture */
3301 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3303 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3305 /* MIPS needs to be pedantic about which ABI the object is
3307 if (gdbarch_tdep (current_gdbarch
)->elf_abi
!= elf_abi
)
3309 return arches
->gdbarch
;
3312 /* Need a new architecture. Fill in a target specific vector. */
3313 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3314 gdbarch
= gdbarch_alloc (&info
, tdep
);
3315 tdep
->elf_abi
= elf_abi
;
3318 case E_MIPS_ABI_O32
:
3320 tdep
->mips_eabi
= 0;
3321 set_gdbarch_long_bit (gdbarch
, 32);
3322 set_gdbarch_ptr_bit (gdbarch
, 32);
3324 case E_MIPS_ABI_O64
:
3326 tdep
->mips_eabi
= 0;
3327 set_gdbarch_long_bit (gdbarch
, 32);
3328 set_gdbarch_ptr_bit (gdbarch
, 32);
3330 case E_MIPS_ABI_EABI32
:
3331 abi_name
= "eabi32";
3332 tdep
->mips_eabi
= 1;
3333 set_gdbarch_long_bit (gdbarch
, 32);
3334 set_gdbarch_ptr_bit (gdbarch
, 32);
3336 case E_MIPS_ABI_EABI64
:
3337 abi_name
= "eabi64";
3338 tdep
->mips_eabi
= 1;
3339 set_gdbarch_long_bit (gdbarch
, 64);
3340 set_gdbarch_ptr_bit (gdbarch
, 64);
3343 abi_name
= "default";
3344 tdep
->mips_eabi
= 0;
3345 set_gdbarch_long_bit (gdbarch
, 32);
3346 set_gdbarch_ptr_bit (gdbarch
, 32);
3349 if (tdep
->mips_eabi
)
3351 /* EABI uses R4 through R11 for args */
3352 tdep
->mips_last_arg_regnum
= 11;
3353 /* EABI uses F12 through F19 for args */
3354 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3358 /* old ABI uses R4 through R7 for args */
3359 tdep
->mips_last_arg_regnum
= 7;
3360 /* old ABI uses F12 through F15 for args */
3361 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3363 set_gdbarch_long_long_bit (gdbarch
, 64);
3365 /* enable/disable the MIPS FPU */
3366 if (!mips_fpu_type_auto
)
3367 tdep
->mips_fpu_type
= mips_fpu_type
;
3368 else if (info
.bfd_arch_info
!= NULL
3369 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3370 switch (info
.bfd_arch_info
->mach
)
3372 case bfd_mach_mips4100
:
3373 case bfd_mach_mips4111
:
3374 case bfd_mach_mips4121
:
3375 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
3378 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3382 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3386 fprintf_unfiltered (stderr
,
3387 "mips_gdbarch_init: (info)elf_abi 0x%x (%s)\n",
3389 fprintf_unfiltered (stderr
,
3390 "mips_gdbarch_init: MIPS_EABI = %d\n",
3392 fprintf_unfiltered (stderr
,
3393 "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n",
3394 tdep
->mips_last_arg_regnum
);
3395 fprintf_unfiltered (stderr
,
3396 "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n",
3397 tdep
->mips_last_fp_arg_regnum
,
3398 tdep
->mips_last_fp_arg_regnum
- FP0_REGNUM
);
3399 fprintf_unfiltered (stderr
,
3400 "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
3401 tdep
->mips_fpu_type
,
3402 (tdep
->mips_fpu_type
== MIPS_FPU_NONE
? "none"
3403 : tdep
->mips_fpu_type
== MIPS_FPU_SINGLE
? "single"
3404 : tdep
->mips_fpu_type
== MIPS_FPU_DOUBLE
? "double"
3411 /* end-sanitize-carp end-sanitize-vr4xxx */
3414 _initialize_mips_tdep ()
3416 static struct cmd_list_element
*mipsfpulist
= NULL
;
3417 struct cmd_list_element
*c
;
3419 /* start-sanitize-carp start-sanitize-vr4xxx */
3421 register_gdbarch_init (bfd_arch_mips
, mips_gdbarch_init
);
3422 /* end-sanitize-carp end-sanitize-vr4xxx */
3423 if (!tm_print_insn
) /* Someone may have already set it */
3424 tm_print_insn
= gdb_print_insn_mips
;
3426 /* Let the user turn off floating point and set the fence post for
3427 heuristic_proc_start. */
3429 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3430 "Set use of MIPS floating-point coprocessor.",
3431 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3432 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3433 "Select single-precision MIPS floating-point coprocessor.",
3435 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3436 "Select double-precision MIPS floating-point coprocessor .",
3438 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3439 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3440 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3441 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3442 "Select no MIPS floating-point coprocessor.",
3444 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3445 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3446 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3447 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3448 "Select MIPS floating-point coprocessor automatically.",
3450 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3451 "Show current use of MIPS floating-point coprocessor target.",
3454 /* start-sanitize-carp start-sanitize-vr4xxx */
3456 /* end-sanitize-carp end-sanitize-vr4xxx */
3457 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3458 (char *) &tmp_mips_processor_type
,
3459 "Set the type of MIPS processor in use.\n\
3460 Set this to be able to access processor-type-specific registers.\n\
3463 c
->function
.cfunc
= mips_set_processor_type_command
;
3464 c
= add_show_from_set (c
, &showlist
);
3465 c
->function
.cfunc
= mips_show_processor_type_command
;
3467 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3468 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3469 /* start-sanitize-carp start-sanitize-vr4xxx */
3471 /* end-sanitize-carp end-sanitize-vr4xxx */
3473 /* We really would like to have both "0" and "unlimited" work, but
3474 command.c doesn't deal with that. So make it a var_zinteger
3475 because the user can always use "999999" or some such for unlimited. */
3476 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3477 (char *) &heuristic_fence_post
,
3479 Set the distance searched for the start of a function.\n\
3480 If you are debugging a stripped executable, GDB needs to search through the\n\
3481 program for the start of a function. This command sets the distance of the\n\
3482 search. The only need to set it is when debugging a stripped executable.",
3484 /* We need to throw away the frame cache when we set this, since it
3485 might change our ability to get backtraces. */
3486 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3487 add_show_from_set (c
, &showlist
);
3489 /* Allow the user to control whether the upper bits of 64-bit
3490 addresses should be zeroed. */
3492 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3493 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3494 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3495 Without an argument, zeroing of upper address bits is enabled.", &setlist
),