1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 const struct register_alias mips_numeric_register_aliases
[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto
= 1;
160 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
162 static int mips_debug
= 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc
*mips_tdesc_gp32
;
170 struct target_desc
*mips_tdesc_gp64
;
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
189 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
191 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
192 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
194 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
196 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
197 functions to test, set, or clear bit 0 of addresses. */
200 is_mips16_addr (CORE_ADDR addr
)
206 unmake_mips16_addr (CORE_ADDR addr
)
208 return ((addr
) & ~(CORE_ADDR
) 1);
212 make_mips16_addr (CORE_ADDR addr
)
214 return ((addr
) | (CORE_ADDR
) 1);
217 /* Return the MIPS ABI associated with GDBARCH. */
219 mips_abi (struct gdbarch
*gdbarch
)
221 return gdbarch_tdep (gdbarch
)->mips_abi
;
225 mips_isa_regsize (struct gdbarch
*gdbarch
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 /* If we know how big the registers are, use that size. */
230 if (tdep
->register_size_valid_p
)
231 return tdep
->register_size
;
233 /* Fall back to the previous behavior. */
234 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
238 /* Return the currently configured (or set) saved register size. */
241 mips_abi_regsize (struct gdbarch
*gdbarch
)
243 switch (mips_abi (gdbarch
))
245 case MIPS_ABI_EABI32
:
251 case MIPS_ABI_EABI64
:
253 case MIPS_ABI_UNKNOWN
:
256 internal_error (__FILE__
, __LINE__
, _("bad switch"));
260 /* Functions for setting and testing a bit in a minimal symbol that
261 marks it as 16-bit function. The MSB of the minimal symbol's
262 "info" field is used for this purpose.
264 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
265 i.e. refers to a 16-bit function, and sets a "special" bit in a
266 minimal symbol to mark it as a 16-bit function
268 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
271 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
273 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
275 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
280 msymbol_is_special (struct minimal_symbol
*msym
)
282 return MSYMBOL_TARGET_FLAG_1 (msym
);
285 /* XFER a value from the big/little/left end of the register.
286 Depending on the size of the value it might occupy the entire
287 register or just part of it. Make an allowance for this, aligning
288 things accordingly. */
291 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
292 int reg_num
, int length
,
293 enum bfd_endian endian
, gdb_byte
*in
,
294 const gdb_byte
*out
, int buf_offset
)
298 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
299 /* Need to transfer the left or right part of the register, based on
300 the targets byte order. */
304 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
306 case BFD_ENDIAN_LITTLE
:
309 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
313 internal_error (__FILE__
, __LINE__
, _("bad switch"));
316 fprintf_unfiltered (gdb_stderr
,
317 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
318 reg_num
, reg_offset
, buf_offset
, length
);
319 if (mips_debug
&& out
!= NULL
)
322 fprintf_unfiltered (gdb_stdlog
, "out ");
323 for (i
= 0; i
< length
; i
++)
324 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
327 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
330 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
332 if (mips_debug
&& in
!= NULL
)
335 fprintf_unfiltered (gdb_stdlog
, "in ");
336 for (i
= 0; i
< length
; i
++)
337 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
340 fprintf_unfiltered (gdb_stdlog
, "\n");
343 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
344 compatiblity mode. A return value of 1 means that we have
345 physical 64-bit registers, but should treat them as 32-bit registers. */
348 mips2_fp_compat (struct frame_info
*frame
)
350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
351 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
353 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
357 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
358 in all the places we deal with FP registers. PR gdb/413. */
359 /* Otherwise check the FR bit in the status register - it controls
360 the FP compatiblity mode. If it is clear we are in compatibility
362 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
369 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
371 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
373 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
375 /* The list of available "set mips " and "show mips " commands. */
377 static struct cmd_list_element
*setmipscmdlist
= NULL
;
378 static struct cmd_list_element
*showmipscmdlist
= NULL
;
380 /* Integer registers 0 thru 31 are handled explicitly by
381 mips_register_name(). Processor specific registers 32 and above
382 are listed in the following tables. */
385 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
389 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
390 "sr", "lo", "hi", "bad", "cause", "pc",
391 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
392 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
393 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
394 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
395 "fsr", "fir", "" /*"fp" */ , "",
396 "", "", "", "", "", "", "", "",
397 "", "", "", "", "", "", "", "",
400 /* Names of IDT R3041 registers. */
402 static const char *mips_r3041_reg_names
[] = {
403 "sr", "lo", "hi", "bad", "cause", "pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "", /*"fp" */ "",
409 "", "", "bus", "ccfg", "", "", "", "",
410 "", "", "port", "cmp", "", "", "epc", "prid",
413 /* Names of tx39 registers. */
415 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
423 "", "", "config", "cache", "debug", "depc", "epc", ""
426 /* Names of IRIX registers. */
427 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
436 /* Return the name of the register corresponding to REGNO. */
438 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
441 /* GPR names for all ABIs other than n32/n64. */
442 static char *mips_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
449 /* GPR names for n32 and n64 ABIs. */
450 static char *mips_n32_n64_gpr_names
[] = {
451 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
452 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
457 enum mips_abi abi
= mips_abi (gdbarch
);
459 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
460 but then don't make the raw register names visible. This (upper)
461 range of user visible register numbers are the pseudo-registers.
463 This approach was adopted accommodate the following scenario:
464 It is possible to debug a 64-bit device using a 32-bit
465 programming model. In such instances, the raw registers are
466 configured to be 64-bits wide, while the pseudo registers are
467 configured to be 32-bits wide. The registers that the user
468 sees - the pseudo registers - match the users expectations
469 given the programming model being used. */
470 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
471 if (regno
< gdbarch_num_regs (gdbarch
))
474 /* The MIPS integer registers are always mapped from 0 to 31. The
475 names of the registers (which reflects the conventions regarding
476 register use) vary depending on the ABI. */
477 if (0 <= rawnum
&& rawnum
< 32)
479 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
480 return mips_n32_n64_gpr_names
[rawnum
];
482 return mips_gpr_names
[rawnum
];
484 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
485 return tdesc_register_name (gdbarch
, rawnum
);
486 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
488 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
489 return tdep
->mips_processor_reg_names
[rawnum
- 32];
492 internal_error (__FILE__
, __LINE__
,
493 _("mips_register_name: bad register number %d"), rawnum
);
496 /* Return the groups that a MIPS register can be categorised into. */
499 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
500 struct reggroup
*reggroup
)
505 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
506 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
507 if (reggroup
== all_reggroup
)
509 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
510 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
511 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
512 (gdbarch), as not all architectures are multi-arch. */
513 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
514 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
515 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
517 if (reggroup
== float_reggroup
)
518 return float_p
&& pseudo
;
519 if (reggroup
== vector_reggroup
)
520 return vector_p
&& pseudo
;
521 if (reggroup
== general_reggroup
)
522 return (!vector_p
&& !float_p
) && pseudo
;
523 /* Save the pseudo registers. Need to make certain that any code
524 extracting register values from a saved register cache also uses
526 if (reggroup
== save_reggroup
)
527 return raw_p
&& pseudo
;
528 /* Restore the same pseudo register. */
529 if (reggroup
== restore_reggroup
)
530 return raw_p
&& pseudo
;
534 /* Return the groups that a MIPS register can be categorised into.
535 This version is only used if we have a target description which
536 describes real registers (and their groups). */
539 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
540 struct reggroup
*reggroup
)
542 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
543 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
546 /* Only save, restore, and display the pseudo registers. Need to
547 make certain that any code extracting register values from a
548 saved register cache also uses pseudo registers.
550 Note: saving and restoring the pseudo registers is slightly
551 strange; if we have 64 bits, we should save and restore all
552 64 bits. But this is hard and has little benefit. */
556 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
560 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
563 /* Map the symbol table registers which live in the range [1 *
564 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
565 registers. Take care of alignment and size problems. */
567 static enum register_status
568 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
569 int cookednum
, gdb_byte
*buf
)
571 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
572 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
573 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 return regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
580 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
585 enum register_status status
;
587 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
588 if (status
== REG_VALID
)
589 store_signed_integer (buf
, 4, byte_order
, regval
);
594 internal_error (__FILE__
, __LINE__
, _("bad register size"));
598 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
599 struct regcache
*regcache
, int cookednum
,
602 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
603 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
604 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
605 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
606 regcache_raw_write (regcache
, rawnum
, buf
);
607 else if (register_size (gdbarch
, rawnum
) >
608 register_size (gdbarch
, cookednum
))
610 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
611 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
614 /* Sign extend the shortened version of the register prior
615 to placing it in the raw register. This is required for
616 some mips64 parts in order to avoid unpredictable behavior. */
617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
618 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
619 regcache_raw_write_signed (regcache
, rawnum
, regval
);
623 internal_error (__FILE__
, __LINE__
, _("bad register size"));
627 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
628 struct agent_expr
*ax
, int reg
)
630 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
631 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
632 && reg
< 2 * gdbarch_num_regs (gdbarch
));
634 ax_reg_mask (ax
, rawnum
);
640 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
641 struct agent_expr
*ax
, int reg
)
643 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
645 && reg
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
650 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
652 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
653 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
656 ax_simple (ax
, aop_lsh
);
659 ax_simple (ax
, aop_rsh_signed
);
663 internal_error (__FILE__
, __LINE__
, _("bad register size"));
668 /* Table to translate MIPS16 register field to actual register number. */
669 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
671 /* Heuristic_proc_start may hunt through the text section for a long
672 time across a 2400 baud serial line. Allows the user to limit this
675 static unsigned int heuristic_fence_post
= 0;
677 /* Number of bytes of storage in the actual machine representation for
678 register N. NOTE: This defines the pseudo register type so need to
679 rebuild the architecture vector. */
681 static int mips64_transfers_32bit_regs_p
= 0;
684 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
685 struct cmd_list_element
*c
)
687 struct gdbarch_info info
;
688 gdbarch_info_init (&info
);
689 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
690 instead of relying on globals. Doing that would let generic code
691 handle the search for this specific architecture. */
692 if (!gdbarch_update_p (info
))
694 mips64_transfers_32bit_regs_p
= 0;
695 error (_("32-bit compatibility mode not supported"));
699 /* Convert to/from a register and the corresponding memory value. */
701 /* This predicate tests for the case of an 8 byte floating point
702 value that is being transferred to or from a pair of floating point
703 registers each of which are (or are considered to be) only 4 bytes
706 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
709 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
710 && register_size (gdbarch
, regnum
) == 4
711 && (regnum
% gdbarch_num_regs (gdbarch
))
712 >= mips_regnum (gdbarch
)->fp0
713 && (regnum
% gdbarch_num_regs (gdbarch
))
714 < mips_regnum (gdbarch
)->fp0
+ 32
715 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
718 /* This predicate tests for the case of a value of less than 8
719 bytes in width that is being transfered to or from an 8 byte
720 general purpose register. */
722 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
725 int num_regs
= gdbarch_num_regs (gdbarch
);
727 return (register_size (gdbarch
, regnum
) == 8
728 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
729 && TYPE_LENGTH (type
) < 8);
733 mips_convert_register_p (struct gdbarch
*gdbarch
,
734 int regnum
, struct type
*type
)
736 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
737 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
741 mips_register_to_value (struct frame_info
*frame
, int regnum
,
742 struct type
*type
, gdb_byte
*to
)
744 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
746 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
748 get_frame_register (frame
, regnum
+ 0, to
+ 4);
749 get_frame_register (frame
, regnum
+ 1, to
+ 0);
751 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
753 int len
= TYPE_LENGTH (type
);
754 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
755 get_frame_register_bytes (frame
, regnum
, 8 - len
, len
, to
);
757 get_frame_register_bytes (frame
, regnum
, 0, len
, to
);
761 internal_error (__FILE__
, __LINE__
,
762 _("mips_register_to_value: unrecognized case"));
767 mips_value_to_register (struct frame_info
*frame
, int regnum
,
768 struct type
*type
, const gdb_byte
*from
)
770 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
772 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
774 put_frame_register (frame
, regnum
+ 0, from
+ 4);
775 put_frame_register (frame
, regnum
+ 1, from
+ 0);
777 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
780 int len
= TYPE_LENGTH (type
);
782 /* Sign extend values, irrespective of type, that are stored to
783 a 64-bit general purpose register. (32-bit unsigned values
784 are stored as signed quantities within a 64-bit register.
785 When performing an operation, in compiled code, that combines
786 a 32-bit unsigned value with a signed 64-bit value, a type
787 conversion is first performed that zeroes out the high 32 bits.) */
788 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
791 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
793 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
794 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
795 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
799 if (from
[len
-1] & 0x80)
800 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
802 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
803 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
804 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
809 internal_error (__FILE__
, __LINE__
,
810 _("mips_value_to_register: unrecognized case"));
814 /* Return the GDB type object for the "standard" data type of data in
818 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
820 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
821 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
822 && (regnum
% gdbarch_num_regs (gdbarch
))
823 < mips_regnum (gdbarch
)->fp0
+ 32)
825 /* The floating-point registers raw, or cooked, always match
826 mips_isa_regsize(), and also map 1:1, byte for byte. */
827 if (mips_isa_regsize (gdbarch
) == 4)
828 return builtin_type (gdbarch
)->builtin_float
;
830 return builtin_type (gdbarch
)->builtin_double
;
832 else if (regnum
< gdbarch_num_regs (gdbarch
))
834 /* The raw or ISA registers. These are all sized according to
836 if (mips_isa_regsize (gdbarch
) == 4)
837 return builtin_type (gdbarch
)->builtin_int32
;
839 return builtin_type (gdbarch
)->builtin_int64
;
843 /* The cooked or ABI registers. These are sized according to
844 the ABI (with a few complications). */
845 if (regnum
>= (gdbarch_num_regs (gdbarch
)
846 + mips_regnum (gdbarch
)->fp_control_status
)
847 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
848 /* The pseudo/cooked view of the embedded registers is always
849 32-bit. The raw view is handled below. */
850 return builtin_type (gdbarch
)->builtin_int32
;
851 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
852 /* The target, while possibly using a 64-bit register buffer,
853 is only transfering 32-bits of each integer register.
854 Reflect this in the cooked/pseudo (ABI) register value. */
855 return builtin_type (gdbarch
)->builtin_int32
;
856 else if (mips_abi_regsize (gdbarch
) == 4)
857 /* The ABI is restricted to 32-bit registers (the ISA could be
859 return builtin_type (gdbarch
)->builtin_int32
;
862 return builtin_type (gdbarch
)->builtin_int64
;
866 /* Return the GDB type for the pseudo register REGNUM, which is the
867 ABI-level view. This function is only called if there is a target
868 description which includes registers, so we know precisely the
869 types of hardware registers. */
872 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
874 const int num_regs
= gdbarch_num_regs (gdbarch
);
875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
876 int rawnum
= regnum
% num_regs
;
877 struct type
*rawtype
;
879 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
881 /* Absent registers are still absent. */
882 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
883 if (TYPE_LENGTH (rawtype
) == 0)
886 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
887 /* Present the floating point registers however the hardware did;
888 do not try to convert between FPU layouts. */
891 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
893 /* The pseudo/cooked view of embedded registers is always
894 32-bit, even if the target transfers 64-bit values for them.
895 New targets relying on XML descriptions should only transfer
896 the necessary 32 bits, but older versions of GDB expected 64,
897 so allow the target to provide 64 bits without interfering
898 with the displayed type. */
899 return builtin_type (gdbarch
)->builtin_int32
;
902 /* Use pointer types for registers if we can. For n32 we can not,
903 since we do not have a 64-bit pointer type. */
904 if (mips_abi_regsize (gdbarch
)
905 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
907 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
908 return builtin_type (gdbarch
)->builtin_data_ptr
;
909 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
910 return builtin_type (gdbarch
)->builtin_func_ptr
;
913 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
914 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
915 return builtin_type (gdbarch
)->builtin_int32
;
917 /* For all other registers, pass through the hardware type. */
921 /* Should the upper word of 64-bit addresses be zeroed? */
922 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
925 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
927 switch (mask_address_var
)
929 case AUTO_BOOLEAN_TRUE
:
931 case AUTO_BOOLEAN_FALSE
:
934 case AUTO_BOOLEAN_AUTO
:
935 return tdep
->default_mask_address_p
;
937 internal_error (__FILE__
, __LINE__
,
938 _("mips_mask_address_p: bad switch"));
944 show_mask_address (struct ui_file
*file
, int from_tty
,
945 struct cmd_list_element
*c
, const char *value
)
947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
949 deprecated_show_value_hack (file
, from_tty
, c
, value
);
950 switch (mask_address_var
)
952 case AUTO_BOOLEAN_TRUE
:
953 printf_filtered ("The 32 bit mips address mask is enabled\n");
955 case AUTO_BOOLEAN_FALSE
:
956 printf_filtered ("The 32 bit mips address mask is disabled\n");
958 case AUTO_BOOLEAN_AUTO
:
960 ("The 32 bit address mask is set automatically. Currently %s\n",
961 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
964 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
969 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
972 mips_pc_is_mips16 (CORE_ADDR memaddr
)
974 struct minimal_symbol
*sym
;
976 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
977 if (is_mips16_addr (memaddr
))
980 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
981 the high bit of the info field. Use this to decide if the function is
982 MIPS16 or normal MIPS. */
983 sym
= lookup_minimal_symbol_by_pc (memaddr
);
985 return msymbol_is_special (sym
);
990 /* MIPS believes that the PC has a sign extended value. Perhaps the
991 all registers should be sign extended for simplicity? */
994 mips_read_pc (struct regcache
*regcache
)
997 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
998 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
999 if (is_mips16_addr (pc
))
1000 pc
= unmake_mips16_addr (pc
);
1005 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1009 pc
= frame_unwind_register_signed
1010 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1011 if (is_mips16_addr (pc
))
1012 pc
= unmake_mips16_addr (pc
);
1017 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1019 return frame_unwind_register_signed
1020 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1023 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1024 dummy frame. The frame ID's base needs to match the TOS value
1025 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1028 static struct frame_id
1029 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1031 return frame_id_build
1032 (get_frame_register_signed (this_frame
,
1033 gdbarch_num_regs (gdbarch
)
1035 get_frame_pc (this_frame
));
1039 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1041 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1042 if (mips_pc_is_mips16 (pc
))
1043 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1045 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1048 /* Fetch and return instruction from the specified location. If the PC
1049 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1052 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1054 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1055 gdb_byte buf
[MIPS_INSN32_SIZE
];
1059 if (mips_pc_is_mips16 (addr
))
1061 instlen
= MIPS_INSN16_SIZE
;
1062 addr
= unmake_mips16_addr (addr
);
1065 instlen
= MIPS_INSN32_SIZE
;
1066 status
= target_read_memory (addr
, buf
, instlen
);
1068 memory_error (status
, addr
);
1069 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1072 /* These are the fields of 32 bit mips instructions. */
1073 #define mips32_op(x) (x >> 26)
1074 #define itype_op(x) (x >> 26)
1075 #define itype_rs(x) ((x >> 21) & 0x1f)
1076 #define itype_rt(x) ((x >> 16) & 0x1f)
1077 #define itype_immediate(x) (x & 0xffff)
1079 #define jtype_op(x) (x >> 26)
1080 #define jtype_target(x) (x & 0x03ffffff)
1082 #define rtype_op(x) (x >> 26)
1083 #define rtype_rs(x) ((x >> 21) & 0x1f)
1084 #define rtype_rt(x) ((x >> 16) & 0x1f)
1085 #define rtype_rd(x) ((x >> 11) & 0x1f)
1086 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1087 #define rtype_funct(x) (x & 0x3f)
1090 mips32_relative_offset (ULONGEST inst
)
1092 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1095 /* Determine where to set a single step breakpoint while considering
1096 branch prediction. */
1098 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1100 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1103 inst
= mips_fetch_instruction (gdbarch
, pc
);
1104 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1107 if (itype_op (inst
) >> 2 == 5)
1108 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1110 op
= (itype_op (inst
) & 0x03);
1120 goto greater_branch
;
1125 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1126 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1128 int tf
= itype_rt (inst
) & 0x01;
1129 int cnum
= itype_rt (inst
) >> 2;
1131 get_frame_register_signed (frame
,
1132 mips_regnum (get_frame_arch (frame
))->
1134 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1136 if (((cond
>> cnum
) & 0x01) == tf
)
1137 pc
+= mips32_relative_offset (inst
) + 4;
1142 pc
+= 4; /* Not a branch, next instruction is easy. */
1145 { /* This gets way messy. */
1147 /* Further subdivide into SPECIAL, REGIMM and other. */
1148 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1150 case 0: /* SPECIAL */
1151 op
= rtype_funct (inst
);
1156 /* Set PC to that address. */
1157 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1159 case 12: /* SYSCALL */
1161 struct gdbarch_tdep
*tdep
;
1163 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1164 if (tdep
->syscall_next_pc
!= NULL
)
1165 pc
= tdep
->syscall_next_pc (frame
);
1174 break; /* end SPECIAL */
1175 case 1: /* REGIMM */
1177 op
= itype_rt (inst
); /* branch condition */
1182 case 16: /* BLTZAL */
1183 case 18: /* BLTZALL */
1185 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1186 pc
+= mips32_relative_offset (inst
) + 4;
1188 pc
+= 8; /* after the delay slot */
1192 case 17: /* BGEZAL */
1193 case 19: /* BGEZALL */
1194 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1195 pc
+= mips32_relative_offset (inst
) + 4;
1197 pc
+= 8; /* after the delay slot */
1199 /* All of the other instructions in the REGIMM category */
1204 break; /* end REGIMM */
1209 reg
= jtype_target (inst
) << 2;
1210 /* Upper four bits get never changed... */
1211 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1214 /* FIXME case JALX : */
1217 reg
= jtype_target (inst
) << 2;
1218 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1219 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1221 break; /* The new PC will be alternate mode */
1222 case 4: /* BEQ, BEQL */
1224 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1225 get_frame_register_signed (frame
, itype_rt (inst
)))
1226 pc
+= mips32_relative_offset (inst
) + 4;
1230 case 5: /* BNE, BNEL */
1232 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1233 get_frame_register_signed (frame
, itype_rt (inst
)))
1234 pc
+= mips32_relative_offset (inst
) + 4;
1238 case 6: /* BLEZ, BLEZL */
1239 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1240 pc
+= mips32_relative_offset (inst
) + 4;
1246 greater_branch
: /* BGTZ, BGTZL */
1247 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1248 pc
+= mips32_relative_offset (inst
) + 4;
1255 } /* mips32_next_pc */
1257 /* Decoding the next place to set a breakpoint is irregular for the
1258 mips 16 variant, but fortunately, there fewer instructions. We have
1259 to cope ith extensions for 16 bit instructions and a pair of actual
1260 32 bit instructions. We dont want to set a single step instruction
1261 on the extend instruction either. */
1263 /* Lots of mips16 instruction formats */
1264 /* Predicting jumps requires itype,ritype,i8type
1265 and their extensions extItype,extritype,extI8type. */
1266 enum mips16_inst_fmts
1268 itype
, /* 0 immediate 5,10 */
1269 ritype
, /* 1 5,3,8 */
1270 rrtype
, /* 2 5,3,3,5 */
1271 rritype
, /* 3 5,3,3,5 */
1272 rrrtype
, /* 4 5,3,3,3,2 */
1273 rriatype
, /* 5 5,3,3,1,4 */
1274 shifttype
, /* 6 5,3,3,3,2 */
1275 i8type
, /* 7 5,3,8 */
1276 i8movtype
, /* 8 5,3,3,5 */
1277 i8mov32rtype
, /* 9 5,3,5,3 */
1278 i64type
, /* 10 5,3,8 */
1279 ri64type
, /* 11 5,3,3,5 */
1280 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1281 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1282 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1283 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1284 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1285 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1286 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1287 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1288 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1289 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1291 /* I am heaping all the fields of the formats into one structure and
1292 then, only the fields which are involved in instruction extension. */
1296 unsigned int regx
; /* Function in i8 type. */
1301 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1302 for the bits which make up the immediate extension. */
1305 extended_offset (unsigned int extension
)
1308 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1310 value
|= (extension
>> 16) & 0x1f; /* extract 10:5 */
1312 value
|= extension
& 0x01f; /* extract 4:0 */
1316 /* Only call this function if you know that this is an extendable
1317 instruction. It won't malfunction, but why make excess remote memory
1318 references? If the immediate operands get sign extended or something,
1319 do it after the extension is performed. */
1320 /* FIXME: Every one of these cases needs to worry about sign extension
1321 when the offset is to be used in relative addressing. */
1324 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1326 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1328 pc
&= 0xfffffffe; /* Clear the low order bit. */
1329 target_read_memory (pc
, buf
, 2);
1330 return extract_unsigned_integer (buf
, 2, byte_order
);
1334 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1335 unsigned int extension
,
1337 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1342 switch (insn_format
)
1349 value
= extended_offset (extension
);
1350 value
= value
<< 11; /* rom for the original value */
1351 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1355 value
= inst
& 0x7ff;
1356 /* FIXME : Consider sign extension. */
1365 { /* A register identifier and an offset. */
1366 /* Most of the fields are the same as I type but the
1367 immediate value is of a different length. */
1371 value
= extended_offset (extension
);
1372 value
= value
<< 8; /* from the original instruction */
1373 value
|= inst
& 0xff; /* eleven bits from instruction */
1374 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1375 if (value
& 0x4000) /* Test the sign bit, bit 26. */
1377 value
&= ~0x3fff; /* Remove the sign bit. */
1383 value
= inst
& 0xff; /* 8 bits */
1384 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1385 /* FIXME: Do sign extension, this format needs it. */
1386 if (value
& 0x80) /* THIS CONFUSES ME. */
1388 value
&= 0xef; /* Remove the sign bit. */
1398 unsigned long value
;
1399 unsigned int nexthalf
;
1400 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1401 value
= value
<< 16;
1402 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1411 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1413 upk
->offset
= offset
;
1420 add_offset_16 (CORE_ADDR pc
, int offset
)
1422 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1426 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1427 unsigned int extension
, unsigned int insn
)
1429 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1430 int op
= (insn
>> 11);
1433 case 2: /* Branch */
1436 struct upk_mips16 upk
;
1437 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1438 offset
= upk
.offset
;
1444 pc
+= (offset
<< 1) + 2;
1447 case 3: /* JAL , JALX - Watch out, these are 32 bit
1450 struct upk_mips16 upk
;
1451 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1452 pc
= add_offset_16 (pc
, upk
.offset
);
1453 if ((insn
>> 10) & 0x01) /* Exchange mode */
1454 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1461 struct upk_mips16 upk
;
1463 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1464 reg
= get_frame_register_signed (frame
, upk
.regx
);
1466 pc
+= (upk
.offset
<< 1) + 2;
1473 struct upk_mips16 upk
;
1475 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1476 reg
= get_frame_register_signed (frame
, upk
.regx
);
1478 pc
+= (upk
.offset
<< 1) + 2;
1483 case 12: /* I8 Formats btez btnez */
1485 struct upk_mips16 upk
;
1487 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1488 /* upk.regx contains the opcode */
1489 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1490 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1491 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1492 /* pc = add_offset_16(pc,upk.offset) ; */
1493 pc
+= (upk
.offset
<< 1) + 2;
1498 case 29: /* RR Formats JR, JALR, JALR-RA */
1500 struct upk_mips16 upk
;
1501 /* upk.fmt = rrtype; */
1506 upk
.regx
= (insn
>> 8) & 0x07;
1507 upk
.regy
= (insn
>> 5) & 0x07;
1515 break; /* Function return instruction. */
1521 break; /* BOGUS Guess */
1523 pc
= get_frame_register_signed (frame
, reg
);
1530 /* This is an instruction extension. Fetch the real instruction
1531 (which follows the extension) and decode things based on
1535 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1536 fetch_mips_16 (gdbarch
, pc
));
1549 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1551 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1552 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1553 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1556 /* The mips_next_pc function supports single_step when the remote
1557 target monitor or stub is not developed enough to do a single_step.
1558 It works by decoding the current instruction and predicting where a
1559 branch will go. This isnt hard because all the data is available.
1560 The MIPS32 and MIPS16 variants are quite different. */
1562 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1564 if (is_mips16_addr (pc
))
1565 return mips16_next_pc (frame
, pc
);
1567 return mips32_next_pc (frame
, pc
);
1570 struct mips_frame_cache
1573 struct trad_frame_saved_reg
*saved_regs
;
1576 /* Set a register's saved stack address in temp_saved_regs. If an
1577 address has already been set for this register, do nothing; this
1578 way we will only recognize the first save of a given register in a
1581 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1582 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1583 Strictly speaking, only the second range is used as it is only second
1584 range (the ABI instead of ISA registers) that comes into play when finding
1585 saved registers in a frame. */
1588 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1589 int regnum
, CORE_ADDR offset
)
1591 if (this_cache
!= NULL
1592 && this_cache
->saved_regs
[regnum
].addr
== -1)
1594 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1596 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1602 /* Fetch the immediate value from a MIPS16 instruction.
1603 If the previous instruction was an EXTEND, use it to extend
1604 the upper bits of the immediate value. This is a helper function
1605 for mips16_scan_prologue. */
1608 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1609 unsigned short inst
, /* current instruction */
1610 int nbits
, /* number of bits in imm field */
1611 int scale
, /* scale factor to be applied to imm */
1612 int is_signed
) /* is the imm field signed? */
1616 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1618 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1619 if (offset
& 0x8000) /* check for negative extend */
1620 offset
= 0 - (0x10000 - (offset
& 0xffff));
1621 return offset
| (inst
& 0x1f);
1625 int max_imm
= 1 << nbits
;
1626 int mask
= max_imm
- 1;
1627 int sign_bit
= max_imm
>> 1;
1629 offset
= inst
& mask
;
1630 if (is_signed
&& (offset
& sign_bit
))
1631 offset
= 0 - (max_imm
- offset
);
1632 return offset
* scale
;
1637 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1638 the associated FRAME_CACHE if not null.
1639 Return the address of the first instruction past the prologue. */
1642 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1643 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1644 struct frame_info
*this_frame
,
1645 struct mips_frame_cache
*this_cache
)
1648 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1650 long frame_offset
= 0; /* Size of stack frame. */
1651 long frame_adjust
= 0; /* Offset of FP from SP. */
1652 int frame_reg
= MIPS_SP_REGNUM
;
1653 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1654 unsigned inst
= 0; /* current instruction */
1655 unsigned entry_inst
= 0; /* the entry instruction */
1656 unsigned save_inst
= 0; /* the save instruction */
1659 int extend_bytes
= 0;
1660 int prev_extend_bytes
;
1661 CORE_ADDR end_prologue_addr
= 0;
1663 /* Can be called when there's no process, and hence when there's no
1665 if (this_frame
!= NULL
)
1666 sp
= get_frame_register_signed (this_frame
,
1667 gdbarch_num_regs (gdbarch
)
1672 if (limit_pc
> start_pc
+ 200)
1673 limit_pc
= start_pc
+ 200;
1675 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1677 /* Save the previous instruction. If it's an EXTEND, we'll extract
1678 the immediate offset extension from it in mips16_get_imm. */
1681 /* Fetch and decode the instruction. */
1682 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1684 /* Normally we ignore extend instructions. However, if it is
1685 not followed by a valid prologue instruction, then this
1686 instruction is not part of the prologue either. We must
1687 remember in this case to adjust the end_prologue_addr back
1689 if ((inst
& 0xf800) == 0xf000) /* extend */
1691 extend_bytes
= MIPS_INSN16_SIZE
;
1695 prev_extend_bytes
= extend_bytes
;
1698 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1699 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1701 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1702 if (offset
< 0) /* Negative stack adjustment? */
1703 frame_offset
-= offset
;
1705 /* Exit loop if a positive stack adjustment is found, which
1706 usually means that the stack cleanup code in the function
1707 epilogue is reached. */
1710 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1712 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1713 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1714 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1716 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1718 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1719 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1720 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1722 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1724 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1725 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1727 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1729 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1730 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1732 else if (inst
== 0x673d) /* move $s1, $sp */
1737 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1739 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1740 frame_addr
= sp
+ offset
;
1742 frame_adjust
= offset
;
1744 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1746 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1747 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1748 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1750 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1752 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1753 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1754 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1756 else if ((inst
& 0xf81f) == 0xe809
1757 && (inst
& 0x700) != 0x700) /* entry */
1758 entry_inst
= inst
; /* Save for later processing. */
1759 else if ((inst
& 0xff80) == 0x6480) /* save */
1761 save_inst
= inst
; /* Save for later processing. */
1762 if (prev_extend_bytes
) /* extend */
1763 save_inst
|= prev_inst
<< 16;
1765 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1766 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1767 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1769 /* This instruction is part of the prologue, but we don't
1770 need to do anything special to handle it. */
1774 /* This instruction is not an instruction typically found
1775 in a prologue, so we must have reached the end of the
1777 if (end_prologue_addr
== 0)
1778 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1782 /* The entry instruction is typically the first instruction in a function,
1783 and it stores registers at offsets relative to the value of the old SP
1784 (before the prologue). But the value of the sp parameter to this
1785 function is the new SP (after the prologue has been executed). So we
1786 can't calculate those offsets until we've seen the entire prologue,
1787 and can calculate what the old SP must have been. */
1788 if (entry_inst
!= 0)
1790 int areg_count
= (entry_inst
>> 8) & 7;
1791 int sreg_count
= (entry_inst
>> 6) & 3;
1793 /* The entry instruction always subtracts 32 from the SP. */
1796 /* Now we can calculate what the SP must have been at the
1797 start of the function prologue. */
1800 /* Check if a0-a3 were saved in the caller's argument save area. */
1801 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1803 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1804 offset
+= mips_abi_regsize (gdbarch
);
1807 /* Check if the ra register was pushed on the stack. */
1809 if (entry_inst
& 0x20)
1811 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1812 offset
-= mips_abi_regsize (gdbarch
);
1815 /* Check if the s0 and s1 registers were pushed on the stack. */
1816 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1818 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1819 offset
-= mips_abi_regsize (gdbarch
);
1823 /* The SAVE instruction is similar to ENTRY, except that defined by the
1824 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1825 size of the frame is specified as an immediate field of instruction
1826 and an extended variation exists which lets additional registers and
1827 frame space to be specified. The instruction always treats registers
1828 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1829 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1831 static int args_table
[16] = {
1832 0, 0, 0, 0, 1, 1, 1, 1,
1833 2, 2, 2, 0, 3, 3, 4, -1,
1835 static int astatic_table
[16] = {
1836 0, 1, 2, 3, 0, 1, 2, 3,
1837 0, 1, 2, 4, 0, 1, 0, -1,
1839 int aregs
= (save_inst
>> 16) & 0xf;
1840 int xsregs
= (save_inst
>> 24) & 0x7;
1841 int args
= args_table
[aregs
];
1842 int astatic
= astatic_table
[aregs
];
1847 warning (_("Invalid number of argument registers encoded in SAVE."));
1852 warning (_("Invalid number of static registers encoded in SAVE."));
1856 /* For standard SAVE the frame size of 0 means 128. */
1857 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1858 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1861 frame_offset
+= frame_size
;
1863 /* Now we can calculate what the SP must have been at the
1864 start of the function prologue. */
1867 /* Check if A0-A3 were saved in the caller's argument save area. */
1868 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1870 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1871 offset
+= mips_abi_regsize (gdbarch
);
1876 /* Check if the RA register was pushed on the stack. */
1877 if (save_inst
& 0x40)
1879 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1880 offset
-= mips_abi_regsize (gdbarch
);
1883 /* Check if the S8 register was pushed on the stack. */
1886 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1887 offset
-= mips_abi_regsize (gdbarch
);
1890 /* Check if S2-S7 were pushed on the stack. */
1891 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1893 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1894 offset
-= mips_abi_regsize (gdbarch
);
1897 /* Check if the S1 register was pushed on the stack. */
1898 if (save_inst
& 0x10)
1900 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1901 offset
-= mips_abi_regsize (gdbarch
);
1903 /* Check if the S0 register was pushed on the stack. */
1904 if (save_inst
& 0x20)
1906 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1907 offset
-= mips_abi_regsize (gdbarch
);
1910 /* Check if A0-A3 were pushed on the stack. */
1911 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1913 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1914 offset
-= mips_abi_regsize (gdbarch
);
1918 if (this_cache
!= NULL
)
1921 (get_frame_register_signed (this_frame
,
1922 gdbarch_num_regs (gdbarch
) + frame_reg
)
1923 + frame_offset
- frame_adjust
);
1924 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1925 be able to get rid of the assignment below, evetually. But it's
1926 still needed for now. */
1927 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1928 + mips_regnum (gdbarch
)->pc
]
1929 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1932 /* If we didn't reach the end of the prologue when scanning the function
1933 instructions, then set end_prologue_addr to the address of the
1934 instruction immediately after the last one we scanned. */
1935 if (end_prologue_addr
== 0)
1936 end_prologue_addr
= cur_pc
;
1938 return end_prologue_addr
;
1941 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1942 Procedures that use the 32-bit instruction set are handled by the
1943 mips_insn32 unwinder. */
1945 static struct mips_frame_cache
*
1946 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1948 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1949 struct mips_frame_cache
*cache
;
1951 if ((*this_cache
) != NULL
)
1952 return (*this_cache
);
1953 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1954 (*this_cache
) = cache
;
1955 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1957 /* Analyze the function prologue. */
1959 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1960 CORE_ADDR start_addr
;
1962 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1963 if (start_addr
== 0)
1964 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1965 /* We can't analyze the prologue if we couldn't find the begining
1967 if (start_addr
== 0)
1970 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1973 /* gdbarch_sp_regnum contains the value and not the address. */
1974 trad_frame_set_value (cache
->saved_regs
,
1975 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1978 return (*this_cache
);
1982 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1983 struct frame_id
*this_id
)
1985 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1987 /* This marks the outermost frame. */
1988 if (info
->base
== 0)
1990 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1993 static struct value
*
1994 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1995 void **this_cache
, int regnum
)
1997 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1999 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2003 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2004 struct frame_info
*this_frame
, void **this_cache
)
2006 CORE_ADDR pc
= get_frame_pc (this_frame
);
2007 if (mips_pc_is_mips16 (pc
))
2012 static const struct frame_unwind mips_insn16_frame_unwind
=
2015 mips_insn16_frame_this_id
,
2016 mips_insn16_frame_prev_register
,
2018 mips_insn16_frame_sniffer
2022 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2025 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2030 static const struct frame_base mips_insn16_frame_base
=
2032 &mips_insn16_frame_unwind
,
2033 mips_insn16_frame_base_address
,
2034 mips_insn16_frame_base_address
,
2035 mips_insn16_frame_base_address
2038 static const struct frame_base
*
2039 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2041 CORE_ADDR pc
= get_frame_pc (this_frame
);
2042 if (mips_pc_is_mips16 (pc
))
2043 return &mips_insn16_frame_base
;
2048 /* Mark all the registers as unset in the saved_regs array
2049 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2052 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2054 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2058 const int num_regs
= gdbarch_num_regs (gdbarch
);
2061 for (i
= 0; i
< num_regs
; i
++)
2063 this_cache
->saved_regs
[i
].addr
= -1;
2068 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2069 the associated FRAME_CACHE if not null.
2070 Return the address of the first instruction past the prologue. */
2073 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2074 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2075 struct frame_info
*this_frame
,
2076 struct mips_frame_cache
*this_cache
)
2079 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2083 int frame_reg
= MIPS_SP_REGNUM
;
2085 CORE_ADDR end_prologue_addr
= 0;
2086 int seen_sp_adjust
= 0;
2087 int load_immediate_bytes
= 0;
2088 int in_delay_slot
= 0;
2089 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2091 /* Can be called when there's no process, and hence when there's no
2093 if (this_frame
!= NULL
)
2094 sp
= get_frame_register_signed (this_frame
,
2095 gdbarch_num_regs (gdbarch
)
2100 if (limit_pc
> start_pc
+ 200)
2101 limit_pc
= start_pc
+ 200;
2106 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2108 unsigned long inst
, high_word
, low_word
;
2111 /* Fetch the instruction. */
2112 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2114 /* Save some code by pre-extracting some useful fields. */
2115 high_word
= (inst
>> 16) & 0xffff;
2116 low_word
= inst
& 0xffff;
2117 reg
= high_word
& 0x1f;
2119 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2120 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2121 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2123 if (low_word
& 0x8000) /* Negative stack adjustment? */
2124 frame_offset
+= 0x10000 - low_word
;
2126 /* Exit loop if a positive stack adjustment is found, which
2127 usually means that the stack cleanup code in the function
2128 epilogue is reached. */
2132 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2133 && !regsize_is_64_bits
)
2135 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2137 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2138 && regsize_is_64_bits
)
2140 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2141 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2143 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2145 /* Old gcc frame, r30 is virtual frame pointer. */
2146 if ((long) low_word
!= frame_offset
)
2147 frame_addr
= sp
+ low_word
;
2148 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2150 unsigned alloca_adjust
;
2153 frame_addr
= get_frame_register_signed
2154 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2156 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2157 if (alloca_adjust
> 0)
2159 /* FP > SP + frame_size. This may be because of
2160 an alloca or somethings similar. Fix sp to
2161 "pre-alloca" value, and try again. */
2162 sp
+= alloca_adjust
;
2163 /* Need to reset the status of all registers. Otherwise,
2164 we will hit a guard that prevents the new address
2165 for each register to be recomputed during the second
2167 reset_saved_regs (gdbarch
, this_cache
);
2172 /* move $30,$sp. With different versions of gas this will be either
2173 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2174 Accept any one of these. */
2175 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2177 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2178 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2180 unsigned alloca_adjust
;
2183 frame_addr
= get_frame_register_signed
2184 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2186 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2187 if (alloca_adjust
> 0)
2189 /* FP > SP + frame_size. This may be because of
2190 an alloca or somethings similar. Fix sp to
2191 "pre-alloca" value, and try again. */
2193 /* Need to reset the status of all registers. Otherwise,
2194 we will hit a guard that prevents the new address
2195 for each register to be recomputed during the second
2197 reset_saved_regs (gdbarch
, this_cache
);
2202 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2203 && !regsize_is_64_bits
)
2205 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2207 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2208 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2209 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2210 || high_word
== 0x3c1c /* lui $gp,n */
2211 || high_word
== 0x279c /* addiu $gp,$gp,n */
2212 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2213 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2216 /* These instructions are part of the prologue, but we don't
2217 need to do anything special to handle them. */
2219 /* The instructions below load $at or $t0 with an immediate
2220 value in preparation for a stack adjustment via
2221 subu $sp,$sp,[$at,$t0]. These instructions could also
2222 initialize a local variable, so we accept them only before
2223 a stack adjustment instruction was seen. */
2224 else if (!seen_sp_adjust
2225 && (high_word
== 0x3c01 /* lui $at,n */
2226 || high_word
== 0x3c08 /* lui $t0,n */
2227 || high_word
== 0x3421 /* ori $at,$at,n */
2228 || high_word
== 0x3508 /* ori $t0,$t0,n */
2229 || high_word
== 0x3401 /* ori $at,$zero,n */
2230 || high_word
== 0x3408 /* ori $t0,$zero,n */
2233 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2237 /* This instruction is not an instruction typically found
2238 in a prologue, so we must have reached the end of the
2240 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2241 loop now? Why would we need to continue scanning the function
2243 if (end_prologue_addr
== 0)
2244 end_prologue_addr
= cur_pc
;
2246 /* Check for branches and jumps. For now, only jump to
2247 register are caught (i.e. returns). */
2248 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2252 /* If the previous instruction was a jump, we must have reached
2253 the end of the prologue by now. Stop scanning so that we do
2254 not go past the function return. */
2259 if (this_cache
!= NULL
)
2262 (get_frame_register_signed (this_frame
,
2263 gdbarch_num_regs (gdbarch
) + frame_reg
)
2265 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2266 this assignment below, eventually. But it's still needed
2268 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2269 + mips_regnum (gdbarch
)->pc
]
2270 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2274 /* If we didn't reach the end of the prologue when scanning the function
2275 instructions, then set end_prologue_addr to the address of the
2276 instruction immediately after the last one we scanned. */
2277 /* brobecker/2004-10-10: I don't think this would ever happen, but
2278 we may as well be careful and do our best if we have a null
2279 end_prologue_addr. */
2280 if (end_prologue_addr
== 0)
2281 end_prologue_addr
= cur_pc
;
2283 /* In a frameless function, we might have incorrectly
2284 skipped some load immediate instructions. Undo the skipping
2285 if the load immediate was not followed by a stack adjustment. */
2286 if (load_immediate_bytes
&& !seen_sp_adjust
)
2287 end_prologue_addr
-= load_immediate_bytes
;
2289 return end_prologue_addr
;
2292 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2293 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2294 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2297 static struct mips_frame_cache
*
2298 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2300 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2301 struct mips_frame_cache
*cache
;
2303 if ((*this_cache
) != NULL
)
2304 return (*this_cache
);
2306 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2307 (*this_cache
) = cache
;
2308 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2310 /* Analyze the function prologue. */
2312 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2313 CORE_ADDR start_addr
;
2315 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2316 if (start_addr
== 0)
2317 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2318 /* We can't analyze the prologue if we couldn't find the begining
2320 if (start_addr
== 0)
2323 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2326 /* gdbarch_sp_regnum contains the value and not the address. */
2327 trad_frame_set_value (cache
->saved_regs
,
2328 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2331 return (*this_cache
);
2335 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2336 struct frame_id
*this_id
)
2338 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2340 /* This marks the outermost frame. */
2341 if (info
->base
== 0)
2343 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2346 static struct value
*
2347 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2348 void **this_cache
, int regnum
)
2350 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2352 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2356 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2357 struct frame_info
*this_frame
, void **this_cache
)
2359 CORE_ADDR pc
= get_frame_pc (this_frame
);
2360 if (! mips_pc_is_mips16 (pc
))
2365 static const struct frame_unwind mips_insn32_frame_unwind
=
2368 mips_insn32_frame_this_id
,
2369 mips_insn32_frame_prev_register
,
2371 mips_insn32_frame_sniffer
2375 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2378 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2383 static const struct frame_base mips_insn32_frame_base
=
2385 &mips_insn32_frame_unwind
,
2386 mips_insn32_frame_base_address
,
2387 mips_insn32_frame_base_address
,
2388 mips_insn32_frame_base_address
2391 static const struct frame_base
*
2392 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2394 CORE_ADDR pc
= get_frame_pc (this_frame
);
2395 if (! mips_pc_is_mips16 (pc
))
2396 return &mips_insn32_frame_base
;
2401 static struct trad_frame_cache
*
2402 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2405 CORE_ADDR start_addr
;
2406 CORE_ADDR stack_addr
;
2407 struct trad_frame_cache
*this_trad_cache
;
2408 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2409 int num_regs
= gdbarch_num_regs (gdbarch
);
2411 if ((*this_cache
) != NULL
)
2412 return (*this_cache
);
2413 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2414 (*this_cache
) = this_trad_cache
;
2416 /* The return address is in the link register. */
2417 trad_frame_set_reg_realreg (this_trad_cache
,
2418 gdbarch_pc_regnum (gdbarch
),
2419 num_regs
+ MIPS_RA_REGNUM
);
2421 /* Frame ID, since it's a frameless / stackless function, no stack
2422 space is allocated and SP on entry is the current SP. */
2423 pc
= get_frame_pc (this_frame
);
2424 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2425 stack_addr
= get_frame_register_signed (this_frame
,
2426 num_regs
+ MIPS_SP_REGNUM
);
2427 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2429 /* Assume that the frame's base is the same as the
2431 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2433 return this_trad_cache
;
2437 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2438 struct frame_id
*this_id
)
2440 struct trad_frame_cache
*this_trad_cache
2441 = mips_stub_frame_cache (this_frame
, this_cache
);
2442 trad_frame_get_id (this_trad_cache
, this_id
);
2445 static struct value
*
2446 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2447 void **this_cache
, int regnum
)
2449 struct trad_frame_cache
*this_trad_cache
2450 = mips_stub_frame_cache (this_frame
, this_cache
);
2451 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2455 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2456 struct frame_info
*this_frame
, void **this_cache
)
2459 struct obj_section
*s
;
2460 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2461 struct minimal_symbol
*msym
;
2463 /* Use the stub unwinder for unreadable code. */
2464 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2467 if (in_plt_section (pc
, NULL
))
2470 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2471 s
= find_pc_section (pc
);
2474 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2475 ".MIPS.stubs") == 0)
2478 /* Calling a PIC function from a non-PIC function passes through a
2479 stub. The stub for foo is named ".pic.foo". */
2480 msym
= lookup_minimal_symbol_by_pc (pc
);
2482 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2483 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2489 static const struct frame_unwind mips_stub_frame_unwind
=
2492 mips_stub_frame_this_id
,
2493 mips_stub_frame_prev_register
,
2495 mips_stub_frame_sniffer
2499 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2502 struct trad_frame_cache
*this_trad_cache
2503 = mips_stub_frame_cache (this_frame
, this_cache
);
2504 return trad_frame_get_this_base (this_trad_cache
);
2507 static const struct frame_base mips_stub_frame_base
=
2509 &mips_stub_frame_unwind
,
2510 mips_stub_frame_base_address
,
2511 mips_stub_frame_base_address
,
2512 mips_stub_frame_base_address
2515 static const struct frame_base
*
2516 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2518 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2519 return &mips_stub_frame_base
;
2524 /* mips_addr_bits_remove - remove useless address bits */
2527 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2529 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2531 if (is_mips16_addr (addr
))
2532 addr
= unmake_mips16_addr (addr
);
2534 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2535 /* This hack is a work-around for existing boards using PMON, the
2536 simulator, and any other 64-bit targets that doesn't have true
2537 64-bit addressing. On these targets, the upper 32 bits of
2538 addresses are ignored by the hardware. Thus, the PC or SP are
2539 likely to have been sign extended to all 1s by instruction
2540 sequences that load 32-bit addresses. For example, a typical
2541 piece of code that loads an address is this:
2543 lui $r2, <upper 16 bits>
2544 ori $r2, <lower 16 bits>
2546 But the lui sign-extends the value such that the upper 32 bits
2547 may be all 1s. The workaround is simply to mask off these
2548 bits. In the future, gcc may be changed to support true 64-bit
2549 addressing, and this masking will have to be disabled. */
2550 return addr
&= 0xffffffffUL
;
2555 /* Instructions used during single-stepping of atomic sequences. */
2556 #define LL_OPCODE 0x30
2557 #define LLD_OPCODE 0x34
2558 #define SC_OPCODE 0x38
2559 #define SCD_OPCODE 0x3c
2561 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2562 instruction and ending with a SC/SCD instruction. If such a sequence
2563 is found, attempt to step through it. A breakpoint is placed at the end of
2567 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2568 struct address_space
*aspace
, CORE_ADDR pc
)
2570 CORE_ADDR breaks
[2] = {-1, -1};
2572 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2576 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2577 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2582 insn
= mips_fetch_instruction (gdbarch
, loc
);
2583 /* Assume all atomic sequences start with a ll/lld instruction. */
2584 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2587 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2589 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2592 loc
+= MIPS_INSN32_SIZE
;
2593 insn
= mips_fetch_instruction (gdbarch
, loc
);
2595 /* Assume that there is at most one branch in the atomic
2596 sequence. If a branch is found, put a breakpoint in its
2597 destination address. */
2598 switch (itype_op (insn
))
2600 case 0: /* SPECIAL */
2601 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2602 return 0; /* fallback to the standard single-step code. */
2604 case 1: /* REGIMM */
2605 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2609 return 0; /* fallback to the standard single-step code. */
2616 case 22: /* BLEZL */
2617 case 23: /* BGTTL */
2623 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2628 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2629 if (last_breakpoint
>= 1)
2630 return 0; /* More than one branch found, fallback to the
2631 standard single-step code. */
2632 breaks
[1] = branch_bp
;
2636 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2640 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2641 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2644 loc
+= MIPS_INSN32_SIZE
;
2646 /* Insert a breakpoint right after the end of the atomic sequence. */
2649 /* Check for duplicated breakpoints. Check also for a breakpoint
2650 placed (branch instruction's destination) in the atomic sequence. */
2651 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2652 last_breakpoint
= 0;
2654 /* Effectively inserts the breakpoints. */
2655 for (index
= 0; index
<= last_breakpoint
; index
++)
2656 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2661 /* mips_software_single_step() is called just before we want to resume
2662 the inferior, if we want to single-step it but there is no hardware
2663 or kernel single-step support (MIPS on GNU/Linux for example). We find
2664 the target of the coming instruction and breakpoint it. */
2667 mips_software_single_step (struct frame_info
*frame
)
2669 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2670 struct address_space
*aspace
= get_frame_address_space (frame
);
2671 CORE_ADDR pc
, next_pc
;
2673 pc
= get_frame_pc (frame
);
2674 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2677 next_pc
= mips_next_pc (frame
, pc
);
2679 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2683 /* Test whether the PC points to the return instruction at the
2684 end of a function. */
2687 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2689 if (mips_pc_is_mips16 (pc
))
2690 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2691 generates a "jr $ra"; other times it generates code to load
2692 the return address from the stack to an accessible register (such
2693 as $a3), then a "jr" using that register. This second case
2694 is almost impossible to distinguish from an indirect jump
2695 used for switch statements, so we don't even try. */
2696 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2698 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2702 /* This fencepost looks highly suspicious to me. Removing it also
2703 seems suspicious as it could affect remote debugging across serial
2707 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2713 struct inferior
*inf
;
2715 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2717 fence
= start_pc
- heuristic_fence_post
;
2721 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2722 fence
= VM_MIN_ADDRESS
;
2724 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2726 inf
= current_inferior ();
2728 /* Search back for previous return. */
2729 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2730 if (start_pc
< fence
)
2732 /* It's not clear to me why we reach this point when
2733 stop_soon, but with this test, at least we
2734 don't print out warnings for every child forked (eg, on
2735 decstation). 22apr93 rich@cygnus.com. */
2736 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2738 static int blurb_printed
= 0;
2740 warning (_("GDB can't find the start of the function at %s."),
2741 paddress (gdbarch
, pc
));
2745 /* This actually happens frequently in embedded
2746 development, when you first connect to a board
2747 and your stack pointer and pc are nowhere in
2748 particular. This message needs to give people
2749 in that situation enough information to
2750 determine that it's no big deal. */
2751 printf_filtered ("\n\
2752 GDB is unable to find the start of the function at %s\n\
2753 and thus can't determine the size of that function's stack frame.\n\
2754 This means that GDB may be unable to access that stack frame, or\n\
2755 the frames below it.\n\
2756 This problem is most likely caused by an invalid program counter or\n\
2758 However, if you think GDB should simply search farther back\n\
2759 from %s for code which looks like the beginning of a\n\
2760 function, you can increase the range of the search using the `set\n\
2761 heuristic-fence-post' command.\n",
2762 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2769 else if (mips_pc_is_mips16 (start_pc
))
2771 unsigned short inst
;
2773 /* On MIPS16, any one of the following is likely to be the
2774 start of a function:
2780 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2781 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2782 if ((inst
& 0xff80) == 0x6480) /* save */
2784 if (start_pc
- instlen
>= fence
)
2786 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2787 if ((inst
& 0xf800) == 0xf000) /* extend */
2788 start_pc
-= instlen
;
2792 else if (((inst
& 0xf81f) == 0xe809
2793 && (inst
& 0x700) != 0x700) /* entry */
2794 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2795 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2796 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2798 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2799 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2804 else if (mips_about_to_return (gdbarch
, start_pc
))
2806 /* Skip return and its delay slot. */
2807 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2814 struct mips_objfile_private
2820 /* According to the current ABI, should the type be passed in a
2821 floating-point register (assuming that there is space)? When there
2822 is no FPU, FP are not even considered as possible candidates for
2823 FP registers and, consequently this returns false - forces FP
2824 arguments into integer registers. */
2827 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2828 struct type
*arg_type
)
2830 return ((typecode
== TYPE_CODE_FLT
2831 || (MIPS_EABI (gdbarch
)
2832 && (typecode
== TYPE_CODE_STRUCT
2833 || typecode
== TYPE_CODE_UNION
)
2834 && TYPE_NFIELDS (arg_type
) == 1
2835 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2837 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2840 /* On o32, argument passing in GPRs depends on the alignment of the type being
2841 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2844 mips_type_needs_double_align (struct type
*type
)
2846 enum type_code typecode
= TYPE_CODE (type
);
2848 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2850 else if (typecode
== TYPE_CODE_STRUCT
)
2852 if (TYPE_NFIELDS (type
) < 1)
2854 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2856 else if (typecode
== TYPE_CODE_UNION
)
2860 n
= TYPE_NFIELDS (type
);
2861 for (i
= 0; i
< n
; i
++)
2862 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2869 /* Adjust the address downward (direction of stack growth) so that it
2870 is correctly aligned for a new stack frame. */
2872 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2874 return align_down (addr
, 16);
2878 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2879 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2880 int nargs
, struct value
**args
, CORE_ADDR sp
,
2881 int struct_return
, CORE_ADDR struct_addr
)
2887 int stack_offset
= 0;
2888 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2889 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2890 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2891 int regsize
= mips_abi_regsize (gdbarch
);
2893 /* For shared libraries, "t9" needs to point at the function
2895 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2897 /* Set the return address register to point to the entry point of
2898 the program, where a breakpoint lies in wait. */
2899 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2901 /* First ensure that the stack and structure return address (if any)
2902 are properly aligned. The stack has to be at least 64-bit
2903 aligned even on 32-bit machines, because doubles must be 64-bit
2904 aligned. For n32 and n64, stack frames need to be 128-bit
2905 aligned, so we round to this widest known alignment. */
2907 sp
= align_down (sp
, 16);
2908 struct_addr
= align_down (struct_addr
, 16);
2910 /* Now make space on the stack for the args. We allocate more
2911 than necessary for EABI, because the first few arguments are
2912 passed in registers, but that's OK. */
2913 for (argnum
= 0; argnum
< nargs
; argnum
++)
2914 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2915 sp
-= align_up (len
, 16);
2918 fprintf_unfiltered (gdb_stdlog
,
2919 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2920 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2922 /* Initialize the integer and float register pointers. */
2923 argreg
= MIPS_A0_REGNUM
;
2924 float_argreg
= mips_fpa0_regnum (gdbarch
);
2926 /* The struct_return pointer occupies the first parameter-passing reg. */
2930 fprintf_unfiltered (gdb_stdlog
,
2931 "mips_eabi_push_dummy_call: "
2932 "struct_return reg=%d %s\n",
2933 argreg
, paddress (gdbarch
, struct_addr
));
2934 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2937 /* Now load as many as possible of the first arguments into
2938 registers, and push the rest onto the stack. Loop thru args
2939 from first to last. */
2940 for (argnum
= 0; argnum
< nargs
; argnum
++)
2942 const gdb_byte
*val
;
2943 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2944 struct value
*arg
= args
[argnum
];
2945 struct type
*arg_type
= check_typedef (value_type (arg
));
2946 int len
= TYPE_LENGTH (arg_type
);
2947 enum type_code typecode
= TYPE_CODE (arg_type
);
2950 fprintf_unfiltered (gdb_stdlog
,
2951 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2952 argnum
+ 1, len
, (int) typecode
);
2954 /* Function pointer arguments to mips16 code need to be made into
2956 if (typecode
== TYPE_CODE_PTR
2957 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2959 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2961 if (mips_pc_is_mips16 (addr
))
2963 store_signed_integer (valbuf
, len
, byte_order
,
2964 make_mips16_addr (addr
));
2968 val
= value_contents (arg
);
2970 /* The EABI passes structures that do not fit in a register by
2972 else if (len
> regsize
2973 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2975 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2976 value_address (arg
));
2977 typecode
= TYPE_CODE_PTR
;
2981 fprintf_unfiltered (gdb_stdlog
, " push");
2984 val
= value_contents (arg
);
2986 /* 32-bit ABIs always start floating point arguments in an
2987 even-numbered floating point register. Round the FP register
2988 up before the check to see if there are any FP registers
2989 left. Non MIPS_EABI targets also pass the FP in the integer
2990 registers so also round up normal registers. */
2991 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2993 if ((float_argreg
& 1))
2997 /* Floating point arguments passed in registers have to be
2998 treated specially. On 32-bit architectures, doubles
2999 are passed in register pairs; the even register gets
3000 the low word, and the odd register gets the high word.
3001 On non-EABI processors, the first two floating point arguments are
3002 also copied to general registers, because MIPS16 functions
3003 don't use float registers for arguments. This duplication of
3004 arguments in general registers can't hurt non-MIPS16 functions
3005 because those registers are normally skipped. */
3006 /* MIPS_EABI squeezes a struct that contains a single floating
3007 point value into an FP register instead of pushing it onto the
3009 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3010 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3012 /* EABI32 will pass doubles in consecutive registers, even on
3013 64-bit cores. At one time, we used to check the size of
3014 `float_argreg' to determine whether or not to pass doubles
3015 in consecutive registers, but this is not sufficient for
3016 making the ABI determination. */
3017 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3019 int low_offset
= gdbarch_byte_order (gdbarch
)
3020 == BFD_ENDIAN_BIG
? 4 : 0;
3023 /* Write the low word of the double to the even register(s). */
3024 regval
= extract_signed_integer (val
+ low_offset
,
3027 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3028 float_argreg
, phex (regval
, 4));
3029 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3031 /* Write the high word of the double to the odd register(s). */
3032 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3035 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3036 float_argreg
, phex (regval
, 4));
3037 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3041 /* This is a floating point value that fits entirely
3042 in a single register. */
3043 /* On 32 bit ABI's the float_argreg is further adjusted
3044 above to ensure that it is even register aligned. */
3045 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3047 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3048 float_argreg
, phex (regval
, len
));
3049 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3054 /* Copy the argument to general registers or the stack in
3055 register-sized pieces. Large arguments are split between
3056 registers and stack. */
3057 /* Note: structs whose size is not a multiple of regsize
3058 are treated specially: Irix cc passes
3059 them in registers where gcc sometimes puts them on the
3060 stack. For maximum compatibility, we will put them in
3062 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3064 /* Note: Floating-point values that didn't fit into an FP
3065 register are only written to memory. */
3068 /* Remember if the argument was written to the stack. */
3069 int stack_used_p
= 0;
3070 int partial_len
= (len
< regsize
? len
: regsize
);
3073 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3076 /* Write this portion of the argument to the stack. */
3077 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3079 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3081 /* Should shorter than int integer values be
3082 promoted to int before being stored? */
3083 int longword_offset
= 0;
3086 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3089 && (typecode
== TYPE_CODE_INT
3090 || typecode
== TYPE_CODE_PTR
3091 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3092 longword_offset
= regsize
- len
;
3093 else if ((typecode
== TYPE_CODE_STRUCT
3094 || typecode
== TYPE_CODE_UNION
)
3095 && TYPE_LENGTH (arg_type
) < regsize
)
3096 longword_offset
= regsize
- len
;
3101 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3102 paddress (gdbarch
, stack_offset
));
3103 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3104 paddress (gdbarch
, longword_offset
));
3107 addr
= sp
+ stack_offset
+ longword_offset
;
3112 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3113 paddress (gdbarch
, addr
));
3114 for (i
= 0; i
< partial_len
; i
++)
3116 fprintf_unfiltered (gdb_stdlog
, "%02x",
3120 write_memory (addr
, val
, partial_len
);
3123 /* Note!!! This is NOT an else clause. Odd sized
3124 structs may go thru BOTH paths. Floating point
3125 arguments will not. */
3126 /* Write this portion of the argument to a general
3127 purpose register. */
3128 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3129 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3132 extract_signed_integer (val
, partial_len
, byte_order
);
3135 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3137 phex (regval
, regsize
));
3138 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3145 /* Compute the offset into the stack at which we will
3146 copy the next parameter.
3148 In the new EABI (and the NABI32), the stack_offset
3149 only needs to be adjusted when it has been used. */
3152 stack_offset
+= align_up (partial_len
, regsize
);
3156 fprintf_unfiltered (gdb_stdlog
, "\n");
3159 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3161 /* Return adjusted stack pointer. */
3165 /* Determine the return value convention being used. */
3167 static enum return_value_convention
3168 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3169 struct type
*type
, struct regcache
*regcache
,
3170 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3173 int fp_return_type
= 0;
3174 int offset
, regnum
, xfer
;
3176 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3177 return RETURN_VALUE_STRUCT_CONVENTION
;
3179 /* Floating point type? */
3180 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3182 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3184 /* Structs with a single field of float type
3185 are returned in a floating point register. */
3186 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3187 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3188 && TYPE_NFIELDS (type
) == 1)
3190 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3192 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3199 /* A floating-point value belongs in the least significant part
3202 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3203 regnum
= mips_regnum (gdbarch
)->fp0
;
3207 /* An integer value goes in V0/V1. */
3209 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3210 regnum
= MIPS_V0_REGNUM
;
3213 offset
< TYPE_LENGTH (type
);
3214 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3216 xfer
= mips_abi_regsize (gdbarch
);
3217 if (offset
+ xfer
> TYPE_LENGTH (type
))
3218 xfer
= TYPE_LENGTH (type
) - offset
;
3219 mips_xfer_register (gdbarch
, regcache
,
3220 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3221 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3225 return RETURN_VALUE_REGISTER_CONVENTION
;
3229 /* N32/N64 ABI stuff. */
3231 /* Search for a naturally aligned double at OFFSET inside a struct
3232 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3236 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3241 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3244 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3247 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3250 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3253 struct type
*field_type
;
3255 /* We're only looking at normal fields. */
3256 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3257 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3260 /* If we have gone past the offset, there is no double to pass. */
3261 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3265 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3267 /* If this field is entirely before the requested offset, go
3268 on to the next one. */
3269 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3272 /* If this is our special aligned double, we can stop. */
3273 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3274 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3277 /* This field starts at or before the requested offset, and
3278 overlaps it. If it is a structure, recurse inwards. */
3279 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3286 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3287 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3288 int nargs
, struct value
**args
, CORE_ADDR sp
,
3289 int struct_return
, CORE_ADDR struct_addr
)
3295 int stack_offset
= 0;
3296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3298 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3300 /* For shared libraries, "t9" needs to point at the function
3302 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3304 /* Set the return address register to point to the entry point of
3305 the program, where a breakpoint lies in wait. */
3306 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3308 /* First ensure that the stack and structure return address (if any)
3309 are properly aligned. The stack has to be at least 64-bit
3310 aligned even on 32-bit machines, because doubles must be 64-bit
3311 aligned. For n32 and n64, stack frames need to be 128-bit
3312 aligned, so we round to this widest known alignment. */
3314 sp
= align_down (sp
, 16);
3315 struct_addr
= align_down (struct_addr
, 16);
3317 /* Now make space on the stack for the args. */
3318 for (argnum
= 0; argnum
< nargs
; argnum
++)
3319 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3320 sp
-= align_up (len
, 16);
3323 fprintf_unfiltered (gdb_stdlog
,
3324 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3325 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3327 /* Initialize the integer and float register pointers. */
3328 argreg
= MIPS_A0_REGNUM
;
3329 float_argreg
= mips_fpa0_regnum (gdbarch
);
3331 /* The struct_return pointer occupies the first parameter-passing reg. */
3335 fprintf_unfiltered (gdb_stdlog
,
3336 "mips_n32n64_push_dummy_call: "
3337 "struct_return reg=%d %s\n",
3338 argreg
, paddress (gdbarch
, struct_addr
));
3339 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3342 /* Now load as many as possible of the first arguments into
3343 registers, and push the rest onto the stack. Loop thru args
3344 from first to last. */
3345 for (argnum
= 0; argnum
< nargs
; argnum
++)
3347 const gdb_byte
*val
;
3348 struct value
*arg
= args
[argnum
];
3349 struct type
*arg_type
= check_typedef (value_type (arg
));
3350 int len
= TYPE_LENGTH (arg_type
);
3351 enum type_code typecode
= TYPE_CODE (arg_type
);
3354 fprintf_unfiltered (gdb_stdlog
,
3355 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3356 argnum
+ 1, len
, (int) typecode
);
3358 val
= value_contents (arg
);
3360 /* A 128-bit long double value requires an even-odd pair of
3361 floating-point registers. */
3363 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3364 && (float_argreg
& 1))
3370 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3371 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3373 /* This is a floating point value that fits entirely
3374 in a single register or a pair of registers. */
3375 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3376 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3378 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3379 float_argreg
, phex (regval
, reglen
));
3380 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3383 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3384 argreg
, phex (regval
, reglen
));
3385 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3390 regval
= extract_unsigned_integer (val
+ reglen
,
3391 reglen
, byte_order
);
3393 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3394 float_argreg
, phex (regval
, reglen
));
3395 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3398 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3399 argreg
, phex (regval
, reglen
));
3400 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3407 /* Copy the argument to general registers or the stack in
3408 register-sized pieces. Large arguments are split between
3409 registers and stack. */
3410 /* For N32/N64, structs, unions, or other composite types are
3411 treated as a sequence of doublewords, and are passed in integer
3412 or floating point registers as though they were simple scalar
3413 parameters to the extent that they fit, with any excess on the
3414 stack packed according to the normal memory layout of the
3416 The caller does not reserve space for the register arguments;
3417 the callee is responsible for reserving it if required. */
3418 /* Note: Floating-point values that didn't fit into an FP
3419 register are only written to memory. */
3422 /* Remember if the argument was written to the stack. */
3423 int stack_used_p
= 0;
3424 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3427 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3430 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3431 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3433 /* Write this portion of the argument to the stack. */
3434 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3436 /* Should shorter than int integer values be
3437 promoted to int before being stored? */
3438 int longword_offset
= 0;
3441 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3443 if ((typecode
== TYPE_CODE_INT
3444 || typecode
== TYPE_CODE_PTR
)
3446 longword_offset
= MIPS64_REGSIZE
- len
;
3451 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3452 paddress (gdbarch
, stack_offset
));
3453 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3454 paddress (gdbarch
, longword_offset
));
3457 addr
= sp
+ stack_offset
+ longword_offset
;
3462 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3463 paddress (gdbarch
, addr
));
3464 for (i
= 0; i
< partial_len
; i
++)
3466 fprintf_unfiltered (gdb_stdlog
, "%02x",
3470 write_memory (addr
, val
, partial_len
);
3473 /* Note!!! This is NOT an else clause. Odd sized
3474 structs may go thru BOTH paths. */
3475 /* Write this portion of the argument to a general
3476 purpose register. */
3477 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3481 /* Sign extend pointers, 32-bit integers and signed
3482 16-bit and 8-bit integers; everything else is taken
3485 if ((partial_len
== 4
3486 && (typecode
== TYPE_CODE_PTR
3487 || typecode
== TYPE_CODE_INT
))
3489 && typecode
== TYPE_CODE_INT
3490 && !TYPE_UNSIGNED (arg_type
)))
3491 regval
= extract_signed_integer (val
, partial_len
,
3494 regval
= extract_unsigned_integer (val
, partial_len
,
3497 /* A non-floating-point argument being passed in a
3498 general register. If a struct or union, and if
3499 the remaining length is smaller than the register
3500 size, we have to adjust the register value on
3503 It does not seem to be necessary to do the
3504 same for integral types. */
3506 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3507 && partial_len
< MIPS64_REGSIZE
3508 && (typecode
== TYPE_CODE_STRUCT
3509 || typecode
== TYPE_CODE_UNION
))
3510 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3514 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3516 phex (regval
, MIPS64_REGSIZE
));
3517 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3519 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3520 TYPE_LENGTH (arg_type
) - len
))
3523 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3525 phex (regval
, MIPS64_REGSIZE
));
3526 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3537 /* Compute the offset into the stack at which we will
3538 copy the next parameter.
3540 In N32 (N64?), the stack_offset only needs to be
3541 adjusted when it has been used. */
3544 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3548 fprintf_unfiltered (gdb_stdlog
, "\n");
3551 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3553 /* Return adjusted stack pointer. */
3557 static enum return_value_convention
3558 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3559 struct type
*type
, struct regcache
*regcache
,
3560 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3564 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3566 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3567 if needed), as appropriate for the type. Composite results (struct,
3568 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3571 * A struct with only one or two floating point fields is returned in $f0
3572 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3575 * Any other composite results of at most 128 bits are returned in
3576 $2 (first 64 bits) and $3 (remainder, if necessary).
3578 * Larger composite results are handled by converting the function to a
3579 procedure with an implicit first parameter, which is a pointer to an area
3580 reserved by the caller to receive the result. [The o32-bit ABI requires
3581 that all composite results be handled by conversion to implicit first
3582 parameters. The MIPS/SGI Fortran implementation has always made a
3583 specific exception to return COMPLEX results in the floating point
3586 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3587 return RETURN_VALUE_STRUCT_CONVENTION
;
3588 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3589 && TYPE_LENGTH (type
) == 16
3590 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3592 /* A 128-bit floating-point value fills both $f0 and $f2. The
3593 two registers are used in the same as memory order, so the
3594 eight bytes with the lower memory address are in $f0. */
3596 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3597 mips_xfer_register (gdbarch
, regcache
,
3598 gdbarch_num_regs (gdbarch
)
3599 + mips_regnum (gdbarch
)->fp0
,
3600 8, gdbarch_byte_order (gdbarch
),
3601 readbuf
, writebuf
, 0);
3602 mips_xfer_register (gdbarch
, regcache
,
3603 gdbarch_num_regs (gdbarch
)
3604 + mips_regnum (gdbarch
)->fp0
+ 2,
3605 8, gdbarch_byte_order (gdbarch
),
3606 readbuf
? readbuf
+ 8 : readbuf
,
3607 writebuf
? writebuf
+ 8 : writebuf
, 0);
3608 return RETURN_VALUE_REGISTER_CONVENTION
;
3610 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3611 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3613 /* A single or double floating-point value that fits in FP0. */
3615 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3616 mips_xfer_register (gdbarch
, regcache
,
3617 gdbarch_num_regs (gdbarch
)
3618 + mips_regnum (gdbarch
)->fp0
,
3620 gdbarch_byte_order (gdbarch
),
3621 readbuf
, writebuf
, 0);
3622 return RETURN_VALUE_REGISTER_CONVENTION
;
3624 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3625 && TYPE_NFIELDS (type
) <= 2
3626 && TYPE_NFIELDS (type
) >= 1
3627 && ((TYPE_NFIELDS (type
) == 1
3628 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3630 || (TYPE_NFIELDS (type
) == 2
3631 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3633 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3634 == TYPE_CODE_FLT
))))
3636 /* A struct that contains one or two floats. Each value is part
3637 in the least significant part of their floating point
3638 register (or GPR, for soft float). */
3641 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3642 ? mips_regnum (gdbarch
)->fp0
3644 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3646 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3649 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3651 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3653 /* A 16-byte long double field goes in two consecutive
3655 mips_xfer_register (gdbarch
, regcache
,
3656 gdbarch_num_regs (gdbarch
) + regnum
,
3658 gdbarch_byte_order (gdbarch
),
3659 readbuf
, writebuf
, offset
);
3660 mips_xfer_register (gdbarch
, regcache
,
3661 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3663 gdbarch_byte_order (gdbarch
),
3664 readbuf
, writebuf
, offset
+ 8);
3667 mips_xfer_register (gdbarch
, regcache
,
3668 gdbarch_num_regs (gdbarch
) + regnum
,
3669 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3670 gdbarch_byte_order (gdbarch
),
3671 readbuf
, writebuf
, offset
);
3673 return RETURN_VALUE_REGISTER_CONVENTION
;
3675 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3676 || TYPE_CODE (type
) == TYPE_CODE_UNION
3677 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3679 /* A composite type. Extract the left justified value,
3680 regardless of the byte order. I.e. DO NOT USE
3684 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3685 offset
< TYPE_LENGTH (type
);
3686 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3688 int xfer
= register_size (gdbarch
, regnum
);
3689 if (offset
+ xfer
> TYPE_LENGTH (type
))
3690 xfer
= TYPE_LENGTH (type
) - offset
;
3692 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3693 offset
, xfer
, regnum
);
3694 mips_xfer_register (gdbarch
, regcache
,
3695 gdbarch_num_regs (gdbarch
) + regnum
,
3696 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3699 return RETURN_VALUE_REGISTER_CONVENTION
;
3703 /* A scalar extract each part but least-significant-byte
3707 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3708 offset
< TYPE_LENGTH (type
);
3709 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3711 int xfer
= register_size (gdbarch
, regnum
);
3712 if (offset
+ xfer
> TYPE_LENGTH (type
))
3713 xfer
= TYPE_LENGTH (type
) - offset
;
3715 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3716 offset
, xfer
, regnum
);
3717 mips_xfer_register (gdbarch
, regcache
,
3718 gdbarch_num_regs (gdbarch
) + regnum
,
3719 xfer
, gdbarch_byte_order (gdbarch
),
3720 readbuf
, writebuf
, offset
);
3722 return RETURN_VALUE_REGISTER_CONVENTION
;
3726 /* O32 ABI stuff. */
3729 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3730 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3731 int nargs
, struct value
**args
, CORE_ADDR sp
,
3732 int struct_return
, CORE_ADDR struct_addr
)
3738 int stack_offset
= 0;
3739 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3741 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3743 /* For shared libraries, "t9" needs to point at the function
3745 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3747 /* Set the return address register to point to the entry point of
3748 the program, where a breakpoint lies in wait. */
3749 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3751 /* First ensure that the stack and structure return address (if any)
3752 are properly aligned. The stack has to be at least 64-bit
3753 aligned even on 32-bit machines, because doubles must be 64-bit
3754 aligned. For n32 and n64, stack frames need to be 128-bit
3755 aligned, so we round to this widest known alignment. */
3757 sp
= align_down (sp
, 16);
3758 struct_addr
= align_down (struct_addr
, 16);
3760 /* Now make space on the stack for the args. */
3761 for (argnum
= 0; argnum
< nargs
; argnum
++)
3763 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3764 int arglen
= TYPE_LENGTH (arg_type
);
3766 /* Align to double-word if necessary. */
3767 if (mips_type_needs_double_align (arg_type
))
3768 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3769 /* Allocate space on the stack. */
3770 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3772 sp
-= align_up (len
, 16);
3775 fprintf_unfiltered (gdb_stdlog
,
3776 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3777 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3779 /* Initialize the integer and float register pointers. */
3780 argreg
= MIPS_A0_REGNUM
;
3781 float_argreg
= mips_fpa0_regnum (gdbarch
);
3783 /* The struct_return pointer occupies the first parameter-passing reg. */
3787 fprintf_unfiltered (gdb_stdlog
,
3788 "mips_o32_push_dummy_call: "
3789 "struct_return reg=%d %s\n",
3790 argreg
, paddress (gdbarch
, struct_addr
));
3791 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3792 stack_offset
+= MIPS32_REGSIZE
;
3795 /* Now load as many as possible of the first arguments into
3796 registers, and push the rest onto the stack. Loop thru args
3797 from first to last. */
3798 for (argnum
= 0; argnum
< nargs
; argnum
++)
3800 const gdb_byte
*val
;
3801 struct value
*arg
= args
[argnum
];
3802 struct type
*arg_type
= check_typedef (value_type (arg
));
3803 int len
= TYPE_LENGTH (arg_type
);
3804 enum type_code typecode
= TYPE_CODE (arg_type
);
3807 fprintf_unfiltered (gdb_stdlog
,
3808 "mips_o32_push_dummy_call: %d len=%d type=%d",
3809 argnum
+ 1, len
, (int) typecode
);
3811 val
= value_contents (arg
);
3813 /* 32-bit ABIs always start floating point arguments in an
3814 even-numbered floating point register. Round the FP register
3815 up before the check to see if there are any FP registers
3816 left. O32/O64 targets also pass the FP in the integer
3817 registers so also round up normal registers. */
3818 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3820 if ((float_argreg
& 1))
3824 /* Floating point arguments passed in registers have to be
3825 treated specially. On 32-bit architectures, doubles
3826 are passed in register pairs; the even register gets
3827 the low word, and the odd register gets the high word.
3828 On O32/O64, the first two floating point arguments are
3829 also copied to general registers, because MIPS16 functions
3830 don't use float registers for arguments. This duplication of
3831 arguments in general registers can't hurt non-MIPS16 functions
3832 because those registers are normally skipped. */
3834 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3835 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3837 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3839 int low_offset
= gdbarch_byte_order (gdbarch
)
3840 == BFD_ENDIAN_BIG
? 4 : 0;
3841 unsigned long regval
;
3843 /* Write the low word of the double to the even register(s). */
3844 regval
= extract_unsigned_integer (val
+ low_offset
,
3847 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3848 float_argreg
, phex (regval
, 4));
3849 regcache_cooked_write_unsigned (regcache
,
3850 float_argreg
++, regval
);
3852 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3853 argreg
, phex (regval
, 4));
3854 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3856 /* Write the high word of the double to the odd register(s). */
3857 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3860 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3861 float_argreg
, phex (regval
, 4));
3862 regcache_cooked_write_unsigned (regcache
,
3863 float_argreg
++, regval
);
3866 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3867 argreg
, phex (regval
, 4));
3868 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3872 /* This is a floating point value that fits entirely
3873 in a single register. */
3874 /* On 32 bit ABI's the float_argreg is further adjusted
3875 above to ensure that it is even register aligned. */
3876 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3878 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3879 float_argreg
, phex (regval
, len
));
3880 regcache_cooked_write_unsigned (regcache
,
3881 float_argreg
++, regval
);
3882 /* Although two FP registers are reserved for each
3883 argument, only one corresponding integer register is
3886 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3887 argreg
, phex (regval
, len
));
3888 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3890 /* Reserve space for the FP register. */
3891 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3895 /* Copy the argument to general registers or the stack in
3896 register-sized pieces. Large arguments are split between
3897 registers and stack. */
3898 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3899 are treated specially: Irix cc passes
3900 them in registers where gcc sometimes puts them on the
3901 stack. For maximum compatibility, we will put them in
3903 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3904 && len
% MIPS32_REGSIZE
!= 0);
3905 /* Structures should be aligned to eight bytes (even arg registers)
3906 on MIPS_ABI_O32, if their first member has double precision. */
3907 if (mips_type_needs_double_align (arg_type
))
3912 stack_offset
+= MIPS32_REGSIZE
;
3917 /* Remember if the argument was written to the stack. */
3918 int stack_used_p
= 0;
3919 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3922 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3925 /* Write this portion of the argument to the stack. */
3926 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3927 || odd_sized_struct
)
3929 /* Should shorter than int integer values be
3930 promoted to int before being stored? */
3931 int longword_offset
= 0;
3937 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3938 paddress (gdbarch
, stack_offset
));
3939 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3940 paddress (gdbarch
, longword_offset
));
3943 addr
= sp
+ stack_offset
+ longword_offset
;
3948 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3949 paddress (gdbarch
, addr
));
3950 for (i
= 0; i
< partial_len
; i
++)
3952 fprintf_unfiltered (gdb_stdlog
, "%02x",
3956 write_memory (addr
, val
, partial_len
);
3959 /* Note!!! This is NOT an else clause. Odd sized
3960 structs may go thru BOTH paths. */
3961 /* Write this portion of the argument to a general
3962 purpose register. */
3963 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3965 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3967 /* Value may need to be sign extended, because
3968 mips_isa_regsize() != mips_abi_regsize(). */
3970 /* A non-floating-point argument being passed in a
3971 general register. If a struct or union, and if
3972 the remaining length is smaller than the register
3973 size, we have to adjust the register value on
3976 It does not seem to be necessary to do the
3977 same for integral types.
3979 Also don't do this adjustment on O64 binaries.
3981 cagney/2001-07-23: gdb/179: Also, GCC, when
3982 outputting LE O32 with sizeof (struct) <
3983 mips_abi_regsize(), generates a left shift
3984 as part of storing the argument in a register
3985 (the left shift isn't generated when
3986 sizeof (struct) >= mips_abi_regsize()). Since
3987 it is quite possible that this is GCC
3988 contradicting the LE/O32 ABI, GDB has not been
3989 adjusted to accommodate this. Either someone
3990 needs to demonstrate that the LE/O32 ABI
3991 specifies such a left shift OR this new ABI gets
3992 identified as such and GDB gets tweaked
3995 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3996 && partial_len
< MIPS32_REGSIZE
3997 && (typecode
== TYPE_CODE_STRUCT
3998 || typecode
== TYPE_CODE_UNION
))
3999 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4003 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4005 phex (regval
, MIPS32_REGSIZE
));
4006 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4009 /* Prevent subsequent floating point arguments from
4010 being passed in floating point registers. */
4011 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4017 /* Compute the offset into the stack at which we will
4018 copy the next parameter.
4020 In older ABIs, the caller reserved space for
4021 registers that contained arguments. This was loosely
4022 refered to as their "home". Consequently, space is
4023 always allocated. */
4025 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4029 fprintf_unfiltered (gdb_stdlog
, "\n");
4032 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4034 /* Return adjusted stack pointer. */
4038 static enum return_value_convention
4039 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4040 struct type
*type
, struct regcache
*regcache
,
4041 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4043 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4045 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4046 || TYPE_CODE (type
) == TYPE_CODE_UNION
4047 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4048 return RETURN_VALUE_STRUCT_CONVENTION
;
4049 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4050 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4052 /* A single-precision floating-point value. It fits in the
4053 least significant part of FP0. */
4055 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4056 mips_xfer_register (gdbarch
, regcache
,
4057 gdbarch_num_regs (gdbarch
)
4058 + mips_regnum (gdbarch
)->fp0
,
4060 gdbarch_byte_order (gdbarch
),
4061 readbuf
, writebuf
, 0);
4062 return RETURN_VALUE_REGISTER_CONVENTION
;
4064 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4065 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4067 /* A double-precision floating-point value. The most
4068 significant part goes in FP1, and the least significant in
4071 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4072 switch (gdbarch_byte_order (gdbarch
))
4074 case BFD_ENDIAN_LITTLE
:
4075 mips_xfer_register (gdbarch
, regcache
,
4076 gdbarch_num_regs (gdbarch
)
4077 + mips_regnum (gdbarch
)->fp0
+
4078 0, 4, gdbarch_byte_order (gdbarch
),
4079 readbuf
, writebuf
, 0);
4080 mips_xfer_register (gdbarch
, regcache
,
4081 gdbarch_num_regs (gdbarch
)
4082 + mips_regnum (gdbarch
)->fp0
+ 1,
4083 4, gdbarch_byte_order (gdbarch
),
4084 readbuf
, writebuf
, 4);
4086 case BFD_ENDIAN_BIG
:
4087 mips_xfer_register (gdbarch
, regcache
,
4088 gdbarch_num_regs (gdbarch
)
4089 + mips_regnum (gdbarch
)->fp0
+ 1,
4090 4, gdbarch_byte_order (gdbarch
),
4091 readbuf
, writebuf
, 0);
4092 mips_xfer_register (gdbarch
, regcache
,
4093 gdbarch_num_regs (gdbarch
)
4094 + mips_regnum (gdbarch
)->fp0
+ 0,
4095 4, gdbarch_byte_order (gdbarch
),
4096 readbuf
, writebuf
, 4);
4099 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4101 return RETURN_VALUE_REGISTER_CONVENTION
;
4104 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4105 && TYPE_NFIELDS (type
) <= 2
4106 && TYPE_NFIELDS (type
) >= 1
4107 && ((TYPE_NFIELDS (type
) == 1
4108 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4110 || (TYPE_NFIELDS (type
) == 2
4111 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4113 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4115 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4117 /* A struct that contains one or two floats. Each value is part
4118 in the least significant part of their floating point
4120 gdb_byte reg
[MAX_REGISTER_SIZE
];
4123 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4124 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4126 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4129 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4131 mips_xfer_register (gdbarch
, regcache
,
4132 gdbarch_num_regs (gdbarch
) + regnum
,
4133 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4134 gdbarch_byte_order (gdbarch
),
4135 readbuf
, writebuf
, offset
);
4137 return RETURN_VALUE_REGISTER_CONVENTION
;
4141 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4142 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4144 /* A structure or union. Extract the left justified value,
4145 regardless of the byte order. I.e. DO NOT USE
4149 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4150 offset
< TYPE_LENGTH (type
);
4151 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4153 int xfer
= register_size (gdbarch
, regnum
);
4154 if (offset
+ xfer
> TYPE_LENGTH (type
))
4155 xfer
= TYPE_LENGTH (type
) - offset
;
4157 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4158 offset
, xfer
, regnum
);
4159 mips_xfer_register (gdbarch
, regcache
,
4160 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4161 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4163 return RETURN_VALUE_REGISTER_CONVENTION
;
4168 /* A scalar extract each part but least-significant-byte
4169 justified. o32 thinks registers are 4 byte, regardless of
4173 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4174 offset
< TYPE_LENGTH (type
);
4175 offset
+= MIPS32_REGSIZE
, regnum
++)
4177 int xfer
= MIPS32_REGSIZE
;
4178 if (offset
+ xfer
> TYPE_LENGTH (type
))
4179 xfer
= TYPE_LENGTH (type
) - offset
;
4181 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4182 offset
, xfer
, regnum
);
4183 mips_xfer_register (gdbarch
, regcache
,
4184 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4185 gdbarch_byte_order (gdbarch
),
4186 readbuf
, writebuf
, offset
);
4188 return RETURN_VALUE_REGISTER_CONVENTION
;
4192 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4196 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4197 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4199 struct value
**args
, CORE_ADDR sp
,
4200 int struct_return
, CORE_ADDR struct_addr
)
4206 int stack_offset
= 0;
4207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4208 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4209 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4211 /* For shared libraries, "t9" needs to point at the function
4213 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4215 /* Set the return address register to point to the entry point of
4216 the program, where a breakpoint lies in wait. */
4217 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4219 /* First ensure that the stack and structure return address (if any)
4220 are properly aligned. The stack has to be at least 64-bit
4221 aligned even on 32-bit machines, because doubles must be 64-bit
4222 aligned. For n32 and n64, stack frames need to be 128-bit
4223 aligned, so we round to this widest known alignment. */
4225 sp
= align_down (sp
, 16);
4226 struct_addr
= align_down (struct_addr
, 16);
4228 /* Now make space on the stack for the args. */
4229 for (argnum
= 0; argnum
< nargs
; argnum
++)
4231 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4232 int arglen
= TYPE_LENGTH (arg_type
);
4234 /* Allocate space on the stack. */
4235 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4237 sp
-= align_up (len
, 16);
4240 fprintf_unfiltered (gdb_stdlog
,
4241 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4242 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4244 /* Initialize the integer and float register pointers. */
4245 argreg
= MIPS_A0_REGNUM
;
4246 float_argreg
= mips_fpa0_regnum (gdbarch
);
4248 /* The struct_return pointer occupies the first parameter-passing reg. */
4252 fprintf_unfiltered (gdb_stdlog
,
4253 "mips_o64_push_dummy_call: "
4254 "struct_return reg=%d %s\n",
4255 argreg
, paddress (gdbarch
, struct_addr
));
4256 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4257 stack_offset
+= MIPS64_REGSIZE
;
4260 /* Now load as many as possible of the first arguments into
4261 registers, and push the rest onto the stack. Loop thru args
4262 from first to last. */
4263 for (argnum
= 0; argnum
< nargs
; argnum
++)
4265 const gdb_byte
*val
;
4266 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4267 struct value
*arg
= args
[argnum
];
4268 struct type
*arg_type
= check_typedef (value_type (arg
));
4269 int len
= TYPE_LENGTH (arg_type
);
4270 enum type_code typecode
= TYPE_CODE (arg_type
);
4273 fprintf_unfiltered (gdb_stdlog
,
4274 "mips_o64_push_dummy_call: %d len=%d type=%d",
4275 argnum
+ 1, len
, (int) typecode
);
4277 val
= value_contents (arg
);
4279 /* Function pointer arguments to mips16 code need to be made into
4281 if (typecode
== TYPE_CODE_PTR
4282 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4284 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4286 if (mips_pc_is_mips16 (addr
))
4288 store_signed_integer (valbuf
, len
, byte_order
,
4289 make_mips16_addr (addr
));
4294 /* Floating point arguments passed in registers have to be
4295 treated specially. On 32-bit architectures, doubles
4296 are passed in register pairs; the even register gets
4297 the low word, and the odd register gets the high word.
4298 On O32/O64, the first two floating point arguments are
4299 also copied to general registers, because MIPS16 functions
4300 don't use float registers for arguments. This duplication of
4301 arguments in general registers can't hurt non-MIPS16 functions
4302 because those registers are normally skipped. */
4304 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4305 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4307 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4309 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4310 float_argreg
, phex (regval
, len
));
4311 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4313 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4314 argreg
, phex (regval
, len
));
4315 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4317 /* Reserve space for the FP register. */
4318 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4322 /* Copy the argument to general registers or the stack in
4323 register-sized pieces. Large arguments are split between
4324 registers and stack. */
4325 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4326 are treated specially: Irix cc passes them in registers
4327 where gcc sometimes puts them on the stack. For maximum
4328 compatibility, we will put them in both places. */
4329 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4330 && len
% MIPS64_REGSIZE
!= 0);
4333 /* Remember if the argument was written to the stack. */
4334 int stack_used_p
= 0;
4335 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4338 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4341 /* Write this portion of the argument to the stack. */
4342 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4343 || odd_sized_struct
)
4345 /* Should shorter than int integer values be
4346 promoted to int before being stored? */
4347 int longword_offset
= 0;
4350 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4352 if ((typecode
== TYPE_CODE_INT
4353 || typecode
== TYPE_CODE_PTR
4354 || typecode
== TYPE_CODE_FLT
)
4356 longword_offset
= MIPS64_REGSIZE
- len
;
4361 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4362 paddress (gdbarch
, stack_offset
));
4363 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4364 paddress (gdbarch
, longword_offset
));
4367 addr
= sp
+ stack_offset
+ longword_offset
;
4372 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4373 paddress (gdbarch
, addr
));
4374 for (i
= 0; i
< partial_len
; i
++)
4376 fprintf_unfiltered (gdb_stdlog
, "%02x",
4380 write_memory (addr
, val
, partial_len
);
4383 /* Note!!! This is NOT an else clause. Odd sized
4384 structs may go thru BOTH paths. */
4385 /* Write this portion of the argument to a general
4386 purpose register. */
4387 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4389 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4391 /* Value may need to be sign extended, because
4392 mips_isa_regsize() != mips_abi_regsize(). */
4394 /* A non-floating-point argument being passed in a
4395 general register. If a struct or union, and if
4396 the remaining length is smaller than the register
4397 size, we have to adjust the register value on
4400 It does not seem to be necessary to do the
4401 same for integral types. */
4403 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4404 && partial_len
< MIPS64_REGSIZE
4405 && (typecode
== TYPE_CODE_STRUCT
4406 || typecode
== TYPE_CODE_UNION
))
4407 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4411 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4413 phex (regval
, MIPS64_REGSIZE
));
4414 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4417 /* Prevent subsequent floating point arguments from
4418 being passed in floating point registers. */
4419 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4425 /* Compute the offset into the stack at which we will
4426 copy the next parameter.
4428 In older ABIs, the caller reserved space for
4429 registers that contained arguments. This was loosely
4430 refered to as their "home". Consequently, space is
4431 always allocated. */
4433 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4437 fprintf_unfiltered (gdb_stdlog
, "\n");
4440 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4442 /* Return adjusted stack pointer. */
4446 static enum return_value_convention
4447 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4448 struct type
*type
, struct regcache
*regcache
,
4449 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4451 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4453 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4454 || TYPE_CODE (type
) == TYPE_CODE_UNION
4455 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4456 return RETURN_VALUE_STRUCT_CONVENTION
;
4457 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4459 /* A floating-point value. It fits in the least significant
4462 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4463 mips_xfer_register (gdbarch
, regcache
,
4464 gdbarch_num_regs (gdbarch
)
4465 + mips_regnum (gdbarch
)->fp0
,
4467 gdbarch_byte_order (gdbarch
),
4468 readbuf
, writebuf
, 0);
4469 return RETURN_VALUE_REGISTER_CONVENTION
;
4473 /* A scalar extract each part but least-significant-byte
4477 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4478 offset
< TYPE_LENGTH (type
);
4479 offset
+= MIPS64_REGSIZE
, regnum
++)
4481 int xfer
= MIPS64_REGSIZE
;
4482 if (offset
+ xfer
> TYPE_LENGTH (type
))
4483 xfer
= TYPE_LENGTH (type
) - offset
;
4485 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4486 offset
, xfer
, regnum
);
4487 mips_xfer_register (gdbarch
, regcache
,
4488 gdbarch_num_regs (gdbarch
) + regnum
,
4489 xfer
, gdbarch_byte_order (gdbarch
),
4490 readbuf
, writebuf
, offset
);
4492 return RETURN_VALUE_REGISTER_CONVENTION
;
4496 /* Floating point register management.
4498 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4499 64bit operations, these early MIPS cpus treat fp register pairs
4500 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4501 registers and offer a compatibility mode that emulates the MIPS2 fp
4502 model. When operating in MIPS2 fp compat mode, later cpu's split
4503 double precision floats into two 32-bit chunks and store them in
4504 consecutive fp regs. To display 64-bit floats stored in this
4505 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4506 Throw in user-configurable endianness and you have a real mess.
4508 The way this works is:
4509 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4510 double-precision value will be split across two logical registers.
4511 The lower-numbered logical register will hold the low-order bits,
4512 regardless of the processor's endianness.
4513 - If we are on a 64-bit processor, and we are looking for a
4514 single-precision value, it will be in the low ordered bits
4515 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4516 save slot in memory.
4517 - If we are in 64-bit mode, everything is straightforward.
4519 Note that this code only deals with "live" registers at the top of the
4520 stack. We will attempt to deal with saved registers later, when
4521 the raw/cooked register interface is in place. (We need a general
4522 interface that can deal with dynamic saved register sizes -- fp
4523 regs could be 32 bits wide in one frame and 64 on the frame above
4526 /* Copy a 32-bit single-precision value from the current frame
4527 into rare_buffer. */
4530 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4531 gdb_byte
*rare_buffer
)
4533 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4534 int raw_size
= register_size (gdbarch
, regno
);
4535 gdb_byte
*raw_buffer
= alloca (raw_size
);
4537 if (!frame_register_read (frame
, regno
, raw_buffer
))
4538 error (_("can't read register %d (%s)"),
4539 regno
, gdbarch_register_name (gdbarch
, regno
));
4542 /* We have a 64-bit value for this register. Find the low-order
4546 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4551 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4555 memcpy (rare_buffer
, raw_buffer
, 4);
4559 /* Copy a 64-bit double-precision value from the current frame into
4560 rare_buffer. This may include getting half of it from the next
4564 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4565 gdb_byte
*rare_buffer
)
4567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4568 int raw_size
= register_size (gdbarch
, regno
);
4570 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4572 /* We have a 64-bit value for this register, and we should use
4574 if (!frame_register_read (frame
, regno
, rare_buffer
))
4575 error (_("can't read register %d (%s)"),
4576 regno
, gdbarch_register_name (gdbarch
, regno
));
4580 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4582 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4583 internal_error (__FILE__
, __LINE__
,
4584 _("mips_read_fp_register_double: bad access to "
4585 "odd-numbered FP register"));
4587 /* mips_read_fp_register_single will find the correct 32 bits from
4589 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4591 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4592 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4596 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4597 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4603 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4605 { /* Do values for FP (float) regs. */
4606 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4607 gdb_byte
*raw_buffer
;
4608 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4611 raw_buffer
= alloca (2 * register_size (gdbarch
,
4612 mips_regnum (gdbarch
)->fp0
));
4614 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4615 fprintf_filtered (file
, "%*s",
4616 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4619 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4621 struct value_print_options opts
;
4623 /* 4-byte registers: Print hex and floating. Also print even
4624 numbered registers as doubles. */
4625 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4626 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4629 get_formatted_print_options (&opts
, 'x');
4630 print_scalar_formatted (raw_buffer
,
4631 builtin_type (gdbarch
)->builtin_uint32
,
4634 fprintf_filtered (file
, " flt: ");
4636 fprintf_filtered (file
, " <invalid float> ");
4638 fprintf_filtered (file
, "%-17.9g", flt1
);
4640 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4642 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4643 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4646 fprintf_filtered (file
, " dbl: ");
4648 fprintf_filtered (file
, "<invalid double>");
4650 fprintf_filtered (file
, "%-24.17g", doub
);
4655 struct value_print_options opts
;
4657 /* Eight byte registers: print each one as hex, float and double. */
4658 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4659 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4662 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4663 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4666 get_formatted_print_options (&opts
, 'x');
4667 print_scalar_formatted (raw_buffer
,
4668 builtin_type (gdbarch
)->builtin_uint64
,
4671 fprintf_filtered (file
, " flt: ");
4673 fprintf_filtered (file
, "<invalid float>");
4675 fprintf_filtered (file
, "%-17.9g", flt1
);
4677 fprintf_filtered (file
, " dbl: ");
4679 fprintf_filtered (file
, "<invalid double>");
4681 fprintf_filtered (file
, "%-24.17g", doub
);
4686 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4689 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4691 struct value_print_options opts
;
4694 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4696 mips_print_fp_register (file
, frame
, regnum
);
4700 val
= get_frame_register_value (frame
, regnum
);
4701 if (value_optimized_out (val
))
4703 fprintf_filtered (file
, "%s: [Invalid]",
4704 gdbarch_register_name (gdbarch
, regnum
));
4708 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4710 /* The problem with printing numeric register names (r26, etc.) is that
4711 the user can't use them on input. Probably the best solution is to
4712 fix it so that either the numeric or the funky (a2, etc.) names
4713 are accepted on input. */
4714 if (regnum
< MIPS_NUMREGS
)
4715 fprintf_filtered (file
, "(r%d): ", regnum
);
4717 fprintf_filtered (file
, ": ");
4719 get_formatted_print_options (&opts
, 'x');
4720 val_print_scalar_formatted (value_type (val
),
4721 value_contents_for_printing (val
),
4722 value_embedded_offset (val
),
4727 /* Replacement for generic do_registers_info.
4728 Print regs in pretty columns. */
4731 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4734 fprintf_filtered (file
, " ");
4735 mips_print_fp_register (file
, frame
, regnum
);
4736 fprintf_filtered (file
, "\n");
4741 /* Print a row's worth of GP (int) registers, with name labels above. */
4744 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4747 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4748 /* Do values for GP (int) regs. */
4749 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4750 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4755 /* For GP registers, we print a separate row of names above the vals. */
4756 for (col
= 0, regnum
= start_regnum
;
4757 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4758 + gdbarch_num_pseudo_regs (gdbarch
);
4761 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4762 continue; /* unused register */
4763 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4765 break; /* End the row: reached FP register. */
4766 /* Large registers are handled separately. */
4767 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4770 break; /* End the row before this register. */
4772 /* Print this register on a row by itself. */
4773 mips_print_register (file
, frame
, regnum
);
4774 fprintf_filtered (file
, "\n");
4778 fprintf_filtered (file
, " ");
4779 fprintf_filtered (file
,
4780 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4781 gdbarch_register_name (gdbarch
, regnum
));
4788 /* Print the R0 to R31 names. */
4789 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4790 fprintf_filtered (file
, "\n R%-4d",
4791 start_regnum
% gdbarch_num_regs (gdbarch
));
4793 fprintf_filtered (file
, "\n ");
4795 /* Now print the values in hex, 4 or 8 to the row. */
4796 for (col
= 0, regnum
= start_regnum
;
4797 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4798 + gdbarch_num_pseudo_regs (gdbarch
);
4801 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4802 continue; /* unused register */
4803 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4805 break; /* End row: reached FP register. */
4806 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4807 break; /* End row: large register. */
4809 /* OK: get the data in raw format. */
4810 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4811 error (_("can't read register %d (%s)"),
4812 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4813 /* pad small registers */
4815 byte
< (mips_abi_regsize (gdbarch
)
4816 - register_size (gdbarch
, regnum
)); byte
++)
4817 printf_filtered (" ");
4818 /* Now print the register value in hex, endian order. */
4819 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4821 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4822 byte
< register_size (gdbarch
, regnum
); byte
++)
4823 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4825 for (byte
= register_size (gdbarch
, regnum
) - 1;
4827 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4828 fprintf_filtered (file
, " ");
4831 if (col
> 0) /* ie. if we actually printed anything... */
4832 fprintf_filtered (file
, "\n");
4837 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4840 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4841 struct frame_info
*frame
, int regnum
, int all
)
4843 if (regnum
!= -1) /* Do one specified register. */
4845 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4846 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4847 error (_("Not a valid register for the current processor type"));
4849 mips_print_register (file
, frame
, regnum
);
4850 fprintf_filtered (file
, "\n");
4853 /* Do all (or most) registers. */
4855 regnum
= gdbarch_num_regs (gdbarch
);
4856 while (regnum
< gdbarch_num_regs (gdbarch
)
4857 + gdbarch_num_pseudo_regs (gdbarch
))
4859 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4862 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4863 regnum
= print_fp_register_row (file
, frame
, regnum
);
4865 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4868 regnum
= print_gp_register_row (file
, frame
, regnum
);
4873 /* Is this a branch with a delay slot? */
4876 is_delayed (unsigned long insn
)
4879 for (i
= 0; i
< NUMOPCODES
; ++i
)
4880 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4881 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4883 return (i
< NUMOPCODES
4884 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4885 | INSN_COND_BRANCH_DELAY
4886 | INSN_COND_BRANCH_LIKELY
)));
4890 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4891 struct frame_info
*frame
)
4893 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4894 CORE_ADDR pc
= get_frame_pc (frame
);
4895 gdb_byte buf
[MIPS_INSN32_SIZE
];
4897 /* There is no branch delay slot on MIPS16. */
4898 if (mips_pc_is_mips16 (pc
))
4901 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4904 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4905 /* If error reading memory, guess that it is not a delayed
4908 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4911 /* To skip prologues, I use this predicate. Returns either PC itself
4912 if the code at PC does not look like a function prologue; otherwise
4913 returns an address that (if we're lucky) follows the prologue. If
4914 LENIENT, then we must skip everything which is involved in setting
4915 up the frame (it's OK to skip more, just so long as we don't skip
4916 anything which might clobber the registers which are being saved.
4917 We must skip more in the case where part of the prologue is in the
4918 delay slot of a non-prologue instruction). */
4921 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4924 CORE_ADDR func_addr
;
4926 /* See if we can determine the end of the prologue via the symbol table.
4927 If so, then return either PC, or the PC after the prologue, whichever
4929 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4931 CORE_ADDR post_prologue_pc
4932 = skip_prologue_using_sal (gdbarch
, func_addr
);
4933 if (post_prologue_pc
!= 0)
4934 return max (pc
, post_prologue_pc
);
4937 /* Can't determine prologue from the symbol table, need to examine
4940 /* Find an upper limit on the function prologue using the debug
4941 information. If the debug information could not be used to provide
4942 that bound, then use an arbitrary large number as the upper bound. */
4943 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4945 limit_pc
= pc
+ 100; /* Magic. */
4947 if (mips_pc_is_mips16 (pc
))
4948 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4950 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4953 /* Check whether the PC is in a function epilogue (32-bit version).
4954 This is a helper function for mips_in_function_epilogue_p. */
4956 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4958 CORE_ADDR func_addr
= 0, func_end
= 0;
4960 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4962 /* The MIPS epilogue is max. 12 bytes long. */
4963 CORE_ADDR addr
= func_end
- 12;
4965 if (addr
< func_addr
+ 4)
4966 addr
= func_addr
+ 4;
4970 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4972 unsigned long high_word
;
4975 inst
= mips_fetch_instruction (gdbarch
, pc
);
4976 high_word
= (inst
>> 16) & 0xffff;
4978 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4979 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4980 && inst
!= 0x03e00008 /* jr $ra */
4981 && inst
!= 0x00000000) /* nop */
4991 /* Check whether the PC is in a function epilogue (16-bit version).
4992 This is a helper function for mips_in_function_epilogue_p. */
4994 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4996 CORE_ADDR func_addr
= 0, func_end
= 0;
4998 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5000 /* The MIPS epilogue is max. 12 bytes long. */
5001 CORE_ADDR addr
= func_end
- 12;
5003 if (addr
< func_addr
+ 4)
5004 addr
= func_addr
+ 4;
5008 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5010 unsigned short inst
;
5012 inst
= mips_fetch_instruction (gdbarch
, pc
);
5014 if ((inst
& 0xf800) == 0xf000) /* extend */
5017 if (inst
!= 0x6300 /* addiu $sp,offset */
5018 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5019 && inst
!= 0xe820 /* jr $ra */
5020 && inst
!= 0xe8a0 /* jrc $ra */
5021 && inst
!= 0x6500) /* nop */
5031 /* The epilogue is defined here as the area at the end of a function,
5032 after an instruction which destroys the function's stack frame. */
5034 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5036 if (mips_pc_is_mips16 (pc
))
5037 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5039 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5042 /* Root of all "set mips "/"show mips " commands. This will eventually be
5043 used for all MIPS-specific commands. */
5046 show_mips_command (char *args
, int from_tty
)
5048 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5052 set_mips_command (char *args
, int from_tty
)
5055 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5056 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5059 /* Commands to show/set the MIPS FPU type. */
5062 show_mipsfpu_command (char *args
, int from_tty
)
5066 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5069 ("The MIPS floating-point coprocessor is unknown "
5070 "because the current architecture is not MIPS.\n");
5074 switch (MIPS_FPU_TYPE (target_gdbarch
))
5076 case MIPS_FPU_SINGLE
:
5077 fpu
= "single-precision";
5079 case MIPS_FPU_DOUBLE
:
5080 fpu
= "double-precision";
5083 fpu
= "absent (none)";
5086 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5088 if (mips_fpu_type_auto
)
5089 printf_unfiltered ("The MIPS floating-point coprocessor "
5090 "is set automatically (currently %s)\n",
5094 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5099 set_mipsfpu_command (char *args
, int from_tty
)
5101 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5102 "\"single\",\"none\" or \"auto\".\n");
5103 show_mipsfpu_command (args
, from_tty
);
5107 set_mipsfpu_single_command (char *args
, int from_tty
)
5109 struct gdbarch_info info
;
5110 gdbarch_info_init (&info
);
5111 mips_fpu_type
= MIPS_FPU_SINGLE
;
5112 mips_fpu_type_auto
= 0;
5113 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5114 instead of relying on globals. Doing that would let generic code
5115 handle the search for this specific architecture. */
5116 if (!gdbarch_update_p (info
))
5117 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5121 set_mipsfpu_double_command (char *args
, int from_tty
)
5123 struct gdbarch_info info
;
5124 gdbarch_info_init (&info
);
5125 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5126 mips_fpu_type_auto
= 0;
5127 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5128 instead of relying on globals. Doing that would let generic code
5129 handle the search for this specific architecture. */
5130 if (!gdbarch_update_p (info
))
5131 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5135 set_mipsfpu_none_command (char *args
, int from_tty
)
5137 struct gdbarch_info info
;
5138 gdbarch_info_init (&info
);
5139 mips_fpu_type
= MIPS_FPU_NONE
;
5140 mips_fpu_type_auto
= 0;
5141 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5142 instead of relying on globals. Doing that would let generic code
5143 handle the search for this specific architecture. */
5144 if (!gdbarch_update_p (info
))
5145 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5149 set_mipsfpu_auto_command (char *args
, int from_tty
)
5151 mips_fpu_type_auto
= 1;
5154 /* Attempt to identify the particular processor model by reading the
5155 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5156 the relevant processor still exists (it dates back to '94) and
5157 secondly this is not the way to do this. The processor type should
5158 be set by forcing an architecture change. */
5161 deprecated_mips_set_processor_regs_hack (void)
5163 struct regcache
*regcache
= get_current_regcache ();
5164 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5168 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5169 if ((prid
& ~0xf) == 0x700)
5170 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5173 /* Just like reinit_frame_cache, but with the right arguments to be
5174 callable as an sfunc. */
5177 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5178 struct cmd_list_element
*c
)
5180 reinit_frame_cache ();
5184 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5186 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5187 disassembler needs to be able to locally determine the ISA, and
5188 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5190 if (mips_pc_is_mips16 (memaddr
))
5191 info
->mach
= bfd_mach_mips16
;
5193 /* Round down the instruction address to the appropriate boundary. */
5194 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5196 /* Set the disassembler options. */
5197 if (!info
->disassembler_options
)
5198 /* This string is not recognized explicitly by the disassembler,
5199 but it tells the disassembler to not try to guess the ABI from
5200 the bfd elf headers, such that, if the user overrides the ABI
5201 of a program linked as NewABI, the disassembly will follow the
5202 register naming conventions specified by the user. */
5203 info
->disassembler_options
= "gpr-names=32";
5205 /* Call the appropriate disassembler based on the target endian-ness. */
5206 if (info
->endian
== BFD_ENDIAN_BIG
)
5207 return print_insn_big_mips (memaddr
, info
);
5209 return print_insn_little_mips (memaddr
, info
);
5213 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5215 /* Set up the disassembler info, so that we get the right
5216 register names from libopcodes. */
5217 info
->disassembler_options
= "gpr-names=n32";
5218 info
->flavour
= bfd_target_elf_flavour
;
5220 return gdb_print_insn_mips (memaddr
, info
);
5224 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5226 /* Set up the disassembler info, so that we get the right
5227 register names from libopcodes. */
5228 info
->disassembler_options
= "gpr-names=64";
5229 info
->flavour
= bfd_target_elf_flavour
;
5231 return gdb_print_insn_mips (memaddr
, info
);
5234 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5235 program counter value to determine whether a 16- or 32-bit breakpoint
5236 should be used. It returns a pointer to a string of bytes that encode a
5237 breakpoint instruction, stores the length of the string to *lenptr, and
5238 adjusts pc (if necessary) to point to the actual memory location where
5239 the breakpoint should be inserted. */
5241 static const gdb_byte
*
5242 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5243 CORE_ADDR
*pcptr
, int *lenptr
)
5245 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5247 if (mips_pc_is_mips16 (*pcptr
))
5249 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5250 *pcptr
= unmake_mips16_addr (*pcptr
);
5251 *lenptr
= sizeof (mips16_big_breakpoint
);
5252 return mips16_big_breakpoint
;
5256 /* The IDT board uses an unusual breakpoint value, and
5257 sometimes gets confused when it sees the usual MIPS
5258 breakpoint instruction. */
5259 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5260 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5261 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5262 /* Likewise, IRIX appears to expect a different breakpoint,
5263 although this is not apparent until you try to use pthreads. */
5264 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5266 *lenptr
= sizeof (big_breakpoint
);
5268 if (strcmp (target_shortname
, "mips") == 0)
5269 return idt_big_breakpoint
;
5270 else if (strcmp (target_shortname
, "ddb") == 0
5271 || strcmp (target_shortname
, "pmon") == 0
5272 || strcmp (target_shortname
, "lsi") == 0)
5273 return pmon_big_breakpoint
;
5274 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5275 return irix_big_breakpoint
;
5277 return big_breakpoint
;
5282 if (mips_pc_is_mips16 (*pcptr
))
5284 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5285 *pcptr
= unmake_mips16_addr (*pcptr
);
5286 *lenptr
= sizeof (mips16_little_breakpoint
);
5287 return mips16_little_breakpoint
;
5291 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5292 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5293 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5295 *lenptr
= sizeof (little_breakpoint
);
5297 if (strcmp (target_shortname
, "mips") == 0)
5298 return idt_little_breakpoint
;
5299 else if (strcmp (target_shortname
, "ddb") == 0
5300 || strcmp (target_shortname
, "pmon") == 0
5301 || strcmp (target_shortname
, "lsi") == 0)
5302 return pmon_little_breakpoint
;
5304 return little_breakpoint
;
5309 /* If PC is in a mips16 call or return stub, return the address of the target
5310 PC, which is either the callee or the caller. There are several
5311 cases which must be handled:
5313 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5314 target PC is in $31 ($ra).
5315 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5316 and the target PC is in $2.
5317 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5318 before the jal instruction, this is effectively a call stub
5319 and the target PC is in $2. Otherwise this is effectively
5320 a return stub and the target PC is in $18.
5322 See the source code for the stubs in gcc/config/mips/mips16.S for
5326 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5328 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5330 CORE_ADDR start_addr
;
5332 /* Find the starting address and name of the function containing the PC. */
5333 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5336 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5337 target PC is in $31 ($ra). */
5338 if (strcmp (name
, "__mips16_ret_sf") == 0
5339 || strcmp (name
, "__mips16_ret_df") == 0)
5340 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5342 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5344 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5345 and the target PC is in $2. */
5346 if (name
[19] >= '0' && name
[19] <= '9')
5347 return get_frame_register_signed (frame
, 2);
5349 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5350 before the jal instruction, this is effectively a call stub
5351 and the target PC is in $2. Otherwise this is effectively
5352 a return stub and the target PC is in $18. */
5353 else if (name
[19] == 's' || name
[19] == 'd')
5355 if (pc
== start_addr
)
5357 /* Check if the target of the stub is a compiler-generated
5358 stub. Such a stub for a function bar might have a name
5359 like __fn_stub_bar, and might look like this:
5364 la $1,bar (becomes a lui/addiu pair)
5366 So scan down to the lui/addi and extract the target
5367 address from those two instructions. */
5369 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5373 /* See if the name of the target function is __fn_stub_*. */
5374 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5377 if (strncmp (name
, "__fn_stub_", 10) != 0
5378 && strcmp (name
, "etext") != 0
5379 && strcmp (name
, "_etext") != 0)
5382 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5383 The limit on the search is arbitrarily set to 20
5384 instructions. FIXME. */
5385 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5387 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5388 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5389 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5390 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5391 return pc
| (inst
& 0xffff); /* low word */
5394 /* Couldn't find the lui/addui pair, so return stub address. */
5398 /* This is the 'return' part of a call stub. The return
5399 address is in $r18. */
5400 return get_frame_register_signed (frame
, 18);
5403 return 0; /* not a stub */
5406 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5407 PC of the stub target. The stub just loads $t9 and jumps to it,
5408 so that $t9 has the correct value at function entry. */
5411 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5413 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5414 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5415 struct minimal_symbol
*msym
;
5417 gdb_byte stub_code
[16];
5418 int32_t stub_words
[4];
5420 /* The stub for foo is named ".pic.foo", and is either two
5421 instructions inserted before foo or a three instruction sequence
5422 which jumps to foo. */
5423 msym
= lookup_minimal_symbol_by_pc (pc
);
5425 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5426 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5427 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5430 /* A two-instruction header. */
5431 if (MSYMBOL_SIZE (msym
) == 8)
5434 /* A three-instruction (plus delay slot) trampoline. */
5435 if (MSYMBOL_SIZE (msym
) == 16)
5437 if (target_read_memory (pc
, stub_code
, 16) != 0)
5439 for (i
= 0; i
< 4; i
++)
5440 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5443 /* A stub contains these instructions:
5446 addiu t9, t9, %lo(target)
5449 This works even for N64, since stubs are only generated with
5451 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5452 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5453 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5454 && stub_words
[3] == 0x00000000)
5455 return (((stub_words
[0] & 0x0000ffff) << 16)
5456 + (stub_words
[2] & 0x0000ffff));
5459 /* Not a recognized stub. */
5464 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5466 CORE_ADDR target_pc
;
5468 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5472 target_pc
= find_solib_trampoline_target (frame
, pc
);
5476 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5483 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5484 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5487 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5490 if (num
>= 0 && num
< 32)
5492 else if (num
>= 38 && num
< 70)
5493 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5495 regnum
= mips_regnum (gdbarch
)->hi
;
5497 regnum
= mips_regnum (gdbarch
)->lo
;
5499 /* This will hopefully (eventually) provoke a warning. Should
5500 we be calling complaint() here? */
5501 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5502 return gdbarch_num_regs (gdbarch
) + regnum
;
5506 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5507 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5510 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5513 if (num
>= 0 && num
< 32)
5515 else if (num
>= 32 && num
< 64)
5516 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5518 regnum
= mips_regnum (gdbarch
)->hi
;
5520 regnum
= mips_regnum (gdbarch
)->lo
;
5522 /* This will hopefully (eventually) provoke a warning. Should we
5523 be calling complaint() here? */
5524 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5525 return gdbarch_num_regs (gdbarch
) + regnum
;
5529 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5531 /* Only makes sense to supply raw registers. */
5532 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5533 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5534 decide if it is valid. Should instead define a standard sim/gdb
5535 register numbering scheme. */
5536 if (gdbarch_register_name (gdbarch
,
5537 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5538 && gdbarch_register_name (gdbarch
,
5539 gdbarch_num_regs (gdbarch
)
5540 + regnum
)[0] != '\0')
5543 return LEGACY_SIM_REGNO_IGNORE
;
5547 /* Convert an integer into an address. Extracting the value signed
5548 guarantees a correctly sign extended address. */
5551 mips_integer_to_address (struct gdbarch
*gdbarch
,
5552 struct type
*type
, const gdb_byte
*buf
)
5554 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5555 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5558 /* Dummy virtual frame pointer method. This is no more or less accurate
5559 than most other architectures; we just need to be explicit about it,
5560 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5561 an assertion failure. */
5564 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5565 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5567 *reg
= MIPS_SP_REGNUM
;
5572 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5574 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5575 const char *name
= bfd_get_section_name (abfd
, sect
);
5577 if (*abip
!= MIPS_ABI_UNKNOWN
)
5580 if (strncmp (name
, ".mdebug.", 8) != 0)
5583 if (strcmp (name
, ".mdebug.abi32") == 0)
5584 *abip
= MIPS_ABI_O32
;
5585 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5586 *abip
= MIPS_ABI_N32
;
5587 else if (strcmp (name
, ".mdebug.abi64") == 0)
5588 *abip
= MIPS_ABI_N64
;
5589 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5590 *abip
= MIPS_ABI_O64
;
5591 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5592 *abip
= MIPS_ABI_EABI32
;
5593 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5594 *abip
= MIPS_ABI_EABI64
;
5596 warning (_("unsupported ABI %s."), name
+ 8);
5600 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5602 int *lbp
= (int *) obj
;
5603 const char *name
= bfd_get_section_name (abfd
, sect
);
5605 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5607 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5609 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5610 warning (_("unrecognized .gcc_compiled_longXX"));
5613 static enum mips_abi
5614 global_mips_abi (void)
5618 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5619 if (mips_abi_strings
[i
] == mips_abi_string
)
5620 return (enum mips_abi
) i
;
5622 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5626 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5628 /* If the size matches the set of 32-bit or 64-bit integer registers,
5629 assume that's what we've got. */
5630 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5631 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5633 /* If the size matches the full set of registers GDB traditionally
5634 knows about, including floating point, for either 32-bit or
5635 64-bit, assume that's what we've got. */
5636 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5637 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5639 /* Otherwise we don't have a useful guess. */
5642 static struct value
*
5643 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5645 const int *reg_p
= baton
;
5646 return value_of_register (*reg_p
, frame
);
5649 static struct gdbarch
*
5650 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5652 struct gdbarch
*gdbarch
;
5653 struct gdbarch_tdep
*tdep
;
5655 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5657 enum mips_fpu_type fpu_type
;
5658 struct tdesc_arch_data
*tdesc_data
= NULL
;
5659 int elf_fpu_type
= 0;
5661 /* Check any target description for validity. */
5662 if (tdesc_has_registers (info
.target_desc
))
5664 static const char *const mips_gprs
[] = {
5665 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5666 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5667 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5668 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5670 static const char *const mips_fprs
[] = {
5671 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5672 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5673 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5674 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5677 const struct tdesc_feature
*feature
;
5680 feature
= tdesc_find_feature (info
.target_desc
,
5681 "org.gnu.gdb.mips.cpu");
5682 if (feature
== NULL
)
5685 tdesc_data
= tdesc_data_alloc ();
5688 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5689 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5693 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5694 MIPS_EMBED_LO_REGNUM
, "lo");
5695 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5696 MIPS_EMBED_HI_REGNUM
, "hi");
5697 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5698 MIPS_EMBED_PC_REGNUM
, "pc");
5702 tdesc_data_cleanup (tdesc_data
);
5706 feature
= tdesc_find_feature (info
.target_desc
,
5707 "org.gnu.gdb.mips.cp0");
5708 if (feature
== NULL
)
5710 tdesc_data_cleanup (tdesc_data
);
5715 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5716 MIPS_EMBED_BADVADDR_REGNUM
,
5718 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5719 MIPS_PS_REGNUM
, "status");
5720 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5721 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5725 tdesc_data_cleanup (tdesc_data
);
5729 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5730 backend is not prepared for that, though. */
5731 feature
= tdesc_find_feature (info
.target_desc
,
5732 "org.gnu.gdb.mips.fpu");
5733 if (feature
== NULL
)
5735 tdesc_data_cleanup (tdesc_data
);
5740 for (i
= 0; i
< 32; i
++)
5741 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5742 i
+ MIPS_EMBED_FP0_REGNUM
,
5745 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5746 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5747 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5748 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5752 tdesc_data_cleanup (tdesc_data
);
5756 /* It would be nice to detect an attempt to use a 64-bit ABI
5757 when only 32-bit registers are provided. */
5760 /* First of all, extract the elf_flags, if available. */
5761 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5762 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5763 else if (arches
!= NULL
)
5764 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5768 fprintf_unfiltered (gdb_stdlog
,
5769 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5771 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5772 switch ((elf_flags
& EF_MIPS_ABI
))
5774 case E_MIPS_ABI_O32
:
5775 found_abi
= MIPS_ABI_O32
;
5777 case E_MIPS_ABI_O64
:
5778 found_abi
= MIPS_ABI_O64
;
5780 case E_MIPS_ABI_EABI32
:
5781 found_abi
= MIPS_ABI_EABI32
;
5783 case E_MIPS_ABI_EABI64
:
5784 found_abi
= MIPS_ABI_EABI64
;
5787 if ((elf_flags
& EF_MIPS_ABI2
))
5788 found_abi
= MIPS_ABI_N32
;
5790 found_abi
= MIPS_ABI_UNKNOWN
;
5794 /* GCC creates a pseudo-section whose name describes the ABI. */
5795 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5796 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5798 /* If we have no useful BFD information, use the ABI from the last
5799 MIPS architecture (if there is one). */
5800 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5801 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5803 /* Try the architecture for any hint of the correct ABI. */
5804 if (found_abi
== MIPS_ABI_UNKNOWN
5805 && info
.bfd_arch_info
!= NULL
5806 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5808 switch (info
.bfd_arch_info
->mach
)
5810 case bfd_mach_mips3900
:
5811 found_abi
= MIPS_ABI_EABI32
;
5813 case bfd_mach_mips4100
:
5814 case bfd_mach_mips5000
:
5815 found_abi
= MIPS_ABI_EABI64
;
5817 case bfd_mach_mips8000
:
5818 case bfd_mach_mips10000
:
5819 /* On Irix, ELF64 executables use the N64 ABI. The
5820 pseudo-sections which describe the ABI aren't present
5821 on IRIX. (Even for executables created by gcc.) */
5822 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5823 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5824 found_abi
= MIPS_ABI_N64
;
5826 found_abi
= MIPS_ABI_N32
;
5831 /* Default 64-bit objects to N64 instead of O32. */
5832 if (found_abi
== MIPS_ABI_UNKNOWN
5833 && info
.abfd
!= NULL
5834 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5835 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5836 found_abi
= MIPS_ABI_N64
;
5839 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5842 /* What has the user specified from the command line? */
5843 wanted_abi
= global_mips_abi ();
5845 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5848 /* Now that we have found what the ABI for this binary would be,
5849 check whether the user is overriding it. */
5850 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5851 mips_abi
= wanted_abi
;
5852 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5853 mips_abi
= found_abi
;
5855 mips_abi
= MIPS_ABI_O32
;
5857 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5860 /* Also used when doing an architecture lookup. */
5862 fprintf_unfiltered (gdb_stdlog
,
5863 "mips_gdbarch_init: "
5864 "mips64_transfers_32bit_regs_p = %d\n",
5865 mips64_transfers_32bit_regs_p
);
5867 /* Determine the MIPS FPU type. */
5870 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5871 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5872 Tag_GNU_MIPS_ABI_FP
);
5873 #endif /* HAVE_ELF */
5875 if (!mips_fpu_type_auto
)
5876 fpu_type
= mips_fpu_type
;
5877 else if (elf_fpu_type
!= 0)
5879 switch (elf_fpu_type
)
5882 fpu_type
= MIPS_FPU_DOUBLE
;
5885 fpu_type
= MIPS_FPU_SINGLE
;
5889 /* Soft float or unknown. */
5890 fpu_type
= MIPS_FPU_NONE
;
5894 else if (info
.bfd_arch_info
!= NULL
5895 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5896 switch (info
.bfd_arch_info
->mach
)
5898 case bfd_mach_mips3900
:
5899 case bfd_mach_mips4100
:
5900 case bfd_mach_mips4111
:
5901 case bfd_mach_mips4120
:
5902 fpu_type
= MIPS_FPU_NONE
;
5904 case bfd_mach_mips4650
:
5905 fpu_type
= MIPS_FPU_SINGLE
;
5908 fpu_type
= MIPS_FPU_DOUBLE
;
5911 else if (arches
!= NULL
)
5912 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5914 fpu_type
= MIPS_FPU_DOUBLE
;
5916 fprintf_unfiltered (gdb_stdlog
,
5917 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5919 /* Check for blatant incompatibilities. */
5921 /* If we have only 32-bit registers, then we can't debug a 64-bit
5923 if (info
.target_desc
5924 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5925 && mips_abi
!= MIPS_ABI_EABI32
5926 && mips_abi
!= MIPS_ABI_O32
)
5928 if (tdesc_data
!= NULL
)
5929 tdesc_data_cleanup (tdesc_data
);
5933 /* Try to find a pre-existing architecture. */
5934 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5936 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5938 /* MIPS needs to be pedantic about which ABI the object is
5940 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5942 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5944 /* Need to be pedantic about which register virtual size is
5946 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5947 != mips64_transfers_32bit_regs_p
)
5949 /* Be pedantic about which FPU is selected. */
5950 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5953 if (tdesc_data
!= NULL
)
5954 tdesc_data_cleanup (tdesc_data
);
5955 return arches
->gdbarch
;
5958 /* Need a new architecture. Fill in a target specific vector. */
5959 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5960 gdbarch
= gdbarch_alloc (&info
, tdep
);
5961 tdep
->elf_flags
= elf_flags
;
5962 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5963 tdep
->found_abi
= found_abi
;
5964 tdep
->mips_abi
= mips_abi
;
5965 tdep
->mips_fpu_type
= fpu_type
;
5966 tdep
->register_size_valid_p
= 0;
5967 tdep
->register_size
= 0;
5968 tdep
->gregset
= NULL
;
5969 tdep
->gregset64
= NULL
;
5970 tdep
->fpregset
= NULL
;
5971 tdep
->fpregset64
= NULL
;
5973 if (info
.target_desc
)
5975 /* Some useful properties can be inferred from the target. */
5976 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5978 tdep
->register_size_valid_p
= 1;
5979 tdep
->register_size
= 4;
5981 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5983 tdep
->register_size_valid_p
= 1;
5984 tdep
->register_size
= 8;
5988 /* Initially set everything according to the default ABI/ISA. */
5989 set_gdbarch_short_bit (gdbarch
, 16);
5990 set_gdbarch_int_bit (gdbarch
, 32);
5991 set_gdbarch_float_bit (gdbarch
, 32);
5992 set_gdbarch_double_bit (gdbarch
, 64);
5993 set_gdbarch_long_double_bit (gdbarch
, 64);
5994 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5995 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5996 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5998 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
5999 mips_ax_pseudo_register_collect
);
6000 set_gdbarch_ax_pseudo_register_push_stack
6001 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6003 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6004 mips_elf_make_msymbol_special
);
6006 /* Fill in the OS dependant register numbers and names. */
6008 const char **reg_names
;
6009 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6010 struct mips_regnum
);
6011 if (tdesc_has_registers (info
.target_desc
))
6013 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6014 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6015 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6016 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6017 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6018 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6019 regnum
->fp_control_status
= 70;
6020 regnum
->fp_implementation_revision
= 71;
6021 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6024 else if (info
.osabi
== GDB_OSABI_IRIX
)
6029 regnum
->badvaddr
= 66;
6032 regnum
->fp_control_status
= 69;
6033 regnum
->fp_implementation_revision
= 70;
6035 reg_names
= mips_irix_reg_names
;
6039 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6040 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6041 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6042 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6043 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6044 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6045 regnum
->fp_control_status
= 70;
6046 regnum
->fp_implementation_revision
= 71;
6048 if (info
.bfd_arch_info
!= NULL
6049 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6050 reg_names
= mips_tx39_reg_names
;
6052 reg_names
= mips_generic_reg_names
;
6054 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6055 replaced by gdbarch_read_pc? */
6056 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6057 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6058 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6059 set_gdbarch_num_regs (gdbarch
, num_regs
);
6060 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6061 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6062 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6063 tdep
->mips_processor_reg_names
= reg_names
;
6064 tdep
->regnum
= regnum
;
6070 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6071 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6072 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6073 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6074 tdep
->default_mask_address_p
= 0;
6075 set_gdbarch_long_bit (gdbarch
, 32);
6076 set_gdbarch_ptr_bit (gdbarch
, 32);
6077 set_gdbarch_long_long_bit (gdbarch
, 64);
6080 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6081 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6082 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6083 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6084 tdep
->default_mask_address_p
= 0;
6085 set_gdbarch_long_bit (gdbarch
, 32);
6086 set_gdbarch_ptr_bit (gdbarch
, 32);
6087 set_gdbarch_long_long_bit (gdbarch
, 64);
6089 case MIPS_ABI_EABI32
:
6090 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6091 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6092 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6093 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6094 tdep
->default_mask_address_p
= 0;
6095 set_gdbarch_long_bit (gdbarch
, 32);
6096 set_gdbarch_ptr_bit (gdbarch
, 32);
6097 set_gdbarch_long_long_bit (gdbarch
, 64);
6099 case MIPS_ABI_EABI64
:
6100 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6101 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6102 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6103 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6104 tdep
->default_mask_address_p
= 0;
6105 set_gdbarch_long_bit (gdbarch
, 64);
6106 set_gdbarch_ptr_bit (gdbarch
, 64);
6107 set_gdbarch_long_long_bit (gdbarch
, 64);
6110 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6111 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6112 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6113 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6114 tdep
->default_mask_address_p
= 0;
6115 set_gdbarch_long_bit (gdbarch
, 32);
6116 set_gdbarch_ptr_bit (gdbarch
, 32);
6117 set_gdbarch_long_long_bit (gdbarch
, 64);
6118 set_gdbarch_long_double_bit (gdbarch
, 128);
6119 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6122 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6123 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6124 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6125 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6126 tdep
->default_mask_address_p
= 0;
6127 set_gdbarch_long_bit (gdbarch
, 64);
6128 set_gdbarch_ptr_bit (gdbarch
, 64);
6129 set_gdbarch_long_long_bit (gdbarch
, 64);
6130 set_gdbarch_long_double_bit (gdbarch
, 128);
6131 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6134 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6137 /* GCC creates a pseudo-section whose name specifies the size of
6138 longs, since -mlong32 or -mlong64 may be used independent of
6139 other options. How those options affect pointer sizes is ABI and
6140 architecture dependent, so use them to override the default sizes
6141 set by the ABI. This table shows the relationship between ABI,
6142 -mlongXX, and size of pointers:
6144 ABI -mlongXX ptr bits
6145 --- -------- --------
6159 Note that for o32 and eabi32, pointers are always 32 bits
6160 regardless of any -mlongXX option. For all others, pointers and
6161 longs are the same, as set by -mlongXX or set by defaults. */
6163 if (info
.abfd
!= NULL
)
6167 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6170 set_gdbarch_long_bit (gdbarch
, long_bit
);
6174 case MIPS_ABI_EABI32
:
6179 case MIPS_ABI_EABI64
:
6180 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6183 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6188 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6189 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6192 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6193 flag in object files because to do so would make it impossible to
6194 link with libraries compiled without "-gp32". This is
6195 unnecessarily restrictive.
6197 We could solve this problem by adding "-gp32" multilibs to gcc,
6198 but to set this flag before gcc is built with such multilibs will
6199 break too many systems.''
6201 But even more unhelpfully, the default linker output target for
6202 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6203 for 64-bit programs - you need to change the ABI to change this,
6204 and not all gcc targets support that currently. Therefore using
6205 this flag to detect 32-bit mode would do the wrong thing given
6206 the current gcc - it would make GDB treat these 64-bit programs
6207 as 32-bit programs by default. */
6209 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6210 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6212 /* Add/remove bits from an address. The MIPS needs be careful to
6213 ensure that all 32 bit addresses are sign extended to 64 bits. */
6214 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6216 /* Unwind the frame. */
6217 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6218 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6219 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6221 /* Map debug register numbers onto internal register numbers. */
6222 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6223 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6224 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6225 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6226 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6227 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6229 /* MIPS version of CALL_DUMMY. */
6231 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6232 replaced by a command, and all targets will default to on stack
6233 (regardless of the stack's execute status). */
6234 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6235 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6237 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6238 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6239 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6241 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6242 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6244 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6246 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6248 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6249 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6250 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6252 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6254 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6256 if (mips_abi
== MIPS_ABI_N32
)
6257 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6258 else if (mips_abi
== MIPS_ABI_N64
)
6259 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6261 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6263 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6264 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6265 need to all be folded into the target vector. Since they are
6266 being used as guards for target_stopped_by_watchpoint, why not have
6267 target_stopped_by_watchpoint return the type of watchpoint that the code
6269 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6271 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6273 set_gdbarch_single_step_through_delay (gdbarch
,
6274 mips_single_step_through_delay
);
6276 /* Virtual tables. */
6277 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6279 mips_register_g_packet_guesses (gdbarch
);
6281 /* Hook in OS ABI-specific overrides, if they have been registered. */
6282 info
.tdep_info
= (void *) tdesc_data
;
6283 gdbarch_init_osabi (info
, gdbarch
);
6285 /* Unwind the frame. */
6286 dwarf2_append_unwinders (gdbarch
);
6287 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6288 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6289 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6290 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6291 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6292 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6293 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6297 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6298 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6300 /* Override the normal target description methods to handle our
6301 dual real and pseudo registers. */
6302 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6303 set_gdbarch_register_reggroup_p (gdbarch
,
6304 mips_tdesc_register_reggroup_p
);
6306 num_regs
= gdbarch_num_regs (gdbarch
);
6307 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6308 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6309 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6312 /* Add ABI-specific aliases for the registers. */
6313 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6314 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6315 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6316 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6318 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6319 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6320 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6322 /* Add some other standard aliases. */
6323 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6324 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6325 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6327 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6328 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6329 value_of_mips_user_reg
,
6330 &mips_numeric_register_aliases
[i
].regnum
);
6336 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6338 struct gdbarch_info info
;
6340 /* Force the architecture to update, and (if it's a MIPS architecture)
6341 mips_gdbarch_init will take care of the rest. */
6342 gdbarch_info_init (&info
);
6343 gdbarch_update_p (info
);
6346 /* Print out which MIPS ABI is in use. */
6349 show_mips_abi (struct ui_file
*file
,
6351 struct cmd_list_element
*ignored_cmd
,
6352 const char *ignored_value
)
6354 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6357 "The MIPS ABI is unknown because the current architecture "
6361 enum mips_abi global_abi
= global_mips_abi ();
6362 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6363 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6365 if (global_abi
== MIPS_ABI_UNKNOWN
)
6368 "The MIPS ABI is set automatically (currently \"%s\").\n",
6370 else if (global_abi
== actual_abi
)
6373 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6377 /* Probably shouldn't happen... */
6378 fprintf_filtered (file
,
6379 "The (auto detected) MIPS ABI \"%s\" is in use "
6380 "even though the user setting was \"%s\".\n",
6381 actual_abi_str
, mips_abi_strings
[global_abi
]);
6387 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6393 int ef_mips_32bitmode
;
6394 /* Determine the ISA. */
6395 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6413 /* Determine the size of a pointer. */
6414 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6415 fprintf_unfiltered (file
,
6416 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6418 fprintf_unfiltered (file
,
6419 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6421 fprintf_unfiltered (file
,
6422 "mips_dump_tdep: ef_mips_arch = %d\n",
6424 fprintf_unfiltered (file
,
6425 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6426 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6427 fprintf_unfiltered (file
,
6429 "mips_mask_address_p() %d (default %d)\n",
6430 mips_mask_address_p (tdep
),
6431 tdep
->default_mask_address_p
);
6433 fprintf_unfiltered (file
,
6434 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6435 MIPS_DEFAULT_FPU_TYPE
,
6436 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6437 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6438 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6440 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6441 MIPS_EABI (gdbarch
));
6442 fprintf_unfiltered (file
,
6443 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6444 MIPS_FPU_TYPE (gdbarch
),
6445 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6446 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6447 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6451 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6454 _initialize_mips_tdep (void)
6456 static struct cmd_list_element
*mipsfpulist
= NULL
;
6457 struct cmd_list_element
*c
;
6459 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6460 if (MIPS_ABI_LAST
+ 1
6461 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6462 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6464 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6466 mips_pdr_data
= register_objfile_data ();
6468 /* Create feature sets with the appropriate properties. The values
6469 are not important. */
6470 mips_tdesc_gp32
= allocate_target_description ();
6471 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6473 mips_tdesc_gp64
= allocate_target_description ();
6474 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6476 /* Add root prefix command for all "set mips"/"show mips" commands. */
6477 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6478 _("Various MIPS specific commands."),
6479 &setmipscmdlist
, "set mips ", 0, &setlist
);
6481 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6482 _("Various MIPS specific commands."),
6483 &showmipscmdlist
, "show mips ", 0, &showlist
);
6485 /* Allow the user to override the ABI. */
6486 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6487 &mips_abi_string
, _("\
6488 Set the MIPS ABI used by this program."), _("\
6489 Show the MIPS ABI used by this program."), _("\
6490 This option can be set to one of:\n\
6491 auto - the default ABI associated with the current binary\n\
6500 &setmipscmdlist
, &showmipscmdlist
);
6502 /* Let the user turn off floating point and set the fence post for
6503 heuristic_proc_start. */
6505 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6506 _("Set use of MIPS floating-point coprocessor."),
6507 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6508 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6509 _("Select single-precision MIPS floating-point coprocessor."),
6511 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6512 _("Select double-precision MIPS floating-point coprocessor."),
6514 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6515 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6516 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6517 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6518 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6519 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6520 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6521 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6522 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6523 _("Select MIPS floating-point coprocessor automatically."),
6525 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6526 _("Show current use of MIPS floating-point coprocessor target."),
6529 /* We really would like to have both "0" and "unlimited" work, but
6530 command.c doesn't deal with that. So make it a var_zinteger
6531 because the user can always use "999999" or some such for unlimited. */
6532 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6533 &heuristic_fence_post
, _("\
6534 Set the distance searched for the start of a function."), _("\
6535 Show the distance searched for the start of a function."), _("\
6536 If you are debugging a stripped executable, GDB needs to search through the\n\
6537 program for the start of a function. This command sets the distance of the\n\
6538 search. The only need to set it is when debugging a stripped executable."),
6539 reinit_frame_cache_sfunc
,
6540 NULL
, /* FIXME: i18n: The distance searched for
6541 the start of a function is %s. */
6542 &setlist
, &showlist
);
6544 /* Allow the user to control whether the upper bits of 64-bit
6545 addresses should be zeroed. */
6546 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6547 &mask_address_var
, _("\
6548 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6549 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6550 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6551 allow GDB to determine the correct value."),
6552 NULL
, show_mask_address
,
6553 &setmipscmdlist
, &showmipscmdlist
);
6555 /* Allow the user to control the size of 32 bit registers within the
6556 raw remote packet. */
6557 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6558 &mips64_transfers_32bit_regs_p
, _("\
6559 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6561 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6563 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6564 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6565 64 bits for others. Use \"off\" to disable compatibility mode"),
6566 set_mips64_transfers_32bit_regs
,
6567 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6568 MIPS target that transfers 32-bit
6569 quantities is %s. */
6570 &setlist
, &showlist
);
6572 /* Debug this files internals. */
6573 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6575 Set mips debugging."), _("\
6576 Show mips debugging."), _("\
6577 When non-zero, mips specific debugging is enabled."),
6579 NULL
, /* FIXME: i18n: Mips debugging is
6581 &setdebuglist
, &showdebuglist
);