1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
54 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE
= 4,
65 MIPS_FPU_DOUBLE_REGSIZE
= 8
69 static const char *mips_abi_string
;
71 static const char *mips_abi_strings
[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc
;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto
[] = "auto";
93 static const char size_32
[] = "32";
94 static const char size_64
[] = "64";
96 static const char *size_enums
[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int mips_default_saved_regsize
;
135 int mips_fp_register_double
;
136 int mips_default_stack_argsize
;
137 int default_mask_address_p
;
138 /* Is the target using 64-bit raw integer registers but only
139 storing a left-aligned 32-bit value in each? */
140 int mips64_transfers_32bit_regs_p
;
141 /* Indexes for various registers. IRIX and embedded have
142 different values. This contains the "public" fields. Don't
143 add any that do not need to be public. */
144 const struct mips_regnum
*regnum
;
147 const struct mips_regnum
*
148 mips_regnum (struct gdbarch
*gdbarch
)
150 return gdbarch_tdep (gdbarch
)->regnum
;
154 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
156 return mips_regnum (gdbarch
)->fp0
+ 12;
159 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
160 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
162 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
164 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
166 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
168 /* Return the currently configured (or set) saved register size. */
170 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
172 static const char *mips_saved_regsize_string
= size_auto
;
174 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
176 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
177 functions to test, set, or clear bit 0 of addresses. */
180 is_mips16_addr (CORE_ADDR addr
)
186 make_mips16_addr (CORE_ADDR addr
)
192 unmake_mips16_addr (CORE_ADDR addr
)
194 return ((addr
) & ~1);
197 /* Return the contents of register REGNUM as a signed integer. */
200 read_signed_register (int regnum
)
202 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
203 deprecated_read_register_gen (regnum
, buf
);
204 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
208 read_signed_register_pid (int regnum
, ptid_t ptid
)
213 if (ptid_equal (ptid
, inferior_ptid
))
214 return read_signed_register (regnum
);
216 save_ptid
= inferior_ptid
;
218 inferior_ptid
= ptid
;
220 retval
= read_signed_register (regnum
);
222 inferior_ptid
= save_ptid
;
227 /* Return the MIPS ABI associated with GDBARCH. */
229 mips_abi (struct gdbarch
*gdbarch
)
231 return gdbarch_tdep (gdbarch
)->mips_abi
;
235 mips_regsize (struct gdbarch
*gdbarch
)
237 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
238 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
242 mips_saved_regsize (void)
244 if (mips_saved_regsize_string
== size_auto
)
245 return MIPS_DEFAULT_SAVED_REGSIZE
;
246 else if (mips_saved_regsize_string
== size_64
)
248 else /* if (mips_saved_regsize_string == size_32) */
252 /* Functions for setting and testing a bit in a minimal symbol that
253 marks it as 16-bit function. The MSB of the minimal symbol's
254 "info" field is used for this purpose.
256 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
257 i.e. refers to a 16-bit function, and sets a "special" bit in a
258 minimal symbol to mark it as a 16-bit function
260 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
263 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
265 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
267 MSYMBOL_INFO (msym
) = (char *)
268 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
269 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
274 msymbol_is_special (struct minimal_symbol
*msym
)
276 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
279 /* XFER a value from the big/little/left end of the register.
280 Depending on the size of the value it might occupy the entire
281 register or just part of it. Make an allowance for this, aligning
282 things accordingly. */
285 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
286 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
289 bfd_byte reg
[MAX_REGISTER_SIZE
];
291 gdb_assert (reg_num
>= NUM_REGS
);
292 /* Need to transfer the left or right part of the register, based on
293 the targets byte order. */
297 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
299 case BFD_ENDIAN_LITTLE
:
302 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
306 internal_error (__FILE__
, __LINE__
, "bad switch");
309 fprintf_unfiltered (gdb_stderr
,
310 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
311 reg_num
, reg_offset
, buf_offset
, length
);
312 if (mips_debug
&& out
!= NULL
)
315 fprintf_unfiltered (gdb_stdlog
, "out ");
316 for (i
= 0; i
< length
; i
++)
317 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
320 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
322 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
323 if (mips_debug
&& in
!= NULL
)
326 fprintf_unfiltered (gdb_stdlog
, "in ");
327 for (i
= 0; i
< length
; i
++)
328 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
331 fprintf_unfiltered (gdb_stdlog
, "\n");
334 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
335 compatiblity mode. A return value of 1 means that we have
336 physical 64-bit registers, but should treat them as 32-bit registers. */
339 mips2_fp_compat (void)
341 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
343 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
347 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
348 in all the places we deal with FP registers. PR gdb/413. */
349 /* Otherwise check the FR bit in the status register - it controls
350 the FP compatiblity mode. If it is clear we are in compatibility
352 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
359 /* Indicate that the ABI makes use of double-precision registers
360 provided by the FPU (rather than combining pairs of registers to
361 form double-precision values). See also MIPS_FPU_TYPE. */
362 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
364 /* The amount of space reserved on the stack for registers. This is
365 different to MIPS_SAVED_REGSIZE as it determines the alignment of
366 data allocated after the registers have run out. */
368 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
370 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
372 static const char *mips_stack_argsize_string
= size_auto
;
375 mips_stack_argsize (void)
377 if (mips_stack_argsize_string
== size_auto
)
378 return MIPS_DEFAULT_STACK_ARGSIZE
;
379 else if (mips_stack_argsize_string
== size_64
)
381 else /* if (mips_stack_argsize_string == size_32) */
385 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
387 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
389 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
390 struct frame_info
*, int);
392 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
394 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
396 static int mips_set_processor_type (char *);
398 static void mips_show_processor_type_command (char *, int);
400 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
402 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
403 struct frame_info
*next_frame
,
406 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
407 mips_extra_func_info_t proc_desc
);
409 static struct type
*mips_float_register_type (void);
410 static struct type
*mips_double_register_type (void);
412 /* This value is the model of MIPS in use. It is derived from the value
413 of the PrID register. */
415 char *mips_processor_type
;
417 char *tmp_mips_processor_type
;
419 /* The list of available "set mips " and "show mips " commands */
421 static struct cmd_list_element
*setmipscmdlist
= NULL
;
422 static struct cmd_list_element
*showmipscmdlist
= NULL
;
424 /* A set of original names, to be used when restoring back to generic
425 registers from a specific set. */
426 static char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
428 /* Integer registers 0 thru 31 are handled explicitly by
429 mips_register_name(). Processor specific registers 32 and above
430 are listed in the sets of register names assigned to
431 mips_processor_reg_names. */
432 static char **mips_processor_reg_names
= mips_generic_reg_names
;
434 /* Return the name of the register corresponding to REGNO. */
436 mips_register_name (int regno
)
438 /* GPR names for all ABIs other than n32/n64. */
439 static char *mips_gpr_names
[] = {
440 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
441 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
442 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
443 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
446 /* GPR names for n32 and n64 ABIs. */
447 static char *mips_n32_n64_gpr_names
[] = {
448 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
449 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
450 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
451 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
454 enum mips_abi abi
= mips_abi (current_gdbarch
);
456 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
457 don't make the raw register names visible. */
458 int rawnum
= regno
% NUM_REGS
;
459 if (regno
< NUM_REGS
)
462 /* The MIPS integer registers are always mapped from 0 to 31. The
463 names of the registers (which reflects the conventions regarding
464 register use) vary depending on the ABI. */
465 if (0 <= rawnum
&& rawnum
< 32)
467 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
468 return mips_n32_n64_gpr_names
[rawnum
];
470 return mips_gpr_names
[rawnum
];
472 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
473 return mips_processor_reg_names
[rawnum
- 32];
475 internal_error (__FILE__
, __LINE__
,
476 "mips_register_name: bad register number %d", rawnum
);
480 /* Names of IDT R3041 registers. */
482 char *mips_r3041_reg_names
[] = {
483 "sr", "lo", "hi", "bad", "cause","pc",
484 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
485 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
486 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
487 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
488 "fsr", "fir", "",/*"fp"*/ "",
489 "", "", "bus", "ccfg", "", "", "", "",
490 "", "", "port", "cmp", "", "", "epc", "prid",
493 /* Names of IDT R3051 registers. */
495 char *mips_r3051_reg_names
[] = {
496 "sr", "lo", "hi", "bad", "cause","pc",
497 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
498 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
499 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
500 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
501 "fsr", "fir", ""/*"fp"*/, "",
502 "inx", "rand", "elo", "", "ctxt", "", "", "",
503 "", "", "ehi", "", "", "", "epc", "prid",
506 /* Names of IDT R3081 registers. */
508 char *mips_r3081_reg_names
[] = {
509 "sr", "lo", "hi", "bad", "cause","pc",
510 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
511 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
512 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
513 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
514 "fsr", "fir", ""/*"fp"*/, "",
515 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
516 "", "", "ehi", "", "", "", "epc", "prid",
519 /* Names of LSI 33k registers. */
521 char *mips_lsi33k_reg_names
[] = {
522 "epc", "hi", "lo", "sr", "cause","badvaddr",
523 "dcic", "bpc", "bda", "", "", "", "", "",
524 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "", "", "", "", "", "",
528 "", "", "", "", "", "", "", "",
529 "", "", "", "", "", "", "", "",
535 } mips_processor_type_table
[] = {
536 { "generic", mips_generic_reg_names
},
537 { "r3041", mips_r3041_reg_names
},
538 { "r3051", mips_r3051_reg_names
},
539 { "r3071", mips_r3081_reg_names
},
540 { "r3081", mips_r3081_reg_names
},
541 { "lsi33k", mips_lsi33k_reg_names
},
546 /* Return the groups that a MIPS register can be categorised into. */
549 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
550 struct reggroup
*reggroup
)
555 int rawnum
= regnum
% NUM_REGS
;
556 int pseudo
= regnum
/ NUM_REGS
;
557 if (reggroup
== all_reggroup
)
559 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
560 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
561 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
562 (gdbarch), as not all architectures are multi-arch. */
563 raw_p
= rawnum
< NUM_REGS
;
564 if (REGISTER_NAME (regnum
) == NULL
565 || REGISTER_NAME (regnum
)[0] == '\0')
567 if (reggroup
== float_reggroup
)
568 return float_p
&& pseudo
;
569 if (reggroup
== vector_reggroup
)
570 return vector_p
&& pseudo
;
571 if (reggroup
== general_reggroup
)
572 return (!vector_p
&& !float_p
) && pseudo
;
573 /* Save the pseudo registers. Need to make certain that any code
574 extracting register values from a saved register cache also uses
576 if (reggroup
== save_reggroup
)
577 return raw_p
&& pseudo
;
578 /* Restore the same pseudo register. */
579 if (reggroup
== restore_reggroup
)
580 return raw_p
&& pseudo
;
584 /* Map the symbol table registers which live in the range [1 *
585 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
590 int cookednum
, void *buf
)
592 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
593 return regcache_raw_read (regcache
, cookednum
% NUM_REGS
, buf
);
597 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
598 int cookednum
, const void *buf
)
600 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
601 return regcache_raw_write (regcache
, cookednum
% NUM_REGS
, buf
);
604 /* Table to translate MIPS16 register field to actual register number. */
605 static int mips16_to_32_reg
[8] =
606 {16, 17, 2, 3, 4, 5, 6, 7};
608 /* Heuristic_proc_start may hunt through the text section for a long
609 time across a 2400 baud serial line. Allows the user to limit this
612 static unsigned int heuristic_fence_post
= 0;
614 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
615 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
616 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
617 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
618 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
619 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
620 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
621 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
622 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
623 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
624 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
625 this will corrupt pdr.iline. Fortunately we don't use it. */
626 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
627 #define _PROC_MAGIC_ 0x0F0F0F0F
628 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
629 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
631 struct linked_proc_info
633 struct mips_extra_func_info info
;
634 struct linked_proc_info
*next
;
636 *linked_proc_desc_table
= NULL
;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p
= 0;
645 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
646 struct cmd_list_element
*c
)
648 struct gdbarch_info info
;
649 gdbarch_info_init (&info
);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info
))
655 mips64_transfers_32bit_regs_p
= 0;
656 error ("32-bit compatibility mode not supported");
660 /* Convert between RAW and VIRTUAL registers. The RAW register size
661 defines the remote-gdb packet. */
664 mips_register_convertible (int reg_nr
)
666 if (gdbarch_tdep (current_gdbarch
)->mips64_transfers_32bit_regs_p
)
669 return (register_size (current_gdbarch
, reg_nr
) > register_size (current_gdbarch
, reg_nr
));
673 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
674 char *raw_buf
, char *virt_buf
)
676 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
678 raw_buf
+ (register_size (current_gdbarch
, n
) - TYPE_LENGTH (virtual_type
)),
679 TYPE_LENGTH (virtual_type
));
683 TYPE_LENGTH (virtual_type
));
687 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
688 const char *virt_buf
, char *raw_buf
)
690 memset (raw_buf
, 0, register_size (current_gdbarch
, n
));
691 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
692 memcpy (raw_buf
+ (register_size (current_gdbarch
, n
) - TYPE_LENGTH (virtual_type
)),
694 TYPE_LENGTH (virtual_type
));
698 TYPE_LENGTH (virtual_type
));
702 mips_convert_register_p (int regnum
, struct type
*type
)
704 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
705 && register_size (current_gdbarch
, regnum
) == 4
706 && (regnum
) >= mips_regnum (current_gdbarch
)->fp0
&& (regnum
) < mips_regnum (current_gdbarch
)->fp0
+ 32
707 && TYPE_CODE(type
) == TYPE_CODE_FLT
708 && TYPE_LENGTH(type
) == 8);
712 mips_register_to_value (struct frame_info
*frame
, int regnum
,
713 struct type
*type
, void *to
)
715 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
716 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
720 mips_value_to_register (struct frame_info
*frame
, int regnum
,
721 struct type
*type
, const void *from
)
723 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
724 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
727 /* Return the GDB type object for the "standard" data type of data in
731 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
733 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
734 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
735 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
737 /* The floating-point registers raw, or cooked, always match
738 mips_regsize(), and also map 1:1, byte for byte. */
739 switch (gdbarch_byte_order (gdbarch
))
742 if (mips_regsize (gdbarch
) == 4)
743 return builtin_type_ieee_single_big
;
745 return builtin_type_ieee_double_big
;
746 case BFD_ENDIAN_LITTLE
:
747 if (mips_regsize (gdbarch
) == 4)
748 return builtin_type_ieee_single_little
;
750 return builtin_type_ieee_double_little
;
751 case BFD_ENDIAN_UNKNOWN
:
753 internal_error (__FILE__
, __LINE__
, "bad switch");
756 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
757 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
758 /* The pseudo/cooked view of the embedded registers is always
759 32-bit. The raw view is handled below. */
760 return builtin_type_int32
;
761 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
762 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
763 /* The target, while using a 64-bit register buffer, is only
764 transfering 32-bits of each integer register. Reflect this in
765 the cooked/pseudo register value. */
766 return builtin_type_int32
;
767 else if (mips_regsize (gdbarch
) == 8)
769 return builtin_type_int64
;
772 return builtin_type_int32
;
775 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
780 return read_signed_register (SP_REGNUM
);
783 /* Should the upper word of 64-bit addresses be zeroed? */
784 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
787 mips_mask_address_p (void)
789 switch (mask_address_var
)
791 case AUTO_BOOLEAN_TRUE
:
793 case AUTO_BOOLEAN_FALSE
:
796 case AUTO_BOOLEAN_AUTO
:
797 return MIPS_DEFAULT_MASK_ADDRESS_P
;
799 internal_error (__FILE__
, __LINE__
,
800 "mips_mask_address_p: bad switch");
806 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
808 switch (mask_address_var
)
810 case AUTO_BOOLEAN_TRUE
:
811 printf_filtered ("The 32 bit mips address mask is enabled\n");
813 case AUTO_BOOLEAN_FALSE
:
814 printf_filtered ("The 32 bit mips address mask is disabled\n");
816 case AUTO_BOOLEAN_AUTO
:
817 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
818 mips_mask_address_p () ? "enabled" : "disabled");
821 internal_error (__FILE__
, __LINE__
,
822 "show_mask_address: bad switch");
827 /* Should call_function allocate stack space for a struct return? */
830 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
832 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
836 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
838 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
841 /* Should call_function pass struct by reference?
842 For each architecture, structs are passed either by
843 value or by reference, depending on their size. */
846 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
848 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
849 int len
= TYPE_LENGTH (check_typedef (type
));
851 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
852 return (len
> MIPS_SAVED_REGSIZE
);
858 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
860 return 0; /* Assumption: N32/N64 never passes struct by ref. */
864 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
866 return 0; /* Assumption: O32/O64 never passes struct by ref. */
869 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
872 pc_is_mips16 (bfd_vma memaddr
)
874 struct minimal_symbol
*sym
;
876 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
877 if (is_mips16_addr (memaddr
))
880 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
881 the high bit of the info field. Use this to decide if the function is
882 MIPS16 or normal MIPS. */
883 sym
= lookup_minimal_symbol_by_pc (memaddr
);
885 return msymbol_is_special (sym
);
890 /* MIPS believes that the PC has a sign extended value. Perhaphs the
891 all registers should be sign extended for simplicity? */
894 mips_read_pc (ptid_t ptid
)
896 return read_signed_register_pid (PC_REGNUM
, ptid
);
899 /* This returns the PC of the first inst after the prologue. If we can't
900 find the prologue, then return 0. */
903 after_prologue (CORE_ADDR pc
,
904 mips_extra_func_info_t proc_desc
)
906 struct symtab_and_line sal
;
907 CORE_ADDR func_addr
, func_end
;
909 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
910 to read the stack pointer from the current machine state, because
911 the current machine state has nothing to do with the information
912 we need from the proc_desc; and the process may or may not exist
915 proc_desc
= find_proc_desc (pc
, NULL
, 0);
919 /* If function is frameless, then we need to do it the hard way. I
920 strongly suspect that frameless always means prologueless... */
921 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
922 && PROC_FRAME_OFFSET (proc_desc
) == 0)
926 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
927 return 0; /* Unknown */
929 sal
= find_pc_line (func_addr
, 0);
931 if (sal
.end
< func_end
)
934 /* The line after the prologue is after the end of the function. In this
935 case, tell the caller to find the prologue the hard way. */
940 /* Decode a MIPS32 instruction that saves a register in the stack, and
941 set the appropriate bit in the general register mask or float register mask
942 to indicate which register is saved. This is a helper function
943 for mips_find_saved_regs. */
946 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
947 unsigned long *float_mask
)
951 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
952 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
953 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
955 /* It might be possible to use the instruction to
956 find the offset, rather than the code below which
957 is based on things being in a certain order in the
958 frame, but figuring out what the instruction's offset
959 is relative to might be a little tricky. */
960 reg
= (inst
& 0x001f0000) >> 16;
961 *gen_mask
|= (1 << reg
);
963 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
964 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
965 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
968 reg
= ((inst
& 0x001f0000) >> 16);
969 *float_mask
|= (1 << reg
);
973 /* Decode a MIPS16 instruction that saves a register in the stack, and
974 set the appropriate bit in the general register or float register mask
975 to indicate which register is saved. This is a helper function
976 for mips_find_saved_regs. */
979 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
981 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
983 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
984 *gen_mask
|= (1 << reg
);
986 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
988 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
989 *gen_mask
|= (1 << reg
);
991 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
992 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
993 *gen_mask
|= (1 << RA_REGNUM
);
997 /* Fetch and return instruction from the specified location. If the PC
998 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1001 mips_fetch_instruction (CORE_ADDR addr
)
1003 char buf
[MIPS_INSTLEN
];
1007 if (pc_is_mips16 (addr
))
1009 instlen
= MIPS16_INSTLEN
;
1010 addr
= unmake_mips16_addr (addr
);
1013 instlen
= MIPS_INSTLEN
;
1014 status
= read_memory_nobpt (addr
, buf
, instlen
);
1016 memory_error (status
, addr
);
1017 return extract_unsigned_integer (buf
, instlen
);
1021 /* These the fields of 32 bit mips instructions */
1022 #define mips32_op(x) (x >> 26)
1023 #define itype_op(x) (x >> 26)
1024 #define itype_rs(x) ((x >> 21) & 0x1f)
1025 #define itype_rt(x) ((x >> 16) & 0x1f)
1026 #define itype_immediate(x) (x & 0xffff)
1028 #define jtype_op(x) (x >> 26)
1029 #define jtype_target(x) (x & 0x03ffffff)
1031 #define rtype_op(x) (x >> 26)
1032 #define rtype_rs(x) ((x >> 21) & 0x1f)
1033 #define rtype_rt(x) ((x >> 16) & 0x1f)
1034 #define rtype_rd(x) ((x >> 11) & 0x1f)
1035 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1036 #define rtype_funct(x) (x & 0x3f)
1039 mips32_relative_offset (unsigned long inst
)
1042 x
= itype_immediate (inst
);
1043 if (x
& 0x8000) /* sign bit set */
1045 x
|= 0xffff0000; /* sign extension */
1051 /* Determine whate to set a single step breakpoint while considering
1052 branch prediction */
1054 mips32_next_pc (CORE_ADDR pc
)
1058 inst
= mips_fetch_instruction (pc
);
1059 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1061 if (itype_op (inst
) >> 2 == 5)
1062 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1064 op
= (itype_op (inst
) & 0x03);
1074 goto greater_branch
;
1079 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1080 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1082 int tf
= itype_rt (inst
) & 0x01;
1083 int cnum
= itype_rt (inst
) >> 2;
1084 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1085 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1087 if (((cond
>> cnum
) & 0x01) == tf
)
1088 pc
+= mips32_relative_offset (inst
) + 4;
1093 pc
+= 4; /* Not a branch, next instruction is easy */
1096 { /* This gets way messy */
1098 /* Further subdivide into SPECIAL, REGIMM and other */
1099 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1101 case 0: /* SPECIAL */
1102 op
= rtype_funct (inst
);
1107 /* Set PC to that address */
1108 pc
= read_signed_register (rtype_rs (inst
));
1114 break; /* end SPECIAL */
1115 case 1: /* REGIMM */
1117 op
= itype_rt (inst
); /* branch condition */
1122 case 16: /* BLTZAL */
1123 case 18: /* BLTZALL */
1125 if (read_signed_register (itype_rs (inst
)) < 0)
1126 pc
+= mips32_relative_offset (inst
) + 4;
1128 pc
+= 8; /* after the delay slot */
1132 case 17: /* BGEZAL */
1133 case 19: /* BGEZALL */
1134 greater_equal_branch
:
1135 if (read_signed_register (itype_rs (inst
)) >= 0)
1136 pc
+= mips32_relative_offset (inst
) + 4;
1138 pc
+= 8; /* after the delay slot */
1140 /* All of the other instructions in the REGIMM category */
1145 break; /* end REGIMM */
1150 reg
= jtype_target (inst
) << 2;
1151 /* Upper four bits get never changed... */
1152 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1155 /* FIXME case JALX : */
1158 reg
= jtype_target (inst
) << 2;
1159 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1160 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1162 break; /* The new PC will be alternate mode */
1163 case 4: /* BEQ, BEQL */
1165 if (read_signed_register (itype_rs (inst
)) ==
1166 read_signed_register (itype_rt (inst
)))
1167 pc
+= mips32_relative_offset (inst
) + 4;
1171 case 5: /* BNE, BNEL */
1173 if (read_signed_register (itype_rs (inst
)) !=
1174 read_signed_register (itype_rt (inst
)))
1175 pc
+= mips32_relative_offset (inst
) + 4;
1179 case 6: /* BLEZ, BLEZL */
1181 if (read_signed_register (itype_rs (inst
) <= 0))
1182 pc
+= mips32_relative_offset (inst
) + 4;
1188 greater_branch
: /* BGTZ, BGTZL */
1189 if (read_signed_register (itype_rs (inst
) > 0))
1190 pc
+= mips32_relative_offset (inst
) + 4;
1197 } /* mips32_next_pc */
1199 /* Decoding the next place to set a breakpoint is irregular for the
1200 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1201 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1202 We dont want to set a single step instruction on the extend instruction
1206 /* Lots of mips16 instruction formats */
1207 /* Predicting jumps requires itype,ritype,i8type
1208 and their extensions extItype,extritype,extI8type
1210 enum mips16_inst_fmts
1212 itype
, /* 0 immediate 5,10 */
1213 ritype
, /* 1 5,3,8 */
1214 rrtype
, /* 2 5,3,3,5 */
1215 rritype
, /* 3 5,3,3,5 */
1216 rrrtype
, /* 4 5,3,3,3,2 */
1217 rriatype
, /* 5 5,3,3,1,4 */
1218 shifttype
, /* 6 5,3,3,3,2 */
1219 i8type
, /* 7 5,3,8 */
1220 i8movtype
, /* 8 5,3,3,5 */
1221 i8mov32rtype
, /* 9 5,3,5,3 */
1222 i64type
, /* 10 5,3,8 */
1223 ri64type
, /* 11 5,3,3,5 */
1224 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1225 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1226 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1227 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1228 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1229 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1230 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1231 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1232 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1233 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1235 /* I am heaping all the fields of the formats into one structure and
1236 then, only the fields which are involved in instruction extension */
1240 unsigned int regx
; /* Function in i8 type */
1245 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1246 for the bits which make up the immediatate extension. */
1249 extended_offset (unsigned int extension
)
1252 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1254 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1256 value
|= extension
& 0x01f; /* extract 4:0 */
1260 /* Only call this function if you know that this is an extendable
1261 instruction, It wont malfunction, but why make excess remote memory references?
1262 If the immediate operands get sign extended or somthing, do it after
1263 the extension is performed.
1265 /* FIXME: Every one of these cases needs to worry about sign extension
1266 when the offset is to be used in relative addressing */
1270 fetch_mips_16 (CORE_ADDR pc
)
1273 pc
&= 0xfffffffe; /* clear the low order bit */
1274 target_read_memory (pc
, buf
, 2);
1275 return extract_unsigned_integer (buf
, 2);
1279 unpack_mips16 (CORE_ADDR pc
,
1280 unsigned int extension
,
1282 enum mips16_inst_fmts insn_format
,
1283 struct upk_mips16
*upk
)
1288 switch (insn_format
)
1295 value
= extended_offset (extension
);
1296 value
= value
<< 11; /* rom for the original value */
1297 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1301 value
= inst
& 0x7ff;
1302 /* FIXME : Consider sign extension */
1311 { /* A register identifier and an offset */
1312 /* Most of the fields are the same as I type but the
1313 immediate value is of a different length */
1317 value
= extended_offset (extension
);
1318 value
= value
<< 8; /* from the original instruction */
1319 value
|= inst
& 0xff; /* eleven bits from instruction */
1320 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1321 if (value
& 0x4000) /* test the sign bit , bit 26 */
1323 value
&= ~0x3fff; /* remove the sign bit */
1329 value
= inst
& 0xff; /* 8 bits */
1330 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1331 /* FIXME: Do sign extension , this format needs it */
1332 if (value
& 0x80) /* THIS CONFUSES ME */
1334 value
&= 0xef; /* remove the sign bit */
1344 unsigned long value
;
1345 unsigned int nexthalf
;
1346 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1347 value
= value
<< 16;
1348 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1356 internal_error (__FILE__
, __LINE__
,
1359 upk
->offset
= offset
;
1366 add_offset_16 (CORE_ADDR pc
, int offset
)
1368 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1372 extended_mips16_next_pc (CORE_ADDR pc
,
1373 unsigned int extension
,
1376 int op
= (insn
>> 11);
1379 case 2: /* Branch */
1382 struct upk_mips16 upk
;
1383 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1384 offset
= upk
.offset
;
1390 pc
+= (offset
<< 1) + 2;
1393 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1395 struct upk_mips16 upk
;
1396 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1397 pc
= add_offset_16 (pc
, upk
.offset
);
1398 if ((insn
>> 10) & 0x01) /* Exchange mode */
1399 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1406 struct upk_mips16 upk
;
1408 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1409 reg
= read_signed_register (upk
.regx
);
1411 pc
+= (upk
.offset
<< 1) + 2;
1418 struct upk_mips16 upk
;
1420 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1421 reg
= read_signed_register (upk
.regx
);
1423 pc
+= (upk
.offset
<< 1) + 2;
1428 case 12: /* I8 Formats btez btnez */
1430 struct upk_mips16 upk
;
1432 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1433 /* upk.regx contains the opcode */
1434 reg
= read_signed_register (24); /* Test register is 24 */
1435 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1436 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1437 /* pc = add_offset_16(pc,upk.offset) ; */
1438 pc
+= (upk
.offset
<< 1) + 2;
1443 case 29: /* RR Formats JR, JALR, JALR-RA */
1445 struct upk_mips16 upk
;
1446 /* upk.fmt = rrtype; */
1451 upk
.regx
= (insn
>> 8) & 0x07;
1452 upk
.regy
= (insn
>> 5) & 0x07;
1460 break; /* Function return instruction */
1466 break; /* BOGUS Guess */
1468 pc
= read_signed_register (reg
);
1475 /* This is an instruction extension. Fetch the real instruction
1476 (which follows the extension) and decode things based on
1480 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1493 mips16_next_pc (CORE_ADDR pc
)
1495 unsigned int insn
= fetch_mips_16 (pc
);
1496 return extended_mips16_next_pc (pc
, 0, insn
);
1499 /* The mips_next_pc function supports single_step when the remote
1500 target monitor or stub is not developed enough to do a single_step.
1501 It works by decoding the current instruction and predicting where a
1502 branch will go. This isnt hard because all the data is available.
1503 The MIPS32 and MIPS16 variants are quite different */
1505 mips_next_pc (CORE_ADDR pc
)
1508 return mips16_next_pc (pc
);
1510 return mips32_next_pc (pc
);
1513 /* Set up the 'saved_regs' array. This is a data structure containing
1514 the addresses on the stack where each register has been saved, for
1515 each stack frame. Registers that have not been saved will have
1516 zero here. The stack pointer register is special: rather than the
1517 address where the stack register has been saved,
1518 saved_regs[SP_REGNUM] will have the actual value of the previous
1519 frame's stack register. */
1522 mips_find_saved_regs (struct frame_info
*fci
)
1525 /* r0 bit means kernel trap */
1527 /* What registers have been saved? Bitmasks. */
1528 unsigned long gen_mask
, float_mask
;
1529 mips_extra_func_info_t proc_desc
;
1531 CORE_ADDR
*saved_regs
;
1533 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1535 saved_regs
= frame_saved_regs_zalloc (fci
);
1537 /* If it is the frame for sigtramp, the saved registers are located
1538 in a sigcontext structure somewhere on the stack. If the stack
1539 layout for sigtramp changes we might have to change these
1540 constants and the companion fixup_sigtramp in mdebugread.c */
1541 #ifndef SIGFRAME_BASE
1542 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1543 above the sigtramp frame. */
1544 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1545 /* FIXME! Are these correct?? */
1546 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1547 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1548 #define SIGFRAME_FPREGSAVE_OFF \
1549 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1551 #ifndef SIGFRAME_REG_SIZE
1552 /* FIXME! Is this correct?? */
1553 #define SIGFRAME_REG_SIZE mips_regsize (current_gdbarch)
1555 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1557 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1559 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1560 + ireg
* SIGFRAME_REG_SIZE
);
1561 set_reg_offset (saved_regs
, ireg
, reg_position
);
1563 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1565 CORE_ADDR reg_position
= (get_frame_base (fci
)
1566 + SIGFRAME_FPREGSAVE_OFF
1567 + ireg
* SIGFRAME_REG_SIZE
);
1568 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1571 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1572 /* SP_REGNUM, contains the value and not the address. */
1573 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1577 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1578 if (proc_desc
== NULL
)
1579 /* I'm not sure how/whether this can happen. Normally when we
1580 can't find a proc_desc, we "synthesize" one using
1581 heuristic_proc_desc and set the saved_regs right away. */
1584 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1585 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1586 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1588 if (/* In any frame other than the innermost or a frame interrupted
1589 by a signal, we assume that all registers have been saved.
1590 This assumes that all register saves in a function happen
1591 before the first function call. */
1592 (get_next_frame (fci
) == NULL
1593 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1595 /* In a dummy frame we know exactly where things are saved. */
1596 && !PROC_DESC_IS_DUMMY (proc_desc
)
1598 /* Don't bother unless we are inside a function prologue.
1599 Outside the prologue, we know where everything is. */
1601 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1603 /* Not sure exactly what kernel_trap means, but if it means the
1604 kernel saves the registers without a prologue doing it, we
1605 better not examine the prologue to see whether registers
1606 have been saved yet. */
1609 /* We need to figure out whether the registers that the
1610 proc_desc claims are saved have been saved yet. */
1614 /* Bitmasks; set if we have found a save for the register. */
1615 unsigned long gen_save_found
= 0;
1616 unsigned long float_save_found
= 0;
1619 /* If the address is odd, assume this is MIPS16 code. */
1620 addr
= PROC_LOW_ADDR (proc_desc
);
1621 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1623 /* Scan through this function's instructions preceding the
1624 current PC, and look for those that save registers. */
1625 while (addr
< get_frame_pc (fci
))
1627 inst
= mips_fetch_instruction (addr
);
1628 if (pc_is_mips16 (addr
))
1629 mips16_decode_reg_save (inst
, &gen_save_found
);
1631 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1634 gen_mask
= gen_save_found
;
1635 float_mask
= float_save_found
;
1638 /* Fill in the offsets for the registers which gen_mask says were
1641 CORE_ADDR reg_position
= (get_frame_base (fci
)
1642 + PROC_REG_OFFSET (proc_desc
));
1643 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1644 if (gen_mask
& 0x80000000)
1646 set_reg_offset (saved_regs
, ireg
, reg_position
);
1647 reg_position
-= MIPS_SAVED_REGSIZE
;
1651 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1652 order of that normally used by gcc. Therefore, we have to fetch
1653 the first instruction of the function, and if it's an entry
1654 instruction that saves $s0 or $s1, correct their saved addresses. */
1655 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1657 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1658 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1662 int sreg_count
= (inst
>> 6) & 3;
1664 /* Check if the ra register was pushed on the stack. */
1665 CORE_ADDR reg_position
= (get_frame_base (fci
)
1666 + PROC_REG_OFFSET (proc_desc
));
1668 reg_position
-= MIPS_SAVED_REGSIZE
;
1670 /* Check if the s0 and s1 registers were pushed on the
1672 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1674 set_reg_offset (saved_regs
, reg
, reg_position
);
1675 reg_position
-= MIPS_SAVED_REGSIZE
;
1680 /* Fill in the offsets for the registers which float_mask says were
1683 CORE_ADDR reg_position
= (get_frame_base (fci
)
1684 + PROC_FREG_OFFSET (proc_desc
));
1686 /* Fill in the offsets for the float registers which float_mask
1688 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1689 if (float_mask
& 0x80000000)
1691 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1693 /* On a big endian 32 bit ABI, floating point registers
1694 are paired to form doubles such that the most
1695 significant part is in $f[N+1] and the least
1696 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1697 registers are also spilled as a pair and stored as a
1700 When little-endian the least significant part is
1701 stored first leading to the memory order $f[N] and
1704 Unfortunately, when big-endian the most significant
1705 part of the double is stored first, and the least
1706 significant is stored second. This leads to the
1707 registers being ordered in memory as firt $f[N+1] and
1710 For the big-endian case make certain that the
1711 addresses point at the correct (swapped) locations
1712 $f[N] and $f[N+1] pair (keep in mind that
1713 reg_position is decremented each time through the
1716 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1717 reg_position
- MIPS_SAVED_REGSIZE
);
1719 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1720 reg_position
+ MIPS_SAVED_REGSIZE
);
1723 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1724 reg_position
-= MIPS_SAVED_REGSIZE
;
1727 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1730 /* SP_REGNUM, contains the value and not the address. */
1731 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1735 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1737 /* Always a pseudo. */
1738 gdb_assert (regno
>= NUM_REGS
);
1742 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1745 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1746 /* The SP_REGNUM is special, its value is stored in saved_regs.
1747 In fact, it is so special that it can even only be fetched
1748 using a raw register number! Once this code as been converted
1749 to frame-unwind the problem goes away. */
1750 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1752 return frame_unwind_register_signed (fi
, regno
);
1756 /* mips_addr_bits_remove - remove useless address bits */
1759 mips_addr_bits_remove (CORE_ADDR addr
)
1761 if (mips_mask_address_p ()
1762 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1763 /* This hack is a work-around for existing boards using PMON, the
1764 simulator, and any other 64-bit targets that doesn't have true
1765 64-bit addressing. On these targets, the upper 32 bits of
1766 addresses are ignored by the hardware. Thus, the PC or SP are
1767 likely to have been sign extended to all 1s by instruction
1768 sequences that load 32-bit addresses. For example, a typical
1769 piece of code that loads an address is this:
1771 lui $r2, <upper 16 bits>
1772 ori $r2, <lower 16 bits>
1774 But the lui sign-extends the value such that the upper 32 bits
1775 may be all 1s. The workaround is simply to mask off these
1776 bits. In the future, gcc may be changed to support true 64-bit
1777 addressing, and this masking will have to be disabled. */
1778 return addr
&= 0xffffffffUL
;
1783 /* mips_software_single_step() is called just before we want to resume
1784 the inferior, if we want to single-step it but there is no hardware
1785 or kernel single-step support (MIPS on GNU/Linux for example). We find
1786 the target of the coming instruction and breakpoint it.
1788 single_step is also called just after the inferior stops. If we had
1789 set up a simulated single-step, we undo our damage. */
1792 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1794 static CORE_ADDR next_pc
;
1795 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1796 static binsn_quantum break_mem
;
1799 if (insert_breakpoints_p
)
1801 pc
= read_register (PC_REGNUM
);
1802 next_pc
= mips_next_pc (pc
);
1804 target_insert_breakpoint (next_pc
, break_mem
);
1807 target_remove_breakpoint (next_pc
, break_mem
);
1811 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1816 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1817 : get_next_frame (prev
)
1818 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1820 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1821 return tmp
? tmp
: pc
;
1826 mips_frame_saved_pc (struct frame_info
*frame
)
1830 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1833 /* Always unwind the cooked PC register value. */
1834 frame_unwind_signed_register (frame
, NUM_REGS
+ PC_REGNUM
, &tmp
);
1839 mips_extra_func_info_t proc_desc
1840 = get_frame_extra_info (frame
)->proc_desc
;
1841 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1842 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1845 /* We have to get the saved pc from the sigcontext if it is
1846 a signal handler frame. */
1847 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1848 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1849 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1852 return ADDR_BITS_REMOVE (saved_pc
);
1855 static struct mips_extra_func_info temp_proc_desc
;
1857 /* This hack will go away once the get_prev_frame() code has been
1858 modified to set the frame's type first. That is BEFORE init extra
1859 frame info et.al. is called. This is because it will become
1860 possible to skip the init extra info call for sigtramp and dummy
1862 static CORE_ADDR
*temp_saved_regs
;
1864 /* Set a register's saved stack address in temp_saved_regs. If an
1865 address has already been set for this register, do nothing; this
1866 way we will only recognize the first save of a given register in a
1869 For simplicity, save the address in both [0 .. NUM_REGS) and
1870 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1871 is used as it is only second range (the ABI instead of ISA
1872 registers) that comes into play when finding saved registers in a
1876 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1878 if (saved_regs
[regno
] == 0)
1880 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1881 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1886 /* Test whether the PC points to the return instruction at the
1887 end of a function. */
1890 mips_about_to_return (CORE_ADDR pc
)
1892 if (pc_is_mips16 (pc
))
1893 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1894 generates a "jr $ra"; other times it generates code to load
1895 the return address from the stack to an accessible register (such
1896 as $a3), then a "jr" using that register. This second case
1897 is almost impossible to distinguish from an indirect jump
1898 used for switch statements, so we don't even try. */
1899 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1901 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1905 /* This fencepost looks highly suspicious to me. Removing it also
1906 seems suspicious as it could affect remote debugging across serial
1910 heuristic_proc_start (CORE_ADDR pc
)
1917 pc
= ADDR_BITS_REMOVE (pc
);
1919 fence
= start_pc
- heuristic_fence_post
;
1923 if (heuristic_fence_post
== UINT_MAX
1924 || fence
< VM_MIN_ADDRESS
)
1925 fence
= VM_MIN_ADDRESS
;
1927 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1929 /* search back for previous return */
1930 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1931 if (start_pc
< fence
)
1933 /* It's not clear to me why we reach this point when
1934 stop_soon, but with this test, at least we
1935 don't print out warnings for every child forked (eg, on
1936 decstation). 22apr93 rich@cygnus.com. */
1937 if (stop_soon
== NO_STOP_QUIETLY
)
1939 static int blurb_printed
= 0;
1941 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1946 /* This actually happens frequently in embedded
1947 development, when you first connect to a board
1948 and your stack pointer and pc are nowhere in
1949 particular. This message needs to give people
1950 in that situation enough information to
1951 determine that it's no big deal. */
1952 printf_filtered ("\n\
1953 GDB is unable to find the start of the function at 0x%s\n\
1954 and thus can't determine the size of that function's stack frame.\n\
1955 This means that GDB may be unable to access that stack frame, or\n\
1956 the frames below it.\n\
1957 This problem is most likely caused by an invalid program counter or\n\
1959 However, if you think GDB should simply search farther back\n\
1960 from 0x%s for code which looks like the beginning of a\n\
1961 function, you can increase the range of the search using the `set\n\
1962 heuristic-fence-post' command.\n",
1963 paddr_nz (pc
), paddr_nz (pc
));
1970 else if (pc_is_mips16 (start_pc
))
1972 unsigned short inst
;
1974 /* On MIPS16, any one of the following is likely to be the
1975 start of a function:
1979 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1980 inst
= mips_fetch_instruction (start_pc
);
1981 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1982 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1983 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1984 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1986 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1987 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1992 else if (mips_about_to_return (start_pc
))
1994 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2001 /* Fetch the immediate value from a MIPS16 instruction.
2002 If the previous instruction was an EXTEND, use it to extend
2003 the upper bits of the immediate value. This is a helper function
2004 for mips16_heuristic_proc_desc. */
2007 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2008 unsigned short inst
, /* current instruction */
2009 int nbits
, /* number of bits in imm field */
2010 int scale
, /* scale factor to be applied to imm */
2011 int is_signed
) /* is the imm field signed? */
2015 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2017 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2018 if (offset
& 0x8000) /* check for negative extend */
2019 offset
= 0 - (0x10000 - (offset
& 0xffff));
2020 return offset
| (inst
& 0x1f);
2024 int max_imm
= 1 << nbits
;
2025 int mask
= max_imm
- 1;
2026 int sign_bit
= max_imm
>> 1;
2028 offset
= inst
& mask
;
2029 if (is_signed
&& (offset
& sign_bit
))
2030 offset
= 0 - (max_imm
- offset
);
2031 return offset
* scale
;
2036 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2037 stream from start_pc to limit_pc. */
2040 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2041 struct frame_info
*next_frame
, CORE_ADDR sp
)
2044 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2045 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2046 unsigned inst
= 0; /* current instruction */
2047 unsigned entry_inst
= 0; /* the entry instruction */
2050 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2051 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2053 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2055 /* Save the previous instruction. If it's an EXTEND, we'll extract
2056 the immediate offset extension from it in mips16_get_imm. */
2059 /* Fetch and decode the instruction. */
2060 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2061 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2062 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2064 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2065 if (offset
< 0) /* negative stack adjustment? */
2066 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2068 /* Exit loop if a positive stack adjustment is found, which
2069 usually means that the stack cleanup code in the function
2070 epilogue is reached. */
2073 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2075 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2076 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2077 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2078 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2080 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2082 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2083 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2084 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2085 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2087 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2089 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2090 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2091 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2093 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2095 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2096 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2097 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2099 else if (inst
== 0x673d) /* move $s1, $sp */
2102 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2104 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2106 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2107 frame_addr
= sp
+ offset
;
2108 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2109 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2111 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2113 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2114 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2115 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2116 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2118 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2120 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2121 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2122 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2123 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2125 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2126 entry_inst
= inst
; /* save for later processing */
2127 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2128 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2131 /* The entry instruction is typically the first instruction in a function,
2132 and it stores registers at offsets relative to the value of the old SP
2133 (before the prologue). But the value of the sp parameter to this
2134 function is the new SP (after the prologue has been executed). So we
2135 can't calculate those offsets until we've seen the entire prologue,
2136 and can calculate what the old SP must have been. */
2137 if (entry_inst
!= 0)
2139 int areg_count
= (entry_inst
>> 8) & 7;
2140 int sreg_count
= (entry_inst
>> 6) & 3;
2142 /* The entry instruction always subtracts 32 from the SP. */
2143 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2145 /* Now we can calculate what the SP must have been at the
2146 start of the function prologue. */
2147 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2149 /* Check if a0-a3 were saved in the caller's argument save area. */
2150 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2152 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2153 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2154 offset
+= MIPS_SAVED_REGSIZE
;
2157 /* Check if the ra register was pushed on the stack. */
2159 if (entry_inst
& 0x20)
2161 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2162 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2163 offset
-= MIPS_SAVED_REGSIZE
;
2166 /* Check if the s0 and s1 registers were pushed on the stack. */
2167 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2169 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2170 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2171 offset
-= MIPS_SAVED_REGSIZE
;
2177 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2178 struct frame_info
*next_frame
, CORE_ADDR sp
)
2181 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2183 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2184 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2185 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2186 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2187 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2189 unsigned long inst
, high_word
, low_word
;
2192 /* Fetch the instruction. */
2193 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2195 /* Save some code by pre-extracting some useful fields. */
2196 high_word
= (inst
>> 16) & 0xffff;
2197 low_word
= inst
& 0xffff;
2198 reg
= high_word
& 0x1f;
2200 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2201 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2202 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2204 if (low_word
& 0x8000) /* negative stack adjustment? */
2205 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2207 /* Exit loop if a positive stack adjustment is found, which
2208 usually means that the stack cleanup code in the function
2209 epilogue is reached. */
2212 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2214 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2215 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2217 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2219 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2220 but the register size used is only 32 bits. Make the address
2221 for the saved register point to the lower 32 bits. */
2222 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2223 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2225 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2227 /* Old gcc frame, r30 is virtual frame pointer. */
2228 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2229 frame_addr
= sp
+ low_word
;
2230 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2232 unsigned alloca_adjust
;
2233 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2234 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2235 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2236 if (alloca_adjust
> 0)
2238 /* FP > SP + frame_size. This may be because
2239 * of an alloca or somethings similar.
2240 * Fix sp to "pre-alloca" value, and try again.
2242 sp
+= alloca_adjust
;
2247 /* move $30,$sp. With different versions of gas this will be either
2248 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2249 Accept any one of these. */
2250 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2252 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2253 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2255 unsigned alloca_adjust
;
2256 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2257 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2258 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2259 if (alloca_adjust
> 0)
2261 /* FP > SP + frame_size. This may be because
2262 * of an alloca or somethings similar.
2263 * Fix sp to "pre-alloca" value, and try again.
2265 sp
+= alloca_adjust
;
2270 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2272 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2273 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2278 static mips_extra_func_info_t
2279 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2280 struct frame_info
*next_frame
, int cur_frame
)
2285 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2291 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2292 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2293 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2294 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2295 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2296 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2298 if (start_pc
+ 200 < limit_pc
)
2299 limit_pc
= start_pc
+ 200;
2300 if (pc_is_mips16 (start_pc
))
2301 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2303 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2304 return &temp_proc_desc
;
2307 struct mips_objfile_private
2313 /* Global used to communicate between non_heuristic_proc_desc and
2314 compare_pdr_entries within qsort (). */
2315 static bfd
*the_bfd
;
2318 compare_pdr_entries (const void *a
, const void *b
)
2320 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2321 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2325 else if (lhs
== rhs
)
2331 static mips_extra_func_info_t
2332 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2334 CORE_ADDR startaddr
;
2335 mips_extra_func_info_t proc_desc
;
2336 struct block
*b
= block_for_pc (pc
);
2338 struct obj_section
*sec
;
2339 struct mips_objfile_private
*priv
;
2341 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2344 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2346 *addrptr
= startaddr
;
2350 sec
= find_pc_section (pc
);
2353 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2355 /* Search the ".pdr" section generated by GAS. This includes most of
2356 the information normally found in ECOFF PDRs. */
2358 the_bfd
= sec
->objfile
->obfd
;
2360 && (the_bfd
->format
== bfd_object
2361 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2362 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2364 /* Right now GAS only outputs the address as a four-byte sequence.
2365 This means that we should not bother with this method on 64-bit
2366 targets (until that is fixed). */
2368 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2369 sizeof (struct mips_objfile_private
));
2371 sec
->objfile
->obj_private
= priv
;
2373 else if (priv
== NULL
)
2377 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2378 sizeof (struct mips_objfile_private
));
2380 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2383 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2384 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2386 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2387 priv
->contents
, 0, priv
->size
);
2389 /* In general, the .pdr section is sorted. However, in the
2390 presence of multiple code sections (and other corner cases)
2391 it can become unsorted. Sort it so that we can use a faster
2393 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2398 sec
->objfile
->obj_private
= priv
;
2402 if (priv
->size
!= 0)
2408 high
= priv
->size
/ 32;
2414 mid
= (low
+ high
) / 2;
2416 ptr
= priv
->contents
+ mid
* 32;
2417 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2418 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2419 SECT_OFF_TEXT (sec
->objfile
));
2420 if (pdr_pc
== startaddr
)
2422 if (pdr_pc
> startaddr
)
2427 while (low
!= high
);
2431 struct symbol
*sym
= find_pc_function (pc
);
2433 /* Fill in what we need of the proc_desc. */
2434 proc_desc
= (mips_extra_func_info_t
)
2435 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2436 sizeof (struct mips_extra_func_info
));
2437 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2439 /* Only used for dummy frames. */
2440 PROC_HIGH_ADDR (proc_desc
) = 0;
2442 PROC_FRAME_OFFSET (proc_desc
)
2443 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2444 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2446 PROC_FRAME_ADJUST (proc_desc
) = 0;
2447 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2449 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2451 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2453 PROC_FREG_OFFSET (proc_desc
)
2454 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2455 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2457 proc_desc
->pdr
.isym
= (long) sym
;
2467 if (startaddr
> BLOCK_START (b
))
2469 /* This is the "pathological" case referred to in a comment in
2470 print_frame_info. It might be better to move this check into
2475 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2477 /* If we never found a PDR for this function in symbol reading, then
2478 examine prologues to find the information. */
2481 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2482 if (PROC_FRAME_REG (proc_desc
) == -1)
2492 static mips_extra_func_info_t
2493 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2495 mips_extra_func_info_t proc_desc
;
2496 CORE_ADDR startaddr
= 0;
2498 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2502 /* IF this is the topmost frame AND
2503 * (this proc does not have debugging information OR
2504 * the PC is in the procedure prologue)
2505 * THEN create a "heuristic" proc_desc (by analyzing
2506 * the actual code) to replace the "official" proc_desc.
2508 if (next_frame
== NULL
)
2510 struct symtab_and_line val
;
2511 struct symbol
*proc_symbol
=
2512 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2516 val
= find_pc_line (BLOCK_START
2517 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2519 val
.pc
= val
.end
? val
.end
: pc
;
2521 if (!proc_symbol
|| pc
< val
.pc
)
2523 mips_extra_func_info_t found_heuristic
=
2524 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2525 pc
, next_frame
, cur_frame
);
2526 if (found_heuristic
)
2527 proc_desc
= found_heuristic
;
2533 /* Is linked_proc_desc_table really necessary? It only seems to be used
2534 by procedure call dummys. However, the procedures being called ought
2535 to have their own proc_descs, and even if they don't,
2536 heuristic_proc_desc knows how to create them! */
2538 struct linked_proc_info
*link
;
2540 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2541 if (PROC_LOW_ADDR (&link
->info
) <= pc
2542 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2546 startaddr
= heuristic_proc_start (pc
);
2549 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2555 get_frame_pointer (struct frame_info
*frame
,
2556 mips_extra_func_info_t proc_desc
)
2558 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2559 + PROC_FRAME_OFFSET (proc_desc
)
2560 - PROC_FRAME_ADJUST (proc_desc
));
2563 static mips_extra_func_info_t cached_proc_desc
;
2566 mips_frame_chain (struct frame_info
*frame
)
2568 mips_extra_func_info_t proc_desc
;
2570 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2572 if (saved_pc
== 0 || deprecated_inside_entry_file (saved_pc
))
2575 /* Check if the PC is inside a call stub. If it is, fetch the
2576 PC of the caller of that stub. */
2577 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2580 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2582 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2583 is well, frame->frame the bottom of the current frame will
2584 contain that value. */
2585 return get_frame_base (frame
);
2588 /* Look up the procedure descriptor for this PC. */
2589 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2593 cached_proc_desc
= proc_desc
;
2595 /* If no frame pointer and frame size is zero, we must be at end
2596 of stack (or otherwise hosed). If we don't check frame size,
2597 we loop forever if we see a zero size frame. */
2598 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2599 && PROC_FRAME_OFFSET (proc_desc
) == 0
2600 /* The previous frame from a sigtramp frame might be frameless
2601 and have frame size zero. */
2602 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2603 /* For a generic dummy frame, let get_frame_pointer() unwind a
2604 register value saved as part of the dummy frame call. */
2605 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2608 return get_frame_pointer (frame
, proc_desc
);
2612 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2615 mips_extra_func_info_t proc_desc
;
2617 if (get_frame_type (fci
) == DUMMY_FRAME
)
2620 /* Use proc_desc calculated in frame_chain. When there is no
2621 next frame, i.e, get_next_frame (fci) == NULL, we call
2622 find_proc_desc () to calculate it, passing an explicit
2623 NULL as the frame parameter. */
2625 get_next_frame (fci
)
2627 : find_proc_desc (get_frame_pc (fci
),
2628 NULL
/* i.e, get_next_frame (fci) */,
2631 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2633 deprecated_set_frame_saved_regs_hack (fci
, NULL
);
2634 get_frame_extra_info (fci
)->proc_desc
=
2635 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2638 /* Fixup frame-pointer - only needed for top frame */
2639 /* This may not be quite right, if proc has a real frame register.
2640 Get the value of the frame relative sp, procedure might have been
2641 interrupted by a signal at it's very start. */
2642 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2643 && !PROC_DESC_IS_DUMMY (proc_desc
))
2644 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2645 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2646 /* Do not ``fix'' fci->frame. It will have the value of the
2647 generic dummy frame's top-of-stack (since the draft
2648 fci->frame is obtained by returning the unwound stack
2649 pointer) and that is what we want. That way the fci->frame
2650 value will match the top-of-stack value that was saved as
2651 part of the dummy frames data. */
2654 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2656 if (proc_desc
== &temp_proc_desc
)
2660 /* Do not set the saved registers for a sigtramp frame,
2661 mips_find_saved_registers will do that for us. We can't
2662 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2664 /* FIXME: cagney/2002-11-18: This problem will go away once
2665 frame.c:get_prev_frame() is modified to set the frame's
2666 type before calling functions like this. */
2667 find_pc_partial_function (get_frame_pc (fci
), &name
,
2668 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2669 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2671 frame_saved_regs_zalloc (fci
);
2672 /* Set value of previous frame's stack pointer.
2673 Remember that saved_regs[SP_REGNUM] is special in
2674 that it contains the value of the stack pointer
2675 register. The other saved_regs values are addresses
2676 (in the inferior) at which a given register's value
2678 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2679 get_frame_base (fci
));
2680 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2681 temp_saved_regs
[RA_REGNUM
]);
2682 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2683 SIZEOF_FRAME_SAVED_REGS
);
2687 /* hack: if argument regs are saved, guess these contain args */
2688 /* assume we can't tell how many args for now */
2689 get_frame_extra_info (fci
)->num_args
= -1;
2690 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2692 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2694 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2701 /* MIPS stack frames are almost impenetrable. When execution stops,
2702 we basically have to look at symbol information for the function
2703 that we stopped in, which tells us *which* register (if any) is
2704 the base of the frame pointer, and what offset from that register
2705 the frame itself is at.
2707 This presents a problem when trying to examine a stack in memory
2708 (that isn't executing at the moment), using the "frame" command. We
2709 don't have a PC, nor do we have any registers except SP.
2711 This routine takes two arguments, SP and PC, and tries to make the
2712 cached frames look as if these two arguments defined a frame on the
2713 cache. This allows the rest of info frame to extract the important
2714 arguments without difficulty. */
2717 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2720 error ("MIPS frame specifications require two arguments: sp and pc");
2722 return create_new_frame (argv
[0], argv
[1]);
2725 /* According to the current ABI, should the type be passed in a
2726 floating-point register (assuming that there is space)? When there
2727 is no FPU, FP are not even considered as possibile candidates for
2728 FP registers and, consequently this returns false - forces FP
2729 arguments into integer registers. */
2732 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2734 return ((typecode
== TYPE_CODE_FLT
2736 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2737 && TYPE_NFIELDS (arg_type
) == 1
2738 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2739 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2742 /* On o32, argument passing in GPRs depends on the alignment of the type being
2743 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2746 mips_type_needs_double_align (struct type
*type
)
2748 enum type_code typecode
= TYPE_CODE (type
);
2750 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2752 else if (typecode
== TYPE_CODE_STRUCT
)
2754 if (TYPE_NFIELDS (type
) < 1)
2756 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2758 else if (typecode
== TYPE_CODE_UNION
)
2762 n
= TYPE_NFIELDS (type
);
2763 for (i
= 0; i
< n
; i
++)
2764 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2771 /* Adjust the address downward (direction of stack growth) so that it
2772 is correctly aligned for a new stack frame. */
2774 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2776 return align_down (addr
, 16);
2780 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2781 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2782 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2783 CORE_ADDR struct_addr
)
2789 int stack_offset
= 0;
2791 /* For shared libraries, "t9" needs to point at the function
2793 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2795 /* Set the return address register to point to the entry point of
2796 the program, where a breakpoint lies in wait. */
2797 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2799 /* First ensure that the stack and structure return address (if any)
2800 are properly aligned. The stack has to be at least 64-bit
2801 aligned even on 32-bit machines, because doubles must be 64-bit
2802 aligned. For n32 and n64, stack frames need to be 128-bit
2803 aligned, so we round to this widest known alignment. */
2805 sp
= align_down (sp
, 16);
2806 struct_addr
= align_down (struct_addr
, 16);
2808 /* Now make space on the stack for the args. We allocate more
2809 than necessary for EABI, because the first few arguments are
2810 passed in registers, but that's OK. */
2811 for (argnum
= 0; argnum
< nargs
; argnum
++)
2812 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2813 MIPS_STACK_ARGSIZE
);
2814 sp
-= align_up (len
, 16);
2817 fprintf_unfiltered (gdb_stdlog
,
2818 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2819 paddr_nz (sp
), (long) align_up (len
, 16));
2821 /* Initialize the integer and float register pointers. */
2823 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2825 /* The struct_return pointer occupies the first parameter-passing reg. */
2829 fprintf_unfiltered (gdb_stdlog
,
2830 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2831 argreg
, paddr_nz (struct_addr
));
2832 write_register (argreg
++, struct_addr
);
2835 /* Now load as many as possible of the first arguments into
2836 registers, and push the rest onto the stack. Loop thru args
2837 from first to last. */
2838 for (argnum
= 0; argnum
< nargs
; argnum
++)
2841 char valbuf
[MAX_REGISTER_SIZE
];
2842 struct value
*arg
= args
[argnum
];
2843 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2844 int len
= TYPE_LENGTH (arg_type
);
2845 enum type_code typecode
= TYPE_CODE (arg_type
);
2848 fprintf_unfiltered (gdb_stdlog
,
2849 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2850 argnum
+ 1, len
, (int) typecode
);
2852 /* The EABI passes structures that do not fit in a register by
2854 if (len
> MIPS_SAVED_REGSIZE
2855 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2857 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2858 typecode
= TYPE_CODE_PTR
;
2859 len
= MIPS_SAVED_REGSIZE
;
2862 fprintf_unfiltered (gdb_stdlog
, " push");
2865 val
= (char *) VALUE_CONTENTS (arg
);
2867 /* 32-bit ABIs always start floating point arguments in an
2868 even-numbered floating point register. Round the FP register
2869 up before the check to see if there are any FP registers
2870 left. Non MIPS_EABI targets also pass the FP in the integer
2871 registers so also round up normal registers. */
2872 if (!FP_REGISTER_DOUBLE
2873 && fp_register_arg_p (typecode
, arg_type
))
2875 if ((float_argreg
& 1))
2879 /* Floating point arguments passed in registers have to be
2880 treated specially. On 32-bit architectures, doubles
2881 are passed in register pairs; the even register gets
2882 the low word, and the odd register gets the high word.
2883 On non-EABI processors, the first two floating point arguments are
2884 also copied to general registers, because MIPS16 functions
2885 don't use float registers for arguments. This duplication of
2886 arguments in general registers can't hurt non-MIPS16 functions
2887 because those registers are normally skipped. */
2888 /* MIPS_EABI squeezes a struct that contains a single floating
2889 point value into an FP register instead of pushing it onto the
2891 if (fp_register_arg_p (typecode
, arg_type
)
2892 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2894 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2896 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2897 unsigned long regval
;
2899 /* Write the low word of the double to the even register(s). */
2900 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2902 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2903 float_argreg
, phex (regval
, 4));
2904 write_register (float_argreg
++, regval
);
2906 /* Write the high word of the double to the odd register(s). */
2907 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2909 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2910 float_argreg
, phex (regval
, 4));
2911 write_register (float_argreg
++, regval
);
2915 /* This is a floating point value that fits entirely
2916 in a single register. */
2917 /* On 32 bit ABI's the float_argreg is further adjusted
2918 above to ensure that it is even register aligned. */
2919 LONGEST regval
= extract_unsigned_integer (val
, len
);
2921 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2922 float_argreg
, phex (regval
, len
));
2923 write_register (float_argreg
++, regval
);
2928 /* Copy the argument to general registers or the stack in
2929 register-sized pieces. Large arguments are split between
2930 registers and stack. */
2931 /* Note: structs whose size is not a multiple of
2932 mips_regsize() are treated specially: Irix cc passes them
2933 in registers where gcc sometimes puts them on the stack.
2934 For maximum compatibility, we will put them in both
2936 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2937 (len
% MIPS_SAVED_REGSIZE
!= 0));
2939 /* Note: Floating-point values that didn't fit into an FP
2940 register are only written to memory. */
2943 /* Remember if the argument was written to the stack. */
2944 int stack_used_p
= 0;
2946 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2949 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2952 /* Write this portion of the argument to the stack. */
2953 if (argreg
> MIPS_LAST_ARG_REGNUM
2955 || fp_register_arg_p (typecode
, arg_type
))
2957 /* Should shorter than int integer values be
2958 promoted to int before being stored? */
2959 int longword_offset
= 0;
2962 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2964 if (MIPS_STACK_ARGSIZE
== 8 &&
2965 (typecode
== TYPE_CODE_INT
||
2966 typecode
== TYPE_CODE_PTR
||
2967 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2968 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2969 else if ((typecode
== TYPE_CODE_STRUCT
||
2970 typecode
== TYPE_CODE_UNION
) &&
2971 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2972 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2977 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2978 paddr_nz (stack_offset
));
2979 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2980 paddr_nz (longword_offset
));
2983 addr
= sp
+ stack_offset
+ longword_offset
;
2988 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2990 for (i
= 0; i
< partial_len
; i
++)
2992 fprintf_unfiltered (gdb_stdlog
, "%02x",
2996 write_memory (addr
, val
, partial_len
);
2999 /* Note!!! This is NOT an else clause. Odd sized
3000 structs may go thru BOTH paths. Floating point
3001 arguments will not. */
3002 /* Write this portion of the argument to a general
3003 purpose register. */
3004 if (argreg
<= MIPS_LAST_ARG_REGNUM
3005 && !fp_register_arg_p (typecode
, arg_type
))
3007 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3010 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3012 phex (regval
, MIPS_SAVED_REGSIZE
));
3013 write_register (argreg
, regval
);
3020 /* Compute the the offset into the stack at which we
3021 will copy the next parameter.
3023 In the new EABI (and the NABI32), the stack_offset
3024 only needs to be adjusted when it has been used. */
3027 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3031 fprintf_unfiltered (gdb_stdlog
, "\n");
3034 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3036 /* Return adjusted stack pointer. */
3040 /* N32/N64 version of push_dummy_call. */
3043 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3044 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3045 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3046 CORE_ADDR struct_addr
)
3052 int stack_offset
= 0;
3054 /* For shared libraries, "t9" needs to point at the function
3056 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3058 /* Set the return address register to point to the entry point of
3059 the program, where a breakpoint lies in wait. */
3060 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3062 /* First ensure that the stack and structure return address (if any)
3063 are properly aligned. The stack has to be at least 64-bit
3064 aligned even on 32-bit machines, because doubles must be 64-bit
3065 aligned. For n32 and n64, stack frames need to be 128-bit
3066 aligned, so we round to this widest known alignment. */
3068 sp
= align_down (sp
, 16);
3069 struct_addr
= align_down (struct_addr
, 16);
3071 /* Now make space on the stack for the args. */
3072 for (argnum
= 0; argnum
< nargs
; argnum
++)
3073 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3074 MIPS_STACK_ARGSIZE
);
3075 sp
-= align_up (len
, 16);
3078 fprintf_unfiltered (gdb_stdlog
,
3079 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3080 paddr_nz (sp
), (long) align_up (len
, 16));
3082 /* Initialize the integer and float register pointers. */
3084 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3086 /* The struct_return pointer occupies the first parameter-passing reg. */
3090 fprintf_unfiltered (gdb_stdlog
,
3091 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3092 argreg
, paddr_nz (struct_addr
));
3093 write_register (argreg
++, struct_addr
);
3096 /* Now load as many as possible of the first arguments into
3097 registers, and push the rest onto the stack. Loop thru args
3098 from first to last. */
3099 for (argnum
= 0; argnum
< nargs
; argnum
++)
3102 char valbuf
[MAX_REGISTER_SIZE
];
3103 struct value
*arg
= args
[argnum
];
3104 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3105 int len
= TYPE_LENGTH (arg_type
);
3106 enum type_code typecode
= TYPE_CODE (arg_type
);
3109 fprintf_unfiltered (gdb_stdlog
,
3110 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3111 argnum
+ 1, len
, (int) typecode
);
3113 val
= (char *) VALUE_CONTENTS (arg
);
3115 if (fp_register_arg_p (typecode
, arg_type
)
3116 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3118 /* This is a floating point value that fits entirely
3119 in a single register. */
3120 /* On 32 bit ABI's the float_argreg is further adjusted
3121 above to ensure that it is even register aligned. */
3122 LONGEST regval
= extract_unsigned_integer (val
, len
);
3124 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3125 float_argreg
, phex (regval
, len
));
3126 write_register (float_argreg
++, regval
);
3129 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3130 argreg
, phex (regval
, len
));
3131 write_register (argreg
, regval
);
3136 /* Copy the argument to general registers or the stack in
3137 register-sized pieces. Large arguments are split between
3138 registers and stack. */
3139 /* Note: structs whose size is not a multiple of
3140 mips_regsize() are treated specially: Irix cc passes them
3141 in registers where gcc sometimes puts them on the stack.
3142 For maximum compatibility, we will put them in both
3144 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3145 (len
% MIPS_SAVED_REGSIZE
!= 0));
3146 /* Note: Floating-point values that didn't fit into an FP
3147 register are only written to memory. */
3150 /* Rememer if the argument was written to the stack. */
3151 int stack_used_p
= 0;
3152 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3153 len
: MIPS_SAVED_REGSIZE
;
3156 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3159 /* Write this portion of the argument to the stack. */
3160 if (argreg
> MIPS_LAST_ARG_REGNUM
3162 || fp_register_arg_p (typecode
, arg_type
))
3164 /* Should shorter than int integer values be
3165 promoted to int before being stored? */
3166 int longword_offset
= 0;
3169 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3171 if (MIPS_STACK_ARGSIZE
== 8 &&
3172 (typecode
== TYPE_CODE_INT
||
3173 typecode
== TYPE_CODE_PTR
||
3174 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3175 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3180 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3181 paddr_nz (stack_offset
));
3182 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3183 paddr_nz (longword_offset
));
3186 addr
= sp
+ stack_offset
+ longword_offset
;
3191 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3193 for (i
= 0; i
< partial_len
; i
++)
3195 fprintf_unfiltered (gdb_stdlog
, "%02x",
3199 write_memory (addr
, val
, partial_len
);
3202 /* Note!!! This is NOT an else clause. Odd sized
3203 structs may go thru BOTH paths. Floating point
3204 arguments will not. */
3205 /* Write this portion of the argument to a general
3206 purpose register. */
3207 if (argreg
<= MIPS_LAST_ARG_REGNUM
3208 && !fp_register_arg_p (typecode
, arg_type
))
3210 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3212 /* A non-floating-point argument being passed in a
3213 general register. If a struct or union, and if
3214 the remaining length is smaller than the register
3215 size, we have to adjust the register value on
3218 It does not seem to be necessary to do the
3219 same for integral types.
3221 cagney/2001-07-23: gdb/179: Also, GCC, when
3222 outputting LE O32 with sizeof (struct) <
3223 MIPS_SAVED_REGSIZE, generates a left shift as
3224 part of storing the argument in a register a
3225 register (the left shift isn't generated when
3226 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3227 is quite possible that this is GCC contradicting
3228 the LE/O32 ABI, GDB has not been adjusted to
3229 accommodate this. Either someone needs to
3230 demonstrate that the LE/O32 ABI specifies such a
3231 left shift OR this new ABI gets identified as
3232 such and GDB gets tweaked accordingly. */
3234 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3235 && partial_len
< MIPS_SAVED_REGSIZE
3236 && (typecode
== TYPE_CODE_STRUCT
||
3237 typecode
== TYPE_CODE_UNION
))
3238 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3242 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3244 phex (regval
, MIPS_SAVED_REGSIZE
));
3245 write_register (argreg
, regval
);
3252 /* Compute the the offset into the stack at which we
3253 will copy the next parameter.
3255 In N32 (N64?), the stack_offset only needs to be
3256 adjusted when it has been used. */
3259 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3263 fprintf_unfiltered (gdb_stdlog
, "\n");
3266 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3268 /* Return adjusted stack pointer. */
3272 /* O32 version of push_dummy_call. */
3275 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3276 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3277 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3278 CORE_ADDR struct_addr
)
3284 int stack_offset
= 0;
3286 /* For shared libraries, "t9" needs to point at the function
3288 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3290 /* Set the return address register to point to the entry point of
3291 the program, where a breakpoint lies in wait. */
3292 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3294 /* First ensure that the stack and structure return address (if any)
3295 are properly aligned. The stack has to be at least 64-bit
3296 aligned even on 32-bit machines, because doubles must be 64-bit
3297 aligned. For n32 and n64, stack frames need to be 128-bit
3298 aligned, so we round to this widest known alignment. */
3300 sp
= align_down (sp
, 16);
3301 struct_addr
= align_down (struct_addr
, 16);
3303 /* Now make space on the stack for the args. */
3304 for (argnum
= 0; argnum
< nargs
; argnum
++)
3305 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3306 MIPS_STACK_ARGSIZE
);
3307 sp
-= align_up (len
, 16);
3310 fprintf_unfiltered (gdb_stdlog
,
3311 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3312 paddr_nz (sp
), (long) align_up (len
, 16));
3314 /* Initialize the integer and float register pointers. */
3316 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3318 /* The struct_return pointer occupies the first parameter-passing reg. */
3322 fprintf_unfiltered (gdb_stdlog
,
3323 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3324 argreg
, paddr_nz (struct_addr
));
3325 write_register (argreg
++, struct_addr
);
3326 stack_offset
+= MIPS_STACK_ARGSIZE
;
3329 /* Now load as many as possible of the first arguments into
3330 registers, and push the rest onto the stack. Loop thru args
3331 from first to last. */
3332 for (argnum
= 0; argnum
< nargs
; argnum
++)
3335 char valbuf
[MAX_REGISTER_SIZE
];
3336 struct value
*arg
= args
[argnum
];
3337 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3338 int len
= TYPE_LENGTH (arg_type
);
3339 enum type_code typecode
= TYPE_CODE (arg_type
);
3342 fprintf_unfiltered (gdb_stdlog
,
3343 "mips_o32_push_dummy_call: %d len=%d type=%d",
3344 argnum
+ 1, len
, (int) typecode
);
3346 val
= (char *) VALUE_CONTENTS (arg
);
3348 /* 32-bit ABIs always start floating point arguments in an
3349 even-numbered floating point register. Round the FP register
3350 up before the check to see if there are any FP registers
3351 left. O32/O64 targets also pass the FP in the integer
3352 registers so also round up normal registers. */
3353 if (!FP_REGISTER_DOUBLE
3354 && fp_register_arg_p (typecode
, arg_type
))
3356 if ((float_argreg
& 1))
3360 /* Floating point arguments passed in registers have to be
3361 treated specially. On 32-bit architectures, doubles
3362 are passed in register pairs; the even register gets
3363 the low word, and the odd register gets the high word.
3364 On O32/O64, the first two floating point arguments are
3365 also copied to general registers, because MIPS16 functions
3366 don't use float registers for arguments. This duplication of
3367 arguments in general registers can't hurt non-MIPS16 functions
3368 because those registers are normally skipped. */
3370 if (fp_register_arg_p (typecode
, arg_type
)
3371 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3373 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3375 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3376 unsigned long regval
;
3378 /* Write the low word of the double to the even register(s). */
3379 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3381 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3382 float_argreg
, phex (regval
, 4));
3383 write_register (float_argreg
++, regval
);
3385 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3386 argreg
, phex (regval
, 4));
3387 write_register (argreg
++, regval
);
3389 /* Write the high word of the double to the odd register(s). */
3390 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3392 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3393 float_argreg
, phex (regval
, 4));
3394 write_register (float_argreg
++, regval
);
3397 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3398 argreg
, phex (regval
, 4));
3399 write_register (argreg
++, regval
);
3403 /* This is a floating point value that fits entirely
3404 in a single register. */
3405 /* On 32 bit ABI's the float_argreg is further adjusted
3406 above to ensure that it is even register aligned. */
3407 LONGEST regval
= extract_unsigned_integer (val
, len
);
3409 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3410 float_argreg
, phex (regval
, len
));
3411 write_register (float_argreg
++, regval
);
3412 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3413 registers for each argument. The below is (my
3414 guess) to ensure that the corresponding integer
3415 register has reserved the same space. */
3417 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3418 argreg
, phex (regval
, len
));
3419 write_register (argreg
, regval
);
3420 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3422 /* Reserve space for the FP register. */
3423 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3427 /* Copy the argument to general registers or the stack in
3428 register-sized pieces. Large arguments are split between
3429 registers and stack. */
3430 /* Note: structs whose size is not a multiple of
3431 mips_regsize() are treated specially: Irix cc passes them
3432 in registers where gcc sometimes puts them on the stack.
3433 For maximum compatibility, we will put them in both
3435 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3436 (len
% MIPS_SAVED_REGSIZE
!= 0));
3437 /* Structures should be aligned to eight bytes (even arg registers)
3438 on MIPS_ABI_O32, if their first member has double precision. */
3439 if (MIPS_SAVED_REGSIZE
< 8
3440 && mips_type_needs_double_align (arg_type
))
3445 /* Note: Floating-point values that didn't fit into an FP
3446 register are only written to memory. */
3449 /* Remember if the argument was written to the stack. */
3450 int stack_used_p
= 0;
3452 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3455 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3458 /* Write this portion of the argument to the stack. */
3459 if (argreg
> MIPS_LAST_ARG_REGNUM
3461 || fp_register_arg_p (typecode
, arg_type
))
3463 /* Should shorter than int integer values be
3464 promoted to int before being stored? */
3465 int longword_offset
= 0;
3468 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3470 if (MIPS_STACK_ARGSIZE
== 8 &&
3471 (typecode
== TYPE_CODE_INT
||
3472 typecode
== TYPE_CODE_PTR
||
3473 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3474 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3479 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3480 paddr_nz (stack_offset
));
3481 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3482 paddr_nz (longword_offset
));
3485 addr
= sp
+ stack_offset
+ longword_offset
;
3490 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3492 for (i
= 0; i
< partial_len
; i
++)
3494 fprintf_unfiltered (gdb_stdlog
, "%02x",
3498 write_memory (addr
, val
, partial_len
);
3501 /* Note!!! This is NOT an else clause. Odd sized
3502 structs may go thru BOTH paths. Floating point
3503 arguments will not. */
3504 /* Write this portion of the argument to a general
3505 purpose register. */
3506 if (argreg
<= MIPS_LAST_ARG_REGNUM
3507 && !fp_register_arg_p (typecode
, arg_type
))
3509 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3510 /* Value may need to be sign extended, because
3511 mips_regsize() != MIPS_SAVED_REGSIZE. */
3513 /* A non-floating-point argument being passed in a
3514 general register. If a struct or union, and if
3515 the remaining length is smaller than the register
3516 size, we have to adjust the register value on
3519 It does not seem to be necessary to do the
3520 same for integral types.
3522 Also don't do this adjustment on O64 binaries.
3524 cagney/2001-07-23: gdb/179: Also, GCC, when
3525 outputting LE O32 with sizeof (struct) <
3526 MIPS_SAVED_REGSIZE, generates a left shift as
3527 part of storing the argument in a register a
3528 register (the left shift isn't generated when
3529 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3530 is quite possible that this is GCC contradicting
3531 the LE/O32 ABI, GDB has not been adjusted to
3532 accommodate this. Either someone needs to
3533 demonstrate that the LE/O32 ABI specifies such a
3534 left shift OR this new ABI gets identified as
3535 such and GDB gets tweaked accordingly. */
3537 if (MIPS_SAVED_REGSIZE
< 8
3538 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3539 && partial_len
< MIPS_SAVED_REGSIZE
3540 && (typecode
== TYPE_CODE_STRUCT
||
3541 typecode
== TYPE_CODE_UNION
))
3542 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3546 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3548 phex (regval
, MIPS_SAVED_REGSIZE
));
3549 write_register (argreg
, regval
);
3552 /* Prevent subsequent floating point arguments from
3553 being passed in floating point registers. */
3554 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3560 /* Compute the the offset into the stack at which we
3561 will copy the next parameter.
3563 In older ABIs, the caller reserved space for
3564 registers that contained arguments. This was loosely
3565 refered to as their "home". Consequently, space is
3566 always allocated. */
3568 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3572 fprintf_unfiltered (gdb_stdlog
, "\n");
3575 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3577 /* Return adjusted stack pointer. */
3581 /* O64 version of push_dummy_call. */
3584 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3585 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3586 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3587 CORE_ADDR struct_addr
)
3593 int stack_offset
= 0;
3595 /* For shared libraries, "t9" needs to point at the function
3597 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3599 /* Set the return address register to point to the entry point of
3600 the program, where a breakpoint lies in wait. */
3601 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3603 /* First ensure that the stack and structure return address (if any)
3604 are properly aligned. The stack has to be at least 64-bit
3605 aligned even on 32-bit machines, because doubles must be 64-bit
3606 aligned. For n32 and n64, stack frames need to be 128-bit
3607 aligned, so we round to this widest known alignment. */
3609 sp
= align_down (sp
, 16);
3610 struct_addr
= align_down (struct_addr
, 16);
3612 /* Now make space on the stack for the args. */
3613 for (argnum
= 0; argnum
< nargs
; argnum
++)
3614 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3615 MIPS_STACK_ARGSIZE
);
3616 sp
-= align_up (len
, 16);
3619 fprintf_unfiltered (gdb_stdlog
,
3620 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3621 paddr_nz (sp
), (long) align_up (len
, 16));
3623 /* Initialize the integer and float register pointers. */
3625 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3627 /* The struct_return pointer occupies the first parameter-passing reg. */
3631 fprintf_unfiltered (gdb_stdlog
,
3632 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3633 argreg
, paddr_nz (struct_addr
));
3634 write_register (argreg
++, struct_addr
);
3635 stack_offset
+= MIPS_STACK_ARGSIZE
;
3638 /* Now load as many as possible of the first arguments into
3639 registers, and push the rest onto the stack. Loop thru args
3640 from first to last. */
3641 for (argnum
= 0; argnum
< nargs
; argnum
++)
3644 char valbuf
[MAX_REGISTER_SIZE
];
3645 struct value
*arg
= args
[argnum
];
3646 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3647 int len
= TYPE_LENGTH (arg_type
);
3648 enum type_code typecode
= TYPE_CODE (arg_type
);
3651 fprintf_unfiltered (gdb_stdlog
,
3652 "mips_o64_push_dummy_call: %d len=%d type=%d",
3653 argnum
+ 1, len
, (int) typecode
);
3655 val
= (char *) VALUE_CONTENTS (arg
);
3657 /* 32-bit ABIs always start floating point arguments in an
3658 even-numbered floating point register. Round the FP register
3659 up before the check to see if there are any FP registers
3660 left. O32/O64 targets also pass the FP in the integer
3661 registers so also round up normal registers. */
3662 if (!FP_REGISTER_DOUBLE
3663 && fp_register_arg_p (typecode
, arg_type
))
3665 if ((float_argreg
& 1))
3669 /* Floating point arguments passed in registers have to be
3670 treated specially. On 32-bit architectures, doubles
3671 are passed in register pairs; the even register gets
3672 the low word, and the odd register gets the high word.
3673 On O32/O64, the first two floating point arguments are
3674 also copied to general registers, because MIPS16 functions
3675 don't use float registers for arguments. This duplication of
3676 arguments in general registers can't hurt non-MIPS16 functions
3677 because those registers are normally skipped. */
3679 if (fp_register_arg_p (typecode
, arg_type
)
3680 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3682 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3684 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3685 unsigned long regval
;
3687 /* Write the low word of the double to the even register(s). */
3688 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3690 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3691 float_argreg
, phex (regval
, 4));
3692 write_register (float_argreg
++, regval
);
3694 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3695 argreg
, phex (regval
, 4));
3696 write_register (argreg
++, regval
);
3698 /* Write the high word of the double to the odd register(s). */
3699 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3701 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3702 float_argreg
, phex (regval
, 4));
3703 write_register (float_argreg
++, regval
);
3706 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3707 argreg
, phex (regval
, 4));
3708 write_register (argreg
++, regval
);
3712 /* This is a floating point value that fits entirely
3713 in a single register. */
3714 /* On 32 bit ABI's the float_argreg is further adjusted
3715 above to ensure that it is even register aligned. */
3716 LONGEST regval
= extract_unsigned_integer (val
, len
);
3718 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3719 float_argreg
, phex (regval
, len
));
3720 write_register (float_argreg
++, regval
);
3721 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3722 registers for each argument. The below is (my
3723 guess) to ensure that the corresponding integer
3724 register has reserved the same space. */
3726 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3727 argreg
, phex (regval
, len
));
3728 write_register (argreg
, regval
);
3729 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3731 /* Reserve space for the FP register. */
3732 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3736 /* Copy the argument to general registers or the stack in
3737 register-sized pieces. Large arguments are split between
3738 registers and stack. */
3739 /* Note: structs whose size is not a multiple of
3740 mips_regsize() are treated specially: Irix cc passes them
3741 in registers where gcc sometimes puts them on the stack.
3742 For maximum compatibility, we will put them in both
3744 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3745 (len
% MIPS_SAVED_REGSIZE
!= 0));
3746 /* Structures should be aligned to eight bytes (even arg registers)
3747 on MIPS_ABI_O32, if their first member has double precision. */
3748 if (MIPS_SAVED_REGSIZE
< 8
3749 && mips_type_needs_double_align (arg_type
))
3754 /* Note: Floating-point values that didn't fit into an FP
3755 register are only written to memory. */
3758 /* Remember if the argument was written to the stack. */
3759 int stack_used_p
= 0;
3761 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3764 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3767 /* Write this portion of the argument to the stack. */
3768 if (argreg
> MIPS_LAST_ARG_REGNUM
3770 || fp_register_arg_p (typecode
, arg_type
))
3772 /* Should shorter than int integer values be
3773 promoted to int before being stored? */
3774 int longword_offset
= 0;
3777 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3779 if (MIPS_STACK_ARGSIZE
== 8 &&
3780 (typecode
== TYPE_CODE_INT
||
3781 typecode
== TYPE_CODE_PTR
||
3782 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3783 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3788 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3789 paddr_nz (stack_offset
));
3790 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3791 paddr_nz (longword_offset
));
3794 addr
= sp
+ stack_offset
+ longword_offset
;
3799 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3801 for (i
= 0; i
< partial_len
; i
++)
3803 fprintf_unfiltered (gdb_stdlog
, "%02x",
3807 write_memory (addr
, val
, partial_len
);
3810 /* Note!!! This is NOT an else clause. Odd sized
3811 structs may go thru BOTH paths. Floating point
3812 arguments will not. */
3813 /* Write this portion of the argument to a general
3814 purpose register. */
3815 if (argreg
<= MIPS_LAST_ARG_REGNUM
3816 && !fp_register_arg_p (typecode
, arg_type
))
3818 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3819 /* Value may need to be sign extended, because
3820 mips_regsize() != MIPS_SAVED_REGSIZE. */
3822 /* A non-floating-point argument being passed in a
3823 general register. If a struct or union, and if
3824 the remaining length is smaller than the register
3825 size, we have to adjust the register value on
3828 It does not seem to be necessary to do the
3829 same for integral types.
3831 Also don't do this adjustment on O64 binaries.
3833 cagney/2001-07-23: gdb/179: Also, GCC, when
3834 outputting LE O32 with sizeof (struct) <
3835 MIPS_SAVED_REGSIZE, generates a left shift as
3836 part of storing the argument in a register a
3837 register (the left shift isn't generated when
3838 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3839 is quite possible that this is GCC contradicting
3840 the LE/O32 ABI, GDB has not been adjusted to
3841 accommodate this. Either someone needs to
3842 demonstrate that the LE/O32 ABI specifies such a
3843 left shift OR this new ABI gets identified as
3844 such and GDB gets tweaked accordingly. */
3846 if (MIPS_SAVED_REGSIZE
< 8
3847 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3848 && partial_len
< MIPS_SAVED_REGSIZE
3849 && (typecode
== TYPE_CODE_STRUCT
||
3850 typecode
== TYPE_CODE_UNION
))
3851 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3855 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3857 phex (regval
, MIPS_SAVED_REGSIZE
));
3858 write_register (argreg
, regval
);
3861 /* Prevent subsequent floating point arguments from
3862 being passed in floating point registers. */
3863 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3869 /* Compute the the offset into the stack at which we
3870 will copy the next parameter.
3872 In older ABIs, the caller reserved space for
3873 registers that contained arguments. This was loosely
3874 refered to as their "home". Consequently, space is
3875 always allocated. */
3877 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3881 fprintf_unfiltered (gdb_stdlog
, "\n");
3884 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3886 /* Return adjusted stack pointer. */
3891 mips_pop_frame (void)
3894 struct frame_info
*frame
= get_current_frame ();
3895 CORE_ADDR new_sp
= get_frame_base (frame
);
3896 mips_extra_func_info_t proc_desc
;
3898 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3900 generic_pop_dummy_frame ();
3901 flush_cached_frames ();
3905 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3906 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3907 mips_find_saved_regs (frame
);
3908 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3909 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3910 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3912 /* Floating point registers must not be sign extended,
3913 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3915 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3916 write_register (regnum
,
3917 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3918 MIPS_SAVED_REGSIZE
));
3920 write_register (regnum
,
3921 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3922 MIPS_SAVED_REGSIZE
));
3925 write_register (SP_REGNUM
, new_sp
);
3926 flush_cached_frames ();
3928 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3930 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3932 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3934 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3936 if (&pi_ptr
->info
== proc_desc
)
3941 error ("Can't locate dummy extra frame info\n");
3943 if (prev_ptr
!= NULL
)
3944 prev_ptr
->next
= pi_ptr
->next
;
3946 linked_proc_desc_table
= pi_ptr
->next
;
3950 write_register (mips_regnum (current_gdbarch
)->hi
,
3951 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3952 MIPS_SAVED_REGSIZE
));
3953 write_register (mips_regnum (current_gdbarch
)->lo
,
3954 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3955 MIPS_SAVED_REGSIZE
));
3956 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3957 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3958 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3959 MIPS_SAVED_REGSIZE
));
3963 /* Floating point register management.
3965 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3966 64bit operations, these early MIPS cpus treat fp register pairs
3967 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3968 registers and offer a compatibility mode that emulates the MIPS2 fp
3969 model. When operating in MIPS2 fp compat mode, later cpu's split
3970 double precision floats into two 32-bit chunks and store them in
3971 consecutive fp regs. To display 64-bit floats stored in this
3972 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3973 Throw in user-configurable endianness and you have a real mess.
3975 The way this works is:
3976 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3977 double-precision value will be split across two logical registers.
3978 The lower-numbered logical register will hold the low-order bits,
3979 regardless of the processor's endianness.
3980 - If we are on a 64-bit processor, and we are looking for a
3981 single-precision value, it will be in the low ordered bits
3982 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3983 save slot in memory.
3984 - If we are in 64-bit mode, everything is straightforward.
3986 Note that this code only deals with "live" registers at the top of the
3987 stack. We will attempt to deal with saved registers later, when
3988 the raw/cooked register interface is in place. (We need a general
3989 interface that can deal with dynamic saved register sizes -- fp
3990 regs could be 32 bits wide in one frame and 64 on the frame above
3993 static struct type
*
3994 mips_float_register_type (void)
3996 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3997 return builtin_type_ieee_single_big
;
3999 return builtin_type_ieee_single_little
;
4002 static struct type
*
4003 mips_double_register_type (void)
4005 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4006 return builtin_type_ieee_double_big
;
4008 return builtin_type_ieee_double_little
;
4011 /* Copy a 32-bit single-precision value from the current frame
4012 into rare_buffer. */
4015 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4018 int raw_size
= register_size (current_gdbarch
, regno
);
4019 char *raw_buffer
= alloca (raw_size
);
4021 if (!frame_register_read (frame
, regno
, raw_buffer
))
4022 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4025 /* We have a 64-bit value for this register. Find the low-order
4029 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4034 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4038 memcpy (rare_buffer
, raw_buffer
, 4);
4042 /* Copy a 64-bit double-precision value from the current frame into
4043 rare_buffer. This may include getting half of it from the next
4047 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4050 int raw_size
= register_size (current_gdbarch
, regno
);
4052 if (raw_size
== 8 && !mips2_fp_compat ())
4054 /* We have a 64-bit value for this register, and we should use
4056 if (!frame_register_read (frame
, regno
, rare_buffer
))
4057 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4061 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4062 internal_error (__FILE__
, __LINE__
,
4063 "mips_read_fp_register_double: bad access to "
4064 "odd-numbered FP register");
4066 /* mips_read_fp_register_single will find the correct 32 bits from
4068 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4070 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4071 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4075 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4076 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4082 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4084 { /* do values for FP (float) regs */
4086 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4087 int inv1
, inv2
, namelen
;
4089 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4091 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4092 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4095 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4097 /* 4-byte registers: Print hex and floating. Also print even
4098 numbered registers as doubles. */
4099 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4100 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4102 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4104 fprintf_filtered (file
, " flt: ");
4106 fprintf_filtered (file
, " <invalid float> ");
4108 fprintf_filtered (file
, "%-17.9g", flt1
);
4110 if (regnum
% 2 == 0)
4112 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4113 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4116 fprintf_filtered (file
, " dbl: ");
4118 fprintf_filtered (file
, "<invalid double>");
4120 fprintf_filtered (file
, "%-24.17g", doub
);
4125 /* Eight byte registers: print each one as hex, float and double. */
4126 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4127 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4129 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4130 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4133 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4135 fprintf_filtered (file
, " flt: ");
4137 fprintf_filtered (file
, "<invalid float>");
4139 fprintf_filtered (file
, "%-17.9g", flt1
);
4141 fprintf_filtered (file
, " dbl: ");
4143 fprintf_filtered (file
, "<invalid double>");
4145 fprintf_filtered (file
, "%-24.17g", doub
);
4150 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4151 int regnum
, int all
)
4153 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4154 char raw_buffer
[MAX_REGISTER_SIZE
];
4157 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4159 mips_print_fp_register (file
, frame
, regnum
);
4163 /* Get the data in raw format. */
4164 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4166 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4170 fputs_filtered (REGISTER_NAME (regnum
), file
);
4172 /* The problem with printing numeric register names (r26, etc.) is that
4173 the user can't use them on input. Probably the best solution is to
4174 fix it so that either the numeric or the funky (a2, etc.) names
4175 are accepted on input. */
4176 if (regnum
< MIPS_NUMREGS
)
4177 fprintf_filtered (file
, "(r%d): ", regnum
);
4179 fprintf_filtered (file
, ": ");
4181 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4182 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4186 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4190 /* Replacement for generic do_registers_info.
4191 Print regs in pretty columns. */
4194 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4197 fprintf_filtered (file
, " ");
4198 mips_print_fp_register (file
, frame
, regnum
);
4199 fprintf_filtered (file
, "\n");
4204 /* Print a row's worth of GP (int) registers, with name labels above */
4207 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4210 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4211 /* do values for GP (int) regs */
4212 char raw_buffer
[MAX_REGISTER_SIZE
];
4213 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4217 /* For GP registers, we print a separate row of names above the vals */
4218 fprintf_filtered (file
, " ");
4219 for (col
= 0, regnum
= start_regnum
;
4220 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4223 if (*REGISTER_NAME (regnum
) == '\0')
4224 continue; /* unused register */
4225 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4226 break; /* end the row: reached FP register */
4227 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4228 REGISTER_NAME (regnum
));
4231 /* print the R0 to R31 names */
4232 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4233 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4235 fprintf_filtered (file
, "\n ");
4237 /* now print the values in hex, 4 or 8 to the row */
4238 for (col
= 0, regnum
= start_regnum
;
4239 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4242 if (*REGISTER_NAME (regnum
) == '\0')
4243 continue; /* unused register */
4244 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4245 break; /* end row: reached FP register */
4246 /* OK: get the data in raw format. */
4247 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4248 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4249 /* pad small registers */
4251 byte
< (mips_regsize (current_gdbarch
)
4252 - register_size (current_gdbarch
, regnum
));
4254 printf_filtered (" ");
4255 /* Now print the register value in hex, endian order. */
4256 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4257 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4258 byte
< register_size (current_gdbarch
, regnum
);
4260 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4262 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4265 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4266 fprintf_filtered (file
, " ");
4269 if (col
> 0) /* ie. if we actually printed anything... */
4270 fprintf_filtered (file
, "\n");
4275 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4278 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4279 struct frame_info
*frame
, int regnum
, int all
)
4281 if (regnum
!= -1) /* do one specified register */
4283 gdb_assert (regnum
>= NUM_REGS
);
4284 if (*(REGISTER_NAME (regnum
)) == '\0')
4285 error ("Not a valid register for the current processor type");
4287 mips_print_register (file
, frame
, regnum
, 0);
4288 fprintf_filtered (file
, "\n");
4291 /* do all (or most) registers */
4294 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4296 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4298 if (all
) /* true for "INFO ALL-REGISTERS" command */
4299 regnum
= print_fp_register_row (file
, frame
, regnum
);
4301 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4304 regnum
= print_gp_register_row (file
, frame
, regnum
);
4309 /* Is this a branch with a delay slot? */
4311 static int is_delayed (unsigned long);
4314 is_delayed (unsigned long insn
)
4317 for (i
= 0; i
< NUMOPCODES
; ++i
)
4318 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4319 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4321 return (i
< NUMOPCODES
4322 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4323 | INSN_COND_BRANCH_DELAY
4324 | INSN_COND_BRANCH_LIKELY
)));
4328 mips_step_skips_delay (CORE_ADDR pc
)
4330 char buf
[MIPS_INSTLEN
];
4332 /* There is no branch delay slot on MIPS16. */
4333 if (pc_is_mips16 (pc
))
4336 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4337 /* If error reading memory, guess that it is not a delayed branch. */
4339 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4343 /* Skip the PC past function prologue instructions (32-bit version).
4344 This is a helper function for mips_skip_prologue. */
4347 mips32_skip_prologue (CORE_ADDR pc
)
4351 int seen_sp_adjust
= 0;
4352 int load_immediate_bytes
= 0;
4354 /* Skip the typical prologue instructions. These are the stack adjustment
4355 instruction and the instructions that save registers on the stack
4356 or in the gcc frame. */
4357 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4359 unsigned long high_word
;
4361 inst
= mips_fetch_instruction (pc
);
4362 high_word
= (inst
>> 16) & 0xffff;
4364 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4365 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4367 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4368 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4370 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4371 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4372 && (inst
& 0x001F0000)) /* reg != $zero */
4375 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4377 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4379 continue; /* reg != $zero */
4381 /* move $s8,$sp. With different versions of gas this will be either
4382 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4383 Accept any one of these. */
4384 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4387 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4389 else if (high_word
== 0x3c1c) /* lui $gp,n */
4391 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4393 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4394 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4396 /* The following instructions load $at or $t0 with an immediate
4397 value in preparation for a stack adjustment via
4398 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4399 a local variable, so we accept them only before a stack adjustment
4400 instruction was seen. */
4401 else if (!seen_sp_adjust
)
4403 if (high_word
== 0x3c01 || /* lui $at,n */
4404 high_word
== 0x3c08) /* lui $t0,n */
4406 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4409 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4410 high_word
== 0x3508 || /* ori $t0,$t0,n */
4411 high_word
== 0x3401 || /* ori $at,$zero,n */
4412 high_word
== 0x3408) /* ori $t0,$zero,n */
4414 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4424 /* In a frameless function, we might have incorrectly
4425 skipped some load immediate instructions. Undo the skipping
4426 if the load immediate was not followed by a stack adjustment. */
4427 if (load_immediate_bytes
&& !seen_sp_adjust
)
4428 pc
-= load_immediate_bytes
;
4432 /* Skip the PC past function prologue instructions (16-bit version).
4433 This is a helper function for mips_skip_prologue. */
4436 mips16_skip_prologue (CORE_ADDR pc
)
4439 int extend_bytes
= 0;
4440 int prev_extend_bytes
;
4442 /* Table of instructions likely to be found in a function prologue. */
4445 unsigned short inst
;
4446 unsigned short mask
;
4453 , /* addiu $sp,offset */
4457 , /* daddiu $sp,offset */
4461 , /* sw reg,n($sp) */
4465 , /* sd reg,n($sp) */
4469 , /* sw $ra,n($sp) */
4473 , /* sd $ra,n($sp) */
4481 , /* sw $a0-$a3,n($s1) */
4485 , /* move reg,$a0-$a3 */
4489 , /* entry pseudo-op */
4493 , /* addiu $s1,$sp,n */
4496 } /* end of table marker */
4499 /* Skip the typical prologue instructions. These are the stack adjustment
4500 instruction and the instructions that save registers on the stack
4501 or in the gcc frame. */
4502 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4504 unsigned short inst
;
4507 inst
= mips_fetch_instruction (pc
);
4509 /* Normally we ignore an extend instruction. However, if it is
4510 not followed by a valid prologue instruction, we must adjust
4511 the pc back over the extend so that it won't be considered
4512 part of the prologue. */
4513 if ((inst
& 0xf800) == 0xf000) /* extend */
4515 extend_bytes
= MIPS16_INSTLEN
;
4518 prev_extend_bytes
= extend_bytes
;
4521 /* Check for other valid prologue instructions besides extend. */
4522 for (i
= 0; table
[i
].mask
!= 0; i
++)
4523 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4525 if (table
[i
].mask
!= 0) /* it was in table? */
4526 continue; /* ignore it */
4530 /* Return the current pc, adjusted backwards by 2 if
4531 the previous instruction was an extend. */
4532 return pc
- prev_extend_bytes
;
4538 /* To skip prologues, I use this predicate. Returns either PC itself
4539 if the code at PC does not look like a function prologue; otherwise
4540 returns an address that (if we're lucky) follows the prologue. If
4541 LENIENT, then we must skip everything which is involved in setting
4542 up the frame (it's OK to skip more, just so long as we don't skip
4543 anything which might clobber the registers which are being saved.
4544 We must skip more in the case where part of the prologue is in the
4545 delay slot of a non-prologue instruction). */
4548 mips_skip_prologue (CORE_ADDR pc
)
4550 /* See if we can determine the end of the prologue via the symbol table.
4551 If so, then return either PC, or the PC after the prologue, whichever
4554 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4556 if (post_prologue_pc
!= 0)
4557 return max (pc
, post_prologue_pc
);
4559 /* Can't determine prologue from the symbol table, need to examine
4562 if (pc_is_mips16 (pc
))
4563 return mips16_skip_prologue (pc
);
4565 return mips32_skip_prologue (pc
);
4568 /* Determine how a return value is stored within the MIPS register
4569 file, given the return type `valtype'. */
4571 struct return_value_word
4580 return_value_location (struct type
*valtype
,
4581 struct return_value_word
*hi
,
4582 struct return_value_word
*lo
)
4584 int len
= TYPE_LENGTH (valtype
);
4586 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4587 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4588 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4590 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4592 /* We need to break a 64bit float in two 32 bit halves and
4593 spread them across a floating-point register pair. */
4594 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4595 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4596 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4597 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4599 hi
->reg_offset
= lo
->reg_offset
;
4600 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4601 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4607 /* The floating point value fits in a single floating-point
4609 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4610 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4613 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4624 /* Locate a result possibly spread across two registers. */
4626 lo
->reg
= regnum
+ 0;
4627 hi
->reg
= regnum
+ 1;
4628 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4629 && len
< MIPS_SAVED_REGSIZE
)
4631 /* "un-left-justify" the value in the low register */
4632 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4637 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4638 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4639 && len
< MIPS_SAVED_REGSIZE
* 2
4640 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4641 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4643 /* "un-left-justify" the value spread across two registers. */
4644 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4645 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4647 hi
->len
= len
- lo
->len
;
4651 /* Only perform a partial copy of the second register. */
4654 if (len
> MIPS_SAVED_REGSIZE
)
4656 lo
->len
= MIPS_SAVED_REGSIZE
;
4657 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4665 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4666 && register_size (current_gdbarch
, regnum
) == 8
4667 && MIPS_SAVED_REGSIZE
== 4)
4669 /* Account for the fact that only the least-signficant part
4670 of the register is being used */
4671 lo
->reg_offset
+= 4;
4672 hi
->reg_offset
+= 4;
4675 hi
->buf_offset
= lo
->len
;
4679 /* Given a return value in `regbuf' with a type `valtype', extract and
4680 copy its value into `valbuf'. */
4683 mips_eabi_extract_return_value (struct type
*valtype
,
4687 struct return_value_word lo
;
4688 struct return_value_word hi
;
4689 return_value_location (valtype
, &hi
, &lo
);
4691 memcpy (valbuf
+ lo
.buf_offset
,
4692 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4696 memcpy (valbuf
+ hi
.buf_offset
,
4697 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4702 mips_o64_extract_return_value (struct type
*valtype
,
4706 struct return_value_word lo
;
4707 struct return_value_word hi
;
4708 return_value_location (valtype
, &hi
, &lo
);
4710 memcpy (valbuf
+ lo
.buf_offset
,
4711 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4715 memcpy (valbuf
+ hi
.buf_offset
,
4716 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4720 /* Given a return value in `valbuf' with a type `valtype', write it's
4721 value into the appropriate register. */
4724 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4726 char raw_buffer
[MAX_REGISTER_SIZE
];
4727 struct return_value_word lo
;
4728 struct return_value_word hi
;
4729 return_value_location (valtype
, &hi
, &lo
);
4731 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4732 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4733 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4734 register_size (current_gdbarch
, lo
.reg
));
4738 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4739 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4740 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4741 register_size (current_gdbarch
, hi
.reg
));
4746 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4748 char raw_buffer
[MAX_REGISTER_SIZE
];
4749 struct return_value_word lo
;
4750 struct return_value_word hi
;
4751 return_value_location (valtype
, &hi
, &lo
);
4753 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4754 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4755 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4756 register_size (current_gdbarch
, lo
.reg
));
4760 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4761 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4762 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4763 register_size (current_gdbarch
, hi
.reg
));
4767 /* O32 ABI stuff. */
4770 mips_o32_xfer_return_value (struct type
*type
,
4771 struct regcache
*regcache
,
4772 bfd_byte
*in
, const bfd_byte
*out
)
4774 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4775 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4776 && TYPE_LENGTH (type
) == 4
4777 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4779 /* A single-precision floating-point value. It fits in the
4780 least significant part of FP0. */
4782 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4783 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
, TYPE_LENGTH (type
),
4784 TARGET_BYTE_ORDER
, in
, out
, 0);
4786 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4787 && TYPE_LENGTH (type
) == 8
4788 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4790 /* A double-precision floating-point value. The most
4791 significant part goes in FP1, and the least significant in
4794 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4795 switch (TARGET_BYTE_ORDER
)
4797 case BFD_ENDIAN_LITTLE
:
4798 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0, 4,
4799 TARGET_BYTE_ORDER
, in
, out
, 0);
4800 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1, 4,
4801 TARGET_BYTE_ORDER
, in
, out
, 4);
4803 case BFD_ENDIAN_BIG
:
4804 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1, 4,
4805 TARGET_BYTE_ORDER
, in
, out
, 0);
4806 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0, 4,
4807 TARGET_BYTE_ORDER
, in
, out
, 4);
4810 internal_error (__FILE__
, __LINE__
, "bad switch");
4814 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4815 && TYPE_NFIELDS (type
) <= 2
4816 && TYPE_NFIELDS (type
) >= 1
4817 && ((TYPE_NFIELDS (type
) == 1
4818 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4820 || (TYPE_NFIELDS (type
) == 2
4821 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4823 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4825 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4827 /* A struct that contains one or two floats. Each value is part
4828 in the least significant part of their floating point
4830 bfd_byte reg
[MAX_REGISTER_SIZE
];
4833 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4834 field
< TYPE_NFIELDS (type
);
4835 field
++, regnum
+= 2)
4837 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4840 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4841 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4842 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4843 TARGET_BYTE_ORDER
, in
, out
, offset
);
4848 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4849 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4851 /* A structure or union. Extract the left justified value,
4852 regardless of the byte order. I.e. DO NOT USE
4856 for (offset
= 0, regnum
= V0_REGNUM
;
4857 offset
< TYPE_LENGTH (type
);
4858 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4860 int xfer
= register_size (current_gdbarch
, regnum
);
4861 if (offset
+ xfer
> TYPE_LENGTH (type
))
4862 xfer
= TYPE_LENGTH (type
) - offset
;
4864 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4865 offset
, xfer
, regnum
);
4866 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4867 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
4873 /* A scalar extract each part but least-significant-byte
4874 justified. o32 thinks registers are 4 byte, regardless of
4875 the ISA. mips_stack_argsize controls this. */
4878 for (offset
= 0, regnum
= V0_REGNUM
;
4879 offset
< TYPE_LENGTH (type
);
4880 offset
+= mips_stack_argsize (), regnum
++)
4882 int xfer
= mips_stack_argsize ();
4884 if (offset
+ xfer
> TYPE_LENGTH (type
))
4885 xfer
= TYPE_LENGTH (type
) - offset
;
4887 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4888 offset
, xfer
, regnum
);
4889 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4890 TARGET_BYTE_ORDER
, in
, out
, offset
);
4896 mips_o32_extract_return_value (struct type
*type
,
4897 struct regcache
*regcache
,
4900 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4904 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4906 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4909 /* N32/N44 ABI stuff. */
4912 mips_n32n64_xfer_return_value (struct type
*type
,
4913 struct regcache
*regcache
,
4914 bfd_byte
*in
, const bfd_byte
*out
)
4916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4917 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4918 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4920 /* A floating-point value belongs in the least significant part
4923 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4924 mips_xfer_register (regcache
, NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
, TYPE_LENGTH (type
),
4925 TARGET_BYTE_ORDER
, in
, out
, 0);
4927 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4928 && TYPE_NFIELDS (type
) <= 2
4929 && TYPE_NFIELDS (type
) >= 1
4930 && ((TYPE_NFIELDS (type
) == 1
4931 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4933 || (TYPE_NFIELDS (type
) == 2
4934 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4936 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4938 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4940 /* A struct that contains one or two floats. Each value is part
4941 in the least significant part of their floating point
4943 bfd_byte reg
[MAX_REGISTER_SIZE
];
4946 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4947 field
< TYPE_NFIELDS (type
);
4948 field
++, regnum
+= 2)
4950 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4953 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4954 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4955 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4956 TARGET_BYTE_ORDER
, in
, out
, offset
);
4959 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4960 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4962 /* A structure or union. Extract the left justified value,
4963 regardless of the byte order. I.e. DO NOT USE
4967 for (offset
= 0, regnum
= V0_REGNUM
;
4968 offset
< TYPE_LENGTH (type
);
4969 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4971 int xfer
= register_size (current_gdbarch
, regnum
);
4972 if (offset
+ xfer
> TYPE_LENGTH (type
))
4973 xfer
= TYPE_LENGTH (type
) - offset
;
4975 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4976 offset
, xfer
, regnum
);
4977 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4978 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
4983 /* A scalar extract each part but least-significant-byte
4987 for (offset
= 0, regnum
= V0_REGNUM
;
4988 offset
< TYPE_LENGTH (type
);
4989 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4991 int xfer
= register_size (current_gdbarch
, regnum
);
4993 if (offset
+ xfer
> TYPE_LENGTH (type
))
4994 xfer
= TYPE_LENGTH (type
) - offset
;
4996 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4997 offset
, xfer
, regnum
);
4998 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4999 TARGET_BYTE_ORDER
, in
, out
, offset
);
5005 mips_n32n64_extract_return_value (struct type
*type
,
5006 struct regcache
*regcache
,
5009 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
5013 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
5015 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
5019 mips_extract_struct_value_address (struct regcache
*regcache
)
5021 /* FIXME: This will only work at random. The caller passes the
5022 struct_return address in V0, but it is not preserved. It may
5023 still be there, or this may be a random value. */
5026 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5030 /* Exported procedure: Is PC in the signal trampoline code */
5033 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5035 if (sigtramp_address
== 0)
5037 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5040 /* Root of all "set mips "/"show mips " commands. This will eventually be
5041 used for all MIPS-specific commands. */
5044 show_mips_command (char *args
, int from_tty
)
5046 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5050 set_mips_command (char *args
, int from_tty
)
5052 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5053 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5056 /* Commands to show/set the MIPS FPU type. */
5059 show_mipsfpu_command (char *args
, int from_tty
)
5062 switch (MIPS_FPU_TYPE
)
5064 case MIPS_FPU_SINGLE
:
5065 fpu
= "single-precision";
5067 case MIPS_FPU_DOUBLE
:
5068 fpu
= "double-precision";
5071 fpu
= "absent (none)";
5074 internal_error (__FILE__
, __LINE__
, "bad switch");
5076 if (mips_fpu_type_auto
)
5077 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5080 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5086 set_mipsfpu_command (char *args
, int from_tty
)
5088 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5089 show_mipsfpu_command (args
, from_tty
);
5093 set_mipsfpu_single_command (char *args
, int from_tty
)
5095 mips_fpu_type
= MIPS_FPU_SINGLE
;
5096 mips_fpu_type_auto
= 0;
5097 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5101 set_mipsfpu_double_command (char *args
, int from_tty
)
5103 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5104 mips_fpu_type_auto
= 0;
5105 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5109 set_mipsfpu_none_command (char *args
, int from_tty
)
5111 mips_fpu_type
= MIPS_FPU_NONE
;
5112 mips_fpu_type_auto
= 0;
5113 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5117 set_mipsfpu_auto_command (char *args
, int from_tty
)
5119 mips_fpu_type_auto
= 1;
5122 /* Command to set the processor type. */
5125 mips_set_processor_type_command (char *args
, int from_tty
)
5129 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
5131 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5132 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5133 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
5135 /* Restore the value. */
5136 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5141 if (!mips_set_processor_type (tmp_mips_processor_type
))
5143 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
5144 /* Restore its value. */
5145 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5150 mips_show_processor_type_command (char *args
, int from_tty
)
5154 /* Modify the actual processor type. */
5157 mips_set_processor_type (char *str
)
5164 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5166 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5168 mips_processor_type
= str
;
5169 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5171 /* FIXME tweak fpu flag too */
5178 /* Attempt to identify the particular processor model by reading the
5182 mips_read_processor_type (void)
5186 prid
= read_register (PRID_REGNUM
);
5188 if ((prid
& ~0xf) == 0x700)
5189 return savestring ("r3041", strlen ("r3041"));
5194 /* Just like reinit_frame_cache, but with the right arguments to be
5195 callable as an sfunc. */
5198 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5199 struct cmd_list_element
*c
)
5201 reinit_frame_cache ();
5205 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5208 mips_extra_func_info_t proc_desc
;
5210 /* Search for the function containing this address. Set the low bit
5211 of the address when searching, in case we were given an even address
5212 that is the start of a 16-bit function. If we didn't do this,
5213 the search would fail because the symbol table says the function
5214 starts at an odd address, i.e. 1 byte past the given address. */
5215 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5216 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5218 /* Make an attempt to determine if this is a 16-bit function. If
5219 the procedure descriptor exists and the address therein is odd,
5220 it's definitely a 16-bit function. Otherwise, we have to just
5221 guess that if the address passed in is odd, it's 16-bits. */
5222 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5223 disassembler needs to be able to locally determine the ISA, and
5224 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5228 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5229 info
->mach
= bfd_mach_mips16
;
5233 if (pc_is_mips16 (memaddr
))
5234 info
->mach
= bfd_mach_mips16
;
5237 /* Round down the instruction address to the appropriate boundary. */
5238 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5240 /* Set the disassembler options. */
5241 if (tdep
->mips_abi
== MIPS_ABI_N32
5242 || tdep
->mips_abi
== MIPS_ABI_N64
)
5244 /* Set up the disassembler info, so that we get the right
5245 register names from libopcodes. */
5246 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5247 info
->disassembler_options
= "gpr-names=n32";
5249 info
->disassembler_options
= "gpr-names=64";
5250 info
->flavour
= bfd_target_elf_flavour
;
5253 /* This string is not recognized explicitly by the disassembler,
5254 but it tells the disassembler to not try to guess the ABI from
5255 the bfd elf headers, such that, if the user overrides the ABI
5256 of a program linked as NewABI, the disassembly will follow the
5257 register naming conventions specified by the user. */
5258 info
->disassembler_options
= "gpr-names=32";
5260 /* Call the appropriate disassembler based on the target endian-ness. */
5261 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5262 return print_insn_big_mips (memaddr
, info
);
5264 return print_insn_little_mips (memaddr
, info
);
5267 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5268 counter value to determine whether a 16- or 32-bit breakpoint should be
5269 used. It returns a pointer to a string of bytes that encode a breakpoint
5270 instruction, stores the length of the string to *lenptr, and adjusts pc
5271 (if necessary) to point to the actual memory location where the
5272 breakpoint should be inserted. */
5274 static const unsigned char *
5275 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5277 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5279 if (pc_is_mips16 (*pcptr
))
5281 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5282 *pcptr
= unmake_mips16_addr (*pcptr
);
5283 *lenptr
= sizeof (mips16_big_breakpoint
);
5284 return mips16_big_breakpoint
;
5288 /* The IDT board uses an unusual breakpoint value, and
5289 sometimes gets confused when it sees the usual MIPS
5290 breakpoint instruction. */
5291 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5292 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5293 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5295 *lenptr
= sizeof (big_breakpoint
);
5297 if (strcmp (target_shortname
, "mips") == 0)
5298 return idt_big_breakpoint
;
5299 else if (strcmp (target_shortname
, "ddb") == 0
5300 || strcmp (target_shortname
, "pmon") == 0
5301 || strcmp (target_shortname
, "lsi") == 0)
5302 return pmon_big_breakpoint
;
5304 return big_breakpoint
;
5309 if (pc_is_mips16 (*pcptr
))
5311 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5312 *pcptr
= unmake_mips16_addr (*pcptr
);
5313 *lenptr
= sizeof (mips16_little_breakpoint
);
5314 return mips16_little_breakpoint
;
5318 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5319 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5320 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5322 *lenptr
= sizeof (little_breakpoint
);
5324 if (strcmp (target_shortname
, "mips") == 0)
5325 return idt_little_breakpoint
;
5326 else if (strcmp (target_shortname
, "ddb") == 0
5327 || strcmp (target_shortname
, "pmon") == 0
5328 || strcmp (target_shortname
, "lsi") == 0)
5329 return pmon_little_breakpoint
;
5331 return little_breakpoint
;
5336 /* If PC is in a mips16 call or return stub, return the address of the target
5337 PC, which is either the callee or the caller. There are several
5338 cases which must be handled:
5340 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5341 target PC is in $31 ($ra).
5342 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5343 and the target PC is in $2.
5344 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5345 before the jal instruction, this is effectively a call stub
5346 and the the target PC is in $2. Otherwise this is effectively
5347 a return stub and the target PC is in $18.
5349 See the source code for the stubs in gcc/config/mips/mips16.S for
5352 This function implements the SKIP_TRAMPOLINE_CODE macro.
5356 mips_skip_stub (CORE_ADDR pc
)
5359 CORE_ADDR start_addr
;
5361 /* Find the starting address and name of the function containing the PC. */
5362 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5365 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5366 target PC is in $31 ($ra). */
5367 if (strcmp (name
, "__mips16_ret_sf") == 0
5368 || strcmp (name
, "__mips16_ret_df") == 0)
5369 return read_signed_register (RA_REGNUM
);
5371 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5373 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5374 and the target PC is in $2. */
5375 if (name
[19] >= '0' && name
[19] <= '9')
5376 return read_signed_register (2);
5378 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5379 before the jal instruction, this is effectively a call stub
5380 and the the target PC is in $2. Otherwise this is effectively
5381 a return stub and the target PC is in $18. */
5382 else if (name
[19] == 's' || name
[19] == 'd')
5384 if (pc
== start_addr
)
5386 /* Check if the target of the stub is a compiler-generated
5387 stub. Such a stub for a function bar might have a name
5388 like __fn_stub_bar, and might look like this:
5393 la $1,bar (becomes a lui/addiu pair)
5395 So scan down to the lui/addi and extract the target
5396 address from those two instructions. */
5398 CORE_ADDR target_pc
= read_signed_register (2);
5402 /* See if the name of the target function is __fn_stub_*. */
5403 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5405 if (strncmp (name
, "__fn_stub_", 10) != 0
5406 && strcmp (name
, "etext") != 0
5407 && strcmp (name
, "_etext") != 0)
5410 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5411 The limit on the search is arbitrarily set to 20
5412 instructions. FIXME. */
5413 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5415 inst
= mips_fetch_instruction (target_pc
);
5416 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5417 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5418 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5419 return pc
| (inst
& 0xffff); /* low word */
5422 /* Couldn't find the lui/addui pair, so return stub address. */
5426 /* This is the 'return' part of a call stub. The return
5427 address is in $r18. */
5428 return read_signed_register (18);
5431 return 0; /* not a stub */
5435 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5436 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5439 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5441 CORE_ADDR start_addr
;
5443 /* Find the starting address of the function containing the PC. If the
5444 caller didn't give us a name, look it up at the same time. */
5445 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5448 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5450 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5451 if (name
[19] >= '0' && name
[19] <= '9')
5453 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5454 before the jal instruction, this is effectively a call stub. */
5455 else if (name
[19] == 's' || name
[19] == 'd')
5456 return pc
== start_addr
;
5459 return 0; /* not a stub */
5463 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5464 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5467 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5469 CORE_ADDR start_addr
;
5471 /* Find the starting address of the function containing the PC. */
5472 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5475 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5476 if (strcmp (name
, "__mips16_ret_sf") == 0
5477 || strcmp (name
, "__mips16_ret_df") == 0)
5480 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5481 i.e. after the jal instruction, this is effectively a return stub. */
5482 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5483 && (name
[19] == 's' || name
[19] == 'd')
5484 && pc
!= start_addr
)
5487 return 0; /* not a stub */
5491 /* Return non-zero if the PC is in a library helper function that should
5492 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5495 mips_ignore_helper (CORE_ADDR pc
)
5499 /* Find the starting address and name of the function containing the PC. */
5500 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5503 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5504 that we want to ignore. */
5505 return (strcmp (name
, "__mips16_ret_sf") == 0
5506 || strcmp (name
, "__mips16_ret_df") == 0);
5510 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5511 the register stored on the stack (32) is different to its real raw
5512 size (64). The below ensures that registers are fetched from the
5513 stack using their ABI size and then stored into the RAW_BUFFER
5514 using their raw size.
5516 The alternative to adding this function would be to add an ABI
5517 macro - REGISTER_STACK_SIZE(). */
5520 mips_get_saved_register (char *raw_buffer
,
5523 struct frame_info
*frame
,
5525 enum lval_type
*lvalp
)
5528 enum lval_type lvalx
;
5532 /* Always a pseudo. */
5533 gdb_assert (regnum
>= NUM_REGS
);
5535 /* Make certain that all needed parameters are present. */
5540 if (optimizedp
== NULL
)
5541 optimizedp
= &optimizedx
;
5543 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5544 /* The SP_REGNUM is special, its value is stored in saved_regs.
5545 In fact, it is so special that it can even only be fetched
5546 using a raw register number! Once this code as been converted
5547 to frame-unwind the problem goes away. */
5548 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5549 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5550 &realnumx
, raw_buffer
);
5552 /* Get it from the next frame. */
5553 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5554 regnum
, optimizedp
, lvalp
, addrp
,
5555 &realnumx
, raw_buffer
);
5558 /* Immediately after a function call, return the saved pc.
5559 Can't always go through the frames for this because on some machines
5560 the new frame is not set up until the new function executes
5561 some instructions. */
5564 mips_saved_pc_after_call (struct frame_info
*frame
)
5566 return read_signed_register (RA_REGNUM
);
5570 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5571 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5574 mips_stab_reg_to_regnum (int num
)
5577 if (num
>= 0 && num
< 32)
5579 else if (num
>= 38 && num
< 70)
5580 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5582 regnum
= mips_regnum (current_gdbarch
)->hi
;
5584 regnum
= mips_regnum (current_gdbarch
)->lo
;
5586 /* This will hopefully (eventually) provoke a warning. Should
5587 we be calling complaint() here? */
5588 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5589 return NUM_REGS
+ regnum
;
5593 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5594 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5597 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5600 if (num
>= 0 && num
< 32)
5602 else if (num
>= 32 && num
< 64)
5603 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5605 regnum
= mips_regnum (current_gdbarch
)->hi
;
5607 regnum
= mips_regnum (current_gdbarch
)->lo
;
5609 /* This will hopefully (eventually) provoke a warning. Should we
5610 be calling complaint() here? */
5611 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5612 return NUM_REGS
+ regnum
;
5616 mips_register_sim_regno (int regnum
)
5618 /* Only makes sense to supply raw registers. */
5619 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5620 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5621 decide if it is valid. Should instead define a standard sim/gdb
5622 register numbering scheme. */
5623 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5624 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5627 return LEGACY_SIM_REGNO_IGNORE
;
5631 /* Convert an integer into an address. By first converting the value
5632 into a pointer and then extracting it signed, the address is
5633 guarenteed to be correctly sign extended. */
5636 mips_integer_to_address (struct type
*type
, void *buf
)
5638 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5639 LONGEST val
= unpack_long (type
, buf
);
5640 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5641 return extract_signed_integer (tmp
,
5642 TYPE_LENGTH (builtin_type_void_data_ptr
));
5646 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5648 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5649 const char *name
= bfd_get_section_name (abfd
, sect
);
5651 if (*abip
!= MIPS_ABI_UNKNOWN
)
5654 if (strncmp (name
, ".mdebug.", 8) != 0)
5657 if (strcmp (name
, ".mdebug.abi32") == 0)
5658 *abip
= MIPS_ABI_O32
;
5659 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5660 *abip
= MIPS_ABI_N32
;
5661 else if (strcmp (name
, ".mdebug.abi64") == 0)
5662 *abip
= MIPS_ABI_N64
;
5663 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5664 *abip
= MIPS_ABI_O64
;
5665 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5666 *abip
= MIPS_ABI_EABI32
;
5667 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5668 *abip
= MIPS_ABI_EABI64
;
5670 warning ("unsupported ABI %s.", name
+ 8);
5673 static enum mips_abi
5674 global_mips_abi (void)
5678 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5679 if (mips_abi_strings
[i
] == mips_abi_string
)
5680 return (enum mips_abi
) i
;
5682 internal_error (__FILE__
, __LINE__
,
5683 "unknown ABI string");
5686 static struct gdbarch
*
5687 mips_gdbarch_init (struct gdbarch_info info
,
5688 struct gdbarch_list
*arches
)
5690 struct gdbarch
*gdbarch
;
5691 struct gdbarch_tdep
*tdep
;
5693 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5700 /* First of all, extract the elf_flags, if available. */
5701 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5702 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5705 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5706 switch ((elf_flags
& EF_MIPS_ABI
))
5708 case E_MIPS_ABI_O32
:
5709 mips_abi
= MIPS_ABI_O32
;
5711 case E_MIPS_ABI_O64
:
5712 mips_abi
= MIPS_ABI_O64
;
5714 case E_MIPS_ABI_EABI32
:
5715 mips_abi
= MIPS_ABI_EABI32
;
5717 case E_MIPS_ABI_EABI64
:
5718 mips_abi
= MIPS_ABI_EABI64
;
5721 if ((elf_flags
& EF_MIPS_ABI2
))
5722 mips_abi
= MIPS_ABI_N32
;
5724 mips_abi
= MIPS_ABI_UNKNOWN
;
5728 /* GCC creates a pseudo-section whose name describes the ABI. */
5729 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5730 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5732 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5733 Use the ABI from the last architecture if there is one. */
5734 if (info
.abfd
== NULL
&& arches
!= NULL
)
5735 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5737 /* Try the architecture for any hint of the correct ABI. */
5738 if (mips_abi
== MIPS_ABI_UNKNOWN
5739 && info
.bfd_arch_info
!= NULL
5740 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5742 switch (info
.bfd_arch_info
->mach
)
5744 case bfd_mach_mips3900
:
5745 mips_abi
= MIPS_ABI_EABI32
;
5747 case bfd_mach_mips4100
:
5748 case bfd_mach_mips5000
:
5749 mips_abi
= MIPS_ABI_EABI64
;
5751 case bfd_mach_mips8000
:
5752 case bfd_mach_mips10000
:
5753 /* On Irix, ELF64 executables use the N64 ABI. The
5754 pseudo-sections which describe the ABI aren't present
5755 on IRIX. (Even for executables created by gcc.) */
5756 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5757 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5758 mips_abi
= MIPS_ABI_N64
;
5760 mips_abi
= MIPS_ABI_N32
;
5765 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5766 mips_abi
= MIPS_ABI_O32
;
5768 /* Now that we have found what the ABI for this binary would be,
5769 check whether the user is overriding it. */
5770 found_abi
= mips_abi
;
5771 wanted_abi
= global_mips_abi ();
5772 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5773 mips_abi
= wanted_abi
;
5777 fprintf_unfiltered (gdb_stdlog
,
5778 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5780 fprintf_unfiltered (gdb_stdlog
,
5781 "mips_gdbarch_init: mips_abi = %d\n",
5783 fprintf_unfiltered (gdb_stdlog
,
5784 "mips_gdbarch_init: found_mips_abi = %d\n",
5788 /* try to find a pre-existing architecture */
5789 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5791 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5793 /* MIPS needs to be pedantic about which ABI the object is
5795 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5797 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5799 /* Need to be pedantic about which register virtual size is
5801 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5802 != mips64_transfers_32bit_regs_p
)
5804 return arches
->gdbarch
;
5807 /* Need a new architecture. Fill in a target specific vector. */
5808 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5809 gdbarch
= gdbarch_alloc (&info
, tdep
);
5810 tdep
->elf_flags
= elf_flags
;
5811 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5813 /* Initially set everything according to the default ABI/ISA. */
5814 set_gdbarch_short_bit (gdbarch
, 16);
5815 set_gdbarch_int_bit (gdbarch
, 32);
5816 set_gdbarch_float_bit (gdbarch
, 32);
5817 set_gdbarch_double_bit (gdbarch
, 64);
5818 set_gdbarch_long_double_bit (gdbarch
, 64);
5819 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5820 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5821 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5822 tdep
->found_abi
= found_abi
;
5823 tdep
->mips_abi
= mips_abi
;
5825 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5826 mips_elf_make_msymbol_special
);
5828 /* Fill in the OS dependant register numbers. */
5830 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5831 struct mips_regnum
);
5832 tdep
->regnum
= regnum
;
5833 if (info
.osabi
== GDB_OSABI_IRIX
)
5838 regnum
->badvaddr
= 66;
5841 regnum
->fp_control_status
= 69;
5842 regnum
->fp_implementation_revision
= 70;
5847 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5848 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5849 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5850 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5851 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5852 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5853 regnum
->fp_control_status
= 70;
5854 regnum
->fp_implementation_revision
= 71;
5857 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5858 replaced by read_pc? */
5859 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5860 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5861 set_gdbarch_num_regs (gdbarch
, num_regs
);
5862 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5868 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5869 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o32_store_return_value
);
5870 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5871 tdep
->mips_default_saved_regsize
= 4;
5872 tdep
->mips_default_stack_argsize
= 4;
5873 tdep
->mips_fp_register_double
= 0;
5874 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5875 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5876 tdep
->default_mask_address_p
= 0;
5877 set_gdbarch_long_bit (gdbarch
, 32);
5878 set_gdbarch_ptr_bit (gdbarch
, 32);
5879 set_gdbarch_long_long_bit (gdbarch
, 64);
5880 set_gdbarch_deprecated_reg_struct_has_addr
5881 (gdbarch
, mips_o32_reg_struct_has_addr
);
5882 set_gdbarch_use_struct_convention (gdbarch
,
5883 always_use_struct_convention
);
5886 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5887 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5888 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5889 tdep
->mips_default_saved_regsize
= 8;
5890 tdep
->mips_default_stack_argsize
= 8;
5891 tdep
->mips_fp_register_double
= 1;
5892 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5893 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5894 tdep
->default_mask_address_p
= 0;
5895 set_gdbarch_long_bit (gdbarch
, 32);
5896 set_gdbarch_ptr_bit (gdbarch
, 32);
5897 set_gdbarch_long_long_bit (gdbarch
, 64);
5898 set_gdbarch_deprecated_reg_struct_has_addr
5899 (gdbarch
, mips_o32_reg_struct_has_addr
);
5900 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5902 case MIPS_ABI_EABI32
:
5903 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5904 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5905 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5906 tdep
->mips_default_saved_regsize
= 4;
5907 tdep
->mips_default_stack_argsize
= 4;
5908 tdep
->mips_fp_register_double
= 0;
5909 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5910 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5911 tdep
->default_mask_address_p
= 0;
5912 set_gdbarch_long_bit (gdbarch
, 32);
5913 set_gdbarch_ptr_bit (gdbarch
, 32);
5914 set_gdbarch_long_long_bit (gdbarch
, 64);
5915 set_gdbarch_deprecated_reg_struct_has_addr
5916 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5917 set_gdbarch_use_struct_convention (gdbarch
,
5918 mips_eabi_use_struct_convention
);
5920 case MIPS_ABI_EABI64
:
5921 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5922 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5923 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5924 tdep
->mips_default_saved_regsize
= 8;
5925 tdep
->mips_default_stack_argsize
= 8;
5926 tdep
->mips_fp_register_double
= 1;
5927 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5928 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5929 tdep
->default_mask_address_p
= 0;
5930 set_gdbarch_long_bit (gdbarch
, 64);
5931 set_gdbarch_ptr_bit (gdbarch
, 64);
5932 set_gdbarch_long_long_bit (gdbarch
, 64);
5933 set_gdbarch_deprecated_reg_struct_has_addr
5934 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5935 set_gdbarch_use_struct_convention (gdbarch
,
5936 mips_eabi_use_struct_convention
);
5939 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5940 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5941 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5942 tdep
->mips_default_saved_regsize
= 8;
5943 tdep
->mips_default_stack_argsize
= 8;
5944 tdep
->mips_fp_register_double
= 1;
5945 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5946 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5947 tdep
->default_mask_address_p
= 0;
5948 set_gdbarch_long_bit (gdbarch
, 32);
5949 set_gdbarch_ptr_bit (gdbarch
, 32);
5950 set_gdbarch_long_long_bit (gdbarch
, 64);
5951 set_gdbarch_use_struct_convention (gdbarch
,
5952 mips_n32n64_use_struct_convention
);
5953 set_gdbarch_deprecated_reg_struct_has_addr
5954 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5957 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5958 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5959 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5960 tdep
->mips_default_saved_regsize
= 8;
5961 tdep
->mips_default_stack_argsize
= 8;
5962 tdep
->mips_fp_register_double
= 1;
5963 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5964 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5965 tdep
->default_mask_address_p
= 0;
5966 set_gdbarch_long_bit (gdbarch
, 64);
5967 set_gdbarch_ptr_bit (gdbarch
, 64);
5968 set_gdbarch_long_long_bit (gdbarch
, 64);
5969 set_gdbarch_use_struct_convention (gdbarch
,
5970 mips_n32n64_use_struct_convention
);
5971 set_gdbarch_deprecated_reg_struct_has_addr
5972 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5975 internal_error (__FILE__
, __LINE__
,
5976 "unknown ABI in switch");
5979 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5980 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5983 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5984 flag in object files because to do so would make it impossible to
5985 link with libraries compiled without "-gp32". This is
5986 unnecessarily restrictive.
5988 We could solve this problem by adding "-gp32" multilibs to gcc,
5989 but to set this flag before gcc is built with such multilibs will
5990 break too many systems.''
5992 But even more unhelpfully, the default linker output target for
5993 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5994 for 64-bit programs - you need to change the ABI to change this,
5995 and not all gcc targets support that currently. Therefore using
5996 this flag to detect 32-bit mode would do the wrong thing given
5997 the current gcc - it would make GDB treat these 64-bit programs
5998 as 32-bit programs by default. */
6000 /* enable/disable the MIPS FPU */
6001 if (!mips_fpu_type_auto
)
6002 tdep
->mips_fpu_type
= mips_fpu_type
;
6003 else if (info
.bfd_arch_info
!= NULL
6004 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6005 switch (info
.bfd_arch_info
->mach
)
6007 case bfd_mach_mips3900
:
6008 case bfd_mach_mips4100
:
6009 case bfd_mach_mips4111
:
6010 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
6012 case bfd_mach_mips4650
:
6013 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
6016 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6020 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6022 /* MIPS version of register names. NOTE: At present the MIPS
6023 register name management is part way between the old -
6024 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
6025 Further work on it is required. */
6026 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6027 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6028 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6029 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6030 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6032 /* Add/remove bits from an address. The MIPS needs be careful to
6033 ensure that all 32 bit addresses are sign extended to 64 bits. */
6034 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6036 /* There's a mess in stack frame creation. See comments in
6037 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6038 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6040 /* Map debug register numbers onto internal register numbers. */
6041 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6042 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6043 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6044 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6045 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6047 /* Initialize a frame */
6048 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6049 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6051 /* MIPS version of CALL_DUMMY */
6053 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6054 replaced by a command, and all targets will default to on stack
6055 (regardless of the stack's execute status). */
6056 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6057 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6058 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6059 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6060 set_gdbarch_deprecated_register_convertible (gdbarch
, mips_register_convertible
);
6061 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, mips_register_convert_to_virtual
);
6062 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, mips_register_convert_to_raw
);
6064 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6065 set_gdbarch_frameless_function_invocation (gdbarch
,
6066 generic_frameless_function_invocation_not
);
6067 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6068 set_gdbarch_frame_args_skip (gdbarch
, 0);
6070 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6072 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6073 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6074 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6076 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6077 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6079 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6080 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6081 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6083 set_gdbarch_function_start_offset (gdbarch
, 0);
6085 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6087 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6088 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6090 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6092 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6093 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6094 need to all be folded into the target vector. Since they are
6095 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6096 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6098 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6100 /* Hook in OS ABI-specific overrides, if they have been registered. */
6101 gdbarch_init_osabi (info
, gdbarch
);
6103 set_gdbarch_extract_struct_value_address (gdbarch
,
6104 mips_extract_struct_value_address
);
6106 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6108 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6109 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6115 mips_abi_update (char *ignore_args
, int from_tty
,
6116 struct cmd_list_element
*c
)
6118 struct gdbarch_info info
;
6120 /* Force the architecture to update, and (if it's a MIPS architecture)
6121 mips_gdbarch_init will take care of the rest. */
6122 gdbarch_info_init (&info
);
6123 gdbarch_update_p (info
);
6126 /* Print out which MIPS ABI is in use. */
6129 show_mips_abi (char *ignore_args
, int from_tty
)
6131 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6133 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6136 enum mips_abi global_abi
= global_mips_abi ();
6137 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6138 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6140 if (global_abi
== MIPS_ABI_UNKNOWN
)
6141 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6143 else if (global_abi
== actual_abi
)
6145 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6149 /* Probably shouldn't happen... */
6151 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6153 mips_abi_strings
[global_abi
]);
6159 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6165 int ef_mips_32bitmode
;
6166 /* determine the ISA */
6167 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6185 /* determine the size of a pointer */
6186 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6190 fprintf_unfiltered (file
,
6191 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6193 fprintf_unfiltered (file
,
6194 "mips_dump_tdep: ef_mips_arch = %d\n",
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6199 mips_abi_strings
[tdep
->mips_abi
]);
6200 fprintf_unfiltered (file
,
6201 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6202 mips_mask_address_p (),
6203 tdep
->default_mask_address_p
);
6205 fprintf_unfiltered (file
,
6206 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6207 FP_REGISTER_DOUBLE
);
6208 fprintf_unfiltered (file
,
6209 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6210 MIPS_DEFAULT_FPU_TYPE
,
6211 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6212 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6213 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6215 fprintf_unfiltered (file
,
6216 "mips_dump_tdep: MIPS_EABI = %d\n",
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6221 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6222 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6223 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6227 MIPS_DEFAULT_SAVED_REGSIZE
);
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6230 FP_REGISTER_DOUBLE
);
6231 fprintf_unfiltered (file
,
6232 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6233 MIPS_DEFAULT_STACK_ARGSIZE
);
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6236 MIPS_STACK_ARGSIZE
);
6237 fprintf_unfiltered (file
,
6238 "mips_dump_tdep: A0_REGNUM = %d\n",
6240 fprintf_unfiltered (file
,
6241 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6242 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6243 fprintf_unfiltered (file
,
6244 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6245 XSTRING (ATTACH_DETACH
));
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6248 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6249 fprintf_unfiltered (file
,
6250 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6251 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6252 fprintf_unfiltered (file
,
6253 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6254 FIRST_EMBED_REGNUM
);
6255 fprintf_unfiltered (file
,
6256 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6257 XSTRING (IGNORE_HELPER_CALL (PC
)));
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6260 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6261 fprintf_unfiltered (file
,
6262 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6263 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6264 fprintf_unfiltered (file
,
6265 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6267 #ifdef MACHINE_CPROC_FP_OFFSET
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6270 MACHINE_CPROC_FP_OFFSET
);
6272 #ifdef MACHINE_CPROC_PC_OFFSET
6273 fprintf_unfiltered (file
,
6274 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6275 MACHINE_CPROC_PC_OFFSET
);
6277 #ifdef MACHINE_CPROC_SP_OFFSET
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6280 MACHINE_CPROC_SP_OFFSET
);
6282 fprintf_unfiltered (file
,
6283 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6285 fprintf_unfiltered (file
,
6286 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6287 fprintf_unfiltered (file
,
6288 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6292 fprintf_unfiltered (file
,
6293 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6294 MIPS_LAST_ARG_REGNUM
,
6295 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6296 fprintf_unfiltered (file
,
6297 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6301 fprintf_unfiltered (file
,
6302 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6303 MIPS_SAVED_REGSIZE
);
6304 fprintf_unfiltered (file
,
6305 "mips_dump_tdep: PRID_REGNUM = %d\n",
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6311 fprintf_unfiltered (file
,
6312 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6323 fprintf_unfiltered (file
,
6324 "mips_dump_tdep: PROC_PC_REG = function?\n");
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6327 fprintf_unfiltered (file
,
6328 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: PS_REGNUM = %d\n",
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: RA_REGNUM = %d\n",
6338 fprintf_unfiltered (file
,
6339 "mips_dump_tdep: SAVED_BYTES = %d\n",
6343 fprintf_unfiltered (file
,
6344 "mips_dump_tdep: SAVED_FP = %d\n",
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: SAVED_PC = %d\n",
6352 fprintf_unfiltered (file
,
6353 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6354 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6360 fprintf_unfiltered (file
,
6361 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6362 SIGFRAME_FPREGSAVE_OFF
);
6363 fprintf_unfiltered (file
,
6364 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6366 fprintf_unfiltered (file
,
6367 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6368 SIGFRAME_REGSAVE_OFF
);
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6372 fprintf_unfiltered (file
,
6373 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6374 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6375 fprintf_unfiltered (file
,
6376 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6377 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6378 fprintf_unfiltered (file
,
6379 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6380 SOFTWARE_SINGLE_STEP_P ());
6381 fprintf_unfiltered (file
,
6382 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6383 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6384 #ifdef STACK_END_ADDR
6385 fprintf_unfiltered (file
,
6386 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6389 fprintf_unfiltered (file
,
6390 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6391 XSTRING (STEP_SKIPS_DELAY (PC
)));
6392 fprintf_unfiltered (file
,
6393 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6394 STEP_SKIPS_DELAY_P
);
6395 fprintf_unfiltered (file
,
6396 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6397 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6398 fprintf_unfiltered (file
,
6399 "mips_dump_tdep: T9_REGNUM = %d\n",
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6403 fprintf_unfiltered (file
,
6404 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6405 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6406 fprintf_unfiltered (file
,
6407 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6408 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6410 fprintf_unfiltered (file
,
6411 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6412 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6415 fprintf_unfiltered (file
,
6416 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6419 #ifdef TRACE_FLAVOR_SIZE
6420 fprintf_unfiltered (file
,
6421 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6425 fprintf_unfiltered (file
,
6426 "mips_dump_tdep: TRACE_SET # %s\n",
6427 XSTRING (TRACE_SET (X
,STATE
)));
6429 #ifdef UNUSED_REGNUM
6430 fprintf_unfiltered (file
,
6431 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6434 fprintf_unfiltered (file
,
6435 "mips_dump_tdep: V0_REGNUM = %d\n",
6437 fprintf_unfiltered (file
,
6438 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6439 (long) VM_MIN_ADDRESS
);
6440 fprintf_unfiltered (file
,
6441 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6443 fprintf_unfiltered (file
,
6444 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6448 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6451 _initialize_mips_tdep (void)
6453 static struct cmd_list_element
*mipsfpulist
= NULL
;
6454 struct cmd_list_element
*c
;
6456 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6457 if (MIPS_ABI_LAST
+ 1
6458 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6459 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6461 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6463 /* Add root prefix command for all "set mips"/"show mips" commands */
6464 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6465 "Various MIPS specific commands.",
6466 &setmipscmdlist
, "set mips ", 0, &setlist
);
6468 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6469 "Various MIPS specific commands.",
6470 &showmipscmdlist
, "show mips ", 0, &showlist
);
6472 /* Allow the user to override the saved register size. */
6473 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6476 &mips_saved_regsize_string
, "\
6477 Set size of general purpose registers saved on the stack.\n\
6478 This option can be set to one of:\n\
6479 32 - Force GDB to treat saved GP registers as 32-bit\n\
6480 64 - Force GDB to treat saved GP registers as 64-bit\n\
6481 auto - Allow GDB to use the target's default setting or autodetect the\n\
6482 saved GP register size from information contained in the executable.\n\
6487 /* Allow the user to override the argument stack size. */
6488 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6491 &mips_stack_argsize_string
, "\
6492 Set the amount of stack space reserved for each argument.\n\
6493 This option can be set to one of:\n\
6494 32 - Force GDB to allocate 32-bit chunks per argument\n\
6495 64 - Force GDB to allocate 64-bit chunks per argument\n\
6496 auto - Allow GDB to determine the correct setting from the current\n\
6497 target and executable (default)",
6501 /* Allow the user to override the ABI. */
6502 c
= add_set_enum_cmd
6503 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6504 "Set the ABI used by this program.\n"
6505 "This option can be set to one of:\n"
6506 " auto - the default ABI associated with the current binary\n"
6514 set_cmd_sfunc (c
, mips_abi_update
);
6515 add_cmd ("abi", class_obscure
, show_mips_abi
,
6516 "Show ABI in use by MIPS target", &showmipscmdlist
);
6518 /* Let the user turn off floating point and set the fence post for
6519 heuristic_proc_start. */
6521 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6522 "Set use of MIPS floating-point coprocessor.",
6523 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6524 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6525 "Select single-precision MIPS floating-point coprocessor.",
6527 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6528 "Select double-precision MIPS floating-point coprocessor.",
6530 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6531 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6532 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6533 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6534 "Select no MIPS floating-point coprocessor.",
6536 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6537 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6538 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6539 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6540 "Select MIPS floating-point coprocessor automatically.",
6542 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6543 "Show current use of MIPS floating-point coprocessor target.",
6546 /* We really would like to have both "0" and "unlimited" work, but
6547 command.c doesn't deal with that. So make it a var_zinteger
6548 because the user can always use "999999" or some such for unlimited. */
6549 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6550 (char *) &heuristic_fence_post
,
6552 Set the distance searched for the start of a function.\n\
6553 If you are debugging a stripped executable, GDB needs to search through the\n\
6554 program for the start of a function. This command sets the distance of the\n\
6555 search. The only need to set it is when debugging a stripped executable.",
6557 /* We need to throw away the frame cache when we set this, since it
6558 might change our ability to get backtraces. */
6559 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6560 add_show_from_set (c
, &showlist
);
6562 /* Allow the user to control whether the upper bits of 64-bit
6563 addresses should be zeroed. */
6564 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6565 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6566 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6567 allow GDB to determine the correct value.\n", "\
6568 Show zeroing of upper 32 bits of 64-bit addresses.",
6569 NULL
, show_mask_address
,
6570 &setmipscmdlist
, &showmipscmdlist
);
6572 /* Allow the user to control the size of 32 bit registers within the
6573 raw remote packet. */
6574 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6575 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6576 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6577 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6578 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6579 64 bits for others. Use \"off\" to disable compatibility mode", "\
6580 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6581 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6582 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6583 64 bits for others. Use \"off\" to disable compatibility mode",
6584 set_mips64_transfers_32bit_regs
, NULL
,
6585 &setlist
, &showlist
);
6587 /* Debug this files internals. */
6588 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6589 &mips_debug
, "Set mips debugging.\n\
6590 When non-zero, mips specific debugging is enabled.", &setdebuglist
),