1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
44 /* FIXME! this code assumes 4-byte instructions. */
45 #define MIPS_INSTLEN 4 /* Length of an instruction */
46 #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16*/
47 #define MIPS_NUMREGS 32 /* Number of integer or float registers */
48 typedef unsigned long t_inst
; /* Integer big enough to hold an instruction */
50 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
51 macros to test, set, or clear bit 0 of addresses. */
52 #define IS_MIPS16_ADDR(addr) ((addr) & 1)
53 #define MAKE_MIPS16_ADDR(addr) ((addr) | 1)
54 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
57 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
60 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
62 static void mips_print_register
PARAMS ((int, int));
64 static mips_extra_func_info_t
65 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
67 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
69 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
71 static void mips_set_fpu_command
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static void mips_show_fpu_command
PARAMS ((char *, int,
75 struct cmd_list_element
*));
77 void mips_set_processor_type_command
PARAMS ((char *, int));
79 int mips_set_processor_type
PARAMS ((char *));
81 static void mips_show_processor_type_command
PARAMS ((char *, int));
83 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
84 struct cmd_list_element
*));
86 static mips_extra_func_info_t
87 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
89 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
90 mips_extra_func_info_t proc_desc
));
92 /* This value is the model of MIPS in use. It is derived from the value
93 of the PrID register. */
95 char *mips_processor_type
;
97 char *tmp_mips_processor_type
;
99 /* Some MIPS boards don't support floating point, so we permit the
100 user to turn it off. */
102 enum mips_fpu_type mips_fpu
;
104 static char *mips_fpu_string
;
106 /* A set of original names, to be used when restoring back to generic
107 registers from a specific set. */
109 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
111 /* Names of IDT R3041 registers. */
113 char *mips_r3041_reg_names
[] = {
114 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
115 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
116 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
117 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
118 "sr", "lo", "hi", "bad", "cause","pc",
119 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
120 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
121 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
122 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
123 "fsr", "fir", "fp", "",
124 "", "", "bus", "ccfg", "", "", "", "",
125 "", "", "port", "cmp", "", "", "epc", "prid",
128 /* Names of IDT R3051 registers. */
130 char *mips_r3051_reg_names
[] = {
131 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
132 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
133 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
134 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
135 "sr", "lo", "hi", "bad", "cause","pc",
136 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
137 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
138 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
139 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
140 "fsr", "fir", "fp", "",
141 "inx", "rand", "elo", "", "ctxt", "", "", "",
142 "", "", "ehi", "", "", "", "epc", "prid",
145 /* Names of IDT R3081 registers. */
147 char *mips_r3081_reg_names
[] = {
148 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
149 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
150 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
151 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
152 "sr", "lo", "hi", "bad", "cause","pc",
153 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
154 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
155 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
156 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
157 "fsr", "fir", "fp", "",
158 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
159 "", "", "ehi", "", "", "", "epc", "prid",
162 /* Names of LSI 33k registers. */
164 char *mips_lsi33k_reg_names
[] = {
165 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
166 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
167 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
168 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
169 "epc", "hi", "lo", "sr", "cause","badvaddr",
170 "dcic", "bpc", "bda", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
182 } mips_processor_type_table
[] = {
183 { "generic", mips_generic_reg_names
},
184 { "r3041", mips_r3041_reg_names
},
185 { "r3051", mips_r3051_reg_names
},
186 { "r3071", mips_r3081_reg_names
},
187 { "r3081", mips_r3081_reg_names
},
188 { "lsi33k", mips_lsi33k_reg_names
},
192 /* Table to translate MIPS16 register field to actual register number. */
193 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
195 /* Heuristic_proc_start may hunt through the text section for a long
196 time across a 2400 baud serial line. Allows the user to limit this
199 static unsigned int heuristic_fence_post
= 0;
201 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
202 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
203 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
204 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
205 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
206 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
207 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
208 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
209 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
210 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
211 #define _PROC_MAGIC_ 0x0F0F0F0F
212 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
213 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
215 struct linked_proc_info
217 struct mips_extra_func_info info
;
218 struct linked_proc_info
*next
;
219 } *linked_proc_desc_table
= NULL
;
222 /* This returns the PC of the first inst after the prologue. If we can't
223 find the prologue, then return 0. */
226 after_prologue (pc
, proc_desc
)
228 mips_extra_func_info_t proc_desc
;
230 struct symtab_and_line sal
;
231 CORE_ADDR func_addr
, func_end
;
234 proc_desc
= find_proc_desc (pc
, NULL
);
238 /* If function is frameless, then we need to do it the hard way. I
239 strongly suspect that frameless always means prologueless... */
240 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
241 && PROC_FRAME_OFFSET (proc_desc
) == 0)
245 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
246 return 0; /* Unknown */
248 sal
= find_pc_line (func_addr
, 0);
250 if (sal
.end
< func_end
)
253 /* The line after the prologue is after the end of the function. In this
254 case, tell the caller to find the prologue the hard way. */
259 /* Decode a MIPS32 instruction that saves a register in the stack, and
260 set the appropriate bit in the general register mask or float register mask
261 to indicate which register is saved. This is a helper function
262 for mips_find_saved_regs. */
265 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
267 unsigned long *gen_mask
;
268 unsigned long *float_mask
;
272 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
273 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
274 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
276 /* It might be possible to use the instruction to
277 find the offset, rather than the code below which
278 is based on things being in a certain order in the
279 frame, but figuring out what the instruction's offset
280 is relative to might be a little tricky. */
281 reg
= (inst
& 0x001f0000) >> 16;
282 *gen_mask
|= (1 << reg
);
284 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
285 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
286 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
289 reg
= ((inst
& 0x001f0000) >> 16);
290 *float_mask
|= (1 << reg
);
294 /* Decode a MIPS16 instruction that saves a register in the stack, and
295 set the appropriate bit in the general register or float register mask
296 to indicate which register is saved. This is a helper function
297 for mips_find_saved_regs. */
300 mips16_decode_reg_save (inst
, gen_mask
)
302 unsigned long *gen_mask
;
304 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
306 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
307 *gen_mask
|= (1 << reg
);
309 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
311 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
312 *gen_mask
|= (1 << reg
);
314 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
315 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
316 *gen_mask
|= (1 << 31);
320 /* Fetch and return instruction from the specified location. If the PC
321 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
324 mips_fetch_instruction (addr
)
327 char buf
[MIPS_INSTLEN
];
331 if (IS_MIPS16_ADDR (addr
))
333 instlen
= MIPS16_INSTLEN
;
334 addr
= UNMAKE_MIPS16_ADDR (addr
);
337 instlen
= MIPS_INSTLEN
;
338 status
= read_memory_nobpt (addr
, buf
, instlen
);
340 memory_error (status
, addr
);
341 return extract_unsigned_integer (buf
, instlen
);
345 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
349 mips_find_saved_regs (fci
)
350 struct frame_info
*fci
;
353 CORE_ADDR reg_position
;
354 /* r0 bit means kernel trap */
356 /* What registers have been saved? Bitmasks. */
357 unsigned long gen_mask
, float_mask
;
358 mips_extra_func_info_t proc_desc
;
361 fci
->saved_regs
= (struct frame_saved_regs
*)
362 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
363 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
365 /* If it is the frame for sigtramp, the saved registers are located
366 in a sigcontext structure somewhere on the stack.
367 If the stack layout for sigtramp changes we might have to change these
368 constants and the companion fixup_sigtramp in mdebugread.c */
369 #ifndef SIGFRAME_BASE
370 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
371 above the sigtramp frame. */
372 #define SIGFRAME_BASE MIPS_REGSIZE
373 /* FIXME! Are these correct?? */
374 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
375 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
376 #define SIGFRAME_FPREGSAVE_OFF \
377 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
379 #ifndef SIGFRAME_REG_SIZE
380 /* FIXME! Is this correct?? */
381 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
383 if (fci
->signal_handler_caller
)
385 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
387 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
388 + ireg
* SIGFRAME_REG_SIZE
;
389 fci
->saved_regs
->regs
[ireg
] = reg_position
;
391 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
393 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
394 + ireg
* SIGFRAME_REG_SIZE
;
395 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
397 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
401 proc_desc
= fci
->proc_desc
;
402 if (proc_desc
== NULL
)
403 /* I'm not sure how/whether this can happen. Normally when we can't
404 find a proc_desc, we "synthesize" one using heuristic_proc_desc
405 and set the saved_regs right away. */
408 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
409 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
410 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
412 if (/* In any frame other than the innermost or a frame interrupted by
413 a signal, we assume that all registers have been saved.
414 This assumes that all register saves in a function happen before
415 the first function call. */
416 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
418 /* In a dummy frame we know exactly where things are saved. */
419 && !PROC_DESC_IS_DUMMY (proc_desc
)
421 /* Don't bother unless we are inside a function prologue. Outside the
422 prologue, we know where everything is. */
424 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
426 /* Not sure exactly what kernel_trap means, but if it means
427 the kernel saves the registers without a prologue doing it,
428 we better not examine the prologue to see whether registers
429 have been saved yet. */
432 /* We need to figure out whether the registers that the proc_desc
433 claims are saved have been saved yet. */
437 /* Bitmasks; set if we have found a save for the register. */
438 unsigned long gen_save_found
= 0;
439 unsigned long float_save_found
= 0;
442 /* If the address is odd, assume this is MIPS16 code. */
443 addr
= PROC_LOW_ADDR (proc_desc
);
444 instlen
= IS_MIPS16_ADDR (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
446 /* Scan through this function's instructions preceding the current
447 PC, and look for those that save registers. */
448 while (addr
< fci
->pc
)
450 inst
= mips_fetch_instruction (addr
);
451 if (IS_MIPS16_ADDR (addr
))
452 mips16_decode_reg_save (inst
, &gen_save_found
);
454 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
457 gen_mask
= gen_save_found
;
458 float_mask
= float_save_found
;
461 /* Fill in the offsets for the registers which gen_mask says
463 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
464 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
465 if (gen_mask
& 0x80000000)
467 fci
->saved_regs
->regs
[ireg
] = reg_position
;
468 reg_position
-= MIPS_REGSIZE
;
471 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
472 of that normally used by gcc. Therefore, we have to fetch the first
473 instruction of the function, and if it's an entry instruction that
474 saves $s0 or $s1, correct their saved addresses. */
475 if (IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc
)))
477 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
478 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
481 int sreg_count
= (inst
>> 6) & 3;
483 /* Check if the ra register was pushed on the stack. */
484 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
486 reg_position
-= MIPS_REGSIZE
;
488 /* Check if the s0 and s1 registers were pushed on the stack. */
489 for (reg
= 16; reg
< sreg_count
+16; reg
++)
491 fci
->saved_regs
->regs
[reg
] = reg_position
;
492 reg_position
-= MIPS_REGSIZE
;
497 /* Fill in the offsets for the registers which float_mask says
499 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
501 /* The freg_offset points to where the first *double* register
502 is saved. So skip to the high-order word. */
503 if (! GDB_TARGET_IS_MIPS64
)
504 reg_position
+= MIPS_REGSIZE
;
506 /* Fill in the offsets for the float registers which float_mask says
508 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
509 if (float_mask
& 0x80000000)
511 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
512 reg_position
-= MIPS_REGSIZE
;
515 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
519 read_next_frame_reg(fi
, regno
)
520 struct frame_info
*fi
;
523 for (; fi
; fi
= fi
->next
)
525 /* We have to get the saved sp from the sigcontext
526 if it is a signal handler frame. */
527 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
531 if (fi
->saved_regs
== NULL
)
532 mips_find_saved_regs (fi
);
533 if (fi
->saved_regs
->regs
[regno
])
534 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
537 return read_register (regno
);
540 /* mips_addr_bits_remove - remove useless address bits */
543 mips_addr_bits_remove (addr
)
546 #if GDB_TARGET_IS_MIPS64
547 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
548 && (strcmp(target_shortname
,"pmon")==0
549 || strcmp(target_shortname
,"ddb")==0
550 || strcmp(target_shortname
,"sim")==0))
552 /* This hack is a work-around for existing boards using PMON,
553 the simulator, and any other 64-bit targets that doesn't have
554 true 64-bit addressing. On these targets, the upper 32 bits
555 of addresses are ignored by the hardware. Thus, the PC or SP
556 are likely to have been sign extended to all 1s by instruction
557 sequences that load 32-bit addresses. For example, a typical
558 piece of code that loads an address is this:
559 lui $r2, <upper 16 bits>
560 ori $r2, <lower 16 bits>
561 But the lui sign-extends the value such that the upper 32 bits
562 may be all 1s. The workaround is simply to mask off these bits.
563 In the future, gcc may be changed to support true 64-bit
564 addressing, and this masking will have to be disabled. */
565 addr
&= (CORE_ADDR
)0xffffffff;
568 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
569 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
570 So we still have to mask off useless bits from addresses. */
571 addr
&= (CORE_ADDR
)0xffffffff;
578 mips_frame_saved_pc(frame
)
579 struct frame_info
*frame
;
582 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
583 /* We have to get the saved pc from the sigcontext
584 if it is a signal handler frame. */
585 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
586 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
588 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
589 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
591 saved_pc
= read_next_frame_reg(frame
, pcreg
);
593 return ADDR_BITS_REMOVE (saved_pc
);
596 static struct mips_extra_func_info temp_proc_desc
;
597 static struct frame_saved_regs temp_saved_regs
;
599 /* This fencepost looks highly suspicious to me. Removing it also
600 seems suspicious as it could affect remote debugging across serial
604 heuristic_proc_start(pc
)
612 pc
= ADDR_BITS_REMOVE (pc
);
614 fence
= start_pc
- heuristic_fence_post
;
615 if (start_pc
== 0) return 0;
617 if (heuristic_fence_post
== UINT_MAX
618 || fence
< VM_MIN_ADDRESS
)
619 fence
= VM_MIN_ADDRESS
;
621 instlen
= IS_MIPS16_ADDR (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
623 /* search back for previous return */
624 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
625 if (start_pc
< fence
)
627 /* It's not clear to me why we reach this point when
628 stop_soon_quietly, but with this test, at least we
629 don't print out warnings for every child forked (eg, on
630 decstation). 22apr93 rich@cygnus.com. */
631 if (!stop_soon_quietly
)
633 static int blurb_printed
= 0;
635 if (fence
== VM_MIN_ADDRESS
)
636 warning("Hit beginning of text section without finding");
638 warning("Hit heuristic-fence-post without finding");
640 warning("enclosing function for address 0x%s", paddr (pc
));
644 This warning occurs if you are debugging a function without any symbols\n\
645 (for example, in a stripped executable). In that case, you may wish to\n\
646 increase the size of the search with the `set heuristic-fence-post' command.\n\
648 Otherwise, you told GDB there was a function where there isn't one, or\n\
649 (more likely) you have encountered a bug in GDB.\n");
656 else if (IS_MIPS16_ADDR (start_pc
))
660 /* On MIPS16, any one of the following is likely to be the
665 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
666 inst
= mips_fetch_instruction (start_pc
);
667 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
668 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
669 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
670 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
672 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
673 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
678 else if (ABOUT_TO_RETURN(start_pc
))
680 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
685 /* skip nops (usually 1) 0 - is this */
686 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
687 start_pc
+= MIPS_INSTLEN
;
692 /* Fetch the immediate value from a MIPS16 instruction.
693 If the previous instruction was an EXTEND, use it to extend
694 the upper bits of the immediate value. This is a helper function
695 for mips16_heuristic_proc_desc. */
698 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
699 unsigned short prev_inst
; /* previous instruction */
700 unsigned short inst
; /* current current instruction */
701 int nbits
; /* number of bits in imm field */
702 int scale
; /* scale factor to be applied to imm */
703 int is_signed
; /* is the imm field signed? */
707 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
709 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
710 if (offset
& 0x8000) /* check for negative extend */
711 offset
= 0 - (0x10000 - (offset
& 0xffff));
712 return offset
| (inst
& 0x1f);
716 int max_imm
= 1 << nbits
;
717 int mask
= max_imm
- 1;
718 int sign_bit
= max_imm
>> 1;
720 offset
= inst
& mask
;
721 if (is_signed
&& (offset
& sign_bit
))
722 offset
= 0 - (max_imm
- offset
);
723 return offset
* scale
;
728 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
729 stream from start_pc to limit_pc. */
732 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
733 CORE_ADDR start_pc
, limit_pc
;
734 struct frame_info
*next_frame
;
738 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
739 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
740 unsigned inst
= 0; /* current instruction */
742 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
744 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
748 /* Save the previous instruction. If it's an EXTEND, we'll extract
749 the immediate offset extension from it in mips16_get_imm. */
752 /* Fetch and decode the instruction. */
753 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
754 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
755 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
757 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
758 if (offset
< 0) /* negative stack adjustment? */
759 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
761 /* Exit loop if a positive stack adjustment is found, which
762 usually means that the stack cleanup code in the function
763 epilogue is reached. */
766 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
768 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
769 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
770 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
771 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
773 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
775 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
776 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
777 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
778 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
780 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
782 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
783 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
784 temp_saved_regs
.regs
[31] = sp
+ offset
;
786 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
788 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
789 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
790 temp_saved_regs
.regs
[31] = sp
+ offset
;
792 else if (inst
== 0x673d) /* move $s1, $sp */
794 frame_addr
= read_next_frame_reg(next_frame
, 30);
795 PROC_FRAME_REG (&temp_proc_desc
) = 17;
797 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
799 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
800 frame_addr
= sp
+ offset
;
801 PROC_FRAME_REG (&temp_proc_desc
) = 17;
803 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
805 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
806 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
807 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
808 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
810 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
812 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
813 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
814 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
815 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
817 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
819 int areg_count
= (inst
>> 8) & 7;
820 int sreg_count
= (inst
>> 6) & 3;
822 /* The entry instruction always subtracts 32 from the SP. */
823 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
825 /* Check if a0-a3 were saved in the caller's argument save area. */
826 for (reg
= 4, offset
= 32; reg
< areg_count
+4; reg
++)
828 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
829 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
830 offset
-= MIPS_REGSIZE
;
833 /* Check if the ra register was pushed on the stack. */
837 PROC_REG_MASK(&temp_proc_desc
) |= 1 << 31;
838 temp_saved_regs
.regs
[31] = sp
+ offset
;
839 offset
-= MIPS_REGSIZE
;
842 /* Check if the s0 and s1 registers were pushed on the stack. */
843 for (reg
= 16; reg
< sreg_count
+16; reg
++)
845 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
846 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
847 offset
-= MIPS_REGSIZE
;
850 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
851 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
856 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
857 CORE_ADDR start_pc
, limit_pc
;
858 struct frame_info
*next_frame
;
862 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
864 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
865 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
867 unsigned long inst
, high_word
, low_word
;
870 /* Fetch the instruction. */
871 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
873 /* Save some code by pre-extracting some useful fields. */
874 high_word
= (inst
>> 16) & 0xffff;
875 low_word
= inst
& 0xffff;
876 reg
= high_word
& 0x1f;
878 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
879 || high_word
== 0x23bd /* addi $sp,$sp,-i */
880 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
882 if (low_word
& 0x8000) /* negative stack adjustment? */
883 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
885 /* Exit loop if a positive stack adjustment is found, which
886 usually means that the stack cleanup code in the function
887 epilogue is reached. */
890 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
892 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
893 temp_saved_regs
.regs
[reg
] = sp
+ low_word
;
895 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
897 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
898 but the register size used is only 32 bits. Make the address
899 for the saved register point to the lower 32 bits. */
900 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
901 temp_saved_regs
.regs
[reg
] = sp
+ low_word
+ 8 - MIPS_REGSIZE
;
903 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
905 /* Old gcc frame, r30 is virtual frame pointer. */
906 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
907 frame_addr
= sp
+ low_word
;
908 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
910 unsigned alloca_adjust
;
911 PROC_FRAME_REG (&temp_proc_desc
) = 30;
912 frame_addr
= read_next_frame_reg(next_frame
, 30);
913 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
914 if (alloca_adjust
> 0)
916 /* FP > SP + frame_size. This may be because
917 * of an alloca or somethings similar.
918 * Fix sp to "pre-alloca" value, and try again.
925 /* move $30,$sp. With different versions of gas this will be either
926 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
927 Accept any one of these. */
928 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
930 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
931 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
933 unsigned alloca_adjust
;
934 PROC_FRAME_REG (&temp_proc_desc
) = 30;
935 frame_addr
= read_next_frame_reg(next_frame
, 30);
936 alloca_adjust
= (unsigned)(frame_addr
- sp
);
937 if (alloca_adjust
> 0)
939 /* FP > SP + frame_size. This may be because
940 * of an alloca or somethings similar.
941 * Fix sp to "pre-alloca" value, and try again.
948 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
950 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
951 temp_saved_regs
.regs
[reg
] = frame_addr
+ low_word
;
956 static mips_extra_func_info_t
957 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
958 CORE_ADDR start_pc
, limit_pc
;
959 struct frame_info
*next_frame
;
961 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
963 if (start_pc
== 0) return NULL
;
964 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
965 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
966 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
967 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
968 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
970 if (start_pc
+ 200 < limit_pc
)
971 limit_pc
= start_pc
+ 200;
972 if (IS_MIPS16_ADDR (start_pc
))
973 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
975 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
976 return &temp_proc_desc
;
979 static mips_extra_func_info_t
980 non_heuristic_proc_desc (pc
, addrptr
)
985 mips_extra_func_info_t proc_desc
;
986 struct block
*b
= block_for_pc(pc
);
989 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
991 *addrptr
= startaddr
;
992 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
996 if (startaddr
> BLOCK_START (b
))
997 /* This is the "pathological" case referred to in a comment in
998 print_frame_info. It might be better to move this check into
1002 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1005 /* If we never found a PDR for this function in symbol reading, then
1006 examine prologues to find the information. */
1009 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1010 if (PROC_FRAME_REG (proc_desc
) == -1)
1020 static mips_extra_func_info_t
1021 find_proc_desc (pc
, next_frame
)
1023 struct frame_info
*next_frame
;
1025 mips_extra_func_info_t proc_desc
;
1026 CORE_ADDR startaddr
;
1028 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1032 /* IF this is the topmost frame AND
1033 * (this proc does not have debugging information OR
1034 * the PC is in the procedure prologue)
1035 * THEN create a "heuristic" proc_desc (by analyzing
1036 * the actual code) to replace the "official" proc_desc.
1038 if (next_frame
== NULL
)
1040 struct symtab_and_line val
;
1041 struct symbol
*proc_symbol
=
1042 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1046 val
= find_pc_line (BLOCK_START
1047 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1049 val
.pc
= val
.end
? val
.end
: pc
;
1051 if (!proc_symbol
|| pc
< val
.pc
)
1053 mips_extra_func_info_t found_heuristic
=
1054 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1056 if (found_heuristic
)
1057 proc_desc
= found_heuristic
;
1063 /* Is linked_proc_desc_table really necessary? It only seems to be used
1064 by procedure call dummys. However, the procedures being called ought
1065 to have their own proc_descs, and even if they don't,
1066 heuristic_proc_desc knows how to create them! */
1068 register struct linked_proc_info
*link
;
1070 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1071 if (PROC_LOW_ADDR(&link
->info
) <= pc
1072 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1076 startaddr
= heuristic_proc_start (pc
);
1079 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1085 get_frame_pointer(frame
, proc_desc
)
1086 struct frame_info
*frame
;
1087 mips_extra_func_info_t proc_desc
;
1089 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
1090 PROC_FRAME_REG(proc_desc
)) + PROC_FRAME_OFFSET(proc_desc
));
1093 mips_extra_func_info_t cached_proc_desc
;
1096 mips_frame_chain(frame
)
1097 struct frame_info
*frame
;
1099 mips_extra_func_info_t proc_desc
;
1100 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1102 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1105 proc_desc
= find_proc_desc(saved_pc
, frame
);
1109 cached_proc_desc
= proc_desc
;
1111 /* If no frame pointer and frame size is zero, we must be at end
1112 of stack (or otherwise hosed). If we don't check frame size,
1113 we loop forever if we see a zero size frame. */
1114 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1115 && PROC_FRAME_OFFSET (proc_desc
) == 0
1116 /* The previous frame from a sigtramp frame might be frameless
1117 and have frame size zero. */
1118 && !frame
->signal_handler_caller
)
1121 return get_frame_pointer (frame
, proc_desc
);
1125 init_extra_frame_info(fci
)
1126 struct frame_info
*fci
;
1130 /* Use proc_desc calculated in frame_chain */
1131 mips_extra_func_info_t proc_desc
=
1132 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1134 fci
->saved_regs
= NULL
;
1136 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1139 /* Fixup frame-pointer - only needed for top frame */
1140 /* This may not be quite right, if proc has a real frame register.
1141 Get the value of the frame relative sp, procedure might have been
1142 interrupted by a signal at it's very start. */
1143 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1144 && !PROC_DESC_IS_DUMMY (proc_desc
))
1145 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1147 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1149 if (proc_desc
== &temp_proc_desc
)
1153 /* Do not set the saved registers for a sigtramp frame,
1154 mips_find_saved_registers will do that for us.
1155 We can't use fci->signal_handler_caller, it is not yet set. */
1156 find_pc_partial_function (fci
->pc
, &name
,
1157 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1158 if (!IN_SIGTRAMP (fci
->pc
, name
))
1160 fci
->saved_regs
= (struct frame_saved_regs
*)
1161 obstack_alloc (&frame_cache_obstack
,
1162 sizeof (struct frame_saved_regs
));
1163 *fci
->saved_regs
= temp_saved_regs
;
1164 fci
->saved_regs
->regs
[PC_REGNUM
]
1165 = fci
->saved_regs
->regs
[RA_REGNUM
];
1169 /* hack: if argument regs are saved, guess these contain args */
1170 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1171 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1173 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1175 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1182 /* MIPS stack frames are almost impenetrable. When execution stops,
1183 we basically have to look at symbol information for the function
1184 that we stopped in, which tells us *which* register (if any) is
1185 the base of the frame pointer, and what offset from that register
1186 the frame itself is at.
1188 This presents a problem when trying to examine a stack in memory
1189 (that isn't executing at the moment), using the "frame" command. We
1190 don't have a PC, nor do we have any registers except SP.
1192 This routine takes two arguments, SP and PC, and tries to make the
1193 cached frames look as if these two arguments defined a frame on the
1194 cache. This allows the rest of info frame to extract the important
1195 arguments without difficulty. */
1198 setup_arbitrary_frame (argc
, argv
)
1203 error ("MIPS frame specifications require two arguments: sp and pc");
1205 return create_new_frame (argv
[0], argv
[1]);
1209 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1214 CORE_ADDR struct_addr
;
1222 /* Macros to round N up or down to the next A boundary; A must be
1224 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1225 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1227 /* First ensure that the stack and structure return address (if any)
1228 are properly aligned. The stack has to be 64-bit aligned even
1229 on 32-bit machines, because doubles must be 64-bit aligned. */
1230 sp
= ROUND_DOWN (sp
, 8);
1231 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1233 /* Now make space on the stack for the args. We allocate more
1234 than necessary for EABI, because the first few arguments are
1235 passed in registers, but that's OK. */
1236 for (argnum
= 0; argnum
< nargs
; argnum
++)
1237 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1238 sp
-= ROUND_UP (len
, 8);
1240 /* Initialize the integer and float register pointers. */
1242 float_argreg
= FPA0_REGNUM
;
1244 /* the struct_return pointer occupies the first parameter-passing reg */
1246 write_register (argreg
++, struct_addr
);
1248 /* The offset onto the stack at which we will start copying parameters
1249 (after the registers are used up) begins at 16 in the old ABI.
1250 This leaves room for the "home" area for register parameters. */
1251 stack_offset
= MIPS_EABI
? 0 : MIPS_REGSIZE
* 4;
1253 /* Now load as many as possible of the first arguments into
1254 registers, and push the rest onto the stack. Loop thru args
1255 from first to last. */
1256 for (argnum
= 0; argnum
< nargs
; argnum
++)
1259 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1260 value_ptr arg
= args
[argnum
];
1261 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1262 int len
= TYPE_LENGTH (arg_type
);
1263 enum type_code typecode
= TYPE_CODE (arg_type
);
1265 /* The EABI passes structures that do not fit in a register by
1266 reference. In all other cases, pass the structure by value. */
1267 if (typecode
== TYPE_CODE_STRUCT
&& MIPS_EABI
&& len
> MIPS_REGSIZE
)
1269 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1274 val
= (char *)VALUE_CONTENTS (arg
);
1276 /* 32-bit ABIs always start floating point arguments in an
1277 even-numbered floating point register. */
1278 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1279 && (float_argreg
& 1))
1282 /* Floating point arguments passed in registers have to be
1283 treated specially. On 32-bit architectures, doubles
1284 are passed in register pairs; the even register gets
1285 the low word, and the odd register gets the high word.
1286 On non-EABI processors, the first two floating point arguments are
1287 also copied to general registers, because MIPS16 functions
1288 don't use float registers for arguments. This duplication of
1289 arguments in general registers can't hurt non-MIPS16 functions
1290 because those registers are normally skipped. */
1291 if (typecode
== TYPE_CODE_FLT
1292 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1293 && mips_fpu
!= MIPS_FPU_NONE
)
1295 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1297 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1298 unsigned long regval
;
1300 /* Write the low word of the double to the even register(s). */
1301 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1302 write_register (float_argreg
++, regval
);
1304 write_register (argreg
+1, regval
);
1306 /* Write the high word of the double to the odd register(s). */
1307 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1308 write_register (float_argreg
++, regval
);
1311 write_register (argreg
, regval
);
1318 /* This is a floating point value that fits entirely
1319 in a single register. */
1320 CORE_ADDR regval
= extract_address (val
, len
);
1321 write_register (float_argreg
++, regval
);
1324 write_register (argreg
, regval
);
1325 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1331 /* Copy the argument to general registers or the stack in
1332 register-sized pieces. Large arguments are split between
1333 registers and stack. */
1336 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1338 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1340 CORE_ADDR regval
= extract_address (val
, partial_len
);
1342 /* It's a simple argument being passed in a general
1344 If the argument length is smaller than the register size,
1345 we have to adjust the argument on big endian targets.
1346 But don't do this adjustment on EABI targets. */
1347 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1348 && partial_len
< MIPS_REGSIZE
1350 regval
<<= ((MIPS_REGSIZE
- partial_len
) * TARGET_CHAR_BIT
);
1351 write_register (argreg
, regval
);
1354 /* If this is the old ABI, prevent subsequent floating
1355 point arguments from being passed in floating point
1358 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1362 /* Write this portion of the argument to the stack. */
1364 write_memory (sp
+ stack_offset
, val
, partial_len
);
1365 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1374 /* Set the return address register to point to the entry
1375 point of the program, where a breakpoint lies in wait. */
1376 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1378 /* Return adjusted stack pointer. */
1383 mips_push_register(CORE_ADDR
*sp
, int regno
)
1385 char buffer
[MAX_REGISTER_RAW_SIZE
];
1386 int regsize
= REGISTER_RAW_SIZE (regno
);
1389 read_register_gen (regno
, buffer
);
1390 write_memory (*sp
, buffer
, regsize
);
1393 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1394 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1397 mips_push_dummy_frame()
1400 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1401 xmalloc(sizeof(struct linked_proc_info
));
1402 mips_extra_func_info_t proc_desc
= &link
->info
;
1403 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1404 CORE_ADDR old_sp
= sp
;
1405 link
->next
= linked_proc_desc_table
;
1406 linked_proc_desc_table
= link
;
1408 /* FIXME! are these correct ? */
1409 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1410 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1411 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1412 #define FLOAT_SINGLE_REG_SAVE_MASK \
1413 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1415 * The registers we must save are all those not preserved across
1416 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1417 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1418 * and FP Control/Status registers.
1421 * Dummy frame layout:
1424 * Saved MMHI, MMLO, FPC_CSR
1429 * Saved D18 (i.e. F19, F18)
1431 * Saved D0 (i.e. F1, F0)
1432 * Argument build area and stack arguments written via mips_push_arguments
1436 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1437 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1438 PROC_FRAME_OFFSET(proc_desc
) = 0;
1439 mips_push_register (&sp
, PC_REGNUM
);
1440 mips_push_register (&sp
, HI_REGNUM
);
1441 mips_push_register (&sp
, LO_REGNUM
);
1442 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1444 /* Save general CPU registers */
1445 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1446 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1447 for (ireg
= 32; --ireg
>= 0; )
1448 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1449 mips_push_register (&sp
, ireg
);
1451 /* Save floating point registers starting with high order word */
1452 PROC_FREG_MASK(proc_desc
) =
1453 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1454 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1455 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1456 for (ireg
= 32; --ireg
>= 0; )
1457 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1458 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1460 /* Update the frame pointer for the call dummy and the stack pointer.
1461 Set the procedure's starting and ending addresses to point to the
1462 call dummy address at the entry point. */
1463 write_register (PUSH_FP_REGNUM
, old_sp
);
1464 write_register (SP_REGNUM
, sp
);
1465 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1466 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1467 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1468 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1474 register int regnum
;
1475 struct frame_info
*frame
= get_current_frame ();
1476 CORE_ADDR new_sp
= FRAME_FP (frame
);
1478 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1480 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1481 if (frame
->saved_regs
== NULL
)
1482 mips_find_saved_regs (frame
);
1483 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1485 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1486 && frame
->saved_regs
->regs
[regnum
])
1487 write_register (regnum
,
1488 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1491 write_register (SP_REGNUM
, new_sp
);
1492 flush_cached_frames ();
1494 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1496 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1498 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1500 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1502 if (&pi_ptr
->info
== proc_desc
)
1507 error ("Can't locate dummy extra frame info\n");
1509 if (prev_ptr
!= NULL
)
1510 prev_ptr
->next
= pi_ptr
->next
;
1512 linked_proc_desc_table
= pi_ptr
->next
;
1516 write_register (HI_REGNUM
,
1517 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1518 write_register (LO_REGNUM
,
1519 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1520 if (mips_fpu
!= MIPS_FPU_NONE
)
1521 write_register (FCRCS_REGNUM
,
1522 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1527 mips_print_register (regnum
, all
)
1530 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1532 /* Get the data in raw format. */
1533 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1535 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1539 /* If an even floating pointer register, also print as double. */
1540 if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+MIPS_NUMREGS
1541 && !((regnum
-FP0_REGNUM
) & 1))
1543 char dbuffer
[MAX_REGISTER_RAW_SIZE
];
1545 /* MIPS doubles are stored in a register pair with the least
1546 signficant register in the lower-numbered register. */
1547 read_relative_register_raw_bytes (regnum
+1, dbuffer
);
1548 read_relative_register_raw_bytes (regnum
, dbuffer
+MIPS_REGSIZE
);
1550 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1551 val_print (builtin_type_double
, dbuffer
, 0,
1552 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1553 printf_filtered ("); ");
1555 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1557 /* The problem with printing numeric register names (r26, etc.) is that
1558 the user can't use them on input. Probably the best solution is to
1559 fix it so that either the numeric or the funky (a2, etc.) names
1560 are accepted on input. */
1561 if (regnum
< MIPS_NUMREGS
)
1562 printf_filtered ("(r%d): ", regnum
);
1564 printf_filtered (": ");
1566 /* If virtual format is floating, print it that way. */
1567 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1568 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1569 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1570 /* Else print as integer in hex. */
1572 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1573 'x', 0, gdb_stdout
);
1576 /* Replacement for generic do_registers_info. */
1579 mips_do_registers_info (regnum
, fpregs
)
1585 if (*(reg_names
[regnum
]) == '\0')
1586 error ("Not a valid register for the current processor type");
1588 mips_print_register (regnum
, 0);
1589 printf_filtered ("\n");
1593 int did_newline
= 0;
1595 for (regnum
= 0; regnum
< NUM_REGS
; )
1597 if (((!fpregs
) && regnum
>= FP0_REGNUM
&& regnum
<= FCRIR_REGNUM
)
1598 || *(reg_names
[regnum
]) == '\0')
1603 mips_print_register (regnum
, 1);
1605 printf_filtered ("; ");
1607 if ((regnum
& 3) == 0)
1609 printf_filtered ("\n");
1614 printf_filtered ("\n");
1618 /* Return number of args passed to a frame. described by FIP.
1619 Can return -1, meaning no way to tell. */
1622 mips_frame_num_args (frame
)
1623 struct frame_info
*frame
;
1625 #if 0 /* FIXME Use or lose this! */
1626 struct chain_info_t
*p
;
1628 p
= mips_find_cached_frame (FRAME_FP (frame
));
1630 return p
->the_info
.numargs
;
1635 /* Is this a branch with a delay slot? */
1637 static int is_delayed
PARAMS ((unsigned long));
1644 for (i
= 0; i
< NUMOPCODES
; ++i
)
1645 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1646 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1648 return (i
< NUMOPCODES
1649 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1650 | INSN_COND_BRANCH_DELAY
1651 | INSN_COND_BRANCH_LIKELY
)));
1655 mips_step_skips_delay (pc
)
1658 char buf
[MIPS_INSTLEN
];
1660 /* There is no branch delay slot on MIPS16. */
1661 if (IS_MIPS16_ADDR (pc
))
1664 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1665 /* If error reading memory, guess that it is not a delayed branch. */
1667 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1671 /* Skip the PC past function prologue instructions (32-bit version).
1672 This is a helper function for mips_skip_prologue. */
1675 mips32_skip_prologue (pc
, lenient
)
1676 CORE_ADDR pc
; /* starting PC to search from */
1681 int seen_sp_adjust
= 0;
1682 int load_immediate_bytes
= 0;
1684 /* Skip the typical prologue instructions. These are the stack adjustment
1685 instruction and the instructions that save registers on the stack
1686 or in the gcc frame. */
1687 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1689 unsigned long high_word
;
1691 inst
= mips_fetch_instruction (pc
);
1692 high_word
= (inst
>> 16) & 0xffff;
1695 if (lenient
&& is_delayed (inst
))
1699 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1700 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1702 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1703 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1705 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1706 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1707 && (inst
& 0x001F0000)) /* reg != $zero */
1710 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1712 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1714 continue; /* reg != $zero */
1716 /* move $s8,$sp. With different versions of gas this will be either
1717 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1718 Accept any one of these. */
1719 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1722 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1724 else if (high_word
== 0x3c1c) /* lui $gp,n */
1726 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1728 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1729 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1731 /* The following instructions load $at or $t0 with an immediate
1732 value in preparation for a stack adjustment via
1733 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1734 a local variable, so we accept them only before a stack adjustment
1735 instruction was seen. */
1736 else if (!seen_sp_adjust
)
1738 if (high_word
== 0x3c01 || /* lui $at,n */
1739 high_word
== 0x3c08) /* lui $t0,n */
1741 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1744 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1745 high_word
== 0x3508 || /* ori $t0,$t0,n */
1746 high_word
== 0x3401 || /* ori $at,$zero,n */
1747 high_word
== 0x3408) /* ori $t0,$zero,n */
1749 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1759 /* In a frameless function, we might have incorrectly
1760 skipped some load immediate instructions. Undo the skipping
1761 if the load immediate was not followed by a stack adjustment. */
1762 if (load_immediate_bytes
&& !seen_sp_adjust
)
1763 pc
-= load_immediate_bytes
;
1767 /* Skip the PC past function prologue instructions (16-bit version).
1768 This is a helper function for mips_skip_prologue. */
1771 mips16_skip_prologue (pc
, lenient
)
1772 CORE_ADDR pc
; /* starting PC to search from */
1776 int extend_bytes
= 0;
1777 int prev_extend_bytes
;
1779 /* Table of instructions likely to be found in a function prologue. */
1782 unsigned short inst
;
1783 unsigned short mask
;
1786 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1787 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1788 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1789 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1790 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1791 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1792 { 0x673d, 0xffff }, /* move $s1,sp */
1793 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1794 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1795 { 0xe809, 0xf81f }, /* entry pseudo-op */
1796 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
1797 { 0, 0 } /* end of table marker */
1800 /* Skip the typical prologue instructions. These are the stack adjustment
1801 instruction and the instructions that save registers on the stack
1802 or in the gcc frame. */
1803 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
1805 unsigned short inst
;
1808 inst
= mips_fetch_instruction (pc
);
1810 /* Normally we ignore an extend instruction. However, if it is
1811 not followed by a valid prologue instruction, we must adjust
1812 the pc back over the extend so that it won't be considered
1813 part of the prologue. */
1814 if ((inst
& 0xf800) == 0xf000) /* extend */
1816 extend_bytes
= MIPS16_INSTLEN
;
1819 prev_extend_bytes
= extend_bytes
;
1822 /* Check for other valid prologue instructions besides extend. */
1823 for (i
= 0; table
[i
].mask
!= 0; i
++)
1824 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
1826 if (table
[i
].mask
!= 0) /* it was in table? */
1827 continue; /* ignore it */
1828 else /* non-prologue */
1830 /* Return the current pc, adjusted backwards by 2 if
1831 the previous instruction was an extend. */
1832 return pc
- prev_extend_bytes
;
1838 /* To skip prologues, I use this predicate. Returns either PC itself
1839 if the code at PC does not look like a function prologue; otherwise
1840 returns an address that (if we're lucky) follows the prologue. If
1841 LENIENT, then we must skip everything which is involved in setting
1842 up the frame (it's OK to skip more, just so long as we don't skip
1843 anything which might clobber the registers which are being saved.
1844 We must skip more in the case where part of the prologue is in the
1845 delay slot of a non-prologue instruction). */
1848 mips_skip_prologue (pc
, lenient
)
1852 /* See if we can determine the end of the prologue via the symbol table.
1853 If so, then return either PC, or the PC after the prologue, whichever
1856 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
1858 if (post_prologue_pc
!= 0)
1859 return max (pc
, post_prologue_pc
);
1861 /* Can't determine prologue from the symbol table, need to examine
1864 if (IS_MIPS16_ADDR (pc
))
1865 return mips16_skip_prologue (pc
, lenient
);
1867 return mips32_skip_prologue (pc
, lenient
);
1871 /* The lenient prologue stuff should be superseded by the code in
1872 init_extra_frame_info which looks to see whether the stores mentioned
1873 in the proc_desc have actually taken place. */
1875 /* Is address PC in the prologue (loosely defined) for function at
1879 mips_in_lenient_prologue (startaddr
, pc
)
1880 CORE_ADDR startaddr
;
1883 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
1884 return pc
>= startaddr
&& pc
< end_prologue
;
1888 /* Given a return value in `regbuf' with a type `valtype',
1889 extract and copy its value into `valbuf'. */
1891 mips_extract_return_value (valtype
, regbuf
, valbuf
)
1892 struct type
*valtype
;
1893 char regbuf
[REGISTER_BYTES
];
1898 int len
= TYPE_LENGTH (valtype
);
1901 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1902 && (mips_fpu
== MIPS_FPU_DOUBLE
1903 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
1905 regnum
= FP0_REGNUM
;
1907 /* If this is a double, the odd-numbered register (FP1) contains the
1908 high word of the result. Copy that to the buffer before
1909 copying the low word in FP0. */
1910 if (len
> MIPS_REGSIZE
)
1912 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
+1), MIPS_REGSIZE
);
1913 len
-= MIPS_REGSIZE
;
1914 valbuf
+= MIPS_REGSIZE
;
1918 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1919 && TYPE_CODE (valtype
) != TYPE_CODE_FLT
1920 && len
< REGISTER_RAW_SIZE (regnum
))
1921 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
1923 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
1926 /* Given a return value in `regbuf' with a type `valtype',
1927 write it's value into the appropriate register. */
1929 mips_store_return_value (valtype
, valbuf
)
1930 struct type
*valtype
;
1934 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1937 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1938 && (mips_fpu
== MIPS_FPU_DOUBLE
1939 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1940 regnum
= FP0_REGNUM
;
1942 memcpy(raw_buffer
, valbuf
, TYPE_LENGTH (valtype
));
1944 #ifdef REGISTER_CONVERT_FROM_TYPE
1945 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
1948 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
, TYPE_LENGTH (valtype
));
1951 /* Exported procedure: Is PC in the signal trampoline code */
1954 in_sigtramp (pc
, ignore
)
1956 char *ignore
; /* function name */
1958 if (sigtramp_address
== 0)
1960 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
1963 /* Command to set FPU type. mips_fpu_string will have been set to the
1964 user's argument. Set mips_fpu based on mips_fpu_string, and then
1965 canonicalize mips_fpu_string. */
1969 mips_set_fpu_command (args
, from_tty
, c
)
1972 struct cmd_list_element
*c
;
1976 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
1977 mips_fpu
= MIPS_FPU_DOUBLE
;
1978 else if (strcasecmp (mips_fpu_string
, "double") == 0
1979 || strcasecmp (mips_fpu_string
, "on") == 0
1980 || strcasecmp (mips_fpu_string
, "1") == 0
1981 || strcasecmp (mips_fpu_string
, "yes") == 0)
1982 mips_fpu
= MIPS_FPU_DOUBLE
;
1983 else if (strcasecmp (mips_fpu_string
, "none") == 0
1984 || strcasecmp (mips_fpu_string
, "off") == 0
1985 || strcasecmp (mips_fpu_string
, "0") == 0
1986 || strcasecmp (mips_fpu_string
, "no") == 0)
1987 mips_fpu
= MIPS_FPU_NONE
;
1988 else if (strcasecmp (mips_fpu_string
, "single") == 0)
1989 mips_fpu
= MIPS_FPU_SINGLE
;
1991 err
= strsave (mips_fpu_string
);
1993 if (mips_fpu_string
!= NULL
)
1994 free (mips_fpu_string
);
1998 case MIPS_FPU_DOUBLE
:
1999 mips_fpu_string
= strsave ("double");
2001 case MIPS_FPU_SINGLE
:
2002 mips_fpu_string
= strsave ("single");
2005 mips_fpu_string
= strsave ("none");
2011 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2012 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2014 do_cleanups (cleanups
);
2019 mips_show_fpu_command (args
, from_tty
, c
)
2022 struct cmd_list_element
*c
;
2026 /* Command to set the processor type. */
2029 mips_set_processor_type_command (args
, from_tty
)
2035 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2037 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2038 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2039 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2041 /* Restore the value. */
2042 tmp_mips_processor_type
= strsave (mips_processor_type
);
2047 if (!mips_set_processor_type (tmp_mips_processor_type
))
2049 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2050 /* Restore its value. */
2051 tmp_mips_processor_type
= strsave (mips_processor_type
);
2056 mips_show_processor_type_command (args
, from_tty
)
2062 /* Modify the actual processor type. */
2065 mips_set_processor_type (str
)
2073 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2075 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2077 mips_processor_type
= str
;
2079 for (j
= 0; j
< NUM_REGS
; ++j
)
2080 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2084 /* FIXME tweak fpu flag too */
2091 /* Attempt to identify the particular processor model by reading the
2095 mips_read_processor_type ()
2099 prid
= read_register (PRID_REGNUM
);
2101 if ((prid
& ~0xf) == 0x700)
2102 return savestring ("r3041", strlen("r3041"));
2107 /* Just like reinit_frame_cache, but with the right arguments to be
2108 callable as an sfunc. */
2111 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2114 struct cmd_list_element
*c
;
2116 reinit_frame_cache ();
2120 gdb_print_insn_mips (memaddr
, info
)
2122 disassemble_info
*info
;
2124 mips_extra_func_info_t proc_desc
;
2126 /* Search for the function containing this address. Set the low bit
2127 of the address when searching, in case we were given an even address
2128 that is the start of a 16-bit function. If we didn't do this,
2129 the search would fail because the symbol table says the function
2130 starts at an odd address, i.e. 1 byte past the given address. */
2131 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2132 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2134 /* Make an attempt to determine if this is a 16-bit function. If
2135 the procedure descriptor exists and the address therein is odd,
2136 it's definitely a 16-bit function. Otherwise, we have to just
2137 guess that if the address passed in is odd, it's 16-bits. */
2139 info
->mach
= IS_MIPS16_ADDR (PROC_LOW_ADDR (proc_desc
)) ? 16 : 0;
2141 info
->mach
= IS_MIPS16_ADDR (memaddr
) ? 16 : 0;
2143 /* Round down the instruction address to the appropriate boundary. */
2144 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2146 /* Call the appropriate disassembler based on the target endian-ness. */
2147 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2148 return print_insn_big_mips (memaddr
, info
);
2150 return print_insn_little_mips (memaddr
, info
);
2153 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2154 counter value to determine whether a 16- or 32-bit breakpoint should be
2155 used. It returns a pointer to a string of bytes that encode a breakpoint
2156 instruction, stores the length of the string to *lenptr, and adjusts pc
2157 (if necessary) to point to the actual memory location where the
2158 breakpoint should be inserted. */
2160 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2164 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2166 if (IS_MIPS16_ADDR (*pcptr
))
2168 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2169 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2170 *lenptr
= sizeof(mips16_big_breakpoint
);
2171 return mips16_big_breakpoint
;
2175 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2176 *lenptr
= sizeof(big_breakpoint
);
2177 return big_breakpoint
;
2182 if (IS_MIPS16_ADDR (*pcptr
))
2184 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2185 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2186 *lenptr
= sizeof(mips16_little_breakpoint
);
2187 return mips16_little_breakpoint
;
2191 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2192 *lenptr
= sizeof(little_breakpoint
);
2193 return little_breakpoint
;
2198 /* Test whether the PC points to the return instruction at the
2199 end of a function. This implements the ABOUT_TO_RETURN macro. */
2202 mips_about_to_return (pc
)
2205 if (IS_MIPS16_ADDR (pc
))
2206 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2207 generates a "jr $ra"; other times it generates code to load
2208 the return address from the stack to an accessible register (such
2209 as $a3), then a "jr" using that register. This second case
2210 is almost impossible to distinguish from an indirect jump
2211 used for switch statements, so we don't even try. */
2212 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2214 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2219 _initialize_mips_tdep ()
2221 struct cmd_list_element
*c
;
2223 tm_print_insn
= gdb_print_insn_mips
;
2225 /* Let the user turn off floating point and set the fence post for
2226 heuristic_proc_start. */
2228 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2229 (char *) &mips_fpu_string
,
2230 "Set use of floating point coprocessor.\n\
2231 Set to `none' to avoid using floating point instructions when calling\n\
2232 functions or dealing with return values. Set to `single' to use only\n\
2233 single precision floating point as on the R4650. Set to `double' for\n\
2234 normal floating point support.",
2236 c
->function
.sfunc
= mips_set_fpu_command
;
2237 c
= add_show_from_set (c
, &showlist
);
2238 c
->function
.sfunc
= mips_show_fpu_command
;
2240 mips_fpu
= MIPS_FPU_DOUBLE
;
2241 mips_fpu_string
= strsave ("double");
2243 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2244 (char *) &tmp_mips_processor_type
,
2245 "Set the type of MIPS processor in use.\n\
2246 Set this to be able to access processor-type-specific registers.\n\
2249 c
->function
.cfunc
= mips_set_processor_type_command
;
2250 c
= add_show_from_set (c
, &showlist
);
2251 c
->function
.cfunc
= mips_show_processor_type_command
;
2253 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2254 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2256 /* We really would like to have both "0" and "unlimited" work, but
2257 command.c doesn't deal with that. So make it a var_zinteger
2258 because the user can always use "999999" or some such for unlimited. */
2259 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2260 (char *) &heuristic_fence_post
,
2262 Set the distance searched for the start of a function.\n\
2263 If you are debugging a stripped executable, GDB needs to search through the\n\
2264 program for the start of a function. This command sets the distance of the\n\
2265 search. The only need to set it is when debugging a stripped executable.",
2267 /* We need to throw away the frame cache when we set this, since it
2268 might change our ability to get backtraces. */
2269 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2270 add_show_from_set (c
, &showlist
);