1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
118 enum mips_abi mips_abi
;
119 const char *mips_abi_string
;
120 enum mips_fpu_type mips_fpu_type
;
121 int mips_last_arg_regnum
;
122 int mips_last_fp_arg_regnum
;
123 int mips_default_saved_regsize
;
124 int mips_fp_register_double
;
125 int mips_regs_have_home_p
;
126 int mips_default_stack_argsize
;
127 int gdb_target_is_mips64
;
128 int default_mask_address_p
;
133 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
134 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
138 #undef MIPS_LAST_FP_ARG_REGNUM
139 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
143 #undef MIPS_LAST_ARG_REGNUM
144 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
149 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
152 /* Return the currently configured (or set) saved register size. */
155 #undef MIPS_DEFAULT_SAVED_REGSIZE
156 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
157 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
158 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Indicate that the ABI makes use of double-precision registers
177 provided by the FPU (rather than combining pairs of registers to
178 form double-precision values). Do not use "TARGET_IS_MIPS64" to
179 determine if the ABI is using double-precision registers. See also
182 #undef FP_REGISTER_DOUBLE
183 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
186 /* Does the caller allocate a ``home'' for each register used in the
187 function call? The N32 ABI and MIPS_EABI do not, the others do. */
190 #undef MIPS_REGS_HAVE_HOME_P
191 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
192 #elif !defined (MIPS_REGS_HAVE_HOME_P)
193 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
196 /* The amount of space reserved on the stack for registers. This is
197 different to MIPS_SAVED_REGSIZE as it determines the alignment of
198 data allocated after the registers have run out. */
201 #undef MIPS_DEFAULT_STACK_ARGSIZE
202 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
203 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
204 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
207 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
209 static const char *mips_stack_argsize_string
= size_auto
;
212 mips_stack_argsize (void)
214 if (mips_stack_argsize_string
== size_auto
)
215 return MIPS_DEFAULT_STACK_ARGSIZE
;
216 else if (mips_stack_argsize_string
== size_64
)
218 else /* if (mips_stack_argsize_string == size_32) */
223 #undef GDB_TARGET_IS_MIPS64
224 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
227 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
229 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
231 static void mips_print_register (int, int);
233 static mips_extra_func_info_t
234 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
236 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
238 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
240 int mips_set_processor_type (char *);
242 static void mips_show_processor_type_command (char *, int);
244 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
246 static mips_extra_func_info_t
247 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
249 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
250 mips_extra_func_info_t proc_desc
);
252 /* This value is the model of MIPS in use. It is derived from the value
253 of the PrID register. */
255 char *mips_processor_type
;
257 char *tmp_mips_processor_type
;
259 /* The list of available "set mips " and "show mips " commands */
261 static struct cmd_list_element
*setmipscmdlist
= NULL
;
262 static struct cmd_list_element
*showmipscmdlist
= NULL
;
264 /* A set of original names, to be used when restoring back to generic
265 registers from a specific set. */
267 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
268 char **mips_processor_reg_names
= mips_generic_reg_names
;
271 mips_register_name (i
)
274 return mips_processor_reg_names
[i
];
277 /* Names of IDT R3041 registers. */
279 char *mips_r3041_reg_names
[] = {
280 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
281 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
282 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
283 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
284 "sr", "lo", "hi", "bad", "cause","pc",
285 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
286 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
287 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
288 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
289 "fsr", "fir", "fp", "",
290 "", "", "bus", "ccfg", "", "", "", "",
291 "", "", "port", "cmp", "", "", "epc", "prid",
294 /* Names of IDT R3051 registers. */
296 char *mips_r3051_reg_names
[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "inx", "rand", "elo", "", "ctxt", "", "", "",
308 "", "", "ehi", "", "", "", "epc", "prid",
311 /* Names of IDT R3081 registers. */
313 char *mips_r3081_reg_names
[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of LSI 33k registers. */
330 char *mips_lsi33k_reg_names
[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "epc", "hi", "lo", "sr", "cause","badvaddr",
336 "dcic", "bpc", "bda", "", "", "", "", "",
337 "", "", "", "", "", "", "", "",
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
342 "", "", "", "", "", "", "", "",
348 } mips_processor_type_table
[] = {
349 { "generic", mips_generic_reg_names
},
350 { "r3041", mips_r3041_reg_names
},
351 { "r3051", mips_r3051_reg_names
},
352 { "r3071", mips_r3081_reg_names
},
353 { "r3081", mips_r3081_reg_names
},
354 { "lsi33k", mips_lsi33k_reg_names
},
362 /* Table to translate MIPS16 register field to actual register number. */
363 static int mips16_to_32_reg
[8] =
364 {16, 17, 2, 3, 4, 5, 6, 7};
366 /* Heuristic_proc_start may hunt through the text section for a long
367 time across a 2400 baud serial line. Allows the user to limit this
370 static unsigned int heuristic_fence_post
= 0;
372 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
373 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
374 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
375 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
376 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
377 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
378 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
379 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
380 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
381 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
382 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
383 #define _PROC_MAGIC_ 0x0F0F0F0F
384 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
385 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
387 struct linked_proc_info
389 struct mips_extra_func_info info
;
390 struct linked_proc_info
*next
;
392 *linked_proc_desc_table
= NULL
;
395 mips_print_extra_frame_info (struct frame_info
*fi
)
399 && fi
->extra_info
->proc_desc
400 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
401 printf_filtered (" frame pointer is at %s+%s\n",
402 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
403 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
406 /* Convert between RAW and VIRTUAL registers. The RAW register size
407 defines the remote-gdb packet. */
409 static int mips64_transfers_32bit_regs_p
= 0;
412 mips_register_raw_size (int reg_nr
)
414 if (mips64_transfers_32bit_regs_p
)
415 return REGISTER_VIRTUAL_SIZE (reg_nr
);
421 mips_register_convertible (int reg_nr
)
423 if (mips64_transfers_32bit_regs_p
)
426 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
430 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
431 char *raw_buf
, char *virt_buf
)
433 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
435 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
436 TYPE_LENGTH (virtual_type
));
440 TYPE_LENGTH (virtual_type
));
444 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
445 char *virt_buf
, char *raw_buf
)
447 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
448 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
449 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
451 TYPE_LENGTH (virtual_type
));
455 TYPE_LENGTH (virtual_type
));
458 /* Should the upper word of 64-bit addresses be zeroed? */
459 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
462 mips_mask_address_p (void)
464 switch (mask_address_var
)
466 case CMD_AUTO_BOOLEAN_TRUE
:
468 case CMD_AUTO_BOOLEAN_FALSE
:
471 case CMD_AUTO_BOOLEAN_AUTO
:
472 return gdbarch_tdep (current_gdbarch
)->default_mask_address_p
;
474 internal_error ("mips_mask_address_p: bad switch");
480 show_mask_address (char *cmd
, int from_tty
)
482 switch (mask_address_var
)
484 case CMD_AUTO_BOOLEAN_TRUE
:
485 printf_filtered ("The 32 bit mips address mask is enabled\n");
487 case CMD_AUTO_BOOLEAN_FALSE
:
488 printf_filtered ("The 32 bit mips address mask is disabled\n");
490 case CMD_AUTO_BOOLEAN_AUTO
:
491 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
492 mips_mask_address_p () ? "enabled" : "disabled");
495 internal_error ("show_mask_address: bad switch");
500 /* Should call_function allocate stack space for a struct return? */
502 mips_use_struct_convention (gcc_p
, type
)
507 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
509 return 1; /* Structures are returned by ref in extra arg0 */
512 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
515 pc_is_mips16 (bfd_vma memaddr
)
517 struct minimal_symbol
*sym
;
519 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
520 if (IS_MIPS16_ADDR (memaddr
))
523 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
524 the high bit of the info field. Use this to decide if the function is
525 MIPS16 or normal MIPS. */
526 sym
= lookup_minimal_symbol_by_pc (memaddr
);
528 return MSYMBOL_IS_SPECIAL (sym
);
533 /* MIPS believes that the PC has a sign extended value. Perhaphs the
534 all registers should be sign extended for simplicity? */
537 mips_read_pc (int pid
)
539 return read_signed_register_pid (PC_REGNUM
, pid
);
542 /* This returns the PC of the first inst after the prologue. If we can't
543 find the prologue, then return 0. */
546 after_prologue (CORE_ADDR pc
,
547 mips_extra_func_info_t proc_desc
)
549 struct symtab_and_line sal
;
550 CORE_ADDR func_addr
, func_end
;
553 proc_desc
= find_proc_desc (pc
, NULL
);
557 /* If function is frameless, then we need to do it the hard way. I
558 strongly suspect that frameless always means prologueless... */
559 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
560 && PROC_FRAME_OFFSET (proc_desc
) == 0)
564 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
565 return 0; /* Unknown */
567 sal
= find_pc_line (func_addr
, 0);
569 if (sal
.end
< func_end
)
572 /* The line after the prologue is after the end of the function. In this
573 case, tell the caller to find the prologue the hard way. */
578 /* Decode a MIPS32 instruction that saves a register in the stack, and
579 set the appropriate bit in the general register mask or float register mask
580 to indicate which register is saved. This is a helper function
581 for mips_find_saved_regs. */
584 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
585 unsigned long *float_mask
)
589 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
590 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
591 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
593 /* It might be possible to use the instruction to
594 find the offset, rather than the code below which
595 is based on things being in a certain order in the
596 frame, but figuring out what the instruction's offset
597 is relative to might be a little tricky. */
598 reg
= (inst
& 0x001f0000) >> 16;
599 *gen_mask
|= (1 << reg
);
601 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
602 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
603 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
606 reg
= ((inst
& 0x001f0000) >> 16);
607 *float_mask
|= (1 << reg
);
611 /* Decode a MIPS16 instruction that saves a register in the stack, and
612 set the appropriate bit in the general register or float register mask
613 to indicate which register is saved. This is a helper function
614 for mips_find_saved_regs. */
617 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
619 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
621 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
622 *gen_mask
|= (1 << reg
);
624 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
626 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
627 *gen_mask
|= (1 << reg
);
629 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
630 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
631 *gen_mask
|= (1 << RA_REGNUM
);
635 /* Fetch and return instruction from the specified location. If the PC
636 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
639 mips_fetch_instruction (CORE_ADDR addr
)
641 char buf
[MIPS_INSTLEN
];
645 if (pc_is_mips16 (addr
))
647 instlen
= MIPS16_INSTLEN
;
648 addr
= UNMAKE_MIPS16_ADDR (addr
);
651 instlen
= MIPS_INSTLEN
;
652 status
= read_memory_nobpt (addr
, buf
, instlen
);
654 memory_error (status
, addr
);
655 return extract_unsigned_integer (buf
, instlen
);
659 /* These the fields of 32 bit mips instructions */
660 #define mips32_op(x) (x >> 25)
661 #define itype_op(x) (x >> 25)
662 #define itype_rs(x) ((x >> 21)& 0x1f)
663 #define itype_rt(x) ((x >> 16) & 0x1f)
664 #define itype_immediate(x) ( x & 0xffff)
666 #define jtype_op(x) (x >> 25)
667 #define jtype_target(x) ( x & 0x03fffff)
669 #define rtype_op(x) (x >>25)
670 #define rtype_rs(x) ((x>>21) & 0x1f)
671 #define rtype_rt(x) ((x>>16) & 0x1f)
672 #define rtype_rd(x) ((x>>11) & 0x1f)
673 #define rtype_shamt(x) ((x>>6) & 0x1f)
674 #define rtype_funct(x) (x & 0x3f )
677 mips32_relative_offset (unsigned long inst
)
680 x
= itype_immediate (inst
);
681 if (x
& 0x8000) /* sign bit set */
683 x
|= 0xffff0000; /* sign extension */
689 /* Determine whate to set a single step breakpoint while considering
692 mips32_next_pc (CORE_ADDR pc
)
696 inst
= mips_fetch_instruction (pc
);
697 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
699 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
701 op
= ((inst
>> 25) & 0x03);
705 goto equal_branch
; /* BEQL */
707 goto neq_branch
; /* BNEZ */
709 goto less_branch
; /* BLEZ */
711 goto greater_branch
; /* BGTZ */
717 pc
+= 4; /* Not a branch, next instruction is easy */
720 { /* This gets way messy */
722 /* Further subdivide into SPECIAL, REGIMM and other */
723 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
725 case 0: /* SPECIAL */
726 op
= rtype_funct (inst
);
731 /* Set PC to that address */
732 pc
= read_signed_register (rtype_rs (inst
));
738 break; /* end special */
741 op
= jtype_op (inst
); /* branch condition */
742 switch (jtype_op (inst
))
746 case 16: /* BLTZALL */
747 case 18: /* BLTZALL */
749 if (read_signed_register (itype_rs (inst
)) < 0)
750 pc
+= mips32_relative_offset (inst
) + 4;
752 pc
+= 8; /* after the delay slot */
756 case 17: /* BGEZAL */
757 case 19: /* BGEZALL */
758 greater_equal_branch
:
759 if (read_signed_register (itype_rs (inst
)) >= 0)
760 pc
+= mips32_relative_offset (inst
) + 4;
762 pc
+= 8; /* after the delay slot */
764 /* All of the other intructions in the REGIMM catagory */
769 break; /* end REGIMM */
774 reg
= jtype_target (inst
) << 2;
775 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
776 /* Whats this mysterious 0xf000000 adjustment ??? */
779 /* FIXME case JALX : */
782 reg
= jtype_target (inst
) << 2;
783 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
784 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
786 break; /* The new PC will be alternate mode */
787 case 4: /* BEQ , BEQL */
789 if (read_signed_register (itype_rs (inst
)) ==
790 read_signed_register (itype_rt (inst
)))
791 pc
+= mips32_relative_offset (inst
) + 4;
795 case 5: /* BNE , BNEL */
797 if (read_signed_register (itype_rs (inst
)) !=
798 read_signed_register (itype_rs (inst
)))
799 pc
+= mips32_relative_offset (inst
) + 4;
803 case 6: /* BLEZ , BLEZL */
805 if (read_signed_register (itype_rs (inst
) <= 0))
806 pc
+= mips32_relative_offset (inst
) + 4;
811 greater_branch
: /* BGTZ BGTZL */
812 if (read_signed_register (itype_rs (inst
) > 0))
813 pc
+= mips32_relative_offset (inst
) + 4;
822 } /* mips32_next_pc */
824 /* Decoding the next place to set a breakpoint is irregular for the
825 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
826 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
827 We dont want to set a single step instruction on the extend instruction
831 /* Lots of mips16 instruction formats */
832 /* Predicting jumps requires itype,ritype,i8type
833 and their extensions extItype,extritype,extI8type
835 enum mips16_inst_fmts
837 itype
, /* 0 immediate 5,10 */
838 ritype
, /* 1 5,3,8 */
839 rrtype
, /* 2 5,3,3,5 */
840 rritype
, /* 3 5,3,3,5 */
841 rrrtype
, /* 4 5,3,3,3,2 */
842 rriatype
, /* 5 5,3,3,1,4 */
843 shifttype
, /* 6 5,3,3,3,2 */
844 i8type
, /* 7 5,3,8 */
845 i8movtype
, /* 8 5,3,3,5 */
846 i8mov32rtype
, /* 9 5,3,5,3 */
847 i64type
, /* 10 5,3,8 */
848 ri64type
, /* 11 5,3,3,5 */
849 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
850 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
851 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
852 extRRItype
, /* 15 5,5,5,5,3,3,5 */
853 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
854 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
855 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
856 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
857 extRi64type
, /* 20 5,6,5,5,3,3,5 */
858 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
860 /* I am heaping all the fields of the formats into one structure and then,
861 only the fields which are involved in instruction extension */
865 enum mips16_inst_fmts fmt
;
866 unsigned long offset
;
867 unsigned int regx
; /* Function in i8 type */
874 print_unpack (char *comment
,
875 struct upk_mips16
*u
)
877 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
878 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
881 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
882 format for the bits which make up the immediatate extension.
885 extended_offset (unsigned long extension
)
888 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
890 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
892 value
|= extension
& 0x01f; /* extract 4:0 */
896 /* Only call this function if you know that this is an extendable
897 instruction, It wont malfunction, but why make excess remote memory references?
898 If the immediate operands get sign extended or somthing, do it after
899 the extension is performed.
901 /* FIXME: Every one of these cases needs to worry about sign extension
902 when the offset is to be used in relative addressing */
905 static unsigned short
906 fetch_mips_16 (CORE_ADDR pc
)
909 pc
&= 0xfffffffe; /* clear the low order bit */
910 target_read_memory (pc
, buf
, 2);
911 return extract_unsigned_integer (buf
, 2);
915 unpack_mips16 (CORE_ADDR pc
,
916 struct upk_mips16
*upk
)
919 unsigned long extension
;
921 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
922 /* Decrement to previous address and loose the 16bit mode flag */
923 /* return if the instruction was extendable, but not actually extended */
924 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
927 extension
= mips_fetch_instruction (extpc
);
936 value
= extended_offset (extension
);
937 value
= value
<< 11; /* rom for the original value */
938 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
942 value
= upk
->inst
& 0x7ff;
943 /* FIXME : Consider sign extension */
950 { /* A register identifier and an offset */
951 /* Most of the fields are the same as I type but the
952 immediate value is of a different length */
956 value
= extended_offset (extension
);
957 value
= value
<< 8; /* from the original instruction */
958 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
959 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
960 if (value
& 0x4000) /* test the sign bit , bit 26 */
962 value
&= ~0x3fff; /* remove the sign bit */
968 value
= upk
->inst
& 0xff; /* 8 bits */
969 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
970 /* FIXME: Do sign extension , this format needs it */
971 if (value
& 0x80) /* THIS CONFUSES ME */
973 value
&= 0xef; /* remove the sign bit */
984 unsigned short nexthalf
;
985 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
987 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
993 printf_filtered ("Decoding unimplemented instruction format type\n");
996 /* print_unpack("UPK",upk) ; */
1000 #define mips16_op(x) (x >> 11)
1002 /* This is a map of the opcodes which ae known to perform branches */
1003 static unsigned char map16
[32] =
1004 {0, 0, 1, 1, 1, 1, 0, 0,
1005 0, 0, 0, 0, 1, 0, 0, 0,
1006 0, 0, 0, 0, 0, 0, 0, 0,
1007 0, 0, 0, 0, 0, 1, 1, 0
1011 add_offset_16 (CORE_ADDR pc
, int offset
)
1013 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1019 static struct upk_mips16 upk
;
1022 mips16_next_pc (CORE_ADDR pc
)
1026 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
1027 inst
= fetch_mips_16 (pc
);
1029 op
= mips16_op (upk
.inst
);
1035 case 2: /* Branch */
1037 unpack_mips16 (pc
, &upk
);
1040 offset
= upk
.offset
;
1046 pc
+= (offset
<< 1) + 2;
1049 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1051 unpack_mips16 (pc
, &upk
);
1052 pc
= add_offset_16 (pc
, upk
.offset
);
1053 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
1054 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1060 unpack_mips16 (pc
, &upk
);
1061 reg
= read_signed_register (upk
.regx
);
1063 pc
+= (upk
.offset
<< 1) + 2;
1069 unpack_mips16 (pc
, &upk
);
1070 reg
= read_signed_register (upk
.regx
);
1072 pc
+= (upk
.offset
<< 1) + 2;
1076 case 12: /* I8 Formats btez btnez */
1078 unpack_mips16 (pc
, &upk
);
1079 /* upk.regx contains the opcode */
1080 reg
= read_signed_register (24); /* Test register is 24 */
1081 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1082 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1083 /* pc = add_offset_16(pc,upk.offset) ; */
1084 pc
+= (upk
.offset
<< 1) + 2;
1088 case 29: /* RR Formats JR, JALR, JALR-RA */
1090 op
= upk
.inst
& 0x1f;
1093 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1094 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1102 break; /* Function return instruction */
1108 break; /* BOGUS Guess */
1110 pc
= read_signed_register (reg
);
1115 case 30: /* This is an extend instruction */
1116 pc
+= 4; /* Dont be setting breakpints on the second half */
1119 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1125 pc
+= 2; /* just a good old instruction */
1126 /* See if we CAN actually break on the next instruction */
1127 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1129 } /* mips16_next_pc */
1131 /* The mips_next_pc function supports single_tep when the remote target monitor or
1132 stub is not developed enough to so a single_step.
1133 It works by decoding the current instruction and predicting where a branch
1134 will go. This isnt hard because all the data is available.
1135 The MIPS32 and MIPS16 variants are quite different
1138 mips_next_pc (CORE_ADDR pc
)
1141 /* inst = mips_fetch_instruction(pc) ; */
1142 /* if (pc_is_mips16) <----- This is failing */
1144 return mips16_next_pc (pc
);
1146 return mips32_next_pc (pc
);
1147 } /* mips_next_pc */
1149 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1153 mips_find_saved_regs (struct frame_info
*fci
)
1156 CORE_ADDR reg_position
;
1157 /* r0 bit means kernel trap */
1159 /* What registers have been saved? Bitmasks. */
1160 unsigned long gen_mask
, float_mask
;
1161 mips_extra_func_info_t proc_desc
;
1164 frame_saved_regs_zalloc (fci
);
1166 /* If it is the frame for sigtramp, the saved registers are located
1167 in a sigcontext structure somewhere on the stack.
1168 If the stack layout for sigtramp changes we might have to change these
1169 constants and the companion fixup_sigtramp in mdebugread.c */
1170 #ifndef SIGFRAME_BASE
1171 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1172 above the sigtramp frame. */
1173 #define SIGFRAME_BASE MIPS_REGSIZE
1174 /* FIXME! Are these correct?? */
1175 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1176 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1177 #define SIGFRAME_FPREGSAVE_OFF \
1178 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1180 #ifndef SIGFRAME_REG_SIZE
1181 /* FIXME! Is this correct?? */
1182 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1184 if (fci
->signal_handler_caller
)
1186 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1188 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1189 + ireg
* SIGFRAME_REG_SIZE
;
1190 fci
->saved_regs
[ireg
] = reg_position
;
1192 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1194 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1195 + ireg
* SIGFRAME_REG_SIZE
;
1196 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1198 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1202 proc_desc
= fci
->extra_info
->proc_desc
;
1203 if (proc_desc
== NULL
)
1204 /* I'm not sure how/whether this can happen. Normally when we can't
1205 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1206 and set the saved_regs right away. */
1209 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1210 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1211 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1213 if ( /* In any frame other than the innermost or a frame interrupted by
1214 a signal, we assume that all registers have been saved.
1215 This assumes that all register saves in a function happen before
1216 the first function call. */
1217 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1219 /* In a dummy frame we know exactly where things are saved. */
1220 && !PROC_DESC_IS_DUMMY (proc_desc
)
1222 /* Don't bother unless we are inside a function prologue. Outside the
1223 prologue, we know where everything is. */
1225 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1227 /* Not sure exactly what kernel_trap means, but if it means
1228 the kernel saves the registers without a prologue doing it,
1229 we better not examine the prologue to see whether registers
1230 have been saved yet. */
1233 /* We need to figure out whether the registers that the proc_desc
1234 claims are saved have been saved yet. */
1238 /* Bitmasks; set if we have found a save for the register. */
1239 unsigned long gen_save_found
= 0;
1240 unsigned long float_save_found
= 0;
1243 /* If the address is odd, assume this is MIPS16 code. */
1244 addr
= PROC_LOW_ADDR (proc_desc
);
1245 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1247 /* Scan through this function's instructions preceding the current
1248 PC, and look for those that save registers. */
1249 while (addr
< fci
->pc
)
1251 inst
= mips_fetch_instruction (addr
);
1252 if (pc_is_mips16 (addr
))
1253 mips16_decode_reg_save (inst
, &gen_save_found
);
1255 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1258 gen_mask
= gen_save_found
;
1259 float_mask
= float_save_found
;
1262 /* Fill in the offsets for the registers which gen_mask says
1264 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1265 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1266 if (gen_mask
& 0x80000000)
1268 fci
->saved_regs
[ireg
] = reg_position
;
1269 reg_position
-= MIPS_SAVED_REGSIZE
;
1272 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1273 of that normally used by gcc. Therefore, we have to fetch the first
1274 instruction of the function, and if it's an entry instruction that
1275 saves $s0 or $s1, correct their saved addresses. */
1276 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1278 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1279 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1282 int sreg_count
= (inst
>> 6) & 3;
1284 /* Check if the ra register was pushed on the stack. */
1285 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1287 reg_position
-= MIPS_SAVED_REGSIZE
;
1289 /* Check if the s0 and s1 registers were pushed on the stack. */
1290 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1292 fci
->saved_regs
[reg
] = reg_position
;
1293 reg_position
-= MIPS_SAVED_REGSIZE
;
1298 /* Fill in the offsets for the registers which float_mask says
1300 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1302 /* The freg_offset points to where the first *double* register
1303 is saved. So skip to the high-order word. */
1304 if (!GDB_TARGET_IS_MIPS64
)
1305 reg_position
+= MIPS_SAVED_REGSIZE
;
1307 /* Fill in the offsets for the float registers which float_mask says
1309 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1310 if (float_mask
& 0x80000000)
1312 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1313 reg_position
-= MIPS_SAVED_REGSIZE
;
1316 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1320 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1322 for (; fi
; fi
= fi
->next
)
1324 /* We have to get the saved sp from the sigcontext
1325 if it is a signal handler frame. */
1326 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1330 if (fi
->saved_regs
== NULL
)
1331 mips_find_saved_regs (fi
);
1332 if (fi
->saved_regs
[regno
])
1333 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1336 return read_signed_register (regno
);
1339 /* mips_addr_bits_remove - remove useless address bits */
1342 mips_addr_bits_remove (CORE_ADDR addr
)
1344 if (GDB_TARGET_IS_MIPS64
)
1346 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1348 /* This hack is a work-around for existing boards using
1349 PMON, the simulator, and any other 64-bit targets that
1350 doesn't have true 64-bit addressing. On these targets,
1351 the upper 32 bits of addresses are ignored by the
1352 hardware. Thus, the PC or SP are likely to have been
1353 sign extended to all 1s by instruction sequences that
1354 load 32-bit addresses. For example, a typical piece of
1355 code that loads an address is this:
1356 lui $r2, <upper 16 bits>
1357 ori $r2, <lower 16 bits>
1358 But the lui sign-extends the value such that the upper 32
1359 bits may be all 1s. The workaround is simply to mask off
1360 these bits. In the future, gcc may be changed to support
1361 true 64-bit addressing, and this masking will have to be
1363 addr
&= (CORE_ADDR
) 0xffffffff;
1366 else if (mips_mask_address_p ())
1368 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1369 masking off bits, instead, the actual target should be asking
1370 for the address to be converted to a valid pointer. */
1371 /* Even when GDB is configured for some 32-bit targets
1372 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1373 so CORE_ADDR is 64 bits. So we still have to mask off
1374 useless bits from addresses. */
1375 addr
&= (CORE_ADDR
) 0xffffffff;
1381 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1385 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1386 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1387 tmp
= mips_skip_stub (pc
);
1388 prev
->pc
= tmp
? tmp
: pc
;
1393 mips_frame_saved_pc (struct frame_info
*frame
)
1396 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1397 /* We have to get the saved pc from the sigcontext
1398 if it is a signal handler frame. */
1399 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1400 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1402 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1403 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1405 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1407 return ADDR_BITS_REMOVE (saved_pc
);
1410 static struct mips_extra_func_info temp_proc_desc
;
1411 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1413 /* Set a register's saved stack address in temp_saved_regs. If an address
1414 has already been set for this register, do nothing; this way we will
1415 only recognize the first save of a given register in a function prologue.
1416 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1419 set_reg_offset (int regno
, CORE_ADDR offset
)
1421 if (temp_saved_regs
[regno
] == 0)
1422 temp_saved_regs
[regno
] = offset
;
1426 /* Test whether the PC points to the return instruction at the
1427 end of a function. */
1430 mips_about_to_return (CORE_ADDR pc
)
1432 if (pc_is_mips16 (pc
))
1433 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1434 generates a "jr $ra"; other times it generates code to load
1435 the return address from the stack to an accessible register (such
1436 as $a3), then a "jr" using that register. This second case
1437 is almost impossible to distinguish from an indirect jump
1438 used for switch statements, so we don't even try. */
1439 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1441 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1445 /* This fencepost looks highly suspicious to me. Removing it also
1446 seems suspicious as it could affect remote debugging across serial
1450 heuristic_proc_start (CORE_ADDR pc
)
1457 pc
= ADDR_BITS_REMOVE (pc
);
1459 fence
= start_pc
- heuristic_fence_post
;
1463 if (heuristic_fence_post
== UINT_MAX
1464 || fence
< VM_MIN_ADDRESS
)
1465 fence
= VM_MIN_ADDRESS
;
1467 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1469 /* search back for previous return */
1470 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1471 if (start_pc
< fence
)
1473 /* It's not clear to me why we reach this point when
1474 stop_soon_quietly, but with this test, at least we
1475 don't print out warnings for every child forked (eg, on
1476 decstation). 22apr93 rich@cygnus.com. */
1477 if (!stop_soon_quietly
)
1479 static int blurb_printed
= 0;
1481 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1486 /* This actually happens frequently in embedded
1487 development, when you first connect to a board
1488 and your stack pointer and pc are nowhere in
1489 particular. This message needs to give people
1490 in that situation enough information to
1491 determine that it's no big deal. */
1492 printf_filtered ("\n\
1493 GDB is unable to find the start of the function at 0x%s\n\
1494 and thus can't determine the size of that function's stack frame.\n\
1495 This means that GDB may be unable to access that stack frame, or\n\
1496 the frames below it.\n\
1497 This problem is most likely caused by an invalid program counter or\n\
1499 However, if you think GDB should simply search farther back\n\
1500 from 0x%s for code which looks like the beginning of a\n\
1501 function, you can increase the range of the search using the `set\n\
1502 heuristic-fence-post' command.\n",
1503 paddr_nz (pc
), paddr_nz (pc
));
1510 else if (pc_is_mips16 (start_pc
))
1512 unsigned short inst
;
1514 /* On MIPS16, any one of the following is likely to be the
1515 start of a function:
1519 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1520 inst
= mips_fetch_instruction (start_pc
);
1521 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1522 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1523 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1524 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1526 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1527 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1532 else if (mips_about_to_return (start_pc
))
1534 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1541 /* Fetch the immediate value from a MIPS16 instruction.
1542 If the previous instruction was an EXTEND, use it to extend
1543 the upper bits of the immediate value. This is a helper function
1544 for mips16_heuristic_proc_desc. */
1547 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1548 unsigned short inst
, /* current instruction */
1549 int nbits
, /* number of bits in imm field */
1550 int scale
, /* scale factor to be applied to imm */
1551 int is_signed
) /* is the imm field signed? */
1555 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1557 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1558 if (offset
& 0x8000) /* check for negative extend */
1559 offset
= 0 - (0x10000 - (offset
& 0xffff));
1560 return offset
| (inst
& 0x1f);
1564 int max_imm
= 1 << nbits
;
1565 int mask
= max_imm
- 1;
1566 int sign_bit
= max_imm
>> 1;
1568 offset
= inst
& mask
;
1569 if (is_signed
&& (offset
& sign_bit
))
1570 offset
= 0 - (max_imm
- offset
);
1571 return offset
* scale
;
1576 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1577 stream from start_pc to limit_pc. */
1580 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1581 struct frame_info
*next_frame
, CORE_ADDR sp
)
1584 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1585 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1586 unsigned inst
= 0; /* current instruction */
1587 unsigned entry_inst
= 0; /* the entry instruction */
1590 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1591 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1593 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1595 /* Save the previous instruction. If it's an EXTEND, we'll extract
1596 the immediate offset extension from it in mips16_get_imm. */
1599 /* Fetch and decode the instruction. */
1600 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1601 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1602 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1604 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1605 if (offset
< 0) /* negative stack adjustment? */
1606 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1608 /* Exit loop if a positive stack adjustment is found, which
1609 usually means that the stack cleanup code in the function
1610 epilogue is reached. */
1613 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1615 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1616 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1617 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1618 set_reg_offset (reg
, sp
+ offset
);
1620 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1622 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1623 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1624 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1625 set_reg_offset (reg
, sp
+ offset
);
1627 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1629 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1630 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1631 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1633 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1635 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1636 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1637 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1639 else if (inst
== 0x673d) /* move $s1, $sp */
1642 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1644 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1646 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1647 frame_addr
= sp
+ offset
;
1648 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1649 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1651 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1653 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1654 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1655 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1656 set_reg_offset (reg
, frame_addr
+ offset
);
1658 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1660 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1661 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1662 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1663 set_reg_offset (reg
, frame_addr
+ offset
);
1665 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1666 entry_inst
= inst
; /* save for later processing */
1667 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1668 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1671 /* The entry instruction is typically the first instruction in a function,
1672 and it stores registers at offsets relative to the value of the old SP
1673 (before the prologue). But the value of the sp parameter to this
1674 function is the new SP (after the prologue has been executed). So we
1675 can't calculate those offsets until we've seen the entire prologue,
1676 and can calculate what the old SP must have been. */
1677 if (entry_inst
!= 0)
1679 int areg_count
= (entry_inst
>> 8) & 7;
1680 int sreg_count
= (entry_inst
>> 6) & 3;
1682 /* The entry instruction always subtracts 32 from the SP. */
1683 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1685 /* Now we can calculate what the SP must have been at the
1686 start of the function prologue. */
1687 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1689 /* Check if a0-a3 were saved in the caller's argument save area. */
1690 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1692 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1693 set_reg_offset (reg
, sp
+ offset
);
1694 offset
+= MIPS_SAVED_REGSIZE
;
1697 /* Check if the ra register was pushed on the stack. */
1699 if (entry_inst
& 0x20)
1701 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1702 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1703 offset
-= MIPS_SAVED_REGSIZE
;
1706 /* Check if the s0 and s1 registers were pushed on the stack. */
1707 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1709 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1710 set_reg_offset (reg
, sp
+ offset
);
1711 offset
-= MIPS_SAVED_REGSIZE
;
1717 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1718 CORE_ADDR start_pc
, limit_pc
;
1719 struct frame_info
*next_frame
;
1723 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1725 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1726 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1727 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1728 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1730 unsigned long inst
, high_word
, low_word
;
1733 /* Fetch the instruction. */
1734 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1736 /* Save some code by pre-extracting some useful fields. */
1737 high_word
= (inst
>> 16) & 0xffff;
1738 low_word
= inst
& 0xffff;
1739 reg
= high_word
& 0x1f;
1741 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1742 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1743 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1745 if (low_word
& 0x8000) /* negative stack adjustment? */
1746 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1748 /* Exit loop if a positive stack adjustment is found, which
1749 usually means that the stack cleanup code in the function
1750 epilogue is reached. */
1753 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1755 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1756 set_reg_offset (reg
, sp
+ low_word
);
1758 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1760 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1761 but the register size used is only 32 bits. Make the address
1762 for the saved register point to the lower 32 bits. */
1763 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1764 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1766 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1768 /* Old gcc frame, r30 is virtual frame pointer. */
1769 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1770 frame_addr
= sp
+ low_word
;
1771 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1773 unsigned alloca_adjust
;
1774 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1775 frame_addr
= read_next_frame_reg (next_frame
, 30);
1776 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1777 if (alloca_adjust
> 0)
1779 /* FP > SP + frame_size. This may be because
1780 * of an alloca or somethings similar.
1781 * Fix sp to "pre-alloca" value, and try again.
1783 sp
+= alloca_adjust
;
1788 /* move $30,$sp. With different versions of gas this will be either
1789 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1790 Accept any one of these. */
1791 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1793 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1794 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1796 unsigned alloca_adjust
;
1797 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1798 frame_addr
= read_next_frame_reg (next_frame
, 30);
1799 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1800 if (alloca_adjust
> 0)
1802 /* FP > SP + frame_size. This may be because
1803 * of an alloca or somethings similar.
1804 * Fix sp to "pre-alloca" value, and try again.
1806 sp
+= alloca_adjust
;
1811 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1813 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1814 set_reg_offset (reg
, frame_addr
+ low_word
);
1819 static mips_extra_func_info_t
1820 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1821 struct frame_info
*next_frame
)
1823 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1827 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1828 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1829 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1830 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1831 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1833 if (start_pc
+ 200 < limit_pc
)
1834 limit_pc
= start_pc
+ 200;
1835 if (pc_is_mips16 (start_pc
))
1836 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1838 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1839 return &temp_proc_desc
;
1842 static mips_extra_func_info_t
1843 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1845 CORE_ADDR startaddr
;
1846 mips_extra_func_info_t proc_desc
;
1847 struct block
*b
= block_for_pc (pc
);
1850 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1852 *addrptr
= startaddr
;
1853 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1857 if (startaddr
> BLOCK_START (b
))
1858 /* This is the "pathological" case referred to in a comment in
1859 print_frame_info. It might be better to move this check into
1863 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1866 /* If we never found a PDR for this function in symbol reading, then
1867 examine prologues to find the information. */
1870 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1871 if (PROC_FRAME_REG (proc_desc
) == -1)
1881 static mips_extra_func_info_t
1882 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
1884 mips_extra_func_info_t proc_desc
;
1885 CORE_ADDR startaddr
;
1887 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1891 /* IF this is the topmost frame AND
1892 * (this proc does not have debugging information OR
1893 * the PC is in the procedure prologue)
1894 * THEN create a "heuristic" proc_desc (by analyzing
1895 * the actual code) to replace the "official" proc_desc.
1897 if (next_frame
== NULL
)
1899 struct symtab_and_line val
;
1900 struct symbol
*proc_symbol
=
1901 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1905 val
= find_pc_line (BLOCK_START
1906 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1908 val
.pc
= val
.end
? val
.end
: pc
;
1910 if (!proc_symbol
|| pc
< val
.pc
)
1912 mips_extra_func_info_t found_heuristic
=
1913 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1915 if (found_heuristic
)
1916 proc_desc
= found_heuristic
;
1922 /* Is linked_proc_desc_table really necessary? It only seems to be used
1923 by procedure call dummys. However, the procedures being called ought
1924 to have their own proc_descs, and even if they don't,
1925 heuristic_proc_desc knows how to create them! */
1927 register struct linked_proc_info
*link
;
1929 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1930 if (PROC_LOW_ADDR (&link
->info
) <= pc
1931 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1935 startaddr
= heuristic_proc_start (pc
);
1938 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1944 get_frame_pointer (struct frame_info
*frame
,
1945 mips_extra_func_info_t proc_desc
)
1947 return ADDR_BITS_REMOVE (
1948 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1949 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1952 mips_extra_func_info_t cached_proc_desc
;
1955 mips_frame_chain (struct frame_info
*frame
)
1957 mips_extra_func_info_t proc_desc
;
1959 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1961 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1964 /* Check if the PC is inside a call stub. If it is, fetch the
1965 PC of the caller of that stub. */
1966 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1969 /* Look up the procedure descriptor for this PC. */
1970 proc_desc
= find_proc_desc (saved_pc
, frame
);
1974 cached_proc_desc
= proc_desc
;
1976 /* If no frame pointer and frame size is zero, we must be at end
1977 of stack (or otherwise hosed). If we don't check frame size,
1978 we loop forever if we see a zero size frame. */
1979 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1980 && PROC_FRAME_OFFSET (proc_desc
) == 0
1981 /* The previous frame from a sigtramp frame might be frameless
1982 and have frame size zero. */
1983 && !frame
->signal_handler_caller
)
1986 return get_frame_pointer (frame
, proc_desc
);
1990 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
1994 /* Use proc_desc calculated in frame_chain */
1995 mips_extra_func_info_t proc_desc
=
1996 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1998 fci
->extra_info
= (struct frame_extra_info
*)
1999 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2001 fci
->saved_regs
= NULL
;
2002 fci
->extra_info
->proc_desc
=
2003 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2006 /* Fixup frame-pointer - only needed for top frame */
2007 /* This may not be quite right, if proc has a real frame register.
2008 Get the value of the frame relative sp, procedure might have been
2009 interrupted by a signal at it's very start. */
2010 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2011 && !PROC_DESC_IS_DUMMY (proc_desc
))
2012 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2014 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2016 if (proc_desc
== &temp_proc_desc
)
2020 /* Do not set the saved registers for a sigtramp frame,
2021 mips_find_saved_registers will do that for us.
2022 We can't use fci->signal_handler_caller, it is not yet set. */
2023 find_pc_partial_function (fci
->pc
, &name
,
2024 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2025 if (!IN_SIGTRAMP (fci
->pc
, name
))
2027 frame_saved_regs_zalloc (fci
);
2028 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2029 fci
->saved_regs
[PC_REGNUM
]
2030 = fci
->saved_regs
[RA_REGNUM
];
2034 /* hack: if argument regs are saved, guess these contain args */
2035 /* assume we can't tell how many args for now */
2036 fci
->extra_info
->num_args
= -1;
2037 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2039 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2041 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2048 /* MIPS stack frames are almost impenetrable. When execution stops,
2049 we basically have to look at symbol information for the function
2050 that we stopped in, which tells us *which* register (if any) is
2051 the base of the frame pointer, and what offset from that register
2052 the frame itself is at.
2054 This presents a problem when trying to examine a stack in memory
2055 (that isn't executing at the moment), using the "frame" command. We
2056 don't have a PC, nor do we have any registers except SP.
2058 This routine takes two arguments, SP and PC, and tries to make the
2059 cached frames look as if these two arguments defined a frame on the
2060 cache. This allows the rest of info frame to extract the important
2061 arguments without difficulty. */
2064 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2067 error ("MIPS frame specifications require two arguments: sp and pc");
2069 return create_new_frame (argv
[0], argv
[1]);
2072 /* According to the current ABI, should the type be passed in a
2073 floating-point register (assuming that there is space)? When there
2074 is no FPU, FP are not even considered as possibile candidates for
2075 FP registers and, consequently this returns false - forces FP
2076 arguments into integer registers. */
2079 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2081 return ((typecode
== TYPE_CODE_FLT
2083 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2084 && TYPE_NFIELDS (arg_type
) == 1
2085 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2086 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2090 mips_push_arguments (int nargs
,
2094 CORE_ADDR struct_addr
)
2100 int stack_offset
= 0;
2102 /* Macros to round N up or down to the next A boundary; A must be
2104 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2105 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2107 /* First ensure that the stack and structure return address (if any)
2108 are properly aligned. The stack has to be at least 64-bit aligned
2109 even on 32-bit machines, because doubles must be 64-bit aligned.
2110 On at least one MIPS variant, stack frames need to be 128-bit
2111 aligned, so we round to this widest known alignment. */
2112 sp
= ROUND_DOWN (sp
, 16);
2113 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2115 /* Now make space on the stack for the args. We allocate more
2116 than necessary for EABI, because the first few arguments are
2117 passed in registers, but that's OK. */
2118 for (argnum
= 0; argnum
< nargs
; argnum
++)
2119 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2120 sp
-= ROUND_UP (len
, 16);
2123 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2124 (long) sp
, ROUND_UP (len
, 16));
2126 /* Initialize the integer and float register pointers. */
2128 float_argreg
= FPA0_REGNUM
;
2130 /* the struct_return pointer occupies the first parameter-passing reg */
2134 fprintf_unfiltered (gdb_stdlog
,
2135 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2136 argreg
, (long) struct_addr
);
2137 write_register (argreg
++, struct_addr
);
2138 if (MIPS_REGS_HAVE_HOME_P
)
2139 stack_offset
+= MIPS_STACK_ARGSIZE
;
2142 /* Now load as many as possible of the first arguments into
2143 registers, and push the rest onto the stack. Loop thru args
2144 from first to last. */
2145 for (argnum
= 0; argnum
< nargs
; argnum
++)
2148 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2149 value_ptr arg
= args
[argnum
];
2150 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2151 int len
= TYPE_LENGTH (arg_type
);
2152 enum type_code typecode
= TYPE_CODE (arg_type
);
2155 fprintf_unfiltered (gdb_stdlog
,
2156 "mips_push_arguments: %d len=%d type=%d",
2157 argnum
+ 1, len
, (int) typecode
);
2159 /* The EABI passes structures that do not fit in a register by
2160 reference. In all other cases, pass the structure by value. */
2162 && len
> MIPS_SAVED_REGSIZE
2163 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2165 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2166 typecode
= TYPE_CODE_PTR
;
2167 len
= MIPS_SAVED_REGSIZE
;
2170 fprintf_unfiltered (gdb_stdlog
, " push");
2173 val
= (char *) VALUE_CONTENTS (arg
);
2175 /* 32-bit ABIs always start floating point arguments in an
2176 even-numbered floating point register. Round the FP register
2177 up before the check to see if there are any FP registers
2178 left. Non MIPS_EABI targets also pass the FP in the integer
2179 registers so also round up normal registers. */
2180 if (!FP_REGISTER_DOUBLE
2181 && fp_register_arg_p (typecode
, arg_type
))
2183 if ((float_argreg
& 1))
2187 /* Floating point arguments passed in registers have to be
2188 treated specially. On 32-bit architectures, doubles
2189 are passed in register pairs; the even register gets
2190 the low word, and the odd register gets the high word.
2191 On non-EABI processors, the first two floating point arguments are
2192 also copied to general registers, because MIPS16 functions
2193 don't use float registers for arguments. This duplication of
2194 arguments in general registers can't hurt non-MIPS16 functions
2195 because those registers are normally skipped. */
2196 /* MIPS_EABI squeeses a struct that contains a single floating
2197 point value into an FP register instead of pusing it onto the
2199 if (fp_register_arg_p (typecode
, arg_type
)
2200 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2202 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2204 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2205 unsigned long regval
;
2207 /* Write the low word of the double to the even register(s). */
2208 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2210 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2211 float_argreg
, phex (regval
, 4));
2212 write_register (float_argreg
++, regval
);
2216 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2217 argreg
, phex (regval
, 4));
2218 write_register (argreg
++, regval
);
2221 /* Write the high word of the double to the odd register(s). */
2222 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2224 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2225 float_argreg
, phex (regval
, 4));
2226 write_register (float_argreg
++, regval
);
2230 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2231 argreg
, phex (regval
, 4));
2232 write_register (argreg
++, regval
);
2238 /* This is a floating point value that fits entirely
2239 in a single register. */
2240 /* On 32 bit ABI's the float_argreg is further adjusted
2241 above to ensure that it is even register aligned. */
2242 LONGEST regval
= extract_unsigned_integer (val
, len
);
2244 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2245 float_argreg
, phex (regval
, len
));
2246 write_register (float_argreg
++, regval
);
2249 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2250 registers for each argument. The below is (my
2251 guess) to ensure that the corresponding integer
2252 register has reserved the same space. */
2254 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2255 argreg
, phex (regval
, len
));
2256 write_register (argreg
, regval
);
2257 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2260 /* Reserve space for the FP register. */
2261 if (MIPS_REGS_HAVE_HOME_P
)
2262 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2266 /* Copy the argument to general registers or the stack in
2267 register-sized pieces. Large arguments are split between
2268 registers and stack. */
2269 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2270 are treated specially: Irix cc passes them in registers
2271 where gcc sometimes puts them on the stack. For maximum
2272 compatibility, we will put them in both places. */
2273 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2274 (len
% MIPS_SAVED_REGSIZE
!= 0));
2275 /* Note: Floating-point values that didn't fit into an FP
2276 register are only written to memory. */
2279 /* Rememer if the argument was written to the stack. */
2280 int stack_used_p
= 0;
2281 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2284 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2287 /* Write this portion of the argument to the stack. */
2288 if (argreg
> MIPS_LAST_ARG_REGNUM
2290 || fp_register_arg_p (typecode
, arg_type
))
2292 /* Should shorter than int integer values be
2293 promoted to int before being stored? */
2294 int longword_offset
= 0;
2297 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2299 if (MIPS_STACK_ARGSIZE
== 8 &&
2300 (typecode
== TYPE_CODE_INT
||
2301 typecode
== TYPE_CODE_PTR
||
2302 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2303 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2304 else if ((typecode
== TYPE_CODE_STRUCT
||
2305 typecode
== TYPE_CODE_UNION
) &&
2306 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2307 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2312 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2313 (long) stack_offset
);
2314 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2315 (long) longword_offset
);
2318 addr
= sp
+ stack_offset
+ longword_offset
;
2323 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2324 for (i
= 0; i
< partial_len
; i
++)
2326 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2329 write_memory (addr
, val
, partial_len
);
2332 /* Note!!! This is NOT an else clause. Odd sized
2333 structs may go thru BOTH paths. Floating point
2334 arguments will not. */
2335 /* Write this portion of the argument to a general
2336 purpose register. */
2337 if (argreg
<= MIPS_LAST_ARG_REGNUM
2338 && !fp_register_arg_p (typecode
, arg_type
))
2340 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2342 /* A non-floating-point argument being passed in a
2343 general register. If a struct or union, and if
2344 the remaining length is smaller than the register
2345 size, we have to adjust the register value on
2348 It does not seem to be necessary to do the
2349 same for integral types.
2351 Also don't do this adjustment on EABI and O64
2355 && MIPS_SAVED_REGSIZE
< 8
2356 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2357 && partial_len
< MIPS_SAVED_REGSIZE
2358 && (typecode
== TYPE_CODE_STRUCT
||
2359 typecode
== TYPE_CODE_UNION
))
2360 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2364 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2366 phex (regval
, MIPS_SAVED_REGSIZE
));
2367 write_register (argreg
, regval
);
2370 /* If this is the old ABI, prevent subsequent floating
2371 point arguments from being passed in floating point
2374 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2380 /* Compute the the offset into the stack at which we
2381 will copy the next parameter.
2383 In older ABIs, the caller reserved space for
2384 registers that contained arguments. This was loosely
2385 refered to as their "home". Consequently, space is
2388 In the new EABI (and the NABI32), the stack_offset
2389 only needs to be adjusted when it has been used.. */
2391 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2392 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2396 fprintf_unfiltered (gdb_stdlog
, "\n");
2399 /* Return adjusted stack pointer. */
2404 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2406 /* Set the return address register to point to the entry
2407 point of the program, where a breakpoint lies in wait. */
2408 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2413 mips_push_register (CORE_ADDR
* sp
, int regno
)
2415 char buffer
[MAX_REGISTER_RAW_SIZE
];
2418 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2420 regsize
= MIPS_SAVED_REGSIZE
;
2421 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2422 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2427 regsize
= REGISTER_RAW_SIZE (regno
);
2431 read_register_gen (regno
, buffer
);
2432 write_memory (*sp
, buffer
+ offset
, regsize
);
2435 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2436 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2439 mips_push_dummy_frame (void)
2442 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2443 xmalloc (sizeof (struct linked_proc_info
));
2444 mips_extra_func_info_t proc_desc
= &link
->info
;
2445 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2446 CORE_ADDR old_sp
= sp
;
2447 link
->next
= linked_proc_desc_table
;
2448 linked_proc_desc_table
= link
;
2450 /* FIXME! are these correct ? */
2451 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2452 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2453 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2454 #define FLOAT_SINGLE_REG_SAVE_MASK \
2455 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2457 * The registers we must save are all those not preserved across
2458 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2459 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2460 * and FP Control/Status registers.
2463 * Dummy frame layout:
2466 * Saved MMHI, MMLO, FPC_CSR
2471 * Saved D18 (i.e. F19, F18)
2473 * Saved D0 (i.e. F1, F0)
2474 * Argument build area and stack arguments written via mips_push_arguments
2478 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2479 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2480 PROC_FRAME_OFFSET (proc_desc
) = 0;
2481 PROC_FRAME_ADJUST (proc_desc
) = 0;
2482 mips_push_register (&sp
, PC_REGNUM
);
2483 mips_push_register (&sp
, HI_REGNUM
);
2484 mips_push_register (&sp
, LO_REGNUM
);
2485 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2487 /* Save general CPU registers */
2488 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2489 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2490 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2491 for (ireg
= 32; --ireg
>= 0;)
2492 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2493 mips_push_register (&sp
, ireg
);
2495 /* Save floating point registers starting with high order word */
2496 PROC_FREG_MASK (proc_desc
) =
2497 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2498 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2499 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2501 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2502 for (ireg
= 32; --ireg
>= 0;)
2503 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2504 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2506 /* Update the frame pointer for the call dummy and the stack pointer.
2507 Set the procedure's starting and ending addresses to point to the
2508 call dummy address at the entry point. */
2509 write_register (PUSH_FP_REGNUM
, old_sp
);
2510 write_register (SP_REGNUM
, sp
);
2511 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2512 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2513 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2514 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2518 mips_pop_frame (void)
2520 register int regnum
;
2521 struct frame_info
*frame
= get_current_frame ();
2522 CORE_ADDR new_sp
= FRAME_FP (frame
);
2524 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2526 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2527 if (frame
->saved_regs
== NULL
)
2528 mips_find_saved_regs (frame
);
2529 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2531 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2532 && frame
->saved_regs
[regnum
])
2533 write_register (regnum
,
2534 read_memory_integer (frame
->saved_regs
[regnum
],
2535 MIPS_SAVED_REGSIZE
));
2537 write_register (SP_REGNUM
, new_sp
);
2538 flush_cached_frames ();
2540 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2542 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2544 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2546 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2548 if (&pi_ptr
->info
== proc_desc
)
2553 error ("Can't locate dummy extra frame info\n");
2555 if (prev_ptr
!= NULL
)
2556 prev_ptr
->next
= pi_ptr
->next
;
2558 linked_proc_desc_table
= pi_ptr
->next
;
2562 write_register (HI_REGNUM
,
2563 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2564 MIPS_SAVED_REGSIZE
));
2565 write_register (LO_REGNUM
,
2566 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2567 MIPS_SAVED_REGSIZE
));
2568 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2569 write_register (FCRCS_REGNUM
,
2570 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2571 MIPS_SAVED_REGSIZE
));
2576 mips_print_register (int regnum
, int all
)
2578 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2580 /* Get the data in raw format. */
2581 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2583 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2587 /* If an even floating point register, also print as double. */
2588 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2589 && !((regnum
- FP0_REGNUM
) & 1))
2590 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2592 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2594 read_relative_register_raw_bytes (regnum
, dbuffer
);
2595 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2596 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2598 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2599 val_print (builtin_type_double
, dbuffer
, 0, 0,
2600 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2601 printf_filtered ("); ");
2603 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2605 /* The problem with printing numeric register names (r26, etc.) is that
2606 the user can't use them on input. Probably the best solution is to
2607 fix it so that either the numeric or the funky (a2, etc.) names
2608 are accepted on input. */
2609 if (regnum
< MIPS_NUMREGS
)
2610 printf_filtered ("(r%d): ", regnum
);
2612 printf_filtered (": ");
2614 /* If virtual format is floating, print it that way. */
2615 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2616 if (FP_REGISTER_DOUBLE
)
2617 { /* show 8-byte floats as float AND double: */
2618 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2620 printf_filtered (" (float) ");
2621 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2622 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2623 printf_filtered (", (double) ");
2624 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2625 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2628 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2629 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2630 /* Else print as integer in hex. */
2635 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2636 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2640 print_scalar_formatted (raw_buffer
+ offset
,
2641 REGISTER_VIRTUAL_TYPE (regnum
),
2642 'x', 0, gdb_stdout
);
2646 /* Replacement for generic do_registers_info.
2647 Print regs in pretty columns. */
2650 do_fp_register_row (int regnum
)
2651 { /* do values for FP (float) regs */
2652 char *raw_buffer
[2];
2654 /* use HI and LO to control the order of combining two flt regs */
2655 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2656 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2657 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2658 int inv1
, inv2
, inv3
;
2660 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2661 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2662 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2664 /* Get the data in raw format. */
2665 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2666 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2667 if (REGISTER_RAW_SIZE (regnum
) == 4)
2669 /* 4-byte registers: we can fit two registers per row. */
2670 /* Also print every pair of 4-byte regs as an 8-byte double. */
2671 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2672 error ("can't read register %d (%s)",
2673 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2675 /* copy the two floats into one double, and unpack both */
2676 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2677 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2678 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2679 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2681 printf_filtered (inv1
? " %-5s: <invalid float>" :
2682 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2683 printf_filtered (inv2
? " %-5s: <invalid float>" :
2684 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2685 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2686 " dbl: %-24.17g\n", doub
);
2687 /* may want to do hex display here (future enhancement) */
2691 { /* eight byte registers: print each one as float AND as double. */
2692 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2694 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2695 flt1
= unpack_double (builtin_type_float
,
2696 &raw_buffer
[HI
][offset
], &inv1
);
2697 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2699 printf_filtered (inv1
? " %-5s: <invalid float>" :
2700 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2701 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2702 " dbl: %-24.17g\n", doub
);
2703 /* may want to do hex display here (future enhancement) */
2709 /* Print a row's worth of GP (int) registers, with name labels above */
2712 do_gp_register_row (int regnum
)
2714 /* do values for GP (int) regs */
2715 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2716 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2718 int start_regnum
= regnum
;
2719 int numregs
= NUM_REGS
;
2722 /* For GP registers, we print a separate row of names above the vals */
2723 printf_filtered (" ");
2724 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2726 if (*REGISTER_NAME (regnum
) == '\0')
2727 continue; /* unused register */
2728 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2729 break; /* end the row: reached FP register */
2730 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2731 REGISTER_NAME (regnum
));
2734 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2735 start_regnum
); /* print the R0 to R31 names */
2737 regnum
= start_regnum
; /* go back to start of row */
2738 /* now print the values in hex, 4 or 8 to the row */
2739 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2741 if (*REGISTER_NAME (regnum
) == '\0')
2742 continue; /* unused register */
2743 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2744 break; /* end row: reached FP register */
2745 /* OK: get the data in raw format. */
2746 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2747 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2748 /* pad small registers */
2749 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2750 printf_filtered (" ");
2751 /* Now print the register value in hex, endian order. */
2752 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2753 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2754 byte
< REGISTER_RAW_SIZE (regnum
);
2756 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2758 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2761 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2762 printf_filtered (" ");
2765 if (col
> 0) /* ie. if we actually printed anything... */
2766 printf_filtered ("\n");
2771 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2774 mips_do_registers_info (int regnum
, int fpregs
)
2776 if (regnum
!= -1) /* do one specified register */
2778 if (*(REGISTER_NAME (regnum
)) == '\0')
2779 error ("Not a valid register for the current processor type");
2781 mips_print_register (regnum
, 0);
2782 printf_filtered ("\n");
2785 /* do all (or most) registers */
2788 while (regnum
< NUM_REGS
)
2790 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2791 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2792 regnum
= do_fp_register_row (regnum
); /* FP regs */
2794 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2796 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2801 /* Return number of args passed to a frame. described by FIP.
2802 Can return -1, meaning no way to tell. */
2805 mips_frame_num_args (struct frame_info
*frame
)
2810 /* Is this a branch with a delay slot? */
2812 static int is_delayed (unsigned long);
2815 is_delayed (unsigned long insn
)
2818 for (i
= 0; i
< NUMOPCODES
; ++i
)
2819 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2820 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2822 return (i
< NUMOPCODES
2823 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2824 | INSN_COND_BRANCH_DELAY
2825 | INSN_COND_BRANCH_LIKELY
)));
2829 mips_step_skips_delay (CORE_ADDR pc
)
2831 char buf
[MIPS_INSTLEN
];
2833 /* There is no branch delay slot on MIPS16. */
2834 if (pc_is_mips16 (pc
))
2837 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2838 /* If error reading memory, guess that it is not a delayed branch. */
2840 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2844 /* Skip the PC past function prologue instructions (32-bit version).
2845 This is a helper function for mips_skip_prologue. */
2848 mips32_skip_prologue (CORE_ADDR pc
)
2852 int seen_sp_adjust
= 0;
2853 int load_immediate_bytes
= 0;
2855 /* Skip the typical prologue instructions. These are the stack adjustment
2856 instruction and the instructions that save registers on the stack
2857 or in the gcc frame. */
2858 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2860 unsigned long high_word
;
2862 inst
= mips_fetch_instruction (pc
);
2863 high_word
= (inst
>> 16) & 0xffff;
2865 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2866 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2868 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2869 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2871 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2872 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2873 && (inst
& 0x001F0000)) /* reg != $zero */
2876 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2878 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2880 continue; /* reg != $zero */
2882 /* move $s8,$sp. With different versions of gas this will be either
2883 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2884 Accept any one of these. */
2885 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2888 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2890 else if (high_word
== 0x3c1c) /* lui $gp,n */
2892 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2894 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2895 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2897 /* The following instructions load $at or $t0 with an immediate
2898 value in preparation for a stack adjustment via
2899 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2900 a local variable, so we accept them only before a stack adjustment
2901 instruction was seen. */
2902 else if (!seen_sp_adjust
)
2904 if (high_word
== 0x3c01 || /* lui $at,n */
2905 high_word
== 0x3c08) /* lui $t0,n */
2907 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2910 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2911 high_word
== 0x3508 || /* ori $t0,$t0,n */
2912 high_word
== 0x3401 || /* ori $at,$zero,n */
2913 high_word
== 0x3408) /* ori $t0,$zero,n */
2915 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2925 /* In a frameless function, we might have incorrectly
2926 skipped some load immediate instructions. Undo the skipping
2927 if the load immediate was not followed by a stack adjustment. */
2928 if (load_immediate_bytes
&& !seen_sp_adjust
)
2929 pc
-= load_immediate_bytes
;
2933 /* Skip the PC past function prologue instructions (16-bit version).
2934 This is a helper function for mips_skip_prologue. */
2937 mips16_skip_prologue (CORE_ADDR pc
)
2940 int extend_bytes
= 0;
2941 int prev_extend_bytes
;
2943 /* Table of instructions likely to be found in a function prologue. */
2946 unsigned short inst
;
2947 unsigned short mask
;
2954 , /* addiu $sp,offset */
2958 , /* daddiu $sp,offset */
2962 , /* sw reg,n($sp) */
2966 , /* sd reg,n($sp) */
2970 , /* sw $ra,n($sp) */
2974 , /* sd $ra,n($sp) */
2982 , /* sw $a0-$a3,n($s1) */
2986 , /* move reg,$a0-$a3 */
2990 , /* entry pseudo-op */
2994 , /* addiu $s1,$sp,n */
2997 } /* end of table marker */
3000 /* Skip the typical prologue instructions. These are the stack adjustment
3001 instruction and the instructions that save registers on the stack
3002 or in the gcc frame. */
3003 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3005 unsigned short inst
;
3008 inst
= mips_fetch_instruction (pc
);
3010 /* Normally we ignore an extend instruction. However, if it is
3011 not followed by a valid prologue instruction, we must adjust
3012 the pc back over the extend so that it won't be considered
3013 part of the prologue. */
3014 if ((inst
& 0xf800) == 0xf000) /* extend */
3016 extend_bytes
= MIPS16_INSTLEN
;
3019 prev_extend_bytes
= extend_bytes
;
3022 /* Check for other valid prologue instructions besides extend. */
3023 for (i
= 0; table
[i
].mask
!= 0; i
++)
3024 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3026 if (table
[i
].mask
!= 0) /* it was in table? */
3027 continue; /* ignore it */
3031 /* Return the current pc, adjusted backwards by 2 if
3032 the previous instruction was an extend. */
3033 return pc
- prev_extend_bytes
;
3039 /* To skip prologues, I use this predicate. Returns either PC itself
3040 if the code at PC does not look like a function prologue; otherwise
3041 returns an address that (if we're lucky) follows the prologue. If
3042 LENIENT, then we must skip everything which is involved in setting
3043 up the frame (it's OK to skip more, just so long as we don't skip
3044 anything which might clobber the registers which are being saved.
3045 We must skip more in the case where part of the prologue is in the
3046 delay slot of a non-prologue instruction). */
3049 mips_skip_prologue (CORE_ADDR pc
)
3051 /* See if we can determine the end of the prologue via the symbol table.
3052 If so, then return either PC, or the PC after the prologue, whichever
3055 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3057 if (post_prologue_pc
!= 0)
3058 return max (pc
, post_prologue_pc
);
3060 /* Can't determine prologue from the symbol table, need to examine
3063 if (pc_is_mips16 (pc
))
3064 return mips16_skip_prologue (pc
);
3066 return mips32_skip_prologue (pc
);
3069 /* Determine how a return value is stored within the MIPS register
3070 file, given the return type `valtype'. */
3072 struct return_value_word
3081 return_value_location (struct type
*valtype
,
3082 struct return_value_word
*hi
,
3083 struct return_value_word
*lo
)
3085 int len
= TYPE_LENGTH (valtype
);
3087 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3088 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3089 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3091 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3093 /* We need to break a 64bit float in two 32 bit halves and
3094 spread them across a floating-point register pair. */
3095 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3096 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3097 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3098 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3100 hi
->reg_offset
= lo
->reg_offset
;
3101 lo
->reg
= FP0_REGNUM
+ 0;
3102 hi
->reg
= FP0_REGNUM
+ 1;
3108 /* The floating point value fits in a single floating-point
3110 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3111 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3114 lo
->reg
= FP0_REGNUM
;
3125 /* Locate a result possibly spread across two registers. */
3127 lo
->reg
= regnum
+ 0;
3128 hi
->reg
= regnum
+ 1;
3129 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3130 && len
< MIPS_SAVED_REGSIZE
)
3132 /* "un-left-justify" the value in the low register */
3133 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3138 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3139 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3140 && len
< MIPS_SAVED_REGSIZE
* 2
3141 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3142 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3144 /* "un-left-justify" the value spread across two registers. */
3145 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3146 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3148 hi
->len
= len
- lo
->len
;
3152 /* Only perform a partial copy of the second register. */
3155 if (len
> MIPS_SAVED_REGSIZE
)
3157 lo
->len
= MIPS_SAVED_REGSIZE
;
3158 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3166 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3167 && REGISTER_RAW_SIZE (regnum
) == 8
3168 && MIPS_SAVED_REGSIZE
== 4)
3170 /* Account for the fact that only the least-signficant part
3171 of the register is being used */
3172 lo
->reg_offset
+= 4;
3173 hi
->reg_offset
+= 4;
3176 hi
->buf_offset
= lo
->len
;
3180 /* Given a return value in `regbuf' with a type `valtype', extract and
3181 copy its value into `valbuf'. */
3184 mips_extract_return_value (struct type
*valtype
,
3185 char regbuf
[REGISTER_BYTES
],
3188 struct return_value_word lo
;
3189 struct return_value_word hi
;
3190 return_value_location (valtype
, &lo
, &hi
);
3192 memcpy (valbuf
+ lo
.buf_offset
,
3193 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3197 memcpy (valbuf
+ hi
.buf_offset
,
3198 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3202 /* Given a return value in `valbuf' with a type `valtype', write it's
3203 value into the appropriate register. */
3206 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3208 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3209 struct return_value_word lo
;
3210 struct return_value_word hi
;
3211 return_value_location (valtype
, &lo
, &hi
);
3213 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3214 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3215 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3217 REGISTER_RAW_SIZE (lo
.reg
));
3221 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3222 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3223 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3225 REGISTER_RAW_SIZE (hi
.reg
));
3229 /* Exported procedure: Is PC in the signal trampoline code */
3232 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3234 if (sigtramp_address
== 0)
3236 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3239 /* Root of all "set mips "/"show mips " commands. This will eventually be
3240 used for all MIPS-specific commands. */
3243 show_mips_command (char *args
, int from_tty
)
3245 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3249 set_mips_command (char *args
, int from_tty
)
3251 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3252 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3255 /* Commands to show/set the MIPS FPU type. */
3258 show_mipsfpu_command (char *args
, int from_tty
)
3262 switch (MIPS_FPU_TYPE
)
3264 case MIPS_FPU_SINGLE
:
3265 fpu
= "single-precision";
3267 case MIPS_FPU_DOUBLE
:
3268 fpu
= "double-precision";
3271 fpu
= "absent (none)";
3274 if (mips_fpu_type_auto
)
3275 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3278 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3284 set_mipsfpu_command (char *args
, int from_tty
)
3286 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3287 show_mipsfpu_command (args
, from_tty
);
3291 set_mipsfpu_single_command (char *args
, int from_tty
)
3293 mips_fpu_type
= MIPS_FPU_SINGLE
;
3294 mips_fpu_type_auto
= 0;
3297 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3302 set_mipsfpu_double_command (char *args
, int from_tty
)
3304 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3305 mips_fpu_type_auto
= 0;
3308 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3313 set_mipsfpu_none_command (char *args
, int from_tty
)
3315 mips_fpu_type
= MIPS_FPU_NONE
;
3316 mips_fpu_type_auto
= 0;
3319 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3324 set_mipsfpu_auto_command (char *args
, int from_tty
)
3326 mips_fpu_type_auto
= 1;
3329 /* Command to set the processor type. */
3332 mips_set_processor_type_command (char *args
, int from_tty
)
3336 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3338 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3339 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3340 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3342 /* Restore the value. */
3343 tmp_mips_processor_type
= strsave (mips_processor_type
);
3348 if (!mips_set_processor_type (tmp_mips_processor_type
))
3350 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3351 /* Restore its value. */
3352 tmp_mips_processor_type
= strsave (mips_processor_type
);
3357 mips_show_processor_type_command (char *args
, int from_tty
)
3361 /* Modify the actual processor type. */
3364 mips_set_processor_type (char *str
)
3371 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3373 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3375 mips_processor_type
= str
;
3376 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3378 /* FIXME tweak fpu flag too */
3385 /* Attempt to identify the particular processor model by reading the
3389 mips_read_processor_type (void)
3393 prid
= read_register (PRID_REGNUM
);
3395 if ((prid
& ~0xf) == 0x700)
3396 return savestring ("r3041", strlen ("r3041"));
3401 /* Just like reinit_frame_cache, but with the right arguments to be
3402 callable as an sfunc. */
3405 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3406 struct cmd_list_element
*c
)
3408 reinit_frame_cache ();
3412 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3414 mips_extra_func_info_t proc_desc
;
3416 /* Search for the function containing this address. Set the low bit
3417 of the address when searching, in case we were given an even address
3418 that is the start of a 16-bit function. If we didn't do this,
3419 the search would fail because the symbol table says the function
3420 starts at an odd address, i.e. 1 byte past the given address. */
3421 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3422 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3424 /* Make an attempt to determine if this is a 16-bit function. If
3425 the procedure descriptor exists and the address therein is odd,
3426 it's definitely a 16-bit function. Otherwise, we have to just
3427 guess that if the address passed in is odd, it's 16-bits. */
3429 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3430 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3432 info
->mach
= pc_is_mips16 (memaddr
) ?
3433 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3435 /* Round down the instruction address to the appropriate boundary. */
3436 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3438 /* Call the appropriate disassembler based on the target endian-ness. */
3439 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3440 return print_insn_big_mips (memaddr
, info
);
3442 return print_insn_little_mips (memaddr
, info
);
3445 /* Old-style breakpoint macros.
3446 The IDT board uses an unusual breakpoint value, and sometimes gets
3447 confused when it sees the usual MIPS breakpoint instruction. */
3449 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3450 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3451 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3452 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3453 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3454 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3455 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3456 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3458 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3459 counter value to determine whether a 16- or 32-bit breakpoint should be
3460 used. It returns a pointer to a string of bytes that encode a breakpoint
3461 instruction, stores the length of the string to *lenptr, and adjusts pc
3462 (if necessary) to point to the actual memory location where the
3463 breakpoint should be inserted. */
3466 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3468 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3470 if (pc_is_mips16 (*pcptr
))
3472 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3473 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3474 *lenptr
= sizeof (mips16_big_breakpoint
);
3475 return mips16_big_breakpoint
;
3479 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3480 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3481 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3483 *lenptr
= sizeof (big_breakpoint
);
3485 if (strcmp (target_shortname
, "mips") == 0)
3486 return idt_big_breakpoint
;
3487 else if (strcmp (target_shortname
, "ddb") == 0
3488 || strcmp (target_shortname
, "pmon") == 0
3489 || strcmp (target_shortname
, "lsi") == 0)
3490 return pmon_big_breakpoint
;
3492 return big_breakpoint
;
3497 if (pc_is_mips16 (*pcptr
))
3499 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3500 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3501 *lenptr
= sizeof (mips16_little_breakpoint
);
3502 return mips16_little_breakpoint
;
3506 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3507 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3508 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3510 *lenptr
= sizeof (little_breakpoint
);
3512 if (strcmp (target_shortname
, "mips") == 0)
3513 return idt_little_breakpoint
;
3514 else if (strcmp (target_shortname
, "ddb") == 0
3515 || strcmp (target_shortname
, "pmon") == 0
3516 || strcmp (target_shortname
, "lsi") == 0)
3517 return pmon_little_breakpoint
;
3519 return little_breakpoint
;
3524 /* If PC is in a mips16 call or return stub, return the address of the target
3525 PC, which is either the callee or the caller. There are several
3526 cases which must be handled:
3528 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3529 target PC is in $31 ($ra).
3530 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3531 and the target PC is in $2.
3532 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3533 before the jal instruction, this is effectively a call stub
3534 and the the target PC is in $2. Otherwise this is effectively
3535 a return stub and the target PC is in $18.
3537 See the source code for the stubs in gcc/config/mips/mips16.S for
3540 This function implements the SKIP_TRAMPOLINE_CODE macro.
3544 mips_skip_stub (CORE_ADDR pc
)
3547 CORE_ADDR start_addr
;
3549 /* Find the starting address and name of the function containing the PC. */
3550 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3553 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3554 target PC is in $31 ($ra). */
3555 if (strcmp (name
, "__mips16_ret_sf") == 0
3556 || strcmp (name
, "__mips16_ret_df") == 0)
3557 return read_signed_register (RA_REGNUM
);
3559 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3561 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3562 and the target PC is in $2. */
3563 if (name
[19] >= '0' && name
[19] <= '9')
3564 return read_signed_register (2);
3566 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3567 before the jal instruction, this is effectively a call stub
3568 and the the target PC is in $2. Otherwise this is effectively
3569 a return stub and the target PC is in $18. */
3570 else if (name
[19] == 's' || name
[19] == 'd')
3572 if (pc
== start_addr
)
3574 /* Check if the target of the stub is a compiler-generated
3575 stub. Such a stub for a function bar might have a name
3576 like __fn_stub_bar, and might look like this:
3581 la $1,bar (becomes a lui/addiu pair)
3583 So scan down to the lui/addi and extract the target
3584 address from those two instructions. */
3586 CORE_ADDR target_pc
= read_signed_register (2);
3590 /* See if the name of the target function is __fn_stub_*. */
3591 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3593 if (strncmp (name
, "__fn_stub_", 10) != 0
3594 && strcmp (name
, "etext") != 0
3595 && strcmp (name
, "_etext") != 0)
3598 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3599 The limit on the search is arbitrarily set to 20
3600 instructions. FIXME. */
3601 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3603 inst
= mips_fetch_instruction (target_pc
);
3604 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3605 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3606 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3607 return pc
| (inst
& 0xffff); /* low word */
3610 /* Couldn't find the lui/addui pair, so return stub address. */
3614 /* This is the 'return' part of a call stub. The return
3615 address is in $r18. */
3616 return read_signed_register (18);
3619 return 0; /* not a stub */
3623 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3624 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3627 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3629 CORE_ADDR start_addr
;
3631 /* Find the starting address of the function containing the PC. If the
3632 caller didn't give us a name, look it up at the same time. */
3633 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3636 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3638 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3639 if (name
[19] >= '0' && name
[19] <= '9')
3641 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3642 before the jal instruction, this is effectively a call stub. */
3643 else if (name
[19] == 's' || name
[19] == 'd')
3644 return pc
== start_addr
;
3647 return 0; /* not a stub */
3651 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3652 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3655 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3657 CORE_ADDR start_addr
;
3659 /* Find the starting address of the function containing the PC. */
3660 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3663 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3664 if (strcmp (name
, "__mips16_ret_sf") == 0
3665 || strcmp (name
, "__mips16_ret_df") == 0)
3668 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3669 i.e. after the jal instruction, this is effectively a return stub. */
3670 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3671 && (name
[19] == 's' || name
[19] == 'd')
3672 && pc
!= start_addr
)
3675 return 0; /* not a stub */
3679 /* Return non-zero if the PC is in a library helper function that should
3680 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3683 mips_ignore_helper (CORE_ADDR pc
)
3687 /* Find the starting address and name of the function containing the PC. */
3688 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3691 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3692 that we want to ignore. */
3693 return (strcmp (name
, "__mips16_ret_sf") == 0
3694 || strcmp (name
, "__mips16_ret_df") == 0);
3698 /* Return a location where we can set a breakpoint that will be hit
3699 when an inferior function call returns. This is normally the
3700 program's entry point. Executables that don't have an entry
3701 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3702 whose address is the location where the breakpoint should be placed. */
3705 mips_call_dummy_address (void)
3707 struct minimal_symbol
*sym
;
3709 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3711 return SYMBOL_VALUE_ADDRESS (sym
);
3713 return entry_point_address ();
3717 /* If the current gcc for for this target does not produce correct debugging
3718 information for float parameters, both prototyped and unprototyped, then
3719 define this macro. This forces gdb to always assume that floats are
3720 passed as doubles and then converted in the callee.
3722 For the mips chip, it appears that the debug info marks the parameters as
3723 floats regardless of whether the function is prototyped, but the actual
3724 values are passed as doubles for the non-prototyped case and floats for
3725 the prototyped case. Thus we choose to make the non-prototyped case work
3726 for C and break the prototyped case, since the non-prototyped case is
3727 probably much more common. (FIXME). */
3730 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3732 return current_language
->la_language
== language_c
;
3735 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3736 the register stored on the stack (32) is different to its real raw
3737 size (64). The below ensures that registers are fetched from the
3738 stack using their ABI size and then stored into the RAW_BUFFER
3739 using their raw size.
3741 The alternative to adding this function would be to add an ABI
3742 macro - REGISTER_STACK_SIZE(). */
3745 mips_get_saved_register (char *raw_buffer
,
3748 struct frame_info
*frame
,
3750 enum lval_type
*lval
)
3754 if (!target_has_registers
)
3755 error ("No registers.");
3757 /* Normal systems don't optimize out things with register numbers. */
3758 if (optimized
!= NULL
)
3760 addr
= find_saved_register (frame
, regnum
);
3764 *lval
= lval_memory
;
3765 if (regnum
== SP_REGNUM
)
3767 if (raw_buffer
!= NULL
)
3769 /* Put it back in target format. */
3770 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3777 if (raw_buffer
!= NULL
)
3781 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3783 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3785 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3786 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3792 *lval
= lval_register
;
3793 addr
= REGISTER_BYTE (regnum
);
3794 if (raw_buffer
!= NULL
)
3795 read_register_gen (regnum
, raw_buffer
);
3801 /* Immediately after a function call, return the saved pc.
3802 Can't always go through the frames for this because on some machines
3803 the new frame is not set up until the new function executes
3804 some instructions. */
3807 mips_saved_pc_after_call (struct frame_info
*frame
)
3809 return read_signed_register (RA_REGNUM
);
3813 static struct gdbarch
*
3814 mips_gdbarch_init (struct gdbarch_info info
,
3815 struct gdbarch_list
*arches
)
3817 static LONGEST mips_call_dummy_words
[] =
3819 struct gdbarch
*gdbarch
;
3820 struct gdbarch_tdep
*tdep
;
3822 enum mips_abi mips_abi
;
3824 /* Extract the elf_flags if available */
3825 if (info
.abfd
!= NULL
3826 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3827 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3831 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3832 switch ((elf_flags
& EF_MIPS_ABI
))
3834 case E_MIPS_ABI_O32
:
3835 mips_abi
= MIPS_ABI_O32
;
3837 case E_MIPS_ABI_O64
:
3838 mips_abi
= MIPS_ABI_O64
;
3840 case E_MIPS_ABI_EABI32
:
3841 mips_abi
= MIPS_ABI_EABI32
;
3843 case E_MIPS_ABI_EABI64
:
3844 mips_abi
= MIPS_ABI_EABI64
;
3847 if ((elf_flags
& EF_MIPS_ABI2
))
3848 mips_abi
= MIPS_ABI_N32
;
3850 mips_abi
= MIPS_ABI_UNKNOWN
;
3854 /* Try the architecture for any hint of the corect ABI */
3855 if (mips_abi
== MIPS_ABI_UNKNOWN
3856 && info
.bfd_arch_info
!= NULL
3857 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3859 switch (info
.bfd_arch_info
->mach
)
3861 case bfd_mach_mips3900
:
3862 mips_abi
= MIPS_ABI_EABI32
;
3864 case bfd_mach_mips4100
:
3865 case bfd_mach_mips5000
:
3866 mips_abi
= MIPS_ABI_EABI64
;
3870 #ifdef MIPS_DEFAULT_ABI
3871 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3872 mips_abi
= MIPS_DEFAULT_ABI
;
3877 fprintf_unfiltered (gdb_stdlog
,
3878 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3880 fprintf_unfiltered (gdb_stdlog
,
3881 "mips_gdbarch_init: mips_abi = %d\n",
3885 /* try to find a pre-existing architecture */
3886 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3888 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3890 /* MIPS needs to be pedantic about which ABI the object is
3892 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3894 if (gdbarch_tdep (current_gdbarch
)->mips_abi
!= mips_abi
)
3896 return arches
->gdbarch
;
3899 /* Need a new architecture. Fill in a target specific vector. */
3900 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3901 gdbarch
= gdbarch_alloc (&info
, tdep
);
3902 tdep
->elf_flags
= elf_flags
;
3904 /* Initially set everything according to the ABI. */
3905 set_gdbarch_short_bit (gdbarch
, 16);
3906 set_gdbarch_int_bit (gdbarch
, 32);
3907 set_gdbarch_float_bit (gdbarch
, 32);
3908 set_gdbarch_double_bit (gdbarch
, 64);
3909 set_gdbarch_long_double_bit (gdbarch
, 64);
3910 tdep
->mips_abi
= mips_abi
;
3914 tdep
->mips_abi_string
= "o32";
3915 tdep
->mips_default_saved_regsize
= 4;
3916 tdep
->mips_default_stack_argsize
= 4;
3917 tdep
->mips_fp_register_double
= 0;
3918 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3919 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3920 tdep
->mips_regs_have_home_p
= 1;
3921 tdep
->gdb_target_is_mips64
= 0;
3922 tdep
->default_mask_address_p
= 0;
3923 set_gdbarch_long_bit (gdbarch
, 32);
3924 set_gdbarch_ptr_bit (gdbarch
, 32);
3925 set_gdbarch_long_long_bit (gdbarch
, 64);
3928 tdep
->mips_abi_string
= "o64";
3929 tdep
->mips_default_saved_regsize
= 8;
3930 tdep
->mips_default_stack_argsize
= 8;
3931 tdep
->mips_fp_register_double
= 1;
3932 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3933 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3934 tdep
->mips_regs_have_home_p
= 1;
3935 tdep
->gdb_target_is_mips64
= 1;
3936 tdep
->default_mask_address_p
= 0;
3937 set_gdbarch_long_bit (gdbarch
, 32);
3938 set_gdbarch_ptr_bit (gdbarch
, 32);
3939 set_gdbarch_long_long_bit (gdbarch
, 64);
3941 case MIPS_ABI_EABI32
:
3942 tdep
->mips_abi_string
= "eabi32";
3943 tdep
->mips_default_saved_regsize
= 4;
3944 tdep
->mips_default_stack_argsize
= 4;
3945 tdep
->mips_fp_register_double
= 0;
3946 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3947 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3948 tdep
->mips_regs_have_home_p
= 0;
3949 tdep
->gdb_target_is_mips64
= 0;
3950 tdep
->default_mask_address_p
= 0;
3951 set_gdbarch_long_bit (gdbarch
, 32);
3952 set_gdbarch_ptr_bit (gdbarch
, 32);
3953 set_gdbarch_long_long_bit (gdbarch
, 64);
3955 case MIPS_ABI_EABI64
:
3956 tdep
->mips_abi_string
= "eabi64";
3957 tdep
->mips_default_saved_regsize
= 8;
3958 tdep
->mips_default_stack_argsize
= 8;
3959 tdep
->mips_fp_register_double
= 1;
3960 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3961 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3962 tdep
->mips_regs_have_home_p
= 0;
3963 tdep
->gdb_target_is_mips64
= 1;
3964 tdep
->default_mask_address_p
= 0;
3965 set_gdbarch_long_bit (gdbarch
, 64);
3966 set_gdbarch_ptr_bit (gdbarch
, 64);
3967 set_gdbarch_long_long_bit (gdbarch
, 64);
3970 tdep
->mips_abi_string
= "n32";
3971 tdep
->mips_default_saved_regsize
= 4;
3972 tdep
->mips_default_stack_argsize
= 8;
3973 tdep
->mips_fp_register_double
= 1;
3974 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3975 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3976 tdep
->mips_regs_have_home_p
= 0;
3977 tdep
->gdb_target_is_mips64
= 0;
3978 tdep
->default_mask_address_p
= 0;
3979 set_gdbarch_long_bit (gdbarch
, 32);
3980 set_gdbarch_ptr_bit (gdbarch
, 32);
3981 set_gdbarch_long_long_bit (gdbarch
, 64);
3984 tdep
->mips_abi_string
= "default";
3985 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
3986 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
3987 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3988 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3989 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3990 tdep
->mips_regs_have_home_p
= 1;
3991 tdep
->gdb_target_is_mips64
= 0;
3992 tdep
->default_mask_address_p
= 0;
3993 set_gdbarch_long_bit (gdbarch
, 32);
3994 set_gdbarch_ptr_bit (gdbarch
, 32);
3995 set_gdbarch_long_long_bit (gdbarch
, 64);
3999 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4000 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4003 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4004 flag in object files because to do so would make it impossible to
4005 link with libraries compiled without "-gp32". This is
4006 unnecessarily restrictive.
4008 We could solve this problem by adding "-gp32" multilibs to gcc,
4009 but to set this flag before gcc is built with such multilibs will
4010 break too many systems.''
4012 But even more unhelpfully, the default linker output target for
4013 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4014 for 64-bit programs - you need to change the ABI to change this,
4015 and not all gcc targets support that currently. Therefore using
4016 this flag to detect 32-bit mode would do the wrong thing given
4017 the current gcc - it would make GDB treat these 64-bit programs
4018 as 32-bit programs by default. */
4020 /* enable/disable the MIPS FPU */
4021 if (!mips_fpu_type_auto
)
4022 tdep
->mips_fpu_type
= mips_fpu_type
;
4023 else if (info
.bfd_arch_info
!= NULL
4024 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4025 switch (info
.bfd_arch_info
->mach
)
4027 case bfd_mach_mips3900
:
4028 case bfd_mach_mips4100
:
4029 case bfd_mach_mips4111
:
4030 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4032 case bfd_mach_mips4650
:
4033 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4036 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4040 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4042 /* MIPS version of register names. NOTE: At present the MIPS
4043 register name management is part way between the old -
4044 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4045 Further work on it is required. */
4046 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4047 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4048 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4049 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4050 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4051 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4052 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4054 /* Initialize a frame */
4055 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4057 /* MIPS version of CALL_DUMMY */
4059 set_gdbarch_call_dummy_p (gdbarch
, 1);
4060 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4061 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4062 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4063 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4064 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4065 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4066 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4067 set_gdbarch_call_dummy_length (gdbarch
, 0);
4068 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4069 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4070 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4071 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4072 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4073 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4074 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4076 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4077 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4079 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4080 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4081 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4082 set_gdbarch_ieee_float (gdbarch
, 1);
4084 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4085 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4091 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4093 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4097 int ef_mips_32bitmode
;
4098 /* determine the ISA */
4099 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4116 /* determine the size of a pointer */
4117 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4118 fprintf_unfiltered (file
,
4119 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4121 fprintf_unfiltered (file
,
4122 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4124 fprintf_unfiltered (file
,
4125 "mips_dump_tdep: ef_mips_arch = %d\n",
4127 fprintf_unfiltered (file
,
4128 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4130 tdep
->mips_abi_string
);
4131 fprintf_unfiltered (file
,
4132 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4133 mips_mask_address_p (),
4134 tdep
->default_mask_address_p
);
4136 fprintf_unfiltered (file
,
4137 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4138 FP_REGISTER_DOUBLE
);
4139 fprintf_unfiltered (file
,
4140 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4141 MIPS_DEFAULT_FPU_TYPE
,
4142 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4143 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4144 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4146 fprintf_unfiltered (file
,
4147 "mips_dump_tdep: MIPS_EABI = %d\n",
4149 fprintf_unfiltered (file
,
4150 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4151 MIPS_LAST_FP_ARG_REGNUM
,
4152 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4153 fprintf_unfiltered (file
,
4154 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4156 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4157 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4158 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4160 fprintf_unfiltered (file
,
4161 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4162 MIPS_DEFAULT_SAVED_REGSIZE
);
4163 fprintf_unfiltered (file
,
4164 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4165 FP_REGISTER_DOUBLE
);
4166 fprintf_unfiltered (file
,
4167 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4168 MIPS_REGS_HAVE_HOME_P
);
4169 fprintf_unfiltered (file
,
4170 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4171 MIPS_DEFAULT_STACK_ARGSIZE
);
4172 fprintf_unfiltered (file
,
4173 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4174 MIPS_STACK_ARGSIZE
);
4175 fprintf_unfiltered (file
,
4176 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4178 fprintf_unfiltered (file
,
4179 "mips_dump_tdep: A0_REGNUM = %d\n",
4181 fprintf_unfiltered (file
,
4182 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4183 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4184 fprintf_unfiltered (file
,
4185 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4186 XSTRING (ATTACH_DETACH
));
4187 fprintf_unfiltered (file
,
4188 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4190 fprintf_unfiltered (file
,
4191 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4192 fprintf_unfiltered (file
,
4193 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4195 fprintf_unfiltered (file
,
4196 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4198 fprintf_unfiltered (file
,
4199 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4201 fprintf_unfiltered (file
,
4202 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4203 XSTRING (DO_REGISTERS_INFO
));
4204 fprintf_unfiltered (file
,
4205 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4206 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4207 fprintf_unfiltered (file
,
4208 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4209 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4210 fprintf_unfiltered (file
,
4211 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4212 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4213 fprintf_unfiltered (file
,
4214 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4216 fprintf_unfiltered (file
,
4217 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4219 fprintf_unfiltered (file
,
4220 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4221 FIRST_EMBED_REGNUM
);
4222 fprintf_unfiltered (file
,
4223 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4225 fprintf_unfiltered (file
,
4226 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4227 GDB_TARGET_IS_MIPS64
);
4228 fprintf_unfiltered (file
,
4229 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4230 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4231 fprintf_unfiltered (file
,
4232 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4233 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4234 fprintf_unfiltered (file
,
4235 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4237 fprintf_unfiltered (file
,
4238 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4239 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4240 fprintf_unfiltered (file
,
4241 "mips_dump_tdep: HI_REGNUM = %d\n",
4243 fprintf_unfiltered (file
,
4244 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4245 fprintf_unfiltered (file
,
4246 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4247 fprintf_unfiltered (file
,
4248 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4249 XSTRING (IGNORE_HELPER_CALL (PC
)));
4250 fprintf_unfiltered (file
,
4251 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4252 XSTRING (INIT_FRAME_PC (FROMLEAF
, PREV
)));
4253 fprintf_unfiltered (file
,
4254 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4255 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF
, PREV
)));
4256 fprintf_unfiltered (file
,
4257 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4258 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4259 fprintf_unfiltered (file
,
4260 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4261 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4262 fprintf_unfiltered (file
,
4263 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4264 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4265 fprintf_unfiltered (file
,
4266 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4267 fprintf_unfiltered (file
,
4268 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4270 fprintf_unfiltered (file
,
4271 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4272 fprintf_unfiltered (file
,
4273 "mips_dump_tdep: LO_REGNUM = %d\n",
4275 #ifdef MACHINE_CPROC_FP_OFFSET
4276 fprintf_unfiltered (file
,
4277 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4278 MACHINE_CPROC_FP_OFFSET
);
4280 #ifdef MACHINE_CPROC_PC_OFFSET
4281 fprintf_unfiltered (file
,
4282 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4283 MACHINE_CPROC_PC_OFFSET
);
4285 #ifdef MACHINE_CPROC_SP_OFFSET
4286 fprintf_unfiltered (file
,
4287 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4288 MACHINE_CPROC_SP_OFFSET
);
4290 fprintf_unfiltered (file
,
4291 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4292 fprintf_unfiltered (file
,
4293 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4294 fprintf_unfiltered (file
,
4295 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4297 fprintf_unfiltered (file
,
4298 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4299 fprintf_unfiltered (file
,
4300 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4301 fprintf_unfiltered (file
,
4302 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4303 fprintf_unfiltered (file
,
4304 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4306 fprintf_unfiltered (file
,
4307 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4308 MIPS_LAST_ARG_REGNUM
,
4309 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4310 fprintf_unfiltered (file
,
4311 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4313 fprintf_unfiltered (file
,
4314 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4315 fprintf_unfiltered (file
,
4316 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4317 MIPS_SAVED_REGSIZE
);
4318 fprintf_unfiltered (file
,
4319 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4320 fprintf_unfiltered (file
,
4321 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4322 XSTRING (MSYMBOL_SIZE (MSYM
)));
4323 fprintf_unfiltered (file
,
4324 "mips_dump_tdep: OP_LDFPR = used?\n");
4325 fprintf_unfiltered (file
,
4326 "mips_dump_tdep: OP_LDGPR = used?\n");
4327 fprintf_unfiltered (file
,
4328 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4329 fprintf_unfiltered (file
,
4330 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4331 fprintf_unfiltered (file
,
4332 "mips_dump_tdep: PRID_REGNUM = %d\n",
4334 fprintf_unfiltered (file
,
4335 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4336 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4337 fprintf_unfiltered (file
,
4338 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4339 fprintf_unfiltered (file
,
4340 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4341 fprintf_unfiltered (file
,
4342 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4343 fprintf_unfiltered (file
,
4344 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4345 fprintf_unfiltered (file
,
4346 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4347 fprintf_unfiltered (file
,
4348 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4349 fprintf_unfiltered (file
,
4350 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4351 fprintf_unfiltered (file
,
4352 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4353 fprintf_unfiltered (file
,
4354 "mips_dump_tdep: PROC_PC_REG = function?\n");
4355 fprintf_unfiltered (file
,
4356 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4357 fprintf_unfiltered (file
,
4358 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4359 fprintf_unfiltered (file
,
4360 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4361 fprintf_unfiltered (file
,
4362 "mips_dump_tdep: PS_REGNUM = %d\n",
4364 fprintf_unfiltered (file
,
4365 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4367 fprintf_unfiltered (file
,
4368 "mips_dump_tdep: RA_REGNUM = %d\n",
4370 fprintf_unfiltered (file
,
4371 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4372 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4373 fprintf_unfiltered (file
,
4374 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4375 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4376 fprintf_unfiltered (file
,
4377 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4378 fprintf_unfiltered (file
,
4379 "mips_dump_tdep: ROUND_DOWN = function?\n");
4380 fprintf_unfiltered (file
,
4381 "mips_dump_tdep: ROUND_UP = function?\n");
4383 fprintf_unfiltered (file
,
4384 "mips_dump_tdep: SAVED_BYTES = %d\n",
4388 fprintf_unfiltered (file
,
4389 "mips_dump_tdep: SAVED_FP = %d\n",
4393 fprintf_unfiltered (file
,
4394 "mips_dump_tdep: SAVED_PC = %d\n",
4397 fprintf_unfiltered (file
,
4398 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4399 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4400 fprintf_unfiltered (file
,
4401 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4402 fprintf_unfiltered (file
,
4403 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4405 fprintf_unfiltered (file
,
4406 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4407 SIGFRAME_FPREGSAVE_OFF
);
4408 fprintf_unfiltered (file
,
4409 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4411 fprintf_unfiltered (file
,
4412 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4413 SIGFRAME_REGSAVE_OFF
);
4414 fprintf_unfiltered (file
,
4415 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4417 fprintf_unfiltered (file
,
4418 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4419 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4420 fprintf_unfiltered (file
,
4421 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4422 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4423 fprintf_unfiltered (file
,
4424 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4425 SOFTWARE_SINGLE_STEP_P
);
4426 fprintf_unfiltered (file
,
4427 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4428 SOFTWARE_SINGLE_STEP_P
);
4429 fprintf_unfiltered (file
,
4430 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4431 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4432 #ifdef STACK_END_ADDR
4433 fprintf_unfiltered (file
,
4434 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4437 fprintf_unfiltered (file
,
4438 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4439 XSTRING (STEP_SKIPS_DELAY (PC
)));
4440 fprintf_unfiltered (file
,
4441 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4442 STEP_SKIPS_DELAY_P
);
4443 fprintf_unfiltered (file
,
4444 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4445 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4446 fprintf_unfiltered (file
,
4447 "mips_dump_tdep: T9_REGNUM = %d\n",
4449 fprintf_unfiltered (file
,
4450 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4451 fprintf_unfiltered (file
,
4452 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4453 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4454 fprintf_unfiltered (file
,
4455 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4456 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4457 fprintf_unfiltered (file
,
4458 "mips_dump_tdep: TARGET_MIPS = used?\n");
4459 fprintf_unfiltered (file
,
4460 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4461 XSTRING (TM_PRINT_INSN_MACH
));
4463 fprintf_unfiltered (file
,
4464 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4465 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4468 fprintf_unfiltered (file
,
4469 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4472 #ifdef TRACE_FLAVOR_SIZE
4473 fprintf_unfiltered (file
,
4474 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4478 fprintf_unfiltered (file
,
4479 "mips_dump_tdep: TRACE_SET # %s\n",
4480 XSTRING (TRACE_SET (X
,STATE
)));
4482 fprintf_unfiltered (file
,
4483 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4484 #ifdef UNUSED_REGNUM
4485 fprintf_unfiltered (file
,
4486 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4489 fprintf_unfiltered (file
,
4490 "mips_dump_tdep: V0_REGNUM = %d\n",
4492 fprintf_unfiltered (file
,
4493 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4494 (long) VM_MIN_ADDRESS
);
4496 fprintf_unfiltered (file
,
4497 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4500 fprintf_unfiltered (file
,
4501 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4503 fprintf_unfiltered (file
,
4504 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4509 _initialize_mips_tdep (void)
4511 static struct cmd_list_element
*mipsfpulist
= NULL
;
4512 struct cmd_list_element
*c
;
4514 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4515 if (!tm_print_insn
) /* Someone may have already set it */
4516 tm_print_insn
= gdb_print_insn_mips
;
4518 /* Add root prefix command for all "set mips"/"show mips" commands */
4519 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4520 "Various MIPS specific commands.",
4521 &setmipscmdlist
, "set mips ", 0, &setlist
);
4523 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4524 "Various MIPS specific commands.",
4525 &showmipscmdlist
, "show mips ", 0, &showlist
);
4527 /* Allow the user to override the saved register size. */
4528 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4531 &mips_saved_regsize_string
, "\
4532 Set size of general purpose registers saved on the stack.\n\
4533 This option can be set to one of:\n\
4534 32 - Force GDB to treat saved GP registers as 32-bit\n\
4535 64 - Force GDB to treat saved GP registers as 64-bit\n\
4536 auto - Allow GDB to use the target's default setting or autodetect the\n\
4537 saved GP register size from information contained in the executable.\n\
4542 /* Allow the user to override the argument stack size. */
4543 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4546 &mips_stack_argsize_string
, "\
4547 Set the amount of stack space reserved for each argument.\n\
4548 This option can be set to one of:\n\
4549 32 - Force GDB to allocate 32-bit chunks per argument\n\
4550 64 - Force GDB to allocate 64-bit chunks per argument\n\
4551 auto - Allow GDB to determine the correct setting from the current\n\
4552 target and executable (default)",
4556 /* Let the user turn off floating point and set the fence post for
4557 heuristic_proc_start. */
4559 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4560 "Set use of MIPS floating-point coprocessor.",
4561 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4562 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4563 "Select single-precision MIPS floating-point coprocessor.",
4565 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4566 "Select double-precision MIPS floating-point coprocessor .",
4568 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4569 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4570 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4571 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4572 "Select no MIPS floating-point coprocessor.",
4574 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4575 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4576 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4577 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4578 "Select MIPS floating-point coprocessor automatically.",
4580 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4581 "Show current use of MIPS floating-point coprocessor target.",
4585 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4586 (char *) &tmp_mips_processor_type
,
4587 "Set the type of MIPS processor in use.\n\
4588 Set this to be able to access processor-type-specific registers.\n\
4591 c
->function
.cfunc
= mips_set_processor_type_command
;
4592 c
= add_show_from_set (c
, &showlist
);
4593 c
->function
.cfunc
= mips_show_processor_type_command
;
4595 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4596 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4599 /* We really would like to have both "0" and "unlimited" work, but
4600 command.c doesn't deal with that. So make it a var_zinteger
4601 because the user can always use "999999" or some such for unlimited. */
4602 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4603 (char *) &heuristic_fence_post
,
4605 Set the distance searched for the start of a function.\n\
4606 If you are debugging a stripped executable, GDB needs to search through the\n\
4607 program for the start of a function. This command sets the distance of the\n\
4608 search. The only need to set it is when debugging a stripped executable.",
4610 /* We need to throw away the frame cache when we set this, since it
4611 might change our ability to get backtraces. */
4612 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4613 add_show_from_set (c
, &showlist
);
4615 /* Allow the user to control whether the upper bits of 64-bit
4616 addresses should be zeroed. */
4617 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4618 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4619 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4620 the correct value.\n",
4622 add_cmd ("mask-address", no_class
, show_mask_address
,
4623 "Show current mask-address value", &showmipscmdlist
);
4625 /* Allow the user to control the size of 32 bit registers within the
4626 raw remote packet. */
4627 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4630 (char *)&mips64_transfers_32bit_regs_p
, "\
4631 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4632 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4633 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4634 64 bits for others. Use \"off\" to disable compatibility mode",
4638 /* Debug this files internals. */
4639 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4640 &mips_debug
, "Set mips debugging.\n\
4641 When non-zero, mips specific debugging is enabled.", &setdebuglist
),