1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
60 #include "dwarf2-frame.h"
61 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 /* Some MIPS boards don't support floating point while others only
148 support single-precision floating-point operations. */
152 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
153 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
154 MIPS_FPU_NONE
/* No floating point. */
157 #ifndef MIPS_DEFAULT_FPU_TYPE
158 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
160 static int mips_fpu_type_auto
= 1;
161 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
163 static int mips_debug
= 0;
165 /* Properties (for struct target_desc) describing the g/G packet
167 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
168 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
170 /* MIPS specific per-architecture information */
173 /* from the elf header */
177 enum mips_abi mips_abi
;
178 enum mips_abi found_abi
;
179 enum mips_fpu_type mips_fpu_type
;
180 int mips_last_arg_regnum
;
181 int mips_last_fp_arg_regnum
;
182 int default_mask_address_p
;
183 /* Is the target using 64-bit raw integer registers but only
184 storing a left-aligned 32-bit value in each? */
185 int mips64_transfers_32bit_regs_p
;
186 /* Indexes for various registers. IRIX and embedded have
187 different values. This contains the "public" fields. Don't
188 add any that do not need to be public. */
189 const struct mips_regnum
*regnum
;
190 /* Register names table for the current register set. */
191 const char **mips_processor_reg_names
;
193 /* The size of register data available from the target, if known.
194 This doesn't quite obsolete the manual
195 mips64_transfers_32bit_regs_p, since that is documented to force
196 left alignment even for big endian (very strange). */
197 int register_size_valid_p
;
202 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
208 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
209 They are implemented as a pair of 64bit doubles where the high
210 part holds the result of the operation rounded to double, and
211 the low double holds the difference between the exact result and
212 the rounded result. So "high" + "low" contains the result with
213 added precision. Unfortunately, the floatformat structure used
214 by GDB is not powerful enough to describe this format. As a temporary
215 measure, we define a 128bit floatformat that only uses the high part.
216 We lose a bit of precision but that's probably the best we can do
217 for now with the current infrastructure. */
219 static const struct floatformat floatformat_n32n64_long_double_big
=
221 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
222 floatformat_intbit_no
,
223 "floatformat_n32n64_long_double_big",
224 n32n64_floatformat_always_valid
227 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
229 &floatformat_n32n64_long_double_big
,
230 &floatformat_n32n64_long_double_big
233 const struct mips_regnum
*
234 mips_regnum (struct gdbarch
*gdbarch
)
236 return gdbarch_tdep (gdbarch
)->regnum
;
240 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
242 return mips_regnum (gdbarch
)->fp0
+ 12;
245 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
246 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
248 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
250 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
252 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
254 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
255 functions to test, set, or clear bit 0 of addresses. */
258 is_mips16_addr (CORE_ADDR addr
)
264 unmake_mips16_addr (CORE_ADDR addr
)
266 return ((addr
) & ~(CORE_ADDR
) 1);
269 /* Return the contents of register REGNUM as a signed integer. */
272 read_signed_register (int regnum
)
275 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
280 read_signed_register_pid (int regnum
, ptid_t ptid
)
285 if (ptid_equal (ptid
, inferior_ptid
))
286 return read_signed_register (regnum
);
288 save_ptid
= inferior_ptid
;
290 inferior_ptid
= ptid
;
292 retval
= read_signed_register (regnum
);
294 inferior_ptid
= save_ptid
;
299 /* Return the MIPS ABI associated with GDBARCH. */
301 mips_abi (struct gdbarch
*gdbarch
)
303 return gdbarch_tdep (gdbarch
)->mips_abi
;
307 mips_isa_regsize (struct gdbarch
*gdbarch
)
309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
311 /* If we know how big the registers are, use that size. */
312 if (tdep
->register_size_valid_p
)
313 return tdep
->register_size
;
315 /* Fall back to the previous behavior. */
316 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
317 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
320 /* Return the currently configured (or set) saved register size. */
323 mips_abi_regsize (struct gdbarch
*gdbarch
)
325 switch (mips_abi (gdbarch
))
327 case MIPS_ABI_EABI32
:
333 case MIPS_ABI_EABI64
:
335 case MIPS_ABI_UNKNOWN
:
338 internal_error (__FILE__
, __LINE__
, _("bad switch"));
342 /* Functions for setting and testing a bit in a minimal symbol that
343 marks it as 16-bit function. The MSB of the minimal symbol's
344 "info" field is used for this purpose.
346 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
347 i.e. refers to a 16-bit function, and sets a "special" bit in a
348 minimal symbol to mark it as a 16-bit function
350 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
353 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
355 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
357 MSYMBOL_INFO (msym
) = (char *)
358 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
359 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
364 msymbol_is_special (struct minimal_symbol
*msym
)
366 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
369 /* XFER a value from the big/little/left end of the register.
370 Depending on the size of the value it might occupy the entire
371 register or just part of it. Make an allowance for this, aligning
372 things accordingly. */
375 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
376 enum bfd_endian endian
, gdb_byte
*in
,
377 const gdb_byte
*out
, int buf_offset
)
380 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
381 /* Need to transfer the left or right part of the register, based on
382 the targets byte order. */
386 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
388 case BFD_ENDIAN_LITTLE
:
391 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
395 internal_error (__FILE__
, __LINE__
, _("bad switch"));
398 fprintf_unfiltered (gdb_stderr
,
399 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
400 reg_num
, reg_offset
, buf_offset
, length
);
401 if (mips_debug
&& out
!= NULL
)
404 fprintf_unfiltered (gdb_stdlog
, "out ");
405 for (i
= 0; i
< length
; i
++)
406 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
409 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
412 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
414 if (mips_debug
&& in
!= NULL
)
417 fprintf_unfiltered (gdb_stdlog
, "in ");
418 for (i
= 0; i
< length
; i
++)
419 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
422 fprintf_unfiltered (gdb_stdlog
, "\n");
425 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
426 compatiblity mode. A return value of 1 means that we have
427 physical 64-bit registers, but should treat them as 32-bit registers. */
430 mips2_fp_compat (struct frame_info
*frame
)
432 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
434 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
439 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
440 in all the places we deal with FP registers. PR gdb/413. */
441 /* Otherwise check the FR bit in the status register - it controls
442 the FP compatiblity mode. If it is clear we are in compatibility
444 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
451 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
453 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
455 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
457 static struct type
*mips_float_register_type (void);
458 static struct type
*mips_double_register_type (void);
460 /* The list of available "set mips " and "show mips " commands */
462 static struct cmd_list_element
*setmipscmdlist
= NULL
;
463 static struct cmd_list_element
*showmipscmdlist
= NULL
;
465 /* Integer registers 0 thru 31 are handled explicitly by
466 mips_register_name(). Processor specific registers 32 and above
467 are listed in the following tables. */
470 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
474 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
475 "sr", "lo", "hi", "bad", "cause", "pc",
476 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
477 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
478 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
479 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
480 "fsr", "fir", "" /*"fp" */ , "",
481 "", "", "", "", "", "", "", "",
482 "", "", "", "", "", "", "", "",
485 /* Names of IDT R3041 registers. */
487 static const char *mips_r3041_reg_names
[] = {
488 "sr", "lo", "hi", "bad", "cause", "pc",
489 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
490 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
491 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
492 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
493 "fsr", "fir", "", /*"fp" */ "",
494 "", "", "bus", "ccfg", "", "", "", "",
495 "", "", "port", "cmp", "", "", "epc", "prid",
498 /* Names of tx39 registers. */
500 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
501 "sr", "lo", "hi", "bad", "cause", "pc",
502 "", "", "", "", "", "", "", "",
503 "", "", "", "", "", "", "", "",
504 "", "", "", "", "", "", "", "",
505 "", "", "", "", "", "", "", "",
507 "", "", "", "", "", "", "", "",
508 "", "", "config", "cache", "debug", "depc", "epc", ""
511 /* Names of IRIX registers. */
512 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
513 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
514 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
515 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
516 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
517 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
521 /* Return the name of the register corresponding to REGNO. */
523 mips_register_name (int regno
)
525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
526 /* GPR names for all ABIs other than n32/n64. */
527 static char *mips_gpr_names
[] = {
528 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
529 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
530 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
531 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
534 /* GPR names for n32 and n64 ABIs. */
535 static char *mips_n32_n64_gpr_names
[] = {
536 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
537 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
538 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
539 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
542 enum mips_abi abi
= mips_abi (current_gdbarch
);
544 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
545 but then don't make the raw register names visible. */
546 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
547 if (regno
< gdbarch_num_regs (current_gdbarch
))
550 /* The MIPS integer registers are always mapped from 0 to 31. The
551 names of the registers (which reflects the conventions regarding
552 register use) vary depending on the ABI. */
553 if (0 <= rawnum
&& rawnum
< 32)
555 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
556 return mips_n32_n64_gpr_names
[rawnum
];
558 return mips_gpr_names
[rawnum
];
560 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch
)))
561 return tdesc_register_name (rawnum
);
562 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
564 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
565 return tdep
->mips_processor_reg_names
[rawnum
- 32];
568 internal_error (__FILE__
, __LINE__
,
569 _("mips_register_name: bad register number %d"), rawnum
);
572 /* Return the groups that a MIPS register can be categorised into. */
575 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
576 struct reggroup
*reggroup
)
581 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
582 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
583 if (reggroup
== all_reggroup
)
585 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
586 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
587 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
588 (gdbarch), as not all architectures are multi-arch. */
589 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
590 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
591 || gdbarch_register_name (current_gdbarch
, regnum
)[0] == '\0')
593 if (reggroup
== float_reggroup
)
594 return float_p
&& pseudo
;
595 if (reggroup
== vector_reggroup
)
596 return vector_p
&& pseudo
;
597 if (reggroup
== general_reggroup
)
598 return (!vector_p
&& !float_p
) && pseudo
;
599 /* Save the pseudo registers. Need to make certain that any code
600 extracting register values from a saved register cache also uses
602 if (reggroup
== save_reggroup
)
603 return raw_p
&& pseudo
;
604 /* Restore the same pseudo register. */
605 if (reggroup
== restore_reggroup
)
606 return raw_p
&& pseudo
;
610 /* Return the groups that a MIPS register can be categorised into.
611 This version is only used if we have a target description which
612 describes real registers (and their groups). */
615 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
616 struct reggroup
*reggroup
)
618 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
619 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
622 /* Only save, restore, and display the pseudo registers. Need to
623 make certain that any code extracting register values from a
624 saved register cache also uses pseudo registers.
626 Note: saving and restoring the pseudo registers is slightly
627 strange; if we have 64 bits, we should save and restore all
628 64 bits. But this is hard and has little benefit. */
632 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
636 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
639 /* Map the symbol table registers which live in the range [1 *
640 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
641 registers. Take care of alignment and size problems. */
644 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
645 int cookednum
, gdb_byte
*buf
)
647 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
648 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
649 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
650 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
651 regcache_raw_read (regcache
, rawnum
, buf
);
652 else if (register_size (gdbarch
, rawnum
) >
653 register_size (gdbarch
, cookednum
))
655 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
656 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
657 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
659 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
662 internal_error (__FILE__
, __LINE__
, _("bad register size"));
666 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
667 struct regcache
*regcache
, int cookednum
,
670 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
671 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
672 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
673 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
674 regcache_raw_write (regcache
, rawnum
, buf
);
675 else if (register_size (gdbarch
, rawnum
) >
676 register_size (gdbarch
, cookednum
))
678 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
679 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
680 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
682 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
685 internal_error (__FILE__
, __LINE__
, _("bad register size"));
688 /* Table to translate MIPS16 register field to actual register number. */
689 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
691 /* Heuristic_proc_start may hunt through the text section for a long
692 time across a 2400 baud serial line. Allows the user to limit this
695 static unsigned int heuristic_fence_post
= 0;
697 /* Number of bytes of storage in the actual machine representation for
698 register N. NOTE: This defines the pseudo register type so need to
699 rebuild the architecture vector. */
701 static int mips64_transfers_32bit_regs_p
= 0;
704 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
705 struct cmd_list_element
*c
)
707 struct gdbarch_info info
;
708 gdbarch_info_init (&info
);
709 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
710 instead of relying on globals. Doing that would let generic code
711 handle the search for this specific architecture. */
712 if (!gdbarch_update_p (info
))
714 mips64_transfers_32bit_regs_p
= 0;
715 error (_("32-bit compatibility mode not supported"));
719 /* Convert to/from a register and the corresponding memory value. */
722 mips_convert_register_p (int regnum
, struct type
*type
)
724 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
725 && register_size (current_gdbarch
, regnum
) == 4
726 && (regnum
% gdbarch_num_regs (current_gdbarch
))
727 >= mips_regnum (current_gdbarch
)->fp0
728 && (regnum
% gdbarch_num_regs (current_gdbarch
))
729 < mips_regnum (current_gdbarch
)->fp0
+ 32
730 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
734 mips_register_to_value (struct frame_info
*frame
, int regnum
,
735 struct type
*type
, gdb_byte
*to
)
737 get_frame_register (frame
, regnum
+ 0, to
+ 4);
738 get_frame_register (frame
, regnum
+ 1, to
+ 0);
742 mips_value_to_register (struct frame_info
*frame
, int regnum
,
743 struct type
*type
, const gdb_byte
*from
)
745 put_frame_register (frame
, regnum
+ 0, from
+ 4);
746 put_frame_register (frame
, regnum
+ 1, from
+ 0);
749 /* Return the GDB type object for the "standard" data type of data in
753 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
755 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
756 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
757 >= mips_regnum (current_gdbarch
)->fp0
758 && (regnum
% gdbarch_num_regs (current_gdbarch
))
759 < mips_regnum (current_gdbarch
)->fp0
+ 32)
761 /* The floating-point registers raw, or cooked, always match
762 mips_isa_regsize(), and also map 1:1, byte for byte. */
763 if (mips_isa_regsize (gdbarch
) == 4)
764 return builtin_type_ieee_single
;
766 return builtin_type_ieee_double
;
768 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
770 /* The raw or ISA registers. These are all sized according to
772 if (mips_isa_regsize (gdbarch
) == 4)
773 return builtin_type_int32
;
775 return builtin_type_int64
;
779 /* The cooked or ABI registers. These are sized according to
780 the ABI (with a few complications). */
781 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
782 + mips_regnum (current_gdbarch
)->fp_control_status
)
783 && regnum
<= gdbarch_num_regs (current_gdbarch
)
784 + MIPS_LAST_EMBED_REGNUM
)
785 /* The pseudo/cooked view of the embedded registers is always
786 32-bit. The raw view is handled below. */
787 return builtin_type_int32
;
788 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
789 /* The target, while possibly using a 64-bit register buffer,
790 is only transfering 32-bits of each integer register.
791 Reflect this in the cooked/pseudo (ABI) register value. */
792 return builtin_type_int32
;
793 else if (mips_abi_regsize (gdbarch
) == 4)
794 /* The ABI is restricted to 32-bit registers (the ISA could be
796 return builtin_type_int32
;
799 return builtin_type_int64
;
803 /* Return the GDB type for the pseudo register REGNUM, which is the
804 ABI-level view. This function is only called if there is a target
805 description which includes registers, so we know precisely the
806 types of hardware registers. */
809 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
811 const int num_regs
= gdbarch_num_regs (gdbarch
);
812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
813 int rawnum
= regnum
% num_regs
;
814 struct type
*rawtype
;
816 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
818 /* Absent registers are still absent. */
819 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
820 if (TYPE_LENGTH (rawtype
) == 0)
823 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
824 /* Present the floating point registers however the hardware did;
825 do not try to convert between FPU layouts. */
828 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
830 /* The pseudo/cooked view of embedded registers is always
831 32-bit, even if the target transfers 64-bit values for them.
832 New targets relying on XML descriptions should only transfer
833 the necessary 32 bits, but older versions of GDB expected 64,
834 so allow the target to provide 64 bits without interfering
835 with the displayed type. */
836 return builtin_type_int32
;
839 /* Use pointer types for registers if we can. For n32 we can not,
840 since we do not have a 64-bit pointer type. */
841 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
843 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
844 return builtin_type_void_data_ptr
;
845 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
846 return builtin_type_void_func_ptr
;
849 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
850 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
851 return builtin_type_int32
;
853 /* For all other registers, pass through the hardware type. */
857 /* Should the upper word of 64-bit addresses be zeroed? */
858 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
861 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
863 switch (mask_address_var
)
865 case AUTO_BOOLEAN_TRUE
:
867 case AUTO_BOOLEAN_FALSE
:
870 case AUTO_BOOLEAN_AUTO
:
871 return tdep
->default_mask_address_p
;
873 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
879 show_mask_address (struct ui_file
*file
, int from_tty
,
880 struct cmd_list_element
*c
, const char *value
)
882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
884 deprecated_show_value_hack (file
, from_tty
, c
, value
);
885 switch (mask_address_var
)
887 case AUTO_BOOLEAN_TRUE
:
888 printf_filtered ("The 32 bit mips address mask is enabled\n");
890 case AUTO_BOOLEAN_FALSE
:
891 printf_filtered ("The 32 bit mips address mask is disabled\n");
893 case AUTO_BOOLEAN_AUTO
:
895 ("The 32 bit address mask is set automatically. Currently %s\n",
896 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
899 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
904 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
907 mips_pc_is_mips16 (CORE_ADDR memaddr
)
909 struct minimal_symbol
*sym
;
911 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
912 if (is_mips16_addr (memaddr
))
915 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
916 the high bit of the info field. Use this to decide if the function is
917 MIPS16 or normal MIPS. */
918 sym
= lookup_minimal_symbol_by_pc (memaddr
);
920 return msymbol_is_special (sym
);
925 /* MIPS believes that the PC has a sign extended value. Perhaps the
926 all registers should be sign extended for simplicity? */
929 mips_read_pc (ptid_t ptid
)
931 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
935 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
937 return frame_unwind_register_signed (next_frame
,
938 gdbarch_num_regs (current_gdbarch
)
939 + mips_regnum (gdbarch
)->pc
);
943 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
945 return frame_unwind_register_signed (next_frame
,
946 gdbarch_num_regs (current_gdbarch
)
950 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
951 dummy frame. The frame ID's base needs to match the TOS value
952 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
955 static struct frame_id
956 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
958 return frame_id_build
959 (frame_unwind_register_signed (next_frame
,
960 gdbarch_num_regs (current_gdbarch
)
962 frame_pc_unwind (next_frame
));
966 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
968 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
971 /* Fetch and return instruction from the specified location. If the PC
972 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
975 mips_fetch_instruction (CORE_ADDR addr
)
977 gdb_byte buf
[MIPS_INSN32_SIZE
];
981 if (mips_pc_is_mips16 (addr
))
983 instlen
= MIPS_INSN16_SIZE
;
984 addr
= unmake_mips16_addr (addr
);
987 instlen
= MIPS_INSN32_SIZE
;
988 status
= read_memory_nobpt (addr
, buf
, instlen
);
990 memory_error (status
, addr
);
991 return extract_unsigned_integer (buf
, instlen
);
994 /* These the fields of 32 bit mips instructions */
995 #define mips32_op(x) (x >> 26)
996 #define itype_op(x) (x >> 26)
997 #define itype_rs(x) ((x >> 21) & 0x1f)
998 #define itype_rt(x) ((x >> 16) & 0x1f)
999 #define itype_immediate(x) (x & 0xffff)
1001 #define jtype_op(x) (x >> 26)
1002 #define jtype_target(x) (x & 0x03ffffff)
1004 #define rtype_op(x) (x >> 26)
1005 #define rtype_rs(x) ((x >> 21) & 0x1f)
1006 #define rtype_rt(x) ((x >> 16) & 0x1f)
1007 #define rtype_rd(x) ((x >> 11) & 0x1f)
1008 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1009 #define rtype_funct(x) (x & 0x3f)
1012 mips32_relative_offset (ULONGEST inst
)
1014 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1017 /* Determine where to set a single step breakpoint while considering
1018 branch prediction. */
1020 mips32_next_pc (CORE_ADDR pc
)
1024 inst
= mips_fetch_instruction (pc
);
1025 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1027 if (itype_op (inst
) >> 2 == 5)
1028 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1030 op
= (itype_op (inst
) & 0x03);
1040 goto greater_branch
;
1045 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1046 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1048 int tf
= itype_rt (inst
) & 0x01;
1049 int cnum
= itype_rt (inst
) >> 2;
1051 read_signed_register (mips_regnum (current_gdbarch
)->
1053 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1055 if (((cond
>> cnum
) & 0x01) == tf
)
1056 pc
+= mips32_relative_offset (inst
) + 4;
1061 pc
+= 4; /* Not a branch, next instruction is easy */
1064 { /* This gets way messy */
1066 /* Further subdivide into SPECIAL, REGIMM and other */
1067 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1069 case 0: /* SPECIAL */
1070 op
= rtype_funct (inst
);
1075 /* Set PC to that address */
1076 pc
= read_signed_register (rtype_rs (inst
));
1082 break; /* end SPECIAL */
1083 case 1: /* REGIMM */
1085 op
= itype_rt (inst
); /* branch condition */
1090 case 16: /* BLTZAL */
1091 case 18: /* BLTZALL */
1093 if (read_signed_register (itype_rs (inst
)) < 0)
1094 pc
+= mips32_relative_offset (inst
) + 4;
1096 pc
+= 8; /* after the delay slot */
1100 case 17: /* BGEZAL */
1101 case 19: /* BGEZALL */
1102 if (read_signed_register (itype_rs (inst
)) >= 0)
1103 pc
+= mips32_relative_offset (inst
) + 4;
1105 pc
+= 8; /* after the delay slot */
1107 /* All of the other instructions in the REGIMM category */
1112 break; /* end REGIMM */
1117 reg
= jtype_target (inst
) << 2;
1118 /* Upper four bits get never changed... */
1119 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1122 /* FIXME case JALX : */
1125 reg
= jtype_target (inst
) << 2;
1126 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1127 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1129 break; /* The new PC will be alternate mode */
1130 case 4: /* BEQ, BEQL */
1132 if (read_signed_register (itype_rs (inst
)) ==
1133 read_signed_register (itype_rt (inst
)))
1134 pc
+= mips32_relative_offset (inst
) + 4;
1138 case 5: /* BNE, BNEL */
1140 if (read_signed_register (itype_rs (inst
)) !=
1141 read_signed_register (itype_rt (inst
)))
1142 pc
+= mips32_relative_offset (inst
) + 4;
1146 case 6: /* BLEZ, BLEZL */
1147 if (read_signed_register (itype_rs (inst
)) <= 0)
1148 pc
+= mips32_relative_offset (inst
) + 4;
1154 greater_branch
: /* BGTZ, BGTZL */
1155 if (read_signed_register (itype_rs (inst
)) > 0)
1156 pc
+= mips32_relative_offset (inst
) + 4;
1163 } /* mips32_next_pc */
1165 /* Decoding the next place to set a breakpoint is irregular for the
1166 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1167 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1168 We dont want to set a single step instruction on the extend instruction
1172 /* Lots of mips16 instruction formats */
1173 /* Predicting jumps requires itype,ritype,i8type
1174 and their extensions extItype,extritype,extI8type
1176 enum mips16_inst_fmts
1178 itype
, /* 0 immediate 5,10 */
1179 ritype
, /* 1 5,3,8 */
1180 rrtype
, /* 2 5,3,3,5 */
1181 rritype
, /* 3 5,3,3,5 */
1182 rrrtype
, /* 4 5,3,3,3,2 */
1183 rriatype
, /* 5 5,3,3,1,4 */
1184 shifttype
, /* 6 5,3,3,3,2 */
1185 i8type
, /* 7 5,3,8 */
1186 i8movtype
, /* 8 5,3,3,5 */
1187 i8mov32rtype
, /* 9 5,3,5,3 */
1188 i64type
, /* 10 5,3,8 */
1189 ri64type
, /* 11 5,3,3,5 */
1190 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1191 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1192 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1193 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1194 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1195 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1196 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1197 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1198 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1199 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1201 /* I am heaping all the fields of the formats into one structure and
1202 then, only the fields which are involved in instruction extension */
1206 unsigned int regx
; /* Function in i8 type */
1211 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1212 for the bits which make up the immediatate extension. */
1215 extended_offset (unsigned int extension
)
1218 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1220 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1222 value
|= extension
& 0x01f; /* extract 4:0 */
1226 /* Only call this function if you know that this is an extendable
1227 instruction, It wont malfunction, but why make excess remote memory references?
1228 If the immediate operands get sign extended or somthing, do it after
1229 the extension is performed.
1231 /* FIXME: Every one of these cases needs to worry about sign extension
1232 when the offset is to be used in relative addressing */
1236 fetch_mips_16 (CORE_ADDR pc
)
1239 pc
&= 0xfffffffe; /* clear the low order bit */
1240 target_read_memory (pc
, buf
, 2);
1241 return extract_unsigned_integer (buf
, 2);
1245 unpack_mips16 (CORE_ADDR pc
,
1246 unsigned int extension
,
1248 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1253 switch (insn_format
)
1260 value
= extended_offset (extension
);
1261 value
= value
<< 11; /* rom for the original value */
1262 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1266 value
= inst
& 0x7ff;
1267 /* FIXME : Consider sign extension */
1276 { /* A register identifier and an offset */
1277 /* Most of the fields are the same as I type but the
1278 immediate value is of a different length */
1282 value
= extended_offset (extension
);
1283 value
= value
<< 8; /* from the original instruction */
1284 value
|= inst
& 0xff; /* eleven bits from instruction */
1285 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1286 if (value
& 0x4000) /* test the sign bit , bit 26 */
1288 value
&= ~0x3fff; /* remove the sign bit */
1294 value
= inst
& 0xff; /* 8 bits */
1295 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1296 /* FIXME: Do sign extension , this format needs it */
1297 if (value
& 0x80) /* THIS CONFUSES ME */
1299 value
&= 0xef; /* remove the sign bit */
1309 unsigned long value
;
1310 unsigned int nexthalf
;
1311 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1312 value
= value
<< 16;
1313 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1321 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1323 upk
->offset
= offset
;
1330 add_offset_16 (CORE_ADDR pc
, int offset
)
1332 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1336 extended_mips16_next_pc (CORE_ADDR pc
,
1337 unsigned int extension
, unsigned int insn
)
1339 int op
= (insn
>> 11);
1342 case 2: /* Branch */
1345 struct upk_mips16 upk
;
1346 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1347 offset
= upk
.offset
;
1353 pc
+= (offset
<< 1) + 2;
1356 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1358 struct upk_mips16 upk
;
1359 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1360 pc
= add_offset_16 (pc
, upk
.offset
);
1361 if ((insn
>> 10) & 0x01) /* Exchange mode */
1362 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1369 struct upk_mips16 upk
;
1371 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1372 reg
= read_signed_register (upk
.regx
);
1374 pc
+= (upk
.offset
<< 1) + 2;
1381 struct upk_mips16 upk
;
1383 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1384 reg
= read_signed_register (upk
.regx
);
1386 pc
+= (upk
.offset
<< 1) + 2;
1391 case 12: /* I8 Formats btez btnez */
1393 struct upk_mips16 upk
;
1395 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1396 /* upk.regx contains the opcode */
1397 reg
= read_signed_register (24); /* Test register is 24 */
1398 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1399 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1400 /* pc = add_offset_16(pc,upk.offset) ; */
1401 pc
+= (upk
.offset
<< 1) + 2;
1406 case 29: /* RR Formats JR, JALR, JALR-RA */
1408 struct upk_mips16 upk
;
1409 /* upk.fmt = rrtype; */
1414 upk
.regx
= (insn
>> 8) & 0x07;
1415 upk
.regy
= (insn
>> 5) & 0x07;
1423 break; /* Function return instruction */
1429 break; /* BOGUS Guess */
1431 pc
= read_signed_register (reg
);
1438 /* This is an instruction extension. Fetch the real instruction
1439 (which follows the extension) and decode things based on
1443 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1456 mips16_next_pc (CORE_ADDR pc
)
1458 unsigned int insn
= fetch_mips_16 (pc
);
1459 return extended_mips16_next_pc (pc
, 0, insn
);
1462 /* The mips_next_pc function supports single_step when the remote
1463 target monitor or stub is not developed enough to do a single_step.
1464 It works by decoding the current instruction and predicting where a
1465 branch will go. This isnt hard because all the data is available.
1466 The MIPS32 and MIPS16 variants are quite different */
1468 mips_next_pc (CORE_ADDR pc
)
1471 return mips16_next_pc (pc
);
1473 return mips32_next_pc (pc
);
1476 struct mips_frame_cache
1479 struct trad_frame_saved_reg
*saved_regs
;
1482 /* Set a register's saved stack address in temp_saved_regs. If an
1483 address has already been set for this register, do nothing; this
1484 way we will only recognize the first save of a given register in a
1487 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1488 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1489 Strictly speaking, only the second range is used as it is only second
1490 range (the ABI instead of ISA registers) that comes into play when finding
1491 saved registers in a frame. */
1494 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1497 if (this_cache
!= NULL
1498 && this_cache
->saved_regs
[regnum
].addr
== -1)
1500 this_cache
->saved_regs
[regnum
1501 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1503 this_cache
->saved_regs
[regnum
1504 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1510 /* Fetch the immediate value from a MIPS16 instruction.
1511 If the previous instruction was an EXTEND, use it to extend
1512 the upper bits of the immediate value. This is a helper function
1513 for mips16_scan_prologue. */
1516 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1517 unsigned short inst
, /* current instruction */
1518 int nbits
, /* number of bits in imm field */
1519 int scale
, /* scale factor to be applied to imm */
1520 int is_signed
) /* is the imm field signed? */
1524 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1526 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1527 if (offset
& 0x8000) /* check for negative extend */
1528 offset
= 0 - (0x10000 - (offset
& 0xffff));
1529 return offset
| (inst
& 0x1f);
1533 int max_imm
= 1 << nbits
;
1534 int mask
= max_imm
- 1;
1535 int sign_bit
= max_imm
>> 1;
1537 offset
= inst
& mask
;
1538 if (is_signed
&& (offset
& sign_bit
))
1539 offset
= 0 - (max_imm
- offset
);
1540 return offset
* scale
;
1545 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1546 the associated FRAME_CACHE if not null.
1547 Return the address of the first instruction past the prologue. */
1550 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1551 struct frame_info
*next_frame
,
1552 struct mips_frame_cache
*this_cache
)
1555 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1557 long frame_offset
= 0; /* Size of stack frame. */
1558 long frame_adjust
= 0; /* Offset of FP from SP. */
1559 int frame_reg
= MIPS_SP_REGNUM
;
1560 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1561 unsigned inst
= 0; /* current instruction */
1562 unsigned entry_inst
= 0; /* the entry instruction */
1565 int extend_bytes
= 0;
1566 int prev_extend_bytes
;
1567 CORE_ADDR end_prologue_addr
= 0;
1569 /* Can be called when there's no process, and hence when there's no
1571 if (next_frame
!= NULL
)
1572 sp
= frame_unwind_register_signed (next_frame
,
1573 gdbarch_num_regs (current_gdbarch
)
1578 if (limit_pc
> start_pc
+ 200)
1579 limit_pc
= start_pc
+ 200;
1581 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1583 /* Save the previous instruction. If it's an EXTEND, we'll extract
1584 the immediate offset extension from it in mips16_get_imm. */
1587 /* Fetch and decode the instruction. */
1588 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1590 /* Normally we ignore extend instructions. However, if it is
1591 not followed by a valid prologue instruction, then this
1592 instruction is not part of the prologue either. We must
1593 remember in this case to adjust the end_prologue_addr back
1595 if ((inst
& 0xf800) == 0xf000) /* extend */
1597 extend_bytes
= MIPS_INSN16_SIZE
;
1601 prev_extend_bytes
= extend_bytes
;
1604 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1605 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1607 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1608 if (offset
< 0) /* negative stack adjustment? */
1609 frame_offset
-= offset
;
1611 /* Exit loop if a positive stack adjustment is found, which
1612 usually means that the stack cleanup code in the function
1613 epilogue is reached. */
1616 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1618 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1619 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1620 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1622 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1624 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1625 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1626 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1628 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1630 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1631 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1633 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1635 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1636 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1638 else if (inst
== 0x673d) /* move $s1, $sp */
1643 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1645 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1646 frame_addr
= sp
+ offset
;
1648 frame_adjust
= offset
;
1650 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1652 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1653 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1654 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1656 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1658 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1659 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1660 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1662 else if ((inst
& 0xf81f) == 0xe809
1663 && (inst
& 0x700) != 0x700) /* entry */
1664 entry_inst
= inst
; /* save for later processing */
1665 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1666 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1667 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1669 /* This instruction is part of the prologue, but we don't
1670 need to do anything special to handle it. */
1674 /* This instruction is not an instruction typically found
1675 in a prologue, so we must have reached the end of the
1677 if (end_prologue_addr
== 0)
1678 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1682 /* The entry instruction is typically the first instruction in a function,
1683 and it stores registers at offsets relative to the value of the old SP
1684 (before the prologue). But the value of the sp parameter to this
1685 function is the new SP (after the prologue has been executed). So we
1686 can't calculate those offsets until we've seen the entire prologue,
1687 and can calculate what the old SP must have been. */
1688 if (entry_inst
!= 0)
1690 int areg_count
= (entry_inst
>> 8) & 7;
1691 int sreg_count
= (entry_inst
>> 6) & 3;
1693 /* The entry instruction always subtracts 32 from the SP. */
1696 /* Now we can calculate what the SP must have been at the
1697 start of the function prologue. */
1700 /* Check if a0-a3 were saved in the caller's argument save area. */
1701 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1703 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1704 offset
+= mips_abi_regsize (current_gdbarch
);
1707 /* Check if the ra register was pushed on the stack. */
1709 if (entry_inst
& 0x20)
1711 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1712 offset
-= mips_abi_regsize (current_gdbarch
);
1715 /* Check if the s0 and s1 registers were pushed on the stack. */
1716 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1718 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1719 offset
-= mips_abi_regsize (current_gdbarch
);
1723 if (this_cache
!= NULL
)
1726 (frame_unwind_register_signed (next_frame
,
1727 gdbarch_num_regs (current_gdbarch
)
1729 + frame_offset
- frame_adjust
);
1730 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1731 be able to get rid of the assignment below, evetually. But it's
1732 still needed for now. */
1733 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1734 + mips_regnum (current_gdbarch
)->pc
]
1735 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1739 /* If we didn't reach the end of the prologue when scanning the function
1740 instructions, then set end_prologue_addr to the address of the
1741 instruction immediately after the last one we scanned. */
1742 if (end_prologue_addr
== 0)
1743 end_prologue_addr
= cur_pc
;
1745 return end_prologue_addr
;
1748 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1749 Procedures that use the 32-bit instruction set are handled by the
1750 mips_insn32 unwinder. */
1752 static struct mips_frame_cache
*
1753 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1755 struct mips_frame_cache
*cache
;
1757 if ((*this_cache
) != NULL
)
1758 return (*this_cache
);
1759 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1760 (*this_cache
) = cache
;
1761 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1763 /* Analyze the function prologue. */
1765 const CORE_ADDR pc
=
1766 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1767 CORE_ADDR start_addr
;
1769 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1770 if (start_addr
== 0)
1771 start_addr
= heuristic_proc_start (pc
);
1772 /* We can't analyze the prologue if we couldn't find the begining
1774 if (start_addr
== 0)
1777 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1780 /* SP_REGNUM, contains the value and not the address. */
1781 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1782 + MIPS_SP_REGNUM
, cache
->base
);
1784 return (*this_cache
);
1788 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1789 struct frame_id
*this_id
)
1791 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1793 (*this_id
) = frame_id_build (info
->base
,
1794 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1798 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1800 int regnum
, int *optimizedp
,
1801 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1802 int *realnump
, gdb_byte
*valuep
)
1804 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1806 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1807 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1810 static const struct frame_unwind mips_insn16_frame_unwind
=
1813 mips_insn16_frame_this_id
,
1814 mips_insn16_frame_prev_register
1817 static const struct frame_unwind
*
1818 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1820 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1821 if (mips_pc_is_mips16 (pc
))
1822 return &mips_insn16_frame_unwind
;
1827 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1830 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1835 static const struct frame_base mips_insn16_frame_base
=
1837 &mips_insn16_frame_unwind
,
1838 mips_insn16_frame_base_address
,
1839 mips_insn16_frame_base_address
,
1840 mips_insn16_frame_base_address
1843 static const struct frame_base
*
1844 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1846 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1847 return &mips_insn16_frame_base
;
1852 /* Mark all the registers as unset in the saved_regs array
1853 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1856 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1858 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1862 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1865 for (i
= 0; i
< num_regs
; i
++)
1867 this_cache
->saved_regs
[i
].addr
= -1;
1872 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1873 the associated FRAME_CACHE if not null.
1874 Return the address of the first instruction past the prologue. */
1877 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1878 struct frame_info
*next_frame
,
1879 struct mips_frame_cache
*this_cache
)
1882 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1885 int frame_reg
= MIPS_SP_REGNUM
;
1887 CORE_ADDR end_prologue_addr
= 0;
1888 int seen_sp_adjust
= 0;
1889 int load_immediate_bytes
= 0;
1891 /* Can be called when there's no process, and hence when there's no
1893 if (next_frame
!= NULL
)
1894 sp
= frame_unwind_register_signed (next_frame
,
1895 gdbarch_num_regs (current_gdbarch
)
1900 if (limit_pc
> start_pc
+ 200)
1901 limit_pc
= start_pc
+ 200;
1906 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1908 unsigned long inst
, high_word
, low_word
;
1911 /* Fetch the instruction. */
1912 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1914 /* Save some code by pre-extracting some useful fields. */
1915 high_word
= (inst
>> 16) & 0xffff;
1916 low_word
= inst
& 0xffff;
1917 reg
= high_word
& 0x1f;
1919 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1920 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1921 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1923 if (low_word
& 0x8000) /* negative stack adjustment? */
1924 frame_offset
+= 0x10000 - low_word
;
1926 /* Exit loop if a positive stack adjustment is found, which
1927 usually means that the stack cleanup code in the function
1928 epilogue is reached. */
1932 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1934 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1936 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1938 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1939 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1941 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1943 /* Old gcc frame, r30 is virtual frame pointer. */
1944 if ((long) low_word
!= frame_offset
)
1945 frame_addr
= sp
+ low_word
;
1946 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1948 unsigned alloca_adjust
;
1951 frame_addr
= frame_unwind_register_signed
1953 gdbarch_num_regs (current_gdbarch
) + 30);
1955 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1956 if (alloca_adjust
> 0)
1958 /* FP > SP + frame_size. This may be because of
1959 an alloca or somethings similar. Fix sp to
1960 "pre-alloca" value, and try again. */
1961 sp
+= alloca_adjust
;
1962 /* Need to reset the status of all registers. Otherwise,
1963 we will hit a guard that prevents the new address
1964 for each register to be recomputed during the second
1966 reset_saved_regs (this_cache
);
1971 /* move $30,$sp. With different versions of gas this will be either
1972 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1973 Accept any one of these. */
1974 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1976 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1977 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1979 unsigned alloca_adjust
;
1982 frame_addr
= frame_unwind_register_signed
1984 gdbarch_num_regs (current_gdbarch
) + 30);
1986 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1987 if (alloca_adjust
> 0)
1989 /* FP > SP + frame_size. This may be because of
1990 an alloca or somethings similar. Fix sp to
1991 "pre-alloca" value, and try again. */
1993 /* Need to reset the status of all registers. Otherwise,
1994 we will hit a guard that prevents the new address
1995 for each register to be recomputed during the second
1997 reset_saved_regs (this_cache
);
2002 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2004 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2006 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2007 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2008 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2009 || high_word
== 0x3c1c /* lui $gp,n */
2010 || high_word
== 0x279c /* addiu $gp,$gp,n */
2011 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2012 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2015 /* These instructions are part of the prologue, but we don't
2016 need to do anything special to handle them. */
2018 /* The instructions below load $at or $t0 with an immediate
2019 value in preparation for a stack adjustment via
2020 subu $sp,$sp,[$at,$t0]. These instructions could also
2021 initialize a local variable, so we accept them only before
2022 a stack adjustment instruction was seen. */
2023 else if (!seen_sp_adjust
2024 && (high_word
== 0x3c01 /* lui $at,n */
2025 || high_word
== 0x3c08 /* lui $t0,n */
2026 || high_word
== 0x3421 /* ori $at,$at,n */
2027 || high_word
== 0x3508 /* ori $t0,$t0,n */
2028 || high_word
== 0x3401 /* ori $at,$zero,n */
2029 || high_word
== 0x3408 /* ori $t0,$zero,n */
2032 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2036 /* This instruction is not an instruction typically found
2037 in a prologue, so we must have reached the end of the
2039 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2040 loop now? Why would we need to continue scanning the function
2042 if (end_prologue_addr
== 0)
2043 end_prologue_addr
= cur_pc
;
2047 if (this_cache
!= NULL
)
2050 (frame_unwind_register_signed (next_frame
,
2051 gdbarch_num_regs (current_gdbarch
)
2054 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2055 this assignment below, eventually. But it's still needed
2057 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2058 + mips_regnum (current_gdbarch
)->pc
]
2059 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2063 /* If we didn't reach the end of the prologue when scanning the function
2064 instructions, then set end_prologue_addr to the address of the
2065 instruction immediately after the last one we scanned. */
2066 /* brobecker/2004-10-10: I don't think this would ever happen, but
2067 we may as well be careful and do our best if we have a null
2068 end_prologue_addr. */
2069 if (end_prologue_addr
== 0)
2070 end_prologue_addr
= cur_pc
;
2072 /* In a frameless function, we might have incorrectly
2073 skipped some load immediate instructions. Undo the skipping
2074 if the load immediate was not followed by a stack adjustment. */
2075 if (load_immediate_bytes
&& !seen_sp_adjust
)
2076 end_prologue_addr
-= load_immediate_bytes
;
2078 return end_prologue_addr
;
2081 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2082 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2083 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2086 static struct mips_frame_cache
*
2087 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2089 struct mips_frame_cache
*cache
;
2091 if ((*this_cache
) != NULL
)
2092 return (*this_cache
);
2094 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2095 (*this_cache
) = cache
;
2096 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2098 /* Analyze the function prologue. */
2100 const CORE_ADDR pc
=
2101 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2102 CORE_ADDR start_addr
;
2104 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2105 if (start_addr
== 0)
2106 start_addr
= heuristic_proc_start (pc
);
2107 /* We can't analyze the prologue if we couldn't find the begining
2109 if (start_addr
== 0)
2112 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2115 /* SP_REGNUM, contains the value and not the address. */
2116 trad_frame_set_value (cache
->saved_regs
,
2117 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
2120 return (*this_cache
);
2124 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2125 struct frame_id
*this_id
)
2127 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2129 (*this_id
) = frame_id_build (info
->base
,
2130 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2134 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2136 int regnum
, int *optimizedp
,
2137 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2138 int *realnump
, gdb_byte
*valuep
)
2140 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2142 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2143 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2146 static const struct frame_unwind mips_insn32_frame_unwind
=
2149 mips_insn32_frame_this_id
,
2150 mips_insn32_frame_prev_register
2153 static const struct frame_unwind
*
2154 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2156 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2157 if (! mips_pc_is_mips16 (pc
))
2158 return &mips_insn32_frame_unwind
;
2163 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2166 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2171 static const struct frame_base mips_insn32_frame_base
=
2173 &mips_insn32_frame_unwind
,
2174 mips_insn32_frame_base_address
,
2175 mips_insn32_frame_base_address
,
2176 mips_insn32_frame_base_address
2179 static const struct frame_base
*
2180 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2182 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2183 return &mips_insn32_frame_base
;
2188 static struct trad_frame_cache
*
2189 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2192 CORE_ADDR start_addr
;
2193 CORE_ADDR stack_addr
;
2194 struct trad_frame_cache
*this_trad_cache
;
2196 if ((*this_cache
) != NULL
)
2197 return (*this_cache
);
2198 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2199 (*this_cache
) = this_trad_cache
;
2201 /* The return address is in the link register. */
2202 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2204 /* Frame ID, since it's a frameless / stackless function, no stack
2205 space is allocated and SP on entry is the current SP. */
2206 pc
= frame_pc_unwind (next_frame
);
2207 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2208 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2209 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2211 /* Assume that the frame's base is the same as the
2213 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2215 return this_trad_cache
;
2219 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2220 struct frame_id
*this_id
)
2222 struct trad_frame_cache
*this_trad_cache
2223 = mips_stub_frame_cache (next_frame
, this_cache
);
2224 trad_frame_get_id (this_trad_cache
, this_id
);
2228 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2230 int regnum
, int *optimizedp
,
2231 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2232 int *realnump
, gdb_byte
*valuep
)
2234 struct trad_frame_cache
*this_trad_cache
2235 = mips_stub_frame_cache (next_frame
, this_cache
);
2236 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2237 lvalp
, addrp
, realnump
, valuep
);
2240 static const struct frame_unwind mips_stub_frame_unwind
=
2243 mips_stub_frame_this_id
,
2244 mips_stub_frame_prev_register
2247 static const struct frame_unwind
*
2248 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2250 struct obj_section
*s
;
2251 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2253 if (in_plt_section (pc
, NULL
))
2254 return &mips_stub_frame_unwind
;
2256 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2257 s
= find_pc_section (pc
);
2260 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2261 ".MIPS.stubs") == 0)
2262 return &mips_stub_frame_unwind
;
2268 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2271 struct trad_frame_cache
*this_trad_cache
2272 = mips_stub_frame_cache (next_frame
, this_cache
);
2273 return trad_frame_get_this_base (this_trad_cache
);
2276 static const struct frame_base mips_stub_frame_base
=
2278 &mips_stub_frame_unwind
,
2279 mips_stub_frame_base_address
,
2280 mips_stub_frame_base_address
,
2281 mips_stub_frame_base_address
2284 static const struct frame_base
*
2285 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2287 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2288 return &mips_stub_frame_base
;
2293 /* mips_addr_bits_remove - remove useless address bits */
2296 mips_addr_bits_remove (CORE_ADDR addr
)
2298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2299 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2300 /* This hack is a work-around for existing boards using PMON, the
2301 simulator, and any other 64-bit targets that doesn't have true
2302 64-bit addressing. On these targets, the upper 32 bits of
2303 addresses are ignored by the hardware. Thus, the PC or SP are
2304 likely to have been sign extended to all 1s by instruction
2305 sequences that load 32-bit addresses. For example, a typical
2306 piece of code that loads an address is this:
2308 lui $r2, <upper 16 bits>
2309 ori $r2, <lower 16 bits>
2311 But the lui sign-extends the value such that the upper 32 bits
2312 may be all 1s. The workaround is simply to mask off these
2313 bits. In the future, gcc may be changed to support true 64-bit
2314 addressing, and this masking will have to be disabled. */
2315 return addr
&= 0xffffffffUL
;
2320 /* mips_software_single_step() is called just before we want to resume
2321 the inferior, if we want to single-step it but there is no hardware
2322 or kernel single-step support (MIPS on GNU/Linux for example). We find
2323 the target of the coming instruction and breakpoint it. */
2326 mips_software_single_step (struct regcache
*regcache
)
2328 CORE_ADDR pc
, next_pc
;
2330 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2331 next_pc
= mips_next_pc (pc
);
2333 insert_single_step_breakpoint (next_pc
);
2337 /* Test whether the PC points to the return instruction at the
2338 end of a function. */
2341 mips_about_to_return (CORE_ADDR pc
)
2343 if (mips_pc_is_mips16 (pc
))
2344 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2345 generates a "jr $ra"; other times it generates code to load
2346 the return address from the stack to an accessible register (such
2347 as $a3), then a "jr" using that register. This second case
2348 is almost impossible to distinguish from an indirect jump
2349 used for switch statements, so we don't even try. */
2350 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2352 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2356 /* This fencepost looks highly suspicious to me. Removing it also
2357 seems suspicious as it could affect remote debugging across serial
2361 heuristic_proc_start (CORE_ADDR pc
)
2368 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2370 fence
= start_pc
- heuristic_fence_post
;
2374 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2375 fence
= VM_MIN_ADDRESS
;
2377 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2379 /* search back for previous return */
2380 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2381 if (start_pc
< fence
)
2383 /* It's not clear to me why we reach this point when
2384 stop_soon, but with this test, at least we
2385 don't print out warnings for every child forked (eg, on
2386 decstation). 22apr93 rich@cygnus.com. */
2387 if (stop_soon
== NO_STOP_QUIETLY
)
2389 static int blurb_printed
= 0;
2391 warning (_("GDB can't find the start of the function at 0x%s."),
2396 /* This actually happens frequently in embedded
2397 development, when you first connect to a board
2398 and your stack pointer and pc are nowhere in
2399 particular. This message needs to give people
2400 in that situation enough information to
2401 determine that it's no big deal. */
2402 printf_filtered ("\n\
2403 GDB is unable to find the start of the function at 0x%s\n\
2404 and thus can't determine the size of that function's stack frame.\n\
2405 This means that GDB may be unable to access that stack frame, or\n\
2406 the frames below it.\n\
2407 This problem is most likely caused by an invalid program counter or\n\
2409 However, if you think GDB should simply search farther back\n\
2410 from 0x%s for code which looks like the beginning of a\n\
2411 function, you can increase the range of the search using the `set\n\
2412 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2419 else if (mips_pc_is_mips16 (start_pc
))
2421 unsigned short inst
;
2423 /* On MIPS16, any one of the following is likely to be the
2424 start of a function:
2428 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2429 inst
= mips_fetch_instruction (start_pc
);
2430 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2431 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2432 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2433 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2435 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2436 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2441 else if (mips_about_to_return (start_pc
))
2443 /* Skip return and its delay slot. */
2444 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2451 struct mips_objfile_private
2457 /* According to the current ABI, should the type be passed in a
2458 floating-point register (assuming that there is space)? When there
2459 is no FPU, FP are not even considered as possible candidates for
2460 FP registers and, consequently this returns false - forces FP
2461 arguments into integer registers. */
2464 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2466 return ((typecode
== TYPE_CODE_FLT
2468 && (typecode
== TYPE_CODE_STRUCT
2469 || typecode
== TYPE_CODE_UNION
)
2470 && TYPE_NFIELDS (arg_type
) == 1
2471 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2473 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2476 /* On o32, argument passing in GPRs depends on the alignment of the type being
2477 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2480 mips_type_needs_double_align (struct type
*type
)
2482 enum type_code typecode
= TYPE_CODE (type
);
2484 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2486 else if (typecode
== TYPE_CODE_STRUCT
)
2488 if (TYPE_NFIELDS (type
) < 1)
2490 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2492 else if (typecode
== TYPE_CODE_UNION
)
2496 n
= TYPE_NFIELDS (type
);
2497 for (i
= 0; i
< n
; i
++)
2498 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2505 /* Adjust the address downward (direction of stack growth) so that it
2506 is correctly aligned for a new stack frame. */
2508 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2510 return align_down (addr
, 16);
2514 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2515 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2516 int nargs
, struct value
**args
, CORE_ADDR sp
,
2517 int struct_return
, CORE_ADDR struct_addr
)
2523 int stack_offset
= 0;
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2525 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2526 int regsize
= mips_abi_regsize (gdbarch
);
2528 /* For shared libraries, "t9" needs to point at the function
2530 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2532 /* Set the return address register to point to the entry point of
2533 the program, where a breakpoint lies in wait. */
2534 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2536 /* First ensure that the stack and structure return address (if any)
2537 are properly aligned. The stack has to be at least 64-bit
2538 aligned even on 32-bit machines, because doubles must be 64-bit
2539 aligned. For n32 and n64, stack frames need to be 128-bit
2540 aligned, so we round to this widest known alignment. */
2542 sp
= align_down (sp
, 16);
2543 struct_addr
= align_down (struct_addr
, 16);
2545 /* Now make space on the stack for the args. We allocate more
2546 than necessary for EABI, because the first few arguments are
2547 passed in registers, but that's OK. */
2548 for (argnum
= 0; argnum
< nargs
; argnum
++)
2549 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2550 sp
-= align_up (len
, 16);
2553 fprintf_unfiltered (gdb_stdlog
,
2554 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2555 paddr_nz (sp
), (long) align_up (len
, 16));
2557 /* Initialize the integer and float register pointers. */
2558 argreg
= MIPS_A0_REGNUM
;
2559 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2561 /* The struct_return pointer occupies the first parameter-passing reg. */
2565 fprintf_unfiltered (gdb_stdlog
,
2566 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2567 argreg
, paddr_nz (struct_addr
));
2568 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2571 /* Now load as many as possible of the first arguments into
2572 registers, and push the rest onto the stack. Loop thru args
2573 from first to last. */
2574 for (argnum
= 0; argnum
< nargs
; argnum
++)
2576 const gdb_byte
*val
;
2577 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2578 struct value
*arg
= args
[argnum
];
2579 struct type
*arg_type
= check_typedef (value_type (arg
));
2580 int len
= TYPE_LENGTH (arg_type
);
2581 enum type_code typecode
= TYPE_CODE (arg_type
);
2584 fprintf_unfiltered (gdb_stdlog
,
2585 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2586 argnum
+ 1, len
, (int) typecode
);
2588 /* The EABI passes structures that do not fit in a register by
2591 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2593 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2594 typecode
= TYPE_CODE_PTR
;
2598 fprintf_unfiltered (gdb_stdlog
, " push");
2601 val
= value_contents (arg
);
2603 /* 32-bit ABIs always start floating point arguments in an
2604 even-numbered floating point register. Round the FP register
2605 up before the check to see if there are any FP registers
2606 left. Non MIPS_EABI targets also pass the FP in the integer
2607 registers so also round up normal registers. */
2608 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2610 if ((float_argreg
& 1))
2614 /* Floating point arguments passed in registers have to be
2615 treated specially. On 32-bit architectures, doubles
2616 are passed in register pairs; the even register gets
2617 the low word, and the odd register gets the high word.
2618 On non-EABI processors, the first two floating point arguments are
2619 also copied to general registers, because MIPS16 functions
2620 don't use float registers for arguments. This duplication of
2621 arguments in general registers can't hurt non-MIPS16 functions
2622 because those registers are normally skipped. */
2623 /* MIPS_EABI squeezes a struct that contains a single floating
2624 point value into an FP register instead of pushing it onto the
2626 if (fp_register_arg_p (typecode
, arg_type
)
2627 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2629 /* EABI32 will pass doubles in consecutive registers, even on
2630 64-bit cores. At one time, we used to check the size of
2631 `float_argreg' to determine whether or not to pass doubles
2632 in consecutive registers, but this is not sufficient for
2633 making the ABI determination. */
2634 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2636 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2637 == BFD_ENDIAN_BIG
? 4 : 0;
2638 unsigned long regval
;
2640 /* Write the low word of the double to the even register(s). */
2641 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2643 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2644 float_argreg
, phex (regval
, 4));
2645 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2647 /* Write the high word of the double to the odd register(s). */
2648 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2650 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2651 float_argreg
, phex (regval
, 4));
2652 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2656 /* This is a floating point value that fits entirely
2657 in a single register. */
2658 /* On 32 bit ABI's the float_argreg is further adjusted
2659 above to ensure that it is even register aligned. */
2660 LONGEST regval
= extract_unsigned_integer (val
, len
);
2662 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2663 float_argreg
, phex (regval
, len
));
2664 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2669 /* Copy the argument to general registers or the stack in
2670 register-sized pieces. Large arguments are split between
2671 registers and stack. */
2672 /* Note: structs whose size is not a multiple of regsize
2673 are treated specially: Irix cc passes
2674 them in registers where gcc sometimes puts them on the
2675 stack. For maximum compatibility, we will put them in
2677 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2679 /* Note: Floating-point values that didn't fit into an FP
2680 register are only written to memory. */
2683 /* Remember if the argument was written to the stack. */
2684 int stack_used_p
= 0;
2685 int partial_len
= (len
< regsize
? len
: regsize
);
2688 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2691 /* Write this portion of the argument to the stack. */
2692 if (argreg
> MIPS_LAST_ARG_REGNUM
2694 || fp_register_arg_p (typecode
, arg_type
))
2696 /* Should shorter than int integer values be
2697 promoted to int before being stored? */
2698 int longword_offset
= 0;
2701 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2704 && (typecode
== TYPE_CODE_INT
2705 || typecode
== TYPE_CODE_PTR
2706 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2707 longword_offset
= regsize
- len
;
2708 else if ((typecode
== TYPE_CODE_STRUCT
2709 || typecode
== TYPE_CODE_UNION
)
2710 && TYPE_LENGTH (arg_type
) < regsize
)
2711 longword_offset
= regsize
- len
;
2716 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2717 paddr_nz (stack_offset
));
2718 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2719 paddr_nz (longword_offset
));
2722 addr
= sp
+ stack_offset
+ longword_offset
;
2727 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2729 for (i
= 0; i
< partial_len
; i
++)
2731 fprintf_unfiltered (gdb_stdlog
, "%02x",
2735 write_memory (addr
, val
, partial_len
);
2738 /* Note!!! This is NOT an else clause. Odd sized
2739 structs may go thru BOTH paths. Floating point
2740 arguments will not. */
2741 /* Write this portion of the argument to a general
2742 purpose register. */
2743 if (argreg
<= MIPS_LAST_ARG_REGNUM
2744 && !fp_register_arg_p (typecode
, arg_type
))
2747 extract_unsigned_integer (val
, partial_len
);
2750 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2752 phex (regval
, regsize
));
2753 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2760 /* Compute the the offset into the stack at which we
2761 will copy the next parameter.
2763 In the new EABI (and the NABI32), the stack_offset
2764 only needs to be adjusted when it has been used. */
2767 stack_offset
+= align_up (partial_len
, regsize
);
2771 fprintf_unfiltered (gdb_stdlog
, "\n");
2774 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2776 /* Return adjusted stack pointer. */
2780 /* Determine the return value convention being used. */
2782 static enum return_value_convention
2783 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2784 struct type
*type
, struct regcache
*regcache
,
2785 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2787 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2788 return RETURN_VALUE_STRUCT_CONVENTION
;
2790 memset (readbuf
, 0, TYPE_LENGTH (type
));
2791 return RETURN_VALUE_REGISTER_CONVENTION
;
2795 /* N32/N64 ABI stuff. */
2798 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2799 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2800 int nargs
, struct value
**args
, CORE_ADDR sp
,
2801 int struct_return
, CORE_ADDR struct_addr
)
2807 int stack_offset
= 0;
2808 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2809 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2811 /* For shared libraries, "t9" needs to point at the function
2813 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2815 /* Set the return address register to point to the entry point of
2816 the program, where a breakpoint lies in wait. */
2817 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2819 /* First ensure that the stack and structure return address (if any)
2820 are properly aligned. The stack has to be at least 64-bit
2821 aligned even on 32-bit machines, because doubles must be 64-bit
2822 aligned. For n32 and n64, stack frames need to be 128-bit
2823 aligned, so we round to this widest known alignment. */
2825 sp
= align_down (sp
, 16);
2826 struct_addr
= align_down (struct_addr
, 16);
2828 /* Now make space on the stack for the args. */
2829 for (argnum
= 0; argnum
< nargs
; argnum
++)
2830 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2831 sp
-= align_up (len
, 16);
2834 fprintf_unfiltered (gdb_stdlog
,
2835 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2836 paddr_nz (sp
), (long) align_up (len
, 16));
2838 /* Initialize the integer and float register pointers. */
2839 argreg
= MIPS_A0_REGNUM
;
2840 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2842 /* The struct_return pointer occupies the first parameter-passing reg. */
2846 fprintf_unfiltered (gdb_stdlog
,
2847 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2848 argreg
, paddr_nz (struct_addr
));
2849 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2852 /* Now load as many as possible of the first arguments into
2853 registers, and push the rest onto the stack. Loop thru args
2854 from first to last. */
2855 for (argnum
= 0; argnum
< nargs
; argnum
++)
2857 const gdb_byte
*val
;
2858 struct value
*arg
= args
[argnum
];
2859 struct type
*arg_type
= check_typedef (value_type (arg
));
2860 int len
= TYPE_LENGTH (arg_type
);
2861 enum type_code typecode
= TYPE_CODE (arg_type
);
2864 fprintf_unfiltered (gdb_stdlog
,
2865 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2866 argnum
+ 1, len
, (int) typecode
);
2868 val
= value_contents (arg
);
2870 if (fp_register_arg_p (typecode
, arg_type
)
2871 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2873 /* This is a floating point value that fits entirely
2874 in a single register. */
2875 /* On 32 bit ABI's the float_argreg is further adjusted
2876 above to ensure that it is even register aligned. */
2877 LONGEST regval
= extract_unsigned_integer (val
, len
);
2879 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2880 float_argreg
, phex (regval
, len
));
2881 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2884 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2885 argreg
, phex (regval
, len
));
2886 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2891 /* Copy the argument to general registers or the stack in
2892 register-sized pieces. Large arguments are split between
2893 registers and stack. */
2894 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2895 are treated specially: Irix cc passes them in registers
2896 where gcc sometimes puts them on the stack. For maximum
2897 compatibility, we will put them in both places. */
2898 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2899 && len
% MIPS64_REGSIZE
!= 0);
2900 /* Note: Floating-point values that didn't fit into an FP
2901 register are only written to memory. */
2904 /* Remember if the argument was written to the stack. */
2905 int stack_used_p
= 0;
2906 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2909 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2912 /* Write this portion of the argument to the stack. */
2913 if (argreg
> MIPS_LAST_ARG_REGNUM
2915 || fp_register_arg_p (typecode
, arg_type
))
2917 /* Should shorter than int integer values be
2918 promoted to int before being stored? */
2919 int longword_offset
= 0;
2922 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2924 if ((typecode
== TYPE_CODE_INT
2925 || typecode
== TYPE_CODE_PTR
2926 || typecode
== TYPE_CODE_FLT
)
2928 longword_offset
= MIPS64_REGSIZE
- len
;
2933 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2934 paddr_nz (stack_offset
));
2935 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2936 paddr_nz (longword_offset
));
2939 addr
= sp
+ stack_offset
+ longword_offset
;
2944 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2946 for (i
= 0; i
< partial_len
; i
++)
2948 fprintf_unfiltered (gdb_stdlog
, "%02x",
2952 write_memory (addr
, val
, partial_len
);
2955 /* Note!!! This is NOT an else clause. Odd sized
2956 structs may go thru BOTH paths. Floating point
2957 arguments will not. */
2958 /* Write this portion of the argument to a general
2959 purpose register. */
2960 if (argreg
<= MIPS_LAST_ARG_REGNUM
2961 && !fp_register_arg_p (typecode
, arg_type
))
2964 extract_unsigned_integer (val
, partial_len
);
2966 /* A non-floating-point argument being passed in a
2967 general register. If a struct or union, and if
2968 the remaining length is smaller than the register
2969 size, we have to adjust the register value on
2972 It does not seem to be necessary to do the
2973 same for integral types. */
2975 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
2976 && partial_len
< MIPS64_REGSIZE
2977 && (typecode
== TYPE_CODE_STRUCT
2978 || typecode
== TYPE_CODE_UNION
))
2979 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
2983 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2985 phex (regval
, MIPS64_REGSIZE
));
2986 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2993 /* Compute the the offset into the stack at which we
2994 will copy the next parameter.
2996 In N32 (N64?), the stack_offset only needs to be
2997 adjusted when it has been used. */
3000 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3004 fprintf_unfiltered (gdb_stdlog
, "\n");
3007 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3009 /* Return adjusted stack pointer. */
3013 static enum return_value_convention
3014 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3015 struct type
*type
, struct regcache
*regcache
,
3016 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3018 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3019 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3020 || TYPE_CODE (type
) == TYPE_CODE_UNION
3021 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3022 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3023 return RETURN_VALUE_STRUCT_CONVENTION
;
3024 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3025 && TYPE_LENGTH (type
) == 16
3026 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3028 /* A 128-bit floating-point value fills both $f0 and $f2. The
3029 two registers are used in the same as memory order, so the
3030 eight bytes with the lower memory address are in $f0. */
3032 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3033 mips_xfer_register (regcache
,
3034 gdbarch_num_regs (current_gdbarch
)
3035 + mips_regnum (current_gdbarch
)->fp0
,
3036 8, gdbarch_byte_order (current_gdbarch
),
3037 readbuf
, writebuf
, 0);
3038 mips_xfer_register (regcache
,
3039 gdbarch_num_regs (current_gdbarch
)
3040 + mips_regnum (current_gdbarch
)->fp0
+ 2,
3041 8, gdbarch_byte_order (current_gdbarch
),
3042 readbuf
? readbuf
+ 8 : readbuf
,
3043 writebuf
? writebuf
+ 8 : writebuf
, 0);
3044 return RETURN_VALUE_REGISTER_CONVENTION
;
3046 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3047 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3049 /* A floating-point value belongs in the least significant part
3052 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3053 mips_xfer_register (regcache
,
3054 gdbarch_num_regs (current_gdbarch
)
3055 + mips_regnum (current_gdbarch
)->fp0
,
3057 gdbarch_byte_order (current_gdbarch
),
3058 readbuf
, writebuf
, 0);
3059 return RETURN_VALUE_REGISTER_CONVENTION
;
3061 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3062 && TYPE_NFIELDS (type
) <= 2
3063 && TYPE_NFIELDS (type
) >= 1
3064 && ((TYPE_NFIELDS (type
) == 1
3065 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3067 || (TYPE_NFIELDS (type
) == 2
3068 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3070 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3072 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3074 /* A struct that contains one or two floats. Each value is part
3075 in the least significant part of their floating point
3079 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3080 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3082 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3085 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3087 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3089 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3090 gdbarch_byte_order (current_gdbarch
),
3091 readbuf
, writebuf
, offset
);
3093 return RETURN_VALUE_REGISTER_CONVENTION
;
3095 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3096 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3098 /* A structure or union. Extract the left justified value,
3099 regardless of the byte order. I.e. DO NOT USE
3103 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3104 offset
< TYPE_LENGTH (type
);
3105 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3107 int xfer
= register_size (current_gdbarch
, regnum
);
3108 if (offset
+ xfer
> TYPE_LENGTH (type
))
3109 xfer
= TYPE_LENGTH (type
) - offset
;
3111 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3112 offset
, xfer
, regnum
);
3113 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3115 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3117 return RETURN_VALUE_REGISTER_CONVENTION
;
3121 /* A scalar extract each part but least-significant-byte
3125 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3126 offset
< TYPE_LENGTH (type
);
3127 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3129 int xfer
= register_size (current_gdbarch
, regnum
);
3130 if (offset
+ xfer
> TYPE_LENGTH (type
))
3131 xfer
= TYPE_LENGTH (type
) - offset
;
3133 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3134 offset
, xfer
, regnum
);
3135 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3137 gdbarch_byte_order (current_gdbarch
),
3138 readbuf
, writebuf
, offset
);
3140 return RETURN_VALUE_REGISTER_CONVENTION
;
3144 /* O32 ABI stuff. */
3147 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3148 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3149 int nargs
, struct value
**args
, CORE_ADDR sp
,
3150 int struct_return
, CORE_ADDR struct_addr
)
3156 int stack_offset
= 0;
3157 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3158 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3160 /* For shared libraries, "t9" needs to point at the function
3162 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3164 /* Set the return address register to point to the entry point of
3165 the program, where a breakpoint lies in wait. */
3166 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3168 /* First ensure that the stack and structure return address (if any)
3169 are properly aligned. The stack has to be at least 64-bit
3170 aligned even on 32-bit machines, because doubles must be 64-bit
3171 aligned. For n32 and n64, stack frames need to be 128-bit
3172 aligned, so we round to this widest known alignment. */
3174 sp
= align_down (sp
, 16);
3175 struct_addr
= align_down (struct_addr
, 16);
3177 /* Now make space on the stack for the args. */
3178 for (argnum
= 0; argnum
< nargs
; argnum
++)
3180 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3181 int arglen
= TYPE_LENGTH (arg_type
);
3183 /* Align to double-word if necessary. */
3184 if (mips_type_needs_double_align (arg_type
))
3185 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3186 /* Allocate space on the stack. */
3187 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3189 sp
-= align_up (len
, 16);
3192 fprintf_unfiltered (gdb_stdlog
,
3193 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3194 paddr_nz (sp
), (long) align_up (len
, 16));
3196 /* Initialize the integer and float register pointers. */
3197 argreg
= MIPS_A0_REGNUM
;
3198 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3200 /* The struct_return pointer occupies the first parameter-passing reg. */
3204 fprintf_unfiltered (gdb_stdlog
,
3205 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3206 argreg
, paddr_nz (struct_addr
));
3207 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3208 stack_offset
+= MIPS32_REGSIZE
;
3211 /* Now load as many as possible of the first arguments into
3212 registers, and push the rest onto the stack. Loop thru args
3213 from first to last. */
3214 for (argnum
= 0; argnum
< nargs
; argnum
++)
3216 const gdb_byte
*val
;
3217 struct value
*arg
= args
[argnum
];
3218 struct type
*arg_type
= check_typedef (value_type (arg
));
3219 int len
= TYPE_LENGTH (arg_type
);
3220 enum type_code typecode
= TYPE_CODE (arg_type
);
3223 fprintf_unfiltered (gdb_stdlog
,
3224 "mips_o32_push_dummy_call: %d len=%d type=%d",
3225 argnum
+ 1, len
, (int) typecode
);
3227 val
= value_contents (arg
);
3229 /* 32-bit ABIs always start floating point arguments in an
3230 even-numbered floating point register. Round the FP register
3231 up before the check to see if there are any FP registers
3232 left. O32/O64 targets also pass the FP in the integer
3233 registers so also round up normal registers. */
3234 if (fp_register_arg_p (typecode
, arg_type
))
3236 if ((float_argreg
& 1))
3240 /* Floating point arguments passed in registers have to be
3241 treated specially. On 32-bit architectures, doubles
3242 are passed in register pairs; the even register gets
3243 the low word, and the odd register gets the high word.
3244 On O32/O64, the first two floating point arguments are
3245 also copied to general registers, because MIPS16 functions
3246 don't use float registers for arguments. This duplication of
3247 arguments in general registers can't hurt non-MIPS16 functions
3248 because those registers are normally skipped. */
3250 if (fp_register_arg_p (typecode
, arg_type
)
3251 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3253 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3255 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3256 == BFD_ENDIAN_BIG
? 4 : 0;
3257 unsigned long regval
;
3259 /* Write the low word of the double to the even register(s). */
3260 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3262 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3263 float_argreg
, phex (regval
, 4));
3264 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3266 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3267 argreg
, phex (regval
, 4));
3268 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3270 /* Write the high word of the double to the odd register(s). */
3271 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3273 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3274 float_argreg
, phex (regval
, 4));
3275 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3278 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3279 argreg
, phex (regval
, 4));
3280 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3284 /* This is a floating point value that fits entirely
3285 in a single register. */
3286 /* On 32 bit ABI's the float_argreg is further adjusted
3287 above to ensure that it is even register aligned. */
3288 LONGEST regval
= extract_unsigned_integer (val
, len
);
3290 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3291 float_argreg
, phex (regval
, len
));
3292 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3293 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3294 registers for each argument. The below is (my
3295 guess) to ensure that the corresponding integer
3296 register has reserved the same space. */
3298 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3299 argreg
, phex (regval
, len
));
3300 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3303 /* Reserve space for the FP register. */
3304 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3308 /* Copy the argument to general registers or the stack in
3309 register-sized pieces. Large arguments are split between
3310 registers and stack. */
3311 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3312 are treated specially: Irix cc passes
3313 them in registers where gcc sometimes puts them on the
3314 stack. For maximum compatibility, we will put them in
3316 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3317 && len
% MIPS32_REGSIZE
!= 0);
3318 /* Structures should be aligned to eight bytes (even arg registers)
3319 on MIPS_ABI_O32, if their first member has double precision. */
3320 if (mips_type_needs_double_align (arg_type
))
3325 stack_offset
+= MIPS32_REGSIZE
;
3330 /* Remember if the argument was written to the stack. */
3331 int stack_used_p
= 0;
3332 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3335 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3338 /* Write this portion of the argument to the stack. */
3339 if (argreg
> MIPS_LAST_ARG_REGNUM
3340 || odd_sized_struct
)
3342 /* Should shorter than int integer values be
3343 promoted to int before being stored? */
3344 int longword_offset
= 0;
3350 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3351 paddr_nz (stack_offset
));
3352 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3353 paddr_nz (longword_offset
));
3356 addr
= sp
+ stack_offset
+ longword_offset
;
3361 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3363 for (i
= 0; i
< partial_len
; i
++)
3365 fprintf_unfiltered (gdb_stdlog
, "%02x",
3369 write_memory (addr
, val
, partial_len
);
3372 /* Note!!! This is NOT an else clause. Odd sized
3373 structs may go thru BOTH paths. */
3374 /* Write this portion of the argument to a general
3375 purpose register. */
3376 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3378 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3379 /* Value may need to be sign extended, because
3380 mips_isa_regsize() != mips_abi_regsize(). */
3382 /* A non-floating-point argument being passed in a
3383 general register. If a struct or union, and if
3384 the remaining length is smaller than the register
3385 size, we have to adjust the register value on
3388 It does not seem to be necessary to do the
3389 same for integral types.
3391 Also don't do this adjustment on O64 binaries.
3393 cagney/2001-07-23: gdb/179: Also, GCC, when
3394 outputting LE O32 with sizeof (struct) <
3395 mips_abi_regsize(), generates a left shift
3396 as part of storing the argument in a register
3397 (the left shift isn't generated when
3398 sizeof (struct) >= mips_abi_regsize()). Since
3399 it is quite possible that this is GCC
3400 contradicting the LE/O32 ABI, GDB has not been
3401 adjusted to accommodate this. Either someone
3402 needs to demonstrate that the LE/O32 ABI
3403 specifies such a left shift OR this new ABI gets
3404 identified as such and GDB gets tweaked
3407 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3408 && partial_len
< MIPS32_REGSIZE
3409 && (typecode
== TYPE_CODE_STRUCT
3410 || typecode
== TYPE_CODE_UNION
))
3411 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3415 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3417 phex (regval
, MIPS32_REGSIZE
));
3418 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3421 /* Prevent subsequent floating point arguments from
3422 being passed in floating point registers. */
3423 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3429 /* Compute the the offset into the stack at which we
3430 will copy the next parameter.
3432 In older ABIs, the caller reserved space for
3433 registers that contained arguments. This was loosely
3434 refered to as their "home". Consequently, space is
3435 always allocated. */
3437 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3441 fprintf_unfiltered (gdb_stdlog
, "\n");
3444 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3446 /* Return adjusted stack pointer. */
3450 static enum return_value_convention
3451 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3452 struct regcache
*regcache
,
3453 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3455 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3457 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3458 || TYPE_CODE (type
) == TYPE_CODE_UNION
3459 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3460 return RETURN_VALUE_STRUCT_CONVENTION
;
3461 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3462 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3464 /* A single-precision floating-point value. It fits in the
3465 least significant part of FP0. */
3467 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3468 mips_xfer_register (regcache
,
3469 gdbarch_num_regs (current_gdbarch
)
3470 + mips_regnum (current_gdbarch
)->fp0
,
3472 gdbarch_byte_order (current_gdbarch
),
3473 readbuf
, writebuf
, 0);
3474 return RETURN_VALUE_REGISTER_CONVENTION
;
3476 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3477 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3479 /* A double-precision floating-point value. The most
3480 significant part goes in FP1, and the least significant in
3483 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3484 switch (gdbarch_byte_order (current_gdbarch
))
3486 case BFD_ENDIAN_LITTLE
:
3487 mips_xfer_register (regcache
,
3488 gdbarch_num_regs (current_gdbarch
)
3489 + mips_regnum (current_gdbarch
)->fp0
+
3490 0, 4, gdbarch_byte_order (current_gdbarch
),
3491 readbuf
, writebuf
, 0);
3492 mips_xfer_register (regcache
,
3493 gdbarch_num_regs (current_gdbarch
)
3494 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3495 4, gdbarch_byte_order (current_gdbarch
),
3496 readbuf
, writebuf
, 4);
3498 case BFD_ENDIAN_BIG
:
3499 mips_xfer_register (regcache
,
3500 gdbarch_num_regs (current_gdbarch
)
3501 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3502 4, gdbarch_byte_order (current_gdbarch
),
3503 readbuf
, writebuf
, 0);
3504 mips_xfer_register (regcache
,
3505 gdbarch_num_regs (current_gdbarch
)
3506 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3507 4, gdbarch_byte_order (current_gdbarch
),
3508 readbuf
, writebuf
, 4);
3511 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3513 return RETURN_VALUE_REGISTER_CONVENTION
;
3516 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3517 && TYPE_NFIELDS (type
) <= 2
3518 && TYPE_NFIELDS (type
) >= 1
3519 && ((TYPE_NFIELDS (type
) == 1
3520 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3522 || (TYPE_NFIELDS (type
) == 2
3523 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3525 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3527 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3529 /* A struct that contains one or two floats. Each value is part
3530 in the least significant part of their floating point
3532 gdb_byte reg
[MAX_REGISTER_SIZE
];
3535 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3536 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3538 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3541 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3543 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3545 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3546 gdbarch_byte_order (current_gdbarch
),
3547 readbuf
, writebuf
, offset
);
3549 return RETURN_VALUE_REGISTER_CONVENTION
;
3553 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3554 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3556 /* A structure or union. Extract the left justified value,
3557 regardless of the byte order. I.e. DO NOT USE
3561 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3562 offset
< TYPE_LENGTH (type
);
3563 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3565 int xfer
= register_size (current_gdbarch
, regnum
);
3566 if (offset
+ xfer
> TYPE_LENGTH (type
))
3567 xfer
= TYPE_LENGTH (type
) - offset
;
3569 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3570 offset
, xfer
, regnum
);
3571 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3573 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3575 return RETURN_VALUE_REGISTER_CONVENTION
;
3580 /* A scalar extract each part but least-significant-byte
3581 justified. o32 thinks registers are 4 byte, regardless of
3585 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3586 offset
< TYPE_LENGTH (type
);
3587 offset
+= MIPS32_REGSIZE
, regnum
++)
3589 int xfer
= MIPS32_REGSIZE
;
3590 if (offset
+ xfer
> TYPE_LENGTH (type
))
3591 xfer
= TYPE_LENGTH (type
) - offset
;
3593 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3594 offset
, xfer
, regnum
);
3595 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3597 gdbarch_byte_order (current_gdbarch
),
3598 readbuf
, writebuf
, offset
);
3600 return RETURN_VALUE_REGISTER_CONVENTION
;
3604 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3608 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3609 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3611 struct value
**args
, CORE_ADDR sp
,
3612 int struct_return
, CORE_ADDR struct_addr
)
3618 int stack_offset
= 0;
3619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3620 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3622 /* For shared libraries, "t9" needs to point at the function
3624 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3626 /* Set the return address register to point to the entry point of
3627 the program, where a breakpoint lies in wait. */
3628 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3630 /* First ensure that the stack and structure return address (if any)
3631 are properly aligned. The stack has to be at least 64-bit
3632 aligned even on 32-bit machines, because doubles must be 64-bit
3633 aligned. For n32 and n64, stack frames need to be 128-bit
3634 aligned, so we round to this widest known alignment. */
3636 sp
= align_down (sp
, 16);
3637 struct_addr
= align_down (struct_addr
, 16);
3639 /* Now make space on the stack for the args. */
3640 for (argnum
= 0; argnum
< nargs
; argnum
++)
3642 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3643 int arglen
= TYPE_LENGTH (arg_type
);
3645 /* Allocate space on the stack. */
3646 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3648 sp
-= align_up (len
, 16);
3651 fprintf_unfiltered (gdb_stdlog
,
3652 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3653 paddr_nz (sp
), (long) align_up (len
, 16));
3655 /* Initialize the integer and float register pointers. */
3656 argreg
= MIPS_A0_REGNUM
;
3657 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3659 /* The struct_return pointer occupies the first parameter-passing reg. */
3663 fprintf_unfiltered (gdb_stdlog
,
3664 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3665 argreg
, paddr_nz (struct_addr
));
3666 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3667 stack_offset
+= MIPS64_REGSIZE
;
3670 /* Now load as many as possible of the first arguments into
3671 registers, and push the rest onto the stack. Loop thru args
3672 from first to last. */
3673 for (argnum
= 0; argnum
< nargs
; argnum
++)
3675 const gdb_byte
*val
;
3676 struct value
*arg
= args
[argnum
];
3677 struct type
*arg_type
= check_typedef (value_type (arg
));
3678 int len
= TYPE_LENGTH (arg_type
);
3679 enum type_code typecode
= TYPE_CODE (arg_type
);
3682 fprintf_unfiltered (gdb_stdlog
,
3683 "mips_o64_push_dummy_call: %d len=%d type=%d",
3684 argnum
+ 1, len
, (int) typecode
);
3686 val
= value_contents (arg
);
3688 /* Floating point arguments passed in registers have to be
3689 treated specially. On 32-bit architectures, doubles
3690 are passed in register pairs; the even register gets
3691 the low word, and the odd register gets the high word.
3692 On O32/O64, the first two floating point arguments are
3693 also copied to general registers, because MIPS16 functions
3694 don't use float registers for arguments. This duplication of
3695 arguments in general registers can't hurt non-MIPS16 functions
3696 because those registers are normally skipped. */
3698 if (fp_register_arg_p (typecode
, arg_type
)
3699 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3701 LONGEST regval
= extract_unsigned_integer (val
, len
);
3703 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3704 float_argreg
, phex (regval
, len
));
3705 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3707 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3708 argreg
, phex (regval
, len
));
3709 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3711 /* Reserve space for the FP register. */
3712 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3716 /* Copy the argument to general registers or the stack in
3717 register-sized pieces. Large arguments are split between
3718 registers and stack. */
3719 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3720 are treated specially: Irix cc passes them in registers
3721 where gcc sometimes puts them on the stack. For maximum
3722 compatibility, we will put them in both places. */
3723 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3724 && len
% MIPS64_REGSIZE
!= 0);
3727 /* Remember if the argument was written to the stack. */
3728 int stack_used_p
= 0;
3729 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3732 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3735 /* Write this portion of the argument to the stack. */
3736 if (argreg
> MIPS_LAST_ARG_REGNUM
3737 || odd_sized_struct
)
3739 /* Should shorter than int integer values be
3740 promoted to int before being stored? */
3741 int longword_offset
= 0;
3744 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3746 if ((typecode
== TYPE_CODE_INT
3747 || typecode
== TYPE_CODE_PTR
3748 || typecode
== TYPE_CODE_FLT
)
3750 longword_offset
= MIPS64_REGSIZE
- len
;
3755 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3756 paddr_nz (stack_offset
));
3757 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3758 paddr_nz (longword_offset
));
3761 addr
= sp
+ stack_offset
+ longword_offset
;
3766 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3768 for (i
= 0; i
< partial_len
; i
++)
3770 fprintf_unfiltered (gdb_stdlog
, "%02x",
3774 write_memory (addr
, val
, partial_len
);
3777 /* Note!!! This is NOT an else clause. Odd sized
3778 structs may go thru BOTH paths. */
3779 /* Write this portion of the argument to a general
3780 purpose register. */
3781 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3783 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3784 /* Value may need to be sign extended, because
3785 mips_isa_regsize() != mips_abi_regsize(). */
3787 /* A non-floating-point argument being passed in a
3788 general register. If a struct or union, and if
3789 the remaining length is smaller than the register
3790 size, we have to adjust the register value on
3793 It does not seem to be necessary to do the
3794 same for integral types. */
3796 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3797 && partial_len
< MIPS64_REGSIZE
3798 && (typecode
== TYPE_CODE_STRUCT
3799 || typecode
== TYPE_CODE_UNION
))
3800 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3804 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3806 phex (regval
, MIPS64_REGSIZE
));
3807 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3810 /* Prevent subsequent floating point arguments from
3811 being passed in floating point registers. */
3812 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3818 /* Compute the the offset into the stack at which we
3819 will copy the next parameter.
3821 In older ABIs, the caller reserved space for
3822 registers that contained arguments. This was loosely
3823 refered to as their "home". Consequently, space is
3824 always allocated. */
3826 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3830 fprintf_unfiltered (gdb_stdlog
, "\n");
3833 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3835 /* Return adjusted stack pointer. */
3839 static enum return_value_convention
3840 mips_o64_return_value (struct gdbarch
*gdbarch
,
3841 struct type
*type
, struct regcache
*regcache
,
3842 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3846 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3847 || TYPE_CODE (type
) == TYPE_CODE_UNION
3848 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3849 return RETURN_VALUE_STRUCT_CONVENTION
;
3850 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3852 /* A floating-point value. It fits in the least significant
3855 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3856 mips_xfer_register (regcache
,
3857 gdbarch_num_regs (current_gdbarch
)
3858 + mips_regnum (current_gdbarch
)->fp0
,
3860 gdbarch_byte_order (current_gdbarch
),
3861 readbuf
, writebuf
, 0);
3862 return RETURN_VALUE_REGISTER_CONVENTION
;
3866 /* A scalar extract each part but least-significant-byte
3870 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3871 offset
< TYPE_LENGTH (type
);
3872 offset
+= MIPS64_REGSIZE
, regnum
++)
3874 int xfer
= MIPS64_REGSIZE
;
3875 if (offset
+ xfer
> TYPE_LENGTH (type
))
3876 xfer
= TYPE_LENGTH (type
) - offset
;
3878 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3879 offset
, xfer
, regnum
);
3880 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3882 gdbarch_byte_order (current_gdbarch
),
3883 readbuf
, writebuf
, offset
);
3885 return RETURN_VALUE_REGISTER_CONVENTION
;
3889 /* Floating point register management.
3891 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3892 64bit operations, these early MIPS cpus treat fp register pairs
3893 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3894 registers and offer a compatibility mode that emulates the MIPS2 fp
3895 model. When operating in MIPS2 fp compat mode, later cpu's split
3896 double precision floats into two 32-bit chunks and store them in
3897 consecutive fp regs. To display 64-bit floats stored in this
3898 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3899 Throw in user-configurable endianness and you have a real mess.
3901 The way this works is:
3902 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3903 double-precision value will be split across two logical registers.
3904 The lower-numbered logical register will hold the low-order bits,
3905 regardless of the processor's endianness.
3906 - If we are on a 64-bit processor, and we are looking for a
3907 single-precision value, it will be in the low ordered bits
3908 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3909 save slot in memory.
3910 - If we are in 64-bit mode, everything is straightforward.
3912 Note that this code only deals with "live" registers at the top of the
3913 stack. We will attempt to deal with saved registers later, when
3914 the raw/cooked register interface is in place. (We need a general
3915 interface that can deal with dynamic saved register sizes -- fp
3916 regs could be 32 bits wide in one frame and 64 on the frame above
3919 static struct type
*
3920 mips_float_register_type (void)
3922 return builtin_type_ieee_single
;
3925 static struct type
*
3926 mips_double_register_type (void)
3928 return builtin_type_ieee_double
;
3931 /* Copy a 32-bit single-precision value from the current frame
3932 into rare_buffer. */
3935 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3936 gdb_byte
*rare_buffer
)
3938 int raw_size
= register_size (current_gdbarch
, regno
);
3939 gdb_byte
*raw_buffer
= alloca (raw_size
);
3941 if (!frame_register_read (frame
, regno
, raw_buffer
))
3942 error (_("can't read register %d (%s)"),
3943 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3946 /* We have a 64-bit value for this register. Find the low-order
3950 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3955 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3959 memcpy (rare_buffer
, raw_buffer
, 4);
3963 /* Copy a 64-bit double-precision value from the current frame into
3964 rare_buffer. This may include getting half of it from the next
3968 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3969 gdb_byte
*rare_buffer
)
3971 int raw_size
= register_size (current_gdbarch
, regno
);
3973 if (raw_size
== 8 && !mips2_fp_compat (frame
))
3975 /* We have a 64-bit value for this register, and we should use
3977 if (!frame_register_read (frame
, regno
, rare_buffer
))
3978 error (_("can't read register %d (%s)"),
3979 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3983 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3984 internal_error (__FILE__
, __LINE__
,
3985 _("mips_read_fp_register_double: bad access to "
3986 "odd-numbered FP register"));
3988 /* mips_read_fp_register_single will find the correct 32 bits from
3990 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3992 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3993 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3997 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3998 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4004 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4006 { /* do values for FP (float) regs */
4007 gdb_byte
*raw_buffer
;
4008 double doub
, flt1
; /* doubles extracted from raw hex data */
4011 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
4012 mips_regnum (current_gdbarch
)->fp0
));
4014 fprintf_filtered (file
, "%s:",
4015 gdbarch_register_name (current_gdbarch
, regnum
));
4016 fprintf_filtered (file
, "%*s",
4017 4 - (int) strlen (gdbarch_register_name
4018 (current_gdbarch
, regnum
)),
4021 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4023 /* 4-byte registers: Print hex and floating. Also print even
4024 numbered registers as doubles. */
4025 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4026 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4028 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4031 fprintf_filtered (file
, " flt: ");
4033 fprintf_filtered (file
, " <invalid float> ");
4035 fprintf_filtered (file
, "%-17.9g", flt1
);
4037 if (regnum
% 2 == 0)
4039 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4040 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4043 fprintf_filtered (file
, " dbl: ");
4045 fprintf_filtered (file
, "<invalid double>");
4047 fprintf_filtered (file
, "%-24.17g", doub
);
4052 /* Eight byte registers: print each one as hex, float and double. */
4053 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4054 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4056 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4057 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4060 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4063 fprintf_filtered (file
, " flt: ");
4065 fprintf_filtered (file
, "<invalid float>");
4067 fprintf_filtered (file
, "%-17.9g", flt1
);
4069 fprintf_filtered (file
, " dbl: ");
4071 fprintf_filtered (file
, "<invalid double>");
4073 fprintf_filtered (file
, "%-24.17g", doub
);
4078 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4081 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4082 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4085 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4087 mips_print_fp_register (file
, frame
, regnum
);
4091 /* Get the data in raw format. */
4092 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4094 fprintf_filtered (file
, "%s: [Invalid]",
4095 gdbarch_register_name (current_gdbarch
, regnum
));
4099 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
4101 /* The problem with printing numeric register names (r26, etc.) is that
4102 the user can't use them on input. Probably the best solution is to
4103 fix it so that either the numeric or the funky (a2, etc.) names
4104 are accepted on input. */
4105 if (regnum
< MIPS_NUMREGS
)
4106 fprintf_filtered (file
, "(r%d): ", regnum
);
4108 fprintf_filtered (file
, ": ");
4110 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4112 register_size (current_gdbarch
,
4113 regnum
) - register_size (current_gdbarch
, regnum
);
4117 print_scalar_formatted (raw_buffer
+ offset
,
4118 register_type (gdbarch
, regnum
), 'x', 0,
4122 /* Replacement for generic do_registers_info.
4123 Print regs in pretty columns. */
4126 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4129 fprintf_filtered (file
, " ");
4130 mips_print_fp_register (file
, frame
, regnum
);
4131 fprintf_filtered (file
, "\n");
4136 /* Print a row's worth of GP (int) registers, with name labels above */
4139 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4142 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4143 /* do values for GP (int) regs */
4144 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4145 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4149 /* For GP registers, we print a separate row of names above the vals */
4150 for (col
= 0, regnum
= start_regnum
;
4151 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4152 + gdbarch_num_pseudo_regs (current_gdbarch
);
4155 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4156 continue; /* unused register */
4157 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4159 break; /* end the row: reached FP register */
4160 /* Large registers are handled separately. */
4161 if (register_size (current_gdbarch
, regnum
)
4162 > mips_abi_regsize (current_gdbarch
))
4165 break; /* End the row before this register. */
4167 /* Print this register on a row by itself. */
4168 mips_print_register (file
, frame
, regnum
);
4169 fprintf_filtered (file
, "\n");
4173 fprintf_filtered (file
, " ");
4174 fprintf_filtered (file
,
4175 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4176 gdbarch_register_name (current_gdbarch
, regnum
));
4183 /* print the R0 to R31 names */
4184 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4185 fprintf_filtered (file
, "\n R%-4d",
4186 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4188 fprintf_filtered (file
, "\n ");
4190 /* now print the values in hex, 4 or 8 to the row */
4191 for (col
= 0, regnum
= start_regnum
;
4192 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4193 + gdbarch_num_pseudo_regs (current_gdbarch
);
4196 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4197 continue; /* unused register */
4198 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4200 break; /* end row: reached FP register */
4201 if (register_size (current_gdbarch
, regnum
)
4202 > mips_abi_regsize (current_gdbarch
))
4203 break; /* End row: large register. */
4205 /* OK: get the data in raw format. */
4206 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4207 error (_("can't read register %d (%s)"),
4208 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
4209 /* pad small registers */
4211 byte
< (mips_abi_regsize (current_gdbarch
)
4212 - register_size (current_gdbarch
, regnum
)); byte
++)
4213 printf_filtered (" ");
4214 /* Now print the register value in hex, endian order. */
4215 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4217 register_size (current_gdbarch
,
4218 regnum
) - register_size (current_gdbarch
, regnum
);
4219 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4220 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4222 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4224 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4225 fprintf_filtered (file
, " ");
4228 if (col
> 0) /* ie. if we actually printed anything... */
4229 fprintf_filtered (file
, "\n");
4234 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4237 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4238 struct frame_info
*frame
, int regnum
, int all
)
4240 if (regnum
!= -1) /* do one specified register */
4242 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4243 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
4244 error (_("Not a valid register for the current processor type"));
4246 mips_print_register (file
, frame
, regnum
);
4247 fprintf_filtered (file
, "\n");
4250 /* do all (or most) registers */
4252 regnum
= gdbarch_num_regs (current_gdbarch
);
4253 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4254 + gdbarch_num_pseudo_regs (current_gdbarch
))
4256 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4259 if (all
) /* true for "INFO ALL-REGISTERS" command */
4260 regnum
= print_fp_register_row (file
, frame
, regnum
);
4262 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4265 regnum
= print_gp_register_row (file
, frame
, regnum
);
4270 /* Is this a branch with a delay slot? */
4273 is_delayed (unsigned long insn
)
4276 for (i
= 0; i
< NUMOPCODES
; ++i
)
4277 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4278 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4280 return (i
< NUMOPCODES
4281 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4282 | INSN_COND_BRANCH_DELAY
4283 | INSN_COND_BRANCH_LIKELY
)));
4287 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4288 struct frame_info
*frame
)
4290 CORE_ADDR pc
= get_frame_pc (frame
);
4291 gdb_byte buf
[MIPS_INSN32_SIZE
];
4293 /* There is no branch delay slot on MIPS16. */
4294 if (mips_pc_is_mips16 (pc
))
4297 if (!breakpoint_here_p (pc
+ 4))
4300 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4301 /* If error reading memory, guess that it is not a delayed
4304 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4307 /* To skip prologues, I use this predicate. Returns either PC itself
4308 if the code at PC does not look like a function prologue; otherwise
4309 returns an address that (if we're lucky) follows the prologue. If
4310 LENIENT, then we must skip everything which is involved in setting
4311 up the frame (it's OK to skip more, just so long as we don't skip
4312 anything which might clobber the registers which are being saved.
4313 We must skip more in the case where part of the prologue is in the
4314 delay slot of a non-prologue instruction). */
4317 mips_skip_prologue (CORE_ADDR pc
)
4320 CORE_ADDR func_addr
;
4322 /* See if we can determine the end of the prologue via the symbol table.
4323 If so, then return either PC, or the PC after the prologue, whichever
4325 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4327 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4328 if (post_prologue_pc
!= 0)
4329 return max (pc
, post_prologue_pc
);
4332 /* Can't determine prologue from the symbol table, need to examine
4335 /* Find an upper limit on the function prologue using the debug
4336 information. If the debug information could not be used to provide
4337 that bound, then use an arbitrary large number as the upper bound. */
4338 limit_pc
= skip_prologue_using_sal (pc
);
4340 limit_pc
= pc
+ 100; /* Magic. */
4342 if (mips_pc_is_mips16 (pc
))
4343 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4345 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4348 /* Root of all "set mips "/"show mips " commands. This will eventually be
4349 used for all MIPS-specific commands. */
4352 show_mips_command (char *args
, int from_tty
)
4354 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4358 set_mips_command (char *args
, int from_tty
)
4361 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4362 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4365 /* Commands to show/set the MIPS FPU type. */
4368 show_mipsfpu_command (char *args
, int from_tty
)
4371 switch (MIPS_FPU_TYPE
)
4373 case MIPS_FPU_SINGLE
:
4374 fpu
= "single-precision";
4376 case MIPS_FPU_DOUBLE
:
4377 fpu
= "double-precision";
4380 fpu
= "absent (none)";
4383 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4385 if (mips_fpu_type_auto
)
4387 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4391 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4396 set_mipsfpu_command (char *args
, int from_tty
)
4399 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4400 show_mipsfpu_command (args
, from_tty
);
4404 set_mipsfpu_single_command (char *args
, int from_tty
)
4406 struct gdbarch_info info
;
4407 gdbarch_info_init (&info
);
4408 mips_fpu_type
= MIPS_FPU_SINGLE
;
4409 mips_fpu_type_auto
= 0;
4410 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4411 instead of relying on globals. Doing that would let generic code
4412 handle the search for this specific architecture. */
4413 if (!gdbarch_update_p (info
))
4414 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4418 set_mipsfpu_double_command (char *args
, int from_tty
)
4420 struct gdbarch_info info
;
4421 gdbarch_info_init (&info
);
4422 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4423 mips_fpu_type_auto
= 0;
4424 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4425 instead of relying on globals. Doing that would let generic code
4426 handle the search for this specific architecture. */
4427 if (!gdbarch_update_p (info
))
4428 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4432 set_mipsfpu_none_command (char *args
, int from_tty
)
4434 struct gdbarch_info info
;
4435 gdbarch_info_init (&info
);
4436 mips_fpu_type
= MIPS_FPU_NONE
;
4437 mips_fpu_type_auto
= 0;
4438 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4439 instead of relying on globals. Doing that would let generic code
4440 handle the search for this specific architecture. */
4441 if (!gdbarch_update_p (info
))
4442 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4446 set_mipsfpu_auto_command (char *args
, int from_tty
)
4448 mips_fpu_type_auto
= 1;
4451 /* Attempt to identify the particular processor model by reading the
4452 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4453 the relevant processor still exists (it dates back to '94) and
4454 secondly this is not the way to do this. The processor type should
4455 be set by forcing an architecture change. */
4458 deprecated_mips_set_processor_regs_hack (void)
4460 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4463 regcache_cooked_read_unsigned (current_regcache
,
4464 MIPS_PRID_REGNUM
, &prid
);
4465 if ((prid
& ~0xf) == 0x700)
4466 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4469 /* Just like reinit_frame_cache, but with the right arguments to be
4470 callable as an sfunc. */
4473 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4474 struct cmd_list_element
*c
)
4476 reinit_frame_cache ();
4480 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4484 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4485 disassembler needs to be able to locally determine the ISA, and
4486 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4488 if (mips_pc_is_mips16 (memaddr
))
4489 info
->mach
= bfd_mach_mips16
;
4491 /* Round down the instruction address to the appropriate boundary. */
4492 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4494 /* Set the disassembler options. */
4495 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4497 /* Set up the disassembler info, so that we get the right
4498 register names from libopcodes. */
4499 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4500 info
->disassembler_options
= "gpr-names=n32";
4502 info
->disassembler_options
= "gpr-names=64";
4503 info
->flavour
= bfd_target_elf_flavour
;
4506 /* This string is not recognized explicitly by the disassembler,
4507 but it tells the disassembler to not try to guess the ABI from
4508 the bfd elf headers, such that, if the user overrides the ABI
4509 of a program linked as NewABI, the disassembly will follow the
4510 register naming conventions specified by the user. */
4511 info
->disassembler_options
= "gpr-names=32";
4513 /* Call the appropriate disassembler based on the target endian-ness. */
4514 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4515 return print_insn_big_mips (memaddr
, info
);
4517 return print_insn_little_mips (memaddr
, info
);
4520 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4521 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4522 It returns a pointer to a string of bytes that encode a breakpoint
4523 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4524 necessary) to point to the actual memory location where the breakpoint
4525 should be inserted. */
4527 static const gdb_byte
*
4528 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4530 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4532 if (mips_pc_is_mips16 (*pcptr
))
4534 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4535 *pcptr
= unmake_mips16_addr (*pcptr
);
4536 *lenptr
= sizeof (mips16_big_breakpoint
);
4537 return mips16_big_breakpoint
;
4541 /* The IDT board uses an unusual breakpoint value, and
4542 sometimes gets confused when it sees the usual MIPS
4543 breakpoint instruction. */
4544 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4545 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4546 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4548 *lenptr
= sizeof (big_breakpoint
);
4550 if (strcmp (target_shortname
, "mips") == 0)
4551 return idt_big_breakpoint
;
4552 else if (strcmp (target_shortname
, "ddb") == 0
4553 || strcmp (target_shortname
, "pmon") == 0
4554 || strcmp (target_shortname
, "lsi") == 0)
4555 return pmon_big_breakpoint
;
4557 return big_breakpoint
;
4562 if (mips_pc_is_mips16 (*pcptr
))
4564 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4565 *pcptr
= unmake_mips16_addr (*pcptr
);
4566 *lenptr
= sizeof (mips16_little_breakpoint
);
4567 return mips16_little_breakpoint
;
4571 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4572 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4573 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4575 *lenptr
= sizeof (little_breakpoint
);
4577 if (strcmp (target_shortname
, "mips") == 0)
4578 return idt_little_breakpoint
;
4579 else if (strcmp (target_shortname
, "ddb") == 0
4580 || strcmp (target_shortname
, "pmon") == 0
4581 || strcmp (target_shortname
, "lsi") == 0)
4582 return pmon_little_breakpoint
;
4584 return little_breakpoint
;
4589 /* If PC is in a mips16 call or return stub, return the address of the target
4590 PC, which is either the callee or the caller. There are several
4591 cases which must be handled:
4593 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4594 target PC is in $31 ($ra).
4595 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4596 and the target PC is in $2.
4597 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4598 before the jal instruction, this is effectively a call stub
4599 and the the target PC is in $2. Otherwise this is effectively
4600 a return stub and the target PC is in $18.
4602 See the source code for the stubs in gcc/config/mips/mips16.S for
4606 mips_skip_trampoline_code (CORE_ADDR pc
)
4609 CORE_ADDR start_addr
;
4611 /* Find the starting address and name of the function containing the PC. */
4612 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4615 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4616 target PC is in $31 ($ra). */
4617 if (strcmp (name
, "__mips16_ret_sf") == 0
4618 || strcmp (name
, "__mips16_ret_df") == 0)
4619 return read_signed_register (MIPS_RA_REGNUM
);
4621 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4623 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4624 and the target PC is in $2. */
4625 if (name
[19] >= '0' && name
[19] <= '9')
4626 return read_signed_register (2);
4628 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4629 before the jal instruction, this is effectively a call stub
4630 and the the target PC is in $2. Otherwise this is effectively
4631 a return stub and the target PC is in $18. */
4632 else if (name
[19] == 's' || name
[19] == 'd')
4634 if (pc
== start_addr
)
4636 /* Check if the target of the stub is a compiler-generated
4637 stub. Such a stub for a function bar might have a name
4638 like __fn_stub_bar, and might look like this:
4643 la $1,bar (becomes a lui/addiu pair)
4645 So scan down to the lui/addi and extract the target
4646 address from those two instructions. */
4648 CORE_ADDR target_pc
= read_signed_register (2);
4652 /* See if the name of the target function is __fn_stub_*. */
4653 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4656 if (strncmp (name
, "__fn_stub_", 10) != 0
4657 && strcmp (name
, "etext") != 0
4658 && strcmp (name
, "_etext") != 0)
4661 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4662 The limit on the search is arbitrarily set to 20
4663 instructions. FIXME. */
4664 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4666 inst
= mips_fetch_instruction (target_pc
);
4667 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4668 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4669 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4670 return pc
| (inst
& 0xffff); /* low word */
4673 /* Couldn't find the lui/addui pair, so return stub address. */
4677 /* This is the 'return' part of a call stub. The return
4678 address is in $r18. */
4679 return read_signed_register (18);
4682 return 0; /* not a stub */
4685 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4686 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4689 mips_stab_reg_to_regnum (int num
)
4692 if (num
>= 0 && num
< 32)
4694 else if (num
>= 38 && num
< 70)
4695 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4697 regnum
= mips_regnum (current_gdbarch
)->hi
;
4699 regnum
= mips_regnum (current_gdbarch
)->lo
;
4701 /* This will hopefully (eventually) provoke a warning. Should
4702 we be calling complaint() here? */
4703 return gdbarch_num_regs (current_gdbarch
)
4704 + gdbarch_num_pseudo_regs (current_gdbarch
);
4705 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4709 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4710 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4713 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4716 if (num
>= 0 && num
< 32)
4718 else if (num
>= 32 && num
< 64)
4719 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4721 regnum
= mips_regnum (current_gdbarch
)->hi
;
4723 regnum
= mips_regnum (current_gdbarch
)->lo
;
4725 /* This will hopefully (eventually) provoke a warning. Should we
4726 be calling complaint() here? */
4727 return gdbarch_num_regs (current_gdbarch
)
4728 + gdbarch_num_pseudo_regs (current_gdbarch
);
4729 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4733 mips_register_sim_regno (int regnum
)
4735 /* Only makes sense to supply raw registers. */
4736 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4737 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4738 decide if it is valid. Should instead define a standard sim/gdb
4739 register numbering scheme. */
4740 if (gdbarch_register_name (current_gdbarch
,
4742 (current_gdbarch
) + regnum
) != NULL
4743 && gdbarch_register_name (current_gdbarch
,
4745 (current_gdbarch
) + regnum
)[0] != '\0')
4748 return LEGACY_SIM_REGNO_IGNORE
;
4752 /* Convert an integer into an address. Extracting the value signed
4753 guarantees a correctly sign extended address. */
4756 mips_integer_to_address (struct gdbarch
*gdbarch
,
4757 struct type
*type
, const gdb_byte
*buf
)
4759 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4763 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4765 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4766 const char *name
= bfd_get_section_name (abfd
, sect
);
4768 if (*abip
!= MIPS_ABI_UNKNOWN
)
4771 if (strncmp (name
, ".mdebug.", 8) != 0)
4774 if (strcmp (name
, ".mdebug.abi32") == 0)
4775 *abip
= MIPS_ABI_O32
;
4776 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4777 *abip
= MIPS_ABI_N32
;
4778 else if (strcmp (name
, ".mdebug.abi64") == 0)
4779 *abip
= MIPS_ABI_N64
;
4780 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4781 *abip
= MIPS_ABI_O64
;
4782 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4783 *abip
= MIPS_ABI_EABI32
;
4784 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4785 *abip
= MIPS_ABI_EABI64
;
4787 warning (_("unsupported ABI %s."), name
+ 8);
4791 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4793 int *lbp
= (int *) obj
;
4794 const char *name
= bfd_get_section_name (abfd
, sect
);
4796 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4798 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4800 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4801 warning (_("unrecognized .gcc_compiled_longXX"));
4804 static enum mips_abi
4805 global_mips_abi (void)
4809 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4810 if (mips_abi_strings
[i
] == mips_abi_string
)
4811 return (enum mips_abi
) i
;
4813 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4817 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4819 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4821 if (tdesc_gp32
== NULL
)
4823 /* Create feature sets with the appropriate properties. The values
4824 are not important. */
4826 tdesc_gp32
= allocate_target_description ();
4827 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4829 tdesc_gp64
= allocate_target_description ();
4830 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4833 /* If the size matches the set of 32-bit or 64-bit integer registers,
4834 assume that's what we've got. */
4835 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4836 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4838 /* If the size matches the full set of registers GDB traditionally
4839 knows about, including floating point, for either 32-bit or
4840 64-bit, assume that's what we've got. */
4841 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4842 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4844 /* Otherwise we don't have a useful guess. */
4847 static struct value
*
4848 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
4850 const int *reg_p
= baton
;
4851 return value_of_register (*reg_p
, frame
);
4854 static struct gdbarch
*
4855 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4857 struct gdbarch
*gdbarch
;
4858 struct gdbarch_tdep
*tdep
;
4860 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4862 enum mips_fpu_type fpu_type
;
4863 struct tdesc_arch_data
*tdesc_data
= NULL
;
4865 /* Check any target description for validity. */
4866 if (tdesc_has_registers (info
.target_desc
))
4868 static const char *const mips_gprs
[] = {
4869 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4870 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4871 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4872 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4874 static const char *const mips_fprs
[] = {
4875 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
4876 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
4877 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
4878 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
4881 const struct tdesc_feature
*feature
;
4884 feature
= tdesc_find_feature (info
.target_desc
,
4885 "org.gnu.gdb.mips.cpu");
4886 if (feature
== NULL
)
4889 tdesc_data
= tdesc_data_alloc ();
4892 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
4893 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
4897 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4898 MIPS_EMBED_LO_REGNUM
, "lo");
4899 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4900 MIPS_EMBED_HI_REGNUM
, "hi");
4901 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4902 MIPS_EMBED_PC_REGNUM
, "pc");
4906 tdesc_data_cleanup (tdesc_data
);
4910 feature
= tdesc_find_feature (info
.target_desc
,
4911 "org.gnu.gdb.mips.cp0");
4912 if (feature
== NULL
)
4914 tdesc_data_cleanup (tdesc_data
);
4919 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4920 MIPS_EMBED_BADVADDR_REGNUM
,
4922 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4923 MIPS_PS_REGNUM
, "status");
4924 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4925 MIPS_EMBED_CAUSE_REGNUM
, "cause");
4929 tdesc_data_cleanup (tdesc_data
);
4933 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
4934 backend is not prepared for that, though. */
4935 feature
= tdesc_find_feature (info
.target_desc
,
4936 "org.gnu.gdb.mips.fpu");
4937 if (feature
== NULL
)
4939 tdesc_data_cleanup (tdesc_data
);
4944 for (i
= 0; i
< 32; i
++)
4945 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4946 i
+ MIPS_EMBED_FP0_REGNUM
,
4949 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4950 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
4951 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4952 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
4956 tdesc_data_cleanup (tdesc_data
);
4960 /* It would be nice to detect an attempt to use a 64-bit ABI
4961 when only 32-bit registers are provided. */
4964 /* First of all, extract the elf_flags, if available. */
4965 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4966 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4967 else if (arches
!= NULL
)
4968 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4972 fprintf_unfiltered (gdb_stdlog
,
4973 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4975 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4976 switch ((elf_flags
& EF_MIPS_ABI
))
4978 case E_MIPS_ABI_O32
:
4979 found_abi
= MIPS_ABI_O32
;
4981 case E_MIPS_ABI_O64
:
4982 found_abi
= MIPS_ABI_O64
;
4984 case E_MIPS_ABI_EABI32
:
4985 found_abi
= MIPS_ABI_EABI32
;
4987 case E_MIPS_ABI_EABI64
:
4988 found_abi
= MIPS_ABI_EABI64
;
4991 if ((elf_flags
& EF_MIPS_ABI2
))
4992 found_abi
= MIPS_ABI_N32
;
4994 found_abi
= MIPS_ABI_UNKNOWN
;
4998 /* GCC creates a pseudo-section whose name describes the ABI. */
4999 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5000 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5002 /* If we have no useful BFD information, use the ABI from the last
5003 MIPS architecture (if there is one). */
5004 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5005 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5007 /* Try the architecture for any hint of the correct ABI. */
5008 if (found_abi
== MIPS_ABI_UNKNOWN
5009 && info
.bfd_arch_info
!= NULL
5010 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5012 switch (info
.bfd_arch_info
->mach
)
5014 case bfd_mach_mips3900
:
5015 found_abi
= MIPS_ABI_EABI32
;
5017 case bfd_mach_mips4100
:
5018 case bfd_mach_mips5000
:
5019 found_abi
= MIPS_ABI_EABI64
;
5021 case bfd_mach_mips8000
:
5022 case bfd_mach_mips10000
:
5023 /* On Irix, ELF64 executables use the N64 ABI. The
5024 pseudo-sections which describe the ABI aren't present
5025 on IRIX. (Even for executables created by gcc.) */
5026 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5027 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5028 found_abi
= MIPS_ABI_N64
;
5030 found_abi
= MIPS_ABI_N32
;
5035 /* Default 64-bit objects to N64 instead of O32. */
5036 if (found_abi
== MIPS_ABI_UNKNOWN
5037 && info
.abfd
!= NULL
5038 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5039 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5040 found_abi
= MIPS_ABI_N64
;
5043 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5046 /* What has the user specified from the command line? */
5047 wanted_abi
= global_mips_abi ();
5049 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5052 /* Now that we have found what the ABI for this binary would be,
5053 check whether the user is overriding it. */
5054 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5055 mips_abi
= wanted_abi
;
5056 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5057 mips_abi
= found_abi
;
5059 mips_abi
= MIPS_ABI_O32
;
5061 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5064 /* Also used when doing an architecture lookup. */
5066 fprintf_unfiltered (gdb_stdlog
,
5067 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5068 mips64_transfers_32bit_regs_p
);
5070 /* Determine the MIPS FPU type. */
5071 if (!mips_fpu_type_auto
)
5072 fpu_type
= mips_fpu_type
;
5073 else if (info
.bfd_arch_info
!= NULL
5074 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5075 switch (info
.bfd_arch_info
->mach
)
5077 case bfd_mach_mips3900
:
5078 case bfd_mach_mips4100
:
5079 case bfd_mach_mips4111
:
5080 case bfd_mach_mips4120
:
5081 fpu_type
= MIPS_FPU_NONE
;
5083 case bfd_mach_mips4650
:
5084 fpu_type
= MIPS_FPU_SINGLE
;
5087 fpu_type
= MIPS_FPU_DOUBLE
;
5090 else if (arches
!= NULL
)
5091 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5093 fpu_type
= MIPS_FPU_DOUBLE
;
5095 fprintf_unfiltered (gdb_stdlog
,
5096 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5098 /* Check for blatant incompatibilities. */
5100 /* If we have only 32-bit registers, then we can't debug a 64-bit
5102 if (info
.target_desc
5103 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5104 && mips_abi
!= MIPS_ABI_EABI32
5105 && mips_abi
!= MIPS_ABI_O32
)
5107 if (tdesc_data
!= NULL
)
5108 tdesc_data_cleanup (tdesc_data
);
5112 /* try to find a pre-existing architecture */
5113 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5115 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5117 /* MIPS needs to be pedantic about which ABI the object is
5119 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5121 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5123 /* Need to be pedantic about which register virtual size is
5125 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5126 != mips64_transfers_32bit_regs_p
)
5128 /* Be pedantic about which FPU is selected. */
5129 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5132 if (tdesc_data
!= NULL
)
5133 tdesc_data_cleanup (tdesc_data
);
5134 return arches
->gdbarch
;
5137 /* Need a new architecture. Fill in a target specific vector. */
5138 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5139 gdbarch
= gdbarch_alloc (&info
, tdep
);
5140 tdep
->elf_flags
= elf_flags
;
5141 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5142 tdep
->found_abi
= found_abi
;
5143 tdep
->mips_abi
= mips_abi
;
5144 tdep
->mips_fpu_type
= fpu_type
;
5145 tdep
->register_size_valid_p
= 0;
5146 tdep
->register_size
= 0;
5148 if (info
.target_desc
)
5150 /* Some useful properties can be inferred from the target. */
5151 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5153 tdep
->register_size_valid_p
= 1;
5154 tdep
->register_size
= 4;
5156 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5158 tdep
->register_size_valid_p
= 1;
5159 tdep
->register_size
= 8;
5163 /* Initially set everything according to the default ABI/ISA. */
5164 set_gdbarch_short_bit (gdbarch
, 16);
5165 set_gdbarch_int_bit (gdbarch
, 32);
5166 set_gdbarch_float_bit (gdbarch
, 32);
5167 set_gdbarch_double_bit (gdbarch
, 64);
5168 set_gdbarch_long_double_bit (gdbarch
, 64);
5169 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5170 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5171 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5173 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5174 mips_elf_make_msymbol_special
);
5176 /* Fill in the OS dependant register numbers and names. */
5178 const char **reg_names
;
5179 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5180 struct mips_regnum
);
5181 if (tdesc_has_registers (info
.target_desc
))
5183 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5184 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5185 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5186 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5187 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5188 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5189 regnum
->fp_control_status
= 70;
5190 regnum
->fp_implementation_revision
= 71;
5191 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5194 else if (info
.osabi
== GDB_OSABI_IRIX
)
5199 regnum
->badvaddr
= 66;
5202 regnum
->fp_control_status
= 69;
5203 regnum
->fp_implementation_revision
= 70;
5205 reg_names
= mips_irix_reg_names
;
5209 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5210 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5211 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5212 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5213 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5214 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5215 regnum
->fp_control_status
= 70;
5216 regnum
->fp_implementation_revision
= 71;
5218 if (info
.bfd_arch_info
!= NULL
5219 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5220 reg_names
= mips_tx39_reg_names
;
5222 reg_names
= mips_generic_reg_names
;
5224 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5225 replaced by read_pc? */
5226 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5227 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5228 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5229 set_gdbarch_num_regs (gdbarch
, num_regs
);
5230 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5231 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5232 tdep
->mips_processor_reg_names
= reg_names
;
5233 tdep
->regnum
= regnum
;
5239 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5240 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5241 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5242 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5243 tdep
->default_mask_address_p
= 0;
5244 set_gdbarch_long_bit (gdbarch
, 32);
5245 set_gdbarch_ptr_bit (gdbarch
, 32);
5246 set_gdbarch_long_long_bit (gdbarch
, 64);
5249 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5250 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5251 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5252 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5253 tdep
->default_mask_address_p
= 0;
5254 set_gdbarch_long_bit (gdbarch
, 32);
5255 set_gdbarch_ptr_bit (gdbarch
, 32);
5256 set_gdbarch_long_long_bit (gdbarch
, 64);
5258 case MIPS_ABI_EABI32
:
5259 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5260 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5261 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5262 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5263 tdep
->default_mask_address_p
= 0;
5264 set_gdbarch_long_bit (gdbarch
, 32);
5265 set_gdbarch_ptr_bit (gdbarch
, 32);
5266 set_gdbarch_long_long_bit (gdbarch
, 64);
5268 case MIPS_ABI_EABI64
:
5269 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5270 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5271 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5272 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5273 tdep
->default_mask_address_p
= 0;
5274 set_gdbarch_long_bit (gdbarch
, 64);
5275 set_gdbarch_ptr_bit (gdbarch
, 64);
5276 set_gdbarch_long_long_bit (gdbarch
, 64);
5279 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5280 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5281 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5282 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5283 tdep
->default_mask_address_p
= 0;
5284 set_gdbarch_long_bit (gdbarch
, 32);
5285 set_gdbarch_ptr_bit (gdbarch
, 32);
5286 set_gdbarch_long_long_bit (gdbarch
, 64);
5287 set_gdbarch_long_double_bit (gdbarch
, 128);
5288 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5291 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5292 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5293 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5294 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5295 tdep
->default_mask_address_p
= 0;
5296 set_gdbarch_long_bit (gdbarch
, 64);
5297 set_gdbarch_ptr_bit (gdbarch
, 64);
5298 set_gdbarch_long_long_bit (gdbarch
, 64);
5299 set_gdbarch_long_double_bit (gdbarch
, 128);
5300 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5303 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5306 /* GCC creates a pseudo-section whose name specifies the size of
5307 longs, since -mlong32 or -mlong64 may be used independent of
5308 other options. How those options affect pointer sizes is ABI and
5309 architecture dependent, so use them to override the default sizes
5310 set by the ABI. This table shows the relationship between ABI,
5311 -mlongXX, and size of pointers:
5313 ABI -mlongXX ptr bits
5314 --- -------- --------
5328 Note that for o32 and eabi32, pointers are always 32 bits
5329 regardless of any -mlongXX option. For all others, pointers and
5330 longs are the same, as set by -mlongXX or set by defaults.
5333 if (info
.abfd
!= NULL
)
5337 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5340 set_gdbarch_long_bit (gdbarch
, long_bit
);
5344 case MIPS_ABI_EABI32
:
5349 case MIPS_ABI_EABI64
:
5350 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5353 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5358 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5359 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5362 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5363 flag in object files because to do so would make it impossible to
5364 link with libraries compiled without "-gp32". This is
5365 unnecessarily restrictive.
5367 We could solve this problem by adding "-gp32" multilibs to gcc,
5368 but to set this flag before gcc is built with such multilibs will
5369 break too many systems.''
5371 But even more unhelpfully, the default linker output target for
5372 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5373 for 64-bit programs - you need to change the ABI to change this,
5374 and not all gcc targets support that currently. Therefore using
5375 this flag to detect 32-bit mode would do the wrong thing given
5376 the current gcc - it would make GDB treat these 64-bit programs
5377 as 32-bit programs by default. */
5379 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5380 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5382 /* Add/remove bits from an address. The MIPS needs be careful to
5383 ensure that all 32 bit addresses are sign extended to 64 bits. */
5384 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5386 /* Unwind the frame. */
5387 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5388 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5389 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5391 /* Map debug register numbers onto internal register numbers. */
5392 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5393 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5394 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5395 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5396 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5397 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5398 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5399 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5401 /* MIPS version of CALL_DUMMY */
5403 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5404 replaced by a command, and all targets will default to on stack
5405 (regardless of the stack's execute status). */
5406 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5407 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5409 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5410 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5411 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5413 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5414 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5416 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5418 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5419 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5420 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5422 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5424 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5426 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5428 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5429 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5430 need to all be folded into the target vector. Since they are
5431 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5432 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5434 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5436 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5438 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5440 /* Virtual tables. */
5441 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5443 mips_register_g_packet_guesses (gdbarch
);
5445 /* Hook in OS ABI-specific overrides, if they have been registered. */
5446 info
.tdep_info
= (void *) tdesc_data
;
5447 gdbarch_init_osabi (info
, gdbarch
);
5449 /* Unwind the frame. */
5450 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5451 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5452 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5453 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5454 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5455 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5456 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5457 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5461 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5462 tdesc_use_registers (gdbarch
, tdesc_data
);
5464 /* Override the normal target description methods to handle our
5465 dual real and pseudo registers. */
5466 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5467 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5469 num_regs
= gdbarch_num_regs (gdbarch
);
5470 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5471 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5472 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5475 /* Add ABI-specific aliases for the registers. */
5476 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5477 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5478 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5479 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5481 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5482 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5483 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5485 /* Add some other standard aliases. */
5486 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5487 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5488 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5494 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5496 struct gdbarch_info info
;
5498 /* Force the architecture to update, and (if it's a MIPS architecture)
5499 mips_gdbarch_init will take care of the rest. */
5500 gdbarch_info_init (&info
);
5501 gdbarch_update_p (info
);
5504 /* Print out which MIPS ABI is in use. */
5507 show_mips_abi (struct ui_file
*file
,
5509 struct cmd_list_element
*ignored_cmd
,
5510 const char *ignored_value
)
5512 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5515 "The MIPS ABI is unknown because the current architecture "
5519 enum mips_abi global_abi
= global_mips_abi ();
5520 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5521 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5523 if (global_abi
== MIPS_ABI_UNKNOWN
)
5526 "The MIPS ABI is set automatically (currently \"%s\").\n",
5528 else if (global_abi
== actual_abi
)
5531 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5535 /* Probably shouldn't happen... */
5538 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5539 actual_abi_str
, mips_abi_strings
[global_abi
]);
5545 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5547 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5551 int ef_mips_32bitmode
;
5552 /* Determine the ISA. */
5553 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5571 /* Determine the size of a pointer. */
5572 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5573 fprintf_unfiltered (file
,
5574 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5576 fprintf_unfiltered (file
,
5577 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5579 fprintf_unfiltered (file
,
5580 "mips_dump_tdep: ef_mips_arch = %d\n",
5582 fprintf_unfiltered (file
,
5583 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5584 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5585 fprintf_unfiltered (file
,
5586 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5587 mips_mask_address_p (tdep
),
5588 tdep
->default_mask_address_p
);
5590 fprintf_unfiltered (file
,
5591 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5592 MIPS_DEFAULT_FPU_TYPE
,
5593 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5594 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5595 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5597 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5598 fprintf_unfiltered (file
,
5599 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5601 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5602 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5603 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5607 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5610 _initialize_mips_tdep (void)
5612 static struct cmd_list_element
*mipsfpulist
= NULL
;
5613 struct cmd_list_element
*c
;
5615 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5616 if (MIPS_ABI_LAST
+ 1
5617 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5618 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5620 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5622 mips_pdr_data
= register_objfile_data ();
5624 /* Add root prefix command for all "set mips"/"show mips" commands */
5625 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5626 _("Various MIPS specific commands."),
5627 &setmipscmdlist
, "set mips ", 0, &setlist
);
5629 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5630 _("Various MIPS specific commands."),
5631 &showmipscmdlist
, "show mips ", 0, &showlist
);
5633 /* Allow the user to override the ABI. */
5634 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5635 &mips_abi_string
, _("\
5636 Set the MIPS ABI used by this program."), _("\
5637 Show the MIPS ABI used by this program."), _("\
5638 This option can be set to one of:\n\
5639 auto - the default ABI associated with the current binary\n\
5648 &setmipscmdlist
, &showmipscmdlist
);
5650 /* Let the user turn off floating point and set the fence post for
5651 heuristic_proc_start. */
5653 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5654 _("Set use of MIPS floating-point coprocessor."),
5655 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5656 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5657 _("Select single-precision MIPS floating-point coprocessor."),
5659 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5660 _("Select double-precision MIPS floating-point coprocessor."),
5662 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5663 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5664 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5665 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5666 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5667 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5668 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5669 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5670 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5671 _("Select MIPS floating-point coprocessor automatically."),
5673 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5674 _("Show current use of MIPS floating-point coprocessor target."),
5677 /* We really would like to have both "0" and "unlimited" work, but
5678 command.c doesn't deal with that. So make it a var_zinteger
5679 because the user can always use "999999" or some such for unlimited. */
5680 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5681 &heuristic_fence_post
, _("\
5682 Set the distance searched for the start of a function."), _("\
5683 Show the distance searched for the start of a function."), _("\
5684 If you are debugging a stripped executable, GDB needs to search through the\n\
5685 program for the start of a function. This command sets the distance of the\n\
5686 search. The only need to set it is when debugging a stripped executable."),
5687 reinit_frame_cache_sfunc
,
5688 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5689 &setlist
, &showlist
);
5691 /* Allow the user to control whether the upper bits of 64-bit
5692 addresses should be zeroed. */
5693 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5694 &mask_address_var
, _("\
5695 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5696 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5697 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5698 allow GDB to determine the correct value."),
5699 NULL
, show_mask_address
,
5700 &setmipscmdlist
, &showmipscmdlist
);
5702 /* Allow the user to control the size of 32 bit registers within the
5703 raw remote packet. */
5704 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5705 &mips64_transfers_32bit_regs_p
, _("\
5706 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5708 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5710 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5711 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5712 64 bits for others. Use \"off\" to disable compatibility mode"),
5713 set_mips64_transfers_32bit_regs
,
5714 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5715 &setlist
, &showlist
);
5717 /* Debug this files internals. */
5718 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5720 Set mips debugging."), _("\
5721 Show mips debugging."), _("\
5722 When non-zero, mips specific debugging is enabled."),
5724 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5725 &setdebuglist
, &showdebuglist
);