1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Decode a MIPS32 instruction that saves a register in the stack, and
949 set the appropriate bit in the general register mask or float register mask
950 to indicate which register is saved. This is a helper function
951 for mips_find_saved_regs. */
954 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
955 unsigned long *float_mask
)
959 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
960 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
961 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
963 /* It might be possible to use the instruction to
964 find the offset, rather than the code below which
965 is based on things being in a certain order in the
966 frame, but figuring out what the instruction's offset
967 is relative to might be a little tricky. */
968 reg
= (inst
& 0x001f0000) >> 16;
969 *gen_mask
|= (1 << reg
);
971 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
972 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
973 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
976 reg
= ((inst
& 0x001f0000) >> 16);
977 *float_mask
|= (1 << reg
);
981 /* Decode a MIPS16 instruction that saves a register in the stack, and
982 set the appropriate bit in the general register or float register mask
983 to indicate which register is saved. This is a helper function
984 for mips_find_saved_regs. */
987 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
989 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
991 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
992 *gen_mask
|= (1 << reg
);
994 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
996 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
997 *gen_mask
|= (1 << reg
);
999 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1000 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1001 *gen_mask
|= (1 << RA_REGNUM
);
1005 /* Fetch and return instruction from the specified location. If the PC
1006 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1009 mips_fetch_instruction (CORE_ADDR addr
)
1011 char buf
[MIPS_INSTLEN
];
1015 if (pc_is_mips16 (addr
))
1017 instlen
= MIPS16_INSTLEN
;
1018 addr
= unmake_mips16_addr (addr
);
1021 instlen
= MIPS_INSTLEN
;
1022 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1024 memory_error (status
, addr
);
1025 return extract_unsigned_integer (buf
, instlen
);
1029 mips16_fetch_instruction (CORE_ADDR addr
)
1031 char buf
[MIPS_INSTLEN
];
1035 instlen
= MIPS16_INSTLEN
;
1036 addr
= unmake_mips16_addr (addr
);
1037 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1039 memory_error (status
, addr
);
1040 return extract_unsigned_integer (buf
, instlen
);
1044 mips32_fetch_instruction (CORE_ADDR addr
)
1046 char buf
[MIPS_INSTLEN
];
1049 instlen
= MIPS_INSTLEN
;
1050 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1052 memory_error (status
, addr
);
1053 return extract_unsigned_integer (buf
, instlen
);
1057 /* These the fields of 32 bit mips instructions */
1058 #define mips32_op(x) (x >> 26)
1059 #define itype_op(x) (x >> 26)
1060 #define itype_rs(x) ((x >> 21) & 0x1f)
1061 #define itype_rt(x) ((x >> 16) & 0x1f)
1062 #define itype_immediate(x) (x & 0xffff)
1064 #define jtype_op(x) (x >> 26)
1065 #define jtype_target(x) (x & 0x03ffffff)
1067 #define rtype_op(x) (x >> 26)
1068 #define rtype_rs(x) ((x >> 21) & 0x1f)
1069 #define rtype_rt(x) ((x >> 16) & 0x1f)
1070 #define rtype_rd(x) ((x >> 11) & 0x1f)
1071 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1072 #define rtype_funct(x) (x & 0x3f)
1075 mips32_relative_offset (unsigned long inst
)
1078 x
= itype_immediate (inst
);
1079 if (x
& 0x8000) /* sign bit set */
1081 x
|= 0xffff0000; /* sign extension */
1087 /* Determine whate to set a single step breakpoint while considering
1088 branch prediction */
1090 mips32_next_pc (CORE_ADDR pc
)
1094 inst
= mips_fetch_instruction (pc
);
1095 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1097 if (itype_op (inst
) >> 2 == 5)
1098 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1100 op
= (itype_op (inst
) & 0x03);
1110 goto greater_branch
;
1115 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1116 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1118 int tf
= itype_rt (inst
) & 0x01;
1119 int cnum
= itype_rt (inst
) >> 2;
1121 read_signed_register (mips_regnum (current_gdbarch
)->
1123 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1125 if (((cond
>> cnum
) & 0x01) == tf
)
1126 pc
+= mips32_relative_offset (inst
) + 4;
1131 pc
+= 4; /* Not a branch, next instruction is easy */
1134 { /* This gets way messy */
1136 /* Further subdivide into SPECIAL, REGIMM and other */
1137 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1139 case 0: /* SPECIAL */
1140 op
= rtype_funct (inst
);
1145 /* Set PC to that address */
1146 pc
= read_signed_register (rtype_rs (inst
));
1152 break; /* end SPECIAL */
1153 case 1: /* REGIMM */
1155 op
= itype_rt (inst
); /* branch condition */
1160 case 16: /* BLTZAL */
1161 case 18: /* BLTZALL */
1163 if (read_signed_register (itype_rs (inst
)) < 0)
1164 pc
+= mips32_relative_offset (inst
) + 4;
1166 pc
+= 8; /* after the delay slot */
1170 case 17: /* BGEZAL */
1171 case 19: /* BGEZALL */
1172 if (read_signed_register (itype_rs (inst
)) >= 0)
1173 pc
+= mips32_relative_offset (inst
) + 4;
1175 pc
+= 8; /* after the delay slot */
1177 /* All of the other instructions in the REGIMM category */
1182 break; /* end REGIMM */
1187 reg
= jtype_target (inst
) << 2;
1188 /* Upper four bits get never changed... */
1189 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1192 /* FIXME case JALX : */
1195 reg
= jtype_target (inst
) << 2;
1196 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1197 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1199 break; /* The new PC will be alternate mode */
1200 case 4: /* BEQ, BEQL */
1202 if (read_signed_register (itype_rs (inst
)) ==
1203 read_signed_register (itype_rt (inst
)))
1204 pc
+= mips32_relative_offset (inst
) + 4;
1208 case 5: /* BNE, BNEL */
1210 if (read_signed_register (itype_rs (inst
)) !=
1211 read_signed_register (itype_rt (inst
)))
1212 pc
+= mips32_relative_offset (inst
) + 4;
1216 case 6: /* BLEZ, BLEZL */
1217 if (read_signed_register (itype_rs (inst
) <= 0))
1218 pc
+= mips32_relative_offset (inst
) + 4;
1224 greater_branch
: /* BGTZ, BGTZL */
1225 if (read_signed_register (itype_rs (inst
) > 0))
1226 pc
+= mips32_relative_offset (inst
) + 4;
1233 } /* mips32_next_pc */
1235 /* Decoding the next place to set a breakpoint is irregular for the
1236 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1237 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1238 We dont want to set a single step instruction on the extend instruction
1242 /* Lots of mips16 instruction formats */
1243 /* Predicting jumps requires itype,ritype,i8type
1244 and their extensions extItype,extritype,extI8type
1246 enum mips16_inst_fmts
1248 itype
, /* 0 immediate 5,10 */
1249 ritype
, /* 1 5,3,8 */
1250 rrtype
, /* 2 5,3,3,5 */
1251 rritype
, /* 3 5,3,3,5 */
1252 rrrtype
, /* 4 5,3,3,3,2 */
1253 rriatype
, /* 5 5,3,3,1,4 */
1254 shifttype
, /* 6 5,3,3,3,2 */
1255 i8type
, /* 7 5,3,8 */
1256 i8movtype
, /* 8 5,3,3,5 */
1257 i8mov32rtype
, /* 9 5,3,5,3 */
1258 i64type
, /* 10 5,3,8 */
1259 ri64type
, /* 11 5,3,3,5 */
1260 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1261 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1262 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1263 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1264 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1265 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1266 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1267 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1268 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1269 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1271 /* I am heaping all the fields of the formats into one structure and
1272 then, only the fields which are involved in instruction extension */
1276 unsigned int regx
; /* Function in i8 type */
1281 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1282 for the bits which make up the immediatate extension. */
1285 extended_offset (unsigned int extension
)
1288 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1290 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1292 value
|= extension
& 0x01f; /* extract 4:0 */
1296 /* Only call this function if you know that this is an extendable
1297 instruction, It wont malfunction, but why make excess remote memory references?
1298 If the immediate operands get sign extended or somthing, do it after
1299 the extension is performed.
1301 /* FIXME: Every one of these cases needs to worry about sign extension
1302 when the offset is to be used in relative addressing */
1306 fetch_mips_16 (CORE_ADDR pc
)
1309 pc
&= 0xfffffffe; /* clear the low order bit */
1310 target_read_memory (pc
, buf
, 2);
1311 return extract_unsigned_integer (buf
, 2);
1315 unpack_mips16 (CORE_ADDR pc
,
1316 unsigned int extension
,
1318 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1323 switch (insn_format
)
1330 value
= extended_offset (extension
);
1331 value
= value
<< 11; /* rom for the original value */
1332 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1336 value
= inst
& 0x7ff;
1337 /* FIXME : Consider sign extension */
1346 { /* A register identifier and an offset */
1347 /* Most of the fields are the same as I type but the
1348 immediate value is of a different length */
1352 value
= extended_offset (extension
);
1353 value
= value
<< 8; /* from the original instruction */
1354 value
|= inst
& 0xff; /* eleven bits from instruction */
1355 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1356 if (value
& 0x4000) /* test the sign bit , bit 26 */
1358 value
&= ~0x3fff; /* remove the sign bit */
1364 value
= inst
& 0xff; /* 8 bits */
1365 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1366 /* FIXME: Do sign extension , this format needs it */
1367 if (value
& 0x80) /* THIS CONFUSES ME */
1369 value
&= 0xef; /* remove the sign bit */
1379 unsigned long value
;
1380 unsigned int nexthalf
;
1381 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1382 value
= value
<< 16;
1383 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1391 internal_error (__FILE__
, __LINE__
, "bad switch");
1393 upk
->offset
= offset
;
1400 add_offset_16 (CORE_ADDR pc
, int offset
)
1402 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1406 extended_mips16_next_pc (CORE_ADDR pc
,
1407 unsigned int extension
, unsigned int insn
)
1409 int op
= (insn
>> 11);
1412 case 2: /* Branch */
1415 struct upk_mips16 upk
;
1416 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1417 offset
= upk
.offset
;
1423 pc
+= (offset
<< 1) + 2;
1426 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1428 struct upk_mips16 upk
;
1429 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1430 pc
= add_offset_16 (pc
, upk
.offset
);
1431 if ((insn
>> 10) & 0x01) /* Exchange mode */
1432 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1439 struct upk_mips16 upk
;
1441 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1442 reg
= read_signed_register (upk
.regx
);
1444 pc
+= (upk
.offset
<< 1) + 2;
1451 struct upk_mips16 upk
;
1453 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1454 reg
= read_signed_register (upk
.regx
);
1456 pc
+= (upk
.offset
<< 1) + 2;
1461 case 12: /* I8 Formats btez btnez */
1463 struct upk_mips16 upk
;
1465 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1466 /* upk.regx contains the opcode */
1467 reg
= read_signed_register (24); /* Test register is 24 */
1468 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1469 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1470 /* pc = add_offset_16(pc,upk.offset) ; */
1471 pc
+= (upk
.offset
<< 1) + 2;
1476 case 29: /* RR Formats JR, JALR, JALR-RA */
1478 struct upk_mips16 upk
;
1479 /* upk.fmt = rrtype; */
1484 upk
.regx
= (insn
>> 8) & 0x07;
1485 upk
.regy
= (insn
>> 5) & 0x07;
1493 break; /* Function return instruction */
1499 break; /* BOGUS Guess */
1501 pc
= read_signed_register (reg
);
1508 /* This is an instruction extension. Fetch the real instruction
1509 (which follows the extension) and decode things based on
1513 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1526 mips16_next_pc (CORE_ADDR pc
)
1528 unsigned int insn
= fetch_mips_16 (pc
);
1529 return extended_mips16_next_pc (pc
, 0, insn
);
1532 /* The mips_next_pc function supports single_step when the remote
1533 target monitor or stub is not developed enough to do a single_step.
1534 It works by decoding the current instruction and predicting where a
1535 branch will go. This isnt hard because all the data is available.
1536 The MIPS32 and MIPS16 variants are quite different */
1538 mips_next_pc (CORE_ADDR pc
)
1541 return mips16_next_pc (pc
);
1543 return mips32_next_pc (pc
);
1546 struct mips_frame_cache
1549 struct trad_frame_saved_reg
*saved_regs
;
1553 static struct mips_frame_cache
*
1554 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1556 CORE_ADDR startaddr
= 0;
1557 mips_extra_func_info_t proc_desc
;
1558 struct mips_frame_cache
*cache
;
1559 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1560 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1561 /* r0 bit means kernel trap */
1563 /* What registers have been saved? Bitmasks. */
1564 unsigned long gen_mask
, float_mask
;
1566 if ((*this_cache
) != NULL
)
1567 return (*this_cache
);
1568 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1569 (*this_cache
) = cache
;
1570 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1572 /* Get the mdebug proc descriptor. */
1573 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1575 /* Must be true. This is only called when the sniffer detected a
1577 gdb_assert (proc_desc
!= NULL
);
1579 /* Extract the frame's base. */
1580 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1581 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1583 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1584 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1585 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1587 /* Must be true. The in_prologue case is left for the heuristic
1588 unwinder. This is always used on kernel traps. */
1589 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1592 /* Fill in the offsets for the registers which gen_mask says were
1595 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1598 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1599 if (gen_mask
& 0x80000000)
1601 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1602 reg_position
-= mips_abi_regsize (gdbarch
);
1606 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1607 order of that normally used by gcc. Therefore, we have to fetch
1608 the first instruction of the function, and if it's an entry
1609 instruction that saves $s0 or $s1, correct their saved addresses. */
1610 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1612 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1613 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1617 int sreg_count
= (inst
>> 6) & 3;
1619 /* Check if the ra register was pushed on the stack. */
1620 CORE_ADDR reg_position
= (cache
->base
1621 + PROC_REG_OFFSET (proc_desc
));
1623 reg_position
-= mips_abi_regsize (gdbarch
);
1625 /* Check if the s0 and s1 registers were pushed on the
1627 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1629 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1631 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1632 reg_position
-= mips_abi_regsize (gdbarch
);
1637 /* Fill in the offsets for the registers which float_mask says were
1640 CORE_ADDR reg_position
= (cache
->base
1641 + PROC_FREG_OFFSET (proc_desc
));
1643 /* Fill in the offsets for the float registers which float_mask
1645 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1646 if (float_mask
& 0x80000000)
1648 if (mips_abi_regsize (gdbarch
) == 4
1649 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1651 /* On a big endian 32 bit ABI, floating point registers
1652 are paired to form doubles such that the most
1653 significant part is in $f[N+1] and the least
1654 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1655 registers are also spilled as a pair and stored as a
1658 When little-endian the least significant part is
1659 stored first leading to the memory order $f[N] and
1662 Unfortunately, when big-endian the most significant
1663 part of the double is stored first, and the least
1664 significant is stored second. This leads to the
1665 registers being ordered in memory as firt $f[N+1] and
1668 For the big-endian case make certain that the
1669 addresses point at the correct (swapped) locations
1670 $f[N] and $f[N+1] pair (keep in mind that
1671 reg_position is decremented each time through the
1674 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1675 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1677 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1678 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1681 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1682 .addr
= reg_position
;
1683 reg_position
-= mips_abi_regsize (gdbarch
);
1686 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1687 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1690 /* SP_REGNUM, contains the value and not the address. */
1691 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1693 return (*this_cache
);
1697 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1698 struct frame_id
*this_id
)
1700 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1702 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1706 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1708 int regnum
, int *optimizedp
,
1709 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1710 int *realnump
, void *valuep
)
1712 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1714 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1715 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1718 static const struct frame_unwind mips_mdebug_frame_unwind
=
1721 mips_mdebug_frame_this_id
,
1722 mips_mdebug_frame_prev_register
1725 static const struct frame_unwind
*
1726 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1728 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1729 CORE_ADDR startaddr
= 0;
1730 mips_extra_func_info_t proc_desc
;
1733 /* Only use the mdebug frame unwinder on mdebug frames where all the
1734 registers have been saved. Leave hard cases such as no mdebug or
1735 in prologue for the heuristic unwinders. */
1737 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1738 if (proc_desc
== NULL
)
1741 /* Not sure exactly what kernel_trap means, but if it means the
1742 kernel saves the registers without a prologue doing it, we better
1743 not examine the prologue to see whether registers have been saved
1745 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1747 return &mips_mdebug_frame_unwind
;
1749 /* In any frame other than the innermost or a frame interrupted by a
1750 signal, we assume that all registers have been saved. This
1751 assumes that all register saves in a function happen before the
1752 first function call. */
1753 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1754 return &mips_mdebug_frame_unwind
;
1760 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1763 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1768 static const struct frame_base mips_mdebug_frame_base
= {
1769 &mips_mdebug_frame_unwind
,
1770 mips_mdebug_frame_base_address
,
1771 mips_mdebug_frame_base_address
,
1772 mips_mdebug_frame_base_address
1775 static const struct frame_base
*
1776 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1778 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1779 return &mips_mdebug_frame_base
;
1784 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1785 Procedures that use the 32-bit instruction set are handled by the
1786 mips_insn32 unwinder. */
1788 static struct mips_frame_cache
*
1789 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1791 mips_extra_func_info_t proc_desc
;
1792 struct mips_frame_cache
*cache
;
1793 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1795 /* r0 bit means kernel trap */
1797 /* What registers have been saved? Bitmasks. */
1798 unsigned long gen_mask
, float_mask
;
1800 if ((*this_cache
) != NULL
)
1801 return (*this_cache
);
1802 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1803 (*this_cache
) = cache
;
1804 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1806 /* Synthesize a proc descriptor. */
1808 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1809 CORE_ADDR start_addr
;
1811 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1812 if (start_addr
== 0)
1813 start_addr
= heuristic_proc_start (pc
);
1816 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1818 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
1822 /* Extract the frame's base. */
1823 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1824 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1826 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1827 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1828 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1830 /* In any frame other than the innermost or a frame interrupted by a
1831 signal, we assume that all registers have been saved. This
1832 assumes that all register saves in a function happen before the
1833 first function call. */
1834 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1835 /* Not sure exactly what kernel_trap means, but if it means the
1836 kernel saves the registers without a prologue doing it, we
1837 better not examine the prologue to see whether registers
1838 have been saved yet. */
1841 /* We need to figure out whether the registers that the
1842 proc_desc claims are saved have been saved yet. */
1846 /* Bitmasks; set if we have found a save for the register. */
1847 unsigned long gen_save_found
= 0;
1848 unsigned long float_save_found
= 0;
1851 /* If the address is odd, assume this is MIPS16 code. */
1852 addr
= PROC_LOW_ADDR (proc_desc
);
1853 mips16
= pc_is_mips16 (addr
);
1855 /* Scan through this function's instructions preceding the
1856 current PC, and look for those that save registers. */
1857 while (addr
< frame_pc_unwind (next_frame
))
1861 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1863 addr
+= MIPS16_INSTLEN
;
1867 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1868 &gen_save_found
, &float_save_found
);
1869 addr
+= MIPS_INSTLEN
;
1872 gen_mask
= gen_save_found
;
1873 float_mask
= float_save_found
;
1876 /* Fill in the offsets for the registers which gen_mask says were
1879 CORE_ADDR reg_position
= (cache
->base
1880 + PROC_REG_OFFSET (proc_desc
));
1882 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1883 if (gen_mask
& 0x80000000)
1885 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1886 reg_position
-= mips_abi_regsize (gdbarch
);
1890 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1891 order of that normally used by gcc. Therefore, we have to fetch
1892 the first instruction of the function, and if it's an entry
1893 instruction that saves $s0 or $s1, correct their saved addresses. */
1894 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1896 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1897 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1901 int sreg_count
= (inst
>> 6) & 3;
1903 /* Check if the ra register was pushed on the stack. */
1904 CORE_ADDR reg_position
= (cache
->base
1905 + PROC_REG_OFFSET (proc_desc
));
1907 reg_position
-= mips_abi_regsize (gdbarch
);
1909 /* Check if the s0 and s1 registers were pushed on the
1911 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1913 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1915 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1916 reg_position
-= mips_abi_regsize (gdbarch
);
1921 /* Fill in the offsets for the registers which float_mask says were
1924 CORE_ADDR reg_position
= (cache
->base
1925 + PROC_FREG_OFFSET (proc_desc
));
1927 /* Fill in the offsets for the float registers which float_mask
1929 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1930 if (float_mask
& 0x80000000)
1932 if (mips_abi_regsize (gdbarch
) == 4
1933 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1935 /* On a big endian 32 bit ABI, floating point registers
1936 are paired to form doubles such that the most
1937 significant part is in $f[N+1] and the least
1938 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1939 registers are also spilled as a pair and stored as a
1942 When little-endian the least significant part is
1943 stored first leading to the memory order $f[N] and
1946 Unfortunately, when big-endian the most significant
1947 part of the double is stored first, and the least
1948 significant is stored second. This leads to the
1949 registers being ordered in memory as firt $f[N+1] and
1952 For the big-endian case make certain that the
1953 addresses point at the correct (swapped) locations
1954 $f[N] and $f[N+1] pair (keep in mind that
1955 reg_position is decremented each time through the
1958 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1959 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1961 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1962 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1965 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1966 .addr
= reg_position
;
1967 reg_position
-= mips_abi_regsize (gdbarch
);
1970 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1971 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1974 /* SP_REGNUM, contains the value and not the address. */
1975 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1977 return (*this_cache
);
1981 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1982 struct frame_id
*this_id
)
1984 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1986 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1990 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1992 int regnum
, int *optimizedp
,
1993 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1994 int *realnump
, void *valuep
)
1996 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1998 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1999 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2002 static const struct frame_unwind mips_insn16_frame_unwind
=
2005 mips_insn16_frame_this_id
,
2006 mips_insn16_frame_prev_register
2009 static const struct frame_unwind
*
2010 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2012 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2013 if (pc_is_mips16 (pc
))
2014 return &mips_insn16_frame_unwind
;
2019 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2022 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2027 static const struct frame_base mips_insn16_frame_base
=
2029 &mips_insn16_frame_unwind
,
2030 mips_insn16_frame_base_address
,
2031 mips_insn16_frame_base_address
,
2032 mips_insn16_frame_base_address
2035 static const struct frame_base
*
2036 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2038 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2039 return &mips_insn16_frame_base
;
2044 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2045 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2046 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2049 static struct mips_frame_cache
*
2050 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2052 mips_extra_func_info_t proc_desc
;
2053 struct mips_frame_cache
*cache
;
2054 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2056 /* r0 bit means kernel trap */
2058 /* What registers have been saved? Bitmasks. */
2059 unsigned long gen_mask
, float_mask
;
2061 if ((*this_cache
) != NULL
)
2062 return (*this_cache
);
2063 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2064 (*this_cache
) = cache
;
2065 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2067 /* Synthesize a proc descriptor. */
2069 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2070 CORE_ADDR start_addr
;
2072 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2073 if (start_addr
== 0)
2074 start_addr
= heuristic_proc_start (pc
);
2077 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
2079 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
2083 if (proc_desc
== NULL
)
2084 /* I'm not sure how/whether this can happen. Normally when we
2085 can't find a proc_desc, we "synthesize" one using
2086 heuristic_proc_desc and set the saved_regs right away. */
2089 /* Extract the frame's base. */
2090 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2091 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2093 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2094 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2095 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2097 /* In any frame other than the innermost or a frame interrupted by a
2098 signal, we assume that all registers have been saved. This
2099 assumes that all register saves in a function happen before the
2100 first function call. */
2101 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2102 /* Not sure exactly what kernel_trap means, but if it means the
2103 kernel saves the registers without a prologue doing it, we
2104 better not examine the prologue to see whether registers
2105 have been saved yet. */
2108 /* We need to figure out whether the registers that the
2109 proc_desc claims are saved have been saved yet. */
2113 /* Bitmasks; set if we have found a save for the register. */
2114 unsigned long gen_save_found
= 0;
2115 unsigned long float_save_found
= 0;
2117 addr
= PROC_LOW_ADDR (proc_desc
);
2119 /* Scan through this function's instructions preceding the
2120 current PC, and look for those that save registers. */
2121 while (addr
< frame_pc_unwind (next_frame
))
2123 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2124 &gen_save_found
, &float_save_found
);
2125 addr
+= MIPS_INSTLEN
;
2127 gen_mask
= gen_save_found
;
2128 float_mask
= float_save_found
;
2131 /* Fill in the offsets for the registers which gen_mask says were
2134 CORE_ADDR reg_position
= (cache
->base
2135 + PROC_REG_OFFSET (proc_desc
));
2137 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2138 if (gen_mask
& 0x80000000)
2140 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2141 reg_position
-= mips_abi_regsize (gdbarch
);
2145 /* Fill in the offsets for the registers which float_mask says were
2148 CORE_ADDR reg_position
= (cache
->base
+ PROC_FREG_OFFSET (proc_desc
));
2151 /* Fill in the offsets for the float registers which float_mask
2153 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2154 if (float_mask
& 0x80000000)
2157 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
;
2159 if (mips_abi_regsize (gdbarch
) == 4
2160 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2162 /* On a big endian 32 bit ABI, floating point registers
2163 are paired to form doubles such that the most
2164 significant part is in $f[N+1] and the least
2165 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2166 registers are also spilled as a pair and stored as a
2169 When little-endian the least significant part is
2170 stored first leading to the memory order $f[N] and
2173 Unfortunately, when big-endian the most significant
2174 part of the double is stored first, and the least
2175 significant is stored second. This leads to the
2176 registers being ordered in memory as firt $f[N+1] and
2179 For the big-endian case make certain that the
2180 addresses point at the correct (swapped) locations
2181 $f[N] and $f[N+1] pair (keep in mind that
2182 reg_position is decremented each time through the
2185 cache
->saved_regs
[regno
].addr
=
2186 reg_position
- mips_abi_regsize (gdbarch
);
2188 cache
->saved_regs
[regno
].addr
=
2189 reg_position
+ mips_abi_regsize (gdbarch
);
2192 cache
->saved_regs
[regno
].addr
= reg_position
;
2193 reg_position
-= mips_abi_regsize (gdbarch
);
2196 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2197 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2200 /* SP_REGNUM, contains the value and not the address. */
2201 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2203 return (*this_cache
);
2207 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2208 struct frame_id
*this_id
)
2210 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2212 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2216 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2218 int regnum
, int *optimizedp
,
2219 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2220 int *realnump
, void *valuep
)
2222 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2224 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2225 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2228 static const struct frame_unwind mips_insn32_frame_unwind
=
2231 mips_insn32_frame_this_id
,
2232 mips_insn32_frame_prev_register
2235 static const struct frame_unwind
*
2236 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2238 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2239 if (! pc_is_mips16 (pc
))
2240 return &mips_insn32_frame_unwind
;
2245 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2248 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2253 static const struct frame_base mips_insn32_frame_base
=
2255 &mips_insn32_frame_unwind
,
2256 mips_insn32_frame_base_address
,
2257 mips_insn32_frame_base_address
,
2258 mips_insn32_frame_base_address
2261 static const struct frame_base
*
2262 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2264 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2265 return &mips_insn32_frame_base
;
2270 static struct trad_frame_cache
*
2271 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2274 CORE_ADDR start_addr
;
2275 CORE_ADDR stack_addr
;
2276 struct trad_frame_cache
*this_trad_cache
;
2278 if ((*this_cache
) != NULL
)
2279 return (*this_cache
);
2280 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2281 (*this_cache
) = this_trad_cache
;
2283 /* The return address is in the link register. */
2284 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2286 /* Frame ID, since it's a frameless / stackless function, no stack
2287 space is allocated and SP on entry is the current SP. */
2288 pc
= frame_pc_unwind (next_frame
);
2289 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2290 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2291 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2293 /* Assume that the frame's base is the same as the
2295 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2297 return this_trad_cache
;
2301 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2302 struct frame_id
*this_id
)
2304 struct trad_frame_cache
*this_trad_cache
2305 = mips_stub_frame_cache (next_frame
, this_cache
);
2306 trad_frame_get_id (this_trad_cache
, this_id
);
2310 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2312 int regnum
, int *optimizedp
,
2313 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2314 int *realnump
, void *valuep
)
2316 struct trad_frame_cache
*this_trad_cache
2317 = mips_stub_frame_cache (next_frame
, this_cache
);
2318 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2319 lvalp
, addrp
, realnump
, valuep
);
2322 static const struct frame_unwind mips_stub_frame_unwind
=
2325 mips_stub_frame_this_id
,
2326 mips_stub_frame_prev_register
2329 static const struct frame_unwind
*
2330 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2332 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2333 if (in_plt_section (pc
, NULL
))
2334 return &mips_stub_frame_unwind
;
2340 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2343 struct trad_frame_cache
*this_trad_cache
2344 = mips_stub_frame_cache (next_frame
, this_cache
);
2345 return trad_frame_get_this_base (this_trad_cache
);
2348 static const struct frame_base mips_stub_frame_base
=
2350 &mips_stub_frame_unwind
,
2351 mips_stub_frame_base_address
,
2352 mips_stub_frame_base_address
,
2353 mips_stub_frame_base_address
2356 static const struct frame_base
*
2357 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2359 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2360 return &mips_stub_frame_base
;
2366 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2368 /* Always a pseudo. */
2369 gdb_assert (regno
>= NUM_REGS
);
2373 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2376 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2377 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2378 In fact, it is so special that it can even only be fetched
2379 using a raw register number! Once this code as been converted
2380 to frame-unwind the problem goes away. */
2381 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2383 return frame_unwind_register_signed (fi
, regno
);
2387 /* mips_addr_bits_remove - remove useless address bits */
2390 mips_addr_bits_remove (CORE_ADDR addr
)
2392 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2393 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2394 /* This hack is a work-around for existing boards using PMON, the
2395 simulator, and any other 64-bit targets that doesn't have true
2396 64-bit addressing. On these targets, the upper 32 bits of
2397 addresses are ignored by the hardware. Thus, the PC or SP are
2398 likely to have been sign extended to all 1s by instruction
2399 sequences that load 32-bit addresses. For example, a typical
2400 piece of code that loads an address is this:
2402 lui $r2, <upper 16 bits>
2403 ori $r2, <lower 16 bits>
2405 But the lui sign-extends the value such that the upper 32 bits
2406 may be all 1s. The workaround is simply to mask off these
2407 bits. In the future, gcc may be changed to support true 64-bit
2408 addressing, and this masking will have to be disabled. */
2409 return addr
&= 0xffffffffUL
;
2414 /* mips_software_single_step() is called just before we want to resume
2415 the inferior, if we want to single-step it but there is no hardware
2416 or kernel single-step support (MIPS on GNU/Linux for example). We find
2417 the target of the coming instruction and breakpoint it.
2419 single_step is also called just after the inferior stops. If we had
2420 set up a simulated single-step, we undo our damage. */
2423 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2425 static CORE_ADDR next_pc
;
2426 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2427 static binsn_quantum break_mem
;
2430 if (insert_breakpoints_p
)
2432 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2433 next_pc
= mips_next_pc (pc
);
2435 target_insert_breakpoint (next_pc
, break_mem
);
2438 target_remove_breakpoint (next_pc
, break_mem
);
2441 static struct mips_extra_func_info temp_proc_desc
;
2443 /* Set a register's saved stack address in temp_saved_regs. If an
2444 address has already been set for this register, do nothing; this
2445 way we will only recognize the first save of a given register in a
2448 For simplicity, save the address in both [0 .. NUM_REGS) and
2449 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2450 is used as it is only second range (the ABI instead of ISA
2451 registers) that comes into play when finding saved registers in a
2455 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2458 if (this_cache
!= NULL
2459 && this_cache
->saved_regs
[regnum
].addr
== 0)
2461 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2462 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2467 /* Test whether the PC points to the return instruction at the
2468 end of a function. */
2471 mips_about_to_return (CORE_ADDR pc
)
2473 if (pc_is_mips16 (pc
))
2474 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2475 generates a "jr $ra"; other times it generates code to load
2476 the return address from the stack to an accessible register (such
2477 as $a3), then a "jr" using that register. This second case
2478 is almost impossible to distinguish from an indirect jump
2479 used for switch statements, so we don't even try. */
2480 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2482 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2486 /* This fencepost looks highly suspicious to me. Removing it also
2487 seems suspicious as it could affect remote debugging across serial
2491 heuristic_proc_start (CORE_ADDR pc
)
2498 pc
= ADDR_BITS_REMOVE (pc
);
2500 fence
= start_pc
- heuristic_fence_post
;
2504 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2505 fence
= VM_MIN_ADDRESS
;
2507 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2509 /* search back for previous return */
2510 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2511 if (start_pc
< fence
)
2513 /* It's not clear to me why we reach this point when
2514 stop_soon, but with this test, at least we
2515 don't print out warnings for every child forked (eg, on
2516 decstation). 22apr93 rich@cygnus.com. */
2517 if (stop_soon
== NO_STOP_QUIETLY
)
2519 static int blurb_printed
= 0;
2521 warning ("GDB can't find the start of the function at 0x%s.",
2526 /* This actually happens frequently in embedded
2527 development, when you first connect to a board
2528 and your stack pointer and pc are nowhere in
2529 particular. This message needs to give people
2530 in that situation enough information to
2531 determine that it's no big deal. */
2532 printf_filtered ("\n\
2533 GDB is unable to find the start of the function at 0x%s\n\
2534 and thus can't determine the size of that function's stack frame.\n\
2535 This means that GDB may be unable to access that stack frame, or\n\
2536 the frames below it.\n\
2537 This problem is most likely caused by an invalid program counter or\n\
2539 However, if you think GDB should simply search farther back\n\
2540 from 0x%s for code which looks like the beginning of a\n\
2541 function, you can increase the range of the search using the `set\n\
2542 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2549 else if (pc_is_mips16 (start_pc
))
2551 unsigned short inst
;
2553 /* On MIPS16, any one of the following is likely to be the
2554 start of a function:
2558 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2559 inst
= mips_fetch_instruction (start_pc
);
2560 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2561 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2562 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2563 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2565 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2566 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2571 else if (mips_about_to_return (start_pc
))
2573 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2580 /* Fetch the immediate value from a MIPS16 instruction.
2581 If the previous instruction was an EXTEND, use it to extend
2582 the upper bits of the immediate value. This is a helper function
2583 for mips16_heuristic_proc_desc. */
2586 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2587 unsigned short inst
, /* current instruction */
2588 int nbits
, /* number of bits in imm field */
2589 int scale
, /* scale factor to be applied to imm */
2590 int is_signed
) /* is the imm field signed? */
2594 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2596 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2597 if (offset
& 0x8000) /* check for negative extend */
2598 offset
= 0 - (0x10000 - (offset
& 0xffff));
2599 return offset
| (inst
& 0x1f);
2603 int max_imm
= 1 << nbits
;
2604 int mask
= max_imm
- 1;
2605 int sign_bit
= max_imm
>> 1;
2607 offset
= inst
& mask
;
2608 if (is_signed
&& (offset
& sign_bit
))
2609 offset
= 0 - (max_imm
- offset
);
2610 return offset
* scale
;
2615 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2616 stream from start_pc to limit_pc. */
2619 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2621 struct frame_info
*next_frame
,
2622 struct mips_frame_cache
*this_cache
)
2625 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2626 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2627 unsigned inst
= 0; /* current instruction */
2628 unsigned entry_inst
= 0; /* the entry instruction */
2630 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2632 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2633 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2635 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2637 /* Save the previous instruction. If it's an EXTEND, we'll extract
2638 the immediate offset extension from it in mips16_get_imm. */
2641 /* Fetch and decode the instruction. */
2642 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2643 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2644 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2646 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2647 if (offset
< 0) /* negative stack adjustment? */
2648 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2650 /* Exit loop if a positive stack adjustment is found, which
2651 usually means that the stack cleanup code in the function
2652 epilogue is reached. */
2655 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2657 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2658 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2659 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2660 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2662 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2664 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2665 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2666 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2667 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2669 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2671 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2672 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2673 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2675 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2677 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2678 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2679 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2681 else if (inst
== 0x673d) /* move $s1, $sp */
2684 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2686 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2688 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2689 frame_addr
= sp
+ offset
;
2690 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2691 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2693 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2695 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2696 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2697 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2698 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2700 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2702 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2703 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2704 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2705 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2707 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2708 entry_inst
= inst
; /* save for later processing */
2709 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2710 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2713 /* The entry instruction is typically the first instruction in a function,
2714 and it stores registers at offsets relative to the value of the old SP
2715 (before the prologue). But the value of the sp parameter to this
2716 function is the new SP (after the prologue has been executed). So we
2717 can't calculate those offsets until we've seen the entire prologue,
2718 and can calculate what the old SP must have been. */
2719 if (entry_inst
!= 0)
2721 int areg_count
= (entry_inst
>> 8) & 7;
2722 int sreg_count
= (entry_inst
>> 6) & 3;
2724 /* The entry instruction always subtracts 32 from the SP. */
2725 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2727 /* Now we can calculate what the SP must have been at the
2728 start of the function prologue. */
2729 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2731 /* Check if a0-a3 were saved in the caller's argument save area. */
2732 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2734 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2735 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2736 offset
+= mips_abi_regsize (current_gdbarch
);
2739 /* Check if the ra register was pushed on the stack. */
2741 if (entry_inst
& 0x20)
2743 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2744 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2745 offset
-= mips_abi_regsize (current_gdbarch
);
2748 /* Check if the s0 and s1 registers were pushed on the stack. */
2749 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2751 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2752 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2753 offset
-= mips_abi_regsize (current_gdbarch
);
2759 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2760 CORE_ADDR sp
, struct frame_info
*next_frame
,
2761 struct mips_frame_cache
*this_cache
)
2764 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2766 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2767 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2768 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2770 unsigned long inst
, high_word
, low_word
;
2773 /* Fetch the instruction. */
2774 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2776 /* Save some code by pre-extracting some useful fields. */
2777 high_word
= (inst
>> 16) & 0xffff;
2778 low_word
= inst
& 0xffff;
2779 reg
= high_word
& 0x1f;
2781 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2782 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2783 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2785 if (low_word
& 0x8000) /* negative stack adjustment? */
2786 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2788 /* Exit loop if a positive stack adjustment is found, which
2789 usually means that the stack cleanup code in the function
2790 epilogue is reached. */
2793 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2795 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2796 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2798 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2800 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2802 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2803 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2805 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2807 /* Old gcc frame, r30 is virtual frame pointer. */
2808 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2809 frame_addr
= sp
+ low_word
;
2810 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2812 unsigned alloca_adjust
;
2813 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2814 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2815 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2816 if (alloca_adjust
> 0)
2818 /* FP > SP + frame_size. This may be because
2819 * of an alloca or somethings similar.
2820 * Fix sp to "pre-alloca" value, and try again.
2822 sp
+= alloca_adjust
;
2827 /* move $30,$sp. With different versions of gas this will be either
2828 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2829 Accept any one of these. */
2830 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2832 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2833 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2835 unsigned alloca_adjust
;
2836 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2837 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2838 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2839 if (alloca_adjust
> 0)
2841 /* FP > SP + frame_size. This may be because
2842 * of an alloca or somethings similar.
2843 * Fix sp to "pre-alloca" value, and try again.
2845 sp
+= alloca_adjust
;
2850 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2852 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2853 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2858 static mips_extra_func_info_t
2859 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2860 struct frame_info
*next_frame
,
2861 struct mips_frame_cache
*this_cache
)
2865 /* Can be called when there's no process, and hence when there's no
2867 if (next_frame
!= NULL
)
2868 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2874 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2875 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2876 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2877 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2879 if (start_pc
+ 200 < limit_pc
)
2880 limit_pc
= start_pc
+ 200;
2881 if (pc_is_mips16 (start_pc
))
2882 mips16_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2883 next_frame
, this_cache
);
2885 mips32_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2886 next_frame
, this_cache
);
2887 return &temp_proc_desc
;
2890 struct mips_objfile_private
2896 /* Global used to communicate between non_heuristic_proc_desc and
2897 compare_pdr_entries within qsort (). */
2898 static bfd
*the_bfd
;
2901 compare_pdr_entries (const void *a
, const void *b
)
2903 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2904 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2908 else if (lhs
== rhs
)
2914 static mips_extra_func_info_t
2915 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2917 CORE_ADDR startaddr
;
2918 mips_extra_func_info_t proc_desc
;
2919 struct block
*b
= block_for_pc (pc
);
2921 struct obj_section
*sec
;
2922 struct mips_objfile_private
*priv
;
2924 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2926 *addrptr
= startaddr
;
2930 sec
= find_pc_section (pc
);
2933 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2935 /* Search the ".pdr" section generated by GAS. This includes most of
2936 the information normally found in ECOFF PDRs. */
2938 the_bfd
= sec
->objfile
->obfd
;
2940 && (the_bfd
->format
== bfd_object
2941 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2942 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2944 /* Right now GAS only outputs the address as a four-byte sequence.
2945 This means that we should not bother with this method on 64-bit
2946 targets (until that is fixed). */
2948 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2949 sizeof (struct mips_objfile_private
));
2951 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2953 else if (priv
== NULL
)
2957 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2958 sizeof (struct mips_objfile_private
));
2960 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2963 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2964 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2966 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2967 priv
->contents
, 0, priv
->size
);
2969 /* In general, the .pdr section is sorted. However, in the
2970 presence of multiple code sections (and other corner cases)
2971 it can become unsorted. Sort it so that we can use a faster
2973 qsort (priv
->contents
, priv
->size
/ 32, 32,
2974 compare_pdr_entries
);
2979 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2983 if (priv
->size
!= 0)
2990 high
= priv
->size
/ 32;
2992 /* We've found a .pdr section describing this objfile. We want to
2993 find the entry which describes this code address. The .pdr
2994 information is not very descriptive; we have only a function
2995 start address. We have to look for the closest entry, because
2996 the local symbol at the beginning of this function may have
2997 been stripped - so if we ask the symbol table for the start
2998 address we may get a preceding global function. */
3000 /* First, find the last .pdr entry starting at or before PC. */
3003 mid
= (low
+ high
) / 2;
3005 ptr
= priv
->contents
+ mid
* 32;
3006 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3007 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3008 SECT_OFF_TEXT (sec
->objfile
));
3015 while (low
!= high
);
3017 /* Both low and high point one past the PDR of interest. If
3018 both are zero, that means this PC is before any region
3019 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3023 ptr
= priv
->contents
+ (low
- 1) * 32;
3024 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3025 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3026 SECT_OFF_TEXT (sec
->objfile
));
3029 /* We don't have a range, so we have no way to know for sure
3030 whether we're in the correct PDR or a PDR for a preceding
3031 function and the current function was a stripped local
3032 symbol. But if the PDR's PC is at least as great as the
3033 best guess from the symbol table, assume that it does cover
3034 the right area; if a .pdr section is present at all then
3035 nearly every function will have an entry. The biggest exception
3036 will be the dynamic linker stubs; conveniently these are
3037 placed before .text instead of after. */
3039 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3041 struct symbol
*sym
= find_pc_function (pc
);
3046 /* Fill in what we need of the proc_desc. */
3047 proc_desc
= (mips_extra_func_info_t
)
3048 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3049 sizeof (struct mips_extra_func_info
));
3050 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3052 /* Only used for dummy frames. */
3053 PROC_HIGH_ADDR (proc_desc
) = 0;
3055 PROC_FRAME_OFFSET (proc_desc
)
3056 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3057 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3059 PROC_FRAME_ADJUST (proc_desc
) = 0;
3060 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3062 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3064 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3066 PROC_FREG_OFFSET (proc_desc
)
3067 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3068 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3070 proc_desc
->pdr
.isym
= (long) sym
;
3080 if (startaddr
> BLOCK_START (b
))
3082 /* This is the "pathological" case referred to in a comment in
3083 print_frame_info. It might be better to move this check into
3088 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3090 /* If we never found a PDR for this function in symbol reading, then
3091 examine prologues to find the information. */
3094 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3095 if (PROC_FRAME_REG (proc_desc
) == -1)
3104 /* MIPS stack frames are almost impenetrable. When execution stops,
3105 we basically have to look at symbol information for the function
3106 that we stopped in, which tells us *which* register (if any) is
3107 the base of the frame pointer, and what offset from that register
3108 the frame itself is at.
3110 This presents a problem when trying to examine a stack in memory
3111 (that isn't executing at the moment), using the "frame" command. We
3112 don't have a PC, nor do we have any registers except SP.
3114 This routine takes two arguments, SP and PC, and tries to make the
3115 cached frames look as if these two arguments defined a frame on the
3116 cache. This allows the rest of info frame to extract the important
3117 arguments without difficulty. */
3120 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3123 error ("MIPS frame specifications require two arguments: sp and pc");
3125 return create_new_frame (argv
[0], argv
[1]);
3128 /* According to the current ABI, should the type be passed in a
3129 floating-point register (assuming that there is space)? When there
3130 is no FPU, FP are not even considered as possibile candidates for
3131 FP registers and, consequently this returns false - forces FP
3132 arguments into integer registers. */
3135 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3137 return ((typecode
== TYPE_CODE_FLT
3139 && (typecode
== TYPE_CODE_STRUCT
3140 || typecode
== TYPE_CODE_UNION
)
3141 && TYPE_NFIELDS (arg_type
) == 1
3142 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3143 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3146 /* On o32, argument passing in GPRs depends on the alignment of the type being
3147 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3150 mips_type_needs_double_align (struct type
*type
)
3152 enum type_code typecode
= TYPE_CODE (type
);
3154 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3156 else if (typecode
== TYPE_CODE_STRUCT
)
3158 if (TYPE_NFIELDS (type
) < 1)
3160 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3162 else if (typecode
== TYPE_CODE_UNION
)
3166 n
= TYPE_NFIELDS (type
);
3167 for (i
= 0; i
< n
; i
++)
3168 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3175 /* Adjust the address downward (direction of stack growth) so that it
3176 is correctly aligned for a new stack frame. */
3178 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3180 return align_down (addr
, 16);
3183 /* Determine how a return value is stored within the MIPS register
3184 file, given the return type `valtype'. */
3186 struct return_value_word
3195 return_value_location (struct type
*valtype
,
3196 struct return_value_word
*hi
,
3197 struct return_value_word
*lo
)
3199 int len
= TYPE_LENGTH (valtype
);
3200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3202 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3203 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3204 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3206 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3208 /* We need to break a 64bit float in two 32 bit halves and
3209 spread them across a floating-point register pair. */
3210 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3211 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3212 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3213 && register_size (current_gdbarch
,
3214 mips_regnum (current_gdbarch
)->
3215 fp0
) == 8) ? 4 : 0);
3216 hi
->reg_offset
= lo
->reg_offset
;
3217 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3218 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3224 /* The floating point value fits in a single floating-point
3226 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3227 && register_size (current_gdbarch
,
3228 mips_regnum (current_gdbarch
)->
3230 && len
== 4) ? 4 : 0);
3231 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3242 /* Locate a result possibly spread across two registers. */
3244 lo
->reg
= regnum
+ 0;
3245 hi
->reg
= regnum
+ 1;
3246 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3247 && len
< mips_abi_regsize (current_gdbarch
))
3249 /* "un-left-justify" the value in the low register */
3250 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3255 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3256 && len
< mips_abi_regsize (current_gdbarch
) * 2
3257 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3258 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3260 /* "un-left-justify" the value spread across two registers. */
3261 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3262 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3264 hi
->len
= len
- lo
->len
;
3268 /* Only perform a partial copy of the second register. */
3271 if (len
> mips_abi_regsize (current_gdbarch
))
3273 lo
->len
= mips_abi_regsize (current_gdbarch
);
3274 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3282 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3283 && register_size (current_gdbarch
, regnum
) == 8
3284 && mips_abi_regsize (current_gdbarch
) == 4)
3286 /* Account for the fact that only the least-signficant part
3287 of the register is being used */
3288 lo
->reg_offset
+= 4;
3289 hi
->reg_offset
+= 4;
3292 hi
->buf_offset
= lo
->len
;
3296 /* Should call_function allocate stack space for a struct return? */
3299 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3302 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3305 /* Should call_function pass struct by reference?
3306 For each architecture, structs are passed either by
3307 value or by reference, depending on their size. */
3310 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3312 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3313 int len
= TYPE_LENGTH (check_typedef (type
));
3314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3316 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3317 return (len
> mips_abi_regsize (current_gdbarch
));
3323 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3324 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3325 int nargs
, struct value
**args
, CORE_ADDR sp
,
3326 int struct_return
, CORE_ADDR struct_addr
)
3332 int stack_offset
= 0;
3333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3334 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3336 /* For shared libraries, "t9" needs to point at the function
3338 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3340 /* Set the return address register to point to the entry point of
3341 the program, where a breakpoint lies in wait. */
3342 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3344 /* First ensure that the stack and structure return address (if any)
3345 are properly aligned. The stack has to be at least 64-bit
3346 aligned even on 32-bit machines, because doubles must be 64-bit
3347 aligned. For n32 and n64, stack frames need to be 128-bit
3348 aligned, so we round to this widest known alignment. */
3350 sp
= align_down (sp
, 16);
3351 struct_addr
= align_down (struct_addr
, 16);
3353 /* Now make space on the stack for the args. We allocate more
3354 than necessary for EABI, because the first few arguments are
3355 passed in registers, but that's OK. */
3356 for (argnum
= 0; argnum
< nargs
; argnum
++)
3357 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3358 mips_stack_argsize (gdbarch
));
3359 sp
-= align_up (len
, 16);
3362 fprintf_unfiltered (gdb_stdlog
,
3363 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3364 paddr_nz (sp
), (long) align_up (len
, 16));
3366 /* Initialize the integer and float register pointers. */
3368 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3370 /* The struct_return pointer occupies the first parameter-passing reg. */
3374 fprintf_unfiltered (gdb_stdlog
,
3375 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3376 argreg
, paddr_nz (struct_addr
));
3377 write_register (argreg
++, struct_addr
);
3380 /* Now load as many as possible of the first arguments into
3381 registers, and push the rest onto the stack. Loop thru args
3382 from first to last. */
3383 for (argnum
= 0; argnum
< nargs
; argnum
++)
3386 char valbuf
[MAX_REGISTER_SIZE
];
3387 struct value
*arg
= args
[argnum
];
3388 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3389 int len
= TYPE_LENGTH (arg_type
);
3390 enum type_code typecode
= TYPE_CODE (arg_type
);
3393 fprintf_unfiltered (gdb_stdlog
,
3394 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3395 argnum
+ 1, len
, (int) typecode
);
3397 /* The EABI passes structures that do not fit in a register by
3399 if (len
> mips_abi_regsize (gdbarch
)
3400 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3402 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3403 VALUE_ADDRESS (arg
));
3404 typecode
= TYPE_CODE_PTR
;
3405 len
= mips_abi_regsize (gdbarch
);
3408 fprintf_unfiltered (gdb_stdlog
, " push");
3411 val
= (char *) VALUE_CONTENTS (arg
);
3413 /* 32-bit ABIs always start floating point arguments in an
3414 even-numbered floating point register. Round the FP register
3415 up before the check to see if there are any FP registers
3416 left. Non MIPS_EABI targets also pass the FP in the integer
3417 registers so also round up normal registers. */
3418 if (mips_abi_regsize (gdbarch
) < 8
3419 && fp_register_arg_p (typecode
, arg_type
))
3421 if ((float_argreg
& 1))
3425 /* Floating point arguments passed in registers have to be
3426 treated specially. On 32-bit architectures, doubles
3427 are passed in register pairs; the even register gets
3428 the low word, and the odd register gets the high word.
3429 On non-EABI processors, the first two floating point arguments are
3430 also copied to general registers, because MIPS16 functions
3431 don't use float registers for arguments. This duplication of
3432 arguments in general registers can't hurt non-MIPS16 functions
3433 because those registers are normally skipped. */
3434 /* MIPS_EABI squeezes a struct that contains a single floating
3435 point value into an FP register instead of pushing it onto the
3437 if (fp_register_arg_p (typecode
, arg_type
)
3438 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3440 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3442 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3443 unsigned long regval
;
3445 /* Write the low word of the double to the even register(s). */
3446 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3449 float_argreg
, phex (regval
, 4));
3450 write_register (float_argreg
++, regval
);
3452 /* Write the high word of the double to the odd register(s). */
3453 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3455 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3456 float_argreg
, phex (regval
, 4));
3457 write_register (float_argreg
++, regval
);
3461 /* This is a floating point value that fits entirely
3462 in a single register. */
3463 /* On 32 bit ABI's the float_argreg is further adjusted
3464 above to ensure that it is even register aligned. */
3465 LONGEST regval
= extract_unsigned_integer (val
, len
);
3467 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3468 float_argreg
, phex (regval
, len
));
3469 write_register (float_argreg
++, regval
);
3474 /* Copy the argument to general registers or the stack in
3475 register-sized pieces. Large arguments are split between
3476 registers and stack. */
3477 /* Note: structs whose size is not a multiple of
3478 mips_abi_regsize() are treated specially: Irix cc passes
3479 them in registers where gcc sometimes puts them on the
3480 stack. For maximum compatibility, we will put them in
3482 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3483 && (len
% mips_abi_regsize (gdbarch
) != 0));
3485 /* Note: Floating-point values that didn't fit into an FP
3486 register are only written to memory. */
3489 /* Remember if the argument was written to the stack. */
3490 int stack_used_p
= 0;
3491 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3492 ? len
: mips_abi_regsize (gdbarch
));
3495 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3498 /* Write this portion of the argument to the stack. */
3499 if (argreg
> MIPS_LAST_ARG_REGNUM
3501 || fp_register_arg_p (typecode
, arg_type
))
3503 /* Should shorter than int integer values be
3504 promoted to int before being stored? */
3505 int longword_offset
= 0;
3508 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3510 if (mips_stack_argsize (gdbarch
) == 8
3511 && (typecode
== TYPE_CODE_INT
3512 || typecode
== TYPE_CODE_PTR
3513 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3514 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3515 else if ((typecode
== TYPE_CODE_STRUCT
3516 || typecode
== TYPE_CODE_UNION
)
3517 && (TYPE_LENGTH (arg_type
)
3518 < mips_stack_argsize (gdbarch
)))
3519 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3524 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3525 paddr_nz (stack_offset
));
3526 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3527 paddr_nz (longword_offset
));
3530 addr
= sp
+ stack_offset
+ longword_offset
;
3535 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3537 for (i
= 0; i
< partial_len
; i
++)
3539 fprintf_unfiltered (gdb_stdlog
, "%02x",
3543 write_memory (addr
, val
, partial_len
);
3546 /* Note!!! This is NOT an else clause. Odd sized
3547 structs may go thru BOTH paths. Floating point
3548 arguments will not. */
3549 /* Write this portion of the argument to a general
3550 purpose register. */
3551 if (argreg
<= MIPS_LAST_ARG_REGNUM
3552 && !fp_register_arg_p (typecode
, arg_type
))
3555 extract_unsigned_integer (val
, partial_len
);
3558 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3561 mips_abi_regsize (gdbarch
)));
3562 write_register (argreg
, regval
);
3569 /* Compute the the offset into the stack at which we
3570 will copy the next parameter.
3572 In the new EABI (and the NABI32), the stack_offset
3573 only needs to be adjusted when it has been used. */
3576 stack_offset
+= align_up (partial_len
,
3577 mips_stack_argsize (gdbarch
));
3581 fprintf_unfiltered (gdb_stdlog
, "\n");
3584 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3586 /* Return adjusted stack pointer. */
3590 /* Given a return value in `regbuf' with a type `valtype', extract and
3591 copy its value into `valbuf'. */
3594 mips_eabi_extract_return_value (struct type
*valtype
,
3595 char regbuf
[], char *valbuf
)
3597 struct return_value_word lo
;
3598 struct return_value_word hi
;
3599 return_value_location (valtype
, &hi
, &lo
);
3601 memcpy (valbuf
+ lo
.buf_offset
,
3602 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3603 lo
.reg_offset
, lo
.len
);
3606 memcpy (valbuf
+ hi
.buf_offset
,
3607 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3608 hi
.reg_offset
, hi
.len
);
3611 /* Given a return value in `valbuf' with a type `valtype', write it's
3612 value into the appropriate register. */
3615 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3617 char raw_buffer
[MAX_REGISTER_SIZE
];
3618 struct return_value_word lo
;
3619 struct return_value_word hi
;
3620 return_value_location (valtype
, &hi
, &lo
);
3622 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3623 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3624 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3625 raw_buffer
, register_size (current_gdbarch
,
3630 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3631 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3632 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3634 register_size (current_gdbarch
,
3639 /* N32/N64 ABI stuff. */
3642 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3643 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3644 int nargs
, struct value
**args
, CORE_ADDR sp
,
3645 int struct_return
, CORE_ADDR struct_addr
)
3651 int stack_offset
= 0;
3652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3653 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3655 /* For shared libraries, "t9" needs to point at the function
3657 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3659 /* Set the return address register to point to the entry point of
3660 the program, where a breakpoint lies in wait. */
3661 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3663 /* First ensure that the stack and structure return address (if any)
3664 are properly aligned. The stack has to be at least 64-bit
3665 aligned even on 32-bit machines, because doubles must be 64-bit
3666 aligned. For n32 and n64, stack frames need to be 128-bit
3667 aligned, so we round to this widest known alignment. */
3669 sp
= align_down (sp
, 16);
3670 struct_addr
= align_down (struct_addr
, 16);
3672 /* Now make space on the stack for the args. */
3673 for (argnum
= 0; argnum
< nargs
; argnum
++)
3674 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3675 mips_stack_argsize (gdbarch
));
3676 sp
-= align_up (len
, 16);
3679 fprintf_unfiltered (gdb_stdlog
,
3680 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3681 paddr_nz (sp
), (long) align_up (len
, 16));
3683 /* Initialize the integer and float register pointers. */
3685 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3687 /* The struct_return pointer occupies the first parameter-passing reg. */
3691 fprintf_unfiltered (gdb_stdlog
,
3692 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3693 argreg
, paddr_nz (struct_addr
));
3694 write_register (argreg
++, struct_addr
);
3697 /* Now load as many as possible of the first arguments into
3698 registers, and push the rest onto the stack. Loop thru args
3699 from first to last. */
3700 for (argnum
= 0; argnum
< nargs
; argnum
++)
3703 struct value
*arg
= args
[argnum
];
3704 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3705 int len
= TYPE_LENGTH (arg_type
);
3706 enum type_code typecode
= TYPE_CODE (arg_type
);
3709 fprintf_unfiltered (gdb_stdlog
,
3710 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3711 argnum
+ 1, len
, (int) typecode
);
3713 val
= (char *) VALUE_CONTENTS (arg
);
3715 if (fp_register_arg_p (typecode
, arg_type
)
3716 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3718 /* This is a floating point value that fits entirely
3719 in a single register. */
3720 /* On 32 bit ABI's the float_argreg is further adjusted
3721 above to ensure that it is even register aligned. */
3722 LONGEST regval
= extract_unsigned_integer (val
, len
);
3724 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3725 float_argreg
, phex (regval
, len
));
3726 write_register (float_argreg
++, regval
);
3729 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3730 argreg
, phex (regval
, len
));
3731 write_register (argreg
, regval
);
3736 /* Copy the argument to general registers or the stack in
3737 register-sized pieces. Large arguments are split between
3738 registers and stack. */
3739 /* Note: structs whose size is not a multiple of
3740 mips_abi_regsize() are treated specially: Irix cc passes
3741 them in registers where gcc sometimes puts them on the
3742 stack. For maximum compatibility, we will put them in
3744 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3745 && (len
% mips_abi_regsize (gdbarch
) != 0));
3746 /* Note: Floating-point values that didn't fit into an FP
3747 register are only written to memory. */
3750 /* Rememer if the argument was written to the stack. */
3751 int stack_used_p
= 0;
3752 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3753 ? len
: mips_abi_regsize (gdbarch
));
3756 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3759 /* Write this portion of the argument to the stack. */
3760 if (argreg
> MIPS_LAST_ARG_REGNUM
3762 || fp_register_arg_p (typecode
, arg_type
))
3764 /* Should shorter than int integer values be
3765 promoted to int before being stored? */
3766 int longword_offset
= 0;
3769 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3771 if (mips_stack_argsize (gdbarch
) == 8
3772 && (typecode
== TYPE_CODE_INT
3773 || typecode
== TYPE_CODE_PTR
3774 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3775 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3780 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3781 paddr_nz (stack_offset
));
3782 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3783 paddr_nz (longword_offset
));
3786 addr
= sp
+ stack_offset
+ longword_offset
;
3791 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3793 for (i
= 0; i
< partial_len
; i
++)
3795 fprintf_unfiltered (gdb_stdlog
, "%02x",
3799 write_memory (addr
, val
, partial_len
);
3802 /* Note!!! This is NOT an else clause. Odd sized
3803 structs may go thru BOTH paths. Floating point
3804 arguments will not. */
3805 /* Write this portion of the argument to a general
3806 purpose register. */
3807 if (argreg
<= MIPS_LAST_ARG_REGNUM
3808 && !fp_register_arg_p (typecode
, arg_type
))
3811 extract_unsigned_integer (val
, partial_len
);
3813 /* A non-floating-point argument being passed in a
3814 general register. If a struct or union, and if
3815 the remaining length is smaller than the register
3816 size, we have to adjust the register value on
3819 It does not seem to be necessary to do the
3820 same for integral types.
3822 cagney/2001-07-23: gdb/179: Also, GCC, when
3823 outputting LE O32 with sizeof (struct) <
3824 mips_abi_regsize(), generates a left shift as
3825 part of storing the argument in a register a
3826 register (the left shift isn't generated when
3827 sizeof (struct) >= mips_abi_regsize()). Since
3828 it is quite possible that this is GCC
3829 contradicting the LE/O32 ABI, GDB has not been
3830 adjusted to accommodate this. Either someone
3831 needs to demonstrate that the LE/O32 ABI
3832 specifies such a left shift OR this new ABI gets
3833 identified as such and GDB gets tweaked
3836 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3837 && partial_len
< mips_abi_regsize (gdbarch
)
3838 && (typecode
== TYPE_CODE_STRUCT
||
3839 typecode
== TYPE_CODE_UNION
))
3840 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3844 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3847 mips_abi_regsize (gdbarch
)));
3848 write_register (argreg
, regval
);
3855 /* Compute the the offset into the stack at which we
3856 will copy the next parameter.
3858 In N32 (N64?), the stack_offset only needs to be
3859 adjusted when it has been used. */
3862 stack_offset
+= align_up (partial_len
,
3863 mips_stack_argsize (gdbarch
));
3867 fprintf_unfiltered (gdb_stdlog
, "\n");
3870 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3872 /* Return adjusted stack pointer. */
3876 static enum return_value_convention
3877 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3878 struct type
*type
, struct regcache
*regcache
,
3879 void *readbuf
, const void *writebuf
)
3881 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3882 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3883 || TYPE_CODE (type
) == TYPE_CODE_UNION
3884 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3885 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3886 return RETURN_VALUE_STRUCT_CONVENTION
;
3887 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3888 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3890 /* A floating-point value belongs in the least significant part
3893 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3894 mips_xfer_register (regcache
,
3895 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3897 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3898 return RETURN_VALUE_REGISTER_CONVENTION
;
3900 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3901 && TYPE_NFIELDS (type
) <= 2
3902 && TYPE_NFIELDS (type
) >= 1
3903 && ((TYPE_NFIELDS (type
) == 1
3904 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3906 || (TYPE_NFIELDS (type
) == 2
3907 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3909 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3911 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3913 /* A struct that contains one or two floats. Each value is part
3914 in the least significant part of their floating point
3918 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3919 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3921 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3924 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3926 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3927 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3928 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3930 return RETURN_VALUE_REGISTER_CONVENTION
;
3932 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3933 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3935 /* A structure or union. Extract the left justified value,
3936 regardless of the byte order. I.e. DO NOT USE
3940 for (offset
= 0, regnum
= V0_REGNUM
;
3941 offset
< TYPE_LENGTH (type
);
3942 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3944 int xfer
= register_size (current_gdbarch
, regnum
);
3945 if (offset
+ xfer
> TYPE_LENGTH (type
))
3946 xfer
= TYPE_LENGTH (type
) - offset
;
3948 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3949 offset
, xfer
, regnum
);
3950 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3951 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3953 return RETURN_VALUE_REGISTER_CONVENTION
;
3957 /* A scalar extract each part but least-significant-byte
3961 for (offset
= 0, regnum
= V0_REGNUM
;
3962 offset
< TYPE_LENGTH (type
);
3963 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3965 int xfer
= register_size (current_gdbarch
, regnum
);
3966 if (offset
+ xfer
> TYPE_LENGTH (type
))
3967 xfer
= TYPE_LENGTH (type
) - offset
;
3969 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3970 offset
, xfer
, regnum
);
3971 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3972 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3974 return RETURN_VALUE_REGISTER_CONVENTION
;
3978 /* O32 ABI stuff. */
3981 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3982 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3983 int nargs
, struct value
**args
, CORE_ADDR sp
,
3984 int struct_return
, CORE_ADDR struct_addr
)
3990 int stack_offset
= 0;
3991 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3992 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3994 /* For shared libraries, "t9" needs to point at the function
3996 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3998 /* Set the return address register to point to the entry point of
3999 the program, where a breakpoint lies in wait. */
4000 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4002 /* First ensure that the stack and structure return address (if any)
4003 are properly aligned. The stack has to be at least 64-bit
4004 aligned even on 32-bit machines, because doubles must be 64-bit
4005 aligned. For n32 and n64, stack frames need to be 128-bit
4006 aligned, so we round to this widest known alignment. */
4008 sp
= align_down (sp
, 16);
4009 struct_addr
= align_down (struct_addr
, 16);
4011 /* Now make space on the stack for the args. */
4012 for (argnum
= 0; argnum
< nargs
; argnum
++)
4013 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4014 mips_stack_argsize (gdbarch
));
4015 sp
-= align_up (len
, 16);
4018 fprintf_unfiltered (gdb_stdlog
,
4019 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4020 paddr_nz (sp
), (long) align_up (len
, 16));
4022 /* Initialize the integer and float register pointers. */
4024 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4026 /* The struct_return pointer occupies the first parameter-passing reg. */
4030 fprintf_unfiltered (gdb_stdlog
,
4031 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4032 argreg
, paddr_nz (struct_addr
));
4033 write_register (argreg
++, struct_addr
);
4034 stack_offset
+= mips_stack_argsize (gdbarch
);
4037 /* Now load as many as possible of the first arguments into
4038 registers, and push the rest onto the stack. Loop thru args
4039 from first to last. */
4040 for (argnum
= 0; argnum
< nargs
; argnum
++)
4043 struct value
*arg
= args
[argnum
];
4044 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4045 int len
= TYPE_LENGTH (arg_type
);
4046 enum type_code typecode
= TYPE_CODE (arg_type
);
4049 fprintf_unfiltered (gdb_stdlog
,
4050 "mips_o32_push_dummy_call: %d len=%d type=%d",
4051 argnum
+ 1, len
, (int) typecode
);
4053 val
= (char *) VALUE_CONTENTS (arg
);
4055 /* 32-bit ABIs always start floating point arguments in an
4056 even-numbered floating point register. Round the FP register
4057 up before the check to see if there are any FP registers
4058 left. O32/O64 targets also pass the FP in the integer
4059 registers so also round up normal registers. */
4060 if (mips_abi_regsize (gdbarch
) < 8
4061 && fp_register_arg_p (typecode
, arg_type
))
4063 if ((float_argreg
& 1))
4067 /* Floating point arguments passed in registers have to be
4068 treated specially. On 32-bit architectures, doubles
4069 are passed in register pairs; the even register gets
4070 the low word, and the odd register gets the high word.
4071 On O32/O64, the first two floating point arguments are
4072 also copied to general registers, because MIPS16 functions
4073 don't use float registers for arguments. This duplication of
4074 arguments in general registers can't hurt non-MIPS16 functions
4075 because those registers are normally skipped. */
4077 if (fp_register_arg_p (typecode
, arg_type
)
4078 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4080 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4082 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4083 unsigned long regval
;
4085 /* Write the low word of the double to the even register(s). */
4086 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4088 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4089 float_argreg
, phex (regval
, 4));
4090 write_register (float_argreg
++, regval
);
4092 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4093 argreg
, phex (regval
, 4));
4094 write_register (argreg
++, regval
);
4096 /* Write the high word of the double to the odd register(s). */
4097 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4099 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4100 float_argreg
, phex (regval
, 4));
4101 write_register (float_argreg
++, regval
);
4104 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4105 argreg
, phex (regval
, 4));
4106 write_register (argreg
++, regval
);
4110 /* This is a floating point value that fits entirely
4111 in a single register. */
4112 /* On 32 bit ABI's the float_argreg is further adjusted
4113 above to ensure that it is even register aligned. */
4114 LONGEST regval
= extract_unsigned_integer (val
, len
);
4116 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4117 float_argreg
, phex (regval
, len
));
4118 write_register (float_argreg
++, regval
);
4119 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4120 registers for each argument. The below is (my
4121 guess) to ensure that the corresponding integer
4122 register has reserved the same space. */
4124 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4125 argreg
, phex (regval
, len
));
4126 write_register (argreg
, regval
);
4127 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4129 /* Reserve space for the FP register. */
4130 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4134 /* Copy the argument to general registers or the stack in
4135 register-sized pieces. Large arguments are split between
4136 registers and stack. */
4137 /* Note: structs whose size is not a multiple of
4138 mips_abi_regsize() are treated specially: Irix cc passes
4139 them in registers where gcc sometimes puts them on the
4140 stack. For maximum compatibility, we will put them in
4142 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4143 && (len
% mips_abi_regsize (gdbarch
) != 0));
4144 /* Structures should be aligned to eight bytes (even arg registers)
4145 on MIPS_ABI_O32, if their first member has double precision. */
4146 if (mips_abi_regsize (gdbarch
) < 8
4147 && mips_type_needs_double_align (arg_type
))
4152 /* Note: Floating-point values that didn't fit into an FP
4153 register are only written to memory. */
4156 /* Remember if the argument was written to the stack. */
4157 int stack_used_p
= 0;
4158 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4159 ? len
: mips_abi_regsize (gdbarch
));
4162 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4165 /* Write this portion of the argument to the stack. */
4166 if (argreg
> MIPS_LAST_ARG_REGNUM
4168 || fp_register_arg_p (typecode
, arg_type
))
4170 /* Should shorter than int integer values be
4171 promoted to int before being stored? */
4172 int longword_offset
= 0;
4175 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4177 if (mips_stack_argsize (gdbarch
) == 8
4178 && (typecode
== TYPE_CODE_INT
4179 || typecode
== TYPE_CODE_PTR
4180 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4181 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4186 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4187 paddr_nz (stack_offset
));
4188 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4189 paddr_nz (longword_offset
));
4192 addr
= sp
+ stack_offset
+ longword_offset
;
4197 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4199 for (i
= 0; i
< partial_len
; i
++)
4201 fprintf_unfiltered (gdb_stdlog
, "%02x",
4205 write_memory (addr
, val
, partial_len
);
4208 /* Note!!! This is NOT an else clause. Odd sized
4209 structs may go thru BOTH paths. Floating point
4210 arguments will not. */
4211 /* Write this portion of the argument to a general
4212 purpose register. */
4213 if (argreg
<= MIPS_LAST_ARG_REGNUM
4214 && !fp_register_arg_p (typecode
, arg_type
))
4216 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4217 /* Value may need to be sign extended, because
4218 mips_isa_regsize() != mips_abi_regsize(). */
4220 /* A non-floating-point argument being passed in a
4221 general register. If a struct or union, and if
4222 the remaining length is smaller than the register
4223 size, we have to adjust the register value on
4226 It does not seem to be necessary to do the
4227 same for integral types.
4229 Also don't do this adjustment on O64 binaries.
4231 cagney/2001-07-23: gdb/179: Also, GCC, when
4232 outputting LE O32 with sizeof (struct) <
4233 mips_abi_regsize(), generates a left shift as
4234 part of storing the argument in a register a
4235 register (the left shift isn't generated when
4236 sizeof (struct) >= mips_abi_regsize()). Since
4237 it is quite possible that this is GCC
4238 contradicting the LE/O32 ABI, GDB has not been
4239 adjusted to accommodate this. Either someone
4240 needs to demonstrate that the LE/O32 ABI
4241 specifies such a left shift OR this new ABI gets
4242 identified as such and GDB gets tweaked
4245 if (mips_abi_regsize (gdbarch
) < 8
4246 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4247 && partial_len
< mips_abi_regsize (gdbarch
)
4248 && (typecode
== TYPE_CODE_STRUCT
||
4249 typecode
== TYPE_CODE_UNION
))
4250 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4254 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4257 mips_abi_regsize (gdbarch
)));
4258 write_register (argreg
, regval
);
4261 /* Prevent subsequent floating point arguments from
4262 being passed in floating point registers. */
4263 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4269 /* Compute the the offset into the stack at which we
4270 will copy the next parameter.
4272 In older ABIs, the caller reserved space for
4273 registers that contained arguments. This was loosely
4274 refered to as their "home". Consequently, space is
4275 always allocated. */
4277 stack_offset
+= align_up (partial_len
,
4278 mips_stack_argsize (gdbarch
));
4282 fprintf_unfiltered (gdb_stdlog
, "\n");
4285 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4287 /* Return adjusted stack pointer. */
4291 static enum return_value_convention
4292 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4293 struct regcache
*regcache
,
4294 void *readbuf
, const void *writebuf
)
4296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4298 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4299 || TYPE_CODE (type
) == TYPE_CODE_UNION
4300 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4301 return RETURN_VALUE_STRUCT_CONVENTION
;
4302 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4303 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4305 /* A single-precision floating-point value. It fits in the
4306 least significant part of FP0. */
4308 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4309 mips_xfer_register (regcache
,
4310 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4312 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4313 return RETURN_VALUE_REGISTER_CONVENTION
;
4315 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4316 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4318 /* A double-precision floating-point value. The most
4319 significant part goes in FP1, and the least significant in
4322 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4323 switch (TARGET_BYTE_ORDER
)
4325 case BFD_ENDIAN_LITTLE
:
4326 mips_xfer_register (regcache
,
4327 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4328 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4329 mips_xfer_register (regcache
,
4330 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4331 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4333 case BFD_ENDIAN_BIG
:
4334 mips_xfer_register (regcache
,
4335 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4336 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4337 mips_xfer_register (regcache
,
4338 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4339 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4342 internal_error (__FILE__
, __LINE__
, "bad switch");
4344 return RETURN_VALUE_REGISTER_CONVENTION
;
4347 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4348 && TYPE_NFIELDS (type
) <= 2
4349 && TYPE_NFIELDS (type
) >= 1
4350 && ((TYPE_NFIELDS (type
) == 1
4351 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4353 || (TYPE_NFIELDS (type
) == 2
4354 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4356 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4358 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4360 /* A struct that contains one or two floats. Each value is part
4361 in the least significant part of their floating point
4363 bfd_byte reg
[MAX_REGISTER_SIZE
];
4366 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4367 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4369 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4372 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4374 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4375 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4376 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4378 return RETURN_VALUE_REGISTER_CONVENTION
;
4382 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4383 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4385 /* A structure or union. Extract the left justified value,
4386 regardless of the byte order. I.e. DO NOT USE
4390 for (offset
= 0, regnum
= V0_REGNUM
;
4391 offset
< TYPE_LENGTH (type
);
4392 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4394 int xfer
= register_size (current_gdbarch
, regnum
);
4395 if (offset
+ xfer
> TYPE_LENGTH (type
))
4396 xfer
= TYPE_LENGTH (type
) - offset
;
4398 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4399 offset
, xfer
, regnum
);
4400 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4401 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4403 return RETURN_VALUE_REGISTER_CONVENTION
;
4408 /* A scalar extract each part but least-significant-byte
4409 justified. o32 thinks registers are 4 byte, regardless of
4410 the ISA. mips_stack_argsize controls this. */
4413 for (offset
= 0, regnum
= V0_REGNUM
;
4414 offset
< TYPE_LENGTH (type
);
4415 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4417 int xfer
= mips_stack_argsize (gdbarch
);
4418 if (offset
+ xfer
> TYPE_LENGTH (type
))
4419 xfer
= TYPE_LENGTH (type
) - offset
;
4421 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4422 offset
, xfer
, regnum
);
4423 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4424 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4426 return RETURN_VALUE_REGISTER_CONVENTION
;
4430 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4434 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4435 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4437 struct value
**args
, CORE_ADDR sp
,
4438 int struct_return
, CORE_ADDR struct_addr
)
4444 int stack_offset
= 0;
4445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4446 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4448 /* For shared libraries, "t9" needs to point at the function
4450 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4452 /* Set the return address register to point to the entry point of
4453 the program, where a breakpoint lies in wait. */
4454 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4456 /* First ensure that the stack and structure return address (if any)
4457 are properly aligned. The stack has to be at least 64-bit
4458 aligned even on 32-bit machines, because doubles must be 64-bit
4459 aligned. For n32 and n64, stack frames need to be 128-bit
4460 aligned, so we round to this widest known alignment. */
4462 sp
= align_down (sp
, 16);
4463 struct_addr
= align_down (struct_addr
, 16);
4465 /* Now make space on the stack for the args. */
4466 for (argnum
= 0; argnum
< nargs
; argnum
++)
4467 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4468 mips_stack_argsize (gdbarch
));
4469 sp
-= align_up (len
, 16);
4472 fprintf_unfiltered (gdb_stdlog
,
4473 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4474 paddr_nz (sp
), (long) align_up (len
, 16));
4476 /* Initialize the integer and float register pointers. */
4478 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4480 /* The struct_return pointer occupies the first parameter-passing reg. */
4484 fprintf_unfiltered (gdb_stdlog
,
4485 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4486 argreg
, paddr_nz (struct_addr
));
4487 write_register (argreg
++, struct_addr
);
4488 stack_offset
+= mips_stack_argsize (gdbarch
);
4491 /* Now load as many as possible of the first arguments into
4492 registers, and push the rest onto the stack. Loop thru args
4493 from first to last. */
4494 for (argnum
= 0; argnum
< nargs
; argnum
++)
4497 struct value
*arg
= args
[argnum
];
4498 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4499 int len
= TYPE_LENGTH (arg_type
);
4500 enum type_code typecode
= TYPE_CODE (arg_type
);
4503 fprintf_unfiltered (gdb_stdlog
,
4504 "mips_o64_push_dummy_call: %d len=%d type=%d",
4505 argnum
+ 1, len
, (int) typecode
);
4507 val
= (char *) VALUE_CONTENTS (arg
);
4509 /* 32-bit ABIs always start floating point arguments in an
4510 even-numbered floating point register. Round the FP register
4511 up before the check to see if there are any FP registers
4512 left. O32/O64 targets also pass the FP in the integer
4513 registers so also round up normal registers. */
4514 if (mips_abi_regsize (gdbarch
) < 8
4515 && fp_register_arg_p (typecode
, arg_type
))
4517 if ((float_argreg
& 1))
4521 /* Floating point arguments passed in registers have to be
4522 treated specially. On 32-bit architectures, doubles
4523 are passed in register pairs; the even register gets
4524 the low word, and the odd register gets the high word.
4525 On O32/O64, the first two floating point arguments are
4526 also copied to general registers, because MIPS16 functions
4527 don't use float registers for arguments. This duplication of
4528 arguments in general registers can't hurt non-MIPS16 functions
4529 because those registers are normally skipped. */
4531 if (fp_register_arg_p (typecode
, arg_type
)
4532 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4534 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4536 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4537 unsigned long regval
;
4539 /* Write the low word of the double to the even register(s). */
4540 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4542 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4543 float_argreg
, phex (regval
, 4));
4544 write_register (float_argreg
++, regval
);
4546 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4547 argreg
, phex (regval
, 4));
4548 write_register (argreg
++, regval
);
4550 /* Write the high word of the double to the odd register(s). */
4551 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4553 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4554 float_argreg
, phex (regval
, 4));
4555 write_register (float_argreg
++, regval
);
4558 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4559 argreg
, phex (regval
, 4));
4560 write_register (argreg
++, regval
);
4564 /* This is a floating point value that fits entirely
4565 in a single register. */
4566 /* On 32 bit ABI's the float_argreg is further adjusted
4567 above to ensure that it is even register aligned. */
4568 LONGEST regval
= extract_unsigned_integer (val
, len
);
4570 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4571 float_argreg
, phex (regval
, len
));
4572 write_register (float_argreg
++, regval
);
4573 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4574 registers for each argument. The below is (my
4575 guess) to ensure that the corresponding integer
4576 register has reserved the same space. */
4578 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4579 argreg
, phex (regval
, len
));
4580 write_register (argreg
, regval
);
4581 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4583 /* Reserve space for the FP register. */
4584 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4588 /* Copy the argument to general registers or the stack in
4589 register-sized pieces. Large arguments are split between
4590 registers and stack. */
4591 /* Note: structs whose size is not a multiple of
4592 mips_abi_regsize() are treated specially: Irix cc passes
4593 them in registers where gcc sometimes puts them on the
4594 stack. For maximum compatibility, we will put them in
4596 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4597 && (len
% mips_abi_regsize (gdbarch
) != 0));
4598 /* Structures should be aligned to eight bytes (even arg registers)
4599 on MIPS_ABI_O32, if their first member has double precision. */
4600 if (mips_abi_regsize (gdbarch
) < 8
4601 && mips_type_needs_double_align (arg_type
))
4606 /* Note: Floating-point values that didn't fit into an FP
4607 register are only written to memory. */
4610 /* Remember if the argument was written to the stack. */
4611 int stack_used_p
= 0;
4612 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4613 ? len
: mips_abi_regsize (gdbarch
));
4616 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4619 /* Write this portion of the argument to the stack. */
4620 if (argreg
> MIPS_LAST_ARG_REGNUM
4622 || fp_register_arg_p (typecode
, arg_type
))
4624 /* Should shorter than int integer values be
4625 promoted to int before being stored? */
4626 int longword_offset
= 0;
4629 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4631 if (mips_stack_argsize (gdbarch
) == 8
4632 && (typecode
== TYPE_CODE_INT
4633 || typecode
== TYPE_CODE_PTR
4634 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4635 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4640 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4641 paddr_nz (stack_offset
));
4642 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4643 paddr_nz (longword_offset
));
4646 addr
= sp
+ stack_offset
+ longword_offset
;
4651 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4653 for (i
= 0; i
< partial_len
; i
++)
4655 fprintf_unfiltered (gdb_stdlog
, "%02x",
4659 write_memory (addr
, val
, partial_len
);
4662 /* Note!!! This is NOT an else clause. Odd sized
4663 structs may go thru BOTH paths. Floating point
4664 arguments will not. */
4665 /* Write this portion of the argument to a general
4666 purpose register. */
4667 if (argreg
<= MIPS_LAST_ARG_REGNUM
4668 && !fp_register_arg_p (typecode
, arg_type
))
4670 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4671 /* Value may need to be sign extended, because
4672 mips_isa_regsize() != mips_abi_regsize(). */
4674 /* A non-floating-point argument being passed in a
4675 general register. If a struct or union, and if
4676 the remaining length is smaller than the register
4677 size, we have to adjust the register value on
4680 It does not seem to be necessary to do the
4681 same for integral types.
4683 Also don't do this adjustment on O64 binaries.
4685 cagney/2001-07-23: gdb/179: Also, GCC, when
4686 outputting LE O32 with sizeof (struct) <
4687 mips_abi_regsize(), generates a left shift as
4688 part of storing the argument in a register a
4689 register (the left shift isn't generated when
4690 sizeof (struct) >= mips_abi_regsize()). Since
4691 it is quite possible that this is GCC
4692 contradicting the LE/O32 ABI, GDB has not been
4693 adjusted to accommodate this. Either someone
4694 needs to demonstrate that the LE/O32 ABI
4695 specifies such a left shift OR this new ABI gets
4696 identified as such and GDB gets tweaked
4699 if (mips_abi_regsize (gdbarch
) < 8
4700 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4701 && partial_len
< mips_abi_regsize (gdbarch
)
4702 && (typecode
== TYPE_CODE_STRUCT
||
4703 typecode
== TYPE_CODE_UNION
))
4704 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4708 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4711 mips_abi_regsize (gdbarch
)));
4712 write_register (argreg
, regval
);
4715 /* Prevent subsequent floating point arguments from
4716 being passed in floating point registers. */
4717 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4723 /* Compute the the offset into the stack at which we
4724 will copy the next parameter.
4726 In older ABIs, the caller reserved space for
4727 registers that contained arguments. This was loosely
4728 refered to as their "home". Consequently, space is
4729 always allocated. */
4731 stack_offset
+= align_up (partial_len
,
4732 mips_stack_argsize (gdbarch
));
4736 fprintf_unfiltered (gdb_stdlog
, "\n");
4739 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4741 /* Return adjusted stack pointer. */
4746 mips_o64_extract_return_value (struct type
*valtype
,
4747 char regbuf
[], char *valbuf
)
4749 struct return_value_word lo
;
4750 struct return_value_word hi
;
4751 return_value_location (valtype
, &hi
, &lo
);
4753 memcpy (valbuf
+ lo
.buf_offset
,
4754 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4755 lo
.reg_offset
, lo
.len
);
4758 memcpy (valbuf
+ hi
.buf_offset
,
4759 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4760 hi
.reg_offset
, hi
.len
);
4764 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4766 char raw_buffer
[MAX_REGISTER_SIZE
];
4767 struct return_value_word lo
;
4768 struct return_value_word hi
;
4769 return_value_location (valtype
, &hi
, &lo
);
4771 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4772 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4773 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4774 raw_buffer
, register_size (current_gdbarch
,
4779 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4780 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4781 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4783 register_size (current_gdbarch
,
4788 /* Floating point register management.
4790 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4791 64bit operations, these early MIPS cpus treat fp register pairs
4792 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4793 registers and offer a compatibility mode that emulates the MIPS2 fp
4794 model. When operating in MIPS2 fp compat mode, later cpu's split
4795 double precision floats into two 32-bit chunks and store them in
4796 consecutive fp regs. To display 64-bit floats stored in this
4797 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4798 Throw in user-configurable endianness and you have a real mess.
4800 The way this works is:
4801 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4802 double-precision value will be split across two logical registers.
4803 The lower-numbered logical register will hold the low-order bits,
4804 regardless of the processor's endianness.
4805 - If we are on a 64-bit processor, and we are looking for a
4806 single-precision value, it will be in the low ordered bits
4807 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4808 save slot in memory.
4809 - If we are in 64-bit mode, everything is straightforward.
4811 Note that this code only deals with "live" registers at the top of the
4812 stack. We will attempt to deal with saved registers later, when
4813 the raw/cooked register interface is in place. (We need a general
4814 interface that can deal with dynamic saved register sizes -- fp
4815 regs could be 32 bits wide in one frame and 64 on the frame above
4818 static struct type
*
4819 mips_float_register_type (void)
4821 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4822 return builtin_type_ieee_single_big
;
4824 return builtin_type_ieee_single_little
;
4827 static struct type
*
4828 mips_double_register_type (void)
4830 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4831 return builtin_type_ieee_double_big
;
4833 return builtin_type_ieee_double_little
;
4836 /* Copy a 32-bit single-precision value from the current frame
4837 into rare_buffer. */
4840 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4843 int raw_size
= register_size (current_gdbarch
, regno
);
4844 char *raw_buffer
= alloca (raw_size
);
4846 if (!frame_register_read (frame
, regno
, raw_buffer
))
4847 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4850 /* We have a 64-bit value for this register. Find the low-order
4854 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4859 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4863 memcpy (rare_buffer
, raw_buffer
, 4);
4867 /* Copy a 64-bit double-precision value from the current frame into
4868 rare_buffer. This may include getting half of it from the next
4872 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4875 int raw_size
= register_size (current_gdbarch
, regno
);
4877 if (raw_size
== 8 && !mips2_fp_compat ())
4879 /* We have a 64-bit value for this register, and we should use
4881 if (!frame_register_read (frame
, regno
, rare_buffer
))
4882 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4886 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4887 internal_error (__FILE__
, __LINE__
,
4888 "mips_read_fp_register_double: bad access to "
4889 "odd-numbered FP register");
4891 /* mips_read_fp_register_single will find the correct 32 bits from
4893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4895 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4896 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4900 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4901 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4907 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4909 { /* do values for FP (float) regs */
4911 double doub
, flt1
; /* doubles extracted from raw hex data */
4915 (char *) alloca (2 *
4916 register_size (current_gdbarch
,
4917 mips_regnum (current_gdbarch
)->fp0
));
4919 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4920 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4923 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4925 /* 4-byte registers: Print hex and floating. Also print even
4926 numbered registers as doubles. */
4927 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4928 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4930 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4933 fprintf_filtered (file
, " flt: ");
4935 fprintf_filtered (file
, " <invalid float> ");
4937 fprintf_filtered (file
, "%-17.9g", flt1
);
4939 if (regnum
% 2 == 0)
4941 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4942 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4945 fprintf_filtered (file
, " dbl: ");
4947 fprintf_filtered (file
, "<invalid double>");
4949 fprintf_filtered (file
, "%-24.17g", doub
);
4954 /* Eight byte registers: print each one as hex, float and double. */
4955 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4956 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4958 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4959 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4962 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4965 fprintf_filtered (file
, " flt: ");
4967 fprintf_filtered (file
, "<invalid float>");
4969 fprintf_filtered (file
, "%-17.9g", flt1
);
4971 fprintf_filtered (file
, " dbl: ");
4973 fprintf_filtered (file
, "<invalid double>");
4975 fprintf_filtered (file
, "%-24.17g", doub
);
4980 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4981 int regnum
, int all
)
4983 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4984 char raw_buffer
[MAX_REGISTER_SIZE
];
4987 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4989 mips_print_fp_register (file
, frame
, regnum
);
4993 /* Get the data in raw format. */
4994 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4996 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5000 fputs_filtered (REGISTER_NAME (regnum
), file
);
5002 /* The problem with printing numeric register names (r26, etc.) is that
5003 the user can't use them on input. Probably the best solution is to
5004 fix it so that either the numeric or the funky (a2, etc.) names
5005 are accepted on input. */
5006 if (regnum
< MIPS_NUMREGS
)
5007 fprintf_filtered (file
, "(r%d): ", regnum
);
5009 fprintf_filtered (file
, ": ");
5011 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5013 register_size (current_gdbarch
,
5014 regnum
) - register_size (current_gdbarch
, regnum
);
5018 print_scalar_formatted (raw_buffer
+ offset
,
5019 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5023 /* Replacement for generic do_registers_info.
5024 Print regs in pretty columns. */
5027 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5030 fprintf_filtered (file
, " ");
5031 mips_print_fp_register (file
, frame
, regnum
);
5032 fprintf_filtered (file
, "\n");
5037 /* Print a row's worth of GP (int) registers, with name labels above */
5040 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5043 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5044 /* do values for GP (int) regs */
5045 char raw_buffer
[MAX_REGISTER_SIZE
];
5046 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5050 /* For GP registers, we print a separate row of names above the vals */
5051 fprintf_filtered (file
, " ");
5052 for (col
= 0, regnum
= start_regnum
;
5053 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5055 if (*REGISTER_NAME (regnum
) == '\0')
5056 continue; /* unused register */
5057 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5059 break; /* end the row: reached FP register */
5060 fprintf_filtered (file
,
5061 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5062 REGISTER_NAME (regnum
));
5065 /* print the R0 to R31 names */
5066 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5067 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5069 fprintf_filtered (file
, "\n ");
5071 /* now print the values in hex, 4 or 8 to the row */
5072 for (col
= 0, regnum
= start_regnum
;
5073 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5075 if (*REGISTER_NAME (regnum
) == '\0')
5076 continue; /* unused register */
5077 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5079 break; /* end row: reached FP register */
5080 /* OK: get the data in raw format. */
5081 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5082 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5083 /* pad small registers */
5085 byte
< (mips_abi_regsize (current_gdbarch
)
5086 - register_size (current_gdbarch
, regnum
)); byte
++)
5087 printf_filtered (" ");
5088 /* Now print the register value in hex, endian order. */
5089 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5091 register_size (current_gdbarch
,
5092 regnum
) - register_size (current_gdbarch
, regnum
);
5093 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5094 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5096 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5098 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5099 fprintf_filtered (file
, " ");
5102 if (col
> 0) /* ie. if we actually printed anything... */
5103 fprintf_filtered (file
, "\n");
5108 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5111 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5112 struct frame_info
*frame
, int regnum
, int all
)
5114 if (regnum
!= -1) /* do one specified register */
5116 gdb_assert (regnum
>= NUM_REGS
);
5117 if (*(REGISTER_NAME (regnum
)) == '\0')
5118 error ("Not a valid register for the current processor type");
5120 mips_print_register (file
, frame
, regnum
, 0);
5121 fprintf_filtered (file
, "\n");
5124 /* do all (or most) registers */
5127 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5129 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5132 if (all
) /* true for "INFO ALL-REGISTERS" command */
5133 regnum
= print_fp_register_row (file
, frame
, regnum
);
5135 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5138 regnum
= print_gp_register_row (file
, frame
, regnum
);
5143 /* Is this a branch with a delay slot? */
5145 static int is_delayed (unsigned long);
5148 is_delayed (unsigned long insn
)
5151 for (i
= 0; i
< NUMOPCODES
; ++i
)
5152 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5153 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5155 return (i
< NUMOPCODES
5156 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5157 | INSN_COND_BRANCH_DELAY
5158 | INSN_COND_BRANCH_LIKELY
)));
5162 mips_step_skips_delay (CORE_ADDR pc
)
5164 char buf
[MIPS_INSTLEN
];
5166 /* There is no branch delay slot on MIPS16. */
5167 if (pc_is_mips16 (pc
))
5170 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5171 /* If error reading memory, guess that it is not a delayed branch. */
5173 return is_delayed ((unsigned long)
5174 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5177 /* Skip the PC past function prologue instructions (32-bit version).
5178 This is a helper function for mips_skip_prologue. */
5181 mips32_skip_prologue (CORE_ADDR pc
)
5185 int seen_sp_adjust
= 0;
5186 int load_immediate_bytes
= 0;
5188 /* Find an upper bound on the prologue. */
5189 end_pc
= skip_prologue_using_sal (pc
);
5191 end_pc
= pc
+ 100; /* Magic. */
5193 /* Skip the typical prologue instructions. These are the stack adjustment
5194 instruction and the instructions that save registers on the stack
5195 or in the gcc frame. */
5196 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5198 unsigned long high_word
;
5200 inst
= mips_fetch_instruction (pc
);
5201 high_word
= (inst
>> 16) & 0xffff;
5203 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5204 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5206 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5207 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5209 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5210 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5211 && (inst
& 0x001F0000)) /* reg != $zero */
5214 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5216 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5218 continue; /* reg != $zero */
5220 /* move $s8,$sp. With different versions of gas this will be either
5221 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5222 Accept any one of these. */
5223 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5226 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5228 else if (high_word
== 0x3c1c) /* lui $gp,n */
5230 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5232 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5233 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5235 /* The following instructions load $at or $t0 with an immediate
5236 value in preparation for a stack adjustment via
5237 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5238 a local variable, so we accept them only before a stack adjustment
5239 instruction was seen. */
5240 else if (!seen_sp_adjust
)
5242 if (high_word
== 0x3c01 || /* lui $at,n */
5243 high_word
== 0x3c08) /* lui $t0,n */
5245 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5248 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5249 high_word
== 0x3508 || /* ori $t0,$t0,n */
5250 high_word
== 0x3401 || /* ori $at,$zero,n */
5251 high_word
== 0x3408) /* ori $t0,$zero,n */
5253 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5263 /* In a frameless function, we might have incorrectly
5264 skipped some load immediate instructions. Undo the skipping
5265 if the load immediate was not followed by a stack adjustment. */
5266 if (load_immediate_bytes
&& !seen_sp_adjust
)
5267 pc
-= load_immediate_bytes
;
5271 /* Skip the PC past function prologue instructions (16-bit version).
5272 This is a helper function for mips_skip_prologue. */
5275 mips16_skip_prologue (CORE_ADDR pc
)
5278 int extend_bytes
= 0;
5279 int prev_extend_bytes
;
5281 /* Table of instructions likely to be found in a function prologue. */
5284 unsigned short inst
;
5285 unsigned short mask
;
5291 , /* addiu $sp,offset */
5294 , /* daddiu $sp,offset */
5297 , /* sw reg,n($sp) */
5300 , /* sd reg,n($sp) */
5303 , /* sw $ra,n($sp) */
5306 , /* sd $ra,n($sp) */
5312 , /* sw $a0-$a3,n($s1) */
5315 , /* move reg,$a0-$a3 */
5318 , /* entry pseudo-op */
5321 , /* addiu $s1,$sp,n */
5323 0, 0} /* end of table marker */
5326 /* Find an upper bound on the prologue. */
5327 end_pc
= skip_prologue_using_sal (pc
);
5329 end_pc
= pc
+ 100; /* Magic. */
5331 /* Skip the typical prologue instructions. These are the stack adjustment
5332 instruction and the instructions that save registers on the stack
5333 or in the gcc frame. */
5334 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5336 unsigned short inst
;
5339 inst
= mips_fetch_instruction (pc
);
5341 /* Normally we ignore an extend instruction. However, if it is
5342 not followed by a valid prologue instruction, we must adjust
5343 the pc back over the extend so that it won't be considered
5344 part of the prologue. */
5345 if ((inst
& 0xf800) == 0xf000) /* extend */
5347 extend_bytes
= MIPS16_INSTLEN
;
5350 prev_extend_bytes
= extend_bytes
;
5353 /* Check for other valid prologue instructions besides extend. */
5354 for (i
= 0; table
[i
].mask
!= 0; i
++)
5355 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5357 if (table
[i
].mask
!= 0) /* it was in table? */
5358 continue; /* ignore it */
5362 /* Return the current pc, adjusted backwards by 2 if
5363 the previous instruction was an extend. */
5364 return pc
- prev_extend_bytes
;
5370 /* To skip prologues, I use this predicate. Returns either PC itself
5371 if the code at PC does not look like a function prologue; otherwise
5372 returns an address that (if we're lucky) follows the prologue. If
5373 LENIENT, then we must skip everything which is involved in setting
5374 up the frame (it's OK to skip more, just so long as we don't skip
5375 anything which might clobber the registers which are being saved.
5376 We must skip more in the case where part of the prologue is in the
5377 delay slot of a non-prologue instruction). */
5380 mips_skip_prologue (CORE_ADDR pc
)
5382 /* See if we can determine the end of the prologue via the symbol table.
5383 If so, then return either PC, or the PC after the prologue, whichever
5386 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5388 if (post_prologue_pc
!= 0)
5389 return max (pc
, post_prologue_pc
);
5391 /* Can't determine prologue from the symbol table, need to examine
5394 if (pc_is_mips16 (pc
))
5395 return mips16_skip_prologue (pc
);
5397 return mips32_skip_prologue (pc
);
5400 /* Root of all "set mips "/"show mips " commands. This will eventually be
5401 used for all MIPS-specific commands. */
5404 show_mips_command (char *args
, int from_tty
)
5406 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5410 set_mips_command (char *args
, int from_tty
)
5413 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5414 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5417 /* Commands to show/set the MIPS FPU type. */
5420 show_mipsfpu_command (char *args
, int from_tty
)
5423 switch (MIPS_FPU_TYPE
)
5425 case MIPS_FPU_SINGLE
:
5426 fpu
= "single-precision";
5428 case MIPS_FPU_DOUBLE
:
5429 fpu
= "double-precision";
5432 fpu
= "absent (none)";
5435 internal_error (__FILE__
, __LINE__
, "bad switch");
5437 if (mips_fpu_type_auto
)
5439 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5443 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5448 set_mipsfpu_command (char *args
, int from_tty
)
5451 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5452 show_mipsfpu_command (args
, from_tty
);
5456 set_mipsfpu_single_command (char *args
, int from_tty
)
5458 struct gdbarch_info info
;
5459 gdbarch_info_init (&info
);
5460 mips_fpu_type
= MIPS_FPU_SINGLE
;
5461 mips_fpu_type_auto
= 0;
5462 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5463 instead of relying on globals. Doing that would let generic code
5464 handle the search for this specific architecture. */
5465 if (!gdbarch_update_p (info
))
5466 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5470 set_mipsfpu_double_command (char *args
, int from_tty
)
5472 struct gdbarch_info info
;
5473 gdbarch_info_init (&info
);
5474 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5475 mips_fpu_type_auto
= 0;
5476 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5477 instead of relying on globals. Doing that would let generic code
5478 handle the search for this specific architecture. */
5479 if (!gdbarch_update_p (info
))
5480 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5484 set_mipsfpu_none_command (char *args
, int from_tty
)
5486 struct gdbarch_info info
;
5487 gdbarch_info_init (&info
);
5488 mips_fpu_type
= MIPS_FPU_NONE
;
5489 mips_fpu_type_auto
= 0;
5490 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5491 instead of relying on globals. Doing that would let generic code
5492 handle the search for this specific architecture. */
5493 if (!gdbarch_update_p (info
))
5494 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5498 set_mipsfpu_auto_command (char *args
, int from_tty
)
5500 mips_fpu_type_auto
= 1;
5503 /* Attempt to identify the particular processor model by reading the
5504 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5505 the relevant processor still exists (it dates back to '94) and
5506 secondly this is not the way to do this. The processor type should
5507 be set by forcing an architecture change. */
5510 deprecated_mips_set_processor_regs_hack (void)
5512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5515 prid
= read_register (PRID_REGNUM
);
5517 if ((prid
& ~0xf) == 0x700)
5518 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5521 /* Just like reinit_frame_cache, but with the right arguments to be
5522 callable as an sfunc. */
5525 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5526 struct cmd_list_element
*c
)
5528 reinit_frame_cache ();
5532 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5534 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5535 mips_extra_func_info_t proc_desc
;
5537 /* Search for the function containing this address. Set the low bit
5538 of the address when searching, in case we were given an even address
5539 that is the start of a 16-bit function. If we didn't do this,
5540 the search would fail because the symbol table says the function
5541 starts at an odd address, i.e. 1 byte past the given address. */
5542 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5543 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5545 /* Make an attempt to determine if this is a 16-bit function. If
5546 the procedure descriptor exists and the address therein is odd,
5547 it's definitely a 16-bit function. Otherwise, we have to just
5548 guess that if the address passed in is odd, it's 16-bits. */
5549 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5550 disassembler needs to be able to locally determine the ISA, and
5551 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5555 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5556 info
->mach
= bfd_mach_mips16
;
5560 if (pc_is_mips16 (memaddr
))
5561 info
->mach
= bfd_mach_mips16
;
5564 /* Round down the instruction address to the appropriate boundary. */
5565 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5567 /* Set the disassembler options. */
5568 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5570 /* Set up the disassembler info, so that we get the right
5571 register names from libopcodes. */
5572 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5573 info
->disassembler_options
= "gpr-names=n32";
5575 info
->disassembler_options
= "gpr-names=64";
5576 info
->flavour
= bfd_target_elf_flavour
;
5579 /* This string is not recognized explicitly by the disassembler,
5580 but it tells the disassembler to not try to guess the ABI from
5581 the bfd elf headers, such that, if the user overrides the ABI
5582 of a program linked as NewABI, the disassembly will follow the
5583 register naming conventions specified by the user. */
5584 info
->disassembler_options
= "gpr-names=32";
5586 /* Call the appropriate disassembler based on the target endian-ness. */
5587 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5588 return print_insn_big_mips (memaddr
, info
);
5590 return print_insn_little_mips (memaddr
, info
);
5593 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5594 counter value to determine whether a 16- or 32-bit breakpoint should be
5595 used. It returns a pointer to a string of bytes that encode a breakpoint
5596 instruction, stores the length of the string to *lenptr, and adjusts pc
5597 (if necessary) to point to the actual memory location where the
5598 breakpoint should be inserted. */
5600 static const unsigned char *
5601 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5603 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5605 if (pc_is_mips16 (*pcptr
))
5607 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5608 *pcptr
= unmake_mips16_addr (*pcptr
);
5609 *lenptr
= sizeof (mips16_big_breakpoint
);
5610 return mips16_big_breakpoint
;
5614 /* The IDT board uses an unusual breakpoint value, and
5615 sometimes gets confused when it sees the usual MIPS
5616 breakpoint instruction. */
5617 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5618 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5619 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5621 *lenptr
= sizeof (big_breakpoint
);
5623 if (strcmp (target_shortname
, "mips") == 0)
5624 return idt_big_breakpoint
;
5625 else if (strcmp (target_shortname
, "ddb") == 0
5626 || strcmp (target_shortname
, "pmon") == 0
5627 || strcmp (target_shortname
, "lsi") == 0)
5628 return pmon_big_breakpoint
;
5630 return big_breakpoint
;
5635 if (pc_is_mips16 (*pcptr
))
5637 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5638 *pcptr
= unmake_mips16_addr (*pcptr
);
5639 *lenptr
= sizeof (mips16_little_breakpoint
);
5640 return mips16_little_breakpoint
;
5644 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5645 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5646 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5648 *lenptr
= sizeof (little_breakpoint
);
5650 if (strcmp (target_shortname
, "mips") == 0)
5651 return idt_little_breakpoint
;
5652 else if (strcmp (target_shortname
, "ddb") == 0
5653 || strcmp (target_shortname
, "pmon") == 0
5654 || strcmp (target_shortname
, "lsi") == 0)
5655 return pmon_little_breakpoint
;
5657 return little_breakpoint
;
5662 /* If PC is in a mips16 call or return stub, return the address of the target
5663 PC, which is either the callee or the caller. There are several
5664 cases which must be handled:
5666 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5667 target PC is in $31 ($ra).
5668 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5669 and the target PC is in $2.
5670 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5671 before the jal instruction, this is effectively a call stub
5672 and the the target PC is in $2. Otherwise this is effectively
5673 a return stub and the target PC is in $18.
5675 See the source code for the stubs in gcc/config/mips/mips16.S for
5678 This function implements the SKIP_TRAMPOLINE_CODE macro.
5682 mips_skip_stub (CORE_ADDR pc
)
5685 CORE_ADDR start_addr
;
5687 /* Find the starting address and name of the function containing the PC. */
5688 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5691 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5692 target PC is in $31 ($ra). */
5693 if (strcmp (name
, "__mips16_ret_sf") == 0
5694 || strcmp (name
, "__mips16_ret_df") == 0)
5695 return read_signed_register (RA_REGNUM
);
5697 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5699 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5700 and the target PC is in $2. */
5701 if (name
[19] >= '0' && name
[19] <= '9')
5702 return read_signed_register (2);
5704 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5705 before the jal instruction, this is effectively a call stub
5706 and the the target PC is in $2. Otherwise this is effectively
5707 a return stub and the target PC is in $18. */
5708 else if (name
[19] == 's' || name
[19] == 'd')
5710 if (pc
== start_addr
)
5712 /* Check if the target of the stub is a compiler-generated
5713 stub. Such a stub for a function bar might have a name
5714 like __fn_stub_bar, and might look like this:
5719 la $1,bar (becomes a lui/addiu pair)
5721 So scan down to the lui/addi and extract the target
5722 address from those two instructions. */
5724 CORE_ADDR target_pc
= read_signed_register (2);
5728 /* See if the name of the target function is __fn_stub_*. */
5729 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5732 if (strncmp (name
, "__fn_stub_", 10) != 0
5733 && strcmp (name
, "etext") != 0
5734 && strcmp (name
, "_etext") != 0)
5737 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5738 The limit on the search is arbitrarily set to 20
5739 instructions. FIXME. */
5740 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5742 inst
= mips_fetch_instruction (target_pc
);
5743 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5744 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5745 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5746 return pc
| (inst
& 0xffff); /* low word */
5749 /* Couldn't find the lui/addui pair, so return stub address. */
5753 /* This is the 'return' part of a call stub. The return
5754 address is in $r18. */
5755 return read_signed_register (18);
5758 return 0; /* not a stub */
5762 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5763 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5766 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5768 CORE_ADDR start_addr
;
5770 /* Find the starting address of the function containing the PC. If the
5771 caller didn't give us a name, look it up at the same time. */
5772 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5776 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5778 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5779 if (name
[19] >= '0' && name
[19] <= '9')
5781 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5782 before the jal instruction, this is effectively a call stub. */
5783 else if (name
[19] == 's' || name
[19] == 'd')
5784 return pc
== start_addr
;
5787 return 0; /* not a stub */
5791 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5792 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5795 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5797 CORE_ADDR start_addr
;
5799 /* Find the starting address of the function containing the PC. */
5800 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5803 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5804 if (strcmp (name
, "__mips16_ret_sf") == 0
5805 || strcmp (name
, "__mips16_ret_df") == 0)
5808 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5809 i.e. after the jal instruction, this is effectively a return stub. */
5810 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5811 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5814 return 0; /* not a stub */
5818 /* Return non-zero if the PC is in a library helper function that
5819 should be ignored. This implements the
5820 DEPRECATED_IGNORE_HELPER_CALL macro. */
5823 mips_ignore_helper (CORE_ADDR pc
)
5827 /* Find the starting address and name of the function containing the PC. */
5828 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5831 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5832 that we want to ignore. */
5833 return (strcmp (name
, "__mips16_ret_sf") == 0
5834 || strcmp (name
, "__mips16_ret_df") == 0);
5838 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5839 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5842 mips_stab_reg_to_regnum (int num
)
5845 if (num
>= 0 && num
< 32)
5847 else if (num
>= 38 && num
< 70)
5848 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5850 regnum
= mips_regnum (current_gdbarch
)->hi
;
5852 regnum
= mips_regnum (current_gdbarch
)->lo
;
5854 /* This will hopefully (eventually) provoke a warning. Should
5855 we be calling complaint() here? */
5856 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5857 return NUM_REGS
+ regnum
;
5861 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5862 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5865 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5868 if (num
>= 0 && num
< 32)
5870 else if (num
>= 32 && num
< 64)
5871 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5873 regnum
= mips_regnum (current_gdbarch
)->hi
;
5875 regnum
= mips_regnum (current_gdbarch
)->lo
;
5877 /* This will hopefully (eventually) provoke a warning. Should we
5878 be calling complaint() here? */
5879 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5880 return NUM_REGS
+ regnum
;
5884 mips_register_sim_regno (int regnum
)
5886 /* Only makes sense to supply raw registers. */
5887 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5888 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5889 decide if it is valid. Should instead define a standard sim/gdb
5890 register numbering scheme. */
5891 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5892 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5895 return LEGACY_SIM_REGNO_IGNORE
;
5899 /* Convert an integer into an address. By first converting the value
5900 into a pointer and then extracting it signed, the address is
5901 guarenteed to be correctly sign extended. */
5904 mips_integer_to_address (struct type
*type
, void *buf
)
5906 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5907 LONGEST val
= unpack_long (type
, buf
);
5908 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5909 return extract_signed_integer (tmp
,
5910 TYPE_LENGTH (builtin_type_void_data_ptr
));
5914 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5916 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5917 const char *name
= bfd_get_section_name (abfd
, sect
);
5919 if (*abip
!= MIPS_ABI_UNKNOWN
)
5922 if (strncmp (name
, ".mdebug.", 8) != 0)
5925 if (strcmp (name
, ".mdebug.abi32") == 0)
5926 *abip
= MIPS_ABI_O32
;
5927 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5928 *abip
= MIPS_ABI_N32
;
5929 else if (strcmp (name
, ".mdebug.abi64") == 0)
5930 *abip
= MIPS_ABI_N64
;
5931 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5932 *abip
= MIPS_ABI_O64
;
5933 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5934 *abip
= MIPS_ABI_EABI32
;
5935 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5936 *abip
= MIPS_ABI_EABI64
;
5938 warning ("unsupported ABI %s.", name
+ 8);
5941 static enum mips_abi
5942 global_mips_abi (void)
5946 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5947 if (mips_abi_strings
[i
] == mips_abi_string
)
5948 return (enum mips_abi
) i
;
5950 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5953 static struct gdbarch
*
5954 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5956 struct gdbarch
*gdbarch
;
5957 struct gdbarch_tdep
*tdep
;
5959 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5961 enum mips_fpu_type fpu_type
;
5963 /* First of all, extract the elf_flags, if available. */
5964 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5965 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5966 else if (arches
!= NULL
)
5967 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5971 fprintf_unfiltered (gdb_stdlog
,
5972 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5974 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5975 switch ((elf_flags
& EF_MIPS_ABI
))
5977 case E_MIPS_ABI_O32
:
5978 found_abi
= MIPS_ABI_O32
;
5980 case E_MIPS_ABI_O64
:
5981 found_abi
= MIPS_ABI_O64
;
5983 case E_MIPS_ABI_EABI32
:
5984 found_abi
= MIPS_ABI_EABI32
;
5986 case E_MIPS_ABI_EABI64
:
5987 found_abi
= MIPS_ABI_EABI64
;
5990 if ((elf_flags
& EF_MIPS_ABI2
))
5991 found_abi
= MIPS_ABI_N32
;
5993 found_abi
= MIPS_ABI_UNKNOWN
;
5997 /* GCC creates a pseudo-section whose name describes the ABI. */
5998 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5999 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6001 /* If we have no useful BFD information, use the ABI from the last
6002 MIPS architecture (if there is one). */
6003 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6004 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6006 /* Try the architecture for any hint of the correct ABI. */
6007 if (found_abi
== MIPS_ABI_UNKNOWN
6008 && info
.bfd_arch_info
!= NULL
6009 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6011 switch (info
.bfd_arch_info
->mach
)
6013 case bfd_mach_mips3900
:
6014 found_abi
= MIPS_ABI_EABI32
;
6016 case bfd_mach_mips4100
:
6017 case bfd_mach_mips5000
:
6018 found_abi
= MIPS_ABI_EABI64
;
6020 case bfd_mach_mips8000
:
6021 case bfd_mach_mips10000
:
6022 /* On Irix, ELF64 executables use the N64 ABI. The
6023 pseudo-sections which describe the ABI aren't present
6024 on IRIX. (Even for executables created by gcc.) */
6025 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6026 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6027 found_abi
= MIPS_ABI_N64
;
6029 found_abi
= MIPS_ABI_N32
;
6035 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6038 /* What has the user specified from the command line? */
6039 wanted_abi
= global_mips_abi ();
6041 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6044 /* Now that we have found what the ABI for this binary would be,
6045 check whether the user is overriding it. */
6046 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6047 mips_abi
= wanted_abi
;
6048 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6049 mips_abi
= found_abi
;
6051 mips_abi
= MIPS_ABI_O32
;
6053 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6056 /* Also used when doing an architecture lookup. */
6058 fprintf_unfiltered (gdb_stdlog
,
6059 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6060 mips64_transfers_32bit_regs_p
);
6062 /* Determine the MIPS FPU type. */
6063 if (!mips_fpu_type_auto
)
6064 fpu_type
= mips_fpu_type
;
6065 else if (info
.bfd_arch_info
!= NULL
6066 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6067 switch (info
.bfd_arch_info
->mach
)
6069 case bfd_mach_mips3900
:
6070 case bfd_mach_mips4100
:
6071 case bfd_mach_mips4111
:
6072 case bfd_mach_mips4120
:
6073 fpu_type
= MIPS_FPU_NONE
;
6075 case bfd_mach_mips4650
:
6076 fpu_type
= MIPS_FPU_SINGLE
;
6079 fpu_type
= MIPS_FPU_DOUBLE
;
6082 else if (arches
!= NULL
)
6083 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6085 fpu_type
= MIPS_FPU_DOUBLE
;
6087 fprintf_unfiltered (gdb_stdlog
,
6088 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6090 /* try to find a pre-existing architecture */
6091 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6093 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6095 /* MIPS needs to be pedantic about which ABI the object is
6097 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6099 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6101 /* Need to be pedantic about which register virtual size is
6103 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6104 != mips64_transfers_32bit_regs_p
)
6106 /* Be pedantic about which FPU is selected. */
6107 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6109 return arches
->gdbarch
;
6112 /* Need a new architecture. Fill in a target specific vector. */
6113 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6114 gdbarch
= gdbarch_alloc (&info
, tdep
);
6115 tdep
->elf_flags
= elf_flags
;
6116 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6117 tdep
->found_abi
= found_abi
;
6118 tdep
->mips_abi
= mips_abi
;
6119 tdep
->mips_fpu_type
= fpu_type
;
6121 /* Initially set everything according to the default ABI/ISA. */
6122 set_gdbarch_short_bit (gdbarch
, 16);
6123 set_gdbarch_int_bit (gdbarch
, 32);
6124 set_gdbarch_float_bit (gdbarch
, 32);
6125 set_gdbarch_double_bit (gdbarch
, 64);
6126 set_gdbarch_long_double_bit (gdbarch
, 64);
6127 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6128 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6129 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6131 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6132 mips_elf_make_msymbol_special
);
6134 /* Fill in the OS dependant register numbers and names. */
6136 const char **reg_names
;
6137 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6138 struct mips_regnum
);
6139 if (info
.osabi
== GDB_OSABI_IRIX
)
6144 regnum
->badvaddr
= 66;
6147 regnum
->fp_control_status
= 69;
6148 regnum
->fp_implementation_revision
= 70;
6150 reg_names
= mips_irix_reg_names
;
6154 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6155 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6156 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6157 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6158 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6159 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6160 regnum
->fp_control_status
= 70;
6161 regnum
->fp_implementation_revision
= 71;
6163 if (info
.bfd_arch_info
!= NULL
6164 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6165 reg_names
= mips_tx39_reg_names
;
6167 reg_names
= mips_generic_reg_names
;
6169 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6170 replaced by read_pc? */
6171 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6172 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6173 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6174 set_gdbarch_num_regs (gdbarch
, num_regs
);
6175 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6176 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6177 tdep
->mips_processor_reg_names
= reg_names
;
6178 tdep
->regnum
= regnum
;
6184 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6185 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6186 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6187 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6188 tdep
->default_mask_address_p
= 0;
6189 set_gdbarch_long_bit (gdbarch
, 32);
6190 set_gdbarch_ptr_bit (gdbarch
, 32);
6191 set_gdbarch_long_long_bit (gdbarch
, 64);
6194 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6195 set_gdbarch_deprecated_store_return_value (gdbarch
,
6196 mips_o64_store_return_value
);
6197 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6198 mips_o64_extract_return_value
);
6199 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6200 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6201 tdep
->default_mask_address_p
= 0;
6202 set_gdbarch_long_bit (gdbarch
, 32);
6203 set_gdbarch_ptr_bit (gdbarch
, 32);
6204 set_gdbarch_long_long_bit (gdbarch
, 64);
6205 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6207 case MIPS_ABI_EABI32
:
6208 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6209 set_gdbarch_deprecated_store_return_value (gdbarch
,
6210 mips_eabi_store_return_value
);
6211 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6212 mips_eabi_extract_return_value
);
6213 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6214 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6215 tdep
->default_mask_address_p
= 0;
6216 set_gdbarch_long_bit (gdbarch
, 32);
6217 set_gdbarch_ptr_bit (gdbarch
, 32);
6218 set_gdbarch_long_long_bit (gdbarch
, 64);
6219 set_gdbarch_deprecated_reg_struct_has_addr
6220 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6221 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6223 case MIPS_ABI_EABI64
:
6224 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6225 set_gdbarch_deprecated_store_return_value (gdbarch
,
6226 mips_eabi_store_return_value
);
6227 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6228 mips_eabi_extract_return_value
);
6229 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6230 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6231 tdep
->default_mask_address_p
= 0;
6232 set_gdbarch_long_bit (gdbarch
, 64);
6233 set_gdbarch_ptr_bit (gdbarch
, 64);
6234 set_gdbarch_long_long_bit (gdbarch
, 64);
6235 set_gdbarch_deprecated_reg_struct_has_addr
6236 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6237 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6240 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6241 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6242 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6243 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6244 tdep
->default_mask_address_p
= 0;
6245 set_gdbarch_long_bit (gdbarch
, 32);
6246 set_gdbarch_ptr_bit (gdbarch
, 32);
6247 set_gdbarch_long_long_bit (gdbarch
, 64);
6248 set_gdbarch_long_double_bit (gdbarch
, 128);
6249 set_gdbarch_long_double_format (gdbarch
,
6250 &floatformat_n32n64_long_double_big
);
6253 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6254 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6255 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6256 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6257 tdep
->default_mask_address_p
= 0;
6258 set_gdbarch_long_bit (gdbarch
, 64);
6259 set_gdbarch_ptr_bit (gdbarch
, 64);
6260 set_gdbarch_long_long_bit (gdbarch
, 64);
6261 set_gdbarch_long_double_bit (gdbarch
, 128);
6262 set_gdbarch_long_double_format (gdbarch
,
6263 &floatformat_n32n64_long_double_big
);
6266 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6269 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6270 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6273 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6274 flag in object files because to do so would make it impossible to
6275 link with libraries compiled without "-gp32". This is
6276 unnecessarily restrictive.
6278 We could solve this problem by adding "-gp32" multilibs to gcc,
6279 but to set this flag before gcc is built with such multilibs will
6280 break too many systems.''
6282 But even more unhelpfully, the default linker output target for
6283 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6284 for 64-bit programs - you need to change the ABI to change this,
6285 and not all gcc targets support that currently. Therefore using
6286 this flag to detect 32-bit mode would do the wrong thing given
6287 the current gcc - it would make GDB treat these 64-bit programs
6288 as 32-bit programs by default. */
6290 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6291 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6292 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6294 /* Add/remove bits from an address. The MIPS needs be careful to
6295 ensure that all 32 bit addresses are sign extended to 64 bits. */
6296 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6298 /* Unwind the frame. */
6299 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6300 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6302 /* Map debug register numbers onto internal register numbers. */
6303 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6304 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6305 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6306 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6307 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6308 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6309 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6310 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6312 /* MIPS version of CALL_DUMMY */
6314 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6315 replaced by a command, and all targets will default to on stack
6316 (regardless of the stack's execute status). */
6317 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6318 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6320 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6321 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6322 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6324 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6325 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6327 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6329 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6330 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6331 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6333 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6335 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6337 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6339 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6340 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6341 need to all be folded into the target vector. Since they are
6342 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6343 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6345 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6347 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6349 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6350 to support MIPS16. This is a bad thing. Make sure not to do it
6351 if we have an OS ABI that actually supports shared libraries, since
6352 shared library support is more important. If we have an OS someday
6353 that supports both shared libraries and MIPS16, we'll have to find
6354 a better place for these. */
6355 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6357 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6358 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6361 /* Hook in OS ABI-specific overrides, if they have been registered. */
6362 gdbarch_init_osabi (info
, gdbarch
);
6364 /* Unwind the frame. */
6365 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6366 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6367 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6368 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6369 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6370 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6371 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6372 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6378 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6380 struct gdbarch_info info
;
6382 /* Force the architecture to update, and (if it's a MIPS architecture)
6383 mips_gdbarch_init will take care of the rest. */
6384 gdbarch_info_init (&info
);
6385 gdbarch_update_p (info
);
6388 /* Print out which MIPS ABI is in use. */
6391 show_mips_abi (char *ignore_args
, int from_tty
)
6393 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6395 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6398 enum mips_abi global_abi
= global_mips_abi ();
6399 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6400 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6402 if (global_abi
== MIPS_ABI_UNKNOWN
)
6404 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6406 else if (global_abi
== actual_abi
)
6408 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6412 /* Probably shouldn't happen... */
6414 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6415 actual_abi_str
, mips_abi_strings
[global_abi
]);
6421 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6423 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6427 int ef_mips_32bitmode
;
6428 /* determine the ISA */
6429 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6447 /* determine the size of a pointer */
6448 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6449 fprintf_unfiltered (file
,
6450 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6452 fprintf_unfiltered (file
,
6453 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6455 fprintf_unfiltered (file
,
6456 "mips_dump_tdep: ef_mips_arch = %d\n",
6458 fprintf_unfiltered (file
,
6459 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6460 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6461 fprintf_unfiltered (file
,
6462 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6463 mips_mask_address_p (tdep
),
6464 tdep
->default_mask_address_p
);
6466 fprintf_unfiltered (file
,
6467 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6468 MIPS_DEFAULT_FPU_TYPE
,
6469 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6470 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6471 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6473 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6474 fprintf_unfiltered (file
,
6475 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6477 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6478 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6479 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6481 fprintf_unfiltered (file
,
6482 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6483 mips_stack_argsize (current_gdbarch
));
6484 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6485 fprintf_unfiltered (file
,
6486 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6487 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6488 fprintf_unfiltered (file
,
6489 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6490 XSTRING (ATTACH_DETACH
));
6491 fprintf_unfiltered (file
,
6492 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6493 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6494 fprintf_unfiltered (file
,
6495 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6496 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6497 fprintf_unfiltered (file
,
6498 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6499 FIRST_EMBED_REGNUM
);
6500 fprintf_unfiltered (file
,
6501 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6502 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6503 fprintf_unfiltered (file
,
6504 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6505 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6506 fprintf_unfiltered (file
,
6507 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6508 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6509 fprintf_unfiltered (file
,
6510 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6512 #ifdef MACHINE_CPROC_FP_OFFSET
6513 fprintf_unfiltered (file
,
6514 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6515 MACHINE_CPROC_FP_OFFSET
);
6517 #ifdef MACHINE_CPROC_PC_OFFSET
6518 fprintf_unfiltered (file
,
6519 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6520 MACHINE_CPROC_PC_OFFSET
);
6522 #ifdef MACHINE_CPROC_SP_OFFSET
6523 fprintf_unfiltered (file
,
6524 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6525 MACHINE_CPROC_SP_OFFSET
);
6527 fprintf_unfiltered (file
,
6528 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6530 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6531 fprintf_unfiltered (file
,
6532 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6533 fprintf_unfiltered (file
,
6534 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6535 fprintf_unfiltered (file
,
6536 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6537 MIPS_LAST_ARG_REGNUM
,
6538 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6539 fprintf_unfiltered (file
,
6540 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6541 fprintf_unfiltered (file
,
6542 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6543 mips_abi_regsize (current_gdbarch
));
6544 fprintf_unfiltered (file
,
6545 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6546 fprintf_unfiltered (file
,
6547 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6548 fprintf_unfiltered (file
,
6549 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6550 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6551 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6552 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6553 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6554 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6555 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6556 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6557 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6558 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6559 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6560 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6562 fprintf_unfiltered (file
,
6563 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6566 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6569 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6571 fprintf_unfiltered (file
,
6572 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6573 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6574 fprintf_unfiltered (file
,
6575 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6576 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6577 fprintf_unfiltered (file
,
6578 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6579 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6580 fprintf_unfiltered (file
,
6581 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6582 SOFTWARE_SINGLE_STEP_P ());
6583 fprintf_unfiltered (file
,
6584 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6585 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6586 #ifdef STACK_END_ADDR
6587 fprintf_unfiltered (file
,
6588 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6591 fprintf_unfiltered (file
,
6592 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6593 XSTRING (STEP_SKIPS_DELAY (PC
)));
6594 fprintf_unfiltered (file
,
6595 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6596 STEP_SKIPS_DELAY_P
);
6597 fprintf_unfiltered (file
,
6598 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6599 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6600 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6601 fprintf_unfiltered (file
,
6602 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6603 fprintf_unfiltered (file
,
6604 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6605 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6606 (TYPE
, CNT
, OTHERTYPE
)));
6608 fprintf_unfiltered (file
,
6609 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6610 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6613 fprintf_unfiltered (file
,
6614 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6616 #ifdef TRACE_FLAVOR_SIZE
6617 fprintf_unfiltered (file
,
6618 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6622 fprintf_unfiltered (file
,
6623 "mips_dump_tdep: TRACE_SET # %s\n",
6624 XSTRING (TRACE_SET (X
, STATE
)));
6626 #ifdef UNUSED_REGNUM
6627 fprintf_unfiltered (file
,
6628 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6630 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6631 fprintf_unfiltered (file
,
6632 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6633 (long) VM_MIN_ADDRESS
);
6634 fprintf_unfiltered (file
,
6635 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6638 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6641 _initialize_mips_tdep (void)
6643 static struct cmd_list_element
*mipsfpulist
= NULL
;
6644 struct cmd_list_element
*c
;
6646 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6647 if (MIPS_ABI_LAST
+ 1
6648 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6649 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6651 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6653 mips_pdr_data
= register_objfile_data ();
6655 /* Add root prefix command for all "set mips"/"show mips" commands */
6656 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6657 "Various MIPS specific commands.",
6658 &setmipscmdlist
, "set mips ", 0, &setlist
);
6660 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6661 "Various MIPS specific commands.",
6662 &showmipscmdlist
, "show mips ", 0, &showlist
);
6664 /* Allow the user to override the saved register size. */
6665 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6668 &mips_abi_regsize_string
, "\
6669 Set size of general purpose registers saved on the stack.\n\
6670 This option can be set to one of:\n\
6671 32 - Force GDB to treat saved GP registers as 32-bit\n\
6672 64 - Force GDB to treat saved GP registers as 64-bit\n\
6673 auto - Allow GDB to use the target's default setting or autodetect the\n\
6674 saved GP register size from information contained in the executable.\n\
6675 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6677 /* Allow the user to override the argument stack size. */
6678 deprecated_add_show_from_set
6679 (add_set_enum_cmd ("stack-arg-size",
6682 &mips_stack_argsize_string
, "\
6683 Set the amount of stack space reserved for each argument.\n\
6684 This option can be set to one of:\n\
6685 32 - Force GDB to allocate 32-bit chunks per argument\n\
6686 64 - Force GDB to allocate 64-bit chunks per argument\n\
6687 auto - Allow GDB to determine the correct setting from the current\n\
6688 target and executable (default)", &setmipscmdlist
),
6691 /* Allow the user to override the ABI. */
6692 c
= add_set_enum_cmd
6693 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6694 "Set the ABI used by this program.\n"
6695 "This option can be set to one of:\n"
6696 " auto - the default ABI associated with the current binary\n"
6698 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6699 set_cmd_sfunc (c
, mips_abi_update
);
6700 add_cmd ("abi", class_obscure
, show_mips_abi
,
6701 "Show ABI in use by MIPS target", &showmipscmdlist
);
6703 /* Let the user turn off floating point and set the fence post for
6704 heuristic_proc_start. */
6706 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6707 "Set use of MIPS floating-point coprocessor.",
6708 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6709 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6710 "Select single-precision MIPS floating-point coprocessor.",
6712 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6713 "Select double-precision MIPS floating-point coprocessor.",
6715 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6716 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6717 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6718 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6719 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6720 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6721 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6722 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6723 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6724 "Select MIPS floating-point coprocessor automatically.",
6726 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6727 "Show current use of MIPS floating-point coprocessor target.",
6730 /* We really would like to have both "0" and "unlimited" work, but
6731 command.c doesn't deal with that. So make it a var_zinteger
6732 because the user can always use "999999" or some such for unlimited. */
6733 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6734 (char *) &heuristic_fence_post
, "\
6735 Set the distance searched for the start of a function.\n\
6736 If you are debugging a stripped executable, GDB needs to search through the\n\
6737 program for the start of a function. This command sets the distance of the\n\
6738 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6739 /* We need to throw away the frame cache when we set this, since it
6740 might change our ability to get backtraces. */
6741 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6742 deprecated_add_show_from_set (c
, &showlist
);
6744 /* Allow the user to control whether the upper bits of 64-bit
6745 addresses should be zeroed. */
6746 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6747 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6748 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6749 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6750 allow GDB to determine the correct value.\n", "\
6751 Zerroing of upper 32 bits of 64-bit address is %s.",
6752 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6754 /* Allow the user to control the size of 32 bit registers within the
6755 raw remote packet. */
6756 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6757 &mips64_transfers_32bit_regs_p
, "\
6758 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6759 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6760 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6761 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6762 64 bits for others. Use \"off\" to disable compatibility mode", "\
6763 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6764 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6766 /* Debug this files internals. */
6767 deprecated_add_show_from_set
6768 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6769 &mips_debug
, "Set mips debugging.\n\
6770 When non-zero, mips specific debugging is enabled.", &setdebuglist
),