1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
118 enum mips_abi mips_abi
;
119 const char *mips_abi_string
;
120 enum mips_fpu_type mips_fpu_type
;
121 int mips_last_arg_regnum
;
122 int mips_last_fp_arg_regnum
;
123 int mips_default_saved_regsize
;
124 int mips_fp_register_double
;
125 int mips_regs_have_home_p
;
126 int mips_default_stack_argsize
;
127 int gdb_target_is_mips64
;
128 int default_mask_address_p
;
133 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
134 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
138 #undef MIPS_LAST_FP_ARG_REGNUM
139 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
143 #undef MIPS_LAST_ARG_REGNUM
144 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
149 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
152 /* Return the currently configured (or set) saved register size. */
155 #undef MIPS_DEFAULT_SAVED_REGSIZE
156 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
157 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
158 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Indicate that the ABI makes use of double-precision registers
177 provided by the FPU (rather than combining pairs of registers to
178 form double-precision values). Do not use "TARGET_IS_MIPS64" to
179 determine if the ABI is using double-precision registers. See also
182 #undef FP_REGISTER_DOUBLE
183 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
186 /* Does the caller allocate a ``home'' for each register used in the
187 function call? The N32 ABI and MIPS_EABI do not, the others do. */
190 #undef MIPS_REGS_HAVE_HOME_P
191 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
192 #elif !defined (MIPS_REGS_HAVE_HOME_P)
193 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
196 /* The amount of space reserved on the stack for registers. This is
197 different to MIPS_SAVED_REGSIZE as it determines the alignment of
198 data allocated after the registers have run out. */
201 #undef MIPS_DEFAULT_STACK_ARGSIZE
202 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
203 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
204 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
207 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
209 static const char *mips_stack_argsize_string
= size_auto
;
212 mips_stack_argsize (void)
214 if (mips_stack_argsize_string
== size_auto
)
215 return MIPS_DEFAULT_STACK_ARGSIZE
;
216 else if (mips_stack_argsize_string
== size_64
)
218 else /* if (mips_stack_argsize_string == size_32) */
223 #undef GDB_TARGET_IS_MIPS64
224 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
228 #undef MIPS_DEFAULT_MASK_ADDRESS_P
229 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
230 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
231 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
234 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
236 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
238 static void mips_print_register (int, int);
240 static mips_extra_func_info_t
241 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
243 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
245 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
247 int mips_set_processor_type (char *);
249 static void mips_show_processor_type_command (char *, int);
251 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
253 static mips_extra_func_info_t
254 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
256 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
257 mips_extra_func_info_t proc_desc
);
259 /* This value is the model of MIPS in use. It is derived from the value
260 of the PrID register. */
262 char *mips_processor_type
;
264 char *tmp_mips_processor_type
;
266 /* The list of available "set mips " and "show mips " commands */
268 static struct cmd_list_element
*setmipscmdlist
= NULL
;
269 static struct cmd_list_element
*showmipscmdlist
= NULL
;
271 /* A set of original names, to be used when restoring back to generic
272 registers from a specific set. */
274 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
275 char **mips_processor_reg_names
= mips_generic_reg_names
;
278 mips_register_name (int i
)
280 return mips_processor_reg_names
[i
];
283 /* Names of IDT R3041 registers. */
285 char *mips_r3041_reg_names
[] = {
286 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
287 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
288 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
289 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
290 "sr", "lo", "hi", "bad", "cause","pc",
291 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
292 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
293 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
294 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
295 "fsr", "fir", "fp", "",
296 "", "", "bus", "ccfg", "", "", "", "",
297 "", "", "port", "cmp", "", "", "epc", "prid",
300 /* Names of IDT R3051 registers. */
302 char *mips_r3051_reg_names
[] = {
303 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
304 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
305 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
306 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
307 "sr", "lo", "hi", "bad", "cause","pc",
308 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
309 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
310 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
311 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
312 "fsr", "fir", "fp", "",
313 "inx", "rand", "elo", "", "ctxt", "", "", "",
314 "", "", "ehi", "", "", "", "epc", "prid",
317 /* Names of IDT R3081 registers. */
319 char *mips_r3081_reg_names
[] = {
320 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
321 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
322 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
323 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
324 "sr", "lo", "hi", "bad", "cause","pc",
325 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
326 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
327 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
328 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
329 "fsr", "fir", "fp", "",
330 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
331 "", "", "ehi", "", "", "", "epc", "prid",
334 /* Names of LSI 33k registers. */
336 char *mips_lsi33k_reg_names
[] = {
337 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
338 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
339 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
340 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
341 "epc", "hi", "lo", "sr", "cause","badvaddr",
342 "dcic", "bpc", "bda", "", "", "", "", "",
343 "", "", "", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
345 "", "", "", "", "", "", "", "",
347 "", "", "", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
354 } mips_processor_type_table
[] = {
355 { "generic", mips_generic_reg_names
},
356 { "r3041", mips_r3041_reg_names
},
357 { "r3051", mips_r3051_reg_names
},
358 { "r3071", mips_r3081_reg_names
},
359 { "r3081", mips_r3081_reg_names
},
360 { "lsi33k", mips_lsi33k_reg_names
},
368 /* Table to translate MIPS16 register field to actual register number. */
369 static int mips16_to_32_reg
[8] =
370 {16, 17, 2, 3, 4, 5, 6, 7};
372 /* Heuristic_proc_start may hunt through the text section for a long
373 time across a 2400 baud serial line. Allows the user to limit this
376 static unsigned int heuristic_fence_post
= 0;
378 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
379 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
380 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
381 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
382 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
383 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
384 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
385 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
386 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
387 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
388 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
389 #define _PROC_MAGIC_ 0x0F0F0F0F
390 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
391 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
393 struct linked_proc_info
395 struct mips_extra_func_info info
;
396 struct linked_proc_info
*next
;
398 *linked_proc_desc_table
= NULL
;
401 mips_print_extra_frame_info (struct frame_info
*fi
)
405 && fi
->extra_info
->proc_desc
406 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
407 printf_filtered (" frame pointer is at %s+%s\n",
408 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
409 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
412 /* Convert between RAW and VIRTUAL registers. The RAW register size
413 defines the remote-gdb packet. */
415 static int mips64_transfers_32bit_regs_p
= 0;
418 mips_register_raw_size (int reg_nr
)
420 if (mips64_transfers_32bit_regs_p
)
421 return REGISTER_VIRTUAL_SIZE (reg_nr
);
422 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
423 && FP_REGISTER_DOUBLE
)
424 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
432 mips_register_convertible (int reg_nr
)
434 if (mips64_transfers_32bit_regs_p
)
437 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
441 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
442 char *raw_buf
, char *virt_buf
)
444 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
446 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
447 TYPE_LENGTH (virtual_type
));
451 TYPE_LENGTH (virtual_type
));
455 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
456 char *virt_buf
, char *raw_buf
)
458 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
459 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
460 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
462 TYPE_LENGTH (virtual_type
));
466 TYPE_LENGTH (virtual_type
));
469 /* Should the upper word of 64-bit addresses be zeroed? */
470 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
473 mips_mask_address_p (void)
475 switch (mask_address_var
)
477 case CMD_AUTO_BOOLEAN_TRUE
:
479 case CMD_AUTO_BOOLEAN_FALSE
:
482 case CMD_AUTO_BOOLEAN_AUTO
:
483 return MIPS_DEFAULT_MASK_ADDRESS_P
;
485 internal_error (__FILE__
, __LINE__
,
486 "mips_mask_address_p: bad switch");
492 show_mask_address (char *cmd
, int from_tty
)
494 switch (mask_address_var
)
496 case CMD_AUTO_BOOLEAN_TRUE
:
497 printf_filtered ("The 32 bit mips address mask is enabled\n");
499 case CMD_AUTO_BOOLEAN_FALSE
:
500 printf_filtered ("The 32 bit mips address mask is disabled\n");
502 case CMD_AUTO_BOOLEAN_AUTO
:
503 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
504 mips_mask_address_p () ? "enabled" : "disabled");
507 internal_error (__FILE__
, __LINE__
,
508 "show_mask_address: bad switch");
513 /* Should call_function allocate stack space for a struct return? */
515 mips_use_struct_convention (int gcc_p
, struct type
*type
)
518 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
520 return 1; /* Structures are returned by ref in extra arg0 */
523 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
526 pc_is_mips16 (bfd_vma memaddr
)
528 struct minimal_symbol
*sym
;
530 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
531 if (IS_MIPS16_ADDR (memaddr
))
534 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
535 the high bit of the info field. Use this to decide if the function is
536 MIPS16 or normal MIPS. */
537 sym
= lookup_minimal_symbol_by_pc (memaddr
);
539 return MSYMBOL_IS_SPECIAL (sym
);
544 /* MIPS believes that the PC has a sign extended value. Perhaphs the
545 all registers should be sign extended for simplicity? */
548 mips_read_pc (int pid
)
550 return read_signed_register_pid (PC_REGNUM
, pid
);
553 /* This returns the PC of the first inst after the prologue. If we can't
554 find the prologue, then return 0. */
557 after_prologue (CORE_ADDR pc
,
558 mips_extra_func_info_t proc_desc
)
560 struct symtab_and_line sal
;
561 CORE_ADDR func_addr
, func_end
;
564 proc_desc
= find_proc_desc (pc
, NULL
);
568 /* If function is frameless, then we need to do it the hard way. I
569 strongly suspect that frameless always means prologueless... */
570 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
571 && PROC_FRAME_OFFSET (proc_desc
) == 0)
575 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
576 return 0; /* Unknown */
578 sal
= find_pc_line (func_addr
, 0);
580 if (sal
.end
< func_end
)
583 /* The line after the prologue is after the end of the function. In this
584 case, tell the caller to find the prologue the hard way. */
589 /* Decode a MIPS32 instruction that saves a register in the stack, and
590 set the appropriate bit in the general register mask or float register mask
591 to indicate which register is saved. This is a helper function
592 for mips_find_saved_regs. */
595 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
596 unsigned long *float_mask
)
600 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
601 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
602 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
604 /* It might be possible to use the instruction to
605 find the offset, rather than the code below which
606 is based on things being in a certain order in the
607 frame, but figuring out what the instruction's offset
608 is relative to might be a little tricky. */
609 reg
= (inst
& 0x001f0000) >> 16;
610 *gen_mask
|= (1 << reg
);
612 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
613 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
614 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
617 reg
= ((inst
& 0x001f0000) >> 16);
618 *float_mask
|= (1 << reg
);
622 /* Decode a MIPS16 instruction that saves a register in the stack, and
623 set the appropriate bit in the general register or float register mask
624 to indicate which register is saved. This is a helper function
625 for mips_find_saved_regs. */
628 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
630 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
632 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
633 *gen_mask
|= (1 << reg
);
635 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
637 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
638 *gen_mask
|= (1 << reg
);
640 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
641 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
642 *gen_mask
|= (1 << RA_REGNUM
);
646 /* Fetch and return instruction from the specified location. If the PC
647 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
650 mips_fetch_instruction (CORE_ADDR addr
)
652 char buf
[MIPS_INSTLEN
];
656 if (pc_is_mips16 (addr
))
658 instlen
= MIPS16_INSTLEN
;
659 addr
= UNMAKE_MIPS16_ADDR (addr
);
662 instlen
= MIPS_INSTLEN
;
663 status
= read_memory_nobpt (addr
, buf
, instlen
);
665 memory_error (status
, addr
);
666 return extract_unsigned_integer (buf
, instlen
);
670 /* These the fields of 32 bit mips instructions */
671 #define mips32_op(x) (x >> 25)
672 #define itype_op(x) (x >> 25)
673 #define itype_rs(x) ((x >> 21)& 0x1f)
674 #define itype_rt(x) ((x >> 16) & 0x1f)
675 #define itype_immediate(x) ( x & 0xffff)
677 #define jtype_op(x) (x >> 25)
678 #define jtype_target(x) ( x & 0x03fffff)
680 #define rtype_op(x) (x >>25)
681 #define rtype_rs(x) ((x>>21) & 0x1f)
682 #define rtype_rt(x) ((x>>16) & 0x1f)
683 #define rtype_rd(x) ((x>>11) & 0x1f)
684 #define rtype_shamt(x) ((x>>6) & 0x1f)
685 #define rtype_funct(x) (x & 0x3f )
688 mips32_relative_offset (unsigned long inst
)
691 x
= itype_immediate (inst
);
692 if (x
& 0x8000) /* sign bit set */
694 x
|= 0xffff0000; /* sign extension */
700 /* Determine whate to set a single step breakpoint while considering
703 mips32_next_pc (CORE_ADDR pc
)
707 inst
= mips_fetch_instruction (pc
);
708 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
710 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
712 op
= ((inst
>> 25) & 0x03);
716 goto equal_branch
; /* BEQL */
718 goto neq_branch
; /* BNEZ */
720 goto less_branch
; /* BLEZ */
722 goto greater_branch
; /* BGTZ */
728 pc
+= 4; /* Not a branch, next instruction is easy */
731 { /* This gets way messy */
733 /* Further subdivide into SPECIAL, REGIMM and other */
734 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
736 case 0: /* SPECIAL */
737 op
= rtype_funct (inst
);
742 /* Set PC to that address */
743 pc
= read_signed_register (rtype_rs (inst
));
749 break; /* end special */
752 op
= jtype_op (inst
); /* branch condition */
753 switch (jtype_op (inst
))
757 case 16: /* BLTZALL */
758 case 18: /* BLTZALL */
760 if (read_signed_register (itype_rs (inst
)) < 0)
761 pc
+= mips32_relative_offset (inst
) + 4;
763 pc
+= 8; /* after the delay slot */
767 case 17: /* BGEZAL */
768 case 19: /* BGEZALL */
769 greater_equal_branch
:
770 if (read_signed_register (itype_rs (inst
)) >= 0)
771 pc
+= mips32_relative_offset (inst
) + 4;
773 pc
+= 8; /* after the delay slot */
775 /* All of the other intructions in the REGIMM catagory */
780 break; /* end REGIMM */
785 reg
= jtype_target (inst
) << 2;
786 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
787 /* Whats this mysterious 0xf000000 adjustment ??? */
790 /* FIXME case JALX : */
793 reg
= jtype_target (inst
) << 2;
794 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
795 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
797 break; /* The new PC will be alternate mode */
798 case 4: /* BEQ , BEQL */
800 if (read_signed_register (itype_rs (inst
)) ==
801 read_signed_register (itype_rt (inst
)))
802 pc
+= mips32_relative_offset (inst
) + 4;
806 case 5: /* BNE , BNEL */
808 if (read_signed_register (itype_rs (inst
)) !=
809 read_signed_register (itype_rs (inst
)))
810 pc
+= mips32_relative_offset (inst
) + 4;
814 case 6: /* BLEZ , BLEZL */
816 if (read_signed_register (itype_rs (inst
) <= 0))
817 pc
+= mips32_relative_offset (inst
) + 4;
822 greater_branch
: /* BGTZ BGTZL */
823 if (read_signed_register (itype_rs (inst
) > 0))
824 pc
+= mips32_relative_offset (inst
) + 4;
833 } /* mips32_next_pc */
835 /* Decoding the next place to set a breakpoint is irregular for the
836 mips 16 variant, but fortunately, there fewer instructions. We have to cope
837 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
838 We dont want to set a single step instruction on the extend instruction
842 /* Lots of mips16 instruction formats */
843 /* Predicting jumps requires itype,ritype,i8type
844 and their extensions extItype,extritype,extI8type
846 enum mips16_inst_fmts
848 itype
, /* 0 immediate 5,10 */
849 ritype
, /* 1 5,3,8 */
850 rrtype
, /* 2 5,3,3,5 */
851 rritype
, /* 3 5,3,3,5 */
852 rrrtype
, /* 4 5,3,3,3,2 */
853 rriatype
, /* 5 5,3,3,1,4 */
854 shifttype
, /* 6 5,3,3,3,2 */
855 i8type
, /* 7 5,3,8 */
856 i8movtype
, /* 8 5,3,3,5 */
857 i8mov32rtype
, /* 9 5,3,5,3 */
858 i64type
, /* 10 5,3,8 */
859 ri64type
, /* 11 5,3,3,5 */
860 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
861 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
862 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
863 extRRItype
, /* 15 5,5,5,5,3,3,5 */
864 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
865 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
866 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
867 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
868 extRi64type
, /* 20 5,6,5,5,3,3,5 */
869 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
871 /* I am heaping all the fields of the formats into one structure and
872 then, only the fields which are involved in instruction extension */
876 unsigned int regx
; /* Function in i8 type */
881 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
882 for the bits which make up the immediatate extension. */
885 extended_offset (unsigned int extension
)
888 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
890 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
892 value
|= extension
& 0x01f; /* extract 4:0 */
896 /* Only call this function if you know that this is an extendable
897 instruction, It wont malfunction, but why make excess remote memory references?
898 If the immediate operands get sign extended or somthing, do it after
899 the extension is performed.
901 /* FIXME: Every one of these cases needs to worry about sign extension
902 when the offset is to be used in relative addressing */
906 fetch_mips_16 (CORE_ADDR pc
)
909 pc
&= 0xfffffffe; /* clear the low order bit */
910 target_read_memory (pc
, buf
, 2);
911 return extract_unsigned_integer (buf
, 2);
915 unpack_mips16 (CORE_ADDR pc
,
916 unsigned int extension
,
918 enum mips16_inst_fmts insn_format
,
919 struct upk_mips16
*upk
)
931 value
= extended_offset (extension
);
932 value
= value
<< 11; /* rom for the original value */
933 value
|= inst
& 0x7ff; /* eleven bits from instruction */
937 value
= inst
& 0x7ff;
938 /* FIXME : Consider sign extension */
947 { /* A register identifier and an offset */
948 /* Most of the fields are the same as I type but the
949 immediate value is of a different length */
953 value
= extended_offset (extension
);
954 value
= value
<< 8; /* from the original instruction */
955 value
|= inst
& 0xff; /* eleven bits from instruction */
956 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
957 if (value
& 0x4000) /* test the sign bit , bit 26 */
959 value
&= ~0x3fff; /* remove the sign bit */
965 value
= inst
& 0xff; /* 8 bits */
966 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
967 /* FIXME: Do sign extension , this format needs it */
968 if (value
& 0x80) /* THIS CONFUSES ME */
970 value
&= 0xef; /* remove the sign bit */
981 unsigned int nexthalf
;
982 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
984 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
992 internal_error (__FILE__
, __LINE__
,
995 upk
->offset
= offset
;
1002 add_offset_16 (CORE_ADDR pc
, int offset
)
1004 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1009 extended_mips16_next_pc (CORE_ADDR pc
,
1010 unsigned int extension
,
1013 int op
= (insn
>> 11);
1016 case 2: /* Branch */
1019 struct upk_mips16 upk
;
1020 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1021 offset
= upk
.offset
;
1027 pc
+= (offset
<< 1) + 2;
1030 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1032 struct upk_mips16 upk
;
1033 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1034 pc
= add_offset_16 (pc
, upk
.offset
);
1035 if ((insn
>> 10) & 0x01) /* Exchange mode */
1036 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1043 struct upk_mips16 upk
;
1045 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1046 reg
= read_signed_register (upk
.regx
);
1048 pc
+= (upk
.offset
<< 1) + 2;
1055 struct upk_mips16 upk
;
1057 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1058 reg
= read_signed_register (upk
.regx
);
1060 pc
+= (upk
.offset
<< 1) + 2;
1065 case 12: /* I8 Formats btez btnez */
1067 struct upk_mips16 upk
;
1069 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1070 /* upk.regx contains the opcode */
1071 reg
= read_signed_register (24); /* Test register is 24 */
1072 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1073 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1074 /* pc = add_offset_16(pc,upk.offset) ; */
1075 pc
+= (upk
.offset
<< 1) + 2;
1080 case 29: /* RR Formats JR, JALR, JALR-RA */
1082 struct upk_mips16 upk
;
1083 /* upk.fmt = rrtype; */
1088 upk
.regx
= (insn
>> 8) & 0x07;
1089 upk
.regy
= (insn
>> 5) & 0x07;
1097 break; /* Function return instruction */
1103 break; /* BOGUS Guess */
1105 pc
= read_signed_register (reg
);
1112 /* This is an instruction extension. Fetch the real instruction
1113 (which follows the extension) and decode things based on
1117 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1130 mips16_next_pc (CORE_ADDR pc
)
1132 unsigned int insn
= fetch_mips_16 (pc
);
1133 return extended_mips16_next_pc (pc
, 0, insn
);
1136 /* The mips_next_pc function supports single_step when the remote
1137 target monitor or stub is not developed enough to do a single_step.
1138 It works by decoding the current instruction and predicting where a
1139 branch will go. This isnt hard because all the data is available.
1140 The MIPS32 and MIPS16 variants are quite different */
1142 mips_next_pc (CORE_ADDR pc
)
1145 return mips16_next_pc (pc
);
1147 return mips32_next_pc (pc
);
1150 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1154 mips_find_saved_regs (struct frame_info
*fci
)
1157 CORE_ADDR reg_position
;
1158 /* r0 bit means kernel trap */
1160 /* What registers have been saved? Bitmasks. */
1161 unsigned long gen_mask
, float_mask
;
1162 mips_extra_func_info_t proc_desc
;
1165 frame_saved_regs_zalloc (fci
);
1167 /* If it is the frame for sigtramp, the saved registers are located
1168 in a sigcontext structure somewhere on the stack.
1169 If the stack layout for sigtramp changes we might have to change these
1170 constants and the companion fixup_sigtramp in mdebugread.c */
1171 #ifndef SIGFRAME_BASE
1172 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1173 above the sigtramp frame. */
1174 #define SIGFRAME_BASE MIPS_REGSIZE
1175 /* FIXME! Are these correct?? */
1176 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1177 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1178 #define SIGFRAME_FPREGSAVE_OFF \
1179 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1181 #ifndef SIGFRAME_REG_SIZE
1182 /* FIXME! Is this correct?? */
1183 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1185 if (fci
->signal_handler_caller
)
1187 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1189 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1190 + ireg
* SIGFRAME_REG_SIZE
;
1191 fci
->saved_regs
[ireg
] = reg_position
;
1193 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1195 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1196 + ireg
* SIGFRAME_REG_SIZE
;
1197 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1199 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1203 proc_desc
= fci
->extra_info
->proc_desc
;
1204 if (proc_desc
== NULL
)
1205 /* I'm not sure how/whether this can happen. Normally when we can't
1206 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1207 and set the saved_regs right away. */
1210 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1211 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1212 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1214 if ( /* In any frame other than the innermost or a frame interrupted by
1215 a signal, we assume that all registers have been saved.
1216 This assumes that all register saves in a function happen before
1217 the first function call. */
1218 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1220 /* In a dummy frame we know exactly where things are saved. */
1221 && !PROC_DESC_IS_DUMMY (proc_desc
)
1223 /* Don't bother unless we are inside a function prologue. Outside the
1224 prologue, we know where everything is. */
1226 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1228 /* Not sure exactly what kernel_trap means, but if it means
1229 the kernel saves the registers without a prologue doing it,
1230 we better not examine the prologue to see whether registers
1231 have been saved yet. */
1234 /* We need to figure out whether the registers that the proc_desc
1235 claims are saved have been saved yet. */
1239 /* Bitmasks; set if we have found a save for the register. */
1240 unsigned long gen_save_found
= 0;
1241 unsigned long float_save_found
= 0;
1244 /* If the address is odd, assume this is MIPS16 code. */
1245 addr
= PROC_LOW_ADDR (proc_desc
);
1246 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1248 /* Scan through this function's instructions preceding the current
1249 PC, and look for those that save registers. */
1250 while (addr
< fci
->pc
)
1252 inst
= mips_fetch_instruction (addr
);
1253 if (pc_is_mips16 (addr
))
1254 mips16_decode_reg_save (inst
, &gen_save_found
);
1256 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1259 gen_mask
= gen_save_found
;
1260 float_mask
= float_save_found
;
1263 /* Fill in the offsets for the registers which gen_mask says
1265 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1266 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1267 if (gen_mask
& 0x80000000)
1269 fci
->saved_regs
[ireg
] = reg_position
;
1270 reg_position
-= MIPS_SAVED_REGSIZE
;
1273 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1274 of that normally used by gcc. Therefore, we have to fetch the first
1275 instruction of the function, and if it's an entry instruction that
1276 saves $s0 or $s1, correct their saved addresses. */
1277 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1279 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1280 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1283 int sreg_count
= (inst
>> 6) & 3;
1285 /* Check if the ra register was pushed on the stack. */
1286 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1288 reg_position
-= MIPS_SAVED_REGSIZE
;
1290 /* Check if the s0 and s1 registers were pushed on the stack. */
1291 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1293 fci
->saved_regs
[reg
] = reg_position
;
1294 reg_position
-= MIPS_SAVED_REGSIZE
;
1299 /* Fill in the offsets for the registers which float_mask says
1301 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1303 /* The freg_offset points to where the first *double* register
1304 is saved. So skip to the high-order word. */
1305 if (!GDB_TARGET_IS_MIPS64
)
1306 reg_position
+= MIPS_SAVED_REGSIZE
;
1308 /* Fill in the offsets for the float registers which float_mask says
1310 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1311 if (float_mask
& 0x80000000)
1313 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1314 reg_position
-= MIPS_SAVED_REGSIZE
;
1317 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1321 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1323 for (; fi
; fi
= fi
->next
)
1325 /* We have to get the saved sp from the sigcontext
1326 if it is a signal handler frame. */
1327 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1331 if (fi
->saved_regs
== NULL
)
1332 mips_find_saved_regs (fi
);
1333 if (fi
->saved_regs
[regno
])
1334 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1337 return read_signed_register (regno
);
1340 /* mips_addr_bits_remove - remove useless address bits */
1343 mips_addr_bits_remove (CORE_ADDR addr
)
1345 if (GDB_TARGET_IS_MIPS64
)
1347 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1349 /* This hack is a work-around for existing boards using
1350 PMON, the simulator, and any other 64-bit targets that
1351 doesn't have true 64-bit addressing. On these targets,
1352 the upper 32 bits of addresses are ignored by the
1353 hardware. Thus, the PC or SP are likely to have been
1354 sign extended to all 1s by instruction sequences that
1355 load 32-bit addresses. For example, a typical piece of
1356 code that loads an address is this:
1357 lui $r2, <upper 16 bits>
1358 ori $r2, <lower 16 bits>
1359 But the lui sign-extends the value such that the upper 32
1360 bits may be all 1s. The workaround is simply to mask off
1361 these bits. In the future, gcc may be changed to support
1362 true 64-bit addressing, and this masking will have to be
1364 addr
&= (CORE_ADDR
) 0xffffffff;
1367 else if (mips_mask_address_p ())
1369 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1370 masking off bits, instead, the actual target should be asking
1371 for the address to be converted to a valid pointer. */
1372 /* Even when GDB is configured for some 32-bit targets
1373 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1374 so CORE_ADDR is 64 bits. So we still have to mask off
1375 useless bits from addresses. */
1376 addr
&= (CORE_ADDR
) 0xffffffff;
1382 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1386 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1387 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1388 tmp
= mips_skip_stub (pc
);
1389 prev
->pc
= tmp
? tmp
: pc
;
1394 mips_frame_saved_pc (struct frame_info
*frame
)
1397 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1398 /* We have to get the saved pc from the sigcontext
1399 if it is a signal handler frame. */
1400 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1401 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1403 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1404 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1406 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1408 return ADDR_BITS_REMOVE (saved_pc
);
1411 static struct mips_extra_func_info temp_proc_desc
;
1412 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1414 /* Set a register's saved stack address in temp_saved_regs. If an address
1415 has already been set for this register, do nothing; this way we will
1416 only recognize the first save of a given register in a function prologue.
1417 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1420 set_reg_offset (int regno
, CORE_ADDR offset
)
1422 if (temp_saved_regs
[regno
] == 0)
1423 temp_saved_regs
[regno
] = offset
;
1427 /* Test whether the PC points to the return instruction at the
1428 end of a function. */
1431 mips_about_to_return (CORE_ADDR pc
)
1433 if (pc_is_mips16 (pc
))
1434 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1435 generates a "jr $ra"; other times it generates code to load
1436 the return address from the stack to an accessible register (such
1437 as $a3), then a "jr" using that register. This second case
1438 is almost impossible to distinguish from an indirect jump
1439 used for switch statements, so we don't even try. */
1440 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1442 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1446 /* This fencepost looks highly suspicious to me. Removing it also
1447 seems suspicious as it could affect remote debugging across serial
1451 heuristic_proc_start (CORE_ADDR pc
)
1458 pc
= ADDR_BITS_REMOVE (pc
);
1460 fence
= start_pc
- heuristic_fence_post
;
1464 if (heuristic_fence_post
== UINT_MAX
1465 || fence
< VM_MIN_ADDRESS
)
1466 fence
= VM_MIN_ADDRESS
;
1468 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1470 /* search back for previous return */
1471 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1472 if (start_pc
< fence
)
1474 /* It's not clear to me why we reach this point when
1475 stop_soon_quietly, but with this test, at least we
1476 don't print out warnings for every child forked (eg, on
1477 decstation). 22apr93 rich@cygnus.com. */
1478 if (!stop_soon_quietly
)
1480 static int blurb_printed
= 0;
1482 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1487 /* This actually happens frequently in embedded
1488 development, when you first connect to a board
1489 and your stack pointer and pc are nowhere in
1490 particular. This message needs to give people
1491 in that situation enough information to
1492 determine that it's no big deal. */
1493 printf_filtered ("\n\
1494 GDB is unable to find the start of the function at 0x%s\n\
1495 and thus can't determine the size of that function's stack frame.\n\
1496 This means that GDB may be unable to access that stack frame, or\n\
1497 the frames below it.\n\
1498 This problem is most likely caused by an invalid program counter or\n\
1500 However, if you think GDB should simply search farther back\n\
1501 from 0x%s for code which looks like the beginning of a\n\
1502 function, you can increase the range of the search using the `set\n\
1503 heuristic-fence-post' command.\n",
1504 paddr_nz (pc
), paddr_nz (pc
));
1511 else if (pc_is_mips16 (start_pc
))
1513 unsigned short inst
;
1515 /* On MIPS16, any one of the following is likely to be the
1516 start of a function:
1520 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1521 inst
= mips_fetch_instruction (start_pc
);
1522 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1523 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1524 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1525 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1527 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1528 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1533 else if (mips_about_to_return (start_pc
))
1535 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1542 /* Fetch the immediate value from a MIPS16 instruction.
1543 If the previous instruction was an EXTEND, use it to extend
1544 the upper bits of the immediate value. This is a helper function
1545 for mips16_heuristic_proc_desc. */
1548 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1549 unsigned short inst
, /* current instruction */
1550 int nbits
, /* number of bits in imm field */
1551 int scale
, /* scale factor to be applied to imm */
1552 int is_signed
) /* is the imm field signed? */
1556 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1558 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1559 if (offset
& 0x8000) /* check for negative extend */
1560 offset
= 0 - (0x10000 - (offset
& 0xffff));
1561 return offset
| (inst
& 0x1f);
1565 int max_imm
= 1 << nbits
;
1566 int mask
= max_imm
- 1;
1567 int sign_bit
= max_imm
>> 1;
1569 offset
= inst
& mask
;
1570 if (is_signed
&& (offset
& sign_bit
))
1571 offset
= 0 - (max_imm
- offset
);
1572 return offset
* scale
;
1577 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1578 stream from start_pc to limit_pc. */
1581 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1582 struct frame_info
*next_frame
, CORE_ADDR sp
)
1585 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1586 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1587 unsigned inst
= 0; /* current instruction */
1588 unsigned entry_inst
= 0; /* the entry instruction */
1591 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1592 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1594 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1596 /* Save the previous instruction. If it's an EXTEND, we'll extract
1597 the immediate offset extension from it in mips16_get_imm. */
1600 /* Fetch and decode the instruction. */
1601 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1602 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1603 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1605 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1606 if (offset
< 0) /* negative stack adjustment? */
1607 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1609 /* Exit loop if a positive stack adjustment is found, which
1610 usually means that the stack cleanup code in the function
1611 epilogue is reached. */
1614 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1616 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1617 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1618 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1619 set_reg_offset (reg
, sp
+ offset
);
1621 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1623 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1624 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1625 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1626 set_reg_offset (reg
, sp
+ offset
);
1628 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1630 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1631 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1632 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1634 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1636 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1637 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1638 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1640 else if (inst
== 0x673d) /* move $s1, $sp */
1643 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1645 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1647 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1648 frame_addr
= sp
+ offset
;
1649 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1650 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1652 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1654 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1655 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1656 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1657 set_reg_offset (reg
, frame_addr
+ offset
);
1659 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1661 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1662 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1663 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1664 set_reg_offset (reg
, frame_addr
+ offset
);
1666 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1667 entry_inst
= inst
; /* save for later processing */
1668 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1669 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1672 /* The entry instruction is typically the first instruction in a function,
1673 and it stores registers at offsets relative to the value of the old SP
1674 (before the prologue). But the value of the sp parameter to this
1675 function is the new SP (after the prologue has been executed). So we
1676 can't calculate those offsets until we've seen the entire prologue,
1677 and can calculate what the old SP must have been. */
1678 if (entry_inst
!= 0)
1680 int areg_count
= (entry_inst
>> 8) & 7;
1681 int sreg_count
= (entry_inst
>> 6) & 3;
1683 /* The entry instruction always subtracts 32 from the SP. */
1684 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1686 /* Now we can calculate what the SP must have been at the
1687 start of the function prologue. */
1688 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1690 /* Check if a0-a3 were saved in the caller's argument save area. */
1691 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1693 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1694 set_reg_offset (reg
, sp
+ offset
);
1695 offset
+= MIPS_SAVED_REGSIZE
;
1698 /* Check if the ra register was pushed on the stack. */
1700 if (entry_inst
& 0x20)
1702 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1703 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1704 offset
-= MIPS_SAVED_REGSIZE
;
1707 /* Check if the s0 and s1 registers were pushed on the stack. */
1708 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1710 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1711 set_reg_offset (reg
, sp
+ offset
);
1712 offset
-= MIPS_SAVED_REGSIZE
;
1718 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1719 struct frame_info
*next_frame
, CORE_ADDR sp
)
1722 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1724 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1725 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1726 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1727 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1729 unsigned long inst
, high_word
, low_word
;
1732 /* Fetch the instruction. */
1733 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1735 /* Save some code by pre-extracting some useful fields. */
1736 high_word
= (inst
>> 16) & 0xffff;
1737 low_word
= inst
& 0xffff;
1738 reg
= high_word
& 0x1f;
1740 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1741 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1742 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1744 if (low_word
& 0x8000) /* negative stack adjustment? */
1745 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1747 /* Exit loop if a positive stack adjustment is found, which
1748 usually means that the stack cleanup code in the function
1749 epilogue is reached. */
1752 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1754 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1755 set_reg_offset (reg
, sp
+ low_word
);
1757 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1759 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1760 but the register size used is only 32 bits. Make the address
1761 for the saved register point to the lower 32 bits. */
1762 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1763 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1765 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1767 /* Old gcc frame, r30 is virtual frame pointer. */
1768 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1769 frame_addr
= sp
+ low_word
;
1770 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1772 unsigned alloca_adjust
;
1773 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1774 frame_addr
= read_next_frame_reg (next_frame
, 30);
1775 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1776 if (alloca_adjust
> 0)
1778 /* FP > SP + frame_size. This may be because
1779 * of an alloca or somethings similar.
1780 * Fix sp to "pre-alloca" value, and try again.
1782 sp
+= alloca_adjust
;
1787 /* move $30,$sp. With different versions of gas this will be either
1788 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1789 Accept any one of these. */
1790 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1792 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1793 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1795 unsigned alloca_adjust
;
1796 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1797 frame_addr
= read_next_frame_reg (next_frame
, 30);
1798 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1799 if (alloca_adjust
> 0)
1801 /* FP > SP + frame_size. This may be because
1802 * of an alloca or somethings similar.
1803 * Fix sp to "pre-alloca" value, and try again.
1805 sp
+= alloca_adjust
;
1810 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1812 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1813 set_reg_offset (reg
, frame_addr
+ low_word
);
1818 static mips_extra_func_info_t
1819 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1820 struct frame_info
*next_frame
)
1822 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1826 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1827 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1828 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1829 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1830 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1832 if (start_pc
+ 200 < limit_pc
)
1833 limit_pc
= start_pc
+ 200;
1834 if (pc_is_mips16 (start_pc
))
1835 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1837 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1838 return &temp_proc_desc
;
1841 static mips_extra_func_info_t
1842 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1844 CORE_ADDR startaddr
;
1845 mips_extra_func_info_t proc_desc
;
1846 struct block
*b
= block_for_pc (pc
);
1849 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1851 *addrptr
= startaddr
;
1852 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1856 if (startaddr
> BLOCK_START (b
))
1857 /* This is the "pathological" case referred to in a comment in
1858 print_frame_info. It might be better to move this check into
1862 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1865 /* If we never found a PDR for this function in symbol reading, then
1866 examine prologues to find the information. */
1869 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1870 if (PROC_FRAME_REG (proc_desc
) == -1)
1880 static mips_extra_func_info_t
1881 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
1883 mips_extra_func_info_t proc_desc
;
1884 CORE_ADDR startaddr
;
1886 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1890 /* IF this is the topmost frame AND
1891 * (this proc does not have debugging information OR
1892 * the PC is in the procedure prologue)
1893 * THEN create a "heuristic" proc_desc (by analyzing
1894 * the actual code) to replace the "official" proc_desc.
1896 if (next_frame
== NULL
)
1898 struct symtab_and_line val
;
1899 struct symbol
*proc_symbol
=
1900 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1904 val
= find_pc_line (BLOCK_START
1905 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1907 val
.pc
= val
.end
? val
.end
: pc
;
1909 if (!proc_symbol
|| pc
< val
.pc
)
1911 mips_extra_func_info_t found_heuristic
=
1912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1914 if (found_heuristic
)
1915 proc_desc
= found_heuristic
;
1921 /* Is linked_proc_desc_table really necessary? It only seems to be used
1922 by procedure call dummys. However, the procedures being called ought
1923 to have their own proc_descs, and even if they don't,
1924 heuristic_proc_desc knows how to create them! */
1926 register struct linked_proc_info
*link
;
1928 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1929 if (PROC_LOW_ADDR (&link
->info
) <= pc
1930 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1934 startaddr
= heuristic_proc_start (pc
);
1937 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1943 get_frame_pointer (struct frame_info
*frame
,
1944 mips_extra_func_info_t proc_desc
)
1946 return ADDR_BITS_REMOVE (
1947 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1948 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1951 mips_extra_func_info_t cached_proc_desc
;
1954 mips_frame_chain (struct frame_info
*frame
)
1956 mips_extra_func_info_t proc_desc
;
1958 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1960 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1963 /* Check if the PC is inside a call stub. If it is, fetch the
1964 PC of the caller of that stub. */
1965 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1968 /* Look up the procedure descriptor for this PC. */
1969 proc_desc
= find_proc_desc (saved_pc
, frame
);
1973 cached_proc_desc
= proc_desc
;
1975 /* If no frame pointer and frame size is zero, we must be at end
1976 of stack (or otherwise hosed). If we don't check frame size,
1977 we loop forever if we see a zero size frame. */
1978 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1979 && PROC_FRAME_OFFSET (proc_desc
) == 0
1980 /* The previous frame from a sigtramp frame might be frameless
1981 and have frame size zero. */
1982 && !frame
->signal_handler_caller
)
1985 return get_frame_pointer (frame
, proc_desc
);
1989 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
1993 /* Use proc_desc calculated in frame_chain */
1994 mips_extra_func_info_t proc_desc
=
1995 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1997 fci
->extra_info
= (struct frame_extra_info
*)
1998 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2000 fci
->saved_regs
= NULL
;
2001 fci
->extra_info
->proc_desc
=
2002 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2005 /* Fixup frame-pointer - only needed for top frame */
2006 /* This may not be quite right, if proc has a real frame register.
2007 Get the value of the frame relative sp, procedure might have been
2008 interrupted by a signal at it's very start. */
2009 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2010 && !PROC_DESC_IS_DUMMY (proc_desc
))
2011 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2013 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2015 if (proc_desc
== &temp_proc_desc
)
2019 /* Do not set the saved registers for a sigtramp frame,
2020 mips_find_saved_registers will do that for us.
2021 We can't use fci->signal_handler_caller, it is not yet set. */
2022 find_pc_partial_function (fci
->pc
, &name
,
2023 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2024 if (!IN_SIGTRAMP (fci
->pc
, name
))
2026 frame_saved_regs_zalloc (fci
);
2027 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2028 fci
->saved_regs
[PC_REGNUM
]
2029 = fci
->saved_regs
[RA_REGNUM
];
2033 /* hack: if argument regs are saved, guess these contain args */
2034 /* assume we can't tell how many args for now */
2035 fci
->extra_info
->num_args
= -1;
2036 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2038 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2040 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2047 /* MIPS stack frames are almost impenetrable. When execution stops,
2048 we basically have to look at symbol information for the function
2049 that we stopped in, which tells us *which* register (if any) is
2050 the base of the frame pointer, and what offset from that register
2051 the frame itself is at.
2053 This presents a problem when trying to examine a stack in memory
2054 (that isn't executing at the moment), using the "frame" command. We
2055 don't have a PC, nor do we have any registers except SP.
2057 This routine takes two arguments, SP and PC, and tries to make the
2058 cached frames look as if these two arguments defined a frame on the
2059 cache. This allows the rest of info frame to extract the important
2060 arguments without difficulty. */
2063 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2066 error ("MIPS frame specifications require two arguments: sp and pc");
2068 return create_new_frame (argv
[0], argv
[1]);
2071 /* According to the current ABI, should the type be passed in a
2072 floating-point register (assuming that there is space)? When there
2073 is no FPU, FP are not even considered as possibile candidates for
2074 FP registers and, consequently this returns false - forces FP
2075 arguments into integer registers. */
2078 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2080 return ((typecode
== TYPE_CODE_FLT
2082 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2083 && TYPE_NFIELDS (arg_type
) == 1
2084 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2085 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2089 mips_push_arguments (int nargs
,
2093 CORE_ADDR struct_addr
)
2099 int stack_offset
= 0;
2101 /* Macros to round N up or down to the next A boundary; A must be
2103 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2104 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2106 /* First ensure that the stack and structure return address (if any)
2107 are properly aligned. The stack has to be at least 64-bit aligned
2108 even on 32-bit machines, because doubles must be 64-bit aligned.
2109 On at least one MIPS variant, stack frames need to be 128-bit
2110 aligned, so we round to this widest known alignment. */
2111 sp
= ROUND_DOWN (sp
, 16);
2112 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2114 /* Now make space on the stack for the args. We allocate more
2115 than necessary for EABI, because the first few arguments are
2116 passed in registers, but that's OK. */
2117 for (argnum
= 0; argnum
< nargs
; argnum
++)
2118 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2119 sp
-= ROUND_UP (len
, 16);
2122 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2123 (long) sp
, ROUND_UP (len
, 16));
2125 /* Initialize the integer and float register pointers. */
2127 float_argreg
= FPA0_REGNUM
;
2129 /* the struct_return pointer occupies the first parameter-passing reg */
2133 fprintf_unfiltered (gdb_stdlog
,
2134 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2135 argreg
, (long) struct_addr
);
2136 write_register (argreg
++, struct_addr
);
2137 if (MIPS_REGS_HAVE_HOME_P
)
2138 stack_offset
+= MIPS_STACK_ARGSIZE
;
2141 /* Now load as many as possible of the first arguments into
2142 registers, and push the rest onto the stack. Loop thru args
2143 from first to last. */
2144 for (argnum
= 0; argnum
< nargs
; argnum
++)
2147 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2148 value_ptr arg
= args
[argnum
];
2149 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2150 int len
= TYPE_LENGTH (arg_type
);
2151 enum type_code typecode
= TYPE_CODE (arg_type
);
2154 fprintf_unfiltered (gdb_stdlog
,
2155 "mips_push_arguments: %d len=%d type=%d",
2156 argnum
+ 1, len
, (int) typecode
);
2158 /* The EABI passes structures that do not fit in a register by
2159 reference. In all other cases, pass the structure by value. */
2161 && len
> MIPS_SAVED_REGSIZE
2162 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2164 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2165 typecode
= TYPE_CODE_PTR
;
2166 len
= MIPS_SAVED_REGSIZE
;
2169 fprintf_unfiltered (gdb_stdlog
, " push");
2172 val
= (char *) VALUE_CONTENTS (arg
);
2174 /* 32-bit ABIs always start floating point arguments in an
2175 even-numbered floating point register. Round the FP register
2176 up before the check to see if there are any FP registers
2177 left. Non MIPS_EABI targets also pass the FP in the integer
2178 registers so also round up normal registers. */
2179 if (!FP_REGISTER_DOUBLE
2180 && fp_register_arg_p (typecode
, arg_type
))
2182 if ((float_argreg
& 1))
2186 /* Floating point arguments passed in registers have to be
2187 treated specially. On 32-bit architectures, doubles
2188 are passed in register pairs; the even register gets
2189 the low word, and the odd register gets the high word.
2190 On non-EABI processors, the first two floating point arguments are
2191 also copied to general registers, because MIPS16 functions
2192 don't use float registers for arguments. This duplication of
2193 arguments in general registers can't hurt non-MIPS16 functions
2194 because those registers are normally skipped. */
2195 /* MIPS_EABI squeeses a struct that contains a single floating
2196 point value into an FP register instead of pusing it onto the
2198 if (fp_register_arg_p (typecode
, arg_type
)
2199 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2201 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2203 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2204 unsigned long regval
;
2206 /* Write the low word of the double to the even register(s). */
2207 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2209 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2210 float_argreg
, phex (regval
, 4));
2211 write_register (float_argreg
++, regval
);
2215 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2216 argreg
, phex (regval
, 4));
2217 write_register (argreg
++, regval
);
2220 /* Write the high word of the double to the odd register(s). */
2221 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2223 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2224 float_argreg
, phex (regval
, 4));
2225 write_register (float_argreg
++, regval
);
2229 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2230 argreg
, phex (regval
, 4));
2231 write_register (argreg
++, regval
);
2237 /* This is a floating point value that fits entirely
2238 in a single register. */
2239 /* On 32 bit ABI's the float_argreg is further adjusted
2240 above to ensure that it is even register aligned. */
2241 LONGEST regval
= extract_unsigned_integer (val
, len
);
2243 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2244 float_argreg
, phex (regval
, len
));
2245 write_register (float_argreg
++, regval
);
2248 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2249 registers for each argument. The below is (my
2250 guess) to ensure that the corresponding integer
2251 register has reserved the same space. */
2253 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2254 argreg
, phex (regval
, len
));
2255 write_register (argreg
, regval
);
2256 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2259 /* Reserve space for the FP register. */
2260 if (MIPS_REGS_HAVE_HOME_P
)
2261 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2265 /* Copy the argument to general registers or the stack in
2266 register-sized pieces. Large arguments are split between
2267 registers and stack. */
2268 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2269 are treated specially: Irix cc passes them in registers
2270 where gcc sometimes puts them on the stack. For maximum
2271 compatibility, we will put them in both places. */
2272 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2273 (len
% MIPS_SAVED_REGSIZE
!= 0));
2274 /* Note: Floating-point values that didn't fit into an FP
2275 register are only written to memory. */
2278 /* Rememer if the argument was written to the stack. */
2279 int stack_used_p
= 0;
2280 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2283 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2286 /* Write this portion of the argument to the stack. */
2287 if (argreg
> MIPS_LAST_ARG_REGNUM
2289 || fp_register_arg_p (typecode
, arg_type
))
2291 /* Should shorter than int integer values be
2292 promoted to int before being stored? */
2293 int longword_offset
= 0;
2296 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2298 if (MIPS_STACK_ARGSIZE
== 8 &&
2299 (typecode
== TYPE_CODE_INT
||
2300 typecode
== TYPE_CODE_PTR
||
2301 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2302 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2303 else if ((typecode
== TYPE_CODE_STRUCT
||
2304 typecode
== TYPE_CODE_UNION
) &&
2305 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2306 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2311 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2312 (long) stack_offset
);
2313 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2314 (long) longword_offset
);
2317 addr
= sp
+ stack_offset
+ longword_offset
;
2322 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2323 for (i
= 0; i
< partial_len
; i
++)
2325 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2328 write_memory (addr
, val
, partial_len
);
2331 /* Note!!! This is NOT an else clause. Odd sized
2332 structs may go thru BOTH paths. Floating point
2333 arguments will not. */
2334 /* Write this portion of the argument to a general
2335 purpose register. */
2336 if (argreg
<= MIPS_LAST_ARG_REGNUM
2337 && !fp_register_arg_p (typecode
, arg_type
))
2339 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2341 /* A non-floating-point argument being passed in a
2342 general register. If a struct or union, and if
2343 the remaining length is smaller than the register
2344 size, we have to adjust the register value on
2347 It does not seem to be necessary to do the
2348 same for integral types.
2350 Also don't do this adjustment on EABI and O64
2354 && MIPS_SAVED_REGSIZE
< 8
2355 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2356 && partial_len
< MIPS_SAVED_REGSIZE
2357 && (typecode
== TYPE_CODE_STRUCT
||
2358 typecode
== TYPE_CODE_UNION
))
2359 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2363 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2365 phex (regval
, MIPS_SAVED_REGSIZE
));
2366 write_register (argreg
, regval
);
2369 /* If this is the old ABI, prevent subsequent floating
2370 point arguments from being passed in floating point
2373 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2379 /* Compute the the offset into the stack at which we
2380 will copy the next parameter.
2382 In older ABIs, the caller reserved space for
2383 registers that contained arguments. This was loosely
2384 refered to as their "home". Consequently, space is
2387 In the new EABI (and the NABI32), the stack_offset
2388 only needs to be adjusted when it has been used.. */
2390 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2391 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2395 fprintf_unfiltered (gdb_stdlog
, "\n");
2398 /* Return adjusted stack pointer. */
2403 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2405 /* Set the return address register to point to the entry
2406 point of the program, where a breakpoint lies in wait. */
2407 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2412 mips_push_register (CORE_ADDR
* sp
, int regno
)
2414 char buffer
[MAX_REGISTER_RAW_SIZE
];
2417 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2419 regsize
= MIPS_SAVED_REGSIZE
;
2420 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2421 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2426 regsize
= REGISTER_RAW_SIZE (regno
);
2430 read_register_gen (regno
, buffer
);
2431 write_memory (*sp
, buffer
+ offset
, regsize
);
2434 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2435 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2438 mips_push_dummy_frame (void)
2441 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2442 xmalloc (sizeof (struct linked_proc_info
));
2443 mips_extra_func_info_t proc_desc
= &link
->info
;
2444 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2445 CORE_ADDR old_sp
= sp
;
2446 link
->next
= linked_proc_desc_table
;
2447 linked_proc_desc_table
= link
;
2449 /* FIXME! are these correct ? */
2450 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2451 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2452 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2453 #define FLOAT_SINGLE_REG_SAVE_MASK \
2454 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2456 * The registers we must save are all those not preserved across
2457 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2458 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2459 * and FP Control/Status registers.
2462 * Dummy frame layout:
2465 * Saved MMHI, MMLO, FPC_CSR
2470 * Saved D18 (i.e. F19, F18)
2472 * Saved D0 (i.e. F1, F0)
2473 * Argument build area and stack arguments written via mips_push_arguments
2477 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2478 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2479 PROC_FRAME_OFFSET (proc_desc
) = 0;
2480 PROC_FRAME_ADJUST (proc_desc
) = 0;
2481 mips_push_register (&sp
, PC_REGNUM
);
2482 mips_push_register (&sp
, HI_REGNUM
);
2483 mips_push_register (&sp
, LO_REGNUM
);
2484 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2486 /* Save general CPU registers */
2487 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2488 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2489 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2490 for (ireg
= 32; --ireg
>= 0;)
2491 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2492 mips_push_register (&sp
, ireg
);
2494 /* Save floating point registers starting with high order word */
2495 PROC_FREG_MASK (proc_desc
) =
2496 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2497 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2498 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2500 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2501 for (ireg
= 32; --ireg
>= 0;)
2502 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2503 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2505 /* Update the frame pointer for the call dummy and the stack pointer.
2506 Set the procedure's starting and ending addresses to point to the
2507 call dummy address at the entry point. */
2508 write_register (PUSH_FP_REGNUM
, old_sp
);
2509 write_register (SP_REGNUM
, sp
);
2510 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2511 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2512 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2513 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2517 mips_pop_frame (void)
2519 register int regnum
;
2520 struct frame_info
*frame
= get_current_frame ();
2521 CORE_ADDR new_sp
= FRAME_FP (frame
);
2523 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2525 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2526 if (frame
->saved_regs
== NULL
)
2527 mips_find_saved_regs (frame
);
2528 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2530 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2531 && frame
->saved_regs
[regnum
])
2532 write_register (regnum
,
2533 read_memory_integer (frame
->saved_regs
[regnum
],
2534 MIPS_SAVED_REGSIZE
));
2536 write_register (SP_REGNUM
, new_sp
);
2537 flush_cached_frames ();
2539 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2541 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2543 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2545 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2547 if (&pi_ptr
->info
== proc_desc
)
2552 error ("Can't locate dummy extra frame info\n");
2554 if (prev_ptr
!= NULL
)
2555 prev_ptr
->next
= pi_ptr
->next
;
2557 linked_proc_desc_table
= pi_ptr
->next
;
2561 write_register (HI_REGNUM
,
2562 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2563 MIPS_SAVED_REGSIZE
));
2564 write_register (LO_REGNUM
,
2565 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2566 MIPS_SAVED_REGSIZE
));
2567 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2568 write_register (FCRCS_REGNUM
,
2569 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2570 MIPS_SAVED_REGSIZE
));
2575 mips_print_register (int regnum
, int all
)
2577 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2579 /* Get the data in raw format. */
2580 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2582 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2586 /* If an even floating point register, also print as double. */
2587 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2588 && !((regnum
- FP0_REGNUM
) & 1))
2589 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2591 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2593 read_relative_register_raw_bytes (regnum
, dbuffer
);
2594 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2595 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2597 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2598 val_print (builtin_type_double
, dbuffer
, 0, 0,
2599 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2600 printf_filtered ("); ");
2602 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2604 /* The problem with printing numeric register names (r26, etc.) is that
2605 the user can't use them on input. Probably the best solution is to
2606 fix it so that either the numeric or the funky (a2, etc.) names
2607 are accepted on input. */
2608 if (regnum
< MIPS_NUMREGS
)
2609 printf_filtered ("(r%d): ", regnum
);
2611 printf_filtered (": ");
2613 /* If virtual format is floating, print it that way. */
2614 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2615 if (FP_REGISTER_DOUBLE
)
2616 { /* show 8-byte floats as float AND double: */
2617 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2619 printf_filtered (" (float) ");
2620 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2621 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2622 printf_filtered (", (double) ");
2623 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2624 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2627 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2628 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2629 /* Else print as integer in hex. */
2634 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2635 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2639 print_scalar_formatted (raw_buffer
+ offset
,
2640 REGISTER_VIRTUAL_TYPE (regnum
),
2641 'x', 0, gdb_stdout
);
2645 /* Replacement for generic do_registers_info.
2646 Print regs in pretty columns. */
2649 do_fp_register_row (int regnum
)
2650 { /* do values for FP (float) regs */
2651 char *raw_buffer
[2];
2653 /* use HI and LO to control the order of combining two flt regs */
2654 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2655 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2656 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2657 int inv1
, inv2
, inv3
;
2659 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2660 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2661 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2663 /* Get the data in raw format. */
2664 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2665 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2666 if (REGISTER_RAW_SIZE (regnum
) == 4)
2668 /* 4-byte registers: we can fit two registers per row. */
2669 /* Also print every pair of 4-byte regs as an 8-byte double. */
2670 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2671 error ("can't read register %d (%s)",
2672 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2674 /* copy the two floats into one double, and unpack both */
2675 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2676 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2677 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2678 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2680 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
2682 printf_filtered (": <invalid float>");
2684 printf_filtered ("%-17.9g", flt1
);
2686 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
2688 printf_filtered (": <invalid float>");
2690 printf_filtered ("%-17.9g", flt2
);
2692 printf_filtered (" dbl: ");
2694 printf_filtered ("<invalid double>");
2696 printf_filtered ("%-24.17g", doub
);
2697 printf_filtered ("\n");
2699 /* may want to do hex display here (future enhancement) */
2703 { /* eight byte registers: print each one as float AND as double. */
2704 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2706 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2707 flt1
= unpack_double (builtin_type_float
,
2708 &raw_buffer
[HI
][offset
], &inv1
);
2709 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2711 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
2713 printf_filtered ("<invalid float>");
2715 printf_filtered ("flt: %-17.9g", flt1
);
2717 printf_filtered (" dbl: ");
2719 printf_filtered ("<invalid double>");
2721 printf_filtered ("%-24.17g", doub
);
2723 printf_filtered ("\n");
2724 /* may want to do hex display here (future enhancement) */
2730 /* Print a row's worth of GP (int) registers, with name labels above */
2733 do_gp_register_row (int regnum
)
2735 /* do values for GP (int) regs */
2736 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2737 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2739 int start_regnum
= regnum
;
2740 int numregs
= NUM_REGS
;
2743 /* For GP registers, we print a separate row of names above the vals */
2744 printf_filtered (" ");
2745 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2747 if (*REGISTER_NAME (regnum
) == '\0')
2748 continue; /* unused register */
2749 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2750 break; /* end the row: reached FP register */
2751 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2752 REGISTER_NAME (regnum
));
2755 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2756 start_regnum
); /* print the R0 to R31 names */
2758 regnum
= start_regnum
; /* go back to start of row */
2759 /* now print the values in hex, 4 or 8 to the row */
2760 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2762 if (*REGISTER_NAME (regnum
) == '\0')
2763 continue; /* unused register */
2764 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2765 break; /* end row: reached FP register */
2766 /* OK: get the data in raw format. */
2767 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2768 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2769 /* pad small registers */
2770 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2771 printf_filtered (" ");
2772 /* Now print the register value in hex, endian order. */
2773 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2774 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2775 byte
< REGISTER_RAW_SIZE (regnum
);
2777 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2779 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2782 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2783 printf_filtered (" ");
2786 if (col
> 0) /* ie. if we actually printed anything... */
2787 printf_filtered ("\n");
2792 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2795 mips_do_registers_info (int regnum
, int fpregs
)
2797 if (regnum
!= -1) /* do one specified register */
2799 if (*(REGISTER_NAME (regnum
)) == '\0')
2800 error ("Not a valid register for the current processor type");
2802 mips_print_register (regnum
, 0);
2803 printf_filtered ("\n");
2806 /* do all (or most) registers */
2809 while (regnum
< NUM_REGS
)
2811 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2812 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2813 regnum
= do_fp_register_row (regnum
); /* FP regs */
2815 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2817 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2822 /* Return number of args passed to a frame. described by FIP.
2823 Can return -1, meaning no way to tell. */
2826 mips_frame_num_args (struct frame_info
*frame
)
2831 /* Is this a branch with a delay slot? */
2833 static int is_delayed (unsigned long);
2836 is_delayed (unsigned long insn
)
2839 for (i
= 0; i
< NUMOPCODES
; ++i
)
2840 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2841 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2843 return (i
< NUMOPCODES
2844 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2845 | INSN_COND_BRANCH_DELAY
2846 | INSN_COND_BRANCH_LIKELY
)));
2850 mips_step_skips_delay (CORE_ADDR pc
)
2852 char buf
[MIPS_INSTLEN
];
2854 /* There is no branch delay slot on MIPS16. */
2855 if (pc_is_mips16 (pc
))
2858 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2859 /* If error reading memory, guess that it is not a delayed branch. */
2861 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2865 /* Skip the PC past function prologue instructions (32-bit version).
2866 This is a helper function for mips_skip_prologue. */
2869 mips32_skip_prologue (CORE_ADDR pc
)
2873 int seen_sp_adjust
= 0;
2874 int load_immediate_bytes
= 0;
2876 /* Skip the typical prologue instructions. These are the stack adjustment
2877 instruction and the instructions that save registers on the stack
2878 or in the gcc frame. */
2879 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2881 unsigned long high_word
;
2883 inst
= mips_fetch_instruction (pc
);
2884 high_word
= (inst
>> 16) & 0xffff;
2886 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2887 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2889 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2890 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2892 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2893 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2894 && (inst
& 0x001F0000)) /* reg != $zero */
2897 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2899 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2901 continue; /* reg != $zero */
2903 /* move $s8,$sp. With different versions of gas this will be either
2904 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2905 Accept any one of these. */
2906 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2909 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2911 else if (high_word
== 0x3c1c) /* lui $gp,n */
2913 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2915 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2916 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2918 /* The following instructions load $at or $t0 with an immediate
2919 value in preparation for a stack adjustment via
2920 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2921 a local variable, so we accept them only before a stack adjustment
2922 instruction was seen. */
2923 else if (!seen_sp_adjust
)
2925 if (high_word
== 0x3c01 || /* lui $at,n */
2926 high_word
== 0x3c08) /* lui $t0,n */
2928 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2931 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2932 high_word
== 0x3508 || /* ori $t0,$t0,n */
2933 high_word
== 0x3401 || /* ori $at,$zero,n */
2934 high_word
== 0x3408) /* ori $t0,$zero,n */
2936 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2946 /* In a frameless function, we might have incorrectly
2947 skipped some load immediate instructions. Undo the skipping
2948 if the load immediate was not followed by a stack adjustment. */
2949 if (load_immediate_bytes
&& !seen_sp_adjust
)
2950 pc
-= load_immediate_bytes
;
2954 /* Skip the PC past function prologue instructions (16-bit version).
2955 This is a helper function for mips_skip_prologue. */
2958 mips16_skip_prologue (CORE_ADDR pc
)
2961 int extend_bytes
= 0;
2962 int prev_extend_bytes
;
2964 /* Table of instructions likely to be found in a function prologue. */
2967 unsigned short inst
;
2968 unsigned short mask
;
2975 , /* addiu $sp,offset */
2979 , /* daddiu $sp,offset */
2983 , /* sw reg,n($sp) */
2987 , /* sd reg,n($sp) */
2991 , /* sw $ra,n($sp) */
2995 , /* sd $ra,n($sp) */
3003 , /* sw $a0-$a3,n($s1) */
3007 , /* move reg,$a0-$a3 */
3011 , /* entry pseudo-op */
3015 , /* addiu $s1,$sp,n */
3018 } /* end of table marker */
3021 /* Skip the typical prologue instructions. These are the stack adjustment
3022 instruction and the instructions that save registers on the stack
3023 or in the gcc frame. */
3024 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3026 unsigned short inst
;
3029 inst
= mips_fetch_instruction (pc
);
3031 /* Normally we ignore an extend instruction. However, if it is
3032 not followed by a valid prologue instruction, we must adjust
3033 the pc back over the extend so that it won't be considered
3034 part of the prologue. */
3035 if ((inst
& 0xf800) == 0xf000) /* extend */
3037 extend_bytes
= MIPS16_INSTLEN
;
3040 prev_extend_bytes
= extend_bytes
;
3043 /* Check for other valid prologue instructions besides extend. */
3044 for (i
= 0; table
[i
].mask
!= 0; i
++)
3045 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3047 if (table
[i
].mask
!= 0) /* it was in table? */
3048 continue; /* ignore it */
3052 /* Return the current pc, adjusted backwards by 2 if
3053 the previous instruction was an extend. */
3054 return pc
- prev_extend_bytes
;
3060 /* To skip prologues, I use this predicate. Returns either PC itself
3061 if the code at PC does not look like a function prologue; otherwise
3062 returns an address that (if we're lucky) follows the prologue. If
3063 LENIENT, then we must skip everything which is involved in setting
3064 up the frame (it's OK to skip more, just so long as we don't skip
3065 anything which might clobber the registers which are being saved.
3066 We must skip more in the case where part of the prologue is in the
3067 delay slot of a non-prologue instruction). */
3070 mips_skip_prologue (CORE_ADDR pc
)
3072 /* See if we can determine the end of the prologue via the symbol table.
3073 If so, then return either PC, or the PC after the prologue, whichever
3076 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3078 if (post_prologue_pc
!= 0)
3079 return max (pc
, post_prologue_pc
);
3081 /* Can't determine prologue from the symbol table, need to examine
3084 if (pc_is_mips16 (pc
))
3085 return mips16_skip_prologue (pc
);
3087 return mips32_skip_prologue (pc
);
3090 /* Determine how a return value is stored within the MIPS register
3091 file, given the return type `valtype'. */
3093 struct return_value_word
3102 return_value_location (struct type
*valtype
,
3103 struct return_value_word
*hi
,
3104 struct return_value_word
*lo
)
3106 int len
= TYPE_LENGTH (valtype
);
3108 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3109 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3110 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3112 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3114 /* We need to break a 64bit float in two 32 bit halves and
3115 spread them across a floating-point register pair. */
3116 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3117 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3118 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3119 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3121 hi
->reg_offset
= lo
->reg_offset
;
3122 lo
->reg
= FP0_REGNUM
+ 0;
3123 hi
->reg
= FP0_REGNUM
+ 1;
3129 /* The floating point value fits in a single floating-point
3131 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3132 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3135 lo
->reg
= FP0_REGNUM
;
3146 /* Locate a result possibly spread across two registers. */
3148 lo
->reg
= regnum
+ 0;
3149 hi
->reg
= regnum
+ 1;
3150 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3151 && len
< MIPS_SAVED_REGSIZE
)
3153 /* "un-left-justify" the value in the low register */
3154 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3159 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3160 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3161 && len
< MIPS_SAVED_REGSIZE
* 2
3162 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3163 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3165 /* "un-left-justify" the value spread across two registers. */
3166 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3167 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3169 hi
->len
= len
- lo
->len
;
3173 /* Only perform a partial copy of the second register. */
3176 if (len
> MIPS_SAVED_REGSIZE
)
3178 lo
->len
= MIPS_SAVED_REGSIZE
;
3179 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3187 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3188 && REGISTER_RAW_SIZE (regnum
) == 8
3189 && MIPS_SAVED_REGSIZE
== 4)
3191 /* Account for the fact that only the least-signficant part
3192 of the register is being used */
3193 lo
->reg_offset
+= 4;
3194 hi
->reg_offset
+= 4;
3197 hi
->buf_offset
= lo
->len
;
3201 /* Given a return value in `regbuf' with a type `valtype', extract and
3202 copy its value into `valbuf'. */
3205 mips_extract_return_value (struct type
*valtype
,
3206 char regbuf
[REGISTER_BYTES
],
3209 struct return_value_word lo
;
3210 struct return_value_word hi
;
3211 return_value_location (valtype
, &lo
, &hi
);
3213 memcpy (valbuf
+ lo
.buf_offset
,
3214 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3218 memcpy (valbuf
+ hi
.buf_offset
,
3219 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3223 /* Given a return value in `valbuf' with a type `valtype', write it's
3224 value into the appropriate register. */
3227 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3229 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3230 struct return_value_word lo
;
3231 struct return_value_word hi
;
3232 return_value_location (valtype
, &lo
, &hi
);
3234 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3235 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3236 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3238 REGISTER_RAW_SIZE (lo
.reg
));
3242 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3243 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3244 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3246 REGISTER_RAW_SIZE (hi
.reg
));
3250 /* Exported procedure: Is PC in the signal trampoline code */
3253 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3255 if (sigtramp_address
== 0)
3257 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3260 /* Root of all "set mips "/"show mips " commands. This will eventually be
3261 used for all MIPS-specific commands. */
3264 show_mips_command (char *args
, int from_tty
)
3266 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3270 set_mips_command (char *args
, int from_tty
)
3272 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3273 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3276 /* Commands to show/set the MIPS FPU type. */
3279 show_mipsfpu_command (char *args
, int from_tty
)
3283 switch (MIPS_FPU_TYPE
)
3285 case MIPS_FPU_SINGLE
:
3286 fpu
= "single-precision";
3288 case MIPS_FPU_DOUBLE
:
3289 fpu
= "double-precision";
3292 fpu
= "absent (none)";
3295 if (mips_fpu_type_auto
)
3296 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3299 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3305 set_mipsfpu_command (char *args
, int from_tty
)
3307 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3308 show_mipsfpu_command (args
, from_tty
);
3312 set_mipsfpu_single_command (char *args
, int from_tty
)
3314 mips_fpu_type
= MIPS_FPU_SINGLE
;
3315 mips_fpu_type_auto
= 0;
3318 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3323 set_mipsfpu_double_command (char *args
, int from_tty
)
3325 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3326 mips_fpu_type_auto
= 0;
3329 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3334 set_mipsfpu_none_command (char *args
, int from_tty
)
3336 mips_fpu_type
= MIPS_FPU_NONE
;
3337 mips_fpu_type_auto
= 0;
3340 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3345 set_mipsfpu_auto_command (char *args
, int from_tty
)
3347 mips_fpu_type_auto
= 1;
3350 /* Command to set the processor type. */
3353 mips_set_processor_type_command (char *args
, int from_tty
)
3357 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3359 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3360 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3361 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3363 /* Restore the value. */
3364 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3369 if (!mips_set_processor_type (tmp_mips_processor_type
))
3371 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3372 /* Restore its value. */
3373 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3378 mips_show_processor_type_command (char *args
, int from_tty
)
3382 /* Modify the actual processor type. */
3385 mips_set_processor_type (char *str
)
3392 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3394 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3396 mips_processor_type
= str
;
3397 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3399 /* FIXME tweak fpu flag too */
3406 /* Attempt to identify the particular processor model by reading the
3410 mips_read_processor_type (void)
3414 prid
= read_register (PRID_REGNUM
);
3416 if ((prid
& ~0xf) == 0x700)
3417 return savestring ("r3041", strlen ("r3041"));
3422 /* Just like reinit_frame_cache, but with the right arguments to be
3423 callable as an sfunc. */
3426 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3427 struct cmd_list_element
*c
)
3429 reinit_frame_cache ();
3433 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3435 mips_extra_func_info_t proc_desc
;
3437 /* Search for the function containing this address. Set the low bit
3438 of the address when searching, in case we were given an even address
3439 that is the start of a 16-bit function. If we didn't do this,
3440 the search would fail because the symbol table says the function
3441 starts at an odd address, i.e. 1 byte past the given address. */
3442 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3443 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3445 /* Make an attempt to determine if this is a 16-bit function. If
3446 the procedure descriptor exists and the address therein is odd,
3447 it's definitely a 16-bit function. Otherwise, we have to just
3448 guess that if the address passed in is odd, it's 16-bits. */
3450 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3451 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3453 info
->mach
= pc_is_mips16 (memaddr
) ?
3454 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3456 /* Round down the instruction address to the appropriate boundary. */
3457 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3459 /* Call the appropriate disassembler based on the target endian-ness. */
3460 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3461 return print_insn_big_mips (memaddr
, info
);
3463 return print_insn_little_mips (memaddr
, info
);
3466 /* Old-style breakpoint macros.
3467 The IDT board uses an unusual breakpoint value, and sometimes gets
3468 confused when it sees the usual MIPS breakpoint instruction. */
3470 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3471 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3472 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3473 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3474 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3475 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3476 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3477 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3479 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3480 counter value to determine whether a 16- or 32-bit breakpoint should be
3481 used. It returns a pointer to a string of bytes that encode a breakpoint
3482 instruction, stores the length of the string to *lenptr, and adjusts pc
3483 (if necessary) to point to the actual memory location where the
3484 breakpoint should be inserted. */
3487 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3489 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3491 if (pc_is_mips16 (*pcptr
))
3493 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3494 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3495 *lenptr
= sizeof (mips16_big_breakpoint
);
3496 return mips16_big_breakpoint
;
3500 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3501 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3502 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3504 *lenptr
= sizeof (big_breakpoint
);
3506 if (strcmp (target_shortname
, "mips") == 0)
3507 return idt_big_breakpoint
;
3508 else if (strcmp (target_shortname
, "ddb") == 0
3509 || strcmp (target_shortname
, "pmon") == 0
3510 || strcmp (target_shortname
, "lsi") == 0)
3511 return pmon_big_breakpoint
;
3513 return big_breakpoint
;
3518 if (pc_is_mips16 (*pcptr
))
3520 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3521 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3522 *lenptr
= sizeof (mips16_little_breakpoint
);
3523 return mips16_little_breakpoint
;
3527 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3528 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3529 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3531 *lenptr
= sizeof (little_breakpoint
);
3533 if (strcmp (target_shortname
, "mips") == 0)
3534 return idt_little_breakpoint
;
3535 else if (strcmp (target_shortname
, "ddb") == 0
3536 || strcmp (target_shortname
, "pmon") == 0
3537 || strcmp (target_shortname
, "lsi") == 0)
3538 return pmon_little_breakpoint
;
3540 return little_breakpoint
;
3545 /* If PC is in a mips16 call or return stub, return the address of the target
3546 PC, which is either the callee or the caller. There are several
3547 cases which must be handled:
3549 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3550 target PC is in $31 ($ra).
3551 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3552 and the target PC is in $2.
3553 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3554 before the jal instruction, this is effectively a call stub
3555 and the the target PC is in $2. Otherwise this is effectively
3556 a return stub and the target PC is in $18.
3558 See the source code for the stubs in gcc/config/mips/mips16.S for
3561 This function implements the SKIP_TRAMPOLINE_CODE macro.
3565 mips_skip_stub (CORE_ADDR pc
)
3568 CORE_ADDR start_addr
;
3570 /* Find the starting address and name of the function containing the PC. */
3571 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3574 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3575 target PC is in $31 ($ra). */
3576 if (strcmp (name
, "__mips16_ret_sf") == 0
3577 || strcmp (name
, "__mips16_ret_df") == 0)
3578 return read_signed_register (RA_REGNUM
);
3580 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3582 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3583 and the target PC is in $2. */
3584 if (name
[19] >= '0' && name
[19] <= '9')
3585 return read_signed_register (2);
3587 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3588 before the jal instruction, this is effectively a call stub
3589 and the the target PC is in $2. Otherwise this is effectively
3590 a return stub and the target PC is in $18. */
3591 else if (name
[19] == 's' || name
[19] == 'd')
3593 if (pc
== start_addr
)
3595 /* Check if the target of the stub is a compiler-generated
3596 stub. Such a stub for a function bar might have a name
3597 like __fn_stub_bar, and might look like this:
3602 la $1,bar (becomes a lui/addiu pair)
3604 So scan down to the lui/addi and extract the target
3605 address from those two instructions. */
3607 CORE_ADDR target_pc
= read_signed_register (2);
3611 /* See if the name of the target function is __fn_stub_*. */
3612 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3614 if (strncmp (name
, "__fn_stub_", 10) != 0
3615 && strcmp (name
, "etext") != 0
3616 && strcmp (name
, "_etext") != 0)
3619 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3620 The limit on the search is arbitrarily set to 20
3621 instructions. FIXME. */
3622 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3624 inst
= mips_fetch_instruction (target_pc
);
3625 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3626 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3627 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3628 return pc
| (inst
& 0xffff); /* low word */
3631 /* Couldn't find the lui/addui pair, so return stub address. */
3635 /* This is the 'return' part of a call stub. The return
3636 address is in $r18. */
3637 return read_signed_register (18);
3640 return 0; /* not a stub */
3644 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3645 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3648 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3650 CORE_ADDR start_addr
;
3652 /* Find the starting address of the function containing the PC. If the
3653 caller didn't give us a name, look it up at the same time. */
3654 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3657 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3659 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3660 if (name
[19] >= '0' && name
[19] <= '9')
3662 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3663 before the jal instruction, this is effectively a call stub. */
3664 else if (name
[19] == 's' || name
[19] == 'd')
3665 return pc
== start_addr
;
3668 return 0; /* not a stub */
3672 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3673 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3676 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3678 CORE_ADDR start_addr
;
3680 /* Find the starting address of the function containing the PC. */
3681 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3684 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3685 if (strcmp (name
, "__mips16_ret_sf") == 0
3686 || strcmp (name
, "__mips16_ret_df") == 0)
3689 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3690 i.e. after the jal instruction, this is effectively a return stub. */
3691 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3692 && (name
[19] == 's' || name
[19] == 'd')
3693 && pc
!= start_addr
)
3696 return 0; /* not a stub */
3700 /* Return non-zero if the PC is in a library helper function that should
3701 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3704 mips_ignore_helper (CORE_ADDR pc
)
3708 /* Find the starting address and name of the function containing the PC. */
3709 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3712 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3713 that we want to ignore. */
3714 return (strcmp (name
, "__mips16_ret_sf") == 0
3715 || strcmp (name
, "__mips16_ret_df") == 0);
3719 /* Return a location where we can set a breakpoint that will be hit
3720 when an inferior function call returns. This is normally the
3721 program's entry point. Executables that don't have an entry
3722 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3723 whose address is the location where the breakpoint should be placed. */
3726 mips_call_dummy_address (void)
3728 struct minimal_symbol
*sym
;
3730 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3732 return SYMBOL_VALUE_ADDRESS (sym
);
3734 return entry_point_address ();
3738 /* If the current gcc for this target does not produce correct debugging
3739 information for float parameters, both prototyped and unprototyped, then
3740 define this macro. This forces gdb to always assume that floats are
3741 passed as doubles and then converted in the callee.
3743 For the mips chip, it appears that the debug info marks the parameters as
3744 floats regardless of whether the function is prototyped, but the actual
3745 values are passed as doubles for the non-prototyped case and floats for
3746 the prototyped case. Thus we choose to make the non-prototyped case work
3747 for C and break the prototyped case, since the non-prototyped case is
3748 probably much more common. (FIXME). */
3751 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3753 return current_language
->la_language
== language_c
;
3756 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3757 the register stored on the stack (32) is different to its real raw
3758 size (64). The below ensures that registers are fetched from the
3759 stack using their ABI size and then stored into the RAW_BUFFER
3760 using their raw size.
3762 The alternative to adding this function would be to add an ABI
3763 macro - REGISTER_STACK_SIZE(). */
3766 mips_get_saved_register (char *raw_buffer
,
3769 struct frame_info
*frame
,
3771 enum lval_type
*lval
)
3775 if (!target_has_registers
)
3776 error ("No registers.");
3778 /* Normal systems don't optimize out things with register numbers. */
3779 if (optimized
!= NULL
)
3781 addr
= find_saved_register (frame
, regnum
);
3785 *lval
= lval_memory
;
3786 if (regnum
== SP_REGNUM
)
3788 if (raw_buffer
!= NULL
)
3790 /* Put it back in target format. */
3791 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3798 if (raw_buffer
!= NULL
)
3802 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3804 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3806 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3807 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3813 *lval
= lval_register
;
3814 addr
= REGISTER_BYTE (regnum
);
3815 if (raw_buffer
!= NULL
)
3816 read_register_gen (regnum
, raw_buffer
);
3822 /* Immediately after a function call, return the saved pc.
3823 Can't always go through the frames for this because on some machines
3824 the new frame is not set up until the new function executes
3825 some instructions. */
3828 mips_saved_pc_after_call (struct frame_info
*frame
)
3830 return read_signed_register (RA_REGNUM
);
3834 /* Convert a dbx stab register number (from `r' declaration) to a gdb
3838 mips_stab_reg_to_regnum (int num
)
3843 return num
+ FP0_REGNUM
- 38;
3846 /* Convert a ecoff register number to a gdb REGNUM */
3849 mips_ecoff_reg_to_regnum (int num
)
3854 return num
+ FP0_REGNUM
- 32;
3857 static struct gdbarch
*
3858 mips_gdbarch_init (struct gdbarch_info info
,
3859 struct gdbarch_list
*arches
)
3861 static LONGEST mips_call_dummy_words
[] =
3863 struct gdbarch
*gdbarch
;
3864 struct gdbarch_tdep
*tdep
;
3866 enum mips_abi mips_abi
;
3868 /* Extract the elf_flags if available */
3869 if (info
.abfd
!= NULL
3870 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3871 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3875 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3876 switch ((elf_flags
& EF_MIPS_ABI
))
3878 case E_MIPS_ABI_O32
:
3879 mips_abi
= MIPS_ABI_O32
;
3881 case E_MIPS_ABI_O64
:
3882 mips_abi
= MIPS_ABI_O64
;
3884 case E_MIPS_ABI_EABI32
:
3885 mips_abi
= MIPS_ABI_EABI32
;
3887 case E_MIPS_ABI_EABI64
:
3888 mips_abi
= MIPS_ABI_EABI64
;
3891 if ((elf_flags
& EF_MIPS_ABI2
))
3892 mips_abi
= MIPS_ABI_N32
;
3894 mips_abi
= MIPS_ABI_UNKNOWN
;
3898 /* Try the architecture for any hint of the corect ABI */
3899 if (mips_abi
== MIPS_ABI_UNKNOWN
3900 && info
.bfd_arch_info
!= NULL
3901 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3903 switch (info
.bfd_arch_info
->mach
)
3905 case bfd_mach_mips3900
:
3906 mips_abi
= MIPS_ABI_EABI32
;
3908 case bfd_mach_mips4100
:
3909 case bfd_mach_mips5000
:
3910 mips_abi
= MIPS_ABI_EABI64
;
3914 #ifdef MIPS_DEFAULT_ABI
3915 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3916 mips_abi
= MIPS_DEFAULT_ABI
;
3921 fprintf_unfiltered (gdb_stdlog
,
3922 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3924 fprintf_unfiltered (gdb_stdlog
,
3925 "mips_gdbarch_init: mips_abi = %d\n",
3929 /* try to find a pre-existing architecture */
3930 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3932 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3934 /* MIPS needs to be pedantic about which ABI the object is
3936 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
3938 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
3940 return arches
->gdbarch
;
3943 /* Need a new architecture. Fill in a target specific vector. */
3944 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3945 gdbarch
= gdbarch_alloc (&info
, tdep
);
3946 tdep
->elf_flags
= elf_flags
;
3948 /* Initially set everything according to the ABI. */
3949 set_gdbarch_short_bit (gdbarch
, 16);
3950 set_gdbarch_int_bit (gdbarch
, 32);
3951 set_gdbarch_float_bit (gdbarch
, 32);
3952 set_gdbarch_double_bit (gdbarch
, 64);
3953 set_gdbarch_long_double_bit (gdbarch
, 64);
3954 tdep
->mips_abi
= mips_abi
;
3958 tdep
->mips_abi_string
= "o32";
3959 tdep
->mips_default_saved_regsize
= 4;
3960 tdep
->mips_default_stack_argsize
= 4;
3961 tdep
->mips_fp_register_double
= 0;
3962 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3963 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3964 tdep
->mips_regs_have_home_p
= 1;
3965 tdep
->gdb_target_is_mips64
= 0;
3966 tdep
->default_mask_address_p
= 0;
3967 set_gdbarch_long_bit (gdbarch
, 32);
3968 set_gdbarch_ptr_bit (gdbarch
, 32);
3969 set_gdbarch_long_long_bit (gdbarch
, 64);
3972 tdep
->mips_abi_string
= "o64";
3973 tdep
->mips_default_saved_regsize
= 8;
3974 tdep
->mips_default_stack_argsize
= 8;
3975 tdep
->mips_fp_register_double
= 1;
3976 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3977 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3978 tdep
->mips_regs_have_home_p
= 1;
3979 tdep
->gdb_target_is_mips64
= 1;
3980 tdep
->default_mask_address_p
= 0;
3981 set_gdbarch_long_bit (gdbarch
, 32);
3982 set_gdbarch_ptr_bit (gdbarch
, 32);
3983 set_gdbarch_long_long_bit (gdbarch
, 64);
3985 case MIPS_ABI_EABI32
:
3986 tdep
->mips_abi_string
= "eabi32";
3987 tdep
->mips_default_saved_regsize
= 4;
3988 tdep
->mips_default_stack_argsize
= 4;
3989 tdep
->mips_fp_register_double
= 0;
3990 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3991 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3992 tdep
->mips_regs_have_home_p
= 0;
3993 tdep
->gdb_target_is_mips64
= 0;
3994 tdep
->default_mask_address_p
= 0;
3995 set_gdbarch_long_bit (gdbarch
, 32);
3996 set_gdbarch_ptr_bit (gdbarch
, 32);
3997 set_gdbarch_long_long_bit (gdbarch
, 64);
3999 case MIPS_ABI_EABI64
:
4000 tdep
->mips_abi_string
= "eabi64";
4001 tdep
->mips_default_saved_regsize
= 8;
4002 tdep
->mips_default_stack_argsize
= 8;
4003 tdep
->mips_fp_register_double
= 1;
4004 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4005 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4006 tdep
->mips_regs_have_home_p
= 0;
4007 tdep
->gdb_target_is_mips64
= 1;
4008 tdep
->default_mask_address_p
= 0;
4009 set_gdbarch_long_bit (gdbarch
, 64);
4010 set_gdbarch_ptr_bit (gdbarch
, 64);
4011 set_gdbarch_long_long_bit (gdbarch
, 64);
4014 tdep
->mips_abi_string
= "n32";
4015 tdep
->mips_default_saved_regsize
= 4;
4016 tdep
->mips_default_stack_argsize
= 8;
4017 tdep
->mips_fp_register_double
= 1;
4018 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4019 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4020 tdep
->mips_regs_have_home_p
= 0;
4021 tdep
->gdb_target_is_mips64
= 0;
4022 tdep
->default_mask_address_p
= 0;
4023 set_gdbarch_long_bit (gdbarch
, 32);
4024 set_gdbarch_ptr_bit (gdbarch
, 32);
4025 set_gdbarch_long_long_bit (gdbarch
, 64);
4028 tdep
->mips_abi_string
= "default";
4029 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4030 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4031 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4032 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4033 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4034 tdep
->mips_regs_have_home_p
= 1;
4035 tdep
->gdb_target_is_mips64
= 0;
4036 tdep
->default_mask_address_p
= 0;
4037 set_gdbarch_long_bit (gdbarch
, 32);
4038 set_gdbarch_ptr_bit (gdbarch
, 32);
4039 set_gdbarch_long_long_bit (gdbarch
, 64);
4043 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4044 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4047 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4048 flag in object files because to do so would make it impossible to
4049 link with libraries compiled without "-gp32". This is
4050 unnecessarily restrictive.
4052 We could solve this problem by adding "-gp32" multilibs to gcc,
4053 but to set this flag before gcc is built with such multilibs will
4054 break too many systems.''
4056 But even more unhelpfully, the default linker output target for
4057 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4058 for 64-bit programs - you need to change the ABI to change this,
4059 and not all gcc targets support that currently. Therefore using
4060 this flag to detect 32-bit mode would do the wrong thing given
4061 the current gcc - it would make GDB treat these 64-bit programs
4062 as 32-bit programs by default. */
4064 /* enable/disable the MIPS FPU */
4065 if (!mips_fpu_type_auto
)
4066 tdep
->mips_fpu_type
= mips_fpu_type
;
4067 else if (info
.bfd_arch_info
!= NULL
4068 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4069 switch (info
.bfd_arch_info
->mach
)
4071 case bfd_mach_mips3900
:
4072 case bfd_mach_mips4100
:
4073 case bfd_mach_mips4111
:
4074 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4076 case bfd_mach_mips4650
:
4077 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4080 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4084 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4086 /* MIPS version of register names. NOTE: At present the MIPS
4087 register name management is part way between the old -
4088 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4089 Further work on it is required. */
4090 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4091 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4092 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4093 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4094 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4095 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4096 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4098 /* Map debug register numbers onto internal register numbers. */
4099 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4100 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4102 /* Initialize a frame */
4103 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4105 /* MIPS version of CALL_DUMMY */
4107 set_gdbarch_call_dummy_p (gdbarch
, 1);
4108 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4109 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4110 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4111 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4112 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4113 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4114 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4115 set_gdbarch_call_dummy_length (gdbarch
, 0);
4116 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4117 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4118 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4119 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4120 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4121 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4122 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4124 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4125 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4127 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4128 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4129 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4130 set_gdbarch_ieee_float (gdbarch
, 1);
4132 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4133 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4139 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4141 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4145 int ef_mips_32bitmode
;
4146 /* determine the ISA */
4147 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4164 /* determine the size of a pointer */
4165 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4166 fprintf_unfiltered (file
,
4167 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4169 fprintf_unfiltered (file
,
4170 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4172 fprintf_unfiltered (file
,
4173 "mips_dump_tdep: ef_mips_arch = %d\n",
4175 fprintf_unfiltered (file
,
4176 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4178 tdep
->mips_abi_string
);
4179 fprintf_unfiltered (file
,
4180 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4181 mips_mask_address_p (),
4182 tdep
->default_mask_address_p
);
4184 fprintf_unfiltered (file
,
4185 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4186 FP_REGISTER_DOUBLE
);
4187 fprintf_unfiltered (file
,
4188 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4189 MIPS_DEFAULT_FPU_TYPE
,
4190 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4191 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4192 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4194 fprintf_unfiltered (file
,
4195 "mips_dump_tdep: MIPS_EABI = %d\n",
4197 fprintf_unfiltered (file
,
4198 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4199 MIPS_LAST_FP_ARG_REGNUM
,
4200 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4201 fprintf_unfiltered (file
,
4202 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4204 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4205 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4206 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4208 fprintf_unfiltered (file
,
4209 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4210 MIPS_DEFAULT_SAVED_REGSIZE
);
4211 fprintf_unfiltered (file
,
4212 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4213 FP_REGISTER_DOUBLE
);
4214 fprintf_unfiltered (file
,
4215 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4216 MIPS_REGS_HAVE_HOME_P
);
4217 fprintf_unfiltered (file
,
4218 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4219 MIPS_DEFAULT_STACK_ARGSIZE
);
4220 fprintf_unfiltered (file
,
4221 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4222 MIPS_STACK_ARGSIZE
);
4223 fprintf_unfiltered (file
,
4224 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4226 fprintf_unfiltered (file
,
4227 "mips_dump_tdep: A0_REGNUM = %d\n",
4229 fprintf_unfiltered (file
,
4230 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4231 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4232 fprintf_unfiltered (file
,
4233 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4234 XSTRING (ATTACH_DETACH
));
4235 fprintf_unfiltered (file
,
4236 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4238 fprintf_unfiltered (file
,
4239 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4240 fprintf_unfiltered (file
,
4241 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4243 fprintf_unfiltered (file
,
4244 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4246 fprintf_unfiltered (file
,
4247 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4249 fprintf_unfiltered (file
,
4250 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4251 XSTRING (DO_REGISTERS_INFO
));
4252 fprintf_unfiltered (file
,
4253 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4254 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4255 fprintf_unfiltered (file
,
4256 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4257 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4258 fprintf_unfiltered (file
,
4259 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4260 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4261 fprintf_unfiltered (file
,
4262 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4264 fprintf_unfiltered (file
,
4265 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4267 fprintf_unfiltered (file
,
4268 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4269 FIRST_EMBED_REGNUM
);
4270 fprintf_unfiltered (file
,
4271 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4273 fprintf_unfiltered (file
,
4274 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4275 GDB_TARGET_IS_MIPS64
);
4276 fprintf_unfiltered (file
,
4277 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4278 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4279 fprintf_unfiltered (file
,
4280 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4281 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4282 fprintf_unfiltered (file
,
4283 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4285 fprintf_unfiltered (file
,
4286 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4287 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4288 fprintf_unfiltered (file
,
4289 "mips_dump_tdep: HI_REGNUM = %d\n",
4291 fprintf_unfiltered (file
,
4292 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4293 fprintf_unfiltered (file
,
4294 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4295 fprintf_unfiltered (file
,
4296 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4297 XSTRING (IGNORE_HELPER_CALL (PC
)));
4298 fprintf_unfiltered (file
,
4299 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4300 XSTRING (INIT_FRAME_PC (FROMLEAF
, PREV
)));
4301 fprintf_unfiltered (file
,
4302 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4303 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF
, PREV
)));
4304 fprintf_unfiltered (file
,
4305 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4306 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4307 fprintf_unfiltered (file
,
4308 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4309 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4310 fprintf_unfiltered (file
,
4311 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4312 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4313 fprintf_unfiltered (file
,
4314 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4315 fprintf_unfiltered (file
,
4316 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4318 fprintf_unfiltered (file
,
4319 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4320 fprintf_unfiltered (file
,
4321 "mips_dump_tdep: LO_REGNUM = %d\n",
4323 #ifdef MACHINE_CPROC_FP_OFFSET
4324 fprintf_unfiltered (file
,
4325 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4326 MACHINE_CPROC_FP_OFFSET
);
4328 #ifdef MACHINE_CPROC_PC_OFFSET
4329 fprintf_unfiltered (file
,
4330 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4331 MACHINE_CPROC_PC_OFFSET
);
4333 #ifdef MACHINE_CPROC_SP_OFFSET
4334 fprintf_unfiltered (file
,
4335 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4336 MACHINE_CPROC_SP_OFFSET
);
4338 fprintf_unfiltered (file
,
4339 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4340 fprintf_unfiltered (file
,
4341 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4342 fprintf_unfiltered (file
,
4343 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4345 fprintf_unfiltered (file
,
4346 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4347 fprintf_unfiltered (file
,
4348 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4349 fprintf_unfiltered (file
,
4350 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4351 fprintf_unfiltered (file
,
4352 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4354 fprintf_unfiltered (file
,
4355 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4356 MIPS_LAST_ARG_REGNUM
,
4357 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4358 fprintf_unfiltered (file
,
4359 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4361 fprintf_unfiltered (file
,
4362 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4363 fprintf_unfiltered (file
,
4364 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4365 MIPS_SAVED_REGSIZE
);
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4368 fprintf_unfiltered (file
,
4369 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4370 XSTRING (MSYMBOL_SIZE (MSYM
)));
4371 fprintf_unfiltered (file
,
4372 "mips_dump_tdep: OP_LDFPR = used?\n");
4373 fprintf_unfiltered (file
,
4374 "mips_dump_tdep: OP_LDGPR = used?\n");
4375 fprintf_unfiltered (file
,
4376 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4377 fprintf_unfiltered (file
,
4378 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4379 fprintf_unfiltered (file
,
4380 "mips_dump_tdep: PRID_REGNUM = %d\n",
4382 fprintf_unfiltered (file
,
4383 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4384 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4385 fprintf_unfiltered (file
,
4386 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4387 fprintf_unfiltered (file
,
4388 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4389 fprintf_unfiltered (file
,
4390 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4391 fprintf_unfiltered (file
,
4392 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4393 fprintf_unfiltered (file
,
4394 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4395 fprintf_unfiltered (file
,
4396 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4397 fprintf_unfiltered (file
,
4398 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4399 fprintf_unfiltered (file
,
4400 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4401 fprintf_unfiltered (file
,
4402 "mips_dump_tdep: PROC_PC_REG = function?\n");
4403 fprintf_unfiltered (file
,
4404 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4405 fprintf_unfiltered (file
,
4406 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4407 fprintf_unfiltered (file
,
4408 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4409 fprintf_unfiltered (file
,
4410 "mips_dump_tdep: PS_REGNUM = %d\n",
4412 fprintf_unfiltered (file
,
4413 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4415 fprintf_unfiltered (file
,
4416 "mips_dump_tdep: RA_REGNUM = %d\n",
4418 fprintf_unfiltered (file
,
4419 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4420 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4421 fprintf_unfiltered (file
,
4422 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4423 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4424 fprintf_unfiltered (file
,
4425 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4426 fprintf_unfiltered (file
,
4427 "mips_dump_tdep: ROUND_DOWN = function?\n");
4428 fprintf_unfiltered (file
,
4429 "mips_dump_tdep: ROUND_UP = function?\n");
4431 fprintf_unfiltered (file
,
4432 "mips_dump_tdep: SAVED_BYTES = %d\n",
4436 fprintf_unfiltered (file
,
4437 "mips_dump_tdep: SAVED_FP = %d\n",
4441 fprintf_unfiltered (file
,
4442 "mips_dump_tdep: SAVED_PC = %d\n",
4445 fprintf_unfiltered (file
,
4446 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4447 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4448 fprintf_unfiltered (file
,
4449 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4450 fprintf_unfiltered (file
,
4451 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4453 fprintf_unfiltered (file
,
4454 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4455 SIGFRAME_FPREGSAVE_OFF
);
4456 fprintf_unfiltered (file
,
4457 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4459 fprintf_unfiltered (file
,
4460 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4461 SIGFRAME_REGSAVE_OFF
);
4462 fprintf_unfiltered (file
,
4463 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4465 fprintf_unfiltered (file
,
4466 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4467 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4468 fprintf_unfiltered (file
,
4469 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4470 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4473 SOFTWARE_SINGLE_STEP_P
);
4474 fprintf_unfiltered (file
,
4475 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4476 SOFTWARE_SINGLE_STEP_P
);
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4479 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4480 #ifdef STACK_END_ADDR
4481 fprintf_unfiltered (file
,
4482 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4485 fprintf_unfiltered (file
,
4486 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4487 XSTRING (STEP_SKIPS_DELAY (PC
)));
4488 fprintf_unfiltered (file
,
4489 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4490 STEP_SKIPS_DELAY_P
);
4491 fprintf_unfiltered (file
,
4492 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4493 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4494 fprintf_unfiltered (file
,
4495 "mips_dump_tdep: T9_REGNUM = %d\n",
4497 fprintf_unfiltered (file
,
4498 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4499 fprintf_unfiltered (file
,
4500 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4501 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4502 fprintf_unfiltered (file
,
4503 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4504 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4505 fprintf_unfiltered (file
,
4506 "mips_dump_tdep: TARGET_MIPS = used?\n");
4507 fprintf_unfiltered (file
,
4508 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4509 XSTRING (TM_PRINT_INSN_MACH
));
4511 fprintf_unfiltered (file
,
4512 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4513 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4516 fprintf_unfiltered (file
,
4517 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4520 #ifdef TRACE_FLAVOR_SIZE
4521 fprintf_unfiltered (file
,
4522 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4526 fprintf_unfiltered (file
,
4527 "mips_dump_tdep: TRACE_SET # %s\n",
4528 XSTRING (TRACE_SET (X
,STATE
)));
4530 fprintf_unfiltered (file
,
4531 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4532 #ifdef UNUSED_REGNUM
4533 fprintf_unfiltered (file
,
4534 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4537 fprintf_unfiltered (file
,
4538 "mips_dump_tdep: V0_REGNUM = %d\n",
4540 fprintf_unfiltered (file
,
4541 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4542 (long) VM_MIN_ADDRESS
);
4544 fprintf_unfiltered (file
,
4545 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4548 fprintf_unfiltered (file
,
4549 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4551 fprintf_unfiltered (file
,
4552 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4557 _initialize_mips_tdep (void)
4559 static struct cmd_list_element
*mipsfpulist
= NULL
;
4560 struct cmd_list_element
*c
;
4562 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4563 if (!tm_print_insn
) /* Someone may have already set it */
4564 tm_print_insn
= gdb_print_insn_mips
;
4566 /* Add root prefix command for all "set mips"/"show mips" commands */
4567 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4568 "Various MIPS specific commands.",
4569 &setmipscmdlist
, "set mips ", 0, &setlist
);
4571 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4572 "Various MIPS specific commands.",
4573 &showmipscmdlist
, "show mips ", 0, &showlist
);
4575 /* Allow the user to override the saved register size. */
4576 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4579 &mips_saved_regsize_string
, "\
4580 Set size of general purpose registers saved on the stack.\n\
4581 This option can be set to one of:\n\
4582 32 - Force GDB to treat saved GP registers as 32-bit\n\
4583 64 - Force GDB to treat saved GP registers as 64-bit\n\
4584 auto - Allow GDB to use the target's default setting or autodetect the\n\
4585 saved GP register size from information contained in the executable.\n\
4590 /* Allow the user to override the argument stack size. */
4591 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4594 &mips_stack_argsize_string
, "\
4595 Set the amount of stack space reserved for each argument.\n\
4596 This option can be set to one of:\n\
4597 32 - Force GDB to allocate 32-bit chunks per argument\n\
4598 64 - Force GDB to allocate 64-bit chunks per argument\n\
4599 auto - Allow GDB to determine the correct setting from the current\n\
4600 target and executable (default)",
4604 /* Let the user turn off floating point and set the fence post for
4605 heuristic_proc_start. */
4607 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4608 "Set use of MIPS floating-point coprocessor.",
4609 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4610 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4611 "Select single-precision MIPS floating-point coprocessor.",
4613 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4614 "Select double-precision MIPS floating-point coprocessor.",
4616 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4617 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4618 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4619 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4620 "Select no MIPS floating-point coprocessor.",
4622 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4623 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4624 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4625 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4626 "Select MIPS floating-point coprocessor automatically.",
4628 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4629 "Show current use of MIPS floating-point coprocessor target.",
4633 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4634 (char *) &tmp_mips_processor_type
,
4635 "Set the type of MIPS processor in use.\n\
4636 Set this to be able to access processor-type-specific registers.\n\
4639 c
->function
.cfunc
= mips_set_processor_type_command
;
4640 c
= add_show_from_set (c
, &showlist
);
4641 c
->function
.cfunc
= mips_show_processor_type_command
;
4643 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4644 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4647 /* We really would like to have both "0" and "unlimited" work, but
4648 command.c doesn't deal with that. So make it a var_zinteger
4649 because the user can always use "999999" or some such for unlimited. */
4650 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4651 (char *) &heuristic_fence_post
,
4653 Set the distance searched for the start of a function.\n\
4654 If you are debugging a stripped executable, GDB needs to search through the\n\
4655 program for the start of a function. This command sets the distance of the\n\
4656 search. The only need to set it is when debugging a stripped executable.",
4658 /* We need to throw away the frame cache when we set this, since it
4659 might change our ability to get backtraces. */
4660 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4661 add_show_from_set (c
, &showlist
);
4663 /* Allow the user to control whether the upper bits of 64-bit
4664 addresses should be zeroed. */
4665 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4666 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4667 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4668 the correct value.\n",
4670 add_cmd ("mask-address", no_class
, show_mask_address
,
4671 "Show current mask-address value", &showmipscmdlist
);
4673 /* Allow the user to control the size of 32 bit registers within the
4674 raw remote packet. */
4675 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4678 (char *)&mips64_transfers_32bit_regs_p
, "\
4679 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4680 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4681 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4682 64 bits for others. Use \"off\" to disable compatibility mode",
4686 /* Debug this files internals. */
4687 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4688 &mips_debug
, "Set mips debugging.\n\
4689 When non-zero, mips specific debugging is enabled.", &setdebuglist
),