1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
);
66 static int micromips_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
68 static int mips16_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE
= 4,
80 MIPS_FPU_DOUBLE_REGSIZE
= 8
89 static const char *mips_abi_string
;
91 static const char *const mips_abi_strings
[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16
[] = "mips16";
106 static const char mips_compression_micromips
[] = "micromips";
107 static const char *const mips_compression_strings
[] =
109 mips_compression_mips16
,
110 mips_compression_micromips
,
114 static const char *mips_compression_string
= mips_compression_mips16
;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases
[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases
[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases
[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM
},
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
165 const struct register_alias mips_numeric_register_aliases
[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto
= 1;
178 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
180 static unsigned int mips_debug
= 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc
*mips_tdesc_gp32
;
188 struct target_desc
*mips_tdesc_gp64
;
190 const struct mips_regnum
*
191 mips_regnum (struct gdbarch
*gdbarch
)
193 return gdbarch_tdep (gdbarch
)->regnum
;
197 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
199 return mips_regnum (gdbarch
)->fp0
+ 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
208 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
210 return (rawnum
>= mips_regnum (gdbarch
)->fp0
211 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_isa_regsize (struct gdbarch
*gdbarch
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* If we know how big the registers are, use that size. */
239 if (tdep
->register_size_valid_p
)
240 return tdep
->register_size
;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch
*gdbarch
)
252 switch (mips_abi (gdbarch
))
254 case MIPS_ABI_EABI32
:
260 case MIPS_ABI_EABI64
:
262 case MIPS_ABI_UNKNOWN
:
265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch
*gdbarch
)
279 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch
*gdbarch
)
287 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr
)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr
)
303 return !is_compact_addr (addr
);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
311 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
319 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr
)
327 return ((addr
) & ~(CORE_ADDR
) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr
)
335 return ((addr
) | (CORE_ADDR
) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
353 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
355 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
357 if ((sym
->flags
& BSF_SYNTHETIC
) != 0)
360 if (ELF_ST_IS_MICROMIPS (elfsym
->internal_elf_sym
.st_other
))
361 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
362 else if (ELF_ST_IS_MIPS16 (elfsym
->internal_elf_sym
.st_other
))
363 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
366 /* Return one iff MSYM refers to standard ISA code. */
369 msymbol_is_mips (struct minimal_symbol
*msym
)
371 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
374 /* Return one iff MSYM refers to MIPS16 code. */
377 msymbol_is_mips16 (struct minimal_symbol
*msym
)
379 return MSYMBOL_TARGET_FLAG_1 (msym
);
382 /* Return one iff MSYM refers to microMIPS code. */
385 msymbol_is_micromips (struct minimal_symbol
*msym
)
387 return MSYMBOL_TARGET_FLAG_2 (msym
);
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
396 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
397 int reg_num
, int length
,
398 enum bfd_endian endian
, gdb_byte
*in
,
399 const gdb_byte
*out
, int buf_offset
)
403 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
409 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
411 case BFD_ENDIAN_LITTLE
:
414 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
418 internal_error (__FILE__
, __LINE__
, _("bad switch"));
421 fprintf_unfiltered (gdb_stderr
,
422 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
423 reg_num
, reg_offset
, buf_offset
, length
);
424 if (mips_debug
&& out
!= NULL
)
427 fprintf_unfiltered (gdb_stdlog
, "out ");
428 for (i
= 0; i
< length
; i
++)
429 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
432 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
435 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
437 if (mips_debug
&& in
!= NULL
)
440 fprintf_unfiltered (gdb_stdlog
, "in ");
441 for (i
= 0; i
< length
; i
++)
442 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
445 fprintf_unfiltered (gdb_stdlog
, "\n");
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
453 mips2_fp_compat (struct frame_info
*frame
)
455 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
458 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
467 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
476 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
478 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
480 /* The list of available "set mips " and "show mips " commands. */
482 static struct cmd_list_element
*setmipscmdlist
= NULL
;
483 static struct cmd_list_element
*showmipscmdlist
= NULL
;
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
490 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
494 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
495 "sr", "lo", "hi", "bad", "cause", "pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
503 /* Names of IDT R3041 registers. */
505 static const char *mips_r3041_reg_names
[] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
511 "fsr", "fir", "", /*"fp" */ "",
512 "", "", "bus", "ccfg", "", "", "", "",
513 "", "", "port", "cmp", "", "", "epc", "prid",
516 /* Names of tx39 registers. */
518 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
519 "sr", "lo", "hi", "bad", "cause", "pc",
520 "", "", "", "", "", "", "", "",
521 "", "", "", "", "", "", "", "",
522 "", "", "", "", "", "", "", "",
523 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "config", "cache", "debug", "depc", "epc",
529 /* Names of IRIX registers. */
530 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
538 /* Names of registers with Linux kernels. */
539 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
540 "sr", "lo", "hi", "bad", "cause", "pc",
541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
549 /* Return the name of the register corresponding to REGNO. */
551 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
554 /* GPR names for all ABIs other than n32/n64. */
555 static char *mips_gpr_names
[] = {
556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
562 /* GPR names for n32 and n64 ABIs. */
563 static char *mips_n32_n64_gpr_names
[] = {
564 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
565 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
567 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
570 enum mips_abi abi
= mips_abi (gdbarch
);
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
583 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
584 if (regno
< gdbarch_num_regs (gdbarch
))
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
590 if (0 <= rawnum
&& rawnum
< 32)
592 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
593 return mips_n32_n64_gpr_names
[rawnum
];
595 return mips_gpr_names
[rawnum
];
597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
598 return tdesc_register_name (gdbarch
, rawnum
);
599 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
601 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
602 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
603 return tdep
->mips_processor_reg_names
[rawnum
- 32];
607 internal_error (__FILE__
, __LINE__
,
608 _("mips_register_name: bad register number %d"), rawnum
);
611 /* Return the groups that a MIPS register can be categorised into. */
614 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
615 struct reggroup
*reggroup
)
620 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
621 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
622 if (reggroup
== all_reggroup
)
624 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
625 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
628 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
629 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
630 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
632 if (reggroup
== float_reggroup
)
633 return float_p
&& pseudo
;
634 if (reggroup
== vector_reggroup
)
635 return vector_p
&& pseudo
;
636 if (reggroup
== general_reggroup
)
637 return (!vector_p
&& !float_p
) && pseudo
;
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
641 if (reggroup
== save_reggroup
)
642 return raw_p
&& pseudo
;
643 /* Restore the same pseudo register. */
644 if (reggroup
== restore_reggroup
)
645 return raw_p
&& pseudo
;
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
654 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
655 struct reggroup
*reggroup
)
657 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
658 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
671 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
675 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
683 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
684 int cookednum
, gdb_byte
*buf
)
686 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
687 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
688 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
689 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
690 return regcache_raw_read (regcache
, rawnum
, buf
);
691 else if (register_size (gdbarch
, rawnum
) >
692 register_size (gdbarch
, cookednum
))
694 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
695 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
700 enum register_status status
;
702 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
703 if (status
== REG_VALID
)
704 store_signed_integer (buf
, 4, byte_order
, regval
);
709 internal_error (__FILE__
, __LINE__
, _("bad register size"));
713 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
714 struct regcache
*regcache
, int cookednum
,
717 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
718 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
719 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
720 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
721 regcache_raw_write (regcache
, rawnum
, buf
);
722 else if (register_size (gdbarch
, rawnum
) >
723 register_size (gdbarch
, cookednum
))
725 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
726 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
732 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
733 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
734 regcache_raw_write_signed (regcache
, rawnum
, regval
);
738 internal_error (__FILE__
, __LINE__
, _("bad register size"));
742 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
743 struct agent_expr
*ax
, int reg
)
745 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
747 && reg
< 2 * gdbarch_num_regs (gdbarch
));
749 ax_reg_mask (ax
, rawnum
);
755 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
756 struct agent_expr
*ax
, int reg
)
758 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
759 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
760 && reg
< 2 * gdbarch_num_regs (gdbarch
));
761 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
765 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
767 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
768 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
771 ax_simple (ax
, aop_lsh
);
774 ax_simple (ax
, aop_rsh_signed
);
778 internal_error (__FILE__
, __LINE__
, _("bad register size"));
783 /* Table to translate 3-bit register field to actual register number. */
784 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
790 static int heuristic_fence_post
= 0;
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
796 static int mips64_transfers_32bit_regs_p
= 0;
799 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
800 struct cmd_list_element
*c
)
802 struct gdbarch_info info
;
803 gdbarch_info_init (&info
);
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
807 if (!gdbarch_update_p (info
))
809 mips64_transfers_32bit_regs_p
= 0;
810 error (_("32-bit compatibility mode not supported"));
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
821 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
824 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
825 && register_size (gdbarch
, regnum
) == 4
826 && mips_float_register_p (gdbarch
, regnum
)
827 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
834 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
837 int num_regs
= gdbarch_num_regs (gdbarch
);
839 return (register_size (gdbarch
, regnum
) == 8
840 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
841 && TYPE_LENGTH (type
) < 8);
845 mips_convert_register_p (struct gdbarch
*gdbarch
,
846 int regnum
, struct type
*type
)
848 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
849 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
853 mips_register_to_value (struct frame_info
*frame
, int regnum
,
854 struct type
*type
, gdb_byte
*to
,
855 int *optimizedp
, int *unavailablep
)
857 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
859 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
861 get_frame_register (frame
, regnum
+ 0, to
+ 4);
862 get_frame_register (frame
, regnum
+ 1, to
+ 0);
864 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
865 optimizedp
, unavailablep
))
868 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
869 optimizedp
, unavailablep
))
871 *optimizedp
= *unavailablep
= 0;
874 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
876 int len
= TYPE_LENGTH (type
);
879 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
880 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
881 optimizedp
, unavailablep
))
884 *optimizedp
= *unavailablep
= 0;
889 internal_error (__FILE__
, __LINE__
,
890 _("mips_register_to_value: unrecognized case"));
895 mips_value_to_register (struct frame_info
*frame
, int regnum
,
896 struct type
*type
, const gdb_byte
*from
)
898 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
900 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
902 put_frame_register (frame
, regnum
+ 0, from
+ 4);
903 put_frame_register (frame
, regnum
+ 1, from
+ 0);
905 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
908 int len
= TYPE_LENGTH (type
);
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
916 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
919 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
921 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
922 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
923 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
927 if (from
[len
-1] & 0x80)
928 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
930 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
931 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
932 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
937 internal_error (__FILE__
, __LINE__
,
938 _("mips_value_to_register: unrecognized case"));
942 /* Return the GDB type object for the "standard" data type of data in
946 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
948 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
949 if (mips_float_register_p (gdbarch
, regnum
))
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
953 if (mips_isa_regsize (gdbarch
) == 4)
954 return builtin_type (gdbarch
)->builtin_float
;
956 return builtin_type (gdbarch
)->builtin_double
;
958 else if (regnum
< gdbarch_num_regs (gdbarch
))
960 /* The raw or ISA registers. These are all sized according to
962 if (mips_isa_regsize (gdbarch
) == 4)
963 return builtin_type (gdbarch
)->builtin_int32
;
965 return builtin_type (gdbarch
)->builtin_int64
;
969 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
973 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
974 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
975 return builtin_type (gdbarch
)->builtin_int32
;
976 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
977 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
978 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
979 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
982 return builtin_type (gdbarch
)->builtin_int32
;
983 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
987 return builtin_type (gdbarch
)->builtin_int32
;
988 else if (mips_abi_regsize (gdbarch
) == 4)
989 /* The ABI is restricted to 32-bit registers (the ISA could be
991 return builtin_type (gdbarch
)->builtin_int32
;
994 return builtin_type (gdbarch
)->builtin_int64
;
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1003 static struct type
*
1004 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1006 const int num_regs
= gdbarch_num_regs (gdbarch
);
1007 int rawnum
= regnum
% num_regs
;
1008 struct type
*rawtype
;
1010 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1012 /* Absent registers are still absent. */
1013 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1014 if (TYPE_LENGTH (rawtype
) == 0)
1017 if (mips_float_register_p (gdbarch
, rawnum
))
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1024 if (mips_abi_regsize (gdbarch
)
1025 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1027 if (rawnum
== MIPS_SP_REGNUM
1028 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1029 return builtin_type (gdbarch
)->builtin_data_ptr
;
1030 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1031 return builtin_type (gdbarch
)->builtin_func_ptr
;
1034 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1035 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1036 || rawnum
== mips_regnum (gdbarch
)->lo
1037 || rawnum
== mips_regnum (gdbarch
)->hi
1038 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1039 || rawnum
== mips_regnum (gdbarch
)->cause
1040 || rawnum
== mips_regnum (gdbarch
)->pc
1041 || (mips_regnum (gdbarch
)->dspacc
!= -1
1042 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1043 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1044 return builtin_type (gdbarch
)->builtin_int32
;
1046 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1047 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1048 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1049 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1057 return builtin_type (gdbarch
)->builtin_int32
;
1060 /* For all other registers, pass through the hardware type. */
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1065 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1068 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1070 switch (mask_address_var
)
1072 case AUTO_BOOLEAN_TRUE
:
1074 case AUTO_BOOLEAN_FALSE
:
1077 case AUTO_BOOLEAN_AUTO
:
1078 return tdep
->default_mask_address_p
;
1080 internal_error (__FILE__
, __LINE__
,
1081 _("mips_mask_address_p: bad switch"));
1087 show_mask_address (struct ui_file
*file
, int from_tty
,
1088 struct cmd_list_element
*c
, const char *value
)
1090 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1092 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1093 switch (mask_address_var
)
1095 case AUTO_BOOLEAN_TRUE
:
1096 printf_filtered ("The 32 bit mips address mask is enabled\n");
1098 case AUTO_BOOLEAN_FALSE
:
1099 printf_filtered ("The 32 bit mips address mask is disabled\n");
1101 case AUTO_BOOLEAN_AUTO
:
1103 ("The 32 bit address mask is set automatically. Currently %s\n",
1104 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1107 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1116 mips_pc_is_mips (CORE_ADDR memaddr
)
1118 struct bound_minimal_symbol sym
;
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1124 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1126 return msymbol_is_mips (sym
.minsym
);
1128 return is_mips_addr (memaddr
);
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1134 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1136 struct bound_minimal_symbol sym
;
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1142 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1144 return msymbol_is_mips16 (sym
.minsym
);
1146 return is_mips16_addr (gdbarch
, memaddr
);
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1152 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1154 struct bound_minimal_symbol sym
;
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1161 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1163 return msymbol_is_micromips (sym
.minsym
);
1165 return is_micromips_addr (gdbarch
, memaddr
);
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1171 static enum mips_isa
1172 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1174 struct bound_minimal_symbol sym
;
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1181 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1184 if (msymbol_is_micromips (sym
.minsym
))
1185 return ISA_MICROMIPS
;
1186 else if (msymbol_is_mips16 (sym
.minsym
))
1193 if (is_mips_addr (memaddr
))
1195 else if (is_micromips_addr (gdbarch
, memaddr
))
1196 return ISA_MICROMIPS
;
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1204 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1205 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1206 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1207 static const char mips_str_call_stub
[] = "__call_stub_";
1208 static const char mips_str_fn_stub
[] = "__fn_stub_";
1210 /* This is used as a PIC thunk prefix. */
1212 static const char mips_str_pic
[] = ".pic.";
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1218 mips_in_frame_stub (CORE_ADDR pc
)
1220 CORE_ADDR start_addr
;
1223 /* Find the starting address of the function containing the PC. */
1224 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1228 if (strncmp (name
, mips_str_mips16_call_stub
,
1229 strlen (mips_str_mips16_call_stub
)) == 0)
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1232 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1235 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1238 return 0; /* Not a stub. */
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1245 mips_read_pc (struct regcache
*regcache
)
1247 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1250 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1251 if (is_compact_addr (pc
))
1252 pc
= unmake_compact_addr (pc
);
1257 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1261 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1262 if (is_compact_addr (pc
))
1263 pc
= unmake_compact_addr (pc
);
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1269 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1271 pc
= frame_unwind_register_signed
1272 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1273 if (is_compact_addr (pc
))
1274 pc
= unmake_compact_addr (pc
);
1275 if (mips_in_frame_stub (pc
))
1277 pc
= frame_unwind_register_signed
1278 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1279 if (is_compact_addr (pc
))
1280 pc
= unmake_compact_addr (pc
);
1287 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1289 return frame_unwind_register_signed
1290 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1298 static struct frame_id
1299 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1301 return frame_id_build
1302 (get_frame_register_signed (this_frame
,
1303 gdbarch_num_regs (gdbarch
)
1305 get_frame_pc (this_frame
));
1308 /* Implement the "write_pc" gdbarch method. */
1311 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1313 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1315 if (mips_pc_is_mips (pc
))
1316 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1318 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1325 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1326 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1329 gdb_byte buf
[MIPS_INSN32_SIZE
];
1337 instlen
= MIPS_INSN16_SIZE
;
1338 addr
= unmake_compact_addr (addr
);
1341 instlen
= MIPS_INSN32_SIZE
;
1344 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1347 status
= target_read_memory (addr
, buf
, instlen
);
1348 if (statusp
!= NULL
)
1352 if (statusp
== NULL
)
1353 memory_error (status
, addr
);
1356 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1410 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1415 if (micromips_op (insn
) == 0x1f)
1416 return 3 * MIPS_INSN16_SIZE
;
1417 else if (((micromips_op (insn
) & 0x4) == 0x4)
1418 || ((micromips_op (insn
) & 0x7) == 0x0))
1419 return 2 * MIPS_INSN16_SIZE
;
1421 return MIPS_INSN16_SIZE
;
1423 if ((insn
& 0xf800) == 0xf000)
1424 return 2 * MIPS_INSN16_SIZE
;
1426 return MIPS_INSN16_SIZE
;
1428 return MIPS_INSN32_SIZE
;
1430 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1434 mips32_relative_offset (ULONGEST inst
)
1436 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1444 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1445 ULONGEST inst
, CORE_ADDR pc
, int count
)
1447 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1448 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1449 int tf
= itype_rt (inst
) & 1;
1450 int mask
= (1 << count
) - 1;
1455 /* No way to handle; it'll most likely trap anyway. */
1458 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1459 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1461 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1462 pc
+= mips32_relative_offset (inst
);
1469 /* Return nonzero if the gdbarch is an Octeon series. */
1472 is_octeon (struct gdbarch
*gdbarch
)
1474 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1476 return (info
->mach
== bfd_mach_mips_octeon
1477 || info
->mach
== bfd_mach_mips_octeonp
1478 || info
->mach
== bfd_mach_mips_octeon2
);
1481 /* Return true if the OP represents the Octeon's BBIT instruction. */
1484 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1486 if (!is_octeon (gdbarch
))
1488 /* BBIT0 is encoded as LWC2: 110 010. */
1489 /* BBIT032 is encoded as LDC2: 110 110. */
1490 /* BBIT1 is encoded as SWC2: 111 010. */
1491 /* BBIT132 is encoded as SDC2: 111 110. */
1492 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1498 /* Determine where to set a single step breakpoint while considering
1499 branch prediction. */
1502 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1504 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1507 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1508 op
= itype_op (inst
);
1509 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1513 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1524 goto greater_branch
;
1529 else if (op
== 17 && itype_rs (inst
) == 8)
1530 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1531 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1532 else if (op
== 17 && itype_rs (inst
) == 9
1533 && (itype_rt (inst
) & 2) == 0)
1534 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1535 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1536 else if (op
== 17 && itype_rs (inst
) == 10
1537 && (itype_rt (inst
) & 2) == 0)
1538 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1539 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1542 /* The new PC will be alternate mode. */
1546 reg
= jtype_target (inst
) << 2;
1547 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1548 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1550 else if (is_octeon_bbit_op (op
, gdbarch
))
1554 branch_if
= op
== 58 || op
== 62;
1555 bit
= itype_rt (inst
);
1557 /* Take into account the *32 instructions. */
1558 if (op
== 54 || op
== 62)
1561 if (((get_frame_register_signed (frame
,
1562 itype_rs (inst
)) >> bit
) & 1)
1564 pc
+= mips32_relative_offset (inst
) + 4;
1566 pc
+= 8; /* After the delay slot. */
1570 pc
+= 4; /* Not a branch, next instruction is easy. */
1573 { /* This gets way messy. */
1575 /* Further subdivide into SPECIAL, REGIMM and other. */
1576 switch (op
& 0x07) /* Extract bits 28,27,26. */
1578 case 0: /* SPECIAL */
1579 op
= rtype_funct (inst
);
1584 /* Set PC to that address. */
1585 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1587 case 12: /* SYSCALL */
1589 struct gdbarch_tdep
*tdep
;
1591 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1592 if (tdep
->syscall_next_pc
!= NULL
)
1593 pc
= tdep
->syscall_next_pc (frame
);
1602 break; /* end SPECIAL */
1603 case 1: /* REGIMM */
1605 op
= itype_rt (inst
); /* branch condition */
1610 case 16: /* BLTZAL */
1611 case 18: /* BLTZALL */
1613 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1614 pc
+= mips32_relative_offset (inst
) + 4;
1616 pc
+= 8; /* after the delay slot */
1620 case 17: /* BGEZAL */
1621 case 19: /* BGEZALL */
1622 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1623 pc
+= mips32_relative_offset (inst
) + 4;
1625 pc
+= 8; /* after the delay slot */
1627 case 0x1c: /* BPOSGE32 */
1628 case 0x1e: /* BPOSGE64 */
1630 if (itype_rs (inst
) == 0)
1632 unsigned int pos
= (op
& 2) ? 64 : 32;
1633 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1636 /* No way to handle; it'll most likely trap anyway. */
1639 if ((get_frame_register_unsigned (frame
,
1640 dspctl
) & 0x7f) >= pos
)
1641 pc
+= mips32_relative_offset (inst
);
1646 /* All of the other instructions in the REGIMM category */
1651 break; /* end REGIMM */
1656 reg
= jtype_target (inst
) << 2;
1657 /* Upper four bits get never changed... */
1658 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1661 case 4: /* BEQ, BEQL */
1663 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1664 get_frame_register_signed (frame
, itype_rt (inst
)))
1665 pc
+= mips32_relative_offset (inst
) + 4;
1669 case 5: /* BNE, BNEL */
1671 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1672 get_frame_register_signed (frame
, itype_rt (inst
)))
1673 pc
+= mips32_relative_offset (inst
) + 4;
1677 case 6: /* BLEZ, BLEZL */
1678 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1679 pc
+= mips32_relative_offset (inst
) + 4;
1685 greater_branch
: /* BGTZ, BGTZL */
1686 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1687 pc
+= mips32_relative_offset (inst
) + 4;
1694 } /* mips32_next_pc */
1696 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1700 micromips_relative_offset7 (ULONGEST insn
)
1702 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1705 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1709 micromips_relative_offset10 (ULONGEST insn
)
1711 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1714 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1718 micromips_relative_offset16 (ULONGEST insn
)
1720 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1723 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1726 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1730 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1731 return mips_insn_size (ISA_MICROMIPS
, insn
);
1734 /* Calculate the address of the next microMIPS instruction to execute
1735 after the INSN coprocessor 1 conditional branch instruction at the
1736 address PC. COUNT denotes the number of coprocessor condition bits
1737 examined by the branch. */
1740 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1741 ULONGEST insn
, CORE_ADDR pc
, int count
)
1743 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1744 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1745 int tf
= b5s5_op (insn
>> 16) & 1;
1746 int mask
= (1 << count
) - 1;
1751 /* No way to handle; it'll most likely trap anyway. */
1754 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1755 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1757 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1758 pc
+= micromips_relative_offset16 (insn
);
1760 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1765 /* Calculate the address of the next microMIPS instruction to execute
1766 after the instruction at the address PC. */
1769 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1771 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1774 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1775 pc
+= MIPS_INSN16_SIZE
;
1776 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1778 /* 48-bit instructions. */
1779 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1780 /* No branch or jump instructions in this category. */
1781 pc
+= 2 * MIPS_INSN16_SIZE
;
1784 /* 32-bit instructions. */
1785 case 2 * MIPS_INSN16_SIZE
:
1787 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1788 pc
+= MIPS_INSN16_SIZE
;
1789 switch (micromips_op (insn
>> 16))
1791 case 0x00: /* POOL32A: bits 000000 */
1792 if (b0s6_op (insn
) == 0x3c
1793 /* POOL32Axf: bits 000000 ... 111100 */
1794 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1795 /* JALR, JALR.HB: 000000 000x111100 111100 */
1796 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1797 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1800 case 0x10: /* POOL32I: bits 010000 */
1801 switch (b5s5_op (insn
>> 16))
1803 case 0x00: /* BLTZ: bits 010000 00000 */
1804 case 0x01: /* BLTZAL: bits 010000 00001 */
1805 case 0x11: /* BLTZALS: bits 010000 10001 */
1806 if (get_frame_register_signed (frame
,
1807 b0s5_reg (insn
>> 16)) < 0)
1808 pc
+= micromips_relative_offset16 (insn
);
1810 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1813 case 0x02: /* BGEZ: bits 010000 00010 */
1814 case 0x03: /* BGEZAL: bits 010000 00011 */
1815 case 0x13: /* BGEZALS: bits 010000 10011 */
1816 if (get_frame_register_signed (frame
,
1817 b0s5_reg (insn
>> 16)) >= 0)
1818 pc
+= micromips_relative_offset16 (insn
);
1820 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1823 case 0x04: /* BLEZ: bits 010000 00100 */
1824 if (get_frame_register_signed (frame
,
1825 b0s5_reg (insn
>> 16)) <= 0)
1826 pc
+= micromips_relative_offset16 (insn
);
1828 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1831 case 0x05: /* BNEZC: bits 010000 00101 */
1832 if (get_frame_register_signed (frame
,
1833 b0s5_reg (insn
>> 16)) != 0)
1834 pc
+= micromips_relative_offset16 (insn
);
1837 case 0x06: /* BGTZ: bits 010000 00110 */
1838 if (get_frame_register_signed (frame
,
1839 b0s5_reg (insn
>> 16)) > 0)
1840 pc
+= micromips_relative_offset16 (insn
);
1842 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1845 case 0x07: /* BEQZC: bits 010000 00111 */
1846 if (get_frame_register_signed (frame
,
1847 b0s5_reg (insn
>> 16)) == 0)
1848 pc
+= micromips_relative_offset16 (insn
);
1851 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1852 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1853 if (((insn
>> 16) & 0x3) == 0x0)
1854 /* BC2F, BC2T: don't know how to handle these. */
1858 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1859 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1861 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1862 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1865 /* No way to handle; it'll most likely trap anyway. */
1868 if ((get_frame_register_unsigned (frame
,
1869 dspctl
) & 0x7f) >= pos
)
1870 pc
+= micromips_relative_offset16 (insn
);
1872 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1876 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1877 /* BC1ANY2F: bits 010000 11100 xxx01 */
1878 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1879 /* BC1ANY2T: bits 010000 11101 xxx01 */
1880 if (((insn
>> 16) & 0x2) == 0x0)
1881 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1882 ((insn
>> 16) & 0x1) + 1);
1885 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1886 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1887 if (((insn
>> 16) & 0x3) == 0x1)
1888 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1893 case 0x1d: /* JALS: bits 011101 */
1894 case 0x35: /* J: bits 110101 */
1895 case 0x3d: /* JAL: bits 111101 */
1896 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1899 case 0x25: /* BEQ: bits 100101 */
1900 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1901 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1902 pc
+= micromips_relative_offset16 (insn
);
1904 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1907 case 0x2d: /* BNE: bits 101101 */
1908 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1909 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1910 pc
+= micromips_relative_offset16 (insn
);
1912 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1915 case 0x3c: /* JALX: bits 111100 */
1916 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1921 /* 16-bit instructions. */
1922 case MIPS_INSN16_SIZE
:
1923 switch (micromips_op (insn
))
1925 case 0x11: /* POOL16C: bits 010001 */
1926 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1927 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1928 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1929 else if (b5s5_op (insn
) == 0x18)
1930 /* JRADDIUSP: bits 010001 11000 */
1931 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1934 case 0x23: /* BEQZ16: bits 100011 */
1936 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1938 if (get_frame_register_signed (frame
, rs
) == 0)
1939 pc
+= micromips_relative_offset7 (insn
);
1941 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1945 case 0x2b: /* BNEZ16: bits 101011 */
1947 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1949 if (get_frame_register_signed (frame
, rs
) != 0)
1950 pc
+= micromips_relative_offset7 (insn
);
1952 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1956 case 0x33: /* B16: bits 110011 */
1957 pc
+= micromips_relative_offset10 (insn
);
1966 /* Decoding the next place to set a breakpoint is irregular for the
1967 mips 16 variant, but fortunately, there fewer instructions. We have
1968 to cope ith extensions for 16 bit instructions and a pair of actual
1969 32 bit instructions. We dont want to set a single step instruction
1970 on the extend instruction either. */
1972 /* Lots of mips16 instruction formats */
1973 /* Predicting jumps requires itype,ritype,i8type
1974 and their extensions extItype,extritype,extI8type. */
1975 enum mips16_inst_fmts
1977 itype
, /* 0 immediate 5,10 */
1978 ritype
, /* 1 5,3,8 */
1979 rrtype
, /* 2 5,3,3,5 */
1980 rritype
, /* 3 5,3,3,5 */
1981 rrrtype
, /* 4 5,3,3,3,2 */
1982 rriatype
, /* 5 5,3,3,1,4 */
1983 shifttype
, /* 6 5,3,3,3,2 */
1984 i8type
, /* 7 5,3,8 */
1985 i8movtype
, /* 8 5,3,3,5 */
1986 i8mov32rtype
, /* 9 5,3,5,3 */
1987 i64type
, /* 10 5,3,8 */
1988 ri64type
, /* 11 5,3,3,5 */
1989 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1990 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1991 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1992 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1993 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1994 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1995 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1996 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1997 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1998 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2000 /* I am heaping all the fields of the formats into one structure and
2001 then, only the fields which are involved in instruction extension. */
2005 unsigned int regx
; /* Function in i8 type. */
2010 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2011 for the bits which make up the immediate extension. */
2014 extended_offset (unsigned int extension
)
2018 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2020 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2022 value
|= extension
& 0x1f; /* Extract 4:0. */
2027 /* Only call this function if you know that this is an extendable
2028 instruction. It won't malfunction, but why make excess remote memory
2029 references? If the immediate operands get sign extended or something,
2030 do it after the extension is performed. */
2031 /* FIXME: Every one of these cases needs to worry about sign extension
2032 when the offset is to be used in relative addressing. */
2035 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2037 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2039 pc
&= 0xfffffffe; /* Clear the low order bit. */
2040 target_read_memory (pc
, buf
, 2);
2041 return extract_unsigned_integer (buf
, 2, byte_order
);
2045 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2046 unsigned int extension
,
2048 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2053 switch (insn_format
)
2060 value
= extended_offset ((extension
<< 16) | inst
);
2061 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2065 value
= inst
& 0x7ff;
2066 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2075 { /* A register identifier and an offset. */
2076 /* Most of the fields are the same as I type but the
2077 immediate value is of a different length. */
2081 value
= extended_offset ((extension
<< 16) | inst
);
2082 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2086 value
= inst
& 0xff; /* 8 bits */
2087 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2090 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2096 unsigned long value
;
2097 unsigned int nexthalf
;
2098 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2099 value
= value
<< 16;
2100 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2101 /* Low bit still set. */
2109 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2111 upk
->offset
= offset
;
2118 add_offset_16 (CORE_ADDR pc
, int offset
)
2120 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2124 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2125 unsigned int extension
, unsigned int insn
)
2127 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2128 int op
= (insn
>> 11);
2131 case 2: /* Branch */
2133 struct upk_mips16 upk
;
2134 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2135 pc
+= (upk
.offset
<< 1) + 2;
2138 case 3: /* JAL , JALX - Watch out, these are 32 bit
2141 struct upk_mips16 upk
;
2142 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2143 pc
= add_offset_16 (pc
, upk
.offset
);
2144 if ((insn
>> 10) & 0x01) /* Exchange mode */
2145 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2152 struct upk_mips16 upk
;
2154 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2155 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2157 pc
+= (upk
.offset
<< 1) + 2;
2164 struct upk_mips16 upk
;
2166 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2167 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2169 pc
+= (upk
.offset
<< 1) + 2;
2174 case 12: /* I8 Formats btez btnez */
2176 struct upk_mips16 upk
;
2178 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2179 /* upk.regx contains the opcode */
2180 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2181 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2182 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2183 /* pc = add_offset_16(pc,upk.offset) ; */
2184 pc
+= (upk
.offset
<< 1) + 2;
2189 case 29: /* RR Formats JR, JALR, JALR-RA */
2191 struct upk_mips16 upk
;
2192 /* upk.fmt = rrtype; */
2197 upk
.regx
= (insn
>> 8) & 0x07;
2198 upk
.regy
= (insn
>> 5) & 0x07;
2199 if ((upk
.regy
& 1) == 0)
2200 reg
= mips_reg3_to_reg
[upk
.regx
];
2202 reg
= 31; /* Function return instruction. */
2203 pc
= get_frame_register_signed (frame
, reg
);
2210 /* This is an instruction extension. Fetch the real instruction
2211 (which follows the extension) and decode things based on
2215 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2216 fetch_mips_16 (gdbarch
, pc
));
2229 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2231 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2232 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2233 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2236 /* The mips_next_pc function supports single_step when the remote
2237 target monitor or stub is not developed enough to do a single_step.
2238 It works by decoding the current instruction and predicting where a
2239 branch will go. This isnt hard because all the data is available.
2240 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2242 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2244 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2246 if (mips_pc_is_mips16 (gdbarch
, pc
))
2247 return mips16_next_pc (frame
, pc
);
2248 else if (mips_pc_is_micromips (gdbarch
, pc
))
2249 return micromips_next_pc (frame
, pc
);
2251 return mips32_next_pc (frame
, pc
);
2254 struct mips_frame_cache
2257 struct trad_frame_saved_reg
*saved_regs
;
2260 /* Set a register's saved stack address in temp_saved_regs. If an
2261 address has already been set for this register, do nothing; this
2262 way we will only recognize the first save of a given register in a
2265 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2266 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2267 Strictly speaking, only the second range is used as it is only second
2268 range (the ABI instead of ISA registers) that comes into play when finding
2269 saved registers in a frame. */
2272 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2273 int regnum
, CORE_ADDR offset
)
2275 if (this_cache
!= NULL
2276 && this_cache
->saved_regs
[regnum
].addr
== -1)
2278 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2280 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2286 /* Fetch the immediate value from a MIPS16 instruction.
2287 If the previous instruction was an EXTEND, use it to extend
2288 the upper bits of the immediate value. This is a helper function
2289 for mips16_scan_prologue. */
2292 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2293 unsigned short inst
, /* current instruction */
2294 int nbits
, /* number of bits in imm field */
2295 int scale
, /* scale factor to be applied to imm */
2296 int is_signed
) /* is the imm field signed? */
2300 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2302 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2303 if (offset
& 0x8000) /* check for negative extend */
2304 offset
= 0 - (0x10000 - (offset
& 0xffff));
2305 return offset
| (inst
& 0x1f);
2309 int max_imm
= 1 << nbits
;
2310 int mask
= max_imm
- 1;
2311 int sign_bit
= max_imm
>> 1;
2313 offset
= inst
& mask
;
2314 if (is_signed
&& (offset
& sign_bit
))
2315 offset
= 0 - (max_imm
- offset
);
2316 return offset
* scale
;
2321 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2322 the associated FRAME_CACHE if not null.
2323 Return the address of the first instruction past the prologue. */
2326 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2327 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2328 struct frame_info
*this_frame
,
2329 struct mips_frame_cache
*this_cache
)
2332 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2334 long frame_offset
= 0; /* Size of stack frame. */
2335 long frame_adjust
= 0; /* Offset of FP from SP. */
2336 int frame_reg
= MIPS_SP_REGNUM
;
2337 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2338 unsigned inst
= 0; /* current instruction */
2339 unsigned entry_inst
= 0; /* the entry instruction */
2340 unsigned save_inst
= 0; /* the save instruction */
2343 int extend_bytes
= 0;
2344 int prev_extend_bytes
;
2345 CORE_ADDR end_prologue_addr
= 0;
2347 /* Can be called when there's no process, and hence when there's no
2349 if (this_frame
!= NULL
)
2350 sp
= get_frame_register_signed (this_frame
,
2351 gdbarch_num_regs (gdbarch
)
2356 if (limit_pc
> start_pc
+ 200)
2357 limit_pc
= start_pc
+ 200;
2359 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2361 /* Save the previous instruction. If it's an EXTEND, we'll extract
2362 the immediate offset extension from it in mips16_get_imm. */
2365 /* Fetch and decode the instruction. */
2366 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2369 /* Normally we ignore extend instructions. However, if it is
2370 not followed by a valid prologue instruction, then this
2371 instruction is not part of the prologue either. We must
2372 remember in this case to adjust the end_prologue_addr back
2374 if ((inst
& 0xf800) == 0xf000) /* extend */
2376 extend_bytes
= MIPS_INSN16_SIZE
;
2380 prev_extend_bytes
= extend_bytes
;
2383 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2384 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2386 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2387 if (offset
< 0) /* Negative stack adjustment? */
2388 frame_offset
-= offset
;
2390 /* Exit loop if a positive stack adjustment is found, which
2391 usually means that the stack cleanup code in the function
2392 epilogue is reached. */
2395 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2397 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2398 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2399 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2401 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2403 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2404 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2405 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2407 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2409 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2410 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2412 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2414 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2415 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2417 else if (inst
== 0x673d) /* move $s1, $sp */
2422 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2424 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2425 frame_addr
= sp
+ offset
;
2427 frame_adjust
= offset
;
2429 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2431 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2432 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2433 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2435 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2437 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2438 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2439 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2441 else if ((inst
& 0xf81f) == 0xe809
2442 && (inst
& 0x700) != 0x700) /* entry */
2443 entry_inst
= inst
; /* Save for later processing. */
2444 else if ((inst
& 0xff80) == 0x6480) /* save */
2446 save_inst
= inst
; /* Save for later processing. */
2447 if (prev_extend_bytes
) /* extend */
2448 save_inst
|= prev_inst
<< 16;
2450 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2451 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2452 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2454 /* This instruction is part of the prologue, but we don't
2455 need to do anything special to handle it. */
2459 /* This instruction is not an instruction typically found
2460 in a prologue, so we must have reached the end of the
2462 if (end_prologue_addr
== 0)
2463 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2467 /* The entry instruction is typically the first instruction in a function,
2468 and it stores registers at offsets relative to the value of the old SP
2469 (before the prologue). But the value of the sp parameter to this
2470 function is the new SP (after the prologue has been executed). So we
2471 can't calculate those offsets until we've seen the entire prologue,
2472 and can calculate what the old SP must have been. */
2473 if (entry_inst
!= 0)
2475 int areg_count
= (entry_inst
>> 8) & 7;
2476 int sreg_count
= (entry_inst
>> 6) & 3;
2478 /* The entry instruction always subtracts 32 from the SP. */
2481 /* Now we can calculate what the SP must have been at the
2482 start of the function prologue. */
2485 /* Check if a0-a3 were saved in the caller's argument save area. */
2486 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2488 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2489 offset
+= mips_abi_regsize (gdbarch
);
2492 /* Check if the ra register was pushed on the stack. */
2494 if (entry_inst
& 0x20)
2496 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2497 offset
-= mips_abi_regsize (gdbarch
);
2500 /* Check if the s0 and s1 registers were pushed on the stack. */
2501 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2503 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2504 offset
-= mips_abi_regsize (gdbarch
);
2508 /* The SAVE instruction is similar to ENTRY, except that defined by the
2509 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2510 size of the frame is specified as an immediate field of instruction
2511 and an extended variation exists which lets additional registers and
2512 frame space to be specified. The instruction always treats registers
2513 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2514 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2516 static int args_table
[16] = {
2517 0, 0, 0, 0, 1, 1, 1, 1,
2518 2, 2, 2, 0, 3, 3, 4, -1,
2520 static int astatic_table
[16] = {
2521 0, 1, 2, 3, 0, 1, 2, 3,
2522 0, 1, 2, 4, 0, 1, 0, -1,
2524 int aregs
= (save_inst
>> 16) & 0xf;
2525 int xsregs
= (save_inst
>> 24) & 0x7;
2526 int args
= args_table
[aregs
];
2527 int astatic
= astatic_table
[aregs
];
2532 warning (_("Invalid number of argument registers encoded in SAVE."));
2537 warning (_("Invalid number of static registers encoded in SAVE."));
2541 /* For standard SAVE the frame size of 0 means 128. */
2542 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2543 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2546 frame_offset
+= frame_size
;
2548 /* Now we can calculate what the SP must have been at the
2549 start of the function prologue. */
2552 /* Check if A0-A3 were saved in the caller's argument save area. */
2553 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2555 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2556 offset
+= mips_abi_regsize (gdbarch
);
2561 /* Check if the RA register was pushed on the stack. */
2562 if (save_inst
& 0x40)
2564 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2565 offset
-= mips_abi_regsize (gdbarch
);
2568 /* Check if the S8 register was pushed on the stack. */
2571 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2572 offset
-= mips_abi_regsize (gdbarch
);
2575 /* Check if S2-S7 were pushed on the stack. */
2576 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2578 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2579 offset
-= mips_abi_regsize (gdbarch
);
2582 /* Check if the S1 register was pushed on the stack. */
2583 if (save_inst
& 0x10)
2585 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2586 offset
-= mips_abi_regsize (gdbarch
);
2588 /* Check if the S0 register was pushed on the stack. */
2589 if (save_inst
& 0x20)
2591 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2592 offset
-= mips_abi_regsize (gdbarch
);
2595 /* Check if A0-A3 were pushed on the stack. */
2596 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2598 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2599 offset
-= mips_abi_regsize (gdbarch
);
2603 if (this_cache
!= NULL
)
2606 (get_frame_register_signed (this_frame
,
2607 gdbarch_num_regs (gdbarch
) + frame_reg
)
2608 + frame_offset
- frame_adjust
);
2609 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2610 be able to get rid of the assignment below, evetually. But it's
2611 still needed for now. */
2612 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2613 + mips_regnum (gdbarch
)->pc
]
2614 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2617 /* If we didn't reach the end of the prologue when scanning the function
2618 instructions, then set end_prologue_addr to the address of the
2619 instruction immediately after the last one we scanned. */
2620 if (end_prologue_addr
== 0)
2621 end_prologue_addr
= cur_pc
;
2623 return end_prologue_addr
;
2626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2627 Procedures that use the 32-bit instruction set are handled by the
2628 mips_insn32 unwinder. */
2630 static struct mips_frame_cache
*
2631 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2633 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2634 struct mips_frame_cache
*cache
;
2636 if ((*this_cache
) != NULL
)
2637 return (*this_cache
);
2638 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2639 (*this_cache
) = cache
;
2640 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2642 /* Analyze the function prologue. */
2644 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2645 CORE_ADDR start_addr
;
2647 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2648 if (start_addr
== 0)
2649 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2650 /* We can't analyze the prologue if we couldn't find the begining
2652 if (start_addr
== 0)
2655 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2658 /* gdbarch_sp_regnum contains the value and not the address. */
2659 trad_frame_set_value (cache
->saved_regs
,
2660 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2663 return (*this_cache
);
2667 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2668 struct frame_id
*this_id
)
2670 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2672 /* This marks the outermost frame. */
2673 if (info
->base
== 0)
2675 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2678 static struct value
*
2679 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2680 void **this_cache
, int regnum
)
2682 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2684 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2688 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2689 struct frame_info
*this_frame
, void **this_cache
)
2691 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2692 CORE_ADDR pc
= get_frame_pc (this_frame
);
2693 if (mips_pc_is_mips16 (gdbarch
, pc
))
2698 static const struct frame_unwind mips_insn16_frame_unwind
=
2701 default_frame_unwind_stop_reason
,
2702 mips_insn16_frame_this_id
,
2703 mips_insn16_frame_prev_register
,
2705 mips_insn16_frame_sniffer
2709 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2712 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2717 static const struct frame_base mips_insn16_frame_base
=
2719 &mips_insn16_frame_unwind
,
2720 mips_insn16_frame_base_address
,
2721 mips_insn16_frame_base_address
,
2722 mips_insn16_frame_base_address
2725 static const struct frame_base
*
2726 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2728 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2729 CORE_ADDR pc
= get_frame_pc (this_frame
);
2730 if (mips_pc_is_mips16 (gdbarch
, pc
))
2731 return &mips_insn16_frame_base
;
2736 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2737 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2738 interpreted directly, and then multiplied by 4. */
2741 micromips_decode_imm9 (int imm
)
2743 imm
= (imm
^ 0x100) - 0x100;
2744 if (imm
> -3 && imm
< 2)
2749 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2750 the address of the first instruction past the prologue. */
2753 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2754 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2755 struct frame_info
*this_frame
,
2756 struct mips_frame_cache
*this_cache
)
2758 CORE_ADDR end_prologue_addr
= 0;
2759 int prev_non_prologue_insn
= 0;
2760 int frame_reg
= MIPS_SP_REGNUM
;
2761 int this_non_prologue_insn
;
2762 int non_prologue_insns
= 0;
2763 long frame_offset
= 0; /* Size of stack frame. */
2764 long frame_adjust
= 0; /* Offset of FP from SP. */
2765 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2768 ULONGEST insn
; /* current instruction */
2772 long v1_off
= 0; /* The assumption is LUI will replace it. */
2783 /* Can be called when there's no process, and hence when there's no
2785 if (this_frame
!= NULL
)
2786 sp
= get_frame_register_signed (this_frame
,
2787 gdbarch_num_regs (gdbarch
)
2792 if (limit_pc
> start_pc
+ 200)
2793 limit_pc
= start_pc
+ 200;
2796 /* Permit at most one non-prologue non-control-transfer instruction
2797 in the middle which may have been reordered by the compiler for
2799 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2801 this_non_prologue_insn
= 0;
2804 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2805 loc
+= MIPS_INSN16_SIZE
;
2806 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2808 /* 48-bit instructions. */
2809 case 3 * MIPS_INSN16_SIZE
:
2810 /* No prologue instructions in this category. */
2811 this_non_prologue_insn
= 1;
2812 loc
+= 2 * MIPS_INSN16_SIZE
;
2815 /* 32-bit instructions. */
2816 case 2 * MIPS_INSN16_SIZE
:
2818 insn
|= mips_fetch_instruction (gdbarch
,
2819 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2820 loc
+= MIPS_INSN16_SIZE
;
2821 switch (micromips_op (insn
>> 16))
2823 /* Record $sp/$fp adjustment. */
2824 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2825 case 0x0: /* POOL32A: bits 000000 */
2826 case 0x16: /* POOL32S: bits 010110 */
2827 op
= b0s11_op (insn
);
2828 sreg
= b0s5_reg (insn
>> 16);
2829 treg
= b5s5_reg (insn
>> 16);
2830 dreg
= b11s5_reg (insn
);
2832 /* SUBU: bits 000000 00111010000 */
2833 /* DSUBU: bits 010110 00111010000 */
2834 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2836 /* (D)SUBU $sp, $v1 */
2838 else if (op
!= 0x150
2839 /* ADDU: bits 000000 00101010000 */
2840 /* DADDU: bits 010110 00101010000 */
2841 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2842 this_non_prologue_insn
= 1;
2845 case 0x8: /* POOL32B: bits 001000 */
2846 op
= b12s4_op (insn
);
2847 breg
= b0s5_reg (insn
>> 16);
2848 reglist
= sreg
= b5s5_reg (insn
>> 16);
2849 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2850 if ((op
== 0x9 || op
== 0xc)
2851 /* SWP: bits 001000 1001 */
2852 /* SDP: bits 001000 1100 */
2853 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2854 /* S[DW]P reg,offset($sp) */
2856 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2857 set_reg_offset (gdbarch
, this_cache
,
2859 set_reg_offset (gdbarch
, this_cache
,
2860 sreg
+ 1, sp
+ offset
+ s
);
2862 else if ((op
== 0xd || op
== 0xf)
2863 /* SWM: bits 001000 1101 */
2864 /* SDM: bits 001000 1111 */
2865 && breg
== MIPS_SP_REGNUM
2866 /* SWM reglist,offset($sp) */
2867 && ((reglist
>= 1 && reglist
<= 9)
2868 || (reglist
>= 16 && reglist
<= 25)))
2870 int sreglist
= min(reglist
& 0xf, 8);
2872 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2873 for (i
= 0; i
< sreglist
; i
++)
2874 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2875 if ((reglist
& 0xf) > 8)
2876 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2877 if ((reglist
& 0x10) == 0x10)
2878 set_reg_offset (gdbarch
, this_cache
,
2879 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2882 this_non_prologue_insn
= 1;
2885 /* Record $sp/$fp adjustment. */
2886 /* Discard (D)ADDIU $gp used for PIC code. */
2887 case 0xc: /* ADDIU: bits 001100 */
2888 case 0x17: /* DADDIU: bits 010111 */
2889 sreg
= b0s5_reg (insn
>> 16);
2890 dreg
= b5s5_reg (insn
>> 16);
2891 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2892 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2893 /* (D)ADDIU $sp, imm */
2895 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2896 /* (D)ADDIU $fp, $sp, imm */
2898 frame_addr
= sp
+ offset
;
2899 frame_adjust
= offset
;
2902 else if (sreg
!= 28 || dreg
!= 28)
2903 /* (D)ADDIU $gp, imm */
2904 this_non_prologue_insn
= 1;
2907 /* LUI $v1 is used for larger $sp adjustments. */
2908 /* Discard LUI $gp is used for PIC code. */
2909 case 0x10: /* POOL32I: bits 010000 */
2910 if (b5s5_op (insn
>> 16) == 0xd
2911 /* LUI: bits 010000 001101 */
2912 && b0s5_reg (insn
>> 16) == 3)
2914 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
2915 else if (b5s5_op (insn
>> 16) != 0xd
2916 /* LUI: bits 010000 001101 */
2917 || b0s5_reg (insn
>> 16) != 28)
2919 this_non_prologue_insn
= 1;
2922 /* ORI $v1 is used for larger $sp adjustments. */
2923 case 0x14: /* ORI: bits 010100 */
2924 sreg
= b0s5_reg (insn
>> 16);
2925 dreg
= b5s5_reg (insn
>> 16);
2926 if (sreg
== 3 && dreg
== 3)
2928 v1_off
|= b0s16_imm (insn
);
2930 this_non_prologue_insn
= 1;
2933 case 0x26: /* SWC1: bits 100110 */
2934 case 0x2e: /* SDC1: bits 101110 */
2935 breg
= b0s5_reg (insn
>> 16);
2936 if (breg
!= MIPS_SP_REGNUM
)
2937 /* S[DW]C1 reg,offset($sp) */
2938 this_non_prologue_insn
= 1;
2941 case 0x36: /* SD: bits 110110 */
2942 case 0x3e: /* SW: bits 111110 */
2943 breg
= b0s5_reg (insn
>> 16);
2944 sreg
= b5s5_reg (insn
>> 16);
2945 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2946 if (breg
== MIPS_SP_REGNUM
)
2947 /* S[DW] reg,offset($sp) */
2948 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2950 this_non_prologue_insn
= 1;
2954 this_non_prologue_insn
= 1;
2959 /* 16-bit instructions. */
2960 case MIPS_INSN16_SIZE
:
2961 switch (micromips_op (insn
))
2963 case 0x3: /* MOVE: bits 000011 */
2964 sreg
= b0s5_reg (insn
);
2965 dreg
= b5s5_reg (insn
);
2966 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2972 else if ((sreg
& 0x1c) != 0x4)
2973 /* MOVE reg, $a0-$a3 */
2974 this_non_prologue_insn
= 1;
2977 case 0x11: /* POOL16C: bits 010001 */
2978 if (b6s4_op (insn
) == 0x5)
2979 /* SWM: bits 010001 0101 */
2981 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
2982 reglist
= b4s2_regl (insn
);
2983 for (i
= 0; i
<= reglist
; i
++)
2984 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
2985 set_reg_offset (gdbarch
, this_cache
,
2986 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
2989 this_non_prologue_insn
= 1;
2992 case 0x13: /* POOL16D: bits 010011 */
2993 if ((insn
& 0x1) == 0x1)
2994 /* ADDIUSP: bits 010011 1 */
2995 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
2996 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
2997 /* ADDIUS5: bits 010011 0 */
2998 /* ADDIUS5 $sp, imm */
2999 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3001 this_non_prologue_insn
= 1;
3004 case 0x32: /* SWSP: bits 110010 */
3005 offset
= b0s5_imm (insn
) << 2;
3006 sreg
= b5s5_reg (insn
);
3007 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3011 this_non_prologue_insn
= 1;
3017 frame_offset
-= sp_adj
;
3019 non_prologue_insns
+= this_non_prologue_insn
;
3020 /* Enough non-prologue insns seen or positive stack adjustment? */
3021 if (end_prologue_addr
== 0 && (non_prologue_insns
> 1 || sp_adj
> 0))
3023 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3026 prev_non_prologue_insn
= this_non_prologue_insn
;
3030 if (this_cache
!= NULL
)
3033 (get_frame_register_signed (this_frame
,
3034 gdbarch_num_regs (gdbarch
) + frame_reg
)
3035 + frame_offset
- frame_adjust
);
3036 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3037 be able to get rid of the assignment below, evetually. But it's
3038 still needed for now. */
3039 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3040 + mips_regnum (gdbarch
)->pc
]
3041 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3044 /* If we didn't reach the end of the prologue when scanning the function
3045 instructions, then set end_prologue_addr to the address of the
3046 instruction immediately after the last one we scanned. Unless the
3047 last one looked like a non-prologue instruction (and we looked ahead),
3048 in which case use its address instead. */
3049 if (end_prologue_addr
== 0)
3050 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3052 return end_prologue_addr
;
3055 /* Heuristic unwinder for procedures using microMIPS instructions.
3056 Procedures that use the 32-bit instruction set are handled by the
3057 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3059 static struct mips_frame_cache
*
3060 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3062 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3063 struct mips_frame_cache
*cache
;
3065 if ((*this_cache
) != NULL
)
3066 return (*this_cache
);
3068 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3069 (*this_cache
) = cache
;
3070 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3072 /* Analyze the function prologue. */
3074 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3075 CORE_ADDR start_addr
;
3077 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3078 if (start_addr
== 0)
3079 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3080 /* We can't analyze the prologue if we couldn't find the begining
3082 if (start_addr
== 0)
3085 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3088 /* gdbarch_sp_regnum contains the value and not the address. */
3089 trad_frame_set_value (cache
->saved_regs
,
3090 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3093 return (*this_cache
);
3097 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3098 struct frame_id
*this_id
)
3100 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3102 /* This marks the outermost frame. */
3103 if (info
->base
== 0)
3105 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3108 static struct value
*
3109 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3110 void **this_cache
, int regnum
)
3112 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3114 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3118 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3119 struct frame_info
*this_frame
, void **this_cache
)
3121 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3122 CORE_ADDR pc
= get_frame_pc (this_frame
);
3124 if (mips_pc_is_micromips (gdbarch
, pc
))
3129 static const struct frame_unwind mips_micro_frame_unwind
=
3132 default_frame_unwind_stop_reason
,
3133 mips_micro_frame_this_id
,
3134 mips_micro_frame_prev_register
,
3136 mips_micro_frame_sniffer
3140 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3143 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3148 static const struct frame_base mips_micro_frame_base
=
3150 &mips_micro_frame_unwind
,
3151 mips_micro_frame_base_address
,
3152 mips_micro_frame_base_address
,
3153 mips_micro_frame_base_address
3156 static const struct frame_base
*
3157 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3159 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3160 CORE_ADDR pc
= get_frame_pc (this_frame
);
3162 if (mips_pc_is_micromips (gdbarch
, pc
))
3163 return &mips_micro_frame_base
;
3168 /* Mark all the registers as unset in the saved_regs array
3169 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3172 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3174 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3178 const int num_regs
= gdbarch_num_regs (gdbarch
);
3181 for (i
= 0; i
< num_regs
; i
++)
3183 this_cache
->saved_regs
[i
].addr
= -1;
3188 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3189 the associated FRAME_CACHE if not null.
3190 Return the address of the first instruction past the prologue. */
3193 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3194 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3195 struct frame_info
*this_frame
,
3196 struct mips_frame_cache
*this_cache
)
3199 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3203 int frame_reg
= MIPS_SP_REGNUM
;
3205 CORE_ADDR end_prologue_addr
= 0;
3206 int seen_sp_adjust
= 0;
3207 int load_immediate_bytes
= 0;
3208 int in_delay_slot
= 0;
3209 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3211 /* Can be called when there's no process, and hence when there's no
3213 if (this_frame
!= NULL
)
3214 sp
= get_frame_register_signed (this_frame
,
3215 gdbarch_num_regs (gdbarch
)
3220 if (limit_pc
> start_pc
+ 200)
3221 limit_pc
= start_pc
+ 200;
3226 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3228 unsigned long inst
, high_word
, low_word
;
3231 /* Fetch the instruction. */
3232 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3235 /* Save some code by pre-extracting some useful fields. */
3236 high_word
= (inst
>> 16) & 0xffff;
3237 low_word
= inst
& 0xffff;
3238 reg
= high_word
& 0x1f;
3240 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3241 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3242 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3244 if (low_word
& 0x8000) /* Negative stack adjustment? */
3245 frame_offset
+= 0x10000 - low_word
;
3247 /* Exit loop if a positive stack adjustment is found, which
3248 usually means that the stack cleanup code in the function
3249 epilogue is reached. */
3253 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3254 && !regsize_is_64_bits
)
3256 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3258 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3259 && regsize_is_64_bits
)
3261 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3262 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3264 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3266 /* Old gcc frame, r30 is virtual frame pointer. */
3267 if ((long) low_word
!= frame_offset
)
3268 frame_addr
= sp
+ low_word
;
3269 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3271 unsigned alloca_adjust
;
3274 frame_addr
= get_frame_register_signed
3275 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3278 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3279 if (alloca_adjust
> 0)
3281 /* FP > SP + frame_size. This may be because of
3282 an alloca or somethings similar. Fix sp to
3283 "pre-alloca" value, and try again. */
3284 sp
+= alloca_adjust
;
3285 /* Need to reset the status of all registers. Otherwise,
3286 we will hit a guard that prevents the new address
3287 for each register to be recomputed during the second
3289 reset_saved_regs (gdbarch
, this_cache
);
3294 /* move $30,$sp. With different versions of gas this will be either
3295 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3296 Accept any one of these. */
3297 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3299 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3300 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3302 unsigned alloca_adjust
;
3305 frame_addr
= get_frame_register_signed
3306 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3308 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3309 if (alloca_adjust
> 0)
3311 /* FP > SP + frame_size. This may be because of
3312 an alloca or somethings similar. Fix sp to
3313 "pre-alloca" value, and try again. */
3315 /* Need to reset the status of all registers. Otherwise,
3316 we will hit a guard that prevents the new address
3317 for each register to be recomputed during the second
3319 reset_saved_regs (gdbarch
, this_cache
);
3324 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3325 && !regsize_is_64_bits
)
3327 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3329 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3330 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3331 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3332 || high_word
== 0x3c1c /* lui $gp,n */
3333 || high_word
== 0x279c /* addiu $gp,$gp,n */
3334 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3335 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3338 /* These instructions are part of the prologue, but we don't
3339 need to do anything special to handle them. */
3341 /* The instructions below load $at or $t0 with an immediate
3342 value in preparation for a stack adjustment via
3343 subu $sp,$sp,[$at,$t0]. These instructions could also
3344 initialize a local variable, so we accept them only before
3345 a stack adjustment instruction was seen. */
3346 else if (!seen_sp_adjust
3347 && (high_word
== 0x3c01 /* lui $at,n */
3348 || high_word
== 0x3c08 /* lui $t0,n */
3349 || high_word
== 0x3421 /* ori $at,$at,n */
3350 || high_word
== 0x3508 /* ori $t0,$t0,n */
3351 || high_word
== 0x3401 /* ori $at,$zero,n */
3352 || high_word
== 0x3408 /* ori $t0,$zero,n */
3355 if (end_prologue_addr
== 0)
3356 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3360 /* This instruction is not an instruction typically found
3361 in a prologue, so we must have reached the end of the
3363 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3364 loop now? Why would we need to continue scanning the function
3366 if (end_prologue_addr
== 0)
3367 end_prologue_addr
= cur_pc
;
3369 /* Check for branches and jumps. For now, only jump to
3370 register are caught (i.e. returns). */
3371 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
3375 /* If the previous instruction was a jump, we must have reached
3376 the end of the prologue by now. Stop scanning so that we do
3377 not go past the function return. */
3382 if (this_cache
!= NULL
)
3385 (get_frame_register_signed (this_frame
,
3386 gdbarch_num_regs (gdbarch
) + frame_reg
)
3388 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3389 this assignment below, eventually. But it's still needed
3391 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3392 + mips_regnum (gdbarch
)->pc
]
3393 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3397 /* If we didn't reach the end of the prologue when scanning the function
3398 instructions, then set end_prologue_addr to the address of the
3399 instruction immediately after the last one we scanned. */
3400 /* brobecker/2004-10-10: I don't think this would ever happen, but
3401 we may as well be careful and do our best if we have a null
3402 end_prologue_addr. */
3403 if (end_prologue_addr
== 0)
3404 end_prologue_addr
= cur_pc
;
3406 /* In a frameless function, we might have incorrectly
3407 skipped some load immediate instructions. Undo the skipping
3408 if the load immediate was not followed by a stack adjustment. */
3409 if (load_immediate_bytes
&& !seen_sp_adjust
)
3410 end_prologue_addr
-= load_immediate_bytes
;
3412 return end_prologue_addr
;
3415 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3416 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3417 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3418 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3420 static struct mips_frame_cache
*
3421 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3423 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3424 struct mips_frame_cache
*cache
;
3426 if ((*this_cache
) != NULL
)
3427 return (*this_cache
);
3429 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3430 (*this_cache
) = cache
;
3431 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3433 /* Analyze the function prologue. */
3435 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3436 CORE_ADDR start_addr
;
3438 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3439 if (start_addr
== 0)
3440 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3441 /* We can't analyze the prologue if we couldn't find the begining
3443 if (start_addr
== 0)
3446 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3449 /* gdbarch_sp_regnum contains the value and not the address. */
3450 trad_frame_set_value (cache
->saved_regs
,
3451 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3454 return (*this_cache
);
3458 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3459 struct frame_id
*this_id
)
3461 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3463 /* This marks the outermost frame. */
3464 if (info
->base
== 0)
3466 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3469 static struct value
*
3470 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3471 void **this_cache
, int regnum
)
3473 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3475 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3479 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3480 struct frame_info
*this_frame
, void **this_cache
)
3482 CORE_ADDR pc
= get_frame_pc (this_frame
);
3483 if (mips_pc_is_mips (pc
))
3488 static const struct frame_unwind mips_insn32_frame_unwind
=
3491 default_frame_unwind_stop_reason
,
3492 mips_insn32_frame_this_id
,
3493 mips_insn32_frame_prev_register
,
3495 mips_insn32_frame_sniffer
3499 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3502 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3507 static const struct frame_base mips_insn32_frame_base
=
3509 &mips_insn32_frame_unwind
,
3510 mips_insn32_frame_base_address
,
3511 mips_insn32_frame_base_address
,
3512 mips_insn32_frame_base_address
3515 static const struct frame_base
*
3516 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3518 CORE_ADDR pc
= get_frame_pc (this_frame
);
3519 if (mips_pc_is_mips (pc
))
3520 return &mips_insn32_frame_base
;
3525 static struct trad_frame_cache
*
3526 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3529 CORE_ADDR start_addr
;
3530 CORE_ADDR stack_addr
;
3531 struct trad_frame_cache
*this_trad_cache
;
3532 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3533 int num_regs
= gdbarch_num_regs (gdbarch
);
3535 if ((*this_cache
) != NULL
)
3536 return (*this_cache
);
3537 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3538 (*this_cache
) = this_trad_cache
;
3540 /* The return address is in the link register. */
3541 trad_frame_set_reg_realreg (this_trad_cache
,
3542 gdbarch_pc_regnum (gdbarch
),
3543 num_regs
+ MIPS_RA_REGNUM
);
3545 /* Frame ID, since it's a frameless / stackless function, no stack
3546 space is allocated and SP on entry is the current SP. */
3547 pc
= get_frame_pc (this_frame
);
3548 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3549 stack_addr
= get_frame_register_signed (this_frame
,
3550 num_regs
+ MIPS_SP_REGNUM
);
3551 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3553 /* Assume that the frame's base is the same as the
3555 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3557 return this_trad_cache
;
3561 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3562 struct frame_id
*this_id
)
3564 struct trad_frame_cache
*this_trad_cache
3565 = mips_stub_frame_cache (this_frame
, this_cache
);
3566 trad_frame_get_id (this_trad_cache
, this_id
);
3569 static struct value
*
3570 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3571 void **this_cache
, int regnum
)
3573 struct trad_frame_cache
*this_trad_cache
3574 = mips_stub_frame_cache (this_frame
, this_cache
);
3575 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3579 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3580 struct frame_info
*this_frame
, void **this_cache
)
3583 struct obj_section
*s
;
3584 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3585 struct bound_minimal_symbol msym
;
3587 /* Use the stub unwinder for unreadable code. */
3588 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3591 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3594 /* Calling a PIC function from a non-PIC function passes through a
3595 stub. The stub for foo is named ".pic.foo". */
3596 msym
= lookup_minimal_symbol_by_pc (pc
);
3597 if (msym
.minsym
!= NULL
3598 && SYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3599 && strncmp (SYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) == 0)
3605 static const struct frame_unwind mips_stub_frame_unwind
=
3608 default_frame_unwind_stop_reason
,
3609 mips_stub_frame_this_id
,
3610 mips_stub_frame_prev_register
,
3612 mips_stub_frame_sniffer
3616 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3619 struct trad_frame_cache
*this_trad_cache
3620 = mips_stub_frame_cache (this_frame
, this_cache
);
3621 return trad_frame_get_this_base (this_trad_cache
);
3624 static const struct frame_base mips_stub_frame_base
=
3626 &mips_stub_frame_unwind
,
3627 mips_stub_frame_base_address
,
3628 mips_stub_frame_base_address
,
3629 mips_stub_frame_base_address
3632 static const struct frame_base
*
3633 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3635 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3636 return &mips_stub_frame_base
;
3641 /* mips_addr_bits_remove - remove useless address bits */
3644 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3646 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3648 if (is_compact_addr (addr
))
3649 addr
= unmake_compact_addr (addr
);
3651 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3652 /* This hack is a work-around for existing boards using PMON, the
3653 simulator, and any other 64-bit targets that doesn't have true
3654 64-bit addressing. On these targets, the upper 32 bits of
3655 addresses are ignored by the hardware. Thus, the PC or SP are
3656 likely to have been sign extended to all 1s by instruction
3657 sequences that load 32-bit addresses. For example, a typical
3658 piece of code that loads an address is this:
3660 lui $r2, <upper 16 bits>
3661 ori $r2, <lower 16 bits>
3663 But the lui sign-extends the value such that the upper 32 bits
3664 may be all 1s. The workaround is simply to mask off these
3665 bits. In the future, gcc may be changed to support true 64-bit
3666 addressing, and this masking will have to be disabled. */
3667 return addr
&= 0xffffffffUL
;
3673 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3674 instruction and ending with a SC/SCD instruction. If such a sequence
3675 is found, attempt to step through it. A breakpoint is placed at the end of
3678 /* Instructions used during single-stepping of atomic sequences, standard
3680 #define LL_OPCODE 0x30
3681 #define LLD_OPCODE 0x34
3682 #define SC_OPCODE 0x38
3683 #define SCD_OPCODE 0x3c
3686 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3687 struct address_space
*aspace
, CORE_ADDR pc
)
3689 CORE_ADDR breaks
[2] = {-1, -1};
3691 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3695 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3696 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3698 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3699 /* Assume all atomic sequences start with a ll/lld instruction. */
3700 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3703 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3705 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3708 loc
+= MIPS_INSN32_SIZE
;
3709 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3711 /* Assume that there is at most one branch in the atomic
3712 sequence. If a branch is found, put a breakpoint in its
3713 destination address. */
3714 switch (itype_op (insn
))
3716 case 0: /* SPECIAL */
3717 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3718 return 0; /* fallback to the standard single-step code. */
3720 case 1: /* REGIMM */
3721 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3722 || ((itype_rt (insn
) & 0x1e) == 0
3723 && itype_rs (insn
) == 0)); /* BPOSGE* */
3727 return 0; /* fallback to the standard single-step code. */
3734 case 22: /* BLEZL */
3735 case 23: /* BGTTL */
3739 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3740 && (itype_rt (insn
) & 0x2) == 0);
3741 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3746 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3751 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3752 if (last_breakpoint
>= 1)
3753 return 0; /* More than one branch found, fallback to the
3754 standard single-step code. */
3755 breaks
[1] = branch_bp
;
3759 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3763 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3764 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3767 loc
+= MIPS_INSN32_SIZE
;
3769 /* Insert a breakpoint right after the end of the atomic sequence. */
3772 /* Check for duplicated breakpoints. Check also for a breakpoint
3773 placed (branch instruction's destination) in the atomic sequence. */
3774 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3775 last_breakpoint
= 0;
3777 /* Effectively inserts the breakpoints. */
3778 for (index
= 0; index
<= last_breakpoint
; index
++)
3779 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3785 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3786 struct address_space
*aspace
,
3789 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3790 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3791 CORE_ADDR breaks
[2] = {-1, -1};
3792 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3800 /* Assume all atomic sequences start with a ll/lld instruction. */
3801 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3802 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3804 loc
+= MIPS_INSN16_SIZE
;
3806 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3807 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3809 loc
+= MIPS_INSN16_SIZE
;
3811 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3812 that no atomic sequence is longer than "atomic_sequence_length"
3814 for (insn_count
= 0;
3815 !sc_found
&& insn_count
< atomic_sequence_length
;
3820 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3821 loc
+= MIPS_INSN16_SIZE
;
3823 /* Assume that there is at most one conditional branch in the
3824 atomic sequence. If a branch is found, put a breakpoint in
3825 its destination address. */
3826 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3828 /* 48-bit instructions. */
3829 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3830 loc
+= 2 * MIPS_INSN16_SIZE
;
3833 /* 32-bit instructions. */
3834 case 2 * MIPS_INSN16_SIZE
:
3835 switch (micromips_op (insn
))
3837 case 0x10: /* POOL32I: bits 010000 */
3838 if ((b5s5_op (insn
) & 0x18) != 0x0
3839 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3840 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3841 && (b5s5_op (insn
) & 0x1d) != 0x11
3842 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3843 && ((b5s5_op (insn
) & 0x1e) != 0x14
3844 || (insn
& 0x3) != 0x0)
3845 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3846 && (b5s5_op (insn
) & 0x1e) != 0x1a
3847 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3848 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3849 || (insn
& 0x3) != 0x0)
3850 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3851 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3852 || (insn
& 0x3) != 0x1))
3853 /* BC1ANY*: bits 010000 111xx xxx01 */
3857 case 0x25: /* BEQ: bits 100101 */
3858 case 0x2d: /* BNE: bits 101101 */
3860 insn
|= mips_fetch_instruction (gdbarch
,
3861 ISA_MICROMIPS
, loc
, NULL
);
3862 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3863 + micromips_relative_offset16 (insn
));
3867 case 0x00: /* POOL32A: bits 000000 */
3869 insn
|= mips_fetch_instruction (gdbarch
,
3870 ISA_MICROMIPS
, loc
, NULL
);
3871 if (b0s6_op (insn
) != 0x3c
3872 /* POOL32Axf: bits 000000 ... 111100 */
3873 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3874 /* JALR, JALR.HB: 000000 000x111100 111100 */
3875 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3879 case 0x1d: /* JALS: bits 011101 */
3880 case 0x35: /* J: bits 110101 */
3881 case 0x3d: /* JAL: bits 111101 */
3882 case 0x3c: /* JALX: bits 111100 */
3883 return 0; /* Fall back to the standard single-step code. */
3885 case 0x18: /* POOL32C: bits 011000 */
3886 if ((b12s4_op (insn
) & 0xb) == 0xb)
3887 /* SC, SCD: bits 011000 1x11 */
3891 loc
+= MIPS_INSN16_SIZE
;
3894 /* 16-bit instructions. */
3895 case MIPS_INSN16_SIZE
:
3896 switch (micromips_op (insn
))
3898 case 0x23: /* BEQZ16: bits 100011 */
3899 case 0x2b: /* BNEZ16: bits 101011 */
3900 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
3904 case 0x11: /* POOL16C: bits 010001 */
3905 if ((b5s5_op (insn
) & 0x1c) != 0xc
3906 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3907 && b5s5_op (insn
) != 0x18)
3908 /* JRADDIUSP: bits 010001 11000 */
3910 return 0; /* Fall back to the standard single-step code. */
3912 case 0x33: /* B16: bits 110011 */
3913 return 0; /* Fall back to the standard single-step code. */
3919 if (last_breakpoint
>= 1)
3920 return 0; /* More than one branch found, fallback to the
3921 standard single-step code. */
3922 breaks
[1] = branch_bp
;
3929 /* Insert a breakpoint right after the end of the atomic sequence. */
3932 /* Check for duplicated breakpoints. Check also for a breakpoint
3933 placed (branch instruction's destination) in the atomic sequence */
3934 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3935 last_breakpoint
= 0;
3937 /* Effectively inserts the breakpoints. */
3938 for (index
= 0; index
<= last_breakpoint
; index
++)
3939 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3945 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3946 struct address_space
*aspace
, CORE_ADDR pc
)
3948 if (mips_pc_is_mips (pc
))
3949 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3950 else if (mips_pc_is_micromips (gdbarch
, pc
))
3951 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3956 /* mips_software_single_step() is called just before we want to resume
3957 the inferior, if we want to single-step it but there is no hardware
3958 or kernel single-step support (MIPS on GNU/Linux for example). We find
3959 the target of the coming instruction and breakpoint it. */
3962 mips_software_single_step (struct frame_info
*frame
)
3964 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3965 struct address_space
*aspace
= get_frame_address_space (frame
);
3966 CORE_ADDR pc
, next_pc
;
3968 pc
= get_frame_pc (frame
);
3969 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
3972 next_pc
= mips_next_pc (frame
, pc
);
3974 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3978 /* Test whether the PC points to the return instruction at the
3979 end of a function. */
3982 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3987 /* This used to check for MIPS16, but this piece of code is never
3988 called for MIPS16 functions. And likewise microMIPS ones. */
3989 gdb_assert (mips_pc_is_mips (pc
));
3991 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
3993 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
3997 /* This fencepost looks highly suspicious to me. Removing it also
3998 seems suspicious as it could affect remote debugging across serial
4002 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4008 struct inferior
*inf
;
4010 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4012 fence
= start_pc
- heuristic_fence_post
;
4016 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4017 fence
= VM_MIN_ADDRESS
;
4019 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4021 inf
= current_inferior ();
4023 /* Search back for previous return. */
4024 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4025 if (start_pc
< fence
)
4027 /* It's not clear to me why we reach this point when
4028 stop_soon, but with this test, at least we
4029 don't print out warnings for every child forked (eg, on
4030 decstation). 22apr93 rich@cygnus.com. */
4031 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4033 static int blurb_printed
= 0;
4035 warning (_("GDB can't find the start of the function at %s."),
4036 paddress (gdbarch
, pc
));
4040 /* This actually happens frequently in embedded
4041 development, when you first connect to a board
4042 and your stack pointer and pc are nowhere in
4043 particular. This message needs to give people
4044 in that situation enough information to
4045 determine that it's no big deal. */
4046 printf_filtered ("\n\
4047 GDB is unable to find the start of the function at %s\n\
4048 and thus can't determine the size of that function's stack frame.\n\
4049 This means that GDB may be unable to access that stack frame, or\n\
4050 the frames below it.\n\
4051 This problem is most likely caused by an invalid program counter or\n\
4053 However, if you think GDB should simply search farther back\n\
4054 from %s for code which looks like the beginning of a\n\
4055 function, you can increase the range of the search using the `set\n\
4056 heuristic-fence-post' command.\n",
4057 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4064 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4066 unsigned short inst
;
4068 /* On MIPS16, any one of the following is likely to be the
4069 start of a function:
4075 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4076 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4077 if ((inst
& 0xff80) == 0x6480) /* save */
4079 if (start_pc
- instlen
>= fence
)
4081 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4082 start_pc
- instlen
, NULL
);
4083 if ((inst
& 0xf800) == 0xf000) /* extend */
4084 start_pc
-= instlen
;
4088 else if (((inst
& 0xf81f) == 0xe809
4089 && (inst
& 0x700) != 0x700) /* entry */
4090 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4091 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4092 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4094 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4095 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4100 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4108 /* On microMIPS, any one of the following is likely to be the
4109 start of a function:
4113 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4114 switch (micromips_op (insn
))
4116 case 0xc: /* ADDIU: bits 001100 */
4117 case 0x17: /* DADDIU: bits 010111 */
4118 sreg
= b0s5_reg (insn
);
4119 dreg
= b5s5_reg (insn
);
4121 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4122 pc
+ MIPS_INSN16_SIZE
, NULL
);
4123 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4124 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4125 /* (D)ADDIU $sp, imm */
4130 case 0x10: /* POOL32I: bits 010000 */
4131 if (b5s5_op (insn
) == 0xd
4132 /* LUI: bits 010000 001101 */
4133 && b0s5_reg (insn
>> 16) == 28)
4138 case 0x13: /* POOL16D: bits 010011 */
4139 if ((insn
& 0x1) == 0x1)
4140 /* ADDIUSP: bits 010011 1 */
4142 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4148 /* ADDIUS5: bits 010011 0 */
4150 dreg
= b5s5_reg (insn
);
4151 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4152 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4153 /* ADDIUS5 $sp, -imm */
4161 else if (mips_about_to_return (gdbarch
, start_pc
))
4163 /* Skip return and its delay slot. */
4164 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4171 struct mips_objfile_private
4177 /* According to the current ABI, should the type be passed in a
4178 floating-point register (assuming that there is space)? When there
4179 is no FPU, FP are not even considered as possible candidates for
4180 FP registers and, consequently this returns false - forces FP
4181 arguments into integer registers. */
4184 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4185 struct type
*arg_type
)
4187 return ((typecode
== TYPE_CODE_FLT
4188 || (MIPS_EABI (gdbarch
)
4189 && (typecode
== TYPE_CODE_STRUCT
4190 || typecode
== TYPE_CODE_UNION
)
4191 && TYPE_NFIELDS (arg_type
) == 1
4192 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4194 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4197 /* On o32, argument passing in GPRs depends on the alignment of the type being
4198 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4201 mips_type_needs_double_align (struct type
*type
)
4203 enum type_code typecode
= TYPE_CODE (type
);
4205 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4207 else if (typecode
== TYPE_CODE_STRUCT
)
4209 if (TYPE_NFIELDS (type
) < 1)
4211 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4213 else if (typecode
== TYPE_CODE_UNION
)
4217 n
= TYPE_NFIELDS (type
);
4218 for (i
= 0; i
< n
; i
++)
4219 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4226 /* Adjust the address downward (direction of stack growth) so that it
4227 is correctly aligned for a new stack frame. */
4229 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4231 return align_down (addr
, 16);
4234 /* Implement the "push_dummy_code" gdbarch method. */
4237 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4238 CORE_ADDR funaddr
, struct value
**args
,
4239 int nargs
, struct type
*value_type
,
4240 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4241 struct regcache
*regcache
)
4243 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4247 /* Reserve enough room on the stack for our breakpoint instruction. */
4248 bp_slot
= sp
- sizeof (nop_insn
);
4250 /* Return to microMIPS mode if calling microMIPS code to avoid
4251 triggering an address error exception on processors that only
4252 support microMIPS execution. */
4253 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4254 ? make_compact_addr (bp_slot
) : bp_slot
);
4256 /* The breakpoint layer automatically adjusts the address of
4257 breakpoints inserted in a branch delay slot. With enough
4258 bad luck, the 4 bytes located just before our breakpoint
4259 instruction could look like a branch instruction, and thus
4260 trigger the adjustement, and break the function call entirely.
4261 So, we reserve those 4 bytes and write a nop instruction
4262 to prevent that from happening. */
4263 nop_addr
= bp_slot
- sizeof (nop_insn
);
4264 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4265 sp
= mips_frame_align (gdbarch
, nop_addr
);
4267 /* Inferior resumes at the function entry point. */
4274 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4275 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4276 int nargs
, struct value
**args
, CORE_ADDR sp
,
4277 int struct_return
, CORE_ADDR struct_addr
)
4283 int stack_offset
= 0;
4284 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4285 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4286 int regsize
= mips_abi_regsize (gdbarch
);
4288 /* For shared libraries, "t9" needs to point at the function
4290 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4292 /* Set the return address register to point to the entry point of
4293 the program, where a breakpoint lies in wait. */
4294 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4296 /* First ensure that the stack and structure return address (if any)
4297 are properly aligned. The stack has to be at least 64-bit
4298 aligned even on 32-bit machines, because doubles must be 64-bit
4299 aligned. For n32 and n64, stack frames need to be 128-bit
4300 aligned, so we round to this widest known alignment. */
4302 sp
= align_down (sp
, 16);
4303 struct_addr
= align_down (struct_addr
, 16);
4305 /* Now make space on the stack for the args. We allocate more
4306 than necessary for EABI, because the first few arguments are
4307 passed in registers, but that's OK. */
4308 for (argnum
= 0; argnum
< nargs
; argnum
++)
4309 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4310 sp
-= align_up (len
, 16);
4313 fprintf_unfiltered (gdb_stdlog
,
4314 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4315 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4317 /* Initialize the integer and float register pointers. */
4318 argreg
= MIPS_A0_REGNUM
;
4319 float_argreg
= mips_fpa0_regnum (gdbarch
);
4321 /* The struct_return pointer occupies the first parameter-passing reg. */
4325 fprintf_unfiltered (gdb_stdlog
,
4326 "mips_eabi_push_dummy_call: "
4327 "struct_return reg=%d %s\n",
4328 argreg
, paddress (gdbarch
, struct_addr
));
4329 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4332 /* Now load as many as possible of the first arguments into
4333 registers, and push the rest onto the stack. Loop thru args
4334 from first to last. */
4335 for (argnum
= 0; argnum
< nargs
; argnum
++)
4337 const gdb_byte
*val
;
4338 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4339 struct value
*arg
= args
[argnum
];
4340 struct type
*arg_type
= check_typedef (value_type (arg
));
4341 int len
= TYPE_LENGTH (arg_type
);
4342 enum type_code typecode
= TYPE_CODE (arg_type
);
4345 fprintf_unfiltered (gdb_stdlog
,
4346 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4347 argnum
+ 1, len
, (int) typecode
);
4349 /* Function pointer arguments to mips16 code need to be made into
4351 if (typecode
== TYPE_CODE_PTR
4352 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4354 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4356 if (mips_pc_is_mips (addr
))
4357 val
= value_contents (arg
);
4360 store_signed_integer (valbuf
, len
, byte_order
,
4361 make_compact_addr (addr
));
4365 /* The EABI passes structures that do not fit in a register by
4367 else if (len
> regsize
4368 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4370 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4371 value_address (arg
));
4372 typecode
= TYPE_CODE_PTR
;
4376 fprintf_unfiltered (gdb_stdlog
, " push");
4379 val
= value_contents (arg
);
4381 /* 32-bit ABIs always start floating point arguments in an
4382 even-numbered floating point register. Round the FP register
4383 up before the check to see if there are any FP registers
4384 left. Non MIPS_EABI targets also pass the FP in the integer
4385 registers so also round up normal registers. */
4386 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4388 if ((float_argreg
& 1))
4392 /* Floating point arguments passed in registers have to be
4393 treated specially. On 32-bit architectures, doubles
4394 are passed in register pairs; the even register gets
4395 the low word, and the odd register gets the high word.
4396 On non-EABI processors, the first two floating point arguments are
4397 also copied to general registers, because MIPS16 functions
4398 don't use float registers for arguments. This duplication of
4399 arguments in general registers can't hurt non-MIPS16 functions
4400 because those registers are normally skipped. */
4401 /* MIPS_EABI squeezes a struct that contains a single floating
4402 point value into an FP register instead of pushing it onto the
4404 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4405 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4407 /* EABI32 will pass doubles in consecutive registers, even on
4408 64-bit cores. At one time, we used to check the size of
4409 `float_argreg' to determine whether or not to pass doubles
4410 in consecutive registers, but this is not sufficient for
4411 making the ABI determination. */
4412 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4414 int low_offset
= gdbarch_byte_order (gdbarch
)
4415 == BFD_ENDIAN_BIG
? 4 : 0;
4418 /* Write the low word of the double to the even register(s). */
4419 regval
= extract_signed_integer (val
+ low_offset
,
4422 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4423 float_argreg
, phex (regval
, 4));
4424 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4426 /* Write the high word of the double to the odd register(s). */
4427 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4430 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4431 float_argreg
, phex (regval
, 4));
4432 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4436 /* This is a floating point value that fits entirely
4437 in a single register. */
4438 /* On 32 bit ABI's the float_argreg is further adjusted
4439 above to ensure that it is even register aligned. */
4440 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4442 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4443 float_argreg
, phex (regval
, len
));
4444 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4449 /* Copy the argument to general registers or the stack in
4450 register-sized pieces. Large arguments are split between
4451 registers and stack. */
4452 /* Note: structs whose size is not a multiple of regsize
4453 are treated specially: Irix cc passes
4454 them in registers where gcc sometimes puts them on the
4455 stack. For maximum compatibility, we will put them in
4457 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4459 /* Note: Floating-point values that didn't fit into an FP
4460 register are only written to memory. */
4463 /* Remember if the argument was written to the stack. */
4464 int stack_used_p
= 0;
4465 int partial_len
= (len
< regsize
? len
: regsize
);
4468 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4471 /* Write this portion of the argument to the stack. */
4472 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4474 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4476 /* Should shorter than int integer values be
4477 promoted to int before being stored? */
4478 int longword_offset
= 0;
4481 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4484 && (typecode
== TYPE_CODE_INT
4485 || typecode
== TYPE_CODE_PTR
4486 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4487 longword_offset
= regsize
- len
;
4488 else if ((typecode
== TYPE_CODE_STRUCT
4489 || typecode
== TYPE_CODE_UNION
)
4490 && TYPE_LENGTH (arg_type
) < regsize
)
4491 longword_offset
= regsize
- len
;
4496 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4497 paddress (gdbarch
, stack_offset
));
4498 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4499 paddress (gdbarch
, longword_offset
));
4502 addr
= sp
+ stack_offset
+ longword_offset
;
4507 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4508 paddress (gdbarch
, addr
));
4509 for (i
= 0; i
< partial_len
; i
++)
4511 fprintf_unfiltered (gdb_stdlog
, "%02x",
4515 write_memory (addr
, val
, partial_len
);
4518 /* Note!!! This is NOT an else clause. Odd sized
4519 structs may go thru BOTH paths. Floating point
4520 arguments will not. */
4521 /* Write this portion of the argument to a general
4522 purpose register. */
4523 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4524 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4527 extract_signed_integer (val
, partial_len
, byte_order
);
4530 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4532 phex (regval
, regsize
));
4533 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4540 /* Compute the offset into the stack at which we will
4541 copy the next parameter.
4543 In the new EABI (and the NABI32), the stack_offset
4544 only needs to be adjusted when it has been used. */
4547 stack_offset
+= align_up (partial_len
, regsize
);
4551 fprintf_unfiltered (gdb_stdlog
, "\n");
4554 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4556 /* Return adjusted stack pointer. */
4560 /* Determine the return value convention being used. */
4562 static enum return_value_convention
4563 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4564 struct type
*type
, struct regcache
*regcache
,
4565 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4567 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4568 int fp_return_type
= 0;
4569 int offset
, regnum
, xfer
;
4571 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4572 return RETURN_VALUE_STRUCT_CONVENTION
;
4574 /* Floating point type? */
4575 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4577 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4579 /* Structs with a single field of float type
4580 are returned in a floating point register. */
4581 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4582 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4583 && TYPE_NFIELDS (type
) == 1)
4585 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4587 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4594 /* A floating-point value belongs in the least significant part
4597 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4598 regnum
= mips_regnum (gdbarch
)->fp0
;
4602 /* An integer value goes in V0/V1. */
4604 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4605 regnum
= MIPS_V0_REGNUM
;
4608 offset
< TYPE_LENGTH (type
);
4609 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4611 xfer
= mips_abi_regsize (gdbarch
);
4612 if (offset
+ xfer
> TYPE_LENGTH (type
))
4613 xfer
= TYPE_LENGTH (type
) - offset
;
4614 mips_xfer_register (gdbarch
, regcache
,
4615 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4616 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4620 return RETURN_VALUE_REGISTER_CONVENTION
;
4624 /* N32/N64 ABI stuff. */
4626 /* Search for a naturally aligned double at OFFSET inside a struct
4627 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4631 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4636 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4639 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4642 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4645 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4648 struct type
*field_type
;
4650 /* We're only looking at normal fields. */
4651 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4652 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4655 /* If we have gone past the offset, there is no double to pass. */
4656 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4660 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4662 /* If this field is entirely before the requested offset, go
4663 on to the next one. */
4664 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4667 /* If this is our special aligned double, we can stop. */
4668 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4669 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4672 /* This field starts at or before the requested offset, and
4673 overlaps it. If it is a structure, recurse inwards. */
4674 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4681 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4682 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4683 int nargs
, struct value
**args
, CORE_ADDR sp
,
4684 int struct_return
, CORE_ADDR struct_addr
)
4690 int stack_offset
= 0;
4691 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4692 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4694 /* For shared libraries, "t9" needs to point at the function
4696 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4698 /* Set the return address register to point to the entry point of
4699 the program, where a breakpoint lies in wait. */
4700 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4702 /* First ensure that the stack and structure return address (if any)
4703 are properly aligned. The stack has to be at least 64-bit
4704 aligned even on 32-bit machines, because doubles must be 64-bit
4705 aligned. For n32 and n64, stack frames need to be 128-bit
4706 aligned, so we round to this widest known alignment. */
4708 sp
= align_down (sp
, 16);
4709 struct_addr
= align_down (struct_addr
, 16);
4711 /* Now make space on the stack for the args. */
4712 for (argnum
= 0; argnum
< nargs
; argnum
++)
4713 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4714 sp
-= align_up (len
, 16);
4717 fprintf_unfiltered (gdb_stdlog
,
4718 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4719 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4721 /* Initialize the integer and float register pointers. */
4722 argreg
= MIPS_A0_REGNUM
;
4723 float_argreg
= mips_fpa0_regnum (gdbarch
);
4725 /* The struct_return pointer occupies the first parameter-passing reg. */
4729 fprintf_unfiltered (gdb_stdlog
,
4730 "mips_n32n64_push_dummy_call: "
4731 "struct_return reg=%d %s\n",
4732 argreg
, paddress (gdbarch
, struct_addr
));
4733 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4736 /* Now load as many as possible of the first arguments into
4737 registers, and push the rest onto the stack. Loop thru args
4738 from first to last. */
4739 for (argnum
= 0; argnum
< nargs
; argnum
++)
4741 const gdb_byte
*val
;
4742 struct value
*arg
= args
[argnum
];
4743 struct type
*arg_type
= check_typedef (value_type (arg
));
4744 int len
= TYPE_LENGTH (arg_type
);
4745 enum type_code typecode
= TYPE_CODE (arg_type
);
4748 fprintf_unfiltered (gdb_stdlog
,
4749 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4750 argnum
+ 1, len
, (int) typecode
);
4752 val
= value_contents (arg
);
4754 /* A 128-bit long double value requires an even-odd pair of
4755 floating-point registers. */
4757 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4758 && (float_argreg
& 1))
4764 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4765 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4767 /* This is a floating point value that fits entirely
4768 in a single register or a pair of registers. */
4769 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4770 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4772 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4773 float_argreg
, phex (regval
, reglen
));
4774 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4777 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4778 argreg
, phex (regval
, reglen
));
4779 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4784 regval
= extract_unsigned_integer (val
+ reglen
,
4785 reglen
, byte_order
);
4787 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4788 float_argreg
, phex (regval
, reglen
));
4789 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4792 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4793 argreg
, phex (regval
, reglen
));
4794 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4801 /* Copy the argument to general registers or the stack in
4802 register-sized pieces. Large arguments are split between
4803 registers and stack. */
4804 /* For N32/N64, structs, unions, or other composite types are
4805 treated as a sequence of doublewords, and are passed in integer
4806 or floating point registers as though they were simple scalar
4807 parameters to the extent that they fit, with any excess on the
4808 stack packed according to the normal memory layout of the
4810 The caller does not reserve space for the register arguments;
4811 the callee is responsible for reserving it if required. */
4812 /* Note: Floating-point values that didn't fit into an FP
4813 register are only written to memory. */
4816 /* Remember if the argument was written to the stack. */
4817 int stack_used_p
= 0;
4818 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4821 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4824 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4825 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4827 /* Write this portion of the argument to the stack. */
4828 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4830 /* Should shorter than int integer values be
4831 promoted to int before being stored? */
4832 int longword_offset
= 0;
4835 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4837 if ((typecode
== TYPE_CODE_INT
4838 || typecode
== TYPE_CODE_PTR
)
4840 longword_offset
= MIPS64_REGSIZE
- len
;
4845 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4846 paddress (gdbarch
, stack_offset
));
4847 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4848 paddress (gdbarch
, longword_offset
));
4851 addr
= sp
+ stack_offset
+ longword_offset
;
4856 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4857 paddress (gdbarch
, addr
));
4858 for (i
= 0; i
< partial_len
; i
++)
4860 fprintf_unfiltered (gdb_stdlog
, "%02x",
4864 write_memory (addr
, val
, partial_len
);
4867 /* Note!!! This is NOT an else clause. Odd sized
4868 structs may go thru BOTH paths. */
4869 /* Write this portion of the argument to a general
4870 purpose register. */
4871 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4875 /* Sign extend pointers, 32-bit integers and signed
4876 16-bit and 8-bit integers; everything else is taken
4879 if ((partial_len
== 4
4880 && (typecode
== TYPE_CODE_PTR
4881 || typecode
== TYPE_CODE_INT
))
4883 && typecode
== TYPE_CODE_INT
4884 && !TYPE_UNSIGNED (arg_type
)))
4885 regval
= extract_signed_integer (val
, partial_len
,
4888 regval
= extract_unsigned_integer (val
, partial_len
,
4891 /* A non-floating-point argument being passed in a
4892 general register. If a struct or union, and if
4893 the remaining length is smaller than the register
4894 size, we have to adjust the register value on
4897 It does not seem to be necessary to do the
4898 same for integral types. */
4900 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4901 && partial_len
< MIPS64_REGSIZE
4902 && (typecode
== TYPE_CODE_STRUCT
4903 || typecode
== TYPE_CODE_UNION
))
4904 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4908 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4910 phex (regval
, MIPS64_REGSIZE
));
4911 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4913 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
4914 TYPE_LENGTH (arg_type
) - len
))
4917 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
4919 phex (regval
, MIPS64_REGSIZE
));
4920 regcache_cooked_write_unsigned (regcache
, float_argreg
,
4931 /* Compute the offset into the stack at which we will
4932 copy the next parameter.
4934 In N32 (N64?), the stack_offset only needs to be
4935 adjusted when it has been used. */
4938 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4942 fprintf_unfiltered (gdb_stdlog
, "\n");
4945 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4947 /* Return adjusted stack pointer. */
4951 static enum return_value_convention
4952 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4953 struct type
*type
, struct regcache
*regcache
,
4954 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4956 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4958 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4960 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4961 if needed), as appropriate for the type. Composite results (struct,
4962 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4965 * A struct with only one or two floating point fields is returned in $f0
4966 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4969 * Any other composite results of at most 128 bits are returned in
4970 $2 (first 64 bits) and $3 (remainder, if necessary).
4972 * Larger composite results are handled by converting the function to a
4973 procedure with an implicit first parameter, which is a pointer to an area
4974 reserved by the caller to receive the result. [The o32-bit ABI requires
4975 that all composite results be handled by conversion to implicit first
4976 parameters. The MIPS/SGI Fortran implementation has always made a
4977 specific exception to return COMPLEX results in the floating point
4980 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
4981 return RETURN_VALUE_STRUCT_CONVENTION
;
4982 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4983 && TYPE_LENGTH (type
) == 16
4984 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4986 /* A 128-bit floating-point value fills both $f0 and $f2. The
4987 two registers are used in the same as memory order, so the
4988 eight bytes with the lower memory address are in $f0. */
4990 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
4991 mips_xfer_register (gdbarch
, regcache
,
4992 (gdbarch_num_regs (gdbarch
)
4993 + mips_regnum (gdbarch
)->fp0
),
4994 8, gdbarch_byte_order (gdbarch
),
4995 readbuf
, writebuf
, 0);
4996 mips_xfer_register (gdbarch
, regcache
,
4997 (gdbarch_num_regs (gdbarch
)
4998 + mips_regnum (gdbarch
)->fp0
+ 2),
4999 8, gdbarch_byte_order (gdbarch
),
5000 readbuf
? readbuf
+ 8 : readbuf
,
5001 writebuf
? writebuf
+ 8 : writebuf
, 0);
5002 return RETURN_VALUE_REGISTER_CONVENTION
;
5004 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5005 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5007 /* A single or double floating-point value that fits in FP0. */
5009 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5010 mips_xfer_register (gdbarch
, regcache
,
5011 (gdbarch_num_regs (gdbarch
)
5012 + mips_regnum (gdbarch
)->fp0
),
5014 gdbarch_byte_order (gdbarch
),
5015 readbuf
, writebuf
, 0);
5016 return RETURN_VALUE_REGISTER_CONVENTION
;
5018 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5019 && TYPE_NFIELDS (type
) <= 2
5020 && TYPE_NFIELDS (type
) >= 1
5021 && ((TYPE_NFIELDS (type
) == 1
5022 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5024 || (TYPE_NFIELDS (type
) == 2
5025 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5027 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5028 == TYPE_CODE_FLT
))))
5030 /* A struct that contains one or two floats. Each value is part
5031 in the least significant part of their floating point
5032 register (or GPR, for soft float). */
5035 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5036 ? mips_regnum (gdbarch
)->fp0
5038 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5040 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5043 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5045 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5047 /* A 16-byte long double field goes in two consecutive
5049 mips_xfer_register (gdbarch
, regcache
,
5050 gdbarch_num_regs (gdbarch
) + regnum
,
5052 gdbarch_byte_order (gdbarch
),
5053 readbuf
, writebuf
, offset
);
5054 mips_xfer_register (gdbarch
, regcache
,
5055 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5057 gdbarch_byte_order (gdbarch
),
5058 readbuf
, writebuf
, offset
+ 8);
5061 mips_xfer_register (gdbarch
, regcache
,
5062 gdbarch_num_regs (gdbarch
) + regnum
,
5063 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5064 gdbarch_byte_order (gdbarch
),
5065 readbuf
, writebuf
, offset
);
5067 return RETURN_VALUE_REGISTER_CONVENTION
;
5069 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5070 || TYPE_CODE (type
) == TYPE_CODE_UNION
5071 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5073 /* A composite type. Extract the left justified value,
5074 regardless of the byte order. I.e. DO NOT USE
5078 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5079 offset
< TYPE_LENGTH (type
);
5080 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5082 int xfer
= register_size (gdbarch
, regnum
);
5083 if (offset
+ xfer
> TYPE_LENGTH (type
))
5084 xfer
= TYPE_LENGTH (type
) - offset
;
5086 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5087 offset
, xfer
, regnum
);
5088 mips_xfer_register (gdbarch
, regcache
,
5089 gdbarch_num_regs (gdbarch
) + regnum
,
5090 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5093 return RETURN_VALUE_REGISTER_CONVENTION
;
5097 /* A scalar extract each part but least-significant-byte
5101 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5102 offset
< TYPE_LENGTH (type
);
5103 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5105 int xfer
= register_size (gdbarch
, regnum
);
5106 if (offset
+ xfer
> TYPE_LENGTH (type
))
5107 xfer
= TYPE_LENGTH (type
) - offset
;
5109 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5110 offset
, xfer
, regnum
);
5111 mips_xfer_register (gdbarch
, regcache
,
5112 gdbarch_num_regs (gdbarch
) + regnum
,
5113 xfer
, gdbarch_byte_order (gdbarch
),
5114 readbuf
, writebuf
, offset
);
5116 return RETURN_VALUE_REGISTER_CONVENTION
;
5120 /* Which registers to use for passing floating-point values between
5121 function calls, one of floating-point, general and both kinds of
5122 registers. O32 and O64 use different register kinds for standard
5123 MIPS and MIPS16 code; to make the handling of cases where we may
5124 not know what kind of code is being used (e.g. no debug information)
5125 easier we sometimes use both kinds. */
5134 /* O32 ABI stuff. */
5137 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5138 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5139 int nargs
, struct value
**args
, CORE_ADDR sp
,
5140 int struct_return
, CORE_ADDR struct_addr
)
5146 int stack_offset
= 0;
5147 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5148 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5150 /* For shared libraries, "t9" needs to point at the function
5152 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5154 /* Set the return address register to point to the entry point of
5155 the program, where a breakpoint lies in wait. */
5156 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5158 /* First ensure that the stack and structure return address (if any)
5159 are properly aligned. The stack has to be at least 64-bit
5160 aligned even on 32-bit machines, because doubles must be 64-bit
5161 aligned. For n32 and n64, stack frames need to be 128-bit
5162 aligned, so we round to this widest known alignment. */
5164 sp
= align_down (sp
, 16);
5165 struct_addr
= align_down (struct_addr
, 16);
5167 /* Now make space on the stack for the args. */
5168 for (argnum
= 0; argnum
< nargs
; argnum
++)
5170 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5172 /* Align to double-word if necessary. */
5173 if (mips_type_needs_double_align (arg_type
))
5174 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5175 /* Allocate space on the stack. */
5176 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5178 sp
-= align_up (len
, 16);
5181 fprintf_unfiltered (gdb_stdlog
,
5182 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5183 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5185 /* Initialize the integer and float register pointers. */
5186 argreg
= MIPS_A0_REGNUM
;
5187 float_argreg
= mips_fpa0_regnum (gdbarch
);
5189 /* The struct_return pointer occupies the first parameter-passing reg. */
5193 fprintf_unfiltered (gdb_stdlog
,
5194 "mips_o32_push_dummy_call: "
5195 "struct_return reg=%d %s\n",
5196 argreg
, paddress (gdbarch
, struct_addr
));
5197 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5198 stack_offset
+= MIPS32_REGSIZE
;
5201 /* Now load as many as possible of the first arguments into
5202 registers, and push the rest onto the stack. Loop thru args
5203 from first to last. */
5204 for (argnum
= 0; argnum
< nargs
; argnum
++)
5206 const gdb_byte
*val
;
5207 struct value
*arg
= args
[argnum
];
5208 struct type
*arg_type
= check_typedef (value_type (arg
));
5209 int len
= TYPE_LENGTH (arg_type
);
5210 enum type_code typecode
= TYPE_CODE (arg_type
);
5213 fprintf_unfiltered (gdb_stdlog
,
5214 "mips_o32_push_dummy_call: %d len=%d type=%d",
5215 argnum
+ 1, len
, (int) typecode
);
5217 val
= value_contents (arg
);
5219 /* 32-bit ABIs always start floating point arguments in an
5220 even-numbered floating point register. Round the FP register
5221 up before the check to see if there are any FP registers
5222 left. O32 targets also pass the FP in the integer registers
5223 so also round up normal registers. */
5224 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5226 if ((float_argreg
& 1))
5230 /* Floating point arguments passed in registers have to be
5231 treated specially. On 32-bit architectures, doubles are
5232 passed in register pairs; the even FP register gets the
5233 low word, and the odd FP register gets the high word.
5234 On O32, the first two floating point arguments are also
5235 copied to general registers, following their memory order,
5236 because MIPS16 functions don't use float registers for
5237 arguments. This duplication of arguments in general
5238 registers can't hurt non-MIPS16 functions, because those
5239 registers are normally skipped. */
5241 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5242 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5244 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5246 int freg_offset
= gdbarch_byte_order (gdbarch
)
5247 == BFD_ENDIAN_BIG
? 1 : 0;
5248 unsigned long regval
;
5251 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5253 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5254 float_argreg
+ freg_offset
,
5256 regcache_cooked_write_unsigned (regcache
,
5257 float_argreg
++ + freg_offset
,
5260 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5261 argreg
, phex (regval
, 4));
5262 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5265 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5267 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5268 float_argreg
- freg_offset
,
5270 regcache_cooked_write_unsigned (regcache
,
5271 float_argreg
++ - freg_offset
,
5274 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5275 argreg
, phex (regval
, 4));
5276 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5280 /* This is a floating point value that fits entirely
5281 in a single register. */
5282 /* On 32 bit ABI's the float_argreg is further adjusted
5283 above to ensure that it is even register aligned. */
5284 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5286 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5287 float_argreg
, phex (regval
, len
));
5288 regcache_cooked_write_unsigned (regcache
,
5289 float_argreg
++, regval
);
5290 /* Although two FP registers are reserved for each
5291 argument, only one corresponding integer register is
5294 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5295 argreg
, phex (regval
, len
));
5296 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5298 /* Reserve space for the FP register. */
5299 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5303 /* Copy the argument to general registers or the stack in
5304 register-sized pieces. Large arguments are split between
5305 registers and stack. */
5306 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5307 are treated specially: Irix cc passes
5308 them in registers where gcc sometimes puts them on the
5309 stack. For maximum compatibility, we will put them in
5311 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5312 && len
% MIPS32_REGSIZE
!= 0);
5313 /* Structures should be aligned to eight bytes (even arg registers)
5314 on MIPS_ABI_O32, if their first member has double precision. */
5315 if (mips_type_needs_double_align (arg_type
))
5320 stack_offset
+= MIPS32_REGSIZE
;
5325 /* Remember if the argument was written to the stack. */
5326 int stack_used_p
= 0;
5327 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5330 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5333 /* Write this portion of the argument to the stack. */
5334 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5335 || odd_sized_struct
)
5337 /* Should shorter than int integer values be
5338 promoted to int before being stored? */
5339 int longword_offset
= 0;
5345 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5346 paddress (gdbarch
, stack_offset
));
5347 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5348 paddress (gdbarch
, longword_offset
));
5351 addr
= sp
+ stack_offset
+ longword_offset
;
5356 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5357 paddress (gdbarch
, addr
));
5358 for (i
= 0; i
< partial_len
; i
++)
5360 fprintf_unfiltered (gdb_stdlog
, "%02x",
5364 write_memory (addr
, val
, partial_len
);
5367 /* Note!!! This is NOT an else clause. Odd sized
5368 structs may go thru BOTH paths. */
5369 /* Write this portion of the argument to a general
5370 purpose register. */
5371 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5373 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5375 /* Value may need to be sign extended, because
5376 mips_isa_regsize() != mips_abi_regsize(). */
5378 /* A non-floating-point argument being passed in a
5379 general register. If a struct or union, and if
5380 the remaining length is smaller than the register
5381 size, we have to adjust the register value on
5384 It does not seem to be necessary to do the
5385 same for integral types.
5387 Also don't do this adjustment on O64 binaries.
5389 cagney/2001-07-23: gdb/179: Also, GCC, when
5390 outputting LE O32 with sizeof (struct) <
5391 mips_abi_regsize(), generates a left shift
5392 as part of storing the argument in a register
5393 (the left shift isn't generated when
5394 sizeof (struct) >= mips_abi_regsize()). Since
5395 it is quite possible that this is GCC
5396 contradicting the LE/O32 ABI, GDB has not been
5397 adjusted to accommodate this. Either someone
5398 needs to demonstrate that the LE/O32 ABI
5399 specifies such a left shift OR this new ABI gets
5400 identified as such and GDB gets tweaked
5403 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5404 && partial_len
< MIPS32_REGSIZE
5405 && (typecode
== TYPE_CODE_STRUCT
5406 || typecode
== TYPE_CODE_UNION
))
5407 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5411 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5413 phex (regval
, MIPS32_REGSIZE
));
5414 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5417 /* Prevent subsequent floating point arguments from
5418 being passed in floating point registers. */
5419 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5425 /* Compute the offset into the stack at which we will
5426 copy the next parameter.
5428 In older ABIs, the caller reserved space for
5429 registers that contained arguments. This was loosely
5430 refered to as their "home". Consequently, space is
5431 always allocated. */
5433 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5437 fprintf_unfiltered (gdb_stdlog
, "\n");
5440 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5442 /* Return adjusted stack pointer. */
5446 static enum return_value_convention
5447 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5448 struct type
*type
, struct regcache
*regcache
,
5449 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5451 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5452 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5454 enum mips_fval_reg fval_reg
;
5456 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5457 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5458 || TYPE_CODE (type
) == TYPE_CODE_UNION
5459 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5460 return RETURN_VALUE_STRUCT_CONVENTION
;
5461 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5462 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5464 /* A single-precision floating-point value. If reading in or copying,
5465 then we get it from/put it to FP0 for standard MIPS code or GPR2
5466 for MIPS16 code. If writing out only, then we put it to both FP0
5467 and GPR2. We do not support reading in with no function known, if
5468 this safety check ever triggers, then we'll have to try harder. */
5469 gdb_assert (function
|| !readbuf
);
5474 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5477 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5479 case mips_fval_both
:
5480 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5483 if (fval_reg
!= mips_fval_gpr
)
5484 mips_xfer_register (gdbarch
, regcache
,
5485 (gdbarch_num_regs (gdbarch
)
5486 + mips_regnum (gdbarch
)->fp0
),
5488 gdbarch_byte_order (gdbarch
),
5489 readbuf
, writebuf
, 0);
5490 if (fval_reg
!= mips_fval_fpr
)
5491 mips_xfer_register (gdbarch
, regcache
,
5492 gdbarch_num_regs (gdbarch
) + 2,
5494 gdbarch_byte_order (gdbarch
),
5495 readbuf
, writebuf
, 0);
5496 return RETURN_VALUE_REGISTER_CONVENTION
;
5498 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5499 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5501 /* A double-precision floating-point value. If reading in or copying,
5502 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5503 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5504 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5505 no function known, if this safety check ever triggers, then we'll
5506 have to try harder. */
5507 gdb_assert (function
|| !readbuf
);
5512 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5515 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5517 case mips_fval_both
:
5518 fprintf_unfiltered (gdb_stderr
,
5519 "Return float in $fp1/$fp0 and $2/$3\n");
5522 if (fval_reg
!= mips_fval_gpr
)
5524 /* The most significant part goes in FP1, and the least significant
5526 switch (gdbarch_byte_order (gdbarch
))
5528 case BFD_ENDIAN_LITTLE
:
5529 mips_xfer_register (gdbarch
, regcache
,
5530 (gdbarch_num_regs (gdbarch
)
5531 + mips_regnum (gdbarch
)->fp0
+ 0),
5532 4, gdbarch_byte_order (gdbarch
),
5533 readbuf
, writebuf
, 0);
5534 mips_xfer_register (gdbarch
, regcache
,
5535 (gdbarch_num_regs (gdbarch
)
5536 + mips_regnum (gdbarch
)->fp0
+ 1),
5537 4, gdbarch_byte_order (gdbarch
),
5538 readbuf
, writebuf
, 4);
5540 case BFD_ENDIAN_BIG
:
5541 mips_xfer_register (gdbarch
, regcache
,
5542 (gdbarch_num_regs (gdbarch
)
5543 + mips_regnum (gdbarch
)->fp0
+ 1),
5544 4, gdbarch_byte_order (gdbarch
),
5545 readbuf
, writebuf
, 0);
5546 mips_xfer_register (gdbarch
, regcache
,
5547 (gdbarch_num_regs (gdbarch
)
5548 + mips_regnum (gdbarch
)->fp0
+ 0),
5549 4, gdbarch_byte_order (gdbarch
),
5550 readbuf
, writebuf
, 4);
5553 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5556 if (fval_reg
!= mips_fval_fpr
)
5558 /* The two 32-bit parts are always placed in GPR2 and GPR3
5559 following these registers' memory order. */
5560 mips_xfer_register (gdbarch
, regcache
,
5561 gdbarch_num_regs (gdbarch
) + 2,
5562 4, gdbarch_byte_order (gdbarch
),
5563 readbuf
, writebuf
, 0);
5564 mips_xfer_register (gdbarch
, regcache
,
5565 gdbarch_num_regs (gdbarch
) + 3,
5566 4, gdbarch_byte_order (gdbarch
),
5567 readbuf
, writebuf
, 4);
5569 return RETURN_VALUE_REGISTER_CONVENTION
;
5572 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5573 && TYPE_NFIELDS (type
) <= 2
5574 && TYPE_NFIELDS (type
) >= 1
5575 && ((TYPE_NFIELDS (type
) == 1
5576 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5578 || (TYPE_NFIELDS (type
) == 2
5579 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5581 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5583 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5585 /* A struct that contains one or two floats. Each value is part
5586 in the least significant part of their floating point
5588 gdb_byte reg
[MAX_REGISTER_SIZE
];
5591 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5592 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5594 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5597 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5599 mips_xfer_register (gdbarch
, regcache
,
5600 gdbarch_num_regs (gdbarch
) + regnum
,
5601 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5602 gdbarch_byte_order (gdbarch
),
5603 readbuf
, writebuf
, offset
);
5605 return RETURN_VALUE_REGISTER_CONVENTION
;
5609 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5610 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5612 /* A structure or union. Extract the left justified value,
5613 regardless of the byte order. I.e. DO NOT USE
5617 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5618 offset
< TYPE_LENGTH (type
);
5619 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5621 int xfer
= register_size (gdbarch
, regnum
);
5622 if (offset
+ xfer
> TYPE_LENGTH (type
))
5623 xfer
= TYPE_LENGTH (type
) - offset
;
5625 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5626 offset
, xfer
, regnum
);
5627 mips_xfer_register (gdbarch
, regcache
,
5628 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5629 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5631 return RETURN_VALUE_REGISTER_CONVENTION
;
5636 /* A scalar extract each part but least-significant-byte
5637 justified. o32 thinks registers are 4 byte, regardless of
5641 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5642 offset
< TYPE_LENGTH (type
);
5643 offset
+= MIPS32_REGSIZE
, regnum
++)
5645 int xfer
= MIPS32_REGSIZE
;
5646 if (offset
+ xfer
> TYPE_LENGTH (type
))
5647 xfer
= TYPE_LENGTH (type
) - offset
;
5649 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5650 offset
, xfer
, regnum
);
5651 mips_xfer_register (gdbarch
, regcache
,
5652 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5653 gdbarch_byte_order (gdbarch
),
5654 readbuf
, writebuf
, offset
);
5656 return RETURN_VALUE_REGISTER_CONVENTION
;
5660 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5664 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5665 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5667 struct value
**args
, CORE_ADDR sp
,
5668 int struct_return
, CORE_ADDR struct_addr
)
5674 int stack_offset
= 0;
5675 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5676 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5678 /* For shared libraries, "t9" needs to point at the function
5680 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5682 /* Set the return address register to point to the entry point of
5683 the program, where a breakpoint lies in wait. */
5684 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5686 /* First ensure that the stack and structure return address (if any)
5687 are properly aligned. The stack has to be at least 64-bit
5688 aligned even on 32-bit machines, because doubles must be 64-bit
5689 aligned. For n32 and n64, stack frames need to be 128-bit
5690 aligned, so we round to this widest known alignment. */
5692 sp
= align_down (sp
, 16);
5693 struct_addr
= align_down (struct_addr
, 16);
5695 /* Now make space on the stack for the args. */
5696 for (argnum
= 0; argnum
< nargs
; argnum
++)
5698 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5700 /* Allocate space on the stack. */
5701 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5703 sp
-= align_up (len
, 16);
5706 fprintf_unfiltered (gdb_stdlog
,
5707 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5708 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5710 /* Initialize the integer and float register pointers. */
5711 argreg
= MIPS_A0_REGNUM
;
5712 float_argreg
= mips_fpa0_regnum (gdbarch
);
5714 /* The struct_return pointer occupies the first parameter-passing reg. */
5718 fprintf_unfiltered (gdb_stdlog
,
5719 "mips_o64_push_dummy_call: "
5720 "struct_return reg=%d %s\n",
5721 argreg
, paddress (gdbarch
, struct_addr
));
5722 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5723 stack_offset
+= MIPS64_REGSIZE
;
5726 /* Now load as many as possible of the first arguments into
5727 registers, and push the rest onto the stack. Loop thru args
5728 from first to last. */
5729 for (argnum
= 0; argnum
< nargs
; argnum
++)
5731 const gdb_byte
*val
;
5732 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5733 struct value
*arg
= args
[argnum
];
5734 struct type
*arg_type
= check_typedef (value_type (arg
));
5735 int len
= TYPE_LENGTH (arg_type
);
5736 enum type_code typecode
= TYPE_CODE (arg_type
);
5739 fprintf_unfiltered (gdb_stdlog
,
5740 "mips_o64_push_dummy_call: %d len=%d type=%d",
5741 argnum
+ 1, len
, (int) typecode
);
5743 val
= value_contents (arg
);
5745 /* Function pointer arguments to mips16 code need to be made into
5747 if (typecode
== TYPE_CODE_PTR
5748 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5750 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5752 if (!mips_pc_is_mips (addr
))
5754 store_signed_integer (valbuf
, len
, byte_order
,
5755 make_compact_addr (addr
));
5760 /* Floating point arguments passed in registers have to be
5761 treated specially. On 32-bit architectures, doubles are
5762 passed in register pairs; the even FP register gets the
5763 low word, and the odd FP register gets the high word.
5764 On O64, the first two floating point arguments are also
5765 copied to general registers, because MIPS16 functions
5766 don't use float registers for arguments. This duplication
5767 of arguments in general registers can't hurt non-MIPS16
5768 functions because those registers are normally skipped. */
5770 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5771 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5773 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5775 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5776 float_argreg
, phex (regval
, len
));
5777 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5779 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5780 argreg
, phex (regval
, len
));
5781 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5783 /* Reserve space for the FP register. */
5784 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5788 /* Copy the argument to general registers or the stack in
5789 register-sized pieces. Large arguments are split between
5790 registers and stack. */
5791 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5792 are treated specially: Irix cc passes them in registers
5793 where gcc sometimes puts them on the stack. For maximum
5794 compatibility, we will put them in both places. */
5795 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5796 && len
% MIPS64_REGSIZE
!= 0);
5799 /* Remember if the argument was written to the stack. */
5800 int stack_used_p
= 0;
5801 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5804 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5807 /* Write this portion of the argument to the stack. */
5808 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5809 || odd_sized_struct
)
5811 /* Should shorter than int integer values be
5812 promoted to int before being stored? */
5813 int longword_offset
= 0;
5816 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5818 if ((typecode
== TYPE_CODE_INT
5819 || typecode
== TYPE_CODE_PTR
5820 || typecode
== TYPE_CODE_FLT
)
5822 longword_offset
= MIPS64_REGSIZE
- len
;
5827 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5828 paddress (gdbarch
, stack_offset
));
5829 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5830 paddress (gdbarch
, longword_offset
));
5833 addr
= sp
+ stack_offset
+ longword_offset
;
5838 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5839 paddress (gdbarch
, addr
));
5840 for (i
= 0; i
< partial_len
; i
++)
5842 fprintf_unfiltered (gdb_stdlog
, "%02x",
5846 write_memory (addr
, val
, partial_len
);
5849 /* Note!!! This is NOT an else clause. Odd sized
5850 structs may go thru BOTH paths. */
5851 /* Write this portion of the argument to a general
5852 purpose register. */
5853 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5855 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5857 /* Value may need to be sign extended, because
5858 mips_isa_regsize() != mips_abi_regsize(). */
5860 /* A non-floating-point argument being passed in a
5861 general register. If a struct or union, and if
5862 the remaining length is smaller than the register
5863 size, we have to adjust the register value on
5866 It does not seem to be necessary to do the
5867 same for integral types. */
5869 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5870 && partial_len
< MIPS64_REGSIZE
5871 && (typecode
== TYPE_CODE_STRUCT
5872 || typecode
== TYPE_CODE_UNION
))
5873 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5877 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5879 phex (regval
, MIPS64_REGSIZE
));
5880 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5883 /* Prevent subsequent floating point arguments from
5884 being passed in floating point registers. */
5885 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5891 /* Compute the offset into the stack at which we will
5892 copy the next parameter.
5894 In older ABIs, the caller reserved space for
5895 registers that contained arguments. This was loosely
5896 refered to as their "home". Consequently, space is
5897 always allocated. */
5899 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5903 fprintf_unfiltered (gdb_stdlog
, "\n");
5906 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5908 /* Return adjusted stack pointer. */
5912 static enum return_value_convention
5913 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5914 struct type
*type
, struct regcache
*regcache
,
5915 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5917 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5918 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5919 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5920 enum mips_fval_reg fval_reg
;
5922 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5923 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5924 || TYPE_CODE (type
) == TYPE_CODE_UNION
5925 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5926 return RETURN_VALUE_STRUCT_CONVENTION
;
5927 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
5929 /* A floating-point value. If reading in or copying, then we get it
5930 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5931 If writing out only, then we put it to both FP0 and GPR2. We do
5932 not support reading in with no function known, if this safety
5933 check ever triggers, then we'll have to try harder. */
5934 gdb_assert (function
|| !readbuf
);
5939 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5942 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5944 case mips_fval_both
:
5945 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5948 if (fval_reg
!= mips_fval_gpr
)
5949 mips_xfer_register (gdbarch
, regcache
,
5950 (gdbarch_num_regs (gdbarch
)
5951 + mips_regnum (gdbarch
)->fp0
),
5953 gdbarch_byte_order (gdbarch
),
5954 readbuf
, writebuf
, 0);
5955 if (fval_reg
!= mips_fval_fpr
)
5956 mips_xfer_register (gdbarch
, regcache
,
5957 gdbarch_num_regs (gdbarch
) + 2,
5959 gdbarch_byte_order (gdbarch
),
5960 readbuf
, writebuf
, 0);
5961 return RETURN_VALUE_REGISTER_CONVENTION
;
5965 /* A scalar extract each part but least-significant-byte
5969 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5970 offset
< TYPE_LENGTH (type
);
5971 offset
+= MIPS64_REGSIZE
, regnum
++)
5973 int xfer
= MIPS64_REGSIZE
;
5974 if (offset
+ xfer
> TYPE_LENGTH (type
))
5975 xfer
= TYPE_LENGTH (type
) - offset
;
5977 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5978 offset
, xfer
, regnum
);
5979 mips_xfer_register (gdbarch
, regcache
,
5980 gdbarch_num_regs (gdbarch
) + regnum
,
5981 xfer
, gdbarch_byte_order (gdbarch
),
5982 readbuf
, writebuf
, offset
);
5984 return RETURN_VALUE_REGISTER_CONVENTION
;
5988 /* Floating point register management.
5990 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5991 64bit operations, these early MIPS cpus treat fp register pairs
5992 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5993 registers and offer a compatibility mode that emulates the MIPS2 fp
5994 model. When operating in MIPS2 fp compat mode, later cpu's split
5995 double precision floats into two 32-bit chunks and store them in
5996 consecutive fp regs. To display 64-bit floats stored in this
5997 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
5998 Throw in user-configurable endianness and you have a real mess.
6000 The way this works is:
6001 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6002 double-precision value will be split across two logical registers.
6003 The lower-numbered logical register will hold the low-order bits,
6004 regardless of the processor's endianness.
6005 - If we are on a 64-bit processor, and we are looking for a
6006 single-precision value, it will be in the low ordered bits
6007 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6008 save slot in memory.
6009 - If we are in 64-bit mode, everything is straightforward.
6011 Note that this code only deals with "live" registers at the top of the
6012 stack. We will attempt to deal with saved registers later, when
6013 the raw/cooked register interface is in place. (We need a general
6014 interface that can deal with dynamic saved register sizes -- fp
6015 regs could be 32 bits wide in one frame and 64 on the frame above
6018 /* Copy a 32-bit single-precision value from the current frame
6019 into rare_buffer. */
6022 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6023 gdb_byte
*rare_buffer
)
6025 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6026 int raw_size
= register_size (gdbarch
, regno
);
6027 gdb_byte
*raw_buffer
= alloca (raw_size
);
6029 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6030 error (_("can't read register %d (%s)"),
6031 regno
, gdbarch_register_name (gdbarch
, regno
));
6034 /* We have a 64-bit value for this register. Find the low-order
6038 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6043 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6047 memcpy (rare_buffer
, raw_buffer
, 4);
6051 /* Copy a 64-bit double-precision value from the current frame into
6052 rare_buffer. This may include getting half of it from the next
6056 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6057 gdb_byte
*rare_buffer
)
6059 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6060 int raw_size
= register_size (gdbarch
, regno
);
6062 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6064 /* We have a 64-bit value for this register, and we should use
6066 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6067 error (_("can't read register %d (%s)"),
6068 regno
, gdbarch_register_name (gdbarch
, regno
));
6072 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6074 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6075 internal_error (__FILE__
, __LINE__
,
6076 _("mips_read_fp_register_double: bad access to "
6077 "odd-numbered FP register"));
6079 /* mips_read_fp_register_single will find the correct 32 bits from
6081 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6083 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6084 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6088 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6089 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6095 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6097 { /* Do values for FP (float) regs. */
6098 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6099 gdb_byte
*raw_buffer
;
6100 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6103 raw_buffer
= alloca (2 * register_size (gdbarch
,
6104 mips_regnum (gdbarch
)->fp0
));
6106 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6107 fprintf_filtered (file
, "%*s",
6108 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6111 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6113 struct value_print_options opts
;
6115 /* 4-byte registers: Print hex and floating. Also print even
6116 numbered registers as doubles. */
6117 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6118 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6121 get_formatted_print_options (&opts
, 'x');
6122 print_scalar_formatted (raw_buffer
,
6123 builtin_type (gdbarch
)->builtin_uint32
,
6126 fprintf_filtered (file
, " flt: ");
6128 fprintf_filtered (file
, " <invalid float> ");
6130 fprintf_filtered (file
, "%-17.9g", flt1
);
6132 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6134 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6135 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6138 fprintf_filtered (file
, " dbl: ");
6140 fprintf_filtered (file
, "<invalid double>");
6142 fprintf_filtered (file
, "%-24.17g", doub
);
6147 struct value_print_options opts
;
6149 /* Eight byte registers: print each one as hex, float and double. */
6150 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6151 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6154 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6155 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6158 get_formatted_print_options (&opts
, 'x');
6159 print_scalar_formatted (raw_buffer
,
6160 builtin_type (gdbarch
)->builtin_uint64
,
6163 fprintf_filtered (file
, " flt: ");
6165 fprintf_filtered (file
, "<invalid float>");
6167 fprintf_filtered (file
, "%-17.9g", flt1
);
6169 fprintf_filtered (file
, " dbl: ");
6171 fprintf_filtered (file
, "<invalid double>");
6173 fprintf_filtered (file
, "%-24.17g", doub
);
6178 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6181 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6182 struct value_print_options opts
;
6185 if (mips_float_register_p (gdbarch
, regnum
))
6187 mips_print_fp_register (file
, frame
, regnum
);
6191 val
= get_frame_register_value (frame
, regnum
);
6192 if (value_optimized_out (val
))
6194 fprintf_filtered (file
, "%s: [Invalid]",
6195 gdbarch_register_name (gdbarch
, regnum
));
6199 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6201 /* The problem with printing numeric register names (r26, etc.) is that
6202 the user can't use them on input. Probably the best solution is to
6203 fix it so that either the numeric or the funky (a2, etc.) names
6204 are accepted on input. */
6205 if (regnum
< MIPS_NUMREGS
)
6206 fprintf_filtered (file
, "(r%d): ", regnum
);
6208 fprintf_filtered (file
, ": ");
6210 get_formatted_print_options (&opts
, 'x');
6211 val_print_scalar_formatted (value_type (val
),
6212 value_contents_for_printing (val
),
6213 value_embedded_offset (val
),
6218 /* Replacement for generic do_registers_info.
6219 Print regs in pretty columns. */
6222 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6225 fprintf_filtered (file
, " ");
6226 mips_print_fp_register (file
, frame
, regnum
);
6227 fprintf_filtered (file
, "\n");
6232 /* Print a row's worth of GP (int) registers, with name labels above. */
6235 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6238 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6239 /* Do values for GP (int) regs. */
6240 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6241 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6246 /* For GP registers, we print a separate row of names above the vals. */
6247 for (col
= 0, regnum
= start_regnum
;
6248 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6249 + gdbarch_num_pseudo_regs (gdbarch
);
6252 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6253 continue; /* unused register */
6254 if (mips_float_register_p (gdbarch
, regnum
))
6255 break; /* End the row: reached FP register. */
6256 /* Large registers are handled separately. */
6257 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6260 break; /* End the row before this register. */
6262 /* Print this register on a row by itself. */
6263 mips_print_register (file
, frame
, regnum
);
6264 fprintf_filtered (file
, "\n");
6268 fprintf_filtered (file
, " ");
6269 fprintf_filtered (file
,
6270 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6271 gdbarch_register_name (gdbarch
, regnum
));
6278 /* Print the R0 to R31 names. */
6279 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6280 fprintf_filtered (file
, "\n R%-4d",
6281 start_regnum
% gdbarch_num_regs (gdbarch
));
6283 fprintf_filtered (file
, "\n ");
6285 /* Now print the values in hex, 4 or 8 to the row. */
6286 for (col
= 0, regnum
= start_regnum
;
6287 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6288 + gdbarch_num_pseudo_regs (gdbarch
);
6291 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6292 continue; /* unused register */
6293 if (mips_float_register_p (gdbarch
, regnum
))
6294 break; /* End row: reached FP register. */
6295 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6296 break; /* End row: large register. */
6298 /* OK: get the data in raw format. */
6299 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6300 error (_("can't read register %d (%s)"),
6301 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6302 /* pad small registers */
6304 byte
< (mips_abi_regsize (gdbarch
)
6305 - register_size (gdbarch
, regnum
)); byte
++)
6306 printf_filtered (" ");
6307 /* Now print the register value in hex, endian order. */
6308 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6310 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6311 byte
< register_size (gdbarch
, regnum
); byte
++)
6312 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6314 for (byte
= register_size (gdbarch
, regnum
) - 1;
6316 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6317 fprintf_filtered (file
, " ");
6320 if (col
> 0) /* ie. if we actually printed anything... */
6321 fprintf_filtered (file
, "\n");
6326 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6329 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6330 struct frame_info
*frame
, int regnum
, int all
)
6332 if (regnum
!= -1) /* Do one specified register. */
6334 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6335 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6336 error (_("Not a valid register for the current processor type"));
6338 mips_print_register (file
, frame
, regnum
);
6339 fprintf_filtered (file
, "\n");
6342 /* Do all (or most) registers. */
6344 regnum
= gdbarch_num_regs (gdbarch
);
6345 while (regnum
< gdbarch_num_regs (gdbarch
)
6346 + gdbarch_num_pseudo_regs (gdbarch
))
6348 if (mips_float_register_p (gdbarch
, regnum
))
6350 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6351 regnum
= print_fp_register_row (file
, frame
, regnum
);
6353 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6356 regnum
= print_gp_register_row (file
, frame
, regnum
);
6362 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6363 struct frame_info
*frame
)
6365 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6366 CORE_ADDR pc
= get_frame_pc (frame
);
6367 struct address_space
*aspace
;
6373 if ((mips_pc_is_mips (pc
)
6374 && !mips32_instruction_has_delay_slot (gdbarch
, pc
))
6375 || (mips_pc_is_micromips (gdbarch
, pc
)
6376 && !micromips_instruction_has_delay_slot (gdbarch
, pc
, 0))
6377 || (mips_pc_is_mips16 (gdbarch
, pc
)
6378 && !mips16_instruction_has_delay_slot (gdbarch
, pc
, 0)))
6381 isa
= mips_pc_isa (gdbarch
, pc
);
6382 /* _has_delay_slot above will have validated the read. */
6383 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6384 size
= mips_insn_size (isa
, insn
);
6385 aspace
= get_frame_address_space (frame
);
6386 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6389 /* To skip prologues, I use this predicate. Returns either PC itself
6390 if the code at PC does not look like a function prologue; otherwise
6391 returns an address that (if we're lucky) follows the prologue. If
6392 LENIENT, then we must skip everything which is involved in setting
6393 up the frame (it's OK to skip more, just so long as we don't skip
6394 anything which might clobber the registers which are being saved.
6395 We must skip more in the case where part of the prologue is in the
6396 delay slot of a non-prologue instruction). */
6399 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6402 CORE_ADDR func_addr
;
6404 /* See if we can determine the end of the prologue via the symbol table.
6405 If so, then return either PC, or the PC after the prologue, whichever
6407 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6409 CORE_ADDR post_prologue_pc
6410 = skip_prologue_using_sal (gdbarch
, func_addr
);
6411 if (post_prologue_pc
!= 0)
6412 return max (pc
, post_prologue_pc
);
6415 /* Can't determine prologue from the symbol table, need to examine
6418 /* Find an upper limit on the function prologue using the debug
6419 information. If the debug information could not be used to provide
6420 that bound, then use an arbitrary large number as the upper bound. */
6421 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6423 limit_pc
= pc
+ 100; /* Magic. */
6425 if (mips_pc_is_mips16 (gdbarch
, pc
))
6426 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6427 else if (mips_pc_is_micromips (gdbarch
, pc
))
6428 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6430 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6433 /* Check whether the PC is in a function epilogue (32-bit version).
6434 This is a helper function for mips_in_function_epilogue_p. */
6436 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6438 CORE_ADDR func_addr
= 0, func_end
= 0;
6440 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6442 /* The MIPS epilogue is max. 12 bytes long. */
6443 CORE_ADDR addr
= func_end
- 12;
6445 if (addr
< func_addr
+ 4)
6446 addr
= func_addr
+ 4;
6450 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6452 unsigned long high_word
;
6455 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6456 high_word
= (inst
>> 16) & 0xffff;
6458 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6459 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6460 && inst
!= 0x03e00008 /* jr $ra */
6461 && inst
!= 0x00000000) /* nop */
6471 /* Check whether the PC is in a function epilogue (microMIPS version).
6472 This is a helper function for mips_in_function_epilogue_p. */
6475 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6477 CORE_ADDR func_addr
= 0;
6478 CORE_ADDR func_end
= 0;
6486 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6489 /* The microMIPS epilogue is max. 12 bytes long. */
6490 addr
= func_end
- 12;
6492 if (addr
< func_addr
+ 2)
6493 addr
= func_addr
+ 2;
6497 for (; pc
< func_end
; pc
+= loc
)
6500 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6501 loc
+= MIPS_INSN16_SIZE
;
6502 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6504 /* 48-bit instructions. */
6505 case 3 * MIPS_INSN16_SIZE
:
6506 /* No epilogue instructions in this category. */
6509 /* 32-bit instructions. */
6510 case 2 * MIPS_INSN16_SIZE
:
6512 insn
|= mips_fetch_instruction (gdbarch
,
6513 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6514 loc
+= MIPS_INSN16_SIZE
;
6515 switch (micromips_op (insn
>> 16))
6517 case 0xc: /* ADDIU: bits 001100 */
6518 case 0x17: /* DADDIU: bits 010111 */
6519 sreg
= b0s5_reg (insn
>> 16);
6520 dreg
= b5s5_reg (insn
>> 16);
6521 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6522 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6523 /* (D)ADDIU $sp, imm */
6533 /* 16-bit instructions. */
6534 case MIPS_INSN16_SIZE
:
6535 switch (micromips_op (insn
))
6537 case 0x3: /* MOVE: bits 000011 */
6538 sreg
= b0s5_reg (insn
);
6539 dreg
= b5s5_reg (insn
);
6540 if (sreg
== 0 && dreg
== 0)
6541 /* MOVE $zero, $zero aka NOP */
6545 case 0x11: /* POOL16C: bits 010001 */
6546 if (b5s5_op (insn
) == 0x18
6547 /* JRADDIUSP: bits 010011 11000 */
6548 || (b5s5_op (insn
) == 0xd
6549 /* JRC: bits 010011 01101 */
6550 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6555 case 0x13: /* POOL16D: bits 010011 */
6556 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6557 if ((insn
& 0x1) == 0x1
6558 /* ADDIUSP: bits 010011 1 */
6572 /* Check whether the PC is in a function epilogue (16-bit version).
6573 This is a helper function for mips_in_function_epilogue_p. */
6575 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6577 CORE_ADDR func_addr
= 0, func_end
= 0;
6579 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6581 /* The MIPS epilogue is max. 12 bytes long. */
6582 CORE_ADDR addr
= func_end
- 12;
6584 if (addr
< func_addr
+ 4)
6585 addr
= func_addr
+ 4;
6589 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6591 unsigned short inst
;
6593 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6595 if ((inst
& 0xf800) == 0xf000) /* extend */
6598 if (inst
!= 0x6300 /* addiu $sp,offset */
6599 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6600 && inst
!= 0xe820 /* jr $ra */
6601 && inst
!= 0xe8a0 /* jrc $ra */
6602 && inst
!= 0x6500) /* nop */
6612 /* The epilogue is defined here as the area at the end of a function,
6613 after an instruction which destroys the function's stack frame. */
6615 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6617 if (mips_pc_is_mips16 (gdbarch
, pc
))
6618 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6619 else if (mips_pc_is_micromips (gdbarch
, pc
))
6620 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6622 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6625 /* Root of all "set mips "/"show mips " commands. This will eventually be
6626 used for all MIPS-specific commands. */
6629 show_mips_command (char *args
, int from_tty
)
6631 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6635 set_mips_command (char *args
, int from_tty
)
6638 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6639 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6642 /* Commands to show/set the MIPS FPU type. */
6645 show_mipsfpu_command (char *args
, int from_tty
)
6649 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6652 ("The MIPS floating-point coprocessor is unknown "
6653 "because the current architecture is not MIPS.\n");
6657 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6659 case MIPS_FPU_SINGLE
:
6660 fpu
= "single-precision";
6662 case MIPS_FPU_DOUBLE
:
6663 fpu
= "double-precision";
6666 fpu
= "absent (none)";
6669 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6671 if (mips_fpu_type_auto
)
6672 printf_unfiltered ("The MIPS floating-point coprocessor "
6673 "is set automatically (currently %s)\n",
6677 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6682 set_mipsfpu_command (char *args
, int from_tty
)
6684 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6685 "\"single\",\"none\" or \"auto\".\n");
6686 show_mipsfpu_command (args
, from_tty
);
6690 set_mipsfpu_single_command (char *args
, int from_tty
)
6692 struct gdbarch_info info
;
6693 gdbarch_info_init (&info
);
6694 mips_fpu_type
= MIPS_FPU_SINGLE
;
6695 mips_fpu_type_auto
= 0;
6696 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6697 instead of relying on globals. Doing that would let generic code
6698 handle the search for this specific architecture. */
6699 if (!gdbarch_update_p (info
))
6700 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6704 set_mipsfpu_double_command (char *args
, int from_tty
)
6706 struct gdbarch_info info
;
6707 gdbarch_info_init (&info
);
6708 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6709 mips_fpu_type_auto
= 0;
6710 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6711 instead of relying on globals. Doing that would let generic code
6712 handle the search for this specific architecture. */
6713 if (!gdbarch_update_p (info
))
6714 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6718 set_mipsfpu_none_command (char *args
, int from_tty
)
6720 struct gdbarch_info info
;
6721 gdbarch_info_init (&info
);
6722 mips_fpu_type
= MIPS_FPU_NONE
;
6723 mips_fpu_type_auto
= 0;
6724 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6725 instead of relying on globals. Doing that would let generic code
6726 handle the search for this specific architecture. */
6727 if (!gdbarch_update_p (info
))
6728 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6732 set_mipsfpu_auto_command (char *args
, int from_tty
)
6734 mips_fpu_type_auto
= 1;
6737 /* Attempt to identify the particular processor model by reading the
6738 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6739 the relevant processor still exists (it dates back to '94) and
6740 secondly this is not the way to do this. The processor type should
6741 be set by forcing an architecture change. */
6744 deprecated_mips_set_processor_regs_hack (void)
6746 struct regcache
*regcache
= get_current_regcache ();
6747 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6748 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6751 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6752 if ((prid
& ~0xf) == 0x700)
6753 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6756 /* Just like reinit_frame_cache, but with the right arguments to be
6757 callable as an sfunc. */
6760 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6761 struct cmd_list_element
*c
)
6763 reinit_frame_cache ();
6767 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6769 struct gdbarch
*gdbarch
= info
->application_data
;
6771 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6772 disassembler needs to be able to locally determine the ISA, and
6773 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6775 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6776 info
->mach
= bfd_mach_mips16
;
6777 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6778 info
->mach
= bfd_mach_mips_micromips
;
6780 /* Round down the instruction address to the appropriate boundary. */
6781 memaddr
&= (info
->mach
== bfd_mach_mips16
6782 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6784 /* Set the disassembler options. */
6785 if (!info
->disassembler_options
)
6786 /* This string is not recognized explicitly by the disassembler,
6787 but it tells the disassembler to not try to guess the ABI from
6788 the bfd elf headers, such that, if the user overrides the ABI
6789 of a program linked as NewABI, the disassembly will follow the
6790 register naming conventions specified by the user. */
6791 info
->disassembler_options
= "gpr-names=32";
6793 /* Call the appropriate disassembler based on the target endian-ness. */
6794 if (info
->endian
== BFD_ENDIAN_BIG
)
6795 return print_insn_big_mips (memaddr
, info
);
6797 return print_insn_little_mips (memaddr
, info
);
6801 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6803 /* Set up the disassembler info, so that we get the right
6804 register names from libopcodes. */
6805 info
->disassembler_options
= "gpr-names=n32";
6806 info
->flavour
= bfd_target_elf_flavour
;
6808 return gdb_print_insn_mips (memaddr
, info
);
6812 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6814 /* Set up the disassembler info, so that we get the right
6815 register names from libopcodes. */
6816 info
->disassembler_options
= "gpr-names=64";
6817 info
->flavour
= bfd_target_elf_flavour
;
6819 return gdb_print_insn_mips (memaddr
, info
);
6822 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6823 program counter value to determine whether a 16- or 32-bit breakpoint
6824 should be used. It returns a pointer to a string of bytes that encode a
6825 breakpoint instruction, stores the length of the string to *lenptr, and
6826 adjusts pc (if necessary) to point to the actual memory location where
6827 the breakpoint should be inserted. */
6829 static const gdb_byte
*
6830 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6831 CORE_ADDR
*pcptr
, int *lenptr
)
6833 CORE_ADDR pc
= *pcptr
;
6835 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6837 if (mips_pc_is_mips16 (gdbarch
, pc
))
6839 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6840 *pcptr
= unmake_compact_addr (pc
);
6841 *lenptr
= sizeof (mips16_big_breakpoint
);
6842 return mips16_big_breakpoint
;
6844 else if (mips_pc_is_micromips (gdbarch
, pc
))
6846 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6847 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6852 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6854 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6855 *pcptr
= unmake_compact_addr (pc
);
6857 return (size
== 2) ? micromips16_big_breakpoint
6858 : micromips32_big_breakpoint
;
6862 /* The IDT board uses an unusual breakpoint value, and
6863 sometimes gets confused when it sees the usual MIPS
6864 breakpoint instruction. */
6865 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6866 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6867 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6868 /* Likewise, IRIX appears to expect a different breakpoint,
6869 although this is not apparent until you try to use pthreads. */
6870 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6872 *lenptr
= sizeof (big_breakpoint
);
6874 if (strcmp (target_shortname
, "mips") == 0)
6875 return idt_big_breakpoint
;
6876 else if (strcmp (target_shortname
, "ddb") == 0
6877 || strcmp (target_shortname
, "pmon") == 0
6878 || strcmp (target_shortname
, "lsi") == 0)
6879 return pmon_big_breakpoint
;
6880 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6881 return irix_big_breakpoint
;
6883 return big_breakpoint
;
6888 if (mips_pc_is_mips16 (gdbarch
, pc
))
6890 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
6891 *pcptr
= unmake_compact_addr (pc
);
6892 *lenptr
= sizeof (mips16_little_breakpoint
);
6893 return mips16_little_breakpoint
;
6895 else if (mips_pc_is_micromips (gdbarch
, pc
))
6897 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
6898 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
6903 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6905 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6906 *pcptr
= unmake_compact_addr (pc
);
6908 return (size
== 2) ? micromips16_little_breakpoint
6909 : micromips32_little_breakpoint
;
6913 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
6914 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
6915 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
6917 *lenptr
= sizeof (little_breakpoint
);
6919 if (strcmp (target_shortname
, "mips") == 0)
6920 return idt_little_breakpoint
;
6921 else if (strcmp (target_shortname
, "ddb") == 0
6922 || strcmp (target_shortname
, "pmon") == 0
6923 || strcmp (target_shortname
, "lsi") == 0)
6924 return pmon_little_breakpoint
;
6926 return little_breakpoint
;
6931 /* Determine the remote breakpoint kind suitable for the PC. The following
6934 * 2 -- 16-bit MIPS16 mode breakpoint,
6936 * 3 -- 16-bit microMIPS mode breakpoint,
6938 * 4 -- 32-bit standard MIPS mode breakpoint,
6940 * 5 -- 32-bit microMIPS mode breakpoint. */
6943 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
6946 CORE_ADDR pc
= *pcptr
;
6948 if (mips_pc_is_mips16 (gdbarch
, pc
))
6950 *pcptr
= unmake_compact_addr (pc
);
6953 else if (mips_pc_is_micromips (gdbarch
, pc
))
6959 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6960 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6961 *pcptr
= unmake_compact_addr (pc
);
6962 *kindptr
= size
| 1;
6968 /* Return non-zero if the ADDR instruction has a branch delay slot
6969 (i.e. it is a jump or branch instruction). This function is based
6970 on mips32_next_pc. */
6973 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
6981 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
6985 op
= itype_op (inst
);
6986 if ((inst
& 0xe0000000) != 0)
6988 rs
= itype_rs (inst
);
6989 rt
= itype_rt (inst
);
6990 return (is_octeon_bbit_op (op
, gdbarch
)
6991 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6992 || op
== 29 /* JALX: bits 011101 */
6995 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
6996 || (rs
== 9 && (rt
& 0x2) == 0)
6997 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
6998 || (rs
== 10 && (rt
& 0x2) == 0))));
6999 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7002 switch (op
& 0x07) /* extract bits 28,27,26 */
7004 case 0: /* SPECIAL */
7005 op
= rtype_funct (inst
);
7006 return (op
== 8 /* JR */
7007 || op
== 9); /* JALR */
7008 break; /* end SPECIAL */
7009 case 1: /* REGIMM */
7010 rs
= itype_rs (inst
);
7011 rt
= itype_rt (inst
); /* branch condition */
7012 return ((rt
& 0xc) == 0
7013 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7014 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7015 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7016 /* BPOSGE32, BPOSGE64: bits 1110x */
7017 break; /* end REGIMM */
7018 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7024 /* Return non-zero if the ADDR instruction, which must be a 32-bit
7025 instruction if MUSTBE32 is set or can be any instruction otherwise,
7026 has a branch delay slot (i.e. it is a non-compact jump instruction). */
7029 micromips_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
7030 CORE_ADDR addr
, int mustbe32
)
7035 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7039 if (!mustbe32
) /* 16-bit instructions. */
7040 return (micromips_op (insn
) == 0x11
7041 /* POOL16C: bits 010001 */
7042 && (b5s5_op (insn
) == 0xc
7043 /* JR16: bits 010001 01100 */
7044 || (b5s5_op (insn
) & 0x1e) == 0xe))
7045 /* JALR16, JALRS16: bits 010001 0111x */
7046 || (micromips_op (insn
) & 0x37) == 0x23
7047 /* BEQZ16, BNEZ16: bits 10x011 */
7048 || micromips_op (insn
) == 0x33;
7049 /* B16: bits 110011 */
7051 /* 32-bit instructions. */
7052 if (micromips_op (insn
) == 0x0)
7053 /* POOL32A: bits 000000 */
7056 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7059 return b0s6_op (insn
) == 0x3c
7060 /* POOL32Axf: bits 000000 ... 111100 */
7061 && (b6s10_ext (insn
) & 0x2bf) == 0x3c;
7062 /* JALR, JALR.HB: 000000 000x111100 111100 */
7063 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7066 return (micromips_op (insn
) == 0x10
7067 /* POOL32I: bits 010000 */
7068 && ((b5s5_op (insn
) & 0x1c) == 0x0
7069 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7070 || (b5s5_op (insn
) & 0x1d) == 0x4
7071 /* BLEZ, BGTZ: bits 010000 001x0 */
7072 || (b5s5_op (insn
) & 0x1d) == 0x11
7073 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7074 || ((b5s5_op (insn
) & 0x1e) == 0x14
7075 && (insn
& 0x3) == 0x0)
7076 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7077 || (b5s5_op (insn
) & 0x1e) == 0x1a
7078 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7079 || ((b5s5_op (insn
) & 0x1e) == 0x1c
7080 && (insn
& 0x3) == 0x0)
7081 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7082 || ((b5s5_op (insn
) & 0x1c) == 0x1c
7083 && (insn
& 0x3) == 0x1)))
7084 /* BC1ANY*: bits 010000 111xx xxx01 */
7085 || (micromips_op (insn
) & 0x1f) == 0x1d
7086 /* JALS, JAL: bits x11101 */
7087 || (micromips_op (insn
) & 0x37) == 0x25
7088 /* BEQ, BNE: bits 10x101 */
7089 || micromips_op (insn
) == 0x35
7090 /* J: bits 110101 */
7091 || micromips_op (insn
) == 0x3c;
7092 /* JALX: bits 111100 */
7096 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
7099 unsigned short inst
;
7102 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7107 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7108 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7111 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7112 This assumes KSSEG exists. */
7115 mips_segment_boundary (CORE_ADDR bpaddr
)
7117 CORE_ADDR mask
= CORE_ADDR_MAX
;
7120 if (sizeof (CORE_ADDR
) == 8)
7121 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7122 a compiler warning produced where CORE_ADDR is a 32-bit type even
7123 though in that case this is dead code). */
7124 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7127 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7128 segsize
= 29; /* 32-bit compatibility segment */
7130 segsize
= 62; /* xkseg */
7132 case 2: /* xkphys */
7135 default: /* xksseg (1), xkuseg/kuseg (0) */
7139 else if (bpaddr
& 0x80000000) /* kernel segment */
7142 segsize
= 31; /* user segment */
7144 return bpaddr
& mask
;
7147 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7148 it backwards if necessary. Return the address of the new location. */
7151 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7153 CORE_ADDR prev_addr
;
7155 CORE_ADDR func_addr
;
7157 /* If a breakpoint is set on the instruction in a branch delay slot,
7158 GDB gets confused. When the breakpoint is hit, the PC isn't on
7159 the instruction in the branch delay slot, the PC will point to
7160 the branch instruction. Since the PC doesn't match any known
7161 breakpoints, GDB reports a trap exception.
7163 There are two possible fixes for this problem.
7165 1) When the breakpoint gets hit, see if the BD bit is set in the
7166 Cause register (which indicates the last exception occurred in a
7167 branch delay slot). If the BD bit is set, fix the PC to point to
7168 the instruction in the branch delay slot.
7170 2) When the user sets the breakpoint, don't allow him to set the
7171 breakpoint on the instruction in the branch delay slot. Instead
7172 move the breakpoint to the branch instruction (which will have
7175 The problem with the first solution is that if the user then
7176 single-steps the processor, the branch instruction will get
7177 skipped (since GDB thinks the PC is on the instruction in the
7180 So, we'll use the second solution. To do this we need to know if
7181 the instruction we're trying to set the breakpoint on is in the
7182 branch delay slot. */
7184 boundary
= mips_segment_boundary (bpaddr
);
7186 /* Make sure we don't scan back before the beginning of the current
7187 function, since we may fetch constant data or insns that look like
7188 a jump. Of course we might do that anyway if the compiler has
7189 moved constants inline. :-( */
7190 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7191 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7192 boundary
= func_addr
;
7194 if (mips_pc_is_mips (bpaddr
))
7196 if (bpaddr
== boundary
)
7199 /* If the previous instruction has a branch delay slot, we have
7200 to move the breakpoint to the branch instruction. */
7201 prev_addr
= bpaddr
- 4;
7202 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
7207 int (*instruction_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7208 CORE_ADDR addr
, jmpaddr
;
7211 boundary
= unmake_compact_addr (boundary
);
7213 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7214 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7215 so try for that first, then try the 2 byte JALR/JR.
7216 The microMIPS ASE has a whole range of jumps and branches
7217 with delay slots, some of which take 4 bytes and some take
7218 2 bytes, so the idea is the same.
7219 FIXME: We have to assume that bpaddr is not the second half
7220 of an extended instruction. */
7221 instruction_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7222 ? micromips_instruction_has_delay_slot
7223 : mips16_instruction_has_delay_slot
);
7227 for (i
= 1; i
< 4; i
++)
7229 if (unmake_compact_addr (addr
) == boundary
)
7231 addr
-= MIPS_INSN16_SIZE
;
7232 if (i
== 1 && instruction_has_delay_slot (gdbarch
, addr
, 0))
7233 /* Looks like a JR/JALR at [target-1], but it could be
7234 the second word of a previous JAL/JALX, so record it
7235 and check back one more. */
7237 else if (i
> 1 && instruction_has_delay_slot (gdbarch
, addr
, 1))
7240 /* Looks like a JAL/JALX at [target-2], but it could also
7241 be the second word of a previous JAL/JALX, record it,
7242 and check back one more. */
7245 /* Looks like a JAL/JALX at [target-3], so any previously
7246 recorded JAL/JALX or JR/JALR must be wrong, because:
7249 -2: JAL-ext (can't be JAL/JALX)
7250 -1: bdslot (can't be JR/JALR)
7253 Of course it could be another JAL-ext which looks
7254 like a JAL, but in that case we'd have broken out
7255 of this loop at [target-2]:
7259 -2: bdslot (can't be jmp)
7266 /* Not a jump instruction: if we're at [target-1] this
7267 could be the second word of a JAL/JALX, so continue;
7268 otherwise we're done. */
7281 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7282 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7285 mips_is_stub_suffix (const char *suffix
, int zero
)
7290 return zero
&& suffix
[1] == '\0';
7292 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7297 return suffix
[1] == '\0';
7303 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7304 call stubs, one of sf, df, sc, or dc. */
7307 mips_is_stub_mode (const char *mode
)
7309 return ((mode
[0] == 's' || mode
[0] == 'd')
7310 && (mode
[1] == 'f' || mode
[1] == 'c'));
7313 /* Code at PC is a compiler-generated stub. Such a stub for a function
7314 bar might have a name like __fn_stub_bar, and might look like this:
7321 followed by (or interspersed with):
7328 addiu $25, $25, %lo(bar)
7331 ($1 may be used in old code; for robustness we accept any register)
7334 lui $28, %hi(_gp_disp)
7335 addiu $28, $28, %lo(_gp_disp)
7338 addiu $25, $25, %lo(bar)
7341 In the case of a __call_stub_bar stub, the sequence to set up
7342 arguments might look like this:
7349 followed by (or interspersed with) one of the jump sequences above.
7351 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7352 of J or JR, respectively, followed by:
7358 We are at the beginning of the stub here, and scan down and extract
7359 the target address from the jump immediate instruction or, if a jump
7360 register instruction is used, from the register referred. Return
7361 the value of PC calculated or 0 if inconclusive.
7363 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7366 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7368 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7369 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7370 int addrreg
= MIPS_ZERO_REGNUM
;
7371 CORE_ADDR start_pc
= pc
;
7372 CORE_ADDR target_pc
= 0;
7379 status
== 0 && target_pc
== 0 && i
< 20;
7380 i
++, pc
+= MIPS_INSN32_SIZE
)
7382 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7388 switch (itype_op (inst
))
7390 case 0: /* SPECIAL */
7391 switch (rtype_funct (inst
))
7395 rs
= rtype_rs (inst
);
7396 if (rs
== MIPS_GP_REGNUM
)
7397 target_pc
= gp
; /* Hmm... */
7398 else if (rs
== addrreg
)
7402 case 0x21: /* ADDU */
7403 rt
= rtype_rt (inst
);
7404 rs
= rtype_rs (inst
);
7405 rd
= rtype_rd (inst
);
7406 if (rd
== MIPS_GP_REGNUM
7407 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7408 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7416 target_pc
= jtype_target (inst
) << 2;
7417 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7421 rt
= itype_rt (inst
);
7422 rs
= itype_rs (inst
);
7425 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7426 if (rt
== MIPS_GP_REGNUM
)
7428 else if (rt
== addrreg
)
7434 rt
= itype_rt (inst
);
7435 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7436 if (rt
== MIPS_GP_REGNUM
)
7438 else if (rt
!= MIPS_ZERO_REGNUM
)
7446 rt
= itype_rt (inst
);
7447 rs
= itype_rs (inst
);
7448 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7449 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7453 memset (buf
, 0, sizeof (buf
));
7454 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7456 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7465 /* If PC is in a MIPS16 call or return stub, return the address of the
7466 target PC, which is either the callee or the caller. There are several
7467 cases which must be handled:
7469 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7470 and the target PC is in $31 ($ra).
7471 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7472 and the target PC is in $2.
7473 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7474 i.e. before the JALR instruction, this is effectively a call stub
7475 and the target PC is in $2. Otherwise this is effectively
7476 a return stub and the target PC is in $18.
7477 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7478 JAL or JALR instruction, this is effectively a call stub and the
7479 target PC is buried in the instruction stream. Otherwise this
7480 is effectively a return stub and the target PC is in $18.
7481 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7482 stub and the target PC is buried in the instruction stream.
7484 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7485 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7489 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7491 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7492 CORE_ADDR start_addr
;
7496 /* Find the starting address and name of the function containing the PC. */
7497 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7500 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7501 and the target PC is in $31 ($ra). */
7502 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7503 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7504 && mips_is_stub_mode (name
+ prefixlen
)
7505 && name
[prefixlen
+ 2] == '\0')
7506 return get_frame_register_signed
7507 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7509 /* If the PC is in __mips16_call_stub_*, this is one of the call
7510 call/return stubs. */
7511 prefixlen
= strlen (mips_str_mips16_call_stub
);
7512 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7514 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7515 and the target PC is in $2. */
7516 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7517 return get_frame_register_signed
7518 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7520 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7521 i.e. before the JALR instruction, this is effectively a call stub
7522 and the target PC is in $2. Otherwise this is effectively
7523 a return stub and the target PC is in $18. */
7524 else if (mips_is_stub_mode (name
+ prefixlen
)
7525 && name
[prefixlen
+ 2] == '_'
7526 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7528 if (pc
== start_addr
)
7529 /* This is the 'call' part of a call stub. The return
7530 address is in $2. */
7531 return get_frame_register_signed
7532 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7534 /* This is the 'return' part of a call stub. The return
7535 address is in $18. */
7536 return get_frame_register_signed
7537 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7540 return 0; /* Not a stub. */
7543 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7544 compiler-generated call or call/return stubs. */
7545 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7546 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7548 if (pc
== start_addr
)
7549 /* This is the 'call' part of a call stub. Call this helper
7550 to scan through this code for interesting instructions
7551 and determine the final PC. */
7552 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7554 /* This is the 'return' part of a call stub. The return address
7556 return get_frame_register_signed
7557 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7560 return 0; /* Not a stub. */
7563 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7564 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7567 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7569 CORE_ADDR start_addr
;
7572 /* Find the starting address of the function containing the PC. */
7573 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7576 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7577 the start, i.e. after the JALR instruction, this is effectively
7579 prefixlen
= strlen (mips_str_mips16_call_stub
);
7580 if (pc
!= start_addr
7581 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7582 && mips_is_stub_mode (name
+ prefixlen
)
7583 && name
[prefixlen
+ 2] == '_'
7584 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7587 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7588 the JAL or JALR instruction, this is effectively a return stub. */
7589 prefixlen
= strlen (mips_str_call_fp_stub
);
7590 if (pc
!= start_addr
7591 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7594 /* Consume the .pic. prefix of any PIC stub, this function must return
7595 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7596 or the call stub path will trigger in handle_inferior_event causing
7598 prefixlen
= strlen (mips_str_pic
);
7599 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7602 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7603 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7604 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7605 && mips_is_stub_mode (name
+ prefixlen
)
7606 && name
[prefixlen
+ 2] == '\0')
7609 return 0; /* Not a stub. */
7612 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7613 PC of the stub target. The stub just loads $t9 and jumps to it,
7614 so that $t9 has the correct value at function entry. */
7617 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7619 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7620 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7621 struct bound_minimal_symbol msym
;
7623 gdb_byte stub_code
[16];
7624 int32_t stub_words
[4];
7626 /* The stub for foo is named ".pic.foo", and is either two
7627 instructions inserted before foo or a three instruction sequence
7628 which jumps to foo. */
7629 msym
= lookup_minimal_symbol_by_pc (pc
);
7630 if (msym
.minsym
== NULL
7631 || SYMBOL_VALUE_ADDRESS (msym
.minsym
) != pc
7632 || SYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7633 || strncmp (SYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) != 0)
7636 /* A two-instruction header. */
7637 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7640 /* A three-instruction (plus delay slot) trampoline. */
7641 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7643 if (target_read_memory (pc
, stub_code
, 16) != 0)
7645 for (i
= 0; i
< 4; i
++)
7646 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7649 /* A stub contains these instructions:
7652 addiu t9, t9, %lo(target)
7655 This works even for N64, since stubs are only generated with
7657 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7658 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7659 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7660 && stub_words
[3] == 0x00000000)
7661 return ((((stub_words
[0] & 0x0000ffff) << 16)
7662 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7665 /* Not a recognized stub. */
7670 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7672 CORE_ADDR requested_pc
= pc
;
7673 CORE_ADDR target_pc
;
7680 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7684 if (is_compact_addr (pc
))
7685 pc
= unmake_compact_addr (pc
);
7688 new_pc
= find_solib_trampoline_target (frame
, pc
);
7692 if (is_compact_addr (pc
))
7693 pc
= unmake_compact_addr (pc
);
7696 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7700 if (is_compact_addr (pc
))
7701 pc
= unmake_compact_addr (pc
);
7704 while (pc
!= target_pc
);
7706 return pc
!= requested_pc
? pc
: 0;
7709 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7710 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7713 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7716 if (num
>= 0 && num
< 32)
7718 else if (num
>= 38 && num
< 70)
7719 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7721 regnum
= mips_regnum (gdbarch
)->hi
;
7723 regnum
= mips_regnum (gdbarch
)->lo
;
7724 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7725 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7727 /* This will hopefully (eventually) provoke a warning. Should
7728 we be calling complaint() here? */
7729 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7730 return gdbarch_num_regs (gdbarch
) + regnum
;
7734 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7735 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7738 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7741 if (num
>= 0 && num
< 32)
7743 else if (num
>= 32 && num
< 64)
7744 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7746 regnum
= mips_regnum (gdbarch
)->hi
;
7748 regnum
= mips_regnum (gdbarch
)->lo
;
7749 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7750 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7752 /* This will hopefully (eventually) provoke a warning. Should we
7753 be calling complaint() here? */
7754 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7755 return gdbarch_num_regs (gdbarch
) + regnum
;
7759 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7761 /* Only makes sense to supply raw registers. */
7762 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7763 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7764 decide if it is valid. Should instead define a standard sim/gdb
7765 register numbering scheme. */
7766 if (gdbarch_register_name (gdbarch
,
7767 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7768 && gdbarch_register_name (gdbarch
,
7769 gdbarch_num_regs (gdbarch
)
7770 + regnum
)[0] != '\0')
7773 return LEGACY_SIM_REGNO_IGNORE
;
7777 /* Convert an integer into an address. Extracting the value signed
7778 guarantees a correctly sign extended address. */
7781 mips_integer_to_address (struct gdbarch
*gdbarch
,
7782 struct type
*type
, const gdb_byte
*buf
)
7784 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7785 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7788 /* Dummy virtual frame pointer method. This is no more or less accurate
7789 than most other architectures; we just need to be explicit about it,
7790 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7791 an assertion failure. */
7794 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7795 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7797 *reg
= MIPS_SP_REGNUM
;
7802 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7804 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7805 const char *name
= bfd_get_section_name (abfd
, sect
);
7807 if (*abip
!= MIPS_ABI_UNKNOWN
)
7810 if (strncmp (name
, ".mdebug.", 8) != 0)
7813 if (strcmp (name
, ".mdebug.abi32") == 0)
7814 *abip
= MIPS_ABI_O32
;
7815 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7816 *abip
= MIPS_ABI_N32
;
7817 else if (strcmp (name
, ".mdebug.abi64") == 0)
7818 *abip
= MIPS_ABI_N64
;
7819 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7820 *abip
= MIPS_ABI_O64
;
7821 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7822 *abip
= MIPS_ABI_EABI32
;
7823 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7824 *abip
= MIPS_ABI_EABI64
;
7826 warning (_("unsupported ABI %s."), name
+ 8);
7830 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7832 int *lbp
= (int *) obj
;
7833 const char *name
= bfd_get_section_name (abfd
, sect
);
7835 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7837 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7839 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7840 warning (_("unrecognized .gcc_compiled_longXX"));
7843 static enum mips_abi
7844 global_mips_abi (void)
7848 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7849 if (mips_abi_strings
[i
] == mips_abi_string
)
7850 return (enum mips_abi
) i
;
7852 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7855 /* Return the default compressed instruction set, either of MIPS16
7856 or microMIPS, selected when none could have been determined from
7857 the ELF header of the binary being executed (or no binary has been
7860 static enum mips_isa
7861 global_mips_compression (void)
7865 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
7866 if (mips_compression_strings
[i
] == mips_compression_string
)
7867 return (enum mips_isa
) i
;
7869 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
7873 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
7875 /* If the size matches the set of 32-bit or 64-bit integer registers,
7876 assume that's what we've got. */
7877 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
7878 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
7880 /* If the size matches the full set of registers GDB traditionally
7881 knows about, including floating point, for either 32-bit or
7882 64-bit, assume that's what we've got. */
7883 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
7884 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
7886 /* Otherwise we don't have a useful guess. */
7889 static struct value
*
7890 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
7892 const int *reg_p
= baton
;
7893 return value_of_register (*reg_p
, frame
);
7896 static struct gdbarch
*
7897 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7899 struct gdbarch
*gdbarch
;
7900 struct gdbarch_tdep
*tdep
;
7902 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
7904 enum mips_fpu_type fpu_type
;
7905 struct tdesc_arch_data
*tdesc_data
= NULL
;
7906 int elf_fpu_type
= 0;
7907 const char **reg_names
;
7908 struct mips_regnum mips_regnum
, *regnum
;
7909 enum mips_isa mips_isa
;
7913 /* Fill in the OS dependent register numbers and names. */
7914 if (info
.osabi
== GDB_OSABI_IRIX
)
7916 mips_regnum
.fp0
= 32;
7917 mips_regnum
.pc
= 64;
7918 mips_regnum
.cause
= 65;
7919 mips_regnum
.badvaddr
= 66;
7920 mips_regnum
.hi
= 67;
7921 mips_regnum
.lo
= 68;
7922 mips_regnum
.fp_control_status
= 69;
7923 mips_regnum
.fp_implementation_revision
= 70;
7924 mips_regnum
.dspacc
= dspacc
= -1;
7925 mips_regnum
.dspctl
= dspctl
= -1;
7927 reg_names
= mips_irix_reg_names
;
7929 else if (info
.osabi
== GDB_OSABI_LINUX
)
7931 mips_regnum
.fp0
= 38;
7932 mips_regnum
.pc
= 37;
7933 mips_regnum
.cause
= 36;
7934 mips_regnum
.badvaddr
= 35;
7935 mips_regnum
.hi
= 34;
7936 mips_regnum
.lo
= 33;
7937 mips_regnum
.fp_control_status
= 70;
7938 mips_regnum
.fp_implementation_revision
= 71;
7939 mips_regnum
.dspacc
= -1;
7940 mips_regnum
.dspctl
= -1;
7944 reg_names
= mips_linux_reg_names
;
7948 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
7949 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
7950 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
7951 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
7952 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
7953 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
7954 mips_regnum
.fp_control_status
= 70;
7955 mips_regnum
.fp_implementation_revision
= 71;
7956 mips_regnum
.dspacc
= dspacc
= -1;
7957 mips_regnum
.dspctl
= dspctl
= -1;
7958 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
7959 if (info
.bfd_arch_info
!= NULL
7960 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
7961 reg_names
= mips_tx39_reg_names
;
7963 reg_names
= mips_generic_reg_names
;
7966 /* Check any target description for validity. */
7967 if (tdesc_has_registers (info
.target_desc
))
7969 static const char *const mips_gprs
[] = {
7970 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7971 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7972 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7973 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7975 static const char *const mips_fprs
[] = {
7976 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7977 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7978 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7979 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7982 const struct tdesc_feature
*feature
;
7985 feature
= tdesc_find_feature (info
.target_desc
,
7986 "org.gnu.gdb.mips.cpu");
7987 if (feature
== NULL
)
7990 tdesc_data
= tdesc_data_alloc ();
7993 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
7994 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
7998 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7999 mips_regnum
.lo
, "lo");
8000 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8001 mips_regnum
.hi
, "hi");
8002 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8003 mips_regnum
.pc
, "pc");
8007 tdesc_data_cleanup (tdesc_data
);
8011 feature
= tdesc_find_feature (info
.target_desc
,
8012 "org.gnu.gdb.mips.cp0");
8013 if (feature
== NULL
)
8015 tdesc_data_cleanup (tdesc_data
);
8020 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8021 mips_regnum
.badvaddr
, "badvaddr");
8022 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8023 MIPS_PS_REGNUM
, "status");
8024 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8025 mips_regnum
.cause
, "cause");
8029 tdesc_data_cleanup (tdesc_data
);
8033 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8034 backend is not prepared for that, though. */
8035 feature
= tdesc_find_feature (info
.target_desc
,
8036 "org.gnu.gdb.mips.fpu");
8037 if (feature
== NULL
)
8039 tdesc_data_cleanup (tdesc_data
);
8044 for (i
= 0; i
< 32; i
++)
8045 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8046 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8048 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8049 mips_regnum
.fp_control_status
,
8052 &= tdesc_numbered_register (feature
, tdesc_data
,
8053 mips_regnum
.fp_implementation_revision
,
8058 tdesc_data_cleanup (tdesc_data
);
8064 feature
= tdesc_find_feature (info
.target_desc
,
8065 "org.gnu.gdb.mips.dsp");
8066 /* The DSP registers are optional; it's OK if they are absent. */
8067 if (feature
!= NULL
)
8071 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8072 dspacc
+ i
++, "hi1");
8073 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8074 dspacc
+ i
++, "lo1");
8075 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8076 dspacc
+ i
++, "hi2");
8077 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8078 dspacc
+ i
++, "lo2");
8079 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8080 dspacc
+ i
++, "hi3");
8081 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8082 dspacc
+ i
++, "lo3");
8084 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8089 tdesc_data_cleanup (tdesc_data
);
8093 mips_regnum
.dspacc
= dspacc
;
8094 mips_regnum
.dspctl
= dspctl
;
8098 /* It would be nice to detect an attempt to use a 64-bit ABI
8099 when only 32-bit registers are provided. */
8103 /* First of all, extract the elf_flags, if available. */
8104 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8105 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8106 else if (arches
!= NULL
)
8107 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8111 fprintf_unfiltered (gdb_stdlog
,
8112 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8114 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8115 switch ((elf_flags
& EF_MIPS_ABI
))
8117 case E_MIPS_ABI_O32
:
8118 found_abi
= MIPS_ABI_O32
;
8120 case E_MIPS_ABI_O64
:
8121 found_abi
= MIPS_ABI_O64
;
8123 case E_MIPS_ABI_EABI32
:
8124 found_abi
= MIPS_ABI_EABI32
;
8126 case E_MIPS_ABI_EABI64
:
8127 found_abi
= MIPS_ABI_EABI64
;
8130 if ((elf_flags
& EF_MIPS_ABI2
))
8131 found_abi
= MIPS_ABI_N32
;
8133 found_abi
= MIPS_ABI_UNKNOWN
;
8137 /* GCC creates a pseudo-section whose name describes the ABI. */
8138 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8139 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8141 /* If we have no useful BFD information, use the ABI from the last
8142 MIPS architecture (if there is one). */
8143 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8144 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8146 /* Try the architecture for any hint of the correct ABI. */
8147 if (found_abi
== MIPS_ABI_UNKNOWN
8148 && info
.bfd_arch_info
!= NULL
8149 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8151 switch (info
.bfd_arch_info
->mach
)
8153 case bfd_mach_mips3900
:
8154 found_abi
= MIPS_ABI_EABI32
;
8156 case bfd_mach_mips4100
:
8157 case bfd_mach_mips5000
:
8158 found_abi
= MIPS_ABI_EABI64
;
8160 case bfd_mach_mips8000
:
8161 case bfd_mach_mips10000
:
8162 /* On Irix, ELF64 executables use the N64 ABI. The
8163 pseudo-sections which describe the ABI aren't present
8164 on IRIX. (Even for executables created by gcc.) */
8165 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8166 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8167 found_abi
= MIPS_ABI_N64
;
8169 found_abi
= MIPS_ABI_N32
;
8174 /* Default 64-bit objects to N64 instead of O32. */
8175 if (found_abi
== MIPS_ABI_UNKNOWN
8176 && info
.abfd
!= NULL
8177 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8178 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8179 found_abi
= MIPS_ABI_N64
;
8182 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8185 /* What has the user specified from the command line? */
8186 wanted_abi
= global_mips_abi ();
8188 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8191 /* Now that we have found what the ABI for this binary would be,
8192 check whether the user is overriding it. */
8193 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8194 mips_abi
= wanted_abi
;
8195 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8196 mips_abi
= found_abi
;
8198 mips_abi
= MIPS_ABI_O32
;
8200 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8203 /* Determine the default compressed ISA. */
8204 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8205 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8206 mips_isa
= ISA_MICROMIPS
;
8207 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8208 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8209 mips_isa
= ISA_MIPS16
;
8211 mips_isa
= global_mips_compression ();
8212 mips_compression_string
= mips_compression_strings
[mips_isa
];
8214 /* Also used when doing an architecture lookup. */
8216 fprintf_unfiltered (gdb_stdlog
,
8217 "mips_gdbarch_init: "
8218 "mips64_transfers_32bit_regs_p = %d\n",
8219 mips64_transfers_32bit_regs_p
);
8221 /* Determine the MIPS FPU type. */
8224 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8225 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8226 Tag_GNU_MIPS_ABI_FP
);
8227 #endif /* HAVE_ELF */
8229 if (!mips_fpu_type_auto
)
8230 fpu_type
= mips_fpu_type
;
8231 else if (elf_fpu_type
!= 0)
8233 switch (elf_fpu_type
)
8236 fpu_type
= MIPS_FPU_DOUBLE
;
8239 fpu_type
= MIPS_FPU_SINGLE
;
8243 /* Soft float or unknown. */
8244 fpu_type
= MIPS_FPU_NONE
;
8248 else if (info
.bfd_arch_info
!= NULL
8249 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8250 switch (info
.bfd_arch_info
->mach
)
8252 case bfd_mach_mips3900
:
8253 case bfd_mach_mips4100
:
8254 case bfd_mach_mips4111
:
8255 case bfd_mach_mips4120
:
8256 fpu_type
= MIPS_FPU_NONE
;
8258 case bfd_mach_mips4650
:
8259 fpu_type
= MIPS_FPU_SINGLE
;
8262 fpu_type
= MIPS_FPU_DOUBLE
;
8265 else if (arches
!= NULL
)
8266 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8268 fpu_type
= MIPS_FPU_DOUBLE
;
8270 fprintf_unfiltered (gdb_stdlog
,
8271 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8273 /* Check for blatant incompatibilities. */
8275 /* If we have only 32-bit registers, then we can't debug a 64-bit
8277 if (info
.target_desc
8278 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8279 && mips_abi
!= MIPS_ABI_EABI32
8280 && mips_abi
!= MIPS_ABI_O32
)
8282 if (tdesc_data
!= NULL
)
8283 tdesc_data_cleanup (tdesc_data
);
8287 /* Try to find a pre-existing architecture. */
8288 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8290 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8292 /* MIPS needs to be pedantic about which ABI the object is
8294 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8296 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8298 /* Need to be pedantic about which register virtual size is
8300 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8301 != mips64_transfers_32bit_regs_p
)
8303 /* Be pedantic about which FPU is selected. */
8304 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8307 if (tdesc_data
!= NULL
)
8308 tdesc_data_cleanup (tdesc_data
);
8309 return arches
->gdbarch
;
8312 /* Need a new architecture. Fill in a target specific vector. */
8313 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8314 gdbarch
= gdbarch_alloc (&info
, tdep
);
8315 tdep
->elf_flags
= elf_flags
;
8316 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8317 tdep
->found_abi
= found_abi
;
8318 tdep
->mips_abi
= mips_abi
;
8319 tdep
->mips_isa
= mips_isa
;
8320 tdep
->mips_fpu_type
= fpu_type
;
8321 tdep
->register_size_valid_p
= 0;
8322 tdep
->register_size
= 0;
8323 tdep
->gregset
= NULL
;
8324 tdep
->gregset64
= NULL
;
8325 tdep
->fpregset
= NULL
;
8326 tdep
->fpregset64
= NULL
;
8328 if (info
.target_desc
)
8330 /* Some useful properties can be inferred from the target. */
8331 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8333 tdep
->register_size_valid_p
= 1;
8334 tdep
->register_size
= 4;
8336 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8338 tdep
->register_size_valid_p
= 1;
8339 tdep
->register_size
= 8;
8343 /* Initially set everything according to the default ABI/ISA. */
8344 set_gdbarch_short_bit (gdbarch
, 16);
8345 set_gdbarch_int_bit (gdbarch
, 32);
8346 set_gdbarch_float_bit (gdbarch
, 32);
8347 set_gdbarch_double_bit (gdbarch
, 64);
8348 set_gdbarch_long_double_bit (gdbarch
, 64);
8349 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8350 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8351 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8353 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8354 mips_ax_pseudo_register_collect
);
8355 set_gdbarch_ax_pseudo_register_push_stack
8356 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8358 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8359 mips_elf_make_msymbol_special
);
8361 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8362 *regnum
= mips_regnum
;
8363 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8364 set_gdbarch_num_regs (gdbarch
, num_regs
);
8365 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8366 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8367 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8368 tdep
->mips_processor_reg_names
= reg_names
;
8369 tdep
->regnum
= regnum
;
8374 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8375 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8376 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8377 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8378 tdep
->default_mask_address_p
= 0;
8379 set_gdbarch_long_bit (gdbarch
, 32);
8380 set_gdbarch_ptr_bit (gdbarch
, 32);
8381 set_gdbarch_long_long_bit (gdbarch
, 64);
8384 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8385 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8386 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8387 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8388 tdep
->default_mask_address_p
= 0;
8389 set_gdbarch_long_bit (gdbarch
, 32);
8390 set_gdbarch_ptr_bit (gdbarch
, 32);
8391 set_gdbarch_long_long_bit (gdbarch
, 64);
8393 case MIPS_ABI_EABI32
:
8394 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8395 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8396 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8397 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8398 tdep
->default_mask_address_p
= 0;
8399 set_gdbarch_long_bit (gdbarch
, 32);
8400 set_gdbarch_ptr_bit (gdbarch
, 32);
8401 set_gdbarch_long_long_bit (gdbarch
, 64);
8403 case MIPS_ABI_EABI64
:
8404 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8405 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8406 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8407 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8408 tdep
->default_mask_address_p
= 0;
8409 set_gdbarch_long_bit (gdbarch
, 64);
8410 set_gdbarch_ptr_bit (gdbarch
, 64);
8411 set_gdbarch_long_long_bit (gdbarch
, 64);
8414 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8415 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8416 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8417 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8418 tdep
->default_mask_address_p
= 0;
8419 set_gdbarch_long_bit (gdbarch
, 32);
8420 set_gdbarch_ptr_bit (gdbarch
, 32);
8421 set_gdbarch_long_long_bit (gdbarch
, 64);
8422 set_gdbarch_long_double_bit (gdbarch
, 128);
8423 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8426 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8427 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8428 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8429 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8430 tdep
->default_mask_address_p
= 0;
8431 set_gdbarch_long_bit (gdbarch
, 64);
8432 set_gdbarch_ptr_bit (gdbarch
, 64);
8433 set_gdbarch_long_long_bit (gdbarch
, 64);
8434 set_gdbarch_long_double_bit (gdbarch
, 128);
8435 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8438 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8441 /* GCC creates a pseudo-section whose name specifies the size of
8442 longs, since -mlong32 or -mlong64 may be used independent of
8443 other options. How those options affect pointer sizes is ABI and
8444 architecture dependent, so use them to override the default sizes
8445 set by the ABI. This table shows the relationship between ABI,
8446 -mlongXX, and size of pointers:
8448 ABI -mlongXX ptr bits
8449 --- -------- --------
8463 Note that for o32 and eabi32, pointers are always 32 bits
8464 regardless of any -mlongXX option. For all others, pointers and
8465 longs are the same, as set by -mlongXX or set by defaults. */
8467 if (info
.abfd
!= NULL
)
8471 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8474 set_gdbarch_long_bit (gdbarch
, long_bit
);
8478 case MIPS_ABI_EABI32
:
8483 case MIPS_ABI_EABI64
:
8484 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8487 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8492 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8493 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8496 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8497 flag in object files because to do so would make it impossible to
8498 link with libraries compiled without "-gp32". This is
8499 unnecessarily restrictive.
8501 We could solve this problem by adding "-gp32" multilibs to gcc,
8502 but to set this flag before gcc is built with such multilibs will
8503 break too many systems.''
8505 But even more unhelpfully, the default linker output target for
8506 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8507 for 64-bit programs - you need to change the ABI to change this,
8508 and not all gcc targets support that currently. Therefore using
8509 this flag to detect 32-bit mode would do the wrong thing given
8510 the current gcc - it would make GDB treat these 64-bit programs
8511 as 32-bit programs by default. */
8513 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8514 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8516 /* Add/remove bits from an address. The MIPS needs be careful to
8517 ensure that all 32 bit addresses are sign extended to 64 bits. */
8518 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8520 /* Unwind the frame. */
8521 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8522 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8523 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8525 /* Map debug register numbers onto internal register numbers. */
8526 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8527 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8528 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8529 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8530 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8531 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8533 /* MIPS version of CALL_DUMMY. */
8535 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8536 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8537 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8539 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8540 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8541 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8543 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8544 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8545 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8546 mips_remote_breakpoint_from_pc
);
8547 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8548 mips_adjust_breakpoint_address
);
8550 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8552 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8554 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8555 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8556 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8558 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8560 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8562 if (mips_abi
== MIPS_ABI_N32
)
8563 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8564 else if (mips_abi
== MIPS_ABI_N64
)
8565 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8567 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8569 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8570 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8571 need to all be folded into the target vector. Since they are
8572 being used as guards for target_stopped_by_watchpoint, why not have
8573 target_stopped_by_watchpoint return the type of watchpoint that the code
8575 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8577 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8579 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8580 to support MIPS16. This is a bad thing. Make sure not to do it
8581 if we have an OS ABI that actually supports shared libraries, since
8582 shared library support is more important. If we have an OS someday
8583 that supports both shared libraries and MIPS16, we'll have to find
8584 a better place for these.
8585 macro/2012-04-25: But that applies to return trampolines only and
8586 currently no MIPS OS ABI uses shared libraries that have them. */
8587 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8589 set_gdbarch_single_step_through_delay (gdbarch
,
8590 mips_single_step_through_delay
);
8592 /* Virtual tables. */
8593 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8595 mips_register_g_packet_guesses (gdbarch
);
8597 /* Hook in OS ABI-specific overrides, if they have been registered. */
8598 info
.tdep_info
= (void *) tdesc_data
;
8599 gdbarch_init_osabi (info
, gdbarch
);
8601 /* The hook may have adjusted num_regs, fetch the final value and
8602 set pc_regnum and sp_regnum now that it has been fixed. */
8603 num_regs
= gdbarch_num_regs (gdbarch
);
8604 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8605 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8607 /* Unwind the frame. */
8608 dwarf2_append_unwinders (gdbarch
);
8609 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8610 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8611 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8612 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8613 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8614 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8615 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8616 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8617 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8621 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8622 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8624 /* Override the normal target description methods to handle our
8625 dual real and pseudo registers. */
8626 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8627 set_gdbarch_register_reggroup_p (gdbarch
,
8628 mips_tdesc_register_reggroup_p
);
8630 num_regs
= gdbarch_num_regs (gdbarch
);
8631 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8632 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8633 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8636 /* Add ABI-specific aliases for the registers. */
8637 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8638 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8639 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8640 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8642 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8643 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8644 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8646 /* Add some other standard aliases. */
8647 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8648 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8649 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8651 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8652 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8653 value_of_mips_user_reg
,
8654 &mips_numeric_register_aliases
[i
].regnum
);
8660 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8662 struct gdbarch_info info
;
8664 /* Force the architecture to update, and (if it's a MIPS architecture)
8665 mips_gdbarch_init will take care of the rest. */
8666 gdbarch_info_init (&info
);
8667 gdbarch_update_p (info
);
8670 /* Print out which MIPS ABI is in use. */
8673 show_mips_abi (struct ui_file
*file
,
8675 struct cmd_list_element
*ignored_cmd
,
8676 const char *ignored_value
)
8678 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8681 "The MIPS ABI is unknown because the current architecture "
8685 enum mips_abi global_abi
= global_mips_abi ();
8686 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8687 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8689 if (global_abi
== MIPS_ABI_UNKNOWN
)
8692 "The MIPS ABI is set automatically (currently \"%s\").\n",
8694 else if (global_abi
== actual_abi
)
8697 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8701 /* Probably shouldn't happen... */
8702 fprintf_filtered (file
,
8703 "The (auto detected) MIPS ABI \"%s\" is in use "
8704 "even though the user setting was \"%s\".\n",
8705 actual_abi_str
, mips_abi_strings
[global_abi
]);
8710 /* Print out which MIPS compressed ISA encoding is used. */
8713 show_mips_compression (struct ui_file
*file
, int from_tty
,
8714 struct cmd_list_element
*c
, const char *value
)
8716 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8721 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8727 int ef_mips_32bitmode
;
8728 /* Determine the ISA. */
8729 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8747 /* Determine the size of a pointer. */
8748 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8749 fprintf_unfiltered (file
,
8750 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8752 fprintf_unfiltered (file
,
8753 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8755 fprintf_unfiltered (file
,
8756 "mips_dump_tdep: ef_mips_arch = %d\n",
8758 fprintf_unfiltered (file
,
8759 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8760 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8761 fprintf_unfiltered (file
,
8763 "mips_mask_address_p() %d (default %d)\n",
8764 mips_mask_address_p (tdep
),
8765 tdep
->default_mask_address_p
);
8767 fprintf_unfiltered (file
,
8768 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8769 MIPS_DEFAULT_FPU_TYPE
,
8770 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8771 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8772 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8774 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8775 MIPS_EABI (gdbarch
));
8776 fprintf_unfiltered (file
,
8777 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8778 MIPS_FPU_TYPE (gdbarch
),
8779 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8780 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8781 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8785 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8788 _initialize_mips_tdep (void)
8790 static struct cmd_list_element
*mipsfpulist
= NULL
;
8791 struct cmd_list_element
*c
;
8793 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8794 if (MIPS_ABI_LAST
+ 1
8795 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8796 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8798 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8800 mips_pdr_data
= register_objfile_data ();
8802 /* Create feature sets with the appropriate properties. The values
8803 are not important. */
8804 mips_tdesc_gp32
= allocate_target_description ();
8805 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8807 mips_tdesc_gp64
= allocate_target_description ();
8808 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8810 /* Add root prefix command for all "set mips"/"show mips" commands. */
8811 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8812 _("Various MIPS specific commands."),
8813 &setmipscmdlist
, "set mips ", 0, &setlist
);
8815 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8816 _("Various MIPS specific commands."),
8817 &showmipscmdlist
, "show mips ", 0, &showlist
);
8819 /* Allow the user to override the ABI. */
8820 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8821 &mips_abi_string
, _("\
8822 Set the MIPS ABI used by this program."), _("\
8823 Show the MIPS ABI used by this program."), _("\
8824 This option can be set to one of:\n\
8825 auto - the default ABI associated with the current binary\n\
8834 &setmipscmdlist
, &showmipscmdlist
);
8836 /* Allow the user to set the ISA to assume for compressed code if ELF
8837 file flags don't tell or there is no program file selected. This
8838 setting is updated whenever unambiguous ELF file flags are interpreted,
8839 and carried over to subsequent sessions. */
8840 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8841 &mips_compression_string
, _("\
8842 Set the compressed ISA encoding used by MIPS code."), _("\
8843 Show the compressed ISA encoding used by MIPS code."), _("\
8844 Select the compressed ISA encoding used in functions that have no symbol\n\
8845 information available. The encoding can be set to either of:\n\
8848 and is updated automatically from ELF file flags if available."),
8850 show_mips_compression
,
8851 &setmipscmdlist
, &showmipscmdlist
);
8853 /* Let the user turn off floating point and set the fence post for
8854 heuristic_proc_start. */
8856 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
8857 _("Set use of MIPS floating-point coprocessor."),
8858 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8859 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8860 _("Select single-precision MIPS floating-point coprocessor."),
8862 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8863 _("Select double-precision MIPS floating-point coprocessor."),
8865 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
8866 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
8867 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
8868 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
8869 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
8870 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
8871 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
8872 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
8873 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
8874 _("Select MIPS floating-point coprocessor automatically."),
8876 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
8877 _("Show current use of MIPS floating-point coprocessor target."),
8880 /* We really would like to have both "0" and "unlimited" work, but
8881 command.c doesn't deal with that. So make it a var_zinteger
8882 because the user can always use "999999" or some such for unlimited. */
8883 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
8884 &heuristic_fence_post
, _("\
8885 Set the distance searched for the start of a function."), _("\
8886 Show the distance searched for the start of a function."), _("\
8887 If you are debugging a stripped executable, GDB needs to search through the\n\
8888 program for the start of a function. This command sets the distance of the\n\
8889 search. The only need to set it is when debugging a stripped executable."),
8890 reinit_frame_cache_sfunc
,
8891 NULL
, /* FIXME: i18n: The distance searched for
8892 the start of a function is %s. */
8893 &setlist
, &showlist
);
8895 /* Allow the user to control whether the upper bits of 64-bit
8896 addresses should be zeroed. */
8897 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
8898 &mask_address_var
, _("\
8899 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8900 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8901 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8902 allow GDB to determine the correct value."),
8903 NULL
, show_mask_address
,
8904 &setmipscmdlist
, &showmipscmdlist
);
8906 /* Allow the user to control the size of 32 bit registers within the
8907 raw remote packet. */
8908 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
8909 &mips64_transfers_32bit_regs_p
, _("\
8910 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8912 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8914 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8915 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8916 64 bits for others. Use \"off\" to disable compatibility mode"),
8917 set_mips64_transfers_32bit_regs
,
8918 NULL
, /* FIXME: i18n: Compatibility with 64-bit
8919 MIPS target that transfers 32-bit
8920 quantities is %s. */
8921 &setlist
, &showlist
);
8923 /* Debug this files internals. */
8924 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
8926 Set mips debugging."), _("\
8927 Show mips debugging."), _("\
8928 When non-zero, mips specific debugging is enabled."),
8930 NULL
, /* FIXME: i18n: Mips debugging is
8932 &setdebuglist
, &showdebuglist
);