1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
54 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE
= 4,
65 MIPS_FPU_DOUBLE_REGSIZE
= 8
69 static const char *mips_abi_string
;
71 static const char *mips_abi_strings
[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc
;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto
[] = "auto";
93 static const char size_32
[] = "32";
94 static const char size_64
[] = "64";
96 static const char *size_enums
[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int mips_default_saved_regsize
;
135 int mips_fp_register_double
;
136 int mips_default_stack_argsize
;
137 int gdb_target_is_mips64
;
138 int default_mask_address_p
;
141 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
142 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
144 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
146 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
148 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
150 /* Return the currently configured (or set) saved register size. */
152 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
154 static const char *mips_saved_regsize_string
= size_auto
;
156 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
158 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
159 functions to test, set, or clear bit 0 of addresses. */
162 is_mips16_addr (CORE_ADDR addr
)
168 make_mips16_addr (CORE_ADDR addr
)
174 unmake_mips16_addr (CORE_ADDR addr
)
176 return ((addr
) & ~1);
179 /* Return the contents of register REGNUM as a signed integer. */
182 read_signed_register (int regnum
)
184 void *buf
= alloca (DEPRECATED_REGISTER_RAW_SIZE (regnum
));
185 deprecated_read_register_gen (regnum
, buf
);
186 return (extract_signed_integer (buf
, DEPRECATED_REGISTER_RAW_SIZE (regnum
)));
190 read_signed_register_pid (int regnum
, ptid_t ptid
)
195 if (ptid_equal (ptid
, inferior_ptid
))
196 return read_signed_register (regnum
);
198 save_ptid
= inferior_ptid
;
200 inferior_ptid
= ptid
;
202 retval
= read_signed_register (regnum
);
204 inferior_ptid
= save_ptid
;
209 /* Return the MIPS ABI associated with GDBARCH. */
211 mips_abi (struct gdbarch
*gdbarch
)
213 return gdbarch_tdep (gdbarch
)->mips_abi
;
217 mips_regsize (struct gdbarch
*gdbarch
)
219 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
220 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
224 mips_saved_regsize (void)
226 if (mips_saved_regsize_string
== size_auto
)
227 return MIPS_DEFAULT_SAVED_REGSIZE
;
228 else if (mips_saved_regsize_string
== size_64
)
230 else /* if (mips_saved_regsize_string == size_32) */
234 /* Functions for setting and testing a bit in a minimal symbol that
235 marks it as 16-bit function. The MSB of the minimal symbol's
236 "info" field is used for this purpose.
238 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
239 i.e. refers to a 16-bit function, and sets a "special" bit in a
240 minimal symbol to mark it as a 16-bit function
242 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
245 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
247 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
249 MSYMBOL_INFO (msym
) = (char *)
250 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
251 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
256 msymbol_is_special (struct minimal_symbol
*msym
)
258 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
261 /* XFER a value from the big/little/left end of the register.
262 Depending on the size of the value it might occupy the entire
263 register or just part of it. Make an allowance for this, aligning
264 things accordingly. */
267 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
268 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
271 bfd_byte reg
[MAX_REGISTER_SIZE
];
273 gdb_assert (reg_num
>= NUM_REGS
);
274 /* Need to transfer the left or right part of the register, based on
275 the targets byte order. */
279 reg_offset
= DEPRECATED_REGISTER_RAW_SIZE (reg_num
) - length
;
281 case BFD_ENDIAN_LITTLE
:
284 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
288 internal_error (__FILE__
, __LINE__
, "bad switch");
291 fprintf_unfiltered (gdb_stderr
,
292 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
293 reg_num
, reg_offset
, buf_offset
, length
);
294 if (mips_debug
&& out
!= NULL
)
297 fprintf_unfiltered (gdb_stdlog
, "out ");
298 for (i
= 0; i
< length
; i
++)
299 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
302 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
304 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
305 if (mips_debug
&& in
!= NULL
)
308 fprintf_unfiltered (gdb_stdlog
, "in ");
309 for (i
= 0; i
< length
; i
++)
310 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
313 fprintf_unfiltered (gdb_stdlog
, "\n");
316 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
317 compatiblity mode. A return value of 1 means that we have
318 physical 64-bit registers, but should treat them as 32-bit registers. */
321 mips2_fp_compat (void)
323 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
325 if (DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
329 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
330 in all the places we deal with FP registers. PR gdb/413. */
331 /* Otherwise check the FR bit in the status register - it controls
332 the FP compatiblity mode. If it is clear we are in compatibility
334 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
341 /* Indicate that the ABI makes use of double-precision registers
342 provided by the FPU (rather than combining pairs of registers to
343 form double-precision values). Do not use "TARGET_IS_MIPS64" to
344 determine if the ABI is using double-precision registers. See also
346 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
348 /* The amount of space reserved on the stack for registers. This is
349 different to MIPS_SAVED_REGSIZE as it determines the alignment of
350 data allocated after the registers have run out. */
352 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
354 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
356 static const char *mips_stack_argsize_string
= size_auto
;
359 mips_stack_argsize (void)
361 if (mips_stack_argsize_string
== size_auto
)
362 return MIPS_DEFAULT_STACK_ARGSIZE
;
363 else if (mips_stack_argsize_string
== size_64
)
365 else /* if (mips_stack_argsize_string == size_32) */
369 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
371 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
373 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
375 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
376 struct frame_info
*, int);
378 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
380 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
382 static int mips_set_processor_type (char *);
384 static void mips_show_processor_type_command (char *, int);
386 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
388 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
389 struct frame_info
*next_frame
,
392 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
393 mips_extra_func_info_t proc_desc
);
395 static struct type
*mips_float_register_type (void);
396 static struct type
*mips_double_register_type (void);
398 /* This value is the model of MIPS in use. It is derived from the value
399 of the PrID register. */
401 char *mips_processor_type
;
403 char *tmp_mips_processor_type
;
405 /* The list of available "set mips " and "show mips " commands */
407 static struct cmd_list_element
*setmipscmdlist
= NULL
;
408 static struct cmd_list_element
*showmipscmdlist
= NULL
;
410 /* A set of original names, to be used when restoring back to generic
411 registers from a specific set. */
412 static char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
414 /* Integer registers 0 thru 31 are handled explicitly by
415 mips_register_name(). Processor specific registers 32 and above
416 are listed in the sets of register names assigned to
417 mips_processor_reg_names. */
418 static char **mips_processor_reg_names
= mips_generic_reg_names
;
420 /* Return the name of the register corresponding to REGNO. */
422 mips_register_name (int regno
)
424 /* GPR names for all ABIs other than n32/n64. */
425 static char *mips_gpr_names
[] = {
426 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
427 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
428 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
429 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
432 /* GPR names for n32 and n64 ABIs. */
433 static char *mips_n32_n64_gpr_names
[] = {
434 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
435 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
436 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
437 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
440 enum mips_abi abi
= mips_abi (current_gdbarch
);
442 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
443 don't make the raw register names visible. */
444 int rawnum
= regno
% NUM_REGS
;
445 if (regno
< NUM_REGS
)
448 /* The MIPS integer registers are always mapped from 0 to 31. The
449 names of the registers (which reflects the conventions regarding
450 register use) vary depending on the ABI. */
451 if (0 <= rawnum
&& rawnum
< 32)
453 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
454 return mips_n32_n64_gpr_names
[rawnum
];
456 return mips_gpr_names
[rawnum
];
458 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
459 return mips_processor_reg_names
[rawnum
- 32];
461 internal_error (__FILE__
, __LINE__
,
462 "mips_register_name: bad register number %d", rawnum
);
466 /* Names of IDT R3041 registers. */
468 char *mips_r3041_reg_names
[] = {
469 "sr", "lo", "hi", "bad", "cause","pc",
470 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
471 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
472 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
473 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
474 "fsr", "fir", "",/*"fp"*/ "",
475 "", "", "bus", "ccfg", "", "", "", "",
476 "", "", "port", "cmp", "", "", "epc", "prid",
479 /* Names of IDT R3051 registers. */
481 char *mips_r3051_reg_names
[] = {
482 "sr", "lo", "hi", "bad", "cause","pc",
483 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
484 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
485 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
486 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
487 "fsr", "fir", ""/*"fp"*/, "",
488 "inx", "rand", "elo", "", "ctxt", "", "", "",
489 "", "", "ehi", "", "", "", "epc", "prid",
492 /* Names of IDT R3081 registers. */
494 char *mips_r3081_reg_names
[] = {
495 "sr", "lo", "hi", "bad", "cause","pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
500 "fsr", "fir", ""/*"fp"*/, "",
501 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
502 "", "", "ehi", "", "", "", "epc", "prid",
505 /* Names of LSI 33k registers. */
507 char *mips_lsi33k_reg_names
[] = {
508 "epc", "hi", "lo", "sr", "cause","badvaddr",
509 "dcic", "bpc", "bda", "", "", "", "", "",
510 "", "", "", "", "", "", "", "",
511 "", "", "", "", "", "", "", "",
512 "", "", "", "", "", "", "", "",
514 "", "", "", "", "", "", "", "",
515 "", "", "", "", "", "", "", "",
521 } mips_processor_type_table
[] = {
522 { "generic", mips_generic_reg_names
},
523 { "r3041", mips_r3041_reg_names
},
524 { "r3051", mips_r3051_reg_names
},
525 { "r3071", mips_r3081_reg_names
},
526 { "r3081", mips_r3081_reg_names
},
527 { "lsi33k", mips_lsi33k_reg_names
},
532 /* Return the groups that a MIPS register can be categorised into. */
535 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
536 struct reggroup
*reggroup
)
541 int rawnum
= regnum
% NUM_REGS
;
542 int pseudo
= regnum
/ NUM_REGS
;
543 if (reggroup
== all_reggroup
)
545 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
546 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
547 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
548 (gdbarch), as not all architectures are multi-arch. */
549 raw_p
= rawnum
< NUM_REGS
;
550 if (REGISTER_NAME (regnum
) == NULL
551 || REGISTER_NAME (regnum
)[0] == '\0')
553 if (reggroup
== float_reggroup
)
554 return float_p
&& pseudo
;
555 if (reggroup
== vector_reggroup
)
556 return vector_p
&& pseudo
;
557 if (reggroup
== general_reggroup
)
558 return (!vector_p
&& !float_p
) && pseudo
;
559 /* Save the pseudo registers. Need to make certain that any code
560 extracting register values from a saved register cache also uses
562 if (reggroup
== save_reggroup
)
563 return raw_p
&& pseudo
;
564 /* Restore the same pseudo register. */
565 if (reggroup
== restore_reggroup
)
566 return raw_p
&& pseudo
;
570 /* Map the symbol table registers which live in the range [1 *
571 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
575 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
576 int cookednum
, void *buf
)
578 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
579 return regcache_raw_read (regcache
, cookednum
% NUM_REGS
, buf
);
583 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
584 int cookednum
, const void *buf
)
586 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
587 return regcache_raw_write (regcache
, cookednum
% NUM_REGS
, buf
);
590 /* Table to translate MIPS16 register field to actual register number. */
591 static int mips16_to_32_reg
[8] =
592 {16, 17, 2, 3, 4, 5, 6, 7};
594 /* Heuristic_proc_start may hunt through the text section for a long
595 time across a 2400 baud serial line. Allows the user to limit this
598 static unsigned int heuristic_fence_post
= 0;
600 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
601 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
602 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
603 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
604 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
605 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
606 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
607 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
608 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
609 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
610 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
611 this will corrupt pdr.iline. Fortunately we don't use it. */
612 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
613 #define _PROC_MAGIC_ 0x0F0F0F0F
614 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
615 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
617 struct linked_proc_info
619 struct mips_extra_func_info info
;
620 struct linked_proc_info
*next
;
622 *linked_proc_desc_table
= NULL
;
624 /* Number of bytes of storage in the actual machine representation for
625 register N. NOTE: This indirectly defines the register size
626 transfered by the GDB protocol. */
628 static int mips64_transfers_32bit_regs_p
= 0;
631 mips_register_raw_size (int regnum
)
633 gdb_assert (regnum
>= 0);
634 if (regnum
< NUM_REGS
)
636 /* For compatibility with old code, implemnt the broken register raw
637 size map for the raw registers.
639 NOTE: cagney/2003-06-15: This is so bogus. The register's
640 raw size is changing according to the ABI
641 (FP_REGISTER_DOUBLE). Also, GDB's protocol is defined by a
642 combination of DEPRECATED_REGISTER_RAW_SIZE and DEPRECATED_REGISTER_BYTE. */
643 if (mips64_transfers_32bit_regs_p
)
644 return DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
645 else if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32
646 && FP_REGISTER_DOUBLE
)
647 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
651 return mips_regsize (current_gdbarch
);
653 else if (regnum
< 2 * NUM_REGS
)
655 /* For the moment map [NUM_REGS .. 2*NUM_REGS) onto the same raw
656 registers, but always return the virtual size. */
657 int rawnum
= regnum
% NUM_REGS
;
658 return TYPE_LENGTH (gdbarch_register_type (current_gdbarch
, rawnum
));
661 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
664 /* Register offset in a buffer for each register.
666 FIXME: cagney/2003-06-15: This is so bogus. Instead REGISTER_TYPE
667 should strictly return the layout of the buffer. Unfortunately
668 remote.c and the MIPS have come to rely on a custom layout that
669 doesn't 1:1 map onto the register type. */
672 mips_register_byte (int regnum
)
674 gdb_assert (regnum
>= 0);
675 if (regnum
< NUM_REGS
)
676 /* Pick up the relevant per-tm file register byte method. */
677 return MIPS_REGISTER_BYTE (regnum
);
678 else if (regnum
< 2 * NUM_REGS
)
682 /* Start with the end of the raw register buffer - assum that
683 MIPS_REGISTER_BYTE (NUM_REGS) returns that end. */
684 byte
= MIPS_REGISTER_BYTE (NUM_REGS
);
685 /* Add space for all the proceeding registers based on their
687 for (reg
= NUM_REGS
; reg
< regnum
; reg
++)
688 byte
+= TYPE_LENGTH (gdbarch_register_type (current_gdbarch
,
693 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
696 /* Convert between RAW and VIRTUAL registers. The RAW register size
697 defines the remote-gdb packet. */
700 mips_register_convertible (int reg_nr
)
702 if (mips64_transfers_32bit_regs_p
)
705 return (DEPRECATED_REGISTER_RAW_SIZE (reg_nr
) > DEPRECATED_REGISTER_VIRTUAL_SIZE (reg_nr
));
709 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
710 char *raw_buf
, char *virt_buf
)
712 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
714 raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
715 TYPE_LENGTH (virtual_type
));
719 TYPE_LENGTH (virtual_type
));
723 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
724 const char *virt_buf
, char *raw_buf
)
726 memset (raw_buf
, 0, DEPRECATED_REGISTER_RAW_SIZE (n
));
727 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
728 memcpy (raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
730 TYPE_LENGTH (virtual_type
));
734 TYPE_LENGTH (virtual_type
));
738 mips_convert_register_p (int regnum
, struct type
*type
)
740 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
741 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4
742 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
743 && TYPE_CODE(type
) == TYPE_CODE_FLT
744 && TYPE_LENGTH(type
) == 8);
748 mips_register_to_value (struct frame_info
*frame
, int regnum
,
749 struct type
*type
, void *to
)
751 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
752 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
756 mips_value_to_register (struct frame_info
*frame
, int regnum
,
757 struct type
*type
, const void *from
)
759 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
760 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
763 /* Return the GDB type object for the "standard" data type of data in
767 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
769 /* For moment, map [NUM_REGS .. 2*NUM_REGS) onto the same raw
770 registers. Even return the same type. */
771 int rawnum
= regnum
% NUM_REGS
;
772 gdb_assert (rawnum
>= 0 && rawnum
< NUM_REGS
);
773 #ifdef MIPS_REGISTER_TYPE
774 return MIPS_REGISTER_TYPE (rawnum
);
776 if (FP0_REGNUM
<= rawnum
&& rawnum
< FP0_REGNUM
+ 32)
778 /* Floating point registers... */
779 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
780 return builtin_type_ieee_double_big
;
782 return builtin_type_ieee_double_little
;
784 else if (rawnum
== PS_REGNUM
/* CR */)
785 return builtin_type_uint32
;
786 else if (FCRCS_REGNUM
<= rawnum
&& rawnum
<= LAST_EMBED_REGNUM
)
787 return builtin_type_uint32
;
790 /* Everything else...
791 Return type appropriate for width of register. */
792 if (mips_regsize (current_gdbarch
) == TYPE_LENGTH (builtin_type_uint64
))
793 return builtin_type_uint64
;
795 return builtin_type_uint32
;
800 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
805 return read_signed_register (SP_REGNUM
);
808 /* Should the upper word of 64-bit addresses be zeroed? */
809 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
812 mips_mask_address_p (void)
814 switch (mask_address_var
)
816 case AUTO_BOOLEAN_TRUE
:
818 case AUTO_BOOLEAN_FALSE
:
821 case AUTO_BOOLEAN_AUTO
:
822 return MIPS_DEFAULT_MASK_ADDRESS_P
;
824 internal_error (__FILE__
, __LINE__
,
825 "mips_mask_address_p: bad switch");
831 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
833 switch (mask_address_var
)
835 case AUTO_BOOLEAN_TRUE
:
836 printf_filtered ("The 32 bit mips address mask is enabled\n");
838 case AUTO_BOOLEAN_FALSE
:
839 printf_filtered ("The 32 bit mips address mask is disabled\n");
841 case AUTO_BOOLEAN_AUTO
:
842 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
843 mips_mask_address_p () ? "enabled" : "disabled");
846 internal_error (__FILE__
, __LINE__
,
847 "show_mask_address: bad switch");
852 /* Should call_function allocate stack space for a struct return? */
855 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
857 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
861 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
863 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
866 /* Should call_function pass struct by reference?
867 For each architecture, structs are passed either by
868 value or by reference, depending on their size. */
871 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
873 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
874 int len
= TYPE_LENGTH (check_typedef (type
));
876 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
877 return (len
> MIPS_SAVED_REGSIZE
);
883 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
885 return 0; /* Assumption: N32/N64 never passes struct by ref. */
889 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
891 return 0; /* Assumption: O32/O64 never passes struct by ref. */
894 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
897 pc_is_mips16 (bfd_vma memaddr
)
899 struct minimal_symbol
*sym
;
901 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
902 if (is_mips16_addr (memaddr
))
905 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
906 the high bit of the info field. Use this to decide if the function is
907 MIPS16 or normal MIPS. */
908 sym
= lookup_minimal_symbol_by_pc (memaddr
);
910 return msymbol_is_special (sym
);
915 /* MIPS believes that the PC has a sign extended value. Perhaphs the
916 all registers should be sign extended for simplicity? */
919 mips_read_pc (ptid_t ptid
)
921 return read_signed_register_pid (PC_REGNUM
, ptid
);
924 /* This returns the PC of the first inst after the prologue. If we can't
925 find the prologue, then return 0. */
928 after_prologue (CORE_ADDR pc
,
929 mips_extra_func_info_t proc_desc
)
931 struct symtab_and_line sal
;
932 CORE_ADDR func_addr
, func_end
;
934 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
935 to read the stack pointer from the current machine state, because
936 the current machine state has nothing to do with the information
937 we need from the proc_desc; and the process may or may not exist
940 proc_desc
= find_proc_desc (pc
, NULL
, 0);
944 /* If function is frameless, then we need to do it the hard way. I
945 strongly suspect that frameless always means prologueless... */
946 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
947 && PROC_FRAME_OFFSET (proc_desc
) == 0)
951 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
952 return 0; /* Unknown */
954 sal
= find_pc_line (func_addr
, 0);
956 if (sal
.end
< func_end
)
959 /* The line after the prologue is after the end of the function. In this
960 case, tell the caller to find the prologue the hard way. */
965 /* Decode a MIPS32 instruction that saves a register in the stack, and
966 set the appropriate bit in the general register mask or float register mask
967 to indicate which register is saved. This is a helper function
968 for mips_find_saved_regs. */
971 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
972 unsigned long *float_mask
)
976 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
977 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
978 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
980 /* It might be possible to use the instruction to
981 find the offset, rather than the code below which
982 is based on things being in a certain order in the
983 frame, but figuring out what the instruction's offset
984 is relative to might be a little tricky. */
985 reg
= (inst
& 0x001f0000) >> 16;
986 *gen_mask
|= (1 << reg
);
988 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
989 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
990 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
993 reg
= ((inst
& 0x001f0000) >> 16);
994 *float_mask
|= (1 << reg
);
998 /* Decode a MIPS16 instruction that saves a register in the stack, and
999 set the appropriate bit in the general register or float register mask
1000 to indicate which register is saved. This is a helper function
1001 for mips_find_saved_regs. */
1004 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
1006 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1008 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1009 *gen_mask
|= (1 << reg
);
1011 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1013 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1014 *gen_mask
|= (1 << reg
);
1016 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1017 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1018 *gen_mask
|= (1 << RA_REGNUM
);
1022 /* Fetch and return instruction from the specified location. If the PC
1023 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1026 mips_fetch_instruction (CORE_ADDR addr
)
1028 char buf
[MIPS_INSTLEN
];
1032 if (pc_is_mips16 (addr
))
1034 instlen
= MIPS16_INSTLEN
;
1035 addr
= unmake_mips16_addr (addr
);
1038 instlen
= MIPS_INSTLEN
;
1039 status
= read_memory_nobpt (addr
, buf
, instlen
);
1041 memory_error (status
, addr
);
1042 return extract_unsigned_integer (buf
, instlen
);
1046 /* These the fields of 32 bit mips instructions */
1047 #define mips32_op(x) (x >> 26)
1048 #define itype_op(x) (x >> 26)
1049 #define itype_rs(x) ((x >> 21) & 0x1f)
1050 #define itype_rt(x) ((x >> 16) & 0x1f)
1051 #define itype_immediate(x) (x & 0xffff)
1053 #define jtype_op(x) (x >> 26)
1054 #define jtype_target(x) (x & 0x03ffffff)
1056 #define rtype_op(x) (x >> 26)
1057 #define rtype_rs(x) ((x >> 21) & 0x1f)
1058 #define rtype_rt(x) ((x >> 16) & 0x1f)
1059 #define rtype_rd(x) ((x >> 11) & 0x1f)
1060 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1061 #define rtype_funct(x) (x & 0x3f)
1064 mips32_relative_offset (unsigned long inst
)
1067 x
= itype_immediate (inst
);
1068 if (x
& 0x8000) /* sign bit set */
1070 x
|= 0xffff0000; /* sign extension */
1076 /* Determine whate to set a single step breakpoint while considering
1077 branch prediction */
1079 mips32_next_pc (CORE_ADDR pc
)
1083 inst
= mips_fetch_instruction (pc
);
1084 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1086 if (itype_op (inst
) >> 2 == 5)
1087 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1089 op
= (itype_op (inst
) & 0x03);
1099 goto greater_branch
;
1104 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1105 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1107 int tf
= itype_rt (inst
) & 0x01;
1108 int cnum
= itype_rt (inst
) >> 2;
1109 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
1110 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1112 if (((cond
>> cnum
) & 0x01) == tf
)
1113 pc
+= mips32_relative_offset (inst
) + 4;
1118 pc
+= 4; /* Not a branch, next instruction is easy */
1121 { /* This gets way messy */
1123 /* Further subdivide into SPECIAL, REGIMM and other */
1124 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1126 case 0: /* SPECIAL */
1127 op
= rtype_funct (inst
);
1132 /* Set PC to that address */
1133 pc
= read_signed_register (rtype_rs (inst
));
1139 break; /* end SPECIAL */
1140 case 1: /* REGIMM */
1142 op
= itype_rt (inst
); /* branch condition */
1147 case 16: /* BLTZAL */
1148 case 18: /* BLTZALL */
1150 if (read_signed_register (itype_rs (inst
)) < 0)
1151 pc
+= mips32_relative_offset (inst
) + 4;
1153 pc
+= 8; /* after the delay slot */
1157 case 17: /* BGEZAL */
1158 case 19: /* BGEZALL */
1159 greater_equal_branch
:
1160 if (read_signed_register (itype_rs (inst
)) >= 0)
1161 pc
+= mips32_relative_offset (inst
) + 4;
1163 pc
+= 8; /* after the delay slot */
1165 /* All of the other instructions in the REGIMM category */
1170 break; /* end REGIMM */
1175 reg
= jtype_target (inst
) << 2;
1176 /* Upper four bits get never changed... */
1177 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1180 /* FIXME case JALX : */
1183 reg
= jtype_target (inst
) << 2;
1184 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1185 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1187 break; /* The new PC will be alternate mode */
1188 case 4: /* BEQ, BEQL */
1190 if (read_signed_register (itype_rs (inst
)) ==
1191 read_signed_register (itype_rt (inst
)))
1192 pc
+= mips32_relative_offset (inst
) + 4;
1196 case 5: /* BNE, BNEL */
1198 if (read_signed_register (itype_rs (inst
)) !=
1199 read_signed_register (itype_rt (inst
)))
1200 pc
+= mips32_relative_offset (inst
) + 4;
1204 case 6: /* BLEZ, BLEZL */
1206 if (read_signed_register (itype_rs (inst
) <= 0))
1207 pc
+= mips32_relative_offset (inst
) + 4;
1213 greater_branch
: /* BGTZ, BGTZL */
1214 if (read_signed_register (itype_rs (inst
) > 0))
1215 pc
+= mips32_relative_offset (inst
) + 4;
1222 } /* mips32_next_pc */
1224 /* Decoding the next place to set a breakpoint is irregular for the
1225 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1226 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1227 We dont want to set a single step instruction on the extend instruction
1231 /* Lots of mips16 instruction formats */
1232 /* Predicting jumps requires itype,ritype,i8type
1233 and their extensions extItype,extritype,extI8type
1235 enum mips16_inst_fmts
1237 itype
, /* 0 immediate 5,10 */
1238 ritype
, /* 1 5,3,8 */
1239 rrtype
, /* 2 5,3,3,5 */
1240 rritype
, /* 3 5,3,3,5 */
1241 rrrtype
, /* 4 5,3,3,3,2 */
1242 rriatype
, /* 5 5,3,3,1,4 */
1243 shifttype
, /* 6 5,3,3,3,2 */
1244 i8type
, /* 7 5,3,8 */
1245 i8movtype
, /* 8 5,3,3,5 */
1246 i8mov32rtype
, /* 9 5,3,5,3 */
1247 i64type
, /* 10 5,3,8 */
1248 ri64type
, /* 11 5,3,3,5 */
1249 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1250 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1251 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1252 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1253 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1254 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1255 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1256 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1257 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1258 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1260 /* I am heaping all the fields of the formats into one structure and
1261 then, only the fields which are involved in instruction extension */
1265 unsigned int regx
; /* Function in i8 type */
1270 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1271 for the bits which make up the immediatate extension. */
1274 extended_offset (unsigned int extension
)
1277 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1279 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1281 value
|= extension
& 0x01f; /* extract 4:0 */
1285 /* Only call this function if you know that this is an extendable
1286 instruction, It wont malfunction, but why make excess remote memory references?
1287 If the immediate operands get sign extended or somthing, do it after
1288 the extension is performed.
1290 /* FIXME: Every one of these cases needs to worry about sign extension
1291 when the offset is to be used in relative addressing */
1295 fetch_mips_16 (CORE_ADDR pc
)
1298 pc
&= 0xfffffffe; /* clear the low order bit */
1299 target_read_memory (pc
, buf
, 2);
1300 return extract_unsigned_integer (buf
, 2);
1304 unpack_mips16 (CORE_ADDR pc
,
1305 unsigned int extension
,
1307 enum mips16_inst_fmts insn_format
,
1308 struct upk_mips16
*upk
)
1313 switch (insn_format
)
1320 value
= extended_offset (extension
);
1321 value
= value
<< 11; /* rom for the original value */
1322 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1326 value
= inst
& 0x7ff;
1327 /* FIXME : Consider sign extension */
1336 { /* A register identifier and an offset */
1337 /* Most of the fields are the same as I type but the
1338 immediate value is of a different length */
1342 value
= extended_offset (extension
);
1343 value
= value
<< 8; /* from the original instruction */
1344 value
|= inst
& 0xff; /* eleven bits from instruction */
1345 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1346 if (value
& 0x4000) /* test the sign bit , bit 26 */
1348 value
&= ~0x3fff; /* remove the sign bit */
1354 value
= inst
& 0xff; /* 8 bits */
1355 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1356 /* FIXME: Do sign extension , this format needs it */
1357 if (value
& 0x80) /* THIS CONFUSES ME */
1359 value
&= 0xef; /* remove the sign bit */
1369 unsigned long value
;
1370 unsigned int nexthalf
;
1371 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1372 value
= value
<< 16;
1373 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1381 internal_error (__FILE__
, __LINE__
,
1384 upk
->offset
= offset
;
1391 add_offset_16 (CORE_ADDR pc
, int offset
)
1393 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1397 extended_mips16_next_pc (CORE_ADDR pc
,
1398 unsigned int extension
,
1401 int op
= (insn
>> 11);
1404 case 2: /* Branch */
1407 struct upk_mips16 upk
;
1408 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1409 offset
= upk
.offset
;
1415 pc
+= (offset
<< 1) + 2;
1418 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1420 struct upk_mips16 upk
;
1421 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1422 pc
= add_offset_16 (pc
, upk
.offset
);
1423 if ((insn
>> 10) & 0x01) /* Exchange mode */
1424 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1431 struct upk_mips16 upk
;
1433 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1434 reg
= read_signed_register (upk
.regx
);
1436 pc
+= (upk
.offset
<< 1) + 2;
1443 struct upk_mips16 upk
;
1445 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1446 reg
= read_signed_register (upk
.regx
);
1448 pc
+= (upk
.offset
<< 1) + 2;
1453 case 12: /* I8 Formats btez btnez */
1455 struct upk_mips16 upk
;
1457 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1458 /* upk.regx contains the opcode */
1459 reg
= read_signed_register (24); /* Test register is 24 */
1460 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1461 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1462 /* pc = add_offset_16(pc,upk.offset) ; */
1463 pc
+= (upk
.offset
<< 1) + 2;
1468 case 29: /* RR Formats JR, JALR, JALR-RA */
1470 struct upk_mips16 upk
;
1471 /* upk.fmt = rrtype; */
1476 upk
.regx
= (insn
>> 8) & 0x07;
1477 upk
.regy
= (insn
>> 5) & 0x07;
1485 break; /* Function return instruction */
1491 break; /* BOGUS Guess */
1493 pc
= read_signed_register (reg
);
1500 /* This is an instruction extension. Fetch the real instruction
1501 (which follows the extension) and decode things based on
1505 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1518 mips16_next_pc (CORE_ADDR pc
)
1520 unsigned int insn
= fetch_mips_16 (pc
);
1521 return extended_mips16_next_pc (pc
, 0, insn
);
1524 /* The mips_next_pc function supports single_step when the remote
1525 target monitor or stub is not developed enough to do a single_step.
1526 It works by decoding the current instruction and predicting where a
1527 branch will go. This isnt hard because all the data is available.
1528 The MIPS32 and MIPS16 variants are quite different */
1530 mips_next_pc (CORE_ADDR pc
)
1533 return mips16_next_pc (pc
);
1535 return mips32_next_pc (pc
);
1538 /* Set up the 'saved_regs' array. This is a data structure containing
1539 the addresses on the stack where each register has been saved, for
1540 each stack frame. Registers that have not been saved will have
1541 zero here. The stack pointer register is special: rather than the
1542 address where the stack register has been saved,
1543 saved_regs[SP_REGNUM] will have the actual value of the previous
1544 frame's stack register. */
1547 mips_find_saved_regs (struct frame_info
*fci
)
1550 /* r0 bit means kernel trap */
1552 /* What registers have been saved? Bitmasks. */
1553 unsigned long gen_mask
, float_mask
;
1554 mips_extra_func_info_t proc_desc
;
1556 CORE_ADDR
*saved_regs
;
1558 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1560 saved_regs
= frame_saved_regs_zalloc (fci
);
1562 /* If it is the frame for sigtramp, the saved registers are located
1563 in a sigcontext structure somewhere on the stack. If the stack
1564 layout for sigtramp changes we might have to change these
1565 constants and the companion fixup_sigtramp in mdebugread.c */
1566 #ifndef SIGFRAME_BASE
1567 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1568 above the sigtramp frame. */
1569 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1570 /* FIXME! Are these correct?? */
1571 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1572 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1573 #define SIGFRAME_FPREGSAVE_OFF \
1574 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1576 #ifndef SIGFRAME_REG_SIZE
1577 /* FIXME! Is this correct?? */
1578 #define SIGFRAME_REG_SIZE mips_regsize (current_gdbarch)
1580 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1582 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1584 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1585 + ireg
* SIGFRAME_REG_SIZE
);
1586 set_reg_offset (saved_regs
, ireg
, reg_position
);
1588 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1590 CORE_ADDR reg_position
= (get_frame_base (fci
)
1591 + SIGFRAME_FPREGSAVE_OFF
1592 + ireg
* SIGFRAME_REG_SIZE
);
1593 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1596 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1597 /* SP_REGNUM, contains the value and not the address. */
1598 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1602 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1603 if (proc_desc
== NULL
)
1604 /* I'm not sure how/whether this can happen. Normally when we
1605 can't find a proc_desc, we "synthesize" one using
1606 heuristic_proc_desc and set the saved_regs right away. */
1609 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1610 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1611 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1613 if (/* In any frame other than the innermost or a frame interrupted
1614 by a signal, we assume that all registers have been saved.
1615 This assumes that all register saves in a function happen
1616 before the first function call. */
1617 (get_next_frame (fci
) == NULL
1618 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1620 /* In a dummy frame we know exactly where things are saved. */
1621 && !PROC_DESC_IS_DUMMY (proc_desc
)
1623 /* Don't bother unless we are inside a function prologue.
1624 Outside the prologue, we know where everything is. */
1626 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1628 /* Not sure exactly what kernel_trap means, but if it means the
1629 kernel saves the registers without a prologue doing it, we
1630 better not examine the prologue to see whether registers
1631 have been saved yet. */
1634 /* We need to figure out whether the registers that the
1635 proc_desc claims are saved have been saved yet. */
1639 /* Bitmasks; set if we have found a save for the register. */
1640 unsigned long gen_save_found
= 0;
1641 unsigned long float_save_found
= 0;
1644 /* If the address is odd, assume this is MIPS16 code. */
1645 addr
= PROC_LOW_ADDR (proc_desc
);
1646 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1648 /* Scan through this function's instructions preceding the
1649 current PC, and look for those that save registers. */
1650 while (addr
< get_frame_pc (fci
))
1652 inst
= mips_fetch_instruction (addr
);
1653 if (pc_is_mips16 (addr
))
1654 mips16_decode_reg_save (inst
, &gen_save_found
);
1656 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1659 gen_mask
= gen_save_found
;
1660 float_mask
= float_save_found
;
1663 /* Fill in the offsets for the registers which gen_mask says were
1666 CORE_ADDR reg_position
= (get_frame_base (fci
)
1667 + PROC_REG_OFFSET (proc_desc
));
1668 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1669 if (gen_mask
& 0x80000000)
1671 set_reg_offset (saved_regs
, ireg
, reg_position
);
1672 reg_position
-= MIPS_SAVED_REGSIZE
;
1676 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1677 order of that normally used by gcc. Therefore, we have to fetch
1678 the first instruction of the function, and if it's an entry
1679 instruction that saves $s0 or $s1, correct their saved addresses. */
1680 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1682 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1683 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1687 int sreg_count
= (inst
>> 6) & 3;
1689 /* Check if the ra register was pushed on the stack. */
1690 CORE_ADDR reg_position
= (get_frame_base (fci
)
1691 + PROC_REG_OFFSET (proc_desc
));
1693 reg_position
-= MIPS_SAVED_REGSIZE
;
1695 /* Check if the s0 and s1 registers were pushed on the
1697 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1699 set_reg_offset (saved_regs
, reg
, reg_position
);
1700 reg_position
-= MIPS_SAVED_REGSIZE
;
1705 /* Fill in the offsets for the registers which float_mask says were
1708 CORE_ADDR reg_position
= (get_frame_base (fci
)
1709 + PROC_FREG_OFFSET (proc_desc
));
1711 /* Fill in the offsets for the float registers which float_mask
1713 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1714 if (float_mask
& 0x80000000)
1716 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1718 /* On a big endian 32 bit ABI, floating point registers
1719 are paired to form doubles such that the most
1720 significant part is in $f[N+1] and the least
1721 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1722 registers are also spilled as a pair and stored as a
1725 When little-endian the least significant part is
1726 stored first leading to the memory order $f[N] and
1729 Unfortunately, when big-endian the most significant
1730 part of the double is stored first, and the least
1731 significant is stored second. This leads to the
1732 registers being ordered in memory as firt $f[N+1] and
1735 For the big-endian case make certain that the
1736 addresses point at the correct (swapped) locations
1737 $f[N] and $f[N+1] pair (keep in mind that
1738 reg_position is decremented each time through the
1741 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1742 reg_position
- MIPS_SAVED_REGSIZE
);
1744 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1745 reg_position
+ MIPS_SAVED_REGSIZE
);
1748 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1749 reg_position
-= MIPS_SAVED_REGSIZE
;
1752 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1755 /* SP_REGNUM, contains the value and not the address. */
1756 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1760 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1762 /* Always a pseudo. */
1763 gdb_assert (regno
>= NUM_REGS
);
1767 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1770 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1771 /* The SP_REGNUM is special, its value is stored in saved_regs.
1772 In fact, it is so special that it can even only be fetched
1773 using a raw register number! Once this code as been converted
1774 to frame-unwind the problem goes away. */
1775 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1777 return frame_unwind_register_signed (fi
, regno
);
1781 /* mips_addr_bits_remove - remove useless address bits */
1784 mips_addr_bits_remove (CORE_ADDR addr
)
1786 if (GDB_TARGET_IS_MIPS64
)
1788 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1790 /* This hack is a work-around for existing boards using
1791 PMON, the simulator, and any other 64-bit targets that
1792 doesn't have true 64-bit addressing. On these targets,
1793 the upper 32 bits of addresses are ignored by the
1794 hardware. Thus, the PC or SP are likely to have been
1795 sign extended to all 1s by instruction sequences that
1796 load 32-bit addresses. For example, a typical piece of
1797 code that loads an address is this:
1798 lui $r2, <upper 16 bits>
1799 ori $r2, <lower 16 bits>
1800 But the lui sign-extends the value such that the upper 32
1801 bits may be all 1s. The workaround is simply to mask off
1802 these bits. In the future, gcc may be changed to support
1803 true 64-bit addressing, and this masking will have to be
1805 addr
&= (CORE_ADDR
) 0xffffffff;
1808 else if (mips_mask_address_p ())
1810 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1811 masking off bits, instead, the actual target should be asking
1812 for the address to be converted to a valid pointer. */
1813 /* Even when GDB is configured for some 32-bit targets
1814 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1815 so CORE_ADDR is 64 bits. So we still have to mask off
1816 useless bits from addresses. */
1817 addr
&= (CORE_ADDR
) 0xffffffff;
1822 /* mips_software_single_step() is called just before we want to resume
1823 the inferior, if we want to single-step it but there is no hardware
1824 or kernel single-step support (MIPS on GNU/Linux for example). We find
1825 the target of the coming instruction and breakpoint it.
1827 single_step is also called just after the inferior stops. If we had
1828 set up a simulated single-step, we undo our damage. */
1831 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1833 static CORE_ADDR next_pc
;
1834 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1835 static binsn_quantum break_mem
;
1838 if (insert_breakpoints_p
)
1840 pc
= read_register (PC_REGNUM
);
1841 next_pc
= mips_next_pc (pc
);
1843 target_insert_breakpoint (next_pc
, break_mem
);
1846 target_remove_breakpoint (next_pc
, break_mem
);
1850 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1855 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1856 : get_next_frame (prev
)
1857 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1859 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1860 return tmp
? tmp
: pc
;
1865 mips_frame_saved_pc (struct frame_info
*frame
)
1869 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1872 /* Always unwind the cooked PC register value. */
1873 frame_unwind_signed_register (frame
, NUM_REGS
+ PC_REGNUM
, &tmp
);
1878 mips_extra_func_info_t proc_desc
1879 = get_frame_extra_info (frame
)->proc_desc
;
1880 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1881 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1884 /* We have to get the saved pc from the sigcontext if it is
1885 a signal handler frame. */
1886 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1887 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1888 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1891 return ADDR_BITS_REMOVE (saved_pc
);
1894 static struct mips_extra_func_info temp_proc_desc
;
1896 /* This hack will go away once the get_prev_frame() code has been
1897 modified to set the frame's type first. That is BEFORE init extra
1898 frame info et.al. is called. This is because it will become
1899 possible to skip the init extra info call for sigtramp and dummy
1901 static CORE_ADDR
*temp_saved_regs
;
1903 /* Set a register's saved stack address in temp_saved_regs. If an
1904 address has already been set for this register, do nothing; this
1905 way we will only recognize the first save of a given register in a
1908 For simplicity, save the address in both [0 .. NUM_REGS) and
1909 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1910 is used as it is only second range (the ABI instead of ISA
1911 registers) that comes into play when finding saved registers in a
1915 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1917 if (saved_regs
[regno
] == 0)
1919 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1920 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1925 /* Test whether the PC points to the return instruction at the
1926 end of a function. */
1929 mips_about_to_return (CORE_ADDR pc
)
1931 if (pc_is_mips16 (pc
))
1932 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1933 generates a "jr $ra"; other times it generates code to load
1934 the return address from the stack to an accessible register (such
1935 as $a3), then a "jr" using that register. This second case
1936 is almost impossible to distinguish from an indirect jump
1937 used for switch statements, so we don't even try. */
1938 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1940 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1944 /* This fencepost looks highly suspicious to me. Removing it also
1945 seems suspicious as it could affect remote debugging across serial
1949 heuristic_proc_start (CORE_ADDR pc
)
1956 pc
= ADDR_BITS_REMOVE (pc
);
1958 fence
= start_pc
- heuristic_fence_post
;
1962 if (heuristic_fence_post
== UINT_MAX
1963 || fence
< VM_MIN_ADDRESS
)
1964 fence
= VM_MIN_ADDRESS
;
1966 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1968 /* search back for previous return */
1969 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1970 if (start_pc
< fence
)
1972 /* It's not clear to me why we reach this point when
1973 stop_soon, but with this test, at least we
1974 don't print out warnings for every child forked (eg, on
1975 decstation). 22apr93 rich@cygnus.com. */
1976 if (stop_soon
== NO_STOP_QUIETLY
)
1978 static int blurb_printed
= 0;
1980 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1985 /* This actually happens frequently in embedded
1986 development, when you first connect to a board
1987 and your stack pointer and pc are nowhere in
1988 particular. This message needs to give people
1989 in that situation enough information to
1990 determine that it's no big deal. */
1991 printf_filtered ("\n\
1992 GDB is unable to find the start of the function at 0x%s\n\
1993 and thus can't determine the size of that function's stack frame.\n\
1994 This means that GDB may be unable to access that stack frame, or\n\
1995 the frames below it.\n\
1996 This problem is most likely caused by an invalid program counter or\n\
1998 However, if you think GDB should simply search farther back\n\
1999 from 0x%s for code which looks like the beginning of a\n\
2000 function, you can increase the range of the search using the `set\n\
2001 heuristic-fence-post' command.\n",
2002 paddr_nz (pc
), paddr_nz (pc
));
2009 else if (pc_is_mips16 (start_pc
))
2011 unsigned short inst
;
2013 /* On MIPS16, any one of the following is likely to be the
2014 start of a function:
2018 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2019 inst
= mips_fetch_instruction (start_pc
);
2020 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2021 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2022 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2023 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2025 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2026 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2031 else if (mips_about_to_return (start_pc
))
2033 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2040 /* Fetch the immediate value from a MIPS16 instruction.
2041 If the previous instruction was an EXTEND, use it to extend
2042 the upper bits of the immediate value. This is a helper function
2043 for mips16_heuristic_proc_desc. */
2046 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2047 unsigned short inst
, /* current instruction */
2048 int nbits
, /* number of bits in imm field */
2049 int scale
, /* scale factor to be applied to imm */
2050 int is_signed
) /* is the imm field signed? */
2054 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2056 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2057 if (offset
& 0x8000) /* check for negative extend */
2058 offset
= 0 - (0x10000 - (offset
& 0xffff));
2059 return offset
| (inst
& 0x1f);
2063 int max_imm
= 1 << nbits
;
2064 int mask
= max_imm
- 1;
2065 int sign_bit
= max_imm
>> 1;
2067 offset
= inst
& mask
;
2068 if (is_signed
&& (offset
& sign_bit
))
2069 offset
= 0 - (max_imm
- offset
);
2070 return offset
* scale
;
2075 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2076 stream from start_pc to limit_pc. */
2079 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2080 struct frame_info
*next_frame
, CORE_ADDR sp
)
2083 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2084 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2085 unsigned inst
= 0; /* current instruction */
2086 unsigned entry_inst
= 0; /* the entry instruction */
2089 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2090 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2092 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2094 /* Save the previous instruction. If it's an EXTEND, we'll extract
2095 the immediate offset extension from it in mips16_get_imm. */
2098 /* Fetch and decode the instruction. */
2099 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2100 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2101 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2103 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2104 if (offset
< 0) /* negative stack adjustment? */
2105 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2107 /* Exit loop if a positive stack adjustment is found, which
2108 usually means that the stack cleanup code in the function
2109 epilogue is reached. */
2112 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2114 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2115 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2116 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2117 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2119 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2121 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2122 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2123 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2124 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2126 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2128 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2129 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2130 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2132 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2134 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2135 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2136 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2138 else if (inst
== 0x673d) /* move $s1, $sp */
2141 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2143 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2145 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2146 frame_addr
= sp
+ offset
;
2147 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2148 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2150 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2152 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2153 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2154 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2155 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2157 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2159 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2160 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2161 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2162 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2164 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2165 entry_inst
= inst
; /* save for later processing */
2166 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2167 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2170 /* The entry instruction is typically the first instruction in a function,
2171 and it stores registers at offsets relative to the value of the old SP
2172 (before the prologue). But the value of the sp parameter to this
2173 function is the new SP (after the prologue has been executed). So we
2174 can't calculate those offsets until we've seen the entire prologue,
2175 and can calculate what the old SP must have been. */
2176 if (entry_inst
!= 0)
2178 int areg_count
= (entry_inst
>> 8) & 7;
2179 int sreg_count
= (entry_inst
>> 6) & 3;
2181 /* The entry instruction always subtracts 32 from the SP. */
2182 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2184 /* Now we can calculate what the SP must have been at the
2185 start of the function prologue. */
2186 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2188 /* Check if a0-a3 were saved in the caller's argument save area. */
2189 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2191 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2192 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2193 offset
+= MIPS_SAVED_REGSIZE
;
2196 /* Check if the ra register was pushed on the stack. */
2198 if (entry_inst
& 0x20)
2200 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2201 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2202 offset
-= MIPS_SAVED_REGSIZE
;
2205 /* Check if the s0 and s1 registers were pushed on the stack. */
2206 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2208 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2209 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2210 offset
-= MIPS_SAVED_REGSIZE
;
2216 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2217 struct frame_info
*next_frame
, CORE_ADDR sp
)
2220 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2222 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2223 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2224 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2225 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2226 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2228 unsigned long inst
, high_word
, low_word
;
2231 /* Fetch the instruction. */
2232 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2234 /* Save some code by pre-extracting some useful fields. */
2235 high_word
= (inst
>> 16) & 0xffff;
2236 low_word
= inst
& 0xffff;
2237 reg
= high_word
& 0x1f;
2239 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2240 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2241 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2243 if (low_word
& 0x8000) /* negative stack adjustment? */
2244 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2246 /* Exit loop if a positive stack adjustment is found, which
2247 usually means that the stack cleanup code in the function
2248 epilogue is reached. */
2251 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2253 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2254 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2256 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2258 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2259 but the register size used is only 32 bits. Make the address
2260 for the saved register point to the lower 32 bits. */
2261 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2262 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2264 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2266 /* Old gcc frame, r30 is virtual frame pointer. */
2267 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2268 frame_addr
= sp
+ low_word
;
2269 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2271 unsigned alloca_adjust
;
2272 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2273 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2274 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2275 if (alloca_adjust
> 0)
2277 /* FP > SP + frame_size. This may be because
2278 * of an alloca or somethings similar.
2279 * Fix sp to "pre-alloca" value, and try again.
2281 sp
+= alloca_adjust
;
2286 /* move $30,$sp. With different versions of gas this will be either
2287 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2288 Accept any one of these. */
2289 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2291 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2292 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2294 unsigned alloca_adjust
;
2295 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2296 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2297 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2298 if (alloca_adjust
> 0)
2300 /* FP > SP + frame_size. This may be because
2301 * of an alloca or somethings similar.
2302 * Fix sp to "pre-alloca" value, and try again.
2304 sp
+= alloca_adjust
;
2309 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2311 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2312 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2317 static mips_extra_func_info_t
2318 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2319 struct frame_info
*next_frame
, int cur_frame
)
2324 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2330 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2331 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2332 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2333 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2334 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2335 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2337 if (start_pc
+ 200 < limit_pc
)
2338 limit_pc
= start_pc
+ 200;
2339 if (pc_is_mips16 (start_pc
))
2340 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2342 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2343 return &temp_proc_desc
;
2346 struct mips_objfile_private
2352 /* Global used to communicate between non_heuristic_proc_desc and
2353 compare_pdr_entries within qsort (). */
2354 static bfd
*the_bfd
;
2357 compare_pdr_entries (const void *a
, const void *b
)
2359 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2360 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2364 else if (lhs
== rhs
)
2370 static mips_extra_func_info_t
2371 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2373 CORE_ADDR startaddr
;
2374 mips_extra_func_info_t proc_desc
;
2375 struct block
*b
= block_for_pc (pc
);
2377 struct obj_section
*sec
;
2378 struct mips_objfile_private
*priv
;
2380 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2383 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2385 *addrptr
= startaddr
;
2389 sec
= find_pc_section (pc
);
2392 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2394 /* Search the ".pdr" section generated by GAS. This includes most of
2395 the information normally found in ECOFF PDRs. */
2397 the_bfd
= sec
->objfile
->obfd
;
2399 && (the_bfd
->format
== bfd_object
2400 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2401 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2403 /* Right now GAS only outputs the address as a four-byte sequence.
2404 This means that we should not bother with this method on 64-bit
2405 targets (until that is fixed). */
2407 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2408 sizeof (struct mips_objfile_private
));
2410 sec
->objfile
->obj_private
= priv
;
2412 else if (priv
== NULL
)
2416 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2417 sizeof (struct mips_objfile_private
));
2419 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2422 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2423 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2425 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2426 priv
->contents
, 0, priv
->size
);
2428 /* In general, the .pdr section is sorted. However, in the
2429 presence of multiple code sections (and other corner cases)
2430 it can become unsorted. Sort it so that we can use a faster
2432 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2437 sec
->objfile
->obj_private
= priv
;
2441 if (priv
->size
!= 0)
2447 high
= priv
->size
/ 32;
2453 mid
= (low
+ high
) / 2;
2455 ptr
= priv
->contents
+ mid
* 32;
2456 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2457 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2458 SECT_OFF_TEXT (sec
->objfile
));
2459 if (pdr_pc
== startaddr
)
2461 if (pdr_pc
> startaddr
)
2466 while (low
!= high
);
2470 struct symbol
*sym
= find_pc_function (pc
);
2472 /* Fill in what we need of the proc_desc. */
2473 proc_desc
= (mips_extra_func_info_t
)
2474 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2475 sizeof (struct mips_extra_func_info
));
2476 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2478 /* Only used for dummy frames. */
2479 PROC_HIGH_ADDR (proc_desc
) = 0;
2481 PROC_FRAME_OFFSET (proc_desc
)
2482 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2483 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2485 PROC_FRAME_ADJUST (proc_desc
) = 0;
2486 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2488 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2490 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2492 PROC_FREG_OFFSET (proc_desc
)
2493 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2494 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2496 proc_desc
->pdr
.isym
= (long) sym
;
2506 if (startaddr
> BLOCK_START (b
))
2508 /* This is the "pathological" case referred to in a comment in
2509 print_frame_info. It might be better to move this check into
2514 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2516 /* If we never found a PDR for this function in symbol reading, then
2517 examine prologues to find the information. */
2520 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2521 if (PROC_FRAME_REG (proc_desc
) == -1)
2531 static mips_extra_func_info_t
2532 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2534 mips_extra_func_info_t proc_desc
;
2535 CORE_ADDR startaddr
= 0;
2537 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2541 /* IF this is the topmost frame AND
2542 * (this proc does not have debugging information OR
2543 * the PC is in the procedure prologue)
2544 * THEN create a "heuristic" proc_desc (by analyzing
2545 * the actual code) to replace the "official" proc_desc.
2547 if (next_frame
== NULL
)
2549 struct symtab_and_line val
;
2550 struct symbol
*proc_symbol
=
2551 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2555 val
= find_pc_line (BLOCK_START
2556 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2558 val
.pc
= val
.end
? val
.end
: pc
;
2560 if (!proc_symbol
|| pc
< val
.pc
)
2562 mips_extra_func_info_t found_heuristic
=
2563 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2564 pc
, next_frame
, cur_frame
);
2565 if (found_heuristic
)
2566 proc_desc
= found_heuristic
;
2572 /* Is linked_proc_desc_table really necessary? It only seems to be used
2573 by procedure call dummys. However, the procedures being called ought
2574 to have their own proc_descs, and even if they don't,
2575 heuristic_proc_desc knows how to create them! */
2577 struct linked_proc_info
*link
;
2579 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2580 if (PROC_LOW_ADDR (&link
->info
) <= pc
2581 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2585 startaddr
= heuristic_proc_start (pc
);
2588 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2594 get_frame_pointer (struct frame_info
*frame
,
2595 mips_extra_func_info_t proc_desc
)
2597 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2598 + PROC_FRAME_OFFSET (proc_desc
)
2599 - PROC_FRAME_ADJUST (proc_desc
));
2602 static mips_extra_func_info_t cached_proc_desc
;
2605 mips_frame_chain (struct frame_info
*frame
)
2607 mips_extra_func_info_t proc_desc
;
2609 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2611 if (saved_pc
== 0 || deprecated_inside_entry_file (saved_pc
))
2614 /* Check if the PC is inside a call stub. If it is, fetch the
2615 PC of the caller of that stub. */
2616 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2619 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2621 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2622 is well, frame->frame the bottom of the current frame will
2623 contain that value. */
2624 return get_frame_base (frame
);
2627 /* Look up the procedure descriptor for this PC. */
2628 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2632 cached_proc_desc
= proc_desc
;
2634 /* If no frame pointer and frame size is zero, we must be at end
2635 of stack (or otherwise hosed). If we don't check frame size,
2636 we loop forever if we see a zero size frame. */
2637 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2638 && PROC_FRAME_OFFSET (proc_desc
) == 0
2639 /* The previous frame from a sigtramp frame might be frameless
2640 and have frame size zero. */
2641 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2642 /* For a generic dummy frame, let get_frame_pointer() unwind a
2643 register value saved as part of the dummy frame call. */
2644 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2647 return get_frame_pointer (frame
, proc_desc
);
2651 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2654 mips_extra_func_info_t proc_desc
;
2656 if (get_frame_type (fci
) == DUMMY_FRAME
)
2659 /* Use proc_desc calculated in frame_chain. When there is no
2660 next frame, i.e, get_next_frame (fci) == NULL, we call
2661 find_proc_desc () to calculate it, passing an explicit
2662 NULL as the frame parameter. */
2664 get_next_frame (fci
)
2666 : find_proc_desc (get_frame_pc (fci
),
2667 NULL
/* i.e, get_next_frame (fci) */,
2670 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2672 deprecated_set_frame_saved_regs_hack (fci
, NULL
);
2673 get_frame_extra_info (fci
)->proc_desc
=
2674 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2677 /* Fixup frame-pointer - only needed for top frame */
2678 /* This may not be quite right, if proc has a real frame register.
2679 Get the value of the frame relative sp, procedure might have been
2680 interrupted by a signal at it's very start. */
2681 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2682 && !PROC_DESC_IS_DUMMY (proc_desc
))
2683 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2684 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2685 /* Do not ``fix'' fci->frame. It will have the value of the
2686 generic dummy frame's top-of-stack (since the draft
2687 fci->frame is obtained by returning the unwound stack
2688 pointer) and that is what we want. That way the fci->frame
2689 value will match the top-of-stack value that was saved as
2690 part of the dummy frames data. */
2693 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2695 if (proc_desc
== &temp_proc_desc
)
2699 /* Do not set the saved registers for a sigtramp frame,
2700 mips_find_saved_registers will do that for us. We can't
2701 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2703 /* FIXME: cagney/2002-11-18: This problem will go away once
2704 frame.c:get_prev_frame() is modified to set the frame's
2705 type before calling functions like this. */
2706 find_pc_partial_function (get_frame_pc (fci
), &name
,
2707 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2708 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2710 frame_saved_regs_zalloc (fci
);
2711 /* Set value of previous frame's stack pointer.
2712 Remember that saved_regs[SP_REGNUM] is special in
2713 that it contains the value of the stack pointer
2714 register. The other saved_regs values are addresses
2715 (in the inferior) at which a given register's value
2717 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2718 get_frame_base (fci
));
2719 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2720 temp_saved_regs
[RA_REGNUM
]);
2721 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2722 SIZEOF_FRAME_SAVED_REGS
);
2726 /* hack: if argument regs are saved, guess these contain args */
2727 /* assume we can't tell how many args for now */
2728 get_frame_extra_info (fci
)->num_args
= -1;
2729 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2731 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2733 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2740 /* MIPS stack frames are almost impenetrable. When execution stops,
2741 we basically have to look at symbol information for the function
2742 that we stopped in, which tells us *which* register (if any) is
2743 the base of the frame pointer, and what offset from that register
2744 the frame itself is at.
2746 This presents a problem when trying to examine a stack in memory
2747 (that isn't executing at the moment), using the "frame" command. We
2748 don't have a PC, nor do we have any registers except SP.
2750 This routine takes two arguments, SP and PC, and tries to make the
2751 cached frames look as if these two arguments defined a frame on the
2752 cache. This allows the rest of info frame to extract the important
2753 arguments without difficulty. */
2756 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2759 error ("MIPS frame specifications require two arguments: sp and pc");
2761 return create_new_frame (argv
[0], argv
[1]);
2764 /* According to the current ABI, should the type be passed in a
2765 floating-point register (assuming that there is space)? When there
2766 is no FPU, FP are not even considered as possibile candidates for
2767 FP registers and, consequently this returns false - forces FP
2768 arguments into integer registers. */
2771 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2773 return ((typecode
== TYPE_CODE_FLT
2775 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2776 && TYPE_NFIELDS (arg_type
) == 1
2777 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2778 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2781 /* On o32, argument passing in GPRs depends on the alignment of the type being
2782 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2785 mips_type_needs_double_align (struct type
*type
)
2787 enum type_code typecode
= TYPE_CODE (type
);
2789 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2791 else if (typecode
== TYPE_CODE_STRUCT
)
2793 if (TYPE_NFIELDS (type
) < 1)
2795 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2797 else if (typecode
== TYPE_CODE_UNION
)
2801 n
= TYPE_NFIELDS (type
);
2802 for (i
= 0; i
< n
; i
++)
2803 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2810 /* Adjust the address downward (direction of stack growth) so that it
2811 is correctly aligned for a new stack frame. */
2813 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2815 return align_down (addr
, 16);
2819 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2820 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2821 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2822 CORE_ADDR struct_addr
)
2828 int stack_offset
= 0;
2830 /* For shared libraries, "t9" needs to point at the function
2832 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2834 /* Set the return address register to point to the entry point of
2835 the program, where a breakpoint lies in wait. */
2836 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2838 /* First ensure that the stack and structure return address (if any)
2839 are properly aligned. The stack has to be at least 64-bit
2840 aligned even on 32-bit machines, because doubles must be 64-bit
2841 aligned. For n32 and n64, stack frames need to be 128-bit
2842 aligned, so we round to this widest known alignment. */
2844 sp
= align_down (sp
, 16);
2845 struct_addr
= align_down (struct_addr
, 16);
2847 /* Now make space on the stack for the args. We allocate more
2848 than necessary for EABI, because the first few arguments are
2849 passed in registers, but that's OK. */
2850 for (argnum
= 0; argnum
< nargs
; argnum
++)
2851 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2852 MIPS_STACK_ARGSIZE
);
2853 sp
-= align_up (len
, 16);
2856 fprintf_unfiltered (gdb_stdlog
,
2857 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2858 paddr_nz (sp
), (long) align_up (len
, 16));
2860 /* Initialize the integer and float register pointers. */
2862 float_argreg
= FPA0_REGNUM
;
2864 /* The struct_return pointer occupies the first parameter-passing reg. */
2868 fprintf_unfiltered (gdb_stdlog
,
2869 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2870 argreg
, paddr_nz (struct_addr
));
2871 write_register (argreg
++, struct_addr
);
2874 /* Now load as many as possible of the first arguments into
2875 registers, and push the rest onto the stack. Loop thru args
2876 from first to last. */
2877 for (argnum
= 0; argnum
< nargs
; argnum
++)
2880 char valbuf
[MAX_REGISTER_SIZE
];
2881 struct value
*arg
= args
[argnum
];
2882 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2883 int len
= TYPE_LENGTH (arg_type
);
2884 enum type_code typecode
= TYPE_CODE (arg_type
);
2887 fprintf_unfiltered (gdb_stdlog
,
2888 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2889 argnum
+ 1, len
, (int) typecode
);
2891 /* The EABI passes structures that do not fit in a register by
2893 if (len
> MIPS_SAVED_REGSIZE
2894 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2896 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2897 typecode
= TYPE_CODE_PTR
;
2898 len
= MIPS_SAVED_REGSIZE
;
2901 fprintf_unfiltered (gdb_stdlog
, " push");
2904 val
= (char *) VALUE_CONTENTS (arg
);
2906 /* 32-bit ABIs always start floating point arguments in an
2907 even-numbered floating point register. Round the FP register
2908 up before the check to see if there are any FP registers
2909 left. Non MIPS_EABI targets also pass the FP in the integer
2910 registers so also round up normal registers. */
2911 if (!FP_REGISTER_DOUBLE
2912 && fp_register_arg_p (typecode
, arg_type
))
2914 if ((float_argreg
& 1))
2918 /* Floating point arguments passed in registers have to be
2919 treated specially. On 32-bit architectures, doubles
2920 are passed in register pairs; the even register gets
2921 the low word, and the odd register gets the high word.
2922 On non-EABI processors, the first two floating point arguments are
2923 also copied to general registers, because MIPS16 functions
2924 don't use float registers for arguments. This duplication of
2925 arguments in general registers can't hurt non-MIPS16 functions
2926 because those registers are normally skipped. */
2927 /* MIPS_EABI squeezes a struct that contains a single floating
2928 point value into an FP register instead of pushing it onto the
2930 if (fp_register_arg_p (typecode
, arg_type
)
2931 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2933 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2935 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2936 unsigned long regval
;
2938 /* Write the low word of the double to the even register(s). */
2939 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2941 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2942 float_argreg
, phex (regval
, 4));
2943 write_register (float_argreg
++, regval
);
2945 /* Write the high word of the double to the odd register(s). */
2946 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2948 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2949 float_argreg
, phex (regval
, 4));
2950 write_register (float_argreg
++, regval
);
2954 /* This is a floating point value that fits entirely
2955 in a single register. */
2956 /* On 32 bit ABI's the float_argreg is further adjusted
2957 above to ensure that it is even register aligned. */
2958 LONGEST regval
= extract_unsigned_integer (val
, len
);
2960 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2961 float_argreg
, phex (regval
, len
));
2962 write_register (float_argreg
++, regval
);
2967 /* Copy the argument to general registers or the stack in
2968 register-sized pieces. Large arguments are split between
2969 registers and stack. */
2970 /* Note: structs whose size is not a multiple of
2971 mips_regsize() are treated specially: Irix cc passes them
2972 in registers where gcc sometimes puts them on the stack.
2973 For maximum compatibility, we will put them in both
2975 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2976 (len
% MIPS_SAVED_REGSIZE
!= 0));
2978 /* Note: Floating-point values that didn't fit into an FP
2979 register are only written to memory. */
2982 /* Remember if the argument was written to the stack. */
2983 int stack_used_p
= 0;
2985 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2988 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2991 /* Write this portion of the argument to the stack. */
2992 if (argreg
> MIPS_LAST_ARG_REGNUM
2994 || fp_register_arg_p (typecode
, arg_type
))
2996 /* Should shorter than int integer values be
2997 promoted to int before being stored? */
2998 int longword_offset
= 0;
3001 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3003 if (MIPS_STACK_ARGSIZE
== 8 &&
3004 (typecode
== TYPE_CODE_INT
||
3005 typecode
== TYPE_CODE_PTR
||
3006 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3007 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3008 else if ((typecode
== TYPE_CODE_STRUCT
||
3009 typecode
== TYPE_CODE_UNION
) &&
3010 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
3011 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3016 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3017 paddr_nz (stack_offset
));
3018 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3019 paddr_nz (longword_offset
));
3022 addr
= sp
+ stack_offset
+ longword_offset
;
3027 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3029 for (i
= 0; i
< partial_len
; i
++)
3031 fprintf_unfiltered (gdb_stdlog
, "%02x",
3035 write_memory (addr
, val
, partial_len
);
3038 /* Note!!! This is NOT an else clause. Odd sized
3039 structs may go thru BOTH paths. Floating point
3040 arguments will not. */
3041 /* Write this portion of the argument to a general
3042 purpose register. */
3043 if (argreg
<= MIPS_LAST_ARG_REGNUM
3044 && !fp_register_arg_p (typecode
, arg_type
))
3046 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3049 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3051 phex (regval
, MIPS_SAVED_REGSIZE
));
3052 write_register (argreg
, regval
);
3059 /* Compute the the offset into the stack at which we
3060 will copy the next parameter.
3062 In the new EABI (and the NABI32), the stack_offset
3063 only needs to be adjusted when it has been used. */
3066 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3070 fprintf_unfiltered (gdb_stdlog
, "\n");
3073 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3075 /* Return adjusted stack pointer. */
3079 /* N32/N64 version of push_dummy_call. */
3082 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3083 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3084 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3085 CORE_ADDR struct_addr
)
3091 int stack_offset
= 0;
3093 /* For shared libraries, "t9" needs to point at the function
3095 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3097 /* Set the return address register to point to the entry point of
3098 the program, where a breakpoint lies in wait. */
3099 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3101 /* First ensure that the stack and structure return address (if any)
3102 are properly aligned. The stack has to be at least 64-bit
3103 aligned even on 32-bit machines, because doubles must be 64-bit
3104 aligned. For n32 and n64, stack frames need to be 128-bit
3105 aligned, so we round to this widest known alignment. */
3107 sp
= align_down (sp
, 16);
3108 struct_addr
= align_down (struct_addr
, 16);
3110 /* Now make space on the stack for the args. */
3111 for (argnum
= 0; argnum
< nargs
; argnum
++)
3112 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3113 MIPS_STACK_ARGSIZE
);
3114 sp
-= align_up (len
, 16);
3117 fprintf_unfiltered (gdb_stdlog
,
3118 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3119 paddr_nz (sp
), (long) align_up (len
, 16));
3121 /* Initialize the integer and float register pointers. */
3123 float_argreg
= FPA0_REGNUM
;
3125 /* The struct_return pointer occupies the first parameter-passing reg. */
3129 fprintf_unfiltered (gdb_stdlog
,
3130 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3131 argreg
, paddr_nz (struct_addr
));
3132 write_register (argreg
++, struct_addr
);
3135 /* Now load as many as possible of the first arguments into
3136 registers, and push the rest onto the stack. Loop thru args
3137 from first to last. */
3138 for (argnum
= 0; argnum
< nargs
; argnum
++)
3141 char valbuf
[MAX_REGISTER_SIZE
];
3142 struct value
*arg
= args
[argnum
];
3143 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3144 int len
= TYPE_LENGTH (arg_type
);
3145 enum type_code typecode
= TYPE_CODE (arg_type
);
3148 fprintf_unfiltered (gdb_stdlog
,
3149 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3150 argnum
+ 1, len
, (int) typecode
);
3152 val
= (char *) VALUE_CONTENTS (arg
);
3154 if (fp_register_arg_p (typecode
, arg_type
)
3155 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3157 /* This is a floating point value that fits entirely
3158 in a single register. */
3159 /* On 32 bit ABI's the float_argreg is further adjusted
3160 above to ensure that it is even register aligned. */
3161 LONGEST regval
= extract_unsigned_integer (val
, len
);
3163 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3164 float_argreg
, phex (regval
, len
));
3165 write_register (float_argreg
++, regval
);
3168 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3169 argreg
, phex (regval
, len
));
3170 write_register (argreg
, regval
);
3175 /* Copy the argument to general registers or the stack in
3176 register-sized pieces. Large arguments are split between
3177 registers and stack. */
3178 /* Note: structs whose size is not a multiple of
3179 mips_regsize() are treated specially: Irix cc passes them
3180 in registers where gcc sometimes puts them on the stack.
3181 For maximum compatibility, we will put them in both
3183 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3184 (len
% MIPS_SAVED_REGSIZE
!= 0));
3185 /* Note: Floating-point values that didn't fit into an FP
3186 register are only written to memory. */
3189 /* Rememer if the argument was written to the stack. */
3190 int stack_used_p
= 0;
3191 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3192 len
: MIPS_SAVED_REGSIZE
;
3195 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3198 /* Write this portion of the argument to the stack. */
3199 if (argreg
> MIPS_LAST_ARG_REGNUM
3201 || fp_register_arg_p (typecode
, arg_type
))
3203 /* Should shorter than int integer values be
3204 promoted to int before being stored? */
3205 int longword_offset
= 0;
3208 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3210 if (MIPS_STACK_ARGSIZE
== 8 &&
3211 (typecode
== TYPE_CODE_INT
||
3212 typecode
== TYPE_CODE_PTR
||
3213 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3214 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3219 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3220 paddr_nz (stack_offset
));
3221 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3222 paddr_nz (longword_offset
));
3225 addr
= sp
+ stack_offset
+ longword_offset
;
3230 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3232 for (i
= 0; i
< partial_len
; i
++)
3234 fprintf_unfiltered (gdb_stdlog
, "%02x",
3238 write_memory (addr
, val
, partial_len
);
3241 /* Note!!! This is NOT an else clause. Odd sized
3242 structs may go thru BOTH paths. Floating point
3243 arguments will not. */
3244 /* Write this portion of the argument to a general
3245 purpose register. */
3246 if (argreg
<= MIPS_LAST_ARG_REGNUM
3247 && !fp_register_arg_p (typecode
, arg_type
))
3249 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3251 /* A non-floating-point argument being passed in a
3252 general register. If a struct or union, and if
3253 the remaining length is smaller than the register
3254 size, we have to adjust the register value on
3257 It does not seem to be necessary to do the
3258 same for integral types.
3260 cagney/2001-07-23: gdb/179: Also, GCC, when
3261 outputting LE O32 with sizeof (struct) <
3262 MIPS_SAVED_REGSIZE, generates a left shift as
3263 part of storing the argument in a register a
3264 register (the left shift isn't generated when
3265 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3266 is quite possible that this is GCC contradicting
3267 the LE/O32 ABI, GDB has not been adjusted to
3268 accommodate this. Either someone needs to
3269 demonstrate that the LE/O32 ABI specifies such a
3270 left shift OR this new ABI gets identified as
3271 such and GDB gets tweaked accordingly. */
3273 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3274 && partial_len
< MIPS_SAVED_REGSIZE
3275 && (typecode
== TYPE_CODE_STRUCT
||
3276 typecode
== TYPE_CODE_UNION
))
3277 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3281 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3283 phex (regval
, MIPS_SAVED_REGSIZE
));
3284 write_register (argreg
, regval
);
3291 /* Compute the the offset into the stack at which we
3292 will copy the next parameter.
3294 In N32 (N64?), the stack_offset only needs to be
3295 adjusted when it has been used. */
3298 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3302 fprintf_unfiltered (gdb_stdlog
, "\n");
3305 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3307 /* Return adjusted stack pointer. */
3311 /* O32 version of push_dummy_call. */
3314 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3315 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3316 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3317 CORE_ADDR struct_addr
)
3323 int stack_offset
= 0;
3325 /* For shared libraries, "t9" needs to point at the function
3327 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3329 /* Set the return address register to point to the entry point of
3330 the program, where a breakpoint lies in wait. */
3331 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3333 /* First ensure that the stack and structure return address (if any)
3334 are properly aligned. The stack has to be at least 64-bit
3335 aligned even on 32-bit machines, because doubles must be 64-bit
3336 aligned. For n32 and n64, stack frames need to be 128-bit
3337 aligned, so we round to this widest known alignment. */
3339 sp
= align_down (sp
, 16);
3340 struct_addr
= align_down (struct_addr
, 16);
3342 /* Now make space on the stack for the args. */
3343 for (argnum
= 0; argnum
< nargs
; argnum
++)
3344 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3345 MIPS_STACK_ARGSIZE
);
3346 sp
-= align_up (len
, 16);
3349 fprintf_unfiltered (gdb_stdlog
,
3350 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3351 paddr_nz (sp
), (long) align_up (len
, 16));
3353 /* Initialize the integer and float register pointers. */
3355 float_argreg
= FPA0_REGNUM
;
3357 /* The struct_return pointer occupies the first parameter-passing reg. */
3361 fprintf_unfiltered (gdb_stdlog
,
3362 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3363 argreg
, paddr_nz (struct_addr
));
3364 write_register (argreg
++, struct_addr
);
3365 stack_offset
+= MIPS_STACK_ARGSIZE
;
3368 /* Now load as many as possible of the first arguments into
3369 registers, and push the rest onto the stack. Loop thru args
3370 from first to last. */
3371 for (argnum
= 0; argnum
< nargs
; argnum
++)
3374 char valbuf
[MAX_REGISTER_SIZE
];
3375 struct value
*arg
= args
[argnum
];
3376 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3377 int len
= TYPE_LENGTH (arg_type
);
3378 enum type_code typecode
= TYPE_CODE (arg_type
);
3381 fprintf_unfiltered (gdb_stdlog
,
3382 "mips_o32_push_dummy_call: %d len=%d type=%d",
3383 argnum
+ 1, len
, (int) typecode
);
3385 val
= (char *) VALUE_CONTENTS (arg
);
3387 /* 32-bit ABIs always start floating point arguments in an
3388 even-numbered floating point register. Round the FP register
3389 up before the check to see if there are any FP registers
3390 left. O32/O64 targets also pass the FP in the integer
3391 registers so also round up normal registers. */
3392 if (!FP_REGISTER_DOUBLE
3393 && fp_register_arg_p (typecode
, arg_type
))
3395 if ((float_argreg
& 1))
3399 /* Floating point arguments passed in registers have to be
3400 treated specially. On 32-bit architectures, doubles
3401 are passed in register pairs; the even register gets
3402 the low word, and the odd register gets the high word.
3403 On O32/O64, the first two floating point arguments are
3404 also copied to general registers, because MIPS16 functions
3405 don't use float registers for arguments. This duplication of
3406 arguments in general registers can't hurt non-MIPS16 functions
3407 because those registers are normally skipped. */
3409 if (fp_register_arg_p (typecode
, arg_type
)
3410 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3412 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3414 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3415 unsigned long regval
;
3417 /* Write the low word of the double to the even register(s). */
3418 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3420 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3421 float_argreg
, phex (regval
, 4));
3422 write_register (float_argreg
++, regval
);
3424 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3425 argreg
, phex (regval
, 4));
3426 write_register (argreg
++, regval
);
3428 /* Write the high word of the double to the odd register(s). */
3429 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3431 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3432 float_argreg
, phex (regval
, 4));
3433 write_register (float_argreg
++, regval
);
3436 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3437 argreg
, phex (regval
, 4));
3438 write_register (argreg
++, regval
);
3442 /* This is a floating point value that fits entirely
3443 in a single register. */
3444 /* On 32 bit ABI's the float_argreg is further adjusted
3445 above to ensure that it is even register aligned. */
3446 LONGEST regval
= extract_unsigned_integer (val
, len
);
3448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3449 float_argreg
, phex (regval
, len
));
3450 write_register (float_argreg
++, regval
);
3451 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3452 registers for each argument. The below is (my
3453 guess) to ensure that the corresponding integer
3454 register has reserved the same space. */
3456 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3457 argreg
, phex (regval
, len
));
3458 write_register (argreg
, regval
);
3459 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3461 /* Reserve space for the FP register. */
3462 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3466 /* Copy the argument to general registers or the stack in
3467 register-sized pieces. Large arguments are split between
3468 registers and stack. */
3469 /* Note: structs whose size is not a multiple of
3470 mips_regsize() are treated specially: Irix cc passes them
3471 in registers where gcc sometimes puts them on the stack.
3472 For maximum compatibility, we will put them in both
3474 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3475 (len
% MIPS_SAVED_REGSIZE
!= 0));
3476 /* Structures should be aligned to eight bytes (even arg registers)
3477 on MIPS_ABI_O32, if their first member has double precision. */
3478 if (MIPS_SAVED_REGSIZE
< 8
3479 && mips_type_needs_double_align (arg_type
))
3484 /* Note: Floating-point values that didn't fit into an FP
3485 register are only written to memory. */
3488 /* Remember if the argument was written to the stack. */
3489 int stack_used_p
= 0;
3491 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3494 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3497 /* Write this portion of the argument to the stack. */
3498 if (argreg
> MIPS_LAST_ARG_REGNUM
3500 || fp_register_arg_p (typecode
, arg_type
))
3502 /* Should shorter than int integer values be
3503 promoted to int before being stored? */
3504 int longword_offset
= 0;
3507 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3509 if (MIPS_STACK_ARGSIZE
== 8 &&
3510 (typecode
== TYPE_CODE_INT
||
3511 typecode
== TYPE_CODE_PTR
||
3512 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3513 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3518 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3519 paddr_nz (stack_offset
));
3520 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3521 paddr_nz (longword_offset
));
3524 addr
= sp
+ stack_offset
+ longword_offset
;
3529 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3531 for (i
= 0; i
< partial_len
; i
++)
3533 fprintf_unfiltered (gdb_stdlog
, "%02x",
3537 write_memory (addr
, val
, partial_len
);
3540 /* Note!!! This is NOT an else clause. Odd sized
3541 structs may go thru BOTH paths. Floating point
3542 arguments will not. */
3543 /* Write this portion of the argument to a general
3544 purpose register. */
3545 if (argreg
<= MIPS_LAST_ARG_REGNUM
3546 && !fp_register_arg_p (typecode
, arg_type
))
3548 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3549 /* Value may need to be sign extended, because
3550 mips_regsize() != MIPS_SAVED_REGSIZE. */
3552 /* A non-floating-point argument being passed in a
3553 general register. If a struct or union, and if
3554 the remaining length is smaller than the register
3555 size, we have to adjust the register value on
3558 It does not seem to be necessary to do the
3559 same for integral types.
3561 Also don't do this adjustment on O64 binaries.
3563 cagney/2001-07-23: gdb/179: Also, GCC, when
3564 outputting LE O32 with sizeof (struct) <
3565 MIPS_SAVED_REGSIZE, generates a left shift as
3566 part of storing the argument in a register a
3567 register (the left shift isn't generated when
3568 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3569 is quite possible that this is GCC contradicting
3570 the LE/O32 ABI, GDB has not been adjusted to
3571 accommodate this. Either someone needs to
3572 demonstrate that the LE/O32 ABI specifies such a
3573 left shift OR this new ABI gets identified as
3574 such and GDB gets tweaked accordingly. */
3576 if (MIPS_SAVED_REGSIZE
< 8
3577 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3578 && partial_len
< MIPS_SAVED_REGSIZE
3579 && (typecode
== TYPE_CODE_STRUCT
||
3580 typecode
== TYPE_CODE_UNION
))
3581 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3585 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3587 phex (regval
, MIPS_SAVED_REGSIZE
));
3588 write_register (argreg
, regval
);
3591 /* Prevent subsequent floating point arguments from
3592 being passed in floating point registers. */
3593 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3599 /* Compute the the offset into the stack at which we
3600 will copy the next parameter.
3602 In older ABIs, the caller reserved space for
3603 registers that contained arguments. This was loosely
3604 refered to as their "home". Consequently, space is
3605 always allocated. */
3607 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3611 fprintf_unfiltered (gdb_stdlog
, "\n");
3614 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3616 /* Return adjusted stack pointer. */
3620 /* O64 version of push_dummy_call. */
3623 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3624 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3625 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3626 CORE_ADDR struct_addr
)
3632 int stack_offset
= 0;
3634 /* For shared libraries, "t9" needs to point at the function
3636 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3638 /* Set the return address register to point to the entry point of
3639 the program, where a breakpoint lies in wait. */
3640 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3642 /* First ensure that the stack and structure return address (if any)
3643 are properly aligned. The stack has to be at least 64-bit
3644 aligned even on 32-bit machines, because doubles must be 64-bit
3645 aligned. For n32 and n64, stack frames need to be 128-bit
3646 aligned, so we round to this widest known alignment. */
3648 sp
= align_down (sp
, 16);
3649 struct_addr
= align_down (struct_addr
, 16);
3651 /* Now make space on the stack for the args. */
3652 for (argnum
= 0; argnum
< nargs
; argnum
++)
3653 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3654 MIPS_STACK_ARGSIZE
);
3655 sp
-= align_up (len
, 16);
3658 fprintf_unfiltered (gdb_stdlog
,
3659 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3660 paddr_nz (sp
), (long) align_up (len
, 16));
3662 /* Initialize the integer and float register pointers. */
3664 float_argreg
= FPA0_REGNUM
;
3666 /* The struct_return pointer occupies the first parameter-passing reg. */
3670 fprintf_unfiltered (gdb_stdlog
,
3671 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3672 argreg
, paddr_nz (struct_addr
));
3673 write_register (argreg
++, struct_addr
);
3674 stack_offset
+= MIPS_STACK_ARGSIZE
;
3677 /* Now load as many as possible of the first arguments into
3678 registers, and push the rest onto the stack. Loop thru args
3679 from first to last. */
3680 for (argnum
= 0; argnum
< nargs
; argnum
++)
3683 char valbuf
[MAX_REGISTER_SIZE
];
3684 struct value
*arg
= args
[argnum
];
3685 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3686 int len
= TYPE_LENGTH (arg_type
);
3687 enum type_code typecode
= TYPE_CODE (arg_type
);
3690 fprintf_unfiltered (gdb_stdlog
,
3691 "mips_o64_push_dummy_call: %d len=%d type=%d",
3692 argnum
+ 1, len
, (int) typecode
);
3694 val
= (char *) VALUE_CONTENTS (arg
);
3696 /* 32-bit ABIs always start floating point arguments in an
3697 even-numbered floating point register. Round the FP register
3698 up before the check to see if there are any FP registers
3699 left. O32/O64 targets also pass the FP in the integer
3700 registers so also round up normal registers. */
3701 if (!FP_REGISTER_DOUBLE
3702 && fp_register_arg_p (typecode
, arg_type
))
3704 if ((float_argreg
& 1))
3708 /* Floating point arguments passed in registers have to be
3709 treated specially. On 32-bit architectures, doubles
3710 are passed in register pairs; the even register gets
3711 the low word, and the odd register gets the high word.
3712 On O32/O64, the first two floating point arguments are
3713 also copied to general registers, because MIPS16 functions
3714 don't use float registers for arguments. This duplication of
3715 arguments in general registers can't hurt non-MIPS16 functions
3716 because those registers are normally skipped. */
3718 if (fp_register_arg_p (typecode
, arg_type
)
3719 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3721 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3723 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3724 unsigned long regval
;
3726 /* Write the low word of the double to the even register(s). */
3727 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3729 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3730 float_argreg
, phex (regval
, 4));
3731 write_register (float_argreg
++, regval
);
3733 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3734 argreg
, phex (regval
, 4));
3735 write_register (argreg
++, regval
);
3737 /* Write the high word of the double to the odd register(s). */
3738 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3740 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3741 float_argreg
, phex (regval
, 4));
3742 write_register (float_argreg
++, regval
);
3745 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3746 argreg
, phex (regval
, 4));
3747 write_register (argreg
++, regval
);
3751 /* This is a floating point value that fits entirely
3752 in a single register. */
3753 /* On 32 bit ABI's the float_argreg is further adjusted
3754 above to ensure that it is even register aligned. */
3755 LONGEST regval
= extract_unsigned_integer (val
, len
);
3757 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3758 float_argreg
, phex (regval
, len
));
3759 write_register (float_argreg
++, regval
);
3760 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3761 registers for each argument. The below is (my
3762 guess) to ensure that the corresponding integer
3763 register has reserved the same space. */
3765 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3766 argreg
, phex (regval
, len
));
3767 write_register (argreg
, regval
);
3768 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3770 /* Reserve space for the FP register. */
3771 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3775 /* Copy the argument to general registers or the stack in
3776 register-sized pieces. Large arguments are split between
3777 registers and stack. */
3778 /* Note: structs whose size is not a multiple of
3779 mips_regsize() are treated specially: Irix cc passes them
3780 in registers where gcc sometimes puts them on the stack.
3781 For maximum compatibility, we will put them in both
3783 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3784 (len
% MIPS_SAVED_REGSIZE
!= 0));
3785 /* Structures should be aligned to eight bytes (even arg registers)
3786 on MIPS_ABI_O32, if their first member has double precision. */
3787 if (MIPS_SAVED_REGSIZE
< 8
3788 && mips_type_needs_double_align (arg_type
))
3793 /* Note: Floating-point values that didn't fit into an FP
3794 register are only written to memory. */
3797 /* Remember if the argument was written to the stack. */
3798 int stack_used_p
= 0;
3800 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3803 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3806 /* Write this portion of the argument to the stack. */
3807 if (argreg
> MIPS_LAST_ARG_REGNUM
3809 || fp_register_arg_p (typecode
, arg_type
))
3811 /* Should shorter than int integer values be
3812 promoted to int before being stored? */
3813 int longword_offset
= 0;
3816 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3818 if (MIPS_STACK_ARGSIZE
== 8 &&
3819 (typecode
== TYPE_CODE_INT
||
3820 typecode
== TYPE_CODE_PTR
||
3821 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3822 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3827 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3828 paddr_nz (stack_offset
));
3829 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3830 paddr_nz (longword_offset
));
3833 addr
= sp
+ stack_offset
+ longword_offset
;
3838 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3840 for (i
= 0; i
< partial_len
; i
++)
3842 fprintf_unfiltered (gdb_stdlog
, "%02x",
3846 write_memory (addr
, val
, partial_len
);
3849 /* Note!!! This is NOT an else clause. Odd sized
3850 structs may go thru BOTH paths. Floating point
3851 arguments will not. */
3852 /* Write this portion of the argument to a general
3853 purpose register. */
3854 if (argreg
<= MIPS_LAST_ARG_REGNUM
3855 && !fp_register_arg_p (typecode
, arg_type
))
3857 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3858 /* Value may need to be sign extended, because
3859 mips_regsize() != MIPS_SAVED_REGSIZE. */
3861 /* A non-floating-point argument being passed in a
3862 general register. If a struct or union, and if
3863 the remaining length is smaller than the register
3864 size, we have to adjust the register value on
3867 It does not seem to be necessary to do the
3868 same for integral types.
3870 Also don't do this adjustment on O64 binaries.
3872 cagney/2001-07-23: gdb/179: Also, GCC, when
3873 outputting LE O32 with sizeof (struct) <
3874 MIPS_SAVED_REGSIZE, generates a left shift as
3875 part of storing the argument in a register a
3876 register (the left shift isn't generated when
3877 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3878 is quite possible that this is GCC contradicting
3879 the LE/O32 ABI, GDB has not been adjusted to
3880 accommodate this. Either someone needs to
3881 demonstrate that the LE/O32 ABI specifies such a
3882 left shift OR this new ABI gets identified as
3883 such and GDB gets tweaked accordingly. */
3885 if (MIPS_SAVED_REGSIZE
< 8
3886 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3887 && partial_len
< MIPS_SAVED_REGSIZE
3888 && (typecode
== TYPE_CODE_STRUCT
||
3889 typecode
== TYPE_CODE_UNION
))
3890 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3894 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3896 phex (regval
, MIPS_SAVED_REGSIZE
));
3897 write_register (argreg
, regval
);
3900 /* Prevent subsequent floating point arguments from
3901 being passed in floating point registers. */
3902 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3908 /* Compute the the offset into the stack at which we
3909 will copy the next parameter.
3911 In older ABIs, the caller reserved space for
3912 registers that contained arguments. This was loosely
3913 refered to as their "home". Consequently, space is
3914 always allocated. */
3916 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3920 fprintf_unfiltered (gdb_stdlog
, "\n");
3923 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3925 /* Return adjusted stack pointer. */
3930 mips_pop_frame (void)
3933 struct frame_info
*frame
= get_current_frame ();
3934 CORE_ADDR new_sp
= get_frame_base (frame
);
3935 mips_extra_func_info_t proc_desc
;
3937 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3939 generic_pop_dummy_frame ();
3940 flush_cached_frames ();
3944 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3945 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3946 mips_find_saved_regs (frame
);
3947 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3948 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3949 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3951 /* Floating point registers must not be sign extended,
3952 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3954 if (FP0_REGNUM
<= regnum
&& regnum
< FP0_REGNUM
+ 32)
3955 write_register (regnum
,
3956 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3957 MIPS_SAVED_REGSIZE
));
3959 write_register (regnum
,
3960 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3961 MIPS_SAVED_REGSIZE
));
3964 write_register (SP_REGNUM
, new_sp
);
3965 flush_cached_frames ();
3967 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3969 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3971 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3973 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3975 if (&pi_ptr
->info
== proc_desc
)
3980 error ("Can't locate dummy extra frame info\n");
3982 if (prev_ptr
!= NULL
)
3983 prev_ptr
->next
= pi_ptr
->next
;
3985 linked_proc_desc_table
= pi_ptr
->next
;
3989 write_register (HI_REGNUM
,
3990 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3991 MIPS_SAVED_REGSIZE
));
3992 write_register (LO_REGNUM
,
3993 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3994 MIPS_SAVED_REGSIZE
));
3995 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3996 write_register (FCRCS_REGNUM
,
3997 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3998 MIPS_SAVED_REGSIZE
));
4002 /* Floating point register management.
4004 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4005 64bit operations, these early MIPS cpus treat fp register pairs
4006 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4007 registers and offer a compatibility mode that emulates the MIPS2 fp
4008 model. When operating in MIPS2 fp compat mode, later cpu's split
4009 double precision floats into two 32-bit chunks and store them in
4010 consecutive fp regs. To display 64-bit floats stored in this
4011 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4012 Throw in user-configurable endianness and you have a real mess.
4014 The way this works is:
4015 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4016 double-precision value will be split across two logical registers.
4017 The lower-numbered logical register will hold the low-order bits,
4018 regardless of the processor's endianness.
4019 - If we are on a 64-bit processor, and we are looking for a
4020 single-precision value, it will be in the low ordered bits
4021 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4022 save slot in memory.
4023 - If we are in 64-bit mode, everything is straightforward.
4025 Note that this code only deals with "live" registers at the top of the
4026 stack. We will attempt to deal with saved registers later, when
4027 the raw/cooked register interface is in place. (We need a general
4028 interface that can deal with dynamic saved register sizes -- fp
4029 regs could be 32 bits wide in one frame and 64 on the frame above
4032 static struct type
*
4033 mips_float_register_type (void)
4035 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4036 return builtin_type_ieee_single_big
;
4038 return builtin_type_ieee_single_little
;
4041 static struct type
*
4042 mips_double_register_type (void)
4044 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4045 return builtin_type_ieee_double_big
;
4047 return builtin_type_ieee_double_little
;
4050 /* Copy a 32-bit single-precision value from the current frame
4051 into rare_buffer. */
4054 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4057 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4058 char *raw_buffer
= alloca (raw_size
);
4060 if (!frame_register_read (frame
, regno
, raw_buffer
))
4061 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4064 /* We have a 64-bit value for this register. Find the low-order
4068 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4073 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4077 memcpy (rare_buffer
, raw_buffer
, 4);
4081 /* Copy a 64-bit double-precision value from the current frame into
4082 rare_buffer. This may include getting half of it from the next
4086 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4089 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4091 if (raw_size
== 8 && !mips2_fp_compat ())
4093 /* We have a 64-bit value for this register, and we should use
4095 if (!frame_register_read (frame
, regno
, rare_buffer
))
4096 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4100 if ((regno
- FP0_REGNUM
) & 1)
4101 internal_error (__FILE__
, __LINE__
,
4102 "mips_read_fp_register_double: bad access to "
4103 "odd-numbered FP register");
4105 /* mips_read_fp_register_single will find the correct 32 bits from
4107 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4109 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4110 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4114 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4115 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4121 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4123 { /* do values for FP (float) regs */
4125 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4126 int inv1
, inv2
, namelen
;
4128 raw_buffer
= (char *) alloca (2 * DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
));
4130 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4131 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4134 if (DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
4136 /* 4-byte registers: Print hex and floating. Also print even
4137 numbered registers as doubles. */
4138 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4139 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4141 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4143 fprintf_filtered (file
, " flt: ");
4145 fprintf_filtered (file
, " <invalid float> ");
4147 fprintf_filtered (file
, "%-17.9g", flt1
);
4149 if (regnum
% 2 == 0)
4151 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4152 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4155 fprintf_filtered (file
, " dbl: ");
4157 fprintf_filtered (file
, "<invalid double>");
4159 fprintf_filtered (file
, "%-24.17g", doub
);
4164 /* Eight byte registers: print each one as hex, float and double. */
4165 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4166 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4168 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4169 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4172 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4174 fprintf_filtered (file
, " flt: ");
4176 fprintf_filtered (file
, "<invalid float>");
4178 fprintf_filtered (file
, "%-17.9g", flt1
);
4180 fprintf_filtered (file
, " dbl: ");
4182 fprintf_filtered (file
, "<invalid double>");
4184 fprintf_filtered (file
, "%-24.17g", doub
);
4189 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4190 int regnum
, int all
)
4192 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4193 char raw_buffer
[MAX_REGISTER_SIZE
];
4196 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4198 mips_print_fp_register (file
, frame
, regnum
);
4202 /* Get the data in raw format. */
4203 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4205 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4209 fputs_filtered (REGISTER_NAME (regnum
), file
);
4211 /* The problem with printing numeric register names (r26, etc.) is that
4212 the user can't use them on input. Probably the best solution is to
4213 fix it so that either the numeric or the funky (a2, etc.) names
4214 are accepted on input. */
4215 if (regnum
< MIPS_NUMREGS
)
4216 fprintf_filtered (file
, "(r%d): ", regnum
);
4218 fprintf_filtered (file
, ": ");
4220 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4221 offset
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
4225 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4229 /* Replacement for generic do_registers_info.
4230 Print regs in pretty columns. */
4233 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4236 fprintf_filtered (file
, " ");
4237 mips_print_fp_register (file
, frame
, regnum
);
4238 fprintf_filtered (file
, "\n");
4243 /* Print a row's worth of GP (int) registers, with name labels above */
4246 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4249 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4250 /* do values for GP (int) regs */
4251 char raw_buffer
[MAX_REGISTER_SIZE
];
4252 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4256 /* For GP registers, we print a separate row of names above the vals */
4257 fprintf_filtered (file
, " ");
4258 for (col
= 0, regnum
= start_regnum
;
4259 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4262 if (*REGISTER_NAME (regnum
) == '\0')
4263 continue; /* unused register */
4264 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4265 break; /* end the row: reached FP register */
4266 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4267 REGISTER_NAME (regnum
));
4270 /* print the R0 to R31 names */
4271 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4272 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4274 fprintf_filtered (file
, "\n ");
4276 /* now print the values in hex, 4 or 8 to the row */
4277 for (col
= 0, regnum
= start_regnum
;
4278 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4281 if (*REGISTER_NAME (regnum
) == '\0')
4282 continue; /* unused register */
4283 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4284 break; /* end row: reached FP register */
4285 /* OK: get the data in raw format. */
4286 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4287 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4288 /* pad small registers */
4290 byte
< (mips_regsize (current_gdbarch
)
4291 - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
));
4293 printf_filtered (" ");
4294 /* Now print the register value in hex, endian order. */
4295 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4296 for (byte
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
4297 byte
< DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4299 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4301 for (byte
= DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
) - 1;
4304 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4305 fprintf_filtered (file
, " ");
4308 if (col
> 0) /* ie. if we actually printed anything... */
4309 fprintf_filtered (file
, "\n");
4314 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4317 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4318 struct frame_info
*frame
, int regnum
, int all
)
4320 if (regnum
!= -1) /* do one specified register */
4322 gdb_assert (regnum
>= NUM_REGS
);
4323 if (*(REGISTER_NAME (regnum
)) == '\0')
4324 error ("Not a valid register for the current processor type");
4326 mips_print_register (file
, frame
, regnum
, 0);
4327 fprintf_filtered (file
, "\n");
4330 /* do all (or most) registers */
4333 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4335 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4337 if (all
) /* true for "INFO ALL-REGISTERS" command */
4338 regnum
= print_fp_register_row (file
, frame
, regnum
);
4340 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4343 regnum
= print_gp_register_row (file
, frame
, regnum
);
4348 /* Is this a branch with a delay slot? */
4350 static int is_delayed (unsigned long);
4353 is_delayed (unsigned long insn
)
4356 for (i
= 0; i
< NUMOPCODES
; ++i
)
4357 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4358 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4360 return (i
< NUMOPCODES
4361 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4362 | INSN_COND_BRANCH_DELAY
4363 | INSN_COND_BRANCH_LIKELY
)));
4367 mips_step_skips_delay (CORE_ADDR pc
)
4369 char buf
[MIPS_INSTLEN
];
4371 /* There is no branch delay slot on MIPS16. */
4372 if (pc_is_mips16 (pc
))
4375 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4376 /* If error reading memory, guess that it is not a delayed branch. */
4378 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4382 /* Skip the PC past function prologue instructions (32-bit version).
4383 This is a helper function for mips_skip_prologue. */
4386 mips32_skip_prologue (CORE_ADDR pc
)
4390 int seen_sp_adjust
= 0;
4391 int load_immediate_bytes
= 0;
4393 /* Skip the typical prologue instructions. These are the stack adjustment
4394 instruction and the instructions that save registers on the stack
4395 or in the gcc frame. */
4396 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4398 unsigned long high_word
;
4400 inst
= mips_fetch_instruction (pc
);
4401 high_word
= (inst
>> 16) & 0xffff;
4403 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4404 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4406 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4407 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4409 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4410 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4411 && (inst
& 0x001F0000)) /* reg != $zero */
4414 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4416 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4418 continue; /* reg != $zero */
4420 /* move $s8,$sp. With different versions of gas this will be either
4421 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4422 Accept any one of these. */
4423 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4426 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4428 else if (high_word
== 0x3c1c) /* lui $gp,n */
4430 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4432 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4433 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4435 /* The following instructions load $at or $t0 with an immediate
4436 value in preparation for a stack adjustment via
4437 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4438 a local variable, so we accept them only before a stack adjustment
4439 instruction was seen. */
4440 else if (!seen_sp_adjust
)
4442 if (high_word
== 0x3c01 || /* lui $at,n */
4443 high_word
== 0x3c08) /* lui $t0,n */
4445 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4448 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4449 high_word
== 0x3508 || /* ori $t0,$t0,n */
4450 high_word
== 0x3401 || /* ori $at,$zero,n */
4451 high_word
== 0x3408) /* ori $t0,$zero,n */
4453 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4463 /* In a frameless function, we might have incorrectly
4464 skipped some load immediate instructions. Undo the skipping
4465 if the load immediate was not followed by a stack adjustment. */
4466 if (load_immediate_bytes
&& !seen_sp_adjust
)
4467 pc
-= load_immediate_bytes
;
4471 /* Skip the PC past function prologue instructions (16-bit version).
4472 This is a helper function for mips_skip_prologue. */
4475 mips16_skip_prologue (CORE_ADDR pc
)
4478 int extend_bytes
= 0;
4479 int prev_extend_bytes
;
4481 /* Table of instructions likely to be found in a function prologue. */
4484 unsigned short inst
;
4485 unsigned short mask
;
4492 , /* addiu $sp,offset */
4496 , /* daddiu $sp,offset */
4500 , /* sw reg,n($sp) */
4504 , /* sd reg,n($sp) */
4508 , /* sw $ra,n($sp) */
4512 , /* sd $ra,n($sp) */
4520 , /* sw $a0-$a3,n($s1) */
4524 , /* move reg,$a0-$a3 */
4528 , /* entry pseudo-op */
4532 , /* addiu $s1,$sp,n */
4535 } /* end of table marker */
4538 /* Skip the typical prologue instructions. These are the stack adjustment
4539 instruction and the instructions that save registers on the stack
4540 or in the gcc frame. */
4541 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4543 unsigned short inst
;
4546 inst
= mips_fetch_instruction (pc
);
4548 /* Normally we ignore an extend instruction. However, if it is
4549 not followed by a valid prologue instruction, we must adjust
4550 the pc back over the extend so that it won't be considered
4551 part of the prologue. */
4552 if ((inst
& 0xf800) == 0xf000) /* extend */
4554 extend_bytes
= MIPS16_INSTLEN
;
4557 prev_extend_bytes
= extend_bytes
;
4560 /* Check for other valid prologue instructions besides extend. */
4561 for (i
= 0; table
[i
].mask
!= 0; i
++)
4562 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4564 if (table
[i
].mask
!= 0) /* it was in table? */
4565 continue; /* ignore it */
4569 /* Return the current pc, adjusted backwards by 2 if
4570 the previous instruction was an extend. */
4571 return pc
- prev_extend_bytes
;
4577 /* To skip prologues, I use this predicate. Returns either PC itself
4578 if the code at PC does not look like a function prologue; otherwise
4579 returns an address that (if we're lucky) follows the prologue. If
4580 LENIENT, then we must skip everything which is involved in setting
4581 up the frame (it's OK to skip more, just so long as we don't skip
4582 anything which might clobber the registers which are being saved.
4583 We must skip more in the case where part of the prologue is in the
4584 delay slot of a non-prologue instruction). */
4587 mips_skip_prologue (CORE_ADDR pc
)
4589 /* See if we can determine the end of the prologue via the symbol table.
4590 If so, then return either PC, or the PC after the prologue, whichever
4593 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4595 if (post_prologue_pc
!= 0)
4596 return max (pc
, post_prologue_pc
);
4598 /* Can't determine prologue from the symbol table, need to examine
4601 if (pc_is_mips16 (pc
))
4602 return mips16_skip_prologue (pc
);
4604 return mips32_skip_prologue (pc
);
4607 /* Determine how a return value is stored within the MIPS register
4608 file, given the return type `valtype'. */
4610 struct return_value_word
4619 return_value_location (struct type
*valtype
,
4620 struct return_value_word
*hi
,
4621 struct return_value_word
*lo
)
4623 int len
= TYPE_LENGTH (valtype
);
4625 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4626 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4627 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4629 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4631 /* We need to break a 64bit float in two 32 bit halves and
4632 spread them across a floating-point register pair. */
4633 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4634 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4635 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4636 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4638 hi
->reg_offset
= lo
->reg_offset
;
4639 lo
->reg
= FP0_REGNUM
+ 0;
4640 hi
->reg
= FP0_REGNUM
+ 1;
4646 /* The floating point value fits in a single floating-point
4648 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4649 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4652 lo
->reg
= FP0_REGNUM
;
4663 /* Locate a result possibly spread across two registers. */
4665 lo
->reg
= regnum
+ 0;
4666 hi
->reg
= regnum
+ 1;
4667 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4668 && len
< MIPS_SAVED_REGSIZE
)
4670 /* "un-left-justify" the value in the low register */
4671 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4676 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4677 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4678 && len
< MIPS_SAVED_REGSIZE
* 2
4679 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4680 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4682 /* "un-left-justify" the value spread across two registers. */
4683 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4684 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4686 hi
->len
= len
- lo
->len
;
4690 /* Only perform a partial copy of the second register. */
4693 if (len
> MIPS_SAVED_REGSIZE
)
4695 lo
->len
= MIPS_SAVED_REGSIZE
;
4696 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4704 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4705 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 8
4706 && MIPS_SAVED_REGSIZE
== 4)
4708 /* Account for the fact that only the least-signficant part
4709 of the register is being used */
4710 lo
->reg_offset
+= 4;
4711 hi
->reg_offset
+= 4;
4714 hi
->buf_offset
= lo
->len
;
4718 /* Given a return value in `regbuf' with a type `valtype', extract and
4719 copy its value into `valbuf'. */
4722 mips_eabi_extract_return_value (struct type
*valtype
,
4726 struct return_value_word lo
;
4727 struct return_value_word hi
;
4728 return_value_location (valtype
, &hi
, &lo
);
4730 memcpy (valbuf
+ lo
.buf_offset
,
4731 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4735 memcpy (valbuf
+ hi
.buf_offset
,
4736 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4741 mips_o64_extract_return_value (struct type
*valtype
,
4745 struct return_value_word lo
;
4746 struct return_value_word hi
;
4747 return_value_location (valtype
, &hi
, &lo
);
4749 memcpy (valbuf
+ lo
.buf_offset
,
4750 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4754 memcpy (valbuf
+ hi
.buf_offset
,
4755 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4759 /* Given a return value in `valbuf' with a type `valtype', write it's
4760 value into the appropriate register. */
4763 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4765 char raw_buffer
[MAX_REGISTER_SIZE
];
4766 struct return_value_word lo
;
4767 struct return_value_word hi
;
4768 return_value_location (valtype
, &hi
, &lo
);
4770 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4771 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4772 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4773 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4777 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4778 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4779 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4780 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4785 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4787 char raw_buffer
[MAX_REGISTER_SIZE
];
4788 struct return_value_word lo
;
4789 struct return_value_word hi
;
4790 return_value_location (valtype
, &hi
, &lo
);
4792 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4793 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4794 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4795 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4799 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4800 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4801 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4802 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4806 /* O32 ABI stuff. */
4809 mips_o32_xfer_return_value (struct type
*type
,
4810 struct regcache
*regcache
,
4811 bfd_byte
*in
, const bfd_byte
*out
)
4813 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4814 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4815 && TYPE_LENGTH (type
) == 4
4816 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4818 /* A single-precision floating-point value. It fits in the
4819 least significant part of FP0. */
4821 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4822 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4823 TARGET_BYTE_ORDER
, in
, out
, 0);
4825 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4826 && TYPE_LENGTH (type
) == 8
4827 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4829 /* A double-precision floating-point value. The most
4830 significant part goes in FP1, and the least significant in
4833 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4834 switch (TARGET_BYTE_ORDER
)
4836 case BFD_ENDIAN_LITTLE
:
4837 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4838 TARGET_BYTE_ORDER
, in
, out
, 0);
4839 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4840 TARGET_BYTE_ORDER
, in
, out
, 4);
4842 case BFD_ENDIAN_BIG
:
4843 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4844 TARGET_BYTE_ORDER
, in
, out
, 0);
4845 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4846 TARGET_BYTE_ORDER
, in
, out
, 4);
4849 internal_error (__FILE__
, __LINE__
, "bad switch");
4853 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4854 && TYPE_NFIELDS (type
) <= 2
4855 && TYPE_NFIELDS (type
) >= 1
4856 && ((TYPE_NFIELDS (type
) == 1
4857 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4859 || (TYPE_NFIELDS (type
) == 2
4860 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4862 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4864 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4866 /* A struct that contains one or two floats. Each value is part
4867 in the least significant part of their floating point
4869 bfd_byte reg
[MAX_REGISTER_SIZE
];
4872 for (field
= 0, regnum
= FP0_REGNUM
;
4873 field
< TYPE_NFIELDS (type
);
4874 field
++, regnum
+= 2)
4876 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4879 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4880 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4881 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4882 TARGET_BYTE_ORDER
, in
, out
, offset
);
4887 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4888 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4890 /* A structure or union. Extract the left justified value,
4891 regardless of the byte order. I.e. DO NOT USE
4895 for (offset
= 0, regnum
= V0_REGNUM
;
4896 offset
< TYPE_LENGTH (type
);
4897 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
4899 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4900 if (offset
+ xfer
> TYPE_LENGTH (type
))
4901 xfer
= TYPE_LENGTH (type
) - offset
;
4903 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4904 offset
, xfer
, regnum
);
4905 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4906 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
4912 /* A scalar extract each part but least-significant-byte
4913 justified. o32 thinks registers are 4 byte, regardless of
4914 the ISA. mips_stack_argsize controls this. */
4917 for (offset
= 0, regnum
= V0_REGNUM
;
4918 offset
< TYPE_LENGTH (type
);
4919 offset
+= mips_stack_argsize (), regnum
++)
4921 int xfer
= mips_stack_argsize ();
4923 if (offset
+ xfer
> TYPE_LENGTH (type
))
4924 xfer
= TYPE_LENGTH (type
) - offset
;
4926 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4927 offset
, xfer
, regnum
);
4928 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4929 TARGET_BYTE_ORDER
, in
, out
, offset
);
4935 mips_o32_extract_return_value (struct type
*type
,
4936 struct regcache
*regcache
,
4939 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4943 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4945 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4948 /* N32/N44 ABI stuff. */
4951 mips_n32n64_xfer_return_value (struct type
*type
,
4952 struct regcache
*regcache
,
4953 bfd_byte
*in
, const bfd_byte
*out
)
4955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4956 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4957 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4959 /* A floating-point value belongs in the least significant part
4962 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4963 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4964 TARGET_BYTE_ORDER
, in
, out
, 0);
4966 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4967 && TYPE_NFIELDS (type
) <= 2
4968 && TYPE_NFIELDS (type
) >= 1
4969 && ((TYPE_NFIELDS (type
) == 1
4970 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4972 || (TYPE_NFIELDS (type
) == 2
4973 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4975 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4977 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4979 /* A struct that contains one or two floats. Each value is part
4980 in the least significant part of their floating point
4982 bfd_byte reg
[MAX_REGISTER_SIZE
];
4985 for (field
= 0, regnum
= FP0_REGNUM
;
4986 field
< TYPE_NFIELDS (type
);
4987 field
++, regnum
+= 2)
4989 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4992 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4993 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4994 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4995 TARGET_BYTE_ORDER
, in
, out
, offset
);
4998 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4999 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5001 /* A structure or union. Extract the left justified value,
5002 regardless of the byte order. I.e. DO NOT USE
5006 for (offset
= 0, regnum
= V0_REGNUM
;
5007 offset
< TYPE_LENGTH (type
);
5008 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
5010 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
5011 if (offset
+ xfer
> TYPE_LENGTH (type
))
5012 xfer
= TYPE_LENGTH (type
) - offset
;
5014 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5015 offset
, xfer
, regnum
);
5016 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5017 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
5022 /* A scalar extract each part but least-significant-byte
5026 for (offset
= 0, regnum
= V0_REGNUM
;
5027 offset
< TYPE_LENGTH (type
);
5028 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
5030 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
5032 if (offset
+ xfer
> TYPE_LENGTH (type
))
5033 xfer
= TYPE_LENGTH (type
) - offset
;
5035 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5036 offset
, xfer
, regnum
);
5037 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5038 TARGET_BYTE_ORDER
, in
, out
, offset
);
5044 mips_n32n64_extract_return_value (struct type
*type
,
5045 struct regcache
*regcache
,
5048 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
5052 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
5054 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
5058 mips_extract_struct_value_address (struct regcache
*regcache
)
5060 /* FIXME: This will only work at random. The caller passes the
5061 struct_return address in V0, but it is not preserved. It may
5062 still be there, or this may be a random value. */
5065 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5069 /* Exported procedure: Is PC in the signal trampoline code */
5072 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5074 if (sigtramp_address
== 0)
5076 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5079 /* Root of all "set mips "/"show mips " commands. This will eventually be
5080 used for all MIPS-specific commands. */
5083 show_mips_command (char *args
, int from_tty
)
5085 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5089 set_mips_command (char *args
, int from_tty
)
5091 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5092 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5095 /* Commands to show/set the MIPS FPU type. */
5098 show_mipsfpu_command (char *args
, int from_tty
)
5101 switch (MIPS_FPU_TYPE
)
5103 case MIPS_FPU_SINGLE
:
5104 fpu
= "single-precision";
5106 case MIPS_FPU_DOUBLE
:
5107 fpu
= "double-precision";
5110 fpu
= "absent (none)";
5113 internal_error (__FILE__
, __LINE__
, "bad switch");
5115 if (mips_fpu_type_auto
)
5116 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5119 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5125 set_mipsfpu_command (char *args
, int from_tty
)
5127 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5128 show_mipsfpu_command (args
, from_tty
);
5132 set_mipsfpu_single_command (char *args
, int from_tty
)
5134 mips_fpu_type
= MIPS_FPU_SINGLE
;
5135 mips_fpu_type_auto
= 0;
5136 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5140 set_mipsfpu_double_command (char *args
, int from_tty
)
5142 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5143 mips_fpu_type_auto
= 0;
5144 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5148 set_mipsfpu_none_command (char *args
, int from_tty
)
5150 mips_fpu_type
= MIPS_FPU_NONE
;
5151 mips_fpu_type_auto
= 0;
5152 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5156 set_mipsfpu_auto_command (char *args
, int from_tty
)
5158 mips_fpu_type_auto
= 1;
5161 /* Command to set the processor type. */
5164 mips_set_processor_type_command (char *args
, int from_tty
)
5168 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
5170 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5171 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5172 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
5174 /* Restore the value. */
5175 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5180 if (!mips_set_processor_type (tmp_mips_processor_type
))
5182 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
5183 /* Restore its value. */
5184 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5189 mips_show_processor_type_command (char *args
, int from_tty
)
5193 /* Modify the actual processor type. */
5196 mips_set_processor_type (char *str
)
5203 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5205 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5207 mips_processor_type
= str
;
5208 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5210 /* FIXME tweak fpu flag too */
5217 /* Attempt to identify the particular processor model by reading the
5221 mips_read_processor_type (void)
5225 prid
= read_register (PRID_REGNUM
);
5227 if ((prid
& ~0xf) == 0x700)
5228 return savestring ("r3041", strlen ("r3041"));
5233 /* Just like reinit_frame_cache, but with the right arguments to be
5234 callable as an sfunc. */
5237 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5238 struct cmd_list_element
*c
)
5240 reinit_frame_cache ();
5244 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5247 mips_extra_func_info_t proc_desc
;
5249 /* Search for the function containing this address. Set the low bit
5250 of the address when searching, in case we were given an even address
5251 that is the start of a 16-bit function. If we didn't do this,
5252 the search would fail because the symbol table says the function
5253 starts at an odd address, i.e. 1 byte past the given address. */
5254 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5255 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5257 /* Make an attempt to determine if this is a 16-bit function. If
5258 the procedure descriptor exists and the address therein is odd,
5259 it's definitely a 16-bit function. Otherwise, we have to just
5260 guess that if the address passed in is odd, it's 16-bits. */
5261 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5262 disassembler needs to be able to locally determine the ISA, and
5263 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5267 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5268 info
->mach
= bfd_mach_mips16
;
5272 if (pc_is_mips16 (memaddr
))
5273 info
->mach
= bfd_mach_mips16
;
5276 /* Round down the instruction address to the appropriate boundary. */
5277 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5279 /* Set the disassembler options. */
5280 if (tdep
->mips_abi
== MIPS_ABI_N32
5281 || tdep
->mips_abi
== MIPS_ABI_N64
)
5283 /* Set up the disassembler info, so that we get the right
5284 register names from libopcodes. */
5285 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5286 info
->disassembler_options
= "gpr-names=n32";
5288 info
->disassembler_options
= "gpr-names=64";
5289 info
->flavour
= bfd_target_elf_flavour
;
5292 /* This string is not recognized explicitly by the disassembler,
5293 but it tells the disassembler to not try to guess the ABI from
5294 the bfd elf headers, such that, if the user overrides the ABI
5295 of a program linked as NewABI, the disassembly will follow the
5296 register naming conventions specified by the user. */
5297 info
->disassembler_options
= "gpr-names=32";
5299 /* Call the appropriate disassembler based on the target endian-ness. */
5300 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5301 return print_insn_big_mips (memaddr
, info
);
5303 return print_insn_little_mips (memaddr
, info
);
5306 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5307 counter value to determine whether a 16- or 32-bit breakpoint should be
5308 used. It returns a pointer to a string of bytes that encode a breakpoint
5309 instruction, stores the length of the string to *lenptr, and adjusts pc
5310 (if necessary) to point to the actual memory location where the
5311 breakpoint should be inserted. */
5313 static const unsigned char *
5314 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5316 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5318 if (pc_is_mips16 (*pcptr
))
5320 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5321 *pcptr
= unmake_mips16_addr (*pcptr
);
5322 *lenptr
= sizeof (mips16_big_breakpoint
);
5323 return mips16_big_breakpoint
;
5327 /* The IDT board uses an unusual breakpoint value, and
5328 sometimes gets confused when it sees the usual MIPS
5329 breakpoint instruction. */
5330 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5331 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5332 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5334 *lenptr
= sizeof (big_breakpoint
);
5336 if (strcmp (target_shortname
, "mips") == 0)
5337 return idt_big_breakpoint
;
5338 else if (strcmp (target_shortname
, "ddb") == 0
5339 || strcmp (target_shortname
, "pmon") == 0
5340 || strcmp (target_shortname
, "lsi") == 0)
5341 return pmon_big_breakpoint
;
5343 return big_breakpoint
;
5348 if (pc_is_mips16 (*pcptr
))
5350 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5351 *pcptr
= unmake_mips16_addr (*pcptr
);
5352 *lenptr
= sizeof (mips16_little_breakpoint
);
5353 return mips16_little_breakpoint
;
5357 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5358 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5359 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5361 *lenptr
= sizeof (little_breakpoint
);
5363 if (strcmp (target_shortname
, "mips") == 0)
5364 return idt_little_breakpoint
;
5365 else if (strcmp (target_shortname
, "ddb") == 0
5366 || strcmp (target_shortname
, "pmon") == 0
5367 || strcmp (target_shortname
, "lsi") == 0)
5368 return pmon_little_breakpoint
;
5370 return little_breakpoint
;
5375 /* If PC is in a mips16 call or return stub, return the address of the target
5376 PC, which is either the callee or the caller. There are several
5377 cases which must be handled:
5379 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5380 target PC is in $31 ($ra).
5381 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5382 and the target PC is in $2.
5383 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5384 before the jal instruction, this is effectively a call stub
5385 and the the target PC is in $2. Otherwise this is effectively
5386 a return stub and the target PC is in $18.
5388 See the source code for the stubs in gcc/config/mips/mips16.S for
5391 This function implements the SKIP_TRAMPOLINE_CODE macro.
5395 mips_skip_stub (CORE_ADDR pc
)
5398 CORE_ADDR start_addr
;
5400 /* Find the starting address and name of the function containing the PC. */
5401 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5404 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5405 target PC is in $31 ($ra). */
5406 if (strcmp (name
, "__mips16_ret_sf") == 0
5407 || strcmp (name
, "__mips16_ret_df") == 0)
5408 return read_signed_register (RA_REGNUM
);
5410 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5412 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5413 and the target PC is in $2. */
5414 if (name
[19] >= '0' && name
[19] <= '9')
5415 return read_signed_register (2);
5417 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5418 before the jal instruction, this is effectively a call stub
5419 and the the target PC is in $2. Otherwise this is effectively
5420 a return stub and the target PC is in $18. */
5421 else if (name
[19] == 's' || name
[19] == 'd')
5423 if (pc
== start_addr
)
5425 /* Check if the target of the stub is a compiler-generated
5426 stub. Such a stub for a function bar might have a name
5427 like __fn_stub_bar, and might look like this:
5432 la $1,bar (becomes a lui/addiu pair)
5434 So scan down to the lui/addi and extract the target
5435 address from those two instructions. */
5437 CORE_ADDR target_pc
= read_signed_register (2);
5441 /* See if the name of the target function is __fn_stub_*. */
5442 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5444 if (strncmp (name
, "__fn_stub_", 10) != 0
5445 && strcmp (name
, "etext") != 0
5446 && strcmp (name
, "_etext") != 0)
5449 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5450 The limit on the search is arbitrarily set to 20
5451 instructions. FIXME. */
5452 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5454 inst
= mips_fetch_instruction (target_pc
);
5455 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5456 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5457 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5458 return pc
| (inst
& 0xffff); /* low word */
5461 /* Couldn't find the lui/addui pair, so return stub address. */
5465 /* This is the 'return' part of a call stub. The return
5466 address is in $r18. */
5467 return read_signed_register (18);
5470 return 0; /* not a stub */
5474 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5475 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5478 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5480 CORE_ADDR start_addr
;
5482 /* Find the starting address of the function containing the PC. If the
5483 caller didn't give us a name, look it up at the same time. */
5484 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5487 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5489 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5490 if (name
[19] >= '0' && name
[19] <= '9')
5492 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5493 before the jal instruction, this is effectively a call stub. */
5494 else if (name
[19] == 's' || name
[19] == 'd')
5495 return pc
== start_addr
;
5498 return 0; /* not a stub */
5502 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5503 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5506 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5508 CORE_ADDR start_addr
;
5510 /* Find the starting address of the function containing the PC. */
5511 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5514 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5515 if (strcmp (name
, "__mips16_ret_sf") == 0
5516 || strcmp (name
, "__mips16_ret_df") == 0)
5519 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5520 i.e. after the jal instruction, this is effectively a return stub. */
5521 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5522 && (name
[19] == 's' || name
[19] == 'd')
5523 && pc
!= start_addr
)
5526 return 0; /* not a stub */
5530 /* Return non-zero if the PC is in a library helper function that should
5531 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5534 mips_ignore_helper (CORE_ADDR pc
)
5538 /* Find the starting address and name of the function containing the PC. */
5539 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5542 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5543 that we want to ignore. */
5544 return (strcmp (name
, "__mips16_ret_sf") == 0
5545 || strcmp (name
, "__mips16_ret_df") == 0);
5549 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5550 the register stored on the stack (32) is different to its real raw
5551 size (64). The below ensures that registers are fetched from the
5552 stack using their ABI size and then stored into the RAW_BUFFER
5553 using their raw size.
5555 The alternative to adding this function would be to add an ABI
5556 macro - REGISTER_STACK_SIZE(). */
5559 mips_get_saved_register (char *raw_buffer
,
5562 struct frame_info
*frame
,
5564 enum lval_type
*lvalp
)
5567 enum lval_type lvalx
;
5571 /* Always a pseudo. */
5572 gdb_assert (regnum
>= NUM_REGS
);
5574 /* Make certain that all needed parameters are present. */
5579 if (optimizedp
== NULL
)
5580 optimizedp
= &optimizedx
;
5582 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5583 /* The SP_REGNUM is special, its value is stored in saved_regs.
5584 In fact, it is so special that it can even only be fetched
5585 using a raw register number! Once this code as been converted
5586 to frame-unwind the problem goes away. */
5587 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5588 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5589 &realnumx
, raw_buffer
);
5591 /* Get it from the next frame. */
5592 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5593 regnum
, optimizedp
, lvalp
, addrp
,
5594 &realnumx
, raw_buffer
);
5597 /* Immediately after a function call, return the saved pc.
5598 Can't always go through the frames for this because on some machines
5599 the new frame is not set up until the new function executes
5600 some instructions. */
5603 mips_saved_pc_after_call (struct frame_info
*frame
)
5605 return read_signed_register (RA_REGNUM
);
5609 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5610 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5613 mips_stab_reg_to_regnum (int num
)
5616 if (num
>= 0 && num
< 32)
5618 else if (num
>= 38 && num
< 70)
5619 regnum
= num
+ FP0_REGNUM
- 38;
5625 /* This will hopefully (eventually) provoke a warning. Should
5626 we be calling complaint() here? */
5627 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5628 return NUM_REGS
+ regnum
;
5632 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5633 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5636 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5639 if (num
>= 0 && num
< 32)
5641 else if (num
>= 32 && num
< 64)
5642 regnum
= num
+ FP0_REGNUM
- 32;
5648 /* This will hopefully (eventually) provoke a warning. Should we
5649 be calling complaint() here? */
5650 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5651 return NUM_REGS
+ regnum
;
5655 mips_register_sim_regno (int regnum
)
5657 /* Only makes sense to supply raw registers. */
5658 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5659 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5660 decide if it is valid. Should instead define a standard sim/gdb
5661 register numbering scheme. */
5662 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5663 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5666 return LEGACY_SIM_REGNO_IGNORE
;
5670 /* Convert an integer into an address. By first converting the value
5671 into a pointer and then extracting it signed, the address is
5672 guarenteed to be correctly sign extended. */
5675 mips_integer_to_address (struct type
*type
, void *buf
)
5677 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5678 LONGEST val
= unpack_long (type
, buf
);
5679 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5680 return extract_signed_integer (tmp
,
5681 TYPE_LENGTH (builtin_type_void_data_ptr
));
5685 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5687 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5688 const char *name
= bfd_get_section_name (abfd
, sect
);
5690 if (*abip
!= MIPS_ABI_UNKNOWN
)
5693 if (strncmp (name
, ".mdebug.", 8) != 0)
5696 if (strcmp (name
, ".mdebug.abi32") == 0)
5697 *abip
= MIPS_ABI_O32
;
5698 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5699 *abip
= MIPS_ABI_N32
;
5700 else if (strcmp (name
, ".mdebug.abi64") == 0)
5701 *abip
= MIPS_ABI_N64
;
5702 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5703 *abip
= MIPS_ABI_O64
;
5704 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5705 *abip
= MIPS_ABI_EABI32
;
5706 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5707 *abip
= MIPS_ABI_EABI64
;
5709 warning ("unsupported ABI %s.", name
+ 8);
5712 static enum mips_abi
5713 global_mips_abi (void)
5717 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5718 if (mips_abi_strings
[i
] == mips_abi_string
)
5719 return (enum mips_abi
) i
;
5721 internal_error (__FILE__
, __LINE__
,
5722 "unknown ABI string");
5725 static struct gdbarch
*
5726 mips_gdbarch_init (struct gdbarch_info info
,
5727 struct gdbarch_list
*arches
)
5729 struct gdbarch
*gdbarch
;
5730 struct gdbarch_tdep
*tdep
;
5732 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5739 /* First of all, extract the elf_flags, if available. */
5740 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5741 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5744 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5745 switch ((elf_flags
& EF_MIPS_ABI
))
5747 case E_MIPS_ABI_O32
:
5748 mips_abi
= MIPS_ABI_O32
;
5750 case E_MIPS_ABI_O64
:
5751 mips_abi
= MIPS_ABI_O64
;
5753 case E_MIPS_ABI_EABI32
:
5754 mips_abi
= MIPS_ABI_EABI32
;
5756 case E_MIPS_ABI_EABI64
:
5757 mips_abi
= MIPS_ABI_EABI64
;
5760 if ((elf_flags
& EF_MIPS_ABI2
))
5761 mips_abi
= MIPS_ABI_N32
;
5763 mips_abi
= MIPS_ABI_UNKNOWN
;
5767 /* GCC creates a pseudo-section whose name describes the ABI. */
5768 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5769 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5771 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5772 Use the ABI from the last architecture if there is one. */
5773 if (info
.abfd
== NULL
&& arches
!= NULL
)
5774 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5776 /* Try the architecture for any hint of the correct ABI. */
5777 if (mips_abi
== MIPS_ABI_UNKNOWN
5778 && info
.bfd_arch_info
!= NULL
5779 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5781 switch (info
.bfd_arch_info
->mach
)
5783 case bfd_mach_mips3900
:
5784 mips_abi
= MIPS_ABI_EABI32
;
5786 case bfd_mach_mips4100
:
5787 case bfd_mach_mips5000
:
5788 mips_abi
= MIPS_ABI_EABI64
;
5790 case bfd_mach_mips8000
:
5791 case bfd_mach_mips10000
:
5792 /* On Irix, ELF64 executables use the N64 ABI. The
5793 pseudo-sections which describe the ABI aren't present
5794 on IRIX. (Even for executables created by gcc.) */
5795 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5796 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5797 mips_abi
= MIPS_ABI_N64
;
5799 mips_abi
= MIPS_ABI_N32
;
5804 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5805 mips_abi
= MIPS_ABI_O32
;
5807 /* Now that we have found what the ABI for this binary would be,
5808 check whether the user is overriding it. */
5809 found_abi
= mips_abi
;
5810 wanted_abi
= global_mips_abi ();
5811 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5812 mips_abi
= wanted_abi
;
5816 fprintf_unfiltered (gdb_stdlog
,
5817 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5819 fprintf_unfiltered (gdb_stdlog
,
5820 "mips_gdbarch_init: mips_abi = %d\n",
5822 fprintf_unfiltered (gdb_stdlog
,
5823 "mips_gdbarch_init: found_mips_abi = %d\n",
5827 /* try to find a pre-existing architecture */
5828 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5830 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5832 /* MIPS needs to be pedantic about which ABI the object is
5834 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5836 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5838 return arches
->gdbarch
;
5841 /* Need a new architecture. Fill in a target specific vector. */
5842 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5843 gdbarch
= gdbarch_alloc (&info
, tdep
);
5844 tdep
->elf_flags
= elf_flags
;
5846 /* Initially set everything according to the default ABI/ISA. */
5847 set_gdbarch_short_bit (gdbarch
, 16);
5848 set_gdbarch_int_bit (gdbarch
, 32);
5849 set_gdbarch_float_bit (gdbarch
, 32);
5850 set_gdbarch_double_bit (gdbarch
, 64);
5851 set_gdbarch_long_double_bit (gdbarch
, 64);
5852 set_gdbarch_deprecated_register_raw_size (gdbarch
, mips_register_raw_size
);
5853 set_gdbarch_deprecated_register_byte (gdbarch
, mips_register_byte
);
5854 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5855 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5856 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5857 tdep
->found_abi
= found_abi
;
5858 tdep
->mips_abi
= mips_abi
;
5860 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5861 mips_elf_make_msymbol_special
);
5864 if (info
.osabi
== GDB_OSABI_IRIX
)
5868 set_gdbarch_num_regs (gdbarch
, num_regs
);
5869 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5874 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5875 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o32_store_return_value
);
5876 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5877 tdep
->mips_default_saved_regsize
= 4;
5878 tdep
->mips_default_stack_argsize
= 4;
5879 tdep
->mips_fp_register_double
= 0;
5880 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5881 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5882 tdep
->gdb_target_is_mips64
= 0;
5883 tdep
->default_mask_address_p
= 0;
5884 set_gdbarch_long_bit (gdbarch
, 32);
5885 set_gdbarch_ptr_bit (gdbarch
, 32);
5886 set_gdbarch_long_long_bit (gdbarch
, 64);
5887 set_gdbarch_deprecated_reg_struct_has_addr
5888 (gdbarch
, mips_o32_reg_struct_has_addr
);
5889 set_gdbarch_use_struct_convention (gdbarch
,
5890 always_use_struct_convention
);
5893 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5894 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5895 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5896 tdep
->mips_default_saved_regsize
= 8;
5897 tdep
->mips_default_stack_argsize
= 8;
5898 tdep
->mips_fp_register_double
= 1;
5899 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5900 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5901 tdep
->gdb_target_is_mips64
= 1;
5902 tdep
->default_mask_address_p
= 0;
5903 set_gdbarch_long_bit (gdbarch
, 32);
5904 set_gdbarch_ptr_bit (gdbarch
, 32);
5905 set_gdbarch_long_long_bit (gdbarch
, 64);
5906 set_gdbarch_deprecated_reg_struct_has_addr
5907 (gdbarch
, mips_o32_reg_struct_has_addr
);
5908 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5910 case MIPS_ABI_EABI32
:
5911 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5912 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5913 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5914 tdep
->mips_default_saved_regsize
= 4;
5915 tdep
->mips_default_stack_argsize
= 4;
5916 tdep
->mips_fp_register_double
= 0;
5917 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5918 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5919 tdep
->gdb_target_is_mips64
= 0;
5920 tdep
->default_mask_address_p
= 0;
5921 set_gdbarch_long_bit (gdbarch
, 32);
5922 set_gdbarch_ptr_bit (gdbarch
, 32);
5923 set_gdbarch_long_long_bit (gdbarch
, 64);
5924 set_gdbarch_deprecated_reg_struct_has_addr
5925 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5926 set_gdbarch_use_struct_convention (gdbarch
,
5927 mips_eabi_use_struct_convention
);
5929 case MIPS_ABI_EABI64
:
5930 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5931 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5932 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5933 tdep
->mips_default_saved_regsize
= 8;
5934 tdep
->mips_default_stack_argsize
= 8;
5935 tdep
->mips_fp_register_double
= 1;
5936 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5937 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5938 tdep
->gdb_target_is_mips64
= 1;
5939 tdep
->default_mask_address_p
= 0;
5940 set_gdbarch_long_bit (gdbarch
, 64);
5941 set_gdbarch_ptr_bit (gdbarch
, 64);
5942 set_gdbarch_long_long_bit (gdbarch
, 64);
5943 set_gdbarch_deprecated_reg_struct_has_addr
5944 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5945 set_gdbarch_use_struct_convention (gdbarch
,
5946 mips_eabi_use_struct_convention
);
5949 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5950 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5951 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5952 tdep
->mips_default_saved_regsize
= 8;
5953 tdep
->mips_default_stack_argsize
= 8;
5954 tdep
->mips_fp_register_double
= 1;
5955 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5956 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5957 tdep
->gdb_target_is_mips64
= 1;
5958 tdep
->default_mask_address_p
= 0;
5959 set_gdbarch_long_bit (gdbarch
, 32);
5960 set_gdbarch_ptr_bit (gdbarch
, 32);
5961 set_gdbarch_long_long_bit (gdbarch
, 64);
5962 set_gdbarch_use_struct_convention (gdbarch
,
5963 mips_n32n64_use_struct_convention
);
5964 set_gdbarch_deprecated_reg_struct_has_addr
5965 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5968 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5969 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5970 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5971 tdep
->mips_default_saved_regsize
= 8;
5972 tdep
->mips_default_stack_argsize
= 8;
5973 tdep
->mips_fp_register_double
= 1;
5974 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5975 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5976 tdep
->gdb_target_is_mips64
= 1;
5977 tdep
->default_mask_address_p
= 0;
5978 set_gdbarch_long_bit (gdbarch
, 64);
5979 set_gdbarch_ptr_bit (gdbarch
, 64);
5980 set_gdbarch_long_long_bit (gdbarch
, 64);
5981 set_gdbarch_use_struct_convention (gdbarch
,
5982 mips_n32n64_use_struct_convention
);
5983 set_gdbarch_deprecated_reg_struct_has_addr
5984 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5987 internal_error (__FILE__
, __LINE__
,
5988 "unknown ABI in switch");
5991 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5992 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5995 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5996 flag in object files because to do so would make it impossible to
5997 link with libraries compiled without "-gp32". This is
5998 unnecessarily restrictive.
6000 We could solve this problem by adding "-gp32" multilibs to gcc,
6001 but to set this flag before gcc is built with such multilibs will
6002 break too many systems.''
6004 But even more unhelpfully, the default linker output target for
6005 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6006 for 64-bit programs - you need to change the ABI to change this,
6007 and not all gcc targets support that currently. Therefore using
6008 this flag to detect 32-bit mode would do the wrong thing given
6009 the current gcc - it would make GDB treat these 64-bit programs
6010 as 32-bit programs by default. */
6012 /* enable/disable the MIPS FPU */
6013 if (!mips_fpu_type_auto
)
6014 tdep
->mips_fpu_type
= mips_fpu_type
;
6015 else if (info
.bfd_arch_info
!= NULL
6016 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6017 switch (info
.bfd_arch_info
->mach
)
6019 case bfd_mach_mips3900
:
6020 case bfd_mach_mips4100
:
6021 case bfd_mach_mips4111
:
6022 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
6024 case bfd_mach_mips4650
:
6025 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
6028 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6032 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6034 /* MIPS version of register names. NOTE: At present the MIPS
6035 register name management is part way between the old -
6036 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
6037 Further work on it is required. */
6038 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6039 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6040 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6041 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6042 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6044 /* Add/remove bits from an address. The MIPS needs be careful to
6045 ensure that all 32 bit addresses are sign extended to 64 bits. */
6046 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6048 /* There's a mess in stack frame creation. See comments in
6049 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6050 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6052 /* Map debug register numbers onto internal register numbers. */
6053 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6054 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6055 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6056 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6057 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6059 /* Initialize a frame */
6060 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6061 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6063 /* MIPS version of CALL_DUMMY */
6065 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6066 replaced by a command, and all targets will default to on stack
6067 (regardless of the stack's execute status). */
6068 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6069 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6070 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6071 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6072 set_gdbarch_deprecated_register_convertible (gdbarch
, mips_register_convertible
);
6073 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, mips_register_convert_to_virtual
);
6074 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, mips_register_convert_to_raw
);
6076 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6077 set_gdbarch_frameless_function_invocation (gdbarch
,
6078 generic_frameless_function_invocation_not
);
6079 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6080 set_gdbarch_frame_args_skip (gdbarch
, 0);
6082 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6084 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6085 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6086 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6088 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6089 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6091 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6092 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6093 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6095 set_gdbarch_function_start_offset (gdbarch
, 0);
6097 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6099 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6100 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6102 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6104 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6105 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6106 need to all be folded into the target vector. Since they are
6107 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6108 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6110 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6112 /* Hook in OS ABI-specific overrides, if they have been registered. */
6113 gdbarch_init_osabi (info
, gdbarch
);
6115 set_gdbarch_extract_struct_value_address (gdbarch
,
6116 mips_extract_struct_value_address
);
6118 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6120 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6121 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6127 mips_abi_update (char *ignore_args
, int from_tty
,
6128 struct cmd_list_element
*c
)
6130 struct gdbarch_info info
;
6132 /* Force the architecture to update, and (if it's a MIPS architecture)
6133 mips_gdbarch_init will take care of the rest. */
6134 gdbarch_info_init (&info
);
6135 gdbarch_update_p (info
);
6138 /* Print out which MIPS ABI is in use. */
6141 show_mips_abi (char *ignore_args
, int from_tty
)
6143 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6145 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6148 enum mips_abi global_abi
= global_mips_abi ();
6149 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6150 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6152 if (global_abi
== MIPS_ABI_UNKNOWN
)
6153 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6155 else if (global_abi
== actual_abi
)
6157 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6161 /* Probably shouldn't happen... */
6163 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6165 mips_abi_strings
[global_abi
]);
6171 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6177 int ef_mips_32bitmode
;
6178 /* determine the ISA */
6179 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6197 /* determine the size of a pointer */
6198 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6202 fprintf_unfiltered (file
,
6203 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6205 fprintf_unfiltered (file
,
6206 "mips_dump_tdep: ef_mips_arch = %d\n",
6208 fprintf_unfiltered (file
,
6209 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6211 mips_abi_strings
[tdep
->mips_abi
]);
6212 fprintf_unfiltered (file
,
6213 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6214 mips_mask_address_p (),
6215 tdep
->default_mask_address_p
);
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6219 FP_REGISTER_DOUBLE
);
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6222 MIPS_DEFAULT_FPU_TYPE
,
6223 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6224 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6225 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: MIPS_EABI = %d\n",
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6232 MIPS_LAST_FP_ARG_REGNUM
,
6233 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6237 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6238 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6239 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6241 fprintf_unfiltered (file
,
6242 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6243 MIPS_DEFAULT_SAVED_REGSIZE
);
6244 fprintf_unfiltered (file
,
6245 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6246 FP_REGISTER_DOUBLE
);
6247 fprintf_unfiltered (file
,
6248 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6249 MIPS_DEFAULT_STACK_ARGSIZE
);
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6252 MIPS_STACK_ARGSIZE
);
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: A0_REGNUM = %d\n",
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6258 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6259 fprintf_unfiltered (file
,
6260 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6261 XSTRING (ATTACH_DETACH
));
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6265 fprintf_unfiltered (file
,
6266 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6270 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6271 fprintf_unfiltered (file
,
6272 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6273 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6282 FIRST_EMBED_REGNUM
);
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6288 GDB_TARGET_IS_MIPS64
);
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: HI_REGNUM = %d\n",
6292 fprintf_unfiltered (file
,
6293 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6294 XSTRING (IGNORE_HELPER_CALL (PC
)));
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6297 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6298 fprintf_unfiltered (file
,
6299 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6300 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6301 fprintf_unfiltered (file
,
6302 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6304 fprintf_unfiltered (file
,
6305 "mips_dump_tdep: LO_REGNUM = %d\n",
6307 #ifdef MACHINE_CPROC_FP_OFFSET
6308 fprintf_unfiltered (file
,
6309 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6310 MACHINE_CPROC_FP_OFFSET
);
6312 #ifdef MACHINE_CPROC_PC_OFFSET
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6315 MACHINE_CPROC_PC_OFFSET
);
6317 #ifdef MACHINE_CPROC_SP_OFFSET
6318 fprintf_unfiltered (file
,
6319 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6320 MACHINE_CPROC_SP_OFFSET
);
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6327 fprintf_unfiltered (file
,
6328 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6332 fprintf_unfiltered (file
,
6333 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6334 MIPS_LAST_ARG_REGNUM
,
6335 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6336 fprintf_unfiltered (file
,
6337 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6339 fprintf_unfiltered (file
,
6340 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6343 MIPS_SAVED_REGSIZE
);
6344 fprintf_unfiltered (file
,
6345 "mips_dump_tdep: OP_LDFPR = used?\n");
6346 fprintf_unfiltered (file
,
6347 "mips_dump_tdep: OP_LDGPR = used?\n");
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: PRID_REGNUM = %d\n",
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6353 fprintf_unfiltered (file
,
6354 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6361 fprintf_unfiltered (file
,
6362 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6363 fprintf_unfiltered (file
,
6364 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6365 fprintf_unfiltered (file
,
6366 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: PROC_PC_REG = function?\n");
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6375 fprintf_unfiltered (file
,
6376 "mips_dump_tdep: PS_REGNUM = %d\n",
6378 fprintf_unfiltered (file
,
6379 "mips_dump_tdep: RA_REGNUM = %d\n",
6382 fprintf_unfiltered (file
,
6383 "mips_dump_tdep: SAVED_BYTES = %d\n",
6387 fprintf_unfiltered (file
,
6388 "mips_dump_tdep: SAVED_FP = %d\n",
6392 fprintf_unfiltered (file
,
6393 "mips_dump_tdep: SAVED_PC = %d\n",
6396 fprintf_unfiltered (file
,
6397 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6398 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6404 fprintf_unfiltered (file
,
6405 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6406 SIGFRAME_FPREGSAVE_OFF
);
6407 fprintf_unfiltered (file
,
6408 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6410 fprintf_unfiltered (file
,
6411 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6412 SIGFRAME_REGSAVE_OFF
);
6413 fprintf_unfiltered (file
,
6414 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6416 fprintf_unfiltered (file
,
6417 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6418 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6419 fprintf_unfiltered (file
,
6420 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6421 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6422 fprintf_unfiltered (file
,
6423 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6424 SOFTWARE_SINGLE_STEP_P ());
6425 fprintf_unfiltered (file
,
6426 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6427 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6428 #ifdef STACK_END_ADDR
6429 fprintf_unfiltered (file
,
6430 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6433 fprintf_unfiltered (file
,
6434 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6435 XSTRING (STEP_SKIPS_DELAY (PC
)));
6436 fprintf_unfiltered (file
,
6437 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6438 STEP_SKIPS_DELAY_P
);
6439 fprintf_unfiltered (file
,
6440 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6441 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6442 fprintf_unfiltered (file
,
6443 "mips_dump_tdep: T9_REGNUM = %d\n",
6445 fprintf_unfiltered (file
,
6446 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6447 fprintf_unfiltered (file
,
6448 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6449 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6450 fprintf_unfiltered (file
,
6451 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6452 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6454 fprintf_unfiltered (file
,
6455 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6456 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6459 fprintf_unfiltered (file
,
6460 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6463 #ifdef TRACE_FLAVOR_SIZE
6464 fprintf_unfiltered (file
,
6465 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6469 fprintf_unfiltered (file
,
6470 "mips_dump_tdep: TRACE_SET # %s\n",
6471 XSTRING (TRACE_SET (X
,STATE
)));
6473 #ifdef UNUSED_REGNUM
6474 fprintf_unfiltered (file
,
6475 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6478 fprintf_unfiltered (file
,
6479 "mips_dump_tdep: V0_REGNUM = %d\n",
6481 fprintf_unfiltered (file
,
6482 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6483 (long) VM_MIN_ADDRESS
);
6484 fprintf_unfiltered (file
,
6485 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6487 fprintf_unfiltered (file
,
6488 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6492 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6495 _initialize_mips_tdep (void)
6497 static struct cmd_list_element
*mipsfpulist
= NULL
;
6498 struct cmd_list_element
*c
;
6500 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6501 if (MIPS_ABI_LAST
+ 1
6502 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6503 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6505 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6507 /* Add root prefix command for all "set mips"/"show mips" commands */
6508 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6509 "Various MIPS specific commands.",
6510 &setmipscmdlist
, "set mips ", 0, &setlist
);
6512 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6513 "Various MIPS specific commands.",
6514 &showmipscmdlist
, "show mips ", 0, &showlist
);
6516 /* Allow the user to override the saved register size. */
6517 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6520 &mips_saved_regsize_string
, "\
6521 Set size of general purpose registers saved on the stack.\n\
6522 This option can be set to one of:\n\
6523 32 - Force GDB to treat saved GP registers as 32-bit\n\
6524 64 - Force GDB to treat saved GP registers as 64-bit\n\
6525 auto - Allow GDB to use the target's default setting or autodetect the\n\
6526 saved GP register size from information contained in the executable.\n\
6531 /* Allow the user to override the argument stack size. */
6532 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6535 &mips_stack_argsize_string
, "\
6536 Set the amount of stack space reserved for each argument.\n\
6537 This option can be set to one of:\n\
6538 32 - Force GDB to allocate 32-bit chunks per argument\n\
6539 64 - Force GDB to allocate 64-bit chunks per argument\n\
6540 auto - Allow GDB to determine the correct setting from the current\n\
6541 target and executable (default)",
6545 /* Allow the user to override the ABI. */
6546 c
= add_set_enum_cmd
6547 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6548 "Set the ABI used by this program.\n"
6549 "This option can be set to one of:\n"
6550 " auto - the default ABI associated with the current binary\n"
6558 set_cmd_sfunc (c
, mips_abi_update
);
6559 add_cmd ("abi", class_obscure
, show_mips_abi
,
6560 "Show ABI in use by MIPS target", &showmipscmdlist
);
6562 /* Let the user turn off floating point and set the fence post for
6563 heuristic_proc_start. */
6565 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6566 "Set use of MIPS floating-point coprocessor.",
6567 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6568 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6569 "Select single-precision MIPS floating-point coprocessor.",
6571 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6572 "Select double-precision MIPS floating-point coprocessor.",
6574 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6575 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6576 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6577 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6578 "Select no MIPS floating-point coprocessor.",
6580 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6581 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6582 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6583 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6584 "Select MIPS floating-point coprocessor automatically.",
6586 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6587 "Show current use of MIPS floating-point coprocessor target.",
6590 /* We really would like to have both "0" and "unlimited" work, but
6591 command.c doesn't deal with that. So make it a var_zinteger
6592 because the user can always use "999999" or some such for unlimited. */
6593 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6594 (char *) &heuristic_fence_post
,
6596 Set the distance searched for the start of a function.\n\
6597 If you are debugging a stripped executable, GDB needs to search through the\n\
6598 program for the start of a function. This command sets the distance of the\n\
6599 search. The only need to set it is when debugging a stripped executable.",
6601 /* We need to throw away the frame cache when we set this, since it
6602 might change our ability to get backtraces. */
6603 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6604 add_show_from_set (c
, &showlist
);
6606 /* Allow the user to control whether the upper bits of 64-bit
6607 addresses should be zeroed. */
6608 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6609 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6610 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6611 allow GDB to determine the correct value.\n", "\
6612 Show zeroing of upper 32 bits of 64-bit addresses.",
6613 NULL
, show_mask_address
,
6614 &setmipscmdlist
, &showmipscmdlist
);
6616 /* Allow the user to control the size of 32 bit registers within the
6617 raw remote packet. */
6618 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6621 (char *)&mips64_transfers_32bit_regs_p
, "\
6622 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6623 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6624 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6625 64 bits for others. Use \"off\" to disable compatibility mode",
6629 /* Debug this files internals. */
6630 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6631 &mips_debug
, "Set mips debugging.\n\
6632 When non-zero, mips specific debugging is enabled.", &setdebuglist
),