1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
42 struct frame_extra_info
44 mips_extra_func_info_t proc_desc
;
48 /* We allow the user to override MIPS_SAVED_REGSIZE, so define
49 the subcommand enum settings allowed. */
50 static char saved_gpreg_size_auto
[] = "auto";
51 static char saved_gpreg_size_32
[] = "32";
52 static char saved_gpreg_size_64
[] = "64";
54 static char *saved_gpreg_size_enums
[] = {
55 saved_gpreg_size_auto
,
61 /* The current (string) value of saved_gpreg_size. */
62 static char *mips_saved_regsize_string
= saved_gpreg_size_auto
;
64 /* Some MIPS boards don't support floating point while others only
65 support single-precision floating-point operations. See also
66 FP_REGISTER_DOUBLE. */
70 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
71 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
72 MIPS_FPU_NONE
/* No floating point. */
75 #ifndef MIPS_DEFAULT_FPU_TYPE
76 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
78 static int mips_fpu_type_auto
= 1;
79 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
80 #define MIPS_FPU_TYPE mips_fpu_type
82 #ifndef MIPS_DEFAULT_SAVED_REGSIZE
83 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
86 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
88 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
89 #ifndef FP_REGISTER_DOUBLE
90 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
94 /* MIPS specific per-architecture information */
97 /* from the elf header */
101 enum mips_fpu_type mips_fpu_type
;
102 int mips_last_arg_regnum
;
103 int mips_last_fp_arg_regnum
;
104 int mips_default_saved_regsize
;
105 int mips_fp_register_double
;
110 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi)
114 #undef MIPS_LAST_FP_ARG_REGNUM
115 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
119 #undef MIPS_LAST_ARG_REGNUM
120 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
125 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
129 #undef MIPS_DEFAULT_SAVED_REGSIZE
130 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
133 /* Indicate that the ABI makes use of double-precision registers
134 provided by the FPU (rather than combining pairs of registers to
135 form double-precision values). Do not use "TARGET_IS_MIPS64" to
136 determine if the ABI is using double-precision registers. See also
139 #undef FP_REGISTER_DOUBLE
140 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
144 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
147 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
150 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
152 static void mips_print_register
PARAMS ((int, int));
154 static mips_extra_func_info_t
155 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
157 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
159 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
161 int mips_set_processor_type
PARAMS ((char *));
163 static void mips_show_processor_type_command
PARAMS ((char *, int));
165 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
166 struct cmd_list_element
*));
168 static mips_extra_func_info_t
169 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
171 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
172 mips_extra_func_info_t proc_desc
));
174 /* This value is the model of MIPS in use. It is derived from the value
175 of the PrID register. */
177 char *mips_processor_type
;
179 char *tmp_mips_processor_type
;
181 /* A set of original names, to be used when restoring back to generic
182 registers from a specific set. */
184 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
185 char **mips_processor_reg_names
= mips_generic_reg_names
;
187 /* The list of available "set mips " and "show mips " commands */
188 static struct cmd_list_element
*setmipscmdlist
= NULL
;
189 static struct cmd_list_element
*showmipscmdlist
= NULL
;
192 mips_register_name (i
)
195 return mips_processor_reg_names
[i
];
198 /* Names of IDT R3041 registers. */
200 char *mips_r3041_reg_names
[] = {
201 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
202 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
203 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
204 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
205 "sr", "lo", "hi", "bad", "cause","pc",
206 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
207 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
208 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
209 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
210 "fsr", "fir", "fp", "",
211 "", "", "bus", "ccfg", "", "", "", "",
212 "", "", "port", "cmp", "", "", "epc", "prid",
215 /* Names of IDT R3051 registers. */
217 char *mips_r3051_reg_names
[] = {
218 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
219 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
220 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
221 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
222 "sr", "lo", "hi", "bad", "cause","pc",
223 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
224 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
225 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
226 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
227 "fsr", "fir", "fp", "",
228 "inx", "rand", "elo", "", "ctxt", "", "", "",
229 "", "", "ehi", "", "", "", "epc", "prid",
232 /* Names of IDT R3081 registers. */
234 char *mips_r3081_reg_names
[] = {
235 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
236 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
237 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
238 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
239 "sr", "lo", "hi", "bad", "cause","pc",
240 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
241 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
242 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
243 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
244 "fsr", "fir", "fp", "",
245 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
246 "", "", "ehi", "", "", "", "epc", "prid",
249 /* Names of LSI 33k registers. */
251 char *mips_lsi33k_reg_names
[] = {
252 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
253 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
254 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
255 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
256 "epc", "hi", "lo", "sr", "cause","badvaddr",
257 "dcic", "bpc", "bda", "", "", "", "", "",
258 "", "", "", "", "", "", "", "",
259 "", "", "", "", "", "", "", "",
260 "", "", "", "", "", "", "", "",
262 "", "", "", "", "", "", "", "",
263 "", "", "", "", "", "", "", "",
269 } mips_processor_type_table
[] = {
270 { "generic", mips_generic_reg_names
},
271 { "r3041", mips_r3041_reg_names
},
272 { "r3051", mips_r3051_reg_names
},
273 { "r3071", mips_r3081_reg_names
},
274 { "r3081", mips_r3081_reg_names
},
275 { "lsi33k", mips_lsi33k_reg_names
},
283 /* Table to translate MIPS16 register field to actual register number. */
284 static int mips16_to_32_reg
[8] =
285 {16, 17, 2, 3, 4, 5, 6, 7};
287 /* Heuristic_proc_start may hunt through the text section for a long
288 time across a 2400 baud serial line. Allows the user to limit this
291 static unsigned int heuristic_fence_post
= 0;
293 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
294 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
295 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
296 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
297 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
298 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
299 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
300 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
301 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
302 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
303 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
304 #define _PROC_MAGIC_ 0x0F0F0F0F
305 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
306 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
308 struct linked_proc_info
310 struct mips_extra_func_info info
;
311 struct linked_proc_info
*next
;
313 *linked_proc_desc_table
= NULL
;
316 mips_print_extra_frame_info (fi
)
317 struct frame_info
*fi
;
321 && fi
->extra_info
->proc_desc
322 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
323 printf_filtered (" frame pointer is at %s+%s\n",
324 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
325 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
328 /* Return the currently configured (or set) saved register size */
331 mips_saved_regsize ()
333 if (mips_saved_regsize_string
== saved_gpreg_size_auto
)
334 return MIPS_DEFAULT_SAVED_REGSIZE
;
335 else if (mips_saved_regsize_string
== saved_gpreg_size_64
)
337 else /* if (mips_saved_regsize_string == saved_gpreg_size_32) */
341 /* Convert between RAW and VIRTUAL registers. The RAW register size
342 defines the remote-gdb packet. */
344 static int mips64_transfers_32bit_regs_p
= 0;
347 mips_register_raw_size (reg_nr
)
350 if (mips64_transfers_32bit_regs_p
)
351 return REGISTER_VIRTUAL_SIZE (reg_nr
);
357 mips_register_convertible (reg_nr
)
360 if (mips64_transfers_32bit_regs_p
)
363 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
367 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
369 struct type
*virtual_type
;
373 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
375 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
376 TYPE_LENGTH (virtual_type
));
380 TYPE_LENGTH (virtual_type
));
384 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
385 struct type
*virtual_type
;
390 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
391 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
392 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
394 TYPE_LENGTH (virtual_type
));
398 TYPE_LENGTH (virtual_type
));
401 /* Should the upper word of 64-bit addresses be zeroed? */
402 static int mask_address_p
= 1;
404 /* Should call_function allocate stack space for a struct return? */
406 mips_use_struct_convention (gcc_p
, type
)
411 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
413 return 1; /* Structures are returned by ref in extra arg0 */
416 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
419 pc_is_mips16 (bfd_vma memaddr
)
421 struct minimal_symbol
*sym
;
423 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
424 if (IS_MIPS16_ADDR (memaddr
))
427 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
428 the high bit of the info field. Use this to decide if the function is
429 MIPS16 or normal MIPS. */
430 sym
= lookup_minimal_symbol_by_pc (memaddr
);
432 return MSYMBOL_IS_SPECIAL (sym
);
438 /* This returns the PC of the first inst after the prologue. If we can't
439 find the prologue, then return 0. */
442 after_prologue (pc
, proc_desc
)
444 mips_extra_func_info_t proc_desc
;
446 struct symtab_and_line sal
;
447 CORE_ADDR func_addr
, func_end
;
450 proc_desc
= find_proc_desc (pc
, NULL
);
454 /* If function is frameless, then we need to do it the hard way. I
455 strongly suspect that frameless always means prologueless... */
456 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
457 && PROC_FRAME_OFFSET (proc_desc
) == 0)
461 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
462 return 0; /* Unknown */
464 sal
= find_pc_line (func_addr
, 0);
466 if (sal
.end
< func_end
)
469 /* The line after the prologue is after the end of the function. In this
470 case, tell the caller to find the prologue the hard way. */
475 /* Decode a MIPS32 instruction that saves a register in the stack, and
476 set the appropriate bit in the general register mask or float register mask
477 to indicate which register is saved. This is a helper function
478 for mips_find_saved_regs. */
481 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
483 unsigned long *gen_mask
;
484 unsigned long *float_mask
;
488 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
489 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
490 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
492 /* It might be possible to use the instruction to
493 find the offset, rather than the code below which
494 is based on things being in a certain order in the
495 frame, but figuring out what the instruction's offset
496 is relative to might be a little tricky. */
497 reg
= (inst
& 0x001f0000) >> 16;
498 *gen_mask
|= (1 << reg
);
500 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
501 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
502 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
505 reg
= ((inst
& 0x001f0000) >> 16);
506 *float_mask
|= (1 << reg
);
510 /* Decode a MIPS16 instruction that saves a register in the stack, and
511 set the appropriate bit in the general register or float register mask
512 to indicate which register is saved. This is a helper function
513 for mips_find_saved_regs. */
516 mips16_decode_reg_save (inst
, gen_mask
)
518 unsigned long *gen_mask
;
520 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
522 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
523 *gen_mask
|= (1 << reg
);
525 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
527 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
528 *gen_mask
|= (1 << reg
);
530 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
531 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
532 *gen_mask
|= (1 << RA_REGNUM
);
536 /* Fetch and return instruction from the specified location. If the PC
537 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
540 mips_fetch_instruction (addr
)
543 char buf
[MIPS_INSTLEN
];
547 if (pc_is_mips16 (addr
))
549 instlen
= MIPS16_INSTLEN
;
550 addr
= UNMAKE_MIPS16_ADDR (addr
);
553 instlen
= MIPS_INSTLEN
;
554 status
= read_memory_nobpt (addr
, buf
, instlen
);
556 memory_error (status
, addr
);
557 return extract_unsigned_integer (buf
, instlen
);
561 /* These the fields of 32 bit mips instructions */
562 #define mips32_op(x) (x >> 25)
563 #define itype_op(x) (x >> 25)
564 #define itype_rs(x) ((x >> 21)& 0x1f)
565 #define itype_rt(x) ((x >> 16) & 0x1f)
566 #define itype_immediate(x) ( x & 0xffff)
568 #define jtype_op(x) (x >> 25)
569 #define jtype_target(x) ( x & 0x03fffff)
571 #define rtype_op(x) (x >>25)
572 #define rtype_rs(x) ((x>>21) & 0x1f)
573 #define rtype_rt(x) ((x>>16) & 0x1f)
574 #define rtype_rd(x) ((x>>11) & 0x1f)
575 #define rtype_shamt(x) ((x>>6) & 0x1f)
576 #define rtype_funct(x) (x & 0x3f )
579 mips32_relative_offset (unsigned long inst
)
582 x
= itype_immediate (inst
);
583 if (x
& 0x8000) /* sign bit set */
585 x
|= 0xffff0000; /* sign extension */
591 /* Determine whate to set a single step breakpoint while considering
594 mips32_next_pc (CORE_ADDR pc
)
598 inst
= mips_fetch_instruction (pc
);
599 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
601 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
603 op
= ((inst
>> 25) & 0x03);
607 goto equal_branch
; /* BEQL */
609 goto neq_branch
; /* BNEZ */
611 goto less_branch
; /* BLEZ */
613 goto greater_branch
; /* BGTZ */
619 pc
+= 4; /* Not a branch, next instruction is easy */
622 { /* This gets way messy */
624 /* Further subdivide into SPECIAL, REGIMM and other */
625 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
627 case 0: /* SPECIAL */
628 op
= rtype_funct (inst
);
633 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
639 break; /* end special */
642 op
= jtype_op (inst
); /* branch condition */
643 switch (jtype_op (inst
))
647 case 16: /* BLTZALL */
648 case 18: /* BLTZALL */
650 if (read_register (itype_rs (inst
)) < 0)
651 pc
+= mips32_relative_offset (inst
) + 4;
653 pc
+= 8; /* after the delay slot */
657 case 17: /* BGEZAL */
658 case 19: /* BGEZALL */
659 greater_equal_branch
:
660 if (read_register (itype_rs (inst
)) >= 0)
661 pc
+= mips32_relative_offset (inst
) + 4;
663 pc
+= 8; /* after the delay slot */
665 /* All of the other intructions in the REGIMM catagory */
670 break; /* end REGIMM */
675 reg
= jtype_target (inst
) << 2;
676 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
677 /* Whats this mysterious 0xf000000 adjustment ??? */
680 /* FIXME case JALX : */
683 reg
= jtype_target (inst
) << 2;
684 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
685 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
687 break; /* The new PC will be alternate mode */
688 case 4: /* BEQ , BEQL */
690 if (read_register (itype_rs (inst
)) ==
691 read_register (itype_rt (inst
)))
692 pc
+= mips32_relative_offset (inst
) + 4;
696 case 5: /* BNE , BNEL */
698 if (read_register (itype_rs (inst
)) !=
699 read_register (itype_rs (inst
)))
700 pc
+= mips32_relative_offset (inst
) + 4;
704 case 6: /* BLEZ , BLEZL */
706 if (read_register (itype_rs (inst
) <= 0))
707 pc
+= mips32_relative_offset (inst
) + 4;
712 greater_branch
: /* BGTZ BGTZL */
713 if (read_register (itype_rs (inst
) > 0))
714 pc
+= mips32_relative_offset (inst
) + 4;
723 } /* mips32_next_pc */
725 /* Decoding the next place to set a breakpoint is irregular for the
726 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
727 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
728 We dont want to set a single step instruction on the extend instruction
732 /* Lots of mips16 instruction formats */
733 /* Predicting jumps requires itype,ritype,i8type
734 and their extensions extItype,extritype,extI8type
736 enum mips16_inst_fmts
738 itype
, /* 0 immediate 5,10 */
739 ritype
, /* 1 5,3,8 */
740 rrtype
, /* 2 5,3,3,5 */
741 rritype
, /* 3 5,3,3,5 */
742 rrrtype
, /* 4 5,3,3,3,2 */
743 rriatype
, /* 5 5,3,3,1,4 */
744 shifttype
, /* 6 5,3,3,3,2 */
745 i8type
, /* 7 5,3,8 */
746 i8movtype
, /* 8 5,3,3,5 */
747 i8mov32rtype
, /* 9 5,3,5,3 */
748 i64type
, /* 10 5,3,8 */
749 ri64type
, /* 11 5,3,3,5 */
750 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
751 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
752 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
753 extRRItype
, /* 15 5,5,5,5,3,3,5 */
754 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
755 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
756 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
757 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
758 extRi64type
, /* 20 5,6,5,5,3,3,5 */
759 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
761 /* I am heaping all the fields of the formats into one structure and then,
762 only the fields which are involved in instruction extension */
766 enum mips16_inst_fmts fmt
;
767 unsigned long offset
;
768 unsigned int regx
; /* Function in i8 type */
775 print_unpack (char *comment
,
776 struct upk_mips16
*u
)
778 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
779 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
782 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
783 format for the bits which make up the immediatate extension.
786 extended_offset (unsigned long extension
)
789 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
791 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
793 value
|= extension
& 0x01f; /* extract 4:0 */
797 /* Only call this function if you know that this is an extendable
798 instruction, It wont malfunction, but why make excess remote memory references?
799 If the immediate operands get sign extended or somthing, do it after
800 the extension is performed.
802 /* FIXME: Every one of these cases needs to worry about sign extension
803 when the offset is to be used in relative addressing */
806 static unsigned short
807 fetch_mips_16 (CORE_ADDR pc
)
810 pc
&= 0xfffffffe; /* clear the low order bit */
811 target_read_memory (pc
, buf
, 2);
812 return extract_unsigned_integer (buf
, 2);
816 unpack_mips16 (CORE_ADDR pc
,
817 struct upk_mips16
*upk
)
820 unsigned long extension
;
822 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
823 /* Decrement to previous address and loose the 16bit mode flag */
824 /* return if the instruction was extendable, but not actually extended */
825 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
828 extension
= mips_fetch_instruction (extpc
);
837 value
= extended_offset (extension
);
838 value
= value
<< 11; /* rom for the original value */
839 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
843 value
= upk
->inst
& 0x7ff;
844 /* FIXME : Consider sign extension */
851 { /* A register identifier and an offset */
852 /* Most of the fields are the same as I type but the
853 immediate value is of a different length */
857 value
= extended_offset (extension
);
858 value
= value
<< 8; /* from the original instruction */
859 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
860 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
861 if (value
& 0x4000) /* test the sign bit , bit 26 */
863 value
&= ~0x3fff; /* remove the sign bit */
869 value
= upk
->inst
& 0xff; /* 8 bits */
870 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
871 /* FIXME: Do sign extension , this format needs it */
872 if (value
& 0x80) /* THIS CONFUSES ME */
874 value
&= 0xef; /* remove the sign bit */
885 unsigned short nexthalf
;
886 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
888 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
894 printf_filtered ("Decoding unimplemented instruction format type\n");
897 /* print_unpack("UPK",upk) ; */
901 #define mips16_op(x) (x >> 11)
903 /* This is a map of the opcodes which ae known to perform branches */
904 static unsigned char map16
[32] =
905 {0, 0, 1, 1, 1, 1, 0, 0,
906 0, 0, 0, 0, 1, 0, 0, 0,
907 0, 0, 0, 0, 0, 0, 0, 0,
908 0, 0, 0, 0, 0, 1, 1, 0
912 add_offset_16 (CORE_ADDR pc
, int offset
)
914 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
920 static struct upk_mips16 upk
;
923 mips16_next_pc (CORE_ADDR pc
)
927 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
928 inst
= fetch_mips_16 (pc
);
930 op
= mips16_op (upk
.inst
);
938 unpack_mips16 (pc
, &upk
);
947 pc
+= (offset
<< 1) + 2;
950 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
952 unpack_mips16 (pc
, &upk
);
953 pc
= add_offset_16 (pc
, upk
.offset
);
954 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
955 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
961 unpack_mips16 (pc
, &upk
);
962 reg
= read_register (upk
.regx
);
964 pc
+= (upk
.offset
<< 1) + 2;
970 unpack_mips16 (pc
, &upk
);
971 reg
= read_register (upk
.regx
);
973 pc
+= (upk
.offset
<< 1) + 2;
977 case 12: /* I8 Formats btez btnez */
979 unpack_mips16 (pc
, &upk
);
980 /* upk.regx contains the opcode */
981 reg
= read_register (24); /* Test register is 24 */
982 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
983 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
984 /* pc = add_offset_16(pc,upk.offset) ; */
985 pc
+= (upk
.offset
<< 1) + 2;
989 case 29: /* RR Formats JR, JALR, JALR-RA */
991 op
= upk
.inst
& 0x1f;
994 upk
.regx
= (upk
.inst
>> 8) & 0x07;
995 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1003 break; /* Function return instruction */
1009 break; /* BOGUS Guess */
1011 pc
= read_register (reg
);
1016 case 30: /* This is an extend instruction */
1017 pc
+= 4; /* Dont be setting breakpints on the second half */
1020 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1026 pc
+= 2; /* just a good old instruction */
1027 /* See if we CAN actually break on the next instruction */
1028 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1030 } /* mips16_next_pc */
1032 /* The mips_next_pc function supports single_tep when the remote target monitor or
1033 stub is not developed enough to so a single_step.
1034 It works by decoding the current instruction and predicting where a branch
1035 will go. This isnt hard because all the data is available.
1036 The MIPS32 and MIPS16 variants are quite different
1039 mips_next_pc (CORE_ADDR pc
)
1042 /* inst = mips_fetch_instruction(pc) ; */
1043 /* if (pc_is_mips16) <----- This is failing */
1045 return mips16_next_pc (pc
);
1047 return mips32_next_pc (pc
);
1048 } /* mips_next_pc */
1050 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1054 mips_find_saved_regs (fci
)
1055 struct frame_info
*fci
;
1058 CORE_ADDR reg_position
;
1059 /* r0 bit means kernel trap */
1061 /* What registers have been saved? Bitmasks. */
1062 unsigned long gen_mask
, float_mask
;
1063 mips_extra_func_info_t proc_desc
;
1066 frame_saved_regs_zalloc (fci
);
1068 /* If it is the frame for sigtramp, the saved registers are located
1069 in a sigcontext structure somewhere on the stack.
1070 If the stack layout for sigtramp changes we might have to change these
1071 constants and the companion fixup_sigtramp in mdebugread.c */
1072 #ifndef SIGFRAME_BASE
1073 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1074 above the sigtramp frame. */
1075 #define SIGFRAME_BASE MIPS_REGSIZE
1076 /* FIXME! Are these correct?? */
1077 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1078 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1079 #define SIGFRAME_FPREGSAVE_OFF \
1080 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1082 #ifndef SIGFRAME_REG_SIZE
1083 /* FIXME! Is this correct?? */
1084 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1086 if (fci
->signal_handler_caller
)
1088 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1090 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1091 + ireg
* SIGFRAME_REG_SIZE
;
1092 fci
->saved_regs
[ireg
] = reg_position
;
1094 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1096 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1097 + ireg
* SIGFRAME_REG_SIZE
;
1098 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1100 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1104 proc_desc
= fci
->extra_info
->proc_desc
;
1105 if (proc_desc
== NULL
)
1106 /* I'm not sure how/whether this can happen. Normally when we can't
1107 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1108 and set the saved_regs right away. */
1111 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1112 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1113 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1115 if ( /* In any frame other than the innermost or a frame interrupted by
1116 a signal, we assume that all registers have been saved.
1117 This assumes that all register saves in a function happen before
1118 the first function call. */
1119 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1121 /* In a dummy frame we know exactly where things are saved. */
1122 && !PROC_DESC_IS_DUMMY (proc_desc
)
1124 /* Don't bother unless we are inside a function prologue. Outside the
1125 prologue, we know where everything is. */
1127 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1129 /* Not sure exactly what kernel_trap means, but if it means
1130 the kernel saves the registers without a prologue doing it,
1131 we better not examine the prologue to see whether registers
1132 have been saved yet. */
1135 /* We need to figure out whether the registers that the proc_desc
1136 claims are saved have been saved yet. */
1140 /* Bitmasks; set if we have found a save for the register. */
1141 unsigned long gen_save_found
= 0;
1142 unsigned long float_save_found
= 0;
1145 /* If the address is odd, assume this is MIPS16 code. */
1146 addr
= PROC_LOW_ADDR (proc_desc
);
1147 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1149 /* Scan through this function's instructions preceding the current
1150 PC, and look for those that save registers. */
1151 while (addr
< fci
->pc
)
1153 inst
= mips_fetch_instruction (addr
);
1154 if (pc_is_mips16 (addr
))
1155 mips16_decode_reg_save (inst
, &gen_save_found
);
1157 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1160 gen_mask
= gen_save_found
;
1161 float_mask
= float_save_found
;
1164 /* Fill in the offsets for the registers which gen_mask says
1166 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1167 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1168 if (gen_mask
& 0x80000000)
1170 fci
->saved_regs
[ireg
] = reg_position
;
1171 reg_position
-= MIPS_SAVED_REGSIZE
;
1174 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1175 of that normally used by gcc. Therefore, we have to fetch the first
1176 instruction of the function, and if it's an entry instruction that
1177 saves $s0 or $s1, correct their saved addresses. */
1178 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1180 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1181 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1184 int sreg_count
= (inst
>> 6) & 3;
1186 /* Check if the ra register was pushed on the stack. */
1187 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1189 reg_position
-= MIPS_SAVED_REGSIZE
;
1191 /* Check if the s0 and s1 registers were pushed on the stack. */
1192 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1194 fci
->saved_regs
[reg
] = reg_position
;
1195 reg_position
-= MIPS_SAVED_REGSIZE
;
1200 /* Fill in the offsets for the registers which float_mask says
1202 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1204 /* The freg_offset points to where the first *double* register
1205 is saved. So skip to the high-order word. */
1206 if (!GDB_TARGET_IS_MIPS64
)
1207 reg_position
+= MIPS_SAVED_REGSIZE
;
1209 /* Fill in the offsets for the float registers which float_mask says
1211 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1212 if (float_mask
& 0x80000000)
1214 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1215 reg_position
-= MIPS_SAVED_REGSIZE
;
1218 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1222 read_next_frame_reg (fi
, regno
)
1223 struct frame_info
*fi
;
1226 for (; fi
; fi
= fi
->next
)
1228 /* We have to get the saved sp from the sigcontext
1229 if it is a signal handler frame. */
1230 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1234 if (fi
->saved_regs
== NULL
)
1235 mips_find_saved_regs (fi
);
1236 if (fi
->saved_regs
[regno
])
1237 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1240 return read_register (regno
);
1243 /* mips_addr_bits_remove - remove useless address bits */
1246 mips_addr_bits_remove (addr
)
1249 #if GDB_TARGET_IS_MIPS64
1250 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1252 /* This hack is a work-around for existing boards using PMON,
1253 the simulator, and any other 64-bit targets that doesn't have
1254 true 64-bit addressing. On these targets, the upper 32 bits
1255 of addresses are ignored by the hardware. Thus, the PC or SP
1256 are likely to have been sign extended to all 1s by instruction
1257 sequences that load 32-bit addresses. For example, a typical
1258 piece of code that loads an address is this:
1259 lui $r2, <upper 16 bits>
1260 ori $r2, <lower 16 bits>
1261 But the lui sign-extends the value such that the upper 32 bits
1262 may be all 1s. The workaround is simply to mask off these bits.
1263 In the future, gcc may be changed to support true 64-bit
1264 addressing, and this masking will have to be disabled. */
1265 addr
&= (CORE_ADDR
) 0xffffffff;
1268 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1269 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1270 So we still have to mask off useless bits from addresses. */
1271 addr
&= (CORE_ADDR
) 0xffffffff;
1278 mips_init_frame_pc_first (fromleaf
, prev
)
1280 struct frame_info
*prev
;
1284 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1285 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1286 tmp
= mips_skip_stub (pc
);
1287 prev
->pc
= tmp
? tmp
: pc
;
1292 mips_frame_saved_pc (frame
)
1293 struct frame_info
*frame
;
1296 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1297 /* We have to get the saved pc from the sigcontext
1298 if it is a signal handler frame. */
1299 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1300 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1302 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1303 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1305 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1307 return ADDR_BITS_REMOVE (saved_pc
);
1310 static struct mips_extra_func_info temp_proc_desc
;
1311 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1313 /* Set a register's saved stack address in temp_saved_regs. If an address
1314 has already been set for this register, do nothing; this way we will
1315 only recognize the first save of a given register in a function prologue.
1316 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1319 set_reg_offset (regno
, offset
)
1323 if (temp_saved_regs
[regno
] == 0)
1324 temp_saved_regs
[regno
] = offset
;
1328 /* Test whether the PC points to the return instruction at the
1329 end of a function. */
1332 mips_about_to_return (pc
)
1335 if (pc_is_mips16 (pc
))
1336 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1337 generates a "jr $ra"; other times it generates code to load
1338 the return address from the stack to an accessible register (such
1339 as $a3), then a "jr" using that register. This second case
1340 is almost impossible to distinguish from an indirect jump
1341 used for switch statements, so we don't even try. */
1342 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1344 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1348 /* This fencepost looks highly suspicious to me. Removing it also
1349 seems suspicious as it could affect remote debugging across serial
1353 heuristic_proc_start (pc
)
1361 pc
= ADDR_BITS_REMOVE (pc
);
1363 fence
= start_pc
- heuristic_fence_post
;
1367 if (heuristic_fence_post
== UINT_MAX
1368 || fence
< VM_MIN_ADDRESS
)
1369 fence
= VM_MIN_ADDRESS
;
1371 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1373 /* search back for previous return */
1374 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1375 if (start_pc
< fence
)
1377 /* It's not clear to me why we reach this point when
1378 stop_soon_quietly, but with this test, at least we
1379 don't print out warnings for every child forked (eg, on
1380 decstation). 22apr93 rich@cygnus.com. */
1381 if (!stop_soon_quietly
)
1383 static int blurb_printed
= 0;
1385 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1390 /* This actually happens frequently in embedded
1391 development, when you first connect to a board
1392 and your stack pointer and pc are nowhere in
1393 particular. This message needs to give people
1394 in that situation enough information to
1395 determine that it's no big deal. */
1396 printf_filtered ("\n\
1397 GDB is unable to find the start of the function at 0x%s\n\
1398 and thus can't determine the size of that function's stack frame.\n\
1399 This means that GDB may be unable to access that stack frame, or\n\
1400 the frames below it.\n\
1401 This problem is most likely caused by an invalid program counter or\n\
1403 However, if you think GDB should simply search farther back\n\
1404 from 0x%s for code which looks like the beginning of a\n\
1405 function, you can increase the range of the search using the `set\n\
1406 heuristic-fence-post' command.\n",
1407 paddr_nz (pc
), paddr_nz (pc
));
1414 else if (pc_is_mips16 (start_pc
))
1416 unsigned short inst
;
1418 /* On MIPS16, any one of the following is likely to be the
1419 start of a function:
1423 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1424 inst
= mips_fetch_instruction (start_pc
);
1425 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1426 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1427 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1428 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1430 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1431 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1436 else if (mips_about_to_return (start_pc
))
1438 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1443 /* skip nops (usually 1) 0 - is this */
1444 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1445 start_pc
+= MIPS_INSTLEN
;
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_heuristic_proc_desc. */
1456 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1457 unsigned short prev_inst
; /* previous instruction */
1458 unsigned short inst
; /* current instruction */
1459 int nbits
; /* number of bits in imm field */
1460 int scale
; /* scale factor to be applied to imm */
1461 int is_signed
; /* is the imm field signed? */
1465 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1467 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1468 if (offset
& 0x8000) /* check for negative extend */
1469 offset
= 0 - (0x10000 - (offset
& 0xffff));
1470 return offset
| (inst
& 0x1f);
1474 int max_imm
= 1 << nbits
;
1475 int mask
= max_imm
- 1;
1476 int sign_bit
= max_imm
>> 1;
1478 offset
= inst
& mask
;
1479 if (is_signed
&& (offset
& sign_bit
))
1480 offset
= 0 - (max_imm
- offset
);
1481 return offset
* scale
;
1486 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1487 stream from start_pc to limit_pc. */
1490 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1491 CORE_ADDR start_pc
, limit_pc
;
1492 struct frame_info
*next_frame
;
1496 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1497 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1498 unsigned inst
= 0; /* current instruction */
1499 unsigned entry_inst
= 0; /* the entry instruction */
1502 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1503 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1505 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1507 /* Save the previous instruction. If it's an EXTEND, we'll extract
1508 the immediate offset extension from it in mips16_get_imm. */
1511 /* Fetch and decode the instruction. */
1512 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1513 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1514 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1516 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1517 if (offset
< 0) /* negative stack adjustment? */
1518 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1520 /* Exit loop if a positive stack adjustment is found, which
1521 usually means that the stack cleanup code in the function
1522 epilogue is reached. */
1525 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1527 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1528 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1529 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1530 set_reg_offset (reg
, sp
+ offset
);
1532 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1534 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1535 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1536 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1537 set_reg_offset (reg
, sp
+ offset
);
1539 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1541 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1542 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1543 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1545 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1547 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1548 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1549 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1551 else if (inst
== 0x673d) /* move $s1, $sp */
1554 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1556 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1558 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1559 frame_addr
= sp
+ offset
;
1560 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1561 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1563 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1565 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1566 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1567 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1568 set_reg_offset (reg
, frame_addr
+ offset
);
1570 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1572 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1573 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1574 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1575 set_reg_offset (reg
, frame_addr
+ offset
);
1577 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1578 entry_inst
= inst
; /* save for later processing */
1579 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1580 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1583 /* The entry instruction is typically the first instruction in a function,
1584 and it stores registers at offsets relative to the value of the old SP
1585 (before the prologue). But the value of the sp parameter to this
1586 function is the new SP (after the prologue has been executed). So we
1587 can't calculate those offsets until we've seen the entire prologue,
1588 and can calculate what the old SP must have been. */
1589 if (entry_inst
!= 0)
1591 int areg_count
= (entry_inst
>> 8) & 7;
1592 int sreg_count
= (entry_inst
>> 6) & 3;
1594 /* The entry instruction always subtracts 32 from the SP. */
1595 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1597 /* Now we can calculate what the SP must have been at the
1598 start of the function prologue. */
1599 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1601 /* Check if a0-a3 were saved in the caller's argument save area. */
1602 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1604 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1605 set_reg_offset (reg
, sp
+ offset
);
1606 offset
+= MIPS_SAVED_REGSIZE
;
1609 /* Check if the ra register was pushed on the stack. */
1611 if (entry_inst
& 0x20)
1613 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1614 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1615 offset
-= MIPS_SAVED_REGSIZE
;
1618 /* Check if the s0 and s1 registers were pushed on the stack. */
1619 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1621 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1622 set_reg_offset (reg
, sp
+ offset
);
1623 offset
-= MIPS_SAVED_REGSIZE
;
1629 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1630 CORE_ADDR start_pc
, limit_pc
;
1631 struct frame_info
*next_frame
;
1635 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1637 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1638 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1639 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1640 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1642 unsigned long inst
, high_word
, low_word
;
1645 /* Fetch the instruction. */
1646 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1648 /* Save some code by pre-extracting some useful fields. */
1649 high_word
= (inst
>> 16) & 0xffff;
1650 low_word
= inst
& 0xffff;
1651 reg
= high_word
& 0x1f;
1653 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1654 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1655 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1657 if (low_word
& 0x8000) /* negative stack adjustment? */
1658 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1660 /* Exit loop if a positive stack adjustment is found, which
1661 usually means that the stack cleanup code in the function
1662 epilogue is reached. */
1665 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1667 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1668 set_reg_offset (reg
, sp
+ low_word
);
1670 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1672 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1673 but the register size used is only 32 bits. Make the address
1674 for the saved register point to the lower 32 bits. */
1675 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1676 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1678 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1680 /* Old gcc frame, r30 is virtual frame pointer. */
1681 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1682 frame_addr
= sp
+ low_word
;
1683 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1685 unsigned alloca_adjust
;
1686 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1687 frame_addr
= read_next_frame_reg (next_frame
, 30);
1688 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1689 if (alloca_adjust
> 0)
1691 /* FP > SP + frame_size. This may be because
1692 * of an alloca or somethings similar.
1693 * Fix sp to "pre-alloca" value, and try again.
1695 sp
+= alloca_adjust
;
1700 /* move $30,$sp. With different versions of gas this will be either
1701 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1702 Accept any one of these. */
1703 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1705 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1706 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1708 unsigned alloca_adjust
;
1709 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1710 frame_addr
= read_next_frame_reg (next_frame
, 30);
1711 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1712 if (alloca_adjust
> 0)
1714 /* FP > SP + frame_size. This may be because
1715 * of an alloca or somethings similar.
1716 * Fix sp to "pre-alloca" value, and try again.
1718 sp
+= alloca_adjust
;
1723 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1725 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1726 set_reg_offset (reg
, frame_addr
+ low_word
);
1731 static mips_extra_func_info_t
1732 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1733 CORE_ADDR start_pc
, limit_pc
;
1734 struct frame_info
*next_frame
;
1736 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1740 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1741 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1742 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1743 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1744 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1746 if (start_pc
+ 200 < limit_pc
)
1747 limit_pc
= start_pc
+ 200;
1748 if (pc_is_mips16 (start_pc
))
1749 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1751 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1752 return &temp_proc_desc
;
1755 static mips_extra_func_info_t
1756 non_heuristic_proc_desc (pc
, addrptr
)
1760 CORE_ADDR startaddr
;
1761 mips_extra_func_info_t proc_desc
;
1762 struct block
*b
= block_for_pc (pc
);
1765 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1767 *addrptr
= startaddr
;
1768 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1772 if (startaddr
> BLOCK_START (b
))
1773 /* This is the "pathological" case referred to in a comment in
1774 print_frame_info. It might be better to move this check into
1778 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1781 /* If we never found a PDR for this function in symbol reading, then
1782 examine prologues to find the information. */
1785 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1786 if (PROC_FRAME_REG (proc_desc
) == -1)
1796 static mips_extra_func_info_t
1797 find_proc_desc (pc
, next_frame
)
1799 struct frame_info
*next_frame
;
1801 mips_extra_func_info_t proc_desc
;
1802 CORE_ADDR startaddr
;
1804 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1808 /* IF this is the topmost frame AND
1809 * (this proc does not have debugging information OR
1810 * the PC is in the procedure prologue)
1811 * THEN create a "heuristic" proc_desc (by analyzing
1812 * the actual code) to replace the "official" proc_desc.
1814 if (next_frame
== NULL
)
1816 struct symtab_and_line val
;
1817 struct symbol
*proc_symbol
=
1818 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1822 val
= find_pc_line (BLOCK_START
1823 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1825 val
.pc
= val
.end
? val
.end
: pc
;
1827 if (!proc_symbol
|| pc
< val
.pc
)
1829 mips_extra_func_info_t found_heuristic
=
1830 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1832 if (found_heuristic
)
1833 proc_desc
= found_heuristic
;
1839 /* Is linked_proc_desc_table really necessary? It only seems to be used
1840 by procedure call dummys. However, the procedures being called ought
1841 to have their own proc_descs, and even if they don't,
1842 heuristic_proc_desc knows how to create them! */
1844 register struct linked_proc_info
*link
;
1846 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1847 if (PROC_LOW_ADDR (&link
->info
) <= pc
1848 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1852 startaddr
= heuristic_proc_start (pc
);
1855 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1861 get_frame_pointer (frame
, proc_desc
)
1862 struct frame_info
*frame
;
1863 mips_extra_func_info_t proc_desc
;
1865 return ADDR_BITS_REMOVE (
1866 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1867 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1870 mips_extra_func_info_t cached_proc_desc
;
1873 mips_frame_chain (frame
)
1874 struct frame_info
*frame
;
1876 mips_extra_func_info_t proc_desc
;
1878 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1880 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1883 /* Check if the PC is inside a call stub. If it is, fetch the
1884 PC of the caller of that stub. */
1885 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1888 /* Look up the procedure descriptor for this PC. */
1889 proc_desc
= find_proc_desc (saved_pc
, frame
);
1893 cached_proc_desc
= proc_desc
;
1895 /* If no frame pointer and frame size is zero, we must be at end
1896 of stack (or otherwise hosed). If we don't check frame size,
1897 we loop forever if we see a zero size frame. */
1898 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1899 && PROC_FRAME_OFFSET (proc_desc
) == 0
1900 /* The previous frame from a sigtramp frame might be frameless
1901 and have frame size zero. */
1902 && !frame
->signal_handler_caller
)
1905 return get_frame_pointer (frame
, proc_desc
);
1909 mips_init_extra_frame_info (fromleaf
, fci
)
1911 struct frame_info
*fci
;
1915 /* Use proc_desc calculated in frame_chain */
1916 mips_extra_func_info_t proc_desc
=
1917 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1919 fci
->extra_info
= (struct frame_extra_info
*)
1920 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1922 fci
->saved_regs
= NULL
;
1923 fci
->extra_info
->proc_desc
=
1924 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1927 /* Fixup frame-pointer - only needed for top frame */
1928 /* This may not be quite right, if proc has a real frame register.
1929 Get the value of the frame relative sp, procedure might have been
1930 interrupted by a signal at it's very start. */
1931 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1932 && !PROC_DESC_IS_DUMMY (proc_desc
))
1933 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1935 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1937 if (proc_desc
== &temp_proc_desc
)
1941 /* Do not set the saved registers for a sigtramp frame,
1942 mips_find_saved_registers will do that for us.
1943 We can't use fci->signal_handler_caller, it is not yet set. */
1944 find_pc_partial_function (fci
->pc
, &name
,
1945 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1946 if (!IN_SIGTRAMP (fci
->pc
, name
))
1948 frame_saved_regs_zalloc (fci
);
1949 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1950 fci
->saved_regs
[PC_REGNUM
]
1951 = fci
->saved_regs
[RA_REGNUM
];
1955 /* hack: if argument regs are saved, guess these contain args */
1956 /* assume we can't tell how many args for now */
1957 fci
->extra_info
->num_args
= -1;
1958 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1960 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1962 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1969 /* MIPS stack frames are almost impenetrable. When execution stops,
1970 we basically have to look at symbol information for the function
1971 that we stopped in, which tells us *which* register (if any) is
1972 the base of the frame pointer, and what offset from that register
1973 the frame itself is at.
1975 This presents a problem when trying to examine a stack in memory
1976 (that isn't executing at the moment), using the "frame" command. We
1977 don't have a PC, nor do we have any registers except SP.
1979 This routine takes two arguments, SP and PC, and tries to make the
1980 cached frames look as if these two arguments defined a frame on the
1981 cache. This allows the rest of info frame to extract the important
1982 arguments without difficulty. */
1985 setup_arbitrary_frame (argc
, argv
)
1990 error ("MIPS frame specifications require two arguments: sp and pc");
1992 return create_new_frame (argv
[0], argv
[1]);
1996 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1998 * For n32 ABI, eight.
1999 * For all others, he same as the size of a general register.
2001 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
2002 #define MIPS_NABI32 1
2003 #define STACK_ARGSIZE 8
2005 #define MIPS_NABI32 0
2006 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
2010 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2015 CORE_ADDR struct_addr
;
2021 int stack_offset
= 0;
2023 /* Macros to round N up or down to the next A boundary; A must be
2025 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2026 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2028 /* First ensure that the stack and structure return address (if any)
2029 are properly aligned. The stack has to be at least 64-bit aligned
2030 even on 32-bit machines, because doubles must be 64-bit aligned.
2031 On at least one MIPS variant, stack frames need to be 128-bit
2032 aligned, so we round to this widest known alignment. */
2033 sp
= ROUND_DOWN (sp
, 16);
2034 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
2036 /* Now make space on the stack for the args. We allocate more
2037 than necessary for EABI, because the first few arguments are
2038 passed in registers, but that's OK. */
2039 for (argnum
= 0; argnum
< nargs
; argnum
++)
2040 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
2041 sp
-= ROUND_UP (len
, 16);
2043 /* Initialize the integer and float register pointers. */
2045 float_argreg
= FPA0_REGNUM
;
2047 /* the struct_return pointer occupies the first parameter-passing reg */
2049 write_register (argreg
++, struct_addr
);
2051 /* Now load as many as possible of the first arguments into
2052 registers, and push the rest onto the stack. Loop thru args
2053 from first to last. */
2054 for (argnum
= 0; argnum
< nargs
; argnum
++)
2057 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2058 value_ptr arg
= args
[argnum
];
2059 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2060 int len
= TYPE_LENGTH (arg_type
);
2061 enum type_code typecode
= TYPE_CODE (arg_type
);
2063 /* The EABI passes structures that do not fit in a register by
2064 reference. In all other cases, pass the structure by value. */
2065 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
2066 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2068 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2069 typecode
= TYPE_CODE_PTR
;
2070 len
= MIPS_SAVED_REGSIZE
;
2074 val
= (char *) VALUE_CONTENTS (arg
);
2076 /* 32-bit ABIs always start floating point arguments in an
2077 even-numbered floating point register. */
2078 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2079 && (float_argreg
& 1))
2082 /* Floating point arguments passed in registers have to be
2083 treated specially. On 32-bit architectures, doubles
2084 are passed in register pairs; the even register gets
2085 the low word, and the odd register gets the high word.
2086 On non-EABI processors, the first two floating point arguments are
2087 also copied to general registers, because MIPS16 functions
2088 don't use float registers for arguments. This duplication of
2089 arguments in general registers can't hurt non-MIPS16 functions
2090 because those registers are normally skipped. */
2091 if (typecode
== TYPE_CODE_FLT
2092 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2093 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2095 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2097 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2098 unsigned long regval
;
2100 /* Write the low word of the double to the even register(s). */
2101 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2102 write_register (float_argreg
++, regval
);
2104 write_register (argreg
+ 1, regval
);
2106 /* Write the high word of the double to the odd register(s). */
2107 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2108 write_register (float_argreg
++, regval
);
2111 write_register (argreg
, regval
);
2118 /* This is a floating point value that fits entirely
2119 in a single register. */
2120 /* On 32 bit ABI's the float_argreg is further adjusted
2121 above to ensure that it is even register aligned. */
2122 CORE_ADDR regval
= extract_address (val
, len
);
2123 write_register (float_argreg
++, regval
);
2126 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2127 registers for each argument. The below is (my
2128 guess) to ensure that the corresponding integer
2129 register has reserved the same space. */
2130 write_register (argreg
, regval
);
2131 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2137 /* Copy the argument to general registers or the stack in
2138 register-sized pieces. Large arguments are split between
2139 registers and stack. */
2140 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2141 are treated specially: Irix cc passes them in registers
2142 where gcc sometimes puts them on the stack. For maximum
2143 compatibility, we will put them in both places. */
2145 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2146 (len
% MIPS_SAVED_REGSIZE
!= 0));
2149 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2151 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2153 /* Write this portion of the argument to the stack. */
2154 /* Should shorter than int integer values be
2155 promoted to int before being stored? */
2157 int longword_offset
= 0;
2158 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2160 if (STACK_ARGSIZE
== 8 &&
2161 (typecode
== TYPE_CODE_INT
||
2162 typecode
== TYPE_CODE_PTR
||
2163 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2164 longword_offset
= STACK_ARGSIZE
- len
;
2165 else if ((typecode
== TYPE_CODE_STRUCT
||
2166 typecode
== TYPE_CODE_UNION
) &&
2167 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2168 longword_offset
= STACK_ARGSIZE
- len
;
2171 write_memory (sp
+ stack_offset
+ longword_offset
,
2175 /* Note!!! This is NOT an else clause.
2176 Odd sized structs may go thru BOTH paths. */
2177 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2179 CORE_ADDR regval
= extract_address (val
, partial_len
);
2181 /* A non-floating-point argument being passed in a
2182 general register. If a struct or union, and if
2183 the remaining length is smaller than the register
2184 size, we have to adjust the register value on
2187 It does not seem to be necessary to do the
2188 same for integral types.
2190 Also don't do this adjustment on EABI and O64
2194 && MIPS_SAVED_REGSIZE
< 8
2195 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2196 && partial_len
< MIPS_SAVED_REGSIZE
2197 && (typecode
== TYPE_CODE_STRUCT
||
2198 typecode
== TYPE_CODE_UNION
))
2199 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2202 write_register (argreg
, regval
);
2205 /* If this is the old ABI, prevent subsequent floating
2206 point arguments from being passed in floating point
2209 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2215 /* The offset onto the stack at which we will start
2216 copying parameters (after the registers are used up)
2217 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2218 leaves room for the "home" area for register parameters.
2220 In the new EABI (and the NABI32), the 8 register parameters
2221 do not have "home" stack space reserved for them, so the
2222 stack offset does not get incremented until after
2223 we have used up the 8 parameter registers. */
2225 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2227 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2232 /* Return adjusted stack pointer. */
2237 mips_push_return_address (pc
, sp
)
2241 /* Set the return address register to point to the entry
2242 point of the program, where a breakpoint lies in wait. */
2243 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2248 mips_push_register (CORE_ADDR
* sp
, int regno
)
2250 char buffer
[MAX_REGISTER_RAW_SIZE
];
2253 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2255 regsize
= MIPS_SAVED_REGSIZE
;
2256 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2257 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2262 regsize
= REGISTER_RAW_SIZE (regno
);
2266 read_register_gen (regno
, buffer
);
2267 write_memory (*sp
, buffer
+ offset
, regsize
);
2270 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2271 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2274 mips_push_dummy_frame ()
2277 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2278 xmalloc (sizeof (struct linked_proc_info
));
2279 mips_extra_func_info_t proc_desc
= &link
->info
;
2280 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2281 CORE_ADDR old_sp
= sp
;
2282 link
->next
= linked_proc_desc_table
;
2283 linked_proc_desc_table
= link
;
2285 /* FIXME! are these correct ? */
2286 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2287 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2288 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2289 #define FLOAT_SINGLE_REG_SAVE_MASK \
2290 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2292 * The registers we must save are all those not preserved across
2293 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2294 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2295 * and FP Control/Status registers.
2298 * Dummy frame layout:
2301 * Saved MMHI, MMLO, FPC_CSR
2306 * Saved D18 (i.e. F19, F18)
2308 * Saved D0 (i.e. F1, F0)
2309 * Argument build area and stack arguments written via mips_push_arguments
2313 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2314 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2315 PROC_FRAME_OFFSET (proc_desc
) = 0;
2316 PROC_FRAME_ADJUST (proc_desc
) = 0;
2317 mips_push_register (&sp
, PC_REGNUM
);
2318 mips_push_register (&sp
, HI_REGNUM
);
2319 mips_push_register (&sp
, LO_REGNUM
);
2320 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2322 /* Save general CPU registers */
2323 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2324 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2325 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2326 for (ireg
= 32; --ireg
>= 0;)
2327 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2328 mips_push_register (&sp
, ireg
);
2330 /* Save floating point registers starting with high order word */
2331 PROC_FREG_MASK (proc_desc
) =
2332 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2333 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2334 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2336 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2337 for (ireg
= 32; --ireg
>= 0;)
2338 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2339 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2341 /* Update the frame pointer for the call dummy and the stack pointer.
2342 Set the procedure's starting and ending addresses to point to the
2343 call dummy address at the entry point. */
2344 write_register (PUSH_FP_REGNUM
, old_sp
);
2345 write_register (SP_REGNUM
, sp
);
2346 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2347 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2348 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2349 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2355 register int regnum
;
2356 struct frame_info
*frame
= get_current_frame ();
2357 CORE_ADDR new_sp
= FRAME_FP (frame
);
2359 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2361 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2362 if (frame
->saved_regs
== NULL
)
2363 mips_find_saved_regs (frame
);
2364 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2366 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2367 && frame
->saved_regs
[regnum
])
2368 write_register (regnum
,
2369 read_memory_integer (frame
->saved_regs
[regnum
],
2370 MIPS_SAVED_REGSIZE
));
2372 write_register (SP_REGNUM
, new_sp
);
2373 flush_cached_frames ();
2375 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2377 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2379 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2381 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2383 if (&pi_ptr
->info
== proc_desc
)
2388 error ("Can't locate dummy extra frame info\n");
2390 if (prev_ptr
!= NULL
)
2391 prev_ptr
->next
= pi_ptr
->next
;
2393 linked_proc_desc_table
= pi_ptr
->next
;
2397 write_register (HI_REGNUM
,
2398 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2399 MIPS_SAVED_REGSIZE
));
2400 write_register (LO_REGNUM
,
2401 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2402 MIPS_SAVED_REGSIZE
));
2403 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2404 write_register (FCRCS_REGNUM
,
2405 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2406 MIPS_SAVED_REGSIZE
));
2411 mips_print_register (regnum
, all
)
2414 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2416 /* Get the data in raw format. */
2417 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2419 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2423 /* If an even floating point register, also print as double. */
2424 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2425 && !((regnum
- FP0_REGNUM
) & 1))
2426 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2428 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2430 read_relative_register_raw_bytes (regnum
, dbuffer
);
2431 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2432 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2434 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2435 val_print (builtin_type_double
, dbuffer
, 0, 0,
2436 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2437 printf_filtered ("); ");
2439 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2441 /* The problem with printing numeric register names (r26, etc.) is that
2442 the user can't use them on input. Probably the best solution is to
2443 fix it so that either the numeric or the funky (a2, etc.) names
2444 are accepted on input. */
2445 if (regnum
< MIPS_NUMREGS
)
2446 printf_filtered ("(r%d): ", regnum
);
2448 printf_filtered (": ");
2450 /* If virtual format is floating, print it that way. */
2451 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2452 if (FP_REGISTER_DOUBLE
)
2453 { /* show 8-byte floats as float AND double: */
2454 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2456 printf_filtered (" (float) ");
2457 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2458 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2459 printf_filtered (", (double) ");
2460 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2461 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2464 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2465 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2466 /* Else print as integer in hex. */
2471 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2472 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2476 print_scalar_formatted (raw_buffer
+ offset
,
2477 REGISTER_VIRTUAL_TYPE (regnum
),
2478 'x', 0, gdb_stdout
);
2482 /* Replacement for generic do_registers_info.
2483 Print regs in pretty columns. */
2486 do_fp_register_row (regnum
)
2488 { /* do values for FP (float) regs */
2489 char *raw_buffer
[2];
2491 /* use HI and LO to control the order of combining two flt regs */
2492 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2493 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2494 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2495 int inv1
, inv2
, inv3
;
2497 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2498 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2499 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2501 /* Get the data in raw format. */
2502 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2503 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2504 if (REGISTER_RAW_SIZE (regnum
) == 4)
2506 /* 4-byte registers: we can fit two registers per row. */
2507 /* Also print every pair of 4-byte regs as an 8-byte double. */
2508 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2509 error ("can't read register %d (%s)",
2510 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2512 /* copy the two floats into one double, and unpack both */
2513 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2514 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2515 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2516 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2518 printf_filtered (inv1
? " %-5s: <invalid float>" :
2519 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2520 printf_filtered (inv2
? " %-5s: <invalid float>" :
2521 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2522 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2523 " dbl: %-24.17g\n", doub
);
2524 /* may want to do hex display here (future enhancement) */
2528 { /* eight byte registers: print each one as float AND as double. */
2529 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2531 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2532 flt1
= unpack_double (builtin_type_float
,
2533 &raw_buffer
[HI
][offset
], &inv1
);
2534 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2536 printf_filtered (inv1
? " %-5s: <invalid float>" :
2537 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2538 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2539 " dbl: %-24.17g\n", doub
);
2540 /* may want to do hex display here (future enhancement) */
2546 /* Print a row's worth of GP (int) registers, with name labels above */
2549 do_gp_register_row (regnum
)
2552 /* do values for GP (int) regs */
2553 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2554 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2556 int start_regnum
= regnum
;
2557 int numregs
= NUM_REGS
;
2560 /* For GP registers, we print a separate row of names above the vals */
2561 printf_filtered (" ");
2562 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2564 if (*REGISTER_NAME (regnum
) == '\0')
2565 continue; /* unused register */
2566 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2567 break; /* end the row: reached FP register */
2568 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2569 REGISTER_NAME (regnum
));
2572 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2573 start_regnum
); /* print the R0 to R31 names */
2575 regnum
= start_regnum
; /* go back to start of row */
2576 /* now print the values in hex, 4 or 8 to the row */
2577 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2579 if (*REGISTER_NAME (regnum
) == '\0')
2580 continue; /* unused register */
2581 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2582 break; /* end row: reached FP register */
2583 /* OK: get the data in raw format. */
2584 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2585 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2586 /* pad small registers */
2587 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2588 printf_filtered (" ");
2589 /* Now print the register value in hex, endian order. */
2590 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2591 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2592 byte
< REGISTER_RAW_SIZE (regnum
);
2594 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2596 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2599 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2600 printf_filtered (" ");
2603 if (col
> 0) /* ie. if we actually printed anything... */
2604 printf_filtered ("\n");
2609 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2612 mips_do_registers_info (regnum
, fpregs
)
2616 if (regnum
!= -1) /* do one specified register */
2618 if (*(REGISTER_NAME (regnum
)) == '\0')
2619 error ("Not a valid register for the current processor type");
2621 mips_print_register (regnum
, 0);
2622 printf_filtered ("\n");
2625 /* do all (or most) registers */
2628 while (regnum
< NUM_REGS
)
2630 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2631 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2632 regnum
= do_fp_register_row (regnum
); /* FP regs */
2634 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2636 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2641 /* Return number of args passed to a frame. described by FIP.
2642 Can return -1, meaning no way to tell. */
2645 mips_frame_num_args (frame
)
2646 struct frame_info
*frame
;
2648 #if 0 /* FIXME Use or lose this! */
2649 struct chain_info_t
*p
;
2651 p
= mips_find_cached_frame (FRAME_FP (frame
));
2653 return p
->the_info
.numargs
;
2658 /* Is this a branch with a delay slot? */
2660 static int is_delayed
PARAMS ((unsigned long));
2667 for (i
= 0; i
< NUMOPCODES
; ++i
)
2668 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2669 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2671 return (i
< NUMOPCODES
2672 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2673 | INSN_COND_BRANCH_DELAY
2674 | INSN_COND_BRANCH_LIKELY
)));
2678 mips_step_skips_delay (pc
)
2681 char buf
[MIPS_INSTLEN
];
2683 /* There is no branch delay slot on MIPS16. */
2684 if (pc_is_mips16 (pc
))
2687 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2688 /* If error reading memory, guess that it is not a delayed branch. */
2690 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2694 /* Skip the PC past function prologue instructions (32-bit version).
2695 This is a helper function for mips_skip_prologue. */
2698 mips32_skip_prologue (pc
, lenient
)
2699 CORE_ADDR pc
; /* starting PC to search from */
2704 int seen_sp_adjust
= 0;
2705 int load_immediate_bytes
= 0;
2707 /* Skip the typical prologue instructions. These are the stack adjustment
2708 instruction and the instructions that save registers on the stack
2709 or in the gcc frame. */
2710 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2712 unsigned long high_word
;
2714 inst
= mips_fetch_instruction (pc
);
2715 high_word
= (inst
>> 16) & 0xffff;
2718 if (lenient
&& is_delayed (inst
))
2722 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2723 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2725 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2726 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2728 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2729 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2730 && (inst
& 0x001F0000)) /* reg != $zero */
2733 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2735 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2737 continue; /* reg != $zero */
2739 /* move $s8,$sp. With different versions of gas this will be either
2740 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2741 Accept any one of these. */
2742 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2745 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2747 else if (high_word
== 0x3c1c) /* lui $gp,n */
2749 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2751 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2752 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2754 /* The following instructions load $at or $t0 with an immediate
2755 value in preparation for a stack adjustment via
2756 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2757 a local variable, so we accept them only before a stack adjustment
2758 instruction was seen. */
2759 else if (!seen_sp_adjust
)
2761 if (high_word
== 0x3c01 || /* lui $at,n */
2762 high_word
== 0x3c08) /* lui $t0,n */
2764 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2767 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2768 high_word
== 0x3508 || /* ori $t0,$t0,n */
2769 high_word
== 0x3401 || /* ori $at,$zero,n */
2770 high_word
== 0x3408) /* ori $t0,$zero,n */
2772 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2782 /* In a frameless function, we might have incorrectly
2783 skipped some load immediate instructions. Undo the skipping
2784 if the load immediate was not followed by a stack adjustment. */
2785 if (load_immediate_bytes
&& !seen_sp_adjust
)
2786 pc
-= load_immediate_bytes
;
2790 /* Skip the PC past function prologue instructions (16-bit version).
2791 This is a helper function for mips_skip_prologue. */
2794 mips16_skip_prologue (pc
, lenient
)
2795 CORE_ADDR pc
; /* starting PC to search from */
2799 int extend_bytes
= 0;
2800 int prev_extend_bytes
;
2802 /* Table of instructions likely to be found in a function prologue. */
2805 unsigned short inst
;
2806 unsigned short mask
;
2813 , /* addiu $sp,offset */
2817 , /* daddiu $sp,offset */
2821 , /* sw reg,n($sp) */
2825 , /* sd reg,n($sp) */
2829 , /* sw $ra,n($sp) */
2833 , /* sd $ra,n($sp) */
2841 , /* sw $a0-$a3,n($s1) */
2845 , /* move reg,$a0-$a3 */
2849 , /* entry pseudo-op */
2853 , /* addiu $s1,$sp,n */
2856 } /* end of table marker */
2859 /* Skip the typical prologue instructions. These are the stack adjustment
2860 instruction and the instructions that save registers on the stack
2861 or in the gcc frame. */
2862 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2864 unsigned short inst
;
2867 inst
= mips_fetch_instruction (pc
);
2869 /* Normally we ignore an extend instruction. However, if it is
2870 not followed by a valid prologue instruction, we must adjust
2871 the pc back over the extend so that it won't be considered
2872 part of the prologue. */
2873 if ((inst
& 0xf800) == 0xf000) /* extend */
2875 extend_bytes
= MIPS16_INSTLEN
;
2878 prev_extend_bytes
= extend_bytes
;
2881 /* Check for other valid prologue instructions besides extend. */
2882 for (i
= 0; table
[i
].mask
!= 0; i
++)
2883 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2885 if (table
[i
].mask
!= 0) /* it was in table? */
2886 continue; /* ignore it */
2890 /* Return the current pc, adjusted backwards by 2 if
2891 the previous instruction was an extend. */
2892 return pc
- prev_extend_bytes
;
2898 /* To skip prologues, I use this predicate. Returns either PC itself
2899 if the code at PC does not look like a function prologue; otherwise
2900 returns an address that (if we're lucky) follows the prologue. If
2901 LENIENT, then we must skip everything which is involved in setting
2902 up the frame (it's OK to skip more, just so long as we don't skip
2903 anything which might clobber the registers which are being saved.
2904 We must skip more in the case where part of the prologue is in the
2905 delay slot of a non-prologue instruction). */
2908 mips_skip_prologue (pc
, lenient
)
2912 /* See if we can determine the end of the prologue via the symbol table.
2913 If so, then return either PC, or the PC after the prologue, whichever
2916 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2918 if (post_prologue_pc
!= 0)
2919 return max (pc
, post_prologue_pc
);
2921 /* Can't determine prologue from the symbol table, need to examine
2924 if (pc_is_mips16 (pc
))
2925 return mips16_skip_prologue (pc
, lenient
);
2927 return mips32_skip_prologue (pc
, lenient
);
2931 /* The lenient prologue stuff should be superseded by the code in
2932 init_extra_frame_info which looks to see whether the stores mentioned
2933 in the proc_desc have actually taken place. */
2935 /* Is address PC in the prologue (loosely defined) for function at
2939 mips_in_lenient_prologue (startaddr
, pc
)
2940 CORE_ADDR startaddr
;
2943 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2944 return pc
>= startaddr
&& pc
< end_prologue
;
2948 /* Determine how a return value is stored within the MIPS register
2949 file, given the return type `valtype'. */
2951 struct return_value_word
2959 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2962 return_value_location (valtype
, hi
, lo
)
2963 struct type
*valtype
;
2964 struct return_value_word
*hi
;
2965 struct return_value_word
*lo
;
2967 int len
= TYPE_LENGTH (valtype
);
2969 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2970 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2971 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2973 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2975 /* We need to break a 64bit float in two 32 bit halves and
2976 spread them across a floating-point register pair. */
2977 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2978 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2979 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2980 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2982 hi
->reg_offset
= lo
->reg_offset
;
2983 lo
->reg
= FP0_REGNUM
+ 0;
2984 hi
->reg
= FP0_REGNUM
+ 1;
2990 /* The floating point value fits in a single floating-point
2992 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2993 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2996 lo
->reg
= FP0_REGNUM
;
3007 /* Locate a result possibly spread across two registers. */
3009 lo
->reg
= regnum
+ 0;
3010 hi
->reg
= regnum
+ 1;
3011 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3012 && len
< MIPS_SAVED_REGSIZE
)
3014 /* "un-left-justify" the value in the low register */
3015 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3020 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3021 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3022 && len
< MIPS_SAVED_REGSIZE
* 2
3023 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3024 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3026 /* "un-left-justify" the value spread across two registers. */
3027 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3028 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3030 hi
->len
= len
- lo
->len
;
3034 /* Only perform a partial copy of the second register. */
3037 if (len
> MIPS_SAVED_REGSIZE
)
3039 lo
->len
= MIPS_SAVED_REGSIZE
;
3040 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3048 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3049 && REGISTER_RAW_SIZE (regnum
) == 8
3050 && MIPS_SAVED_REGSIZE
== 4)
3052 /* Account for the fact that only the least-signficant part
3053 of the register is being used */
3054 lo
->reg_offset
+= 4;
3055 hi
->reg_offset
+= 4;
3058 hi
->buf_offset
= lo
->len
;
3062 /* Given a return value in `regbuf' with a type `valtype', extract and
3063 copy its value into `valbuf'. */
3066 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3067 struct type
*valtype
;
3068 char regbuf
[REGISTER_BYTES
];
3071 struct return_value_word lo
;
3072 struct return_value_word hi
;
3073 return_value_location (valtype
, &lo
, &hi
);
3075 memcpy (valbuf
+ lo
.buf_offset
,
3076 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3080 memcpy (valbuf
+ hi
.buf_offset
,
3081 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3087 int len
= TYPE_LENGTH (valtype
);
3090 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3091 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3092 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3093 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3094 regnum
= FP0_REGNUM
;
3096 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3097 { /* "un-left-justify" the value from the register */
3098 if (len
< REGISTER_RAW_SIZE (regnum
))
3099 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3100 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3101 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3102 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3103 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3104 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3106 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3107 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3111 /* Given a return value in `valbuf' with a type `valtype', write it's
3112 value into the appropriate register. */
3115 mips_store_return_value (valtype
, valbuf
)
3116 struct type
*valtype
;
3119 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3120 struct return_value_word lo
;
3121 struct return_value_word hi
;
3122 return_value_location (valtype
, &lo
, &hi
);
3124 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3125 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3126 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3128 REGISTER_RAW_SIZE (lo
.reg
));
3132 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3133 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3134 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3136 REGISTER_RAW_SIZE (hi
.reg
));
3142 int len
= TYPE_LENGTH (valtype
);
3143 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3146 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3147 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3148 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3149 && len
<= MIPS_REGSIZE
)))
3150 regnum
= FP0_REGNUM
;
3152 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3153 { /* "left-justify" the value in the register */
3154 if (len
< REGISTER_RAW_SIZE (regnum
))
3155 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3156 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3157 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3158 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3159 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3160 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3162 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3163 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3164 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3165 len
> REGISTER_RAW_SIZE (regnum
) ?
3166 len
: REGISTER_RAW_SIZE (regnum
));
3170 /* Exported procedure: Is PC in the signal trampoline code */
3173 in_sigtramp (pc
, ignore
)
3175 char *ignore
; /* function name */
3177 if (sigtramp_address
== 0)
3179 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3182 /* Root of all "set mips "/"show mips " commands. This will eventually be
3183 used for all MIPS-specific commands. */
3185 static void show_mips_command
PARAMS ((char *, int));
3187 show_mips_command (args
, from_tty
)
3191 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3194 static void set_mips_command
PARAMS ((char *, int));
3196 set_mips_command (args
, from_tty
)
3200 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3201 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3204 /* Commands to show/set the MIPS FPU type. */
3206 static void show_mipsfpu_command
PARAMS ((char *, int));
3208 show_mipsfpu_command (args
, from_tty
)
3214 switch (MIPS_FPU_TYPE
)
3216 case MIPS_FPU_SINGLE
:
3217 fpu
= "single-precision";
3219 case MIPS_FPU_DOUBLE
:
3220 fpu
= "double-precision";
3223 fpu
= "absent (none)";
3226 if (mips_fpu_type_auto
)
3227 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3230 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3235 static void set_mipsfpu_command
PARAMS ((char *, int));
3237 set_mipsfpu_command (args
, from_tty
)
3241 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3242 show_mipsfpu_command (args
, from_tty
);
3245 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3247 set_mipsfpu_single_command (args
, from_tty
)
3251 mips_fpu_type
= MIPS_FPU_SINGLE
;
3252 mips_fpu_type_auto
= 0;
3255 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3259 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3261 set_mipsfpu_double_command (args
, from_tty
)
3265 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3266 mips_fpu_type_auto
= 0;
3269 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3273 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3275 set_mipsfpu_none_command (args
, from_tty
)
3279 mips_fpu_type
= MIPS_FPU_NONE
;
3280 mips_fpu_type_auto
= 0;
3283 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3287 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3289 set_mipsfpu_auto_command (args
, from_tty
)
3293 mips_fpu_type_auto
= 1;
3296 /* Command to set the processor type. */
3299 mips_set_processor_type_command (args
, from_tty
)
3305 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3307 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3308 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3309 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3311 /* Restore the value. */
3312 tmp_mips_processor_type
= strsave (mips_processor_type
);
3317 if (!mips_set_processor_type (tmp_mips_processor_type
))
3319 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3320 /* Restore its value. */
3321 tmp_mips_processor_type
= strsave (mips_processor_type
);
3326 mips_show_processor_type_command (args
, from_tty
)
3332 /* Modify the actual processor type. */
3335 mips_set_processor_type (str
)
3343 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3345 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3347 mips_processor_type
= str
;
3348 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3350 /* FIXME tweak fpu flag too */
3357 /* Attempt to identify the particular processor model by reading the
3361 mips_read_processor_type ()
3365 prid
= read_register (PRID_REGNUM
);
3367 if ((prid
& ~0xf) == 0x700)
3368 return savestring ("r3041", strlen ("r3041"));
3373 /* Just like reinit_frame_cache, but with the right arguments to be
3374 callable as an sfunc. */
3377 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3380 struct cmd_list_element
*c
;
3382 reinit_frame_cache ();
3386 gdb_print_insn_mips (memaddr
, info
)
3388 disassemble_info
*info
;
3390 mips_extra_func_info_t proc_desc
;
3392 /* Search for the function containing this address. Set the low bit
3393 of the address when searching, in case we were given an even address
3394 that is the start of a 16-bit function. If we didn't do this,
3395 the search would fail because the symbol table says the function
3396 starts at an odd address, i.e. 1 byte past the given address. */
3397 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3398 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3400 /* Make an attempt to determine if this is a 16-bit function. If
3401 the procedure descriptor exists and the address therein is odd,
3402 it's definitely a 16-bit function. Otherwise, we have to just
3403 guess that if the address passed in is odd, it's 16-bits. */
3405 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3407 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3409 /* Round down the instruction address to the appropriate boundary. */
3410 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3412 /* Call the appropriate disassembler based on the target endian-ness. */
3413 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3414 return print_insn_big_mips (memaddr
, info
);
3416 return print_insn_little_mips (memaddr
, info
);
3419 /* Old-style breakpoint macros.
3420 The IDT board uses an unusual breakpoint value, and sometimes gets
3421 confused when it sees the usual MIPS breakpoint instruction. */
3423 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3424 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3425 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3426 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3427 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3428 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3429 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3430 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3432 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3433 counter value to determine whether a 16- or 32-bit breakpoint should be
3434 used. It returns a pointer to a string of bytes that encode a breakpoint
3435 instruction, stores the length of the string to *lenptr, and adjusts pc
3436 (if necessary) to point to the actual memory location where the
3437 breakpoint should be inserted. */
3440 mips_breakpoint_from_pc (pcptr
, lenptr
)
3444 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3446 if (pc_is_mips16 (*pcptr
))
3448 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3449 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3450 *lenptr
= sizeof (mips16_big_breakpoint
);
3451 return mips16_big_breakpoint
;
3455 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3456 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3457 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3459 *lenptr
= sizeof (big_breakpoint
);
3461 if (strcmp (target_shortname
, "mips") == 0)
3462 return idt_big_breakpoint
;
3463 else if (strcmp (target_shortname
, "ddb") == 0
3464 || strcmp (target_shortname
, "pmon") == 0
3465 || strcmp (target_shortname
, "lsi") == 0)
3466 return pmon_big_breakpoint
;
3468 return big_breakpoint
;
3473 if (pc_is_mips16 (*pcptr
))
3475 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3476 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3477 *lenptr
= sizeof (mips16_little_breakpoint
);
3478 return mips16_little_breakpoint
;
3482 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3483 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3484 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3486 *lenptr
= sizeof (little_breakpoint
);
3488 if (strcmp (target_shortname
, "mips") == 0)
3489 return idt_little_breakpoint
;
3490 else if (strcmp (target_shortname
, "ddb") == 0
3491 || strcmp (target_shortname
, "pmon") == 0
3492 || strcmp (target_shortname
, "lsi") == 0)
3493 return pmon_little_breakpoint
;
3495 return little_breakpoint
;
3500 /* If PC is in a mips16 call or return stub, return the address of the target
3501 PC, which is either the callee or the caller. There are several
3502 cases which must be handled:
3504 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3505 target PC is in $31 ($ra).
3506 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3507 and the target PC is in $2.
3508 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3509 before the jal instruction, this is effectively a call stub
3510 and the the target PC is in $2. Otherwise this is effectively
3511 a return stub and the target PC is in $18.
3513 See the source code for the stubs in gcc/config/mips/mips16.S for
3516 This function implements the SKIP_TRAMPOLINE_CODE macro.
3524 CORE_ADDR start_addr
;
3526 /* Find the starting address and name of the function containing the PC. */
3527 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3530 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3531 target PC is in $31 ($ra). */
3532 if (strcmp (name
, "__mips16_ret_sf") == 0
3533 || strcmp (name
, "__mips16_ret_df") == 0)
3534 return read_register (RA_REGNUM
);
3536 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3538 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3539 and the target PC is in $2. */
3540 if (name
[19] >= '0' && name
[19] <= '9')
3541 return read_register (2);
3543 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3544 before the jal instruction, this is effectively a call stub
3545 and the the target PC is in $2. Otherwise this is effectively
3546 a return stub and the target PC is in $18. */
3547 else if (name
[19] == 's' || name
[19] == 'd')
3549 if (pc
== start_addr
)
3551 /* Check if the target of the stub is a compiler-generated
3552 stub. Such a stub for a function bar might have a name
3553 like __fn_stub_bar, and might look like this:
3558 la $1,bar (becomes a lui/addiu pair)
3560 So scan down to the lui/addi and extract the target
3561 address from those two instructions. */
3563 CORE_ADDR target_pc
= read_register (2);
3567 /* See if the name of the target function is __fn_stub_*. */
3568 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3570 if (strncmp (name
, "__fn_stub_", 10) != 0
3571 && strcmp (name
, "etext") != 0
3572 && strcmp (name
, "_etext") != 0)
3575 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3576 The limit on the search is arbitrarily set to 20
3577 instructions. FIXME. */
3578 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3580 inst
= mips_fetch_instruction (target_pc
);
3581 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3582 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3583 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3584 return pc
| (inst
& 0xffff); /* low word */
3587 /* Couldn't find the lui/addui pair, so return stub address. */
3591 /* This is the 'return' part of a call stub. The return
3592 address is in $r18. */
3593 return read_register (18);
3596 return 0; /* not a stub */
3600 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3601 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3604 mips_in_call_stub (pc
, name
)
3608 CORE_ADDR start_addr
;
3610 /* Find the starting address of the function containing the PC. If the
3611 caller didn't give us a name, look it up at the same time. */
3612 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3615 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3617 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3618 if (name
[19] >= '0' && name
[19] <= '9')
3620 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3621 before the jal instruction, this is effectively a call stub. */
3622 else if (name
[19] == 's' || name
[19] == 'd')
3623 return pc
== start_addr
;
3626 return 0; /* not a stub */
3630 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3631 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3634 mips_in_return_stub (pc
, name
)
3638 CORE_ADDR start_addr
;
3640 /* Find the starting address of the function containing the PC. */
3641 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3644 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3645 if (strcmp (name
, "__mips16_ret_sf") == 0
3646 || strcmp (name
, "__mips16_ret_df") == 0)
3649 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3650 i.e. after the jal instruction, this is effectively a return stub. */
3651 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3652 && (name
[19] == 's' || name
[19] == 'd')
3653 && pc
!= start_addr
)
3656 return 0; /* not a stub */
3660 /* Return non-zero if the PC is in a library helper function that should
3661 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3664 mips_ignore_helper (pc
)
3669 /* Find the starting address and name of the function containing the PC. */
3670 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3673 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3674 that we want to ignore. */
3675 return (strcmp (name
, "__mips16_ret_sf") == 0
3676 || strcmp (name
, "__mips16_ret_df") == 0);
3680 /* Return a location where we can set a breakpoint that will be hit
3681 when an inferior function call returns. This is normally the
3682 program's entry point. Executables that don't have an entry
3683 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3684 whose address is the location where the breakpoint should be placed. */
3687 mips_call_dummy_address ()
3689 struct minimal_symbol
*sym
;
3691 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3693 return SYMBOL_VALUE_ADDRESS (sym
);
3695 return entry_point_address ();
3699 /* If the current gcc for for this target does not produce correct debugging
3700 information for float parameters, both prototyped and unprototyped, then
3701 define this macro. This forces gdb to always assume that floats are
3702 passed as doubles and then converted in the callee.
3704 For the mips chip, it appears that the debug info marks the parameters as
3705 floats regardless of whether the function is prototyped, but the actual
3706 values are passed as doubles for the non-prototyped case and floats for
3707 the prototyped case. Thus we choose to make the non-prototyped case work
3708 for C and break the prototyped case, since the non-prototyped case is
3709 probably much more common. (FIXME). */
3712 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3714 return current_language
->la_language
== language_c
;
3718 static gdbarch_init_ftype mips_gdbarch_init
;
3719 static struct gdbarch
*
3720 mips_gdbarch_init (info
, arches
)
3721 struct gdbarch_info info
;
3722 struct gdbarch_list
*arches
;
3724 static LONGEST mips_call_dummy_words
[] =
3726 struct gdbarch
*gdbarch
;
3727 struct gdbarch_tdep
*tdep
;
3730 int ef_mips_bitptrs
;
3733 /* Extract the elf_flags if available */
3734 if (info
.abfd
!= NULL
3735 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3736 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3740 /* try to find a pre-existing architecture */
3741 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3743 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3745 /* MIPS needs to be pedantic about which ABI the object is
3747 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3749 return arches
->gdbarch
;
3752 /* Need a new architecture. Fill in a target specific vector. */
3753 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3754 gdbarch
= gdbarch_alloc (&info
, tdep
);
3755 tdep
->elf_flags
= elf_flags
;
3757 /* Initially set everything according to the ABI. */
3758 set_gdbarch_short_bit (gdbarch
, 16);
3759 set_gdbarch_int_bit (gdbarch
, 32);
3760 set_gdbarch_float_bit (gdbarch
, 32);
3761 set_gdbarch_double_bit (gdbarch
, 64);
3762 set_gdbarch_long_double_bit (gdbarch
, 64);
3763 switch ((elf_flags
& EF_MIPS_ABI
))
3765 case E_MIPS_ABI_O32
:
3766 ef_mips_abi
= "o32";
3767 tdep
->mips_eabi
= 0;
3768 tdep
->mips_default_saved_regsize
= 4;
3769 tdep
->mips_fp_register_double
= 0;
3770 set_gdbarch_long_bit (gdbarch
, 32);
3771 set_gdbarch_ptr_bit (gdbarch
, 32);
3772 set_gdbarch_long_long_bit (gdbarch
, 64);
3774 case E_MIPS_ABI_O64
:
3775 ef_mips_abi
= "o64";
3776 tdep
->mips_eabi
= 0;
3777 tdep
->mips_default_saved_regsize
= 8;
3778 tdep
->mips_fp_register_double
= 1;
3779 set_gdbarch_long_bit (gdbarch
, 32);
3780 set_gdbarch_ptr_bit (gdbarch
, 32);
3781 set_gdbarch_long_long_bit (gdbarch
, 64);
3783 case E_MIPS_ABI_EABI32
:
3784 ef_mips_abi
= "eabi32";
3785 tdep
->mips_eabi
= 1;
3786 tdep
->mips_default_saved_regsize
= 4;
3787 tdep
->mips_fp_register_double
= 0;
3788 set_gdbarch_long_bit (gdbarch
, 32);
3789 set_gdbarch_ptr_bit (gdbarch
, 32);
3790 set_gdbarch_long_long_bit (gdbarch
, 64);
3792 case E_MIPS_ABI_EABI64
:
3793 ef_mips_abi
= "eabi64";
3794 tdep
->mips_eabi
= 1;
3795 tdep
->mips_default_saved_regsize
= 8;
3796 tdep
->mips_fp_register_double
= 1;
3797 set_gdbarch_long_bit (gdbarch
, 64);
3798 set_gdbarch_ptr_bit (gdbarch
, 64);
3799 set_gdbarch_long_long_bit (gdbarch
, 64);
3802 ef_mips_abi
= "default";
3803 tdep
->mips_eabi
= 0;
3804 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
3805 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3806 set_gdbarch_long_bit (gdbarch
, 32);
3807 set_gdbarch_ptr_bit (gdbarch
, 32);
3808 set_gdbarch_long_long_bit (gdbarch
, 64);
3812 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
3813 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
3816 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
3817 flag in object files because to do so would make it impossible to
3818 link with libraries compiled without "-gp32". This is
3819 unnecessarily restrictive.
3821 We could solve this problem by adding "-gp32" multilibs to gcc,
3822 but to set this flag before gcc is built with such multilibs will
3823 break too many systems.''
3825 But even more unhelpfully, the default linker output target for
3826 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
3827 for 64-bit programs - you need to change the ABI to change this,
3828 and not all gcc targets support that currently. Therefore using
3829 this flag to detect 32-bit mode would do the wrong thing given
3830 the current gcc - it would make GDB treat these 64-bit programs
3831 as 32-bit programs by default. */
3833 /* determine the ISA */
3834 switch (elf_flags
& EF_MIPS_ARCH
)
3853 /* determine the size of a pointer */
3854 if ((elf_flags
& EF_MIPS_32BITPTRS
))
3856 ef_mips_bitptrs
= 32;
3858 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
3860 ef_mips_bitptrs
= 64;
3864 ef_mips_bitptrs
= 0;
3868 /* Select either of the two alternative ABI's */
3869 if (tdep
->mips_eabi
)
3871 /* EABI uses R4 through R11 for args */
3872 tdep
->mips_last_arg_regnum
= 11;
3873 /* EABI uses F12 through F19 for args */
3874 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3878 /* old ABI uses R4 through R7 for args */
3879 tdep
->mips_last_arg_regnum
= 7;
3880 /* old ABI uses F12 through F15 for args */
3881 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3884 /* enable/disable the MIPS FPU */
3885 if (!mips_fpu_type_auto
)
3886 tdep
->mips_fpu_type
= mips_fpu_type
;
3887 else if (info
.bfd_arch_info
!= NULL
3888 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3889 switch (info
.bfd_arch_info
->mach
)
3891 case bfd_mach_mips4100
:
3892 case bfd_mach_mips4111
:
3893 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
3896 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3900 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3902 /* MIPS version of register names. NOTE: At present the MIPS
3903 register name management is part way between the old -
3904 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
3905 Further work on it is required. */
3906 set_gdbarch_register_name (gdbarch
, mips_register_name
);
3907 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3908 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3909 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3910 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3911 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3912 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3914 /* Initialize a frame */
3915 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
3917 /* MIPS version of CALL_DUMMY */
3919 set_gdbarch_call_dummy_p (gdbarch
, 1);
3920 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
3921 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3922 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3923 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
3924 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3925 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
3926 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3927 set_gdbarch_call_dummy_length (gdbarch
, 0);
3928 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3929 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
3930 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
3931 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
3932 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
3933 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
3934 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
3936 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3937 set_gdbarch_get_saved_register (gdbarch
, default_get_saved_register
);
3941 fprintf_unfiltered (gdb_stderr
,
3942 "mips_gdbarch_init: (info)elf_flags = 0x%x\n",
3944 fprintf_unfiltered (gdb_stderr
,
3945 "mips_gdbarch_init: (info)ef_mips_abi = %s\n",
3947 fprintf_unfiltered (gdb_stderr
,
3948 "mips_gdbarch_init: (info)ef_mips_arch = %d\n",
3950 fprintf_unfiltered (gdb_stderr
,
3951 "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n",
3953 fprintf_unfiltered (gdb_stderr
,
3954 "mips_gdbarch_init: MIPS_EABI = %d\n",
3956 fprintf_unfiltered (gdb_stderr
,
3957 "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n",
3958 tdep
->mips_last_arg_regnum
);
3959 fprintf_unfiltered (gdb_stderr
,
3960 "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n",
3961 tdep
->mips_last_fp_arg_regnum
,
3962 tdep
->mips_last_fp_arg_regnum
- FP0_REGNUM
);
3963 fprintf_unfiltered (gdb_stderr
,
3964 "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
3965 tdep
->mips_fpu_type
,
3966 (tdep
->mips_fpu_type
== MIPS_FPU_NONE
? "none"
3967 : tdep
->mips_fpu_type
== MIPS_FPU_SINGLE
? "single"
3968 : tdep
->mips_fpu_type
== MIPS_FPU_DOUBLE
? "double"
3970 fprintf_unfiltered (gdb_stderr
,
3971 "mips_gdbarch_init: tdep->mips_default_saved_regsize = %d\n",
3972 tdep
->mips_default_saved_regsize
);
3973 fprintf_unfiltered (gdb_stderr
,
3974 "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n",
3975 tdep
->mips_fp_register_double
,
3976 (tdep
->mips_fp_register_double
? "true" : "false"));
3984 _initialize_mips_tdep ()
3986 static struct cmd_list_element
*mipsfpulist
= NULL
;
3987 struct cmd_list_element
*c
;
3990 register_gdbarch_init (bfd_arch_mips
, mips_gdbarch_init
);
3991 if (!tm_print_insn
) /* Someone may have already set it */
3992 tm_print_insn
= gdb_print_insn_mips
;
3994 /* Add root prefix command for all "set mips"/"show mips" commands */
3995 add_prefix_cmd ("mips", no_class
, set_mips_command
,
3996 "Various MIPS specific commands.",
3997 &setmipscmdlist
, "set mips ", 0, &setlist
);
3999 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4000 "Various MIPS specific commands.",
4001 &showmipscmdlist
, "show mips ", 0, &showlist
);
4003 /* Allow the user to override the saved register size. */
4004 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4006 saved_gpreg_size_enums
,
4007 (char *) &mips_saved_regsize_string
, "\
4008 Set size of general purpose registers saved on the stack.\n\
4009 This option can be set to one of:\n\
4010 32 - Force GDB to treat saved GP registers as 32-bit\n\
4011 64 - Force GDB to treat saved GP registers as 64-bit\n\
4012 auto - Allow GDB to use the target's default setting or autodetect the\n\
4013 saved GP register size from information contained in the executable.\n\
4018 /* Let the user turn off floating point and set the fence post for
4019 heuristic_proc_start. */
4021 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4022 "Set use of MIPS floating-point coprocessor.",
4023 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4024 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4025 "Select single-precision MIPS floating-point coprocessor.",
4027 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4028 "Select double-precision MIPS floating-point coprocessor .",
4030 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4031 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4032 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4033 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4034 "Select no MIPS floating-point coprocessor.",
4036 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4037 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4038 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4039 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4040 "Select MIPS floating-point coprocessor automatically.",
4042 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4043 "Show current use of MIPS floating-point coprocessor target.",
4047 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4048 (char *) &tmp_mips_processor_type
,
4049 "Set the type of MIPS processor in use.\n\
4050 Set this to be able to access processor-type-specific registers.\n\
4053 c
->function
.cfunc
= mips_set_processor_type_command
;
4054 c
= add_show_from_set (c
, &showlist
);
4055 c
->function
.cfunc
= mips_show_processor_type_command
;
4057 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4058 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4061 /* We really would like to have both "0" and "unlimited" work, but
4062 command.c doesn't deal with that. So make it a var_zinteger
4063 because the user can always use "999999" or some such for unlimited. */
4064 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4065 (char *) &heuristic_fence_post
,
4067 Set the distance searched for the start of a function.\n\
4068 If you are debugging a stripped executable, GDB needs to search through the\n\
4069 program for the start of a function. This command sets the distance of the\n\
4070 search. The only need to set it is when debugging a stripped executable.",
4072 /* We need to throw away the frame cache when we set this, since it
4073 might change our ability to get backtraces. */
4074 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4075 add_show_from_set (c
, &showlist
);
4077 /* Allow the user to control whether the upper bits of 64-bit
4078 addresses should be zeroed. */
4080 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
4081 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4082 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
4083 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
4086 /* Allow the user to control the size of 32 bit registers within the
4087 raw remote packet. */
4088 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4091 (char *)&mips64_transfers_32bit_regs_p
, "\
4092 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4093 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4094 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4095 64 bits for others. Use \"off\" to disable compatibility mode",