1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
);
64 static int micromips_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
66 static int mips16_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
69 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
70 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
71 #define ST0_FR (1 << 26)
73 /* The sizes of floating point registers. */
77 MIPS_FPU_SINGLE_REGSIZE
= 4,
78 MIPS_FPU_DOUBLE_REGSIZE
= 8
87 static const char *mips_abi_string
;
89 static const char *const mips_abi_strings
[] = {
100 /* For backwards compatibility we default to MIPS16. This flag is
101 overridden as soon as unambiguous ELF file flags tell us the
102 compressed ISA encoding used. */
103 static const char mips_compression_mips16
[] = "mips16";
104 static const char mips_compression_micromips
[] = "micromips";
105 static const char *const mips_compression_strings
[] =
107 mips_compression_mips16
,
108 mips_compression_micromips
,
112 static const char *mips_compression_string
= mips_compression_mips16
;
114 /* The standard register names, and all the valid aliases for them. */
115 struct register_alias
121 /* Aliases for o32 and most other ABIs. */
122 const struct register_alias mips_o32_aliases
[] = {
129 /* Aliases for n32 and n64. */
130 const struct register_alias mips_n32_n64_aliases
[] = {
137 /* Aliases for ABI-independent registers. */
138 const struct register_alias mips_register_aliases
[] = {
139 /* The architecture manuals specify these ABI-independent names for
141 #define R(n) { "r" #n, n }
142 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
143 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
144 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
145 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
148 /* k0 and k1 are sometimes called these instead (for "kernel
153 /* This is the traditional GDB name for the CP0 status register. */
154 { "sr", MIPS_PS_REGNUM
},
156 /* This is the traditional GDB name for the CP0 BadVAddr register. */
157 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
159 /* This is the traditional GDB name for the FCSR. */
160 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
163 const struct register_alias mips_numeric_register_aliases
[] = {
164 #define R(n) { #n, n }
165 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
166 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
167 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
168 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
172 #ifndef MIPS_DEFAULT_FPU_TYPE
173 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
175 static int mips_fpu_type_auto
= 1;
176 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
178 static unsigned int mips_debug
= 0;
180 /* Properties (for struct target_desc) describing the g/G packet
182 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
183 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
185 struct target_desc
*mips_tdesc_gp32
;
186 struct target_desc
*mips_tdesc_gp64
;
188 const struct mips_regnum
*
189 mips_regnum (struct gdbarch
*gdbarch
)
191 return gdbarch_tdep (gdbarch
)->regnum
;
195 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
197 return mips_regnum (gdbarch
)->fp0
+ 12;
200 /* Return 1 if REGNUM refers to a floating-point general register, raw
201 or cooked. Otherwise return 0. */
204 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
206 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
208 return (rawnum
>= mips_regnum (gdbarch
)->fp0
209 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
212 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
214 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
216 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
217 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
220 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
222 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
224 /* Return the MIPS ABI associated with GDBARCH. */
226 mips_abi (struct gdbarch
*gdbarch
)
228 return gdbarch_tdep (gdbarch
)->mips_abi
;
232 mips_isa_regsize (struct gdbarch
*gdbarch
)
234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
236 /* If we know how big the registers are, use that size. */
237 if (tdep
->register_size_valid_p
)
238 return tdep
->register_size
;
240 /* Fall back to the previous behavior. */
241 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
242 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
245 /* Return the currently configured (or set) saved register size. */
248 mips_abi_regsize (struct gdbarch
*gdbarch
)
250 switch (mips_abi (gdbarch
))
252 case MIPS_ABI_EABI32
:
258 case MIPS_ABI_EABI64
:
260 case MIPS_ABI_UNKNOWN
:
263 internal_error (__FILE__
, __LINE__
, _("bad switch"));
267 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
268 are some functions to handle addresses associated with compressed
269 code including but not limited to testing, setting, or clearing
270 bit 0 of such addresses. */
272 /* Return one iff compressed code is the MIPS16 instruction set. */
275 is_mips16_isa (struct gdbarch
*gdbarch
)
277 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
280 /* Return one iff compressed code is the microMIPS instruction set. */
283 is_micromips_isa (struct gdbarch
*gdbarch
)
285 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
288 /* Return one iff ADDR denotes compressed code. */
291 is_compact_addr (CORE_ADDR addr
)
296 /* Return one iff ADDR denotes standard ISA code. */
299 is_mips_addr (CORE_ADDR addr
)
301 return !is_compact_addr (addr
);
304 /* Return one iff ADDR denotes MIPS16 code. */
307 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
309 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
312 /* Return one iff ADDR denotes microMIPS code. */
315 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
317 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
320 /* Strip the ISA (compression) bit off from ADDR. */
323 unmake_compact_addr (CORE_ADDR addr
)
325 return ((addr
) & ~(CORE_ADDR
) 1);
328 /* Add the ISA (compression) bit to ADDR. */
331 make_compact_addr (CORE_ADDR addr
)
333 return ((addr
) | (CORE_ADDR
) 1);
336 /* Functions for setting and testing a bit in a minimal symbol that
337 marks it as MIPS16 or microMIPS function. The MSB of the minimal
338 symbol's "info" field is used for this purpose.
340 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
341 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
342 one of the "special" bits in a minimal symbol to mark it accordingly.
343 The test checks an ELF-private flag that is valid for true function
344 symbols only; for synthetic symbols such as for PLT stubs that have
345 no ELF-private part at all the MIPS BFD backend arranges for this
346 information to be carried in the asymbol's udata field instead.
348 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
349 in a minimal symbol. */
352 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
354 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
355 unsigned char st_other
;
357 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
358 st_other
= elfsym
->internal_elf_sym
.st_other
;
359 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
360 st_other
= sym
->udata
.i
;
364 if (ELF_ST_IS_MICROMIPS (st_other
))
365 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
366 else if (ELF_ST_IS_MIPS16 (st_other
))
367 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
370 /* Return one iff MSYM refers to standard ISA code. */
373 msymbol_is_mips (struct minimal_symbol
*msym
)
375 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
378 /* Return one iff MSYM refers to MIPS16 code. */
381 msymbol_is_mips16 (struct minimal_symbol
*msym
)
383 return MSYMBOL_TARGET_FLAG_1 (msym
);
386 /* Return one iff MSYM refers to microMIPS code. */
389 msymbol_is_micromips (struct minimal_symbol
*msym
)
391 return MSYMBOL_TARGET_FLAG_2 (msym
);
394 /* XFER a value from the big/little/left end of the register.
395 Depending on the size of the value it might occupy the entire
396 register or just part of it. Make an allowance for this, aligning
397 things accordingly. */
400 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
401 int reg_num
, int length
,
402 enum bfd_endian endian
, gdb_byte
*in
,
403 const gdb_byte
*out
, int buf_offset
)
407 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
408 /* Need to transfer the left or right part of the register, based on
409 the targets byte order. */
413 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
415 case BFD_ENDIAN_LITTLE
:
418 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
422 internal_error (__FILE__
, __LINE__
, _("bad switch"));
425 fprintf_unfiltered (gdb_stderr
,
426 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
427 reg_num
, reg_offset
, buf_offset
, length
);
428 if (mips_debug
&& out
!= NULL
)
431 fprintf_unfiltered (gdb_stdlog
, "out ");
432 for (i
= 0; i
< length
; i
++)
433 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
436 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
439 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
441 if (mips_debug
&& in
!= NULL
)
444 fprintf_unfiltered (gdb_stdlog
, "in ");
445 for (i
= 0; i
< length
; i
++)
446 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
449 fprintf_unfiltered (gdb_stdlog
, "\n");
452 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
453 compatiblity mode. A return value of 1 means that we have
454 physical 64-bit registers, but should treat them as 32-bit registers. */
457 mips2_fp_compat (struct frame_info
*frame
)
459 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
460 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
462 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
466 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
467 in all the places we deal with FP registers. PR gdb/413. */
468 /* Otherwise check the FR bit in the status register - it controls
469 the FP compatiblity mode. If it is clear we are in compatibility
471 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
478 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
480 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
482 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
484 /* The list of available "set mips " and "show mips " commands. */
486 static struct cmd_list_element
*setmipscmdlist
= NULL
;
487 static struct cmd_list_element
*showmipscmdlist
= NULL
;
489 /* Integer registers 0 thru 31 are handled explicitly by
490 mips_register_name(). Processor specific registers 32 and above
491 are listed in the following tables. */
494 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
498 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
499 "sr", "lo", "hi", "bad", "cause", "pc",
500 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
501 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
502 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
503 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
507 /* Names of IDT R3041 registers. */
509 static const char *mips_r3041_reg_names
[] = {
510 "sr", "lo", "hi", "bad", "cause", "pc",
511 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
512 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
513 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
514 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
515 "fsr", "fir", "", /*"fp" */ "",
516 "", "", "bus", "ccfg", "", "", "", "",
517 "", "", "port", "cmp", "", "", "epc", "prid",
520 /* Names of tx39 registers. */
522 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
523 "sr", "lo", "hi", "bad", "cause", "pc",
524 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "", "", "", "", "", "",
527 "", "", "", "", "", "", "", "",
529 "", "", "", "", "", "", "", "",
530 "", "", "config", "cache", "debug", "depc", "epc",
533 /* Names of IRIX registers. */
534 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
535 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
536 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
537 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
538 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
539 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
542 /* Names of registers with Linux kernels. */
543 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
544 "sr", "lo", "hi", "bad", "cause", "pc",
545 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
546 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
547 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
548 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
553 /* Return the name of the register corresponding to REGNO. */
555 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
557 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
558 /* GPR names for all ABIs other than n32/n64. */
559 static char *mips_gpr_names
[] = {
560 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
561 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
562 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
563 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
566 /* GPR names for n32 and n64 ABIs. */
567 static char *mips_n32_n64_gpr_names
[] = {
568 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
569 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
570 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
571 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
574 enum mips_abi abi
= mips_abi (gdbarch
);
576 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
577 but then don't make the raw register names visible. This (upper)
578 range of user visible register numbers are the pseudo-registers.
580 This approach was adopted accommodate the following scenario:
581 It is possible to debug a 64-bit device using a 32-bit
582 programming model. In such instances, the raw registers are
583 configured to be 64-bits wide, while the pseudo registers are
584 configured to be 32-bits wide. The registers that the user
585 sees - the pseudo registers - match the users expectations
586 given the programming model being used. */
587 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
588 if (regno
< gdbarch_num_regs (gdbarch
))
591 /* The MIPS integer registers are always mapped from 0 to 31. The
592 names of the registers (which reflects the conventions regarding
593 register use) vary depending on the ABI. */
594 if (0 <= rawnum
&& rawnum
< 32)
596 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
597 return mips_n32_n64_gpr_names
[rawnum
];
599 return mips_gpr_names
[rawnum
];
601 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
602 return tdesc_register_name (gdbarch
, rawnum
);
603 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
605 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
606 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
607 return tdep
->mips_processor_reg_names
[rawnum
- 32];
611 internal_error (__FILE__
, __LINE__
,
612 _("mips_register_name: bad register number %d"), rawnum
);
615 /* Return the groups that a MIPS register can be categorised into. */
618 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
619 struct reggroup
*reggroup
)
624 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
625 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
626 if (reggroup
== all_reggroup
)
628 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
629 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
630 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
631 (gdbarch), as not all architectures are multi-arch. */
632 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
633 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
634 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
636 if (reggroup
== float_reggroup
)
637 return float_p
&& pseudo
;
638 if (reggroup
== vector_reggroup
)
639 return vector_p
&& pseudo
;
640 if (reggroup
== general_reggroup
)
641 return (!vector_p
&& !float_p
) && pseudo
;
642 /* Save the pseudo registers. Need to make certain that any code
643 extracting register values from a saved register cache also uses
645 if (reggroup
== save_reggroup
)
646 return raw_p
&& pseudo
;
647 /* Restore the same pseudo register. */
648 if (reggroup
== restore_reggroup
)
649 return raw_p
&& pseudo
;
653 /* Return the groups that a MIPS register can be categorised into.
654 This version is only used if we have a target description which
655 describes real registers (and their groups). */
658 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
659 struct reggroup
*reggroup
)
661 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
662 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
665 /* Only save, restore, and display the pseudo registers. Need to
666 make certain that any code extracting register values from a
667 saved register cache also uses pseudo registers.
669 Note: saving and restoring the pseudo registers is slightly
670 strange; if we have 64 bits, we should save and restore all
671 64 bits. But this is hard and has little benefit. */
675 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
679 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
682 /* Map the symbol table registers which live in the range [1 *
683 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
684 registers. Take care of alignment and size problems. */
686 static enum register_status
687 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
688 int cookednum
, gdb_byte
*buf
)
690 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
691 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
692 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
693 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
694 return regcache_raw_read (regcache
, rawnum
, buf
);
695 else if (register_size (gdbarch
, rawnum
) >
696 register_size (gdbarch
, cookednum
))
698 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
699 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
702 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
704 enum register_status status
;
706 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
707 if (status
== REG_VALID
)
708 store_signed_integer (buf
, 4, byte_order
, regval
);
713 internal_error (__FILE__
, __LINE__
, _("bad register size"));
717 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
718 struct regcache
*regcache
, int cookednum
,
721 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
722 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
723 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
724 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
725 regcache_raw_write (regcache
, rawnum
, buf
);
726 else if (register_size (gdbarch
, rawnum
) >
727 register_size (gdbarch
, cookednum
))
729 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
730 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
733 /* Sign extend the shortened version of the register prior
734 to placing it in the raw register. This is required for
735 some mips64 parts in order to avoid unpredictable behavior. */
736 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
737 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
738 regcache_raw_write_signed (regcache
, rawnum
, regval
);
742 internal_error (__FILE__
, __LINE__
, _("bad register size"));
746 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
747 struct agent_expr
*ax
, int reg
)
749 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
750 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
751 && reg
< 2 * gdbarch_num_regs (gdbarch
));
753 ax_reg_mask (ax
, rawnum
);
759 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
760 struct agent_expr
*ax
, int reg
)
762 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
763 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
764 && reg
< 2 * gdbarch_num_regs (gdbarch
));
765 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
769 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
771 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
772 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
775 ax_simple (ax
, aop_lsh
);
778 ax_simple (ax
, aop_rsh_signed
);
782 internal_error (__FILE__
, __LINE__
, _("bad register size"));
787 /* Table to translate 3-bit register field to actual register number. */
788 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
790 /* Heuristic_proc_start may hunt through the text section for a long
791 time across a 2400 baud serial line. Allows the user to limit this
794 static int heuristic_fence_post
= 0;
796 /* Number of bytes of storage in the actual machine representation for
797 register N. NOTE: This defines the pseudo register type so need to
798 rebuild the architecture vector. */
800 static int mips64_transfers_32bit_regs_p
= 0;
803 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
804 struct cmd_list_element
*c
)
806 struct gdbarch_info info
;
807 gdbarch_info_init (&info
);
808 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
809 instead of relying on globals. Doing that would let generic code
810 handle the search for this specific architecture. */
811 if (!gdbarch_update_p (info
))
813 mips64_transfers_32bit_regs_p
= 0;
814 error (_("32-bit compatibility mode not supported"));
818 /* Convert to/from a register and the corresponding memory value. */
820 /* This predicate tests for the case of an 8 byte floating point
821 value that is being transferred to or from a pair of floating point
822 registers each of which are (or are considered to be) only 4 bytes
825 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
828 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
829 && register_size (gdbarch
, regnum
) == 4
830 && mips_float_register_p (gdbarch
, regnum
)
831 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
834 /* This predicate tests for the case of a value of less than 8
835 bytes in width that is being transfered to or from an 8 byte
836 general purpose register. */
838 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
841 int num_regs
= gdbarch_num_regs (gdbarch
);
843 return (register_size (gdbarch
, regnum
) == 8
844 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
845 && TYPE_LENGTH (type
) < 8);
849 mips_convert_register_p (struct gdbarch
*gdbarch
,
850 int regnum
, struct type
*type
)
852 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
853 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
857 mips_register_to_value (struct frame_info
*frame
, int regnum
,
858 struct type
*type
, gdb_byte
*to
,
859 int *optimizedp
, int *unavailablep
)
861 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
863 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
865 get_frame_register (frame
, regnum
+ 0, to
+ 4);
866 get_frame_register (frame
, regnum
+ 1, to
+ 0);
868 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
869 optimizedp
, unavailablep
))
872 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
873 optimizedp
, unavailablep
))
875 *optimizedp
= *unavailablep
= 0;
878 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
880 int len
= TYPE_LENGTH (type
);
883 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
884 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
885 optimizedp
, unavailablep
))
888 *optimizedp
= *unavailablep
= 0;
893 internal_error (__FILE__
, __LINE__
,
894 _("mips_register_to_value: unrecognized case"));
899 mips_value_to_register (struct frame_info
*frame
, int regnum
,
900 struct type
*type
, const gdb_byte
*from
)
902 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
904 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
906 put_frame_register (frame
, regnum
+ 0, from
+ 4);
907 put_frame_register (frame
, regnum
+ 1, from
+ 0);
909 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
912 int len
= TYPE_LENGTH (type
);
914 /* Sign extend values, irrespective of type, that are stored to
915 a 64-bit general purpose register. (32-bit unsigned values
916 are stored as signed quantities within a 64-bit register.
917 When performing an operation, in compiled code, that combines
918 a 32-bit unsigned value with a signed 64-bit value, a type
919 conversion is first performed that zeroes out the high 32 bits.) */
920 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
923 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
925 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
926 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
927 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
931 if (from
[len
-1] & 0x80)
932 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
934 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
935 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
936 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
941 internal_error (__FILE__
, __LINE__
,
942 _("mips_value_to_register: unrecognized case"));
946 /* Return the GDB type object for the "standard" data type of data in
950 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
952 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
953 if (mips_float_register_p (gdbarch
, regnum
))
955 /* The floating-point registers raw, or cooked, always match
956 mips_isa_regsize(), and also map 1:1, byte for byte. */
957 if (mips_isa_regsize (gdbarch
) == 4)
958 return builtin_type (gdbarch
)->builtin_float
;
960 return builtin_type (gdbarch
)->builtin_double
;
962 else if (regnum
< gdbarch_num_regs (gdbarch
))
964 /* The raw or ISA registers. These are all sized according to
966 if (mips_isa_regsize (gdbarch
) == 4)
967 return builtin_type (gdbarch
)->builtin_int32
;
969 return builtin_type (gdbarch
)->builtin_int64
;
973 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
975 /* The cooked or ABI registers. These are sized according to
976 the ABI (with a few complications). */
977 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
978 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
979 return builtin_type (gdbarch
)->builtin_int32
;
980 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
981 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
982 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
983 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
984 /* The pseudo/cooked view of the embedded registers is always
985 32-bit. The raw view is handled below. */
986 return builtin_type (gdbarch
)->builtin_int32
;
987 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
988 /* The target, while possibly using a 64-bit register buffer,
989 is only transfering 32-bits of each integer register.
990 Reflect this in the cooked/pseudo (ABI) register value. */
991 return builtin_type (gdbarch
)->builtin_int32
;
992 else if (mips_abi_regsize (gdbarch
) == 4)
993 /* The ABI is restricted to 32-bit registers (the ISA could be
995 return builtin_type (gdbarch
)->builtin_int32
;
998 return builtin_type (gdbarch
)->builtin_int64
;
1002 /* Return the GDB type for the pseudo register REGNUM, which is the
1003 ABI-level view. This function is only called if there is a target
1004 description which includes registers, so we know precisely the
1005 types of hardware registers. */
1007 static struct type
*
1008 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1010 const int num_regs
= gdbarch_num_regs (gdbarch
);
1011 int rawnum
= regnum
% num_regs
;
1012 struct type
*rawtype
;
1014 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1016 /* Absent registers are still absent. */
1017 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1018 if (TYPE_LENGTH (rawtype
) == 0)
1021 if (mips_float_register_p (gdbarch
, rawnum
))
1022 /* Present the floating point registers however the hardware did;
1023 do not try to convert between FPU layouts. */
1026 /* Use pointer types for registers if we can. For n32 we can not,
1027 since we do not have a 64-bit pointer type. */
1028 if (mips_abi_regsize (gdbarch
)
1029 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1031 if (rawnum
== MIPS_SP_REGNUM
1032 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1033 return builtin_type (gdbarch
)->builtin_data_ptr
;
1034 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1035 return builtin_type (gdbarch
)->builtin_func_ptr
;
1038 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1039 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1040 || rawnum
== mips_regnum (gdbarch
)->lo
1041 || rawnum
== mips_regnum (gdbarch
)->hi
1042 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1043 || rawnum
== mips_regnum (gdbarch
)->cause
1044 || rawnum
== mips_regnum (gdbarch
)->pc
1045 || (mips_regnum (gdbarch
)->dspacc
!= -1
1046 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1047 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1048 return builtin_type (gdbarch
)->builtin_int32
;
1050 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1051 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1052 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1053 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1055 /* The pseudo/cooked view of embedded registers is always
1056 32-bit, even if the target transfers 64-bit values for them.
1057 New targets relying on XML descriptions should only transfer
1058 the necessary 32 bits, but older versions of GDB expected 64,
1059 so allow the target to provide 64 bits without interfering
1060 with the displayed type. */
1061 return builtin_type (gdbarch
)->builtin_int32
;
1064 /* For all other registers, pass through the hardware type. */
1068 /* Should the upper word of 64-bit addresses be zeroed? */
1069 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1072 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1074 switch (mask_address_var
)
1076 case AUTO_BOOLEAN_TRUE
:
1078 case AUTO_BOOLEAN_FALSE
:
1081 case AUTO_BOOLEAN_AUTO
:
1082 return tdep
->default_mask_address_p
;
1084 internal_error (__FILE__
, __LINE__
,
1085 _("mips_mask_address_p: bad switch"));
1091 show_mask_address (struct ui_file
*file
, int from_tty
,
1092 struct cmd_list_element
*c
, const char *value
)
1094 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1096 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1097 switch (mask_address_var
)
1099 case AUTO_BOOLEAN_TRUE
:
1100 printf_filtered ("The 32 bit mips address mask is enabled\n");
1102 case AUTO_BOOLEAN_FALSE
:
1103 printf_filtered ("The 32 bit mips address mask is disabled\n");
1105 case AUTO_BOOLEAN_AUTO
:
1107 ("The 32 bit address mask is set automatically. Currently %s\n",
1108 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1111 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1116 /* Tell if the program counter value in MEMADDR is in a standard ISA
1120 mips_pc_is_mips (CORE_ADDR memaddr
)
1122 struct bound_minimal_symbol sym
;
1124 /* Flags indicating that this is a MIPS16 or microMIPS function is
1125 stored by elfread.c in the high bit of the info field. Use this
1126 to decide if the function is standard MIPS. Otherwise if bit 0
1127 of the address is clear, then this is a standard MIPS function. */
1128 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1130 return msymbol_is_mips (sym
.minsym
);
1132 return is_mips_addr (memaddr
);
1135 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1138 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1140 struct bound_minimal_symbol sym
;
1142 /* A flag indicating that this is a MIPS16 function is stored by
1143 elfread.c in the high bit of the info field. Use this to decide
1144 if the function is MIPS16. Otherwise if bit 0 of the address is
1145 set, then ELF file flags will tell if this is a MIPS16 function. */
1146 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1148 return msymbol_is_mips16 (sym
.minsym
);
1150 return is_mips16_addr (gdbarch
, memaddr
);
1153 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1156 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1158 struct bound_minimal_symbol sym
;
1160 /* A flag indicating that this is a microMIPS function is stored by
1161 elfread.c in the high bit of the info field. Use this to decide
1162 if the function is microMIPS. Otherwise if bit 0 of the address
1163 is set, then ELF file flags will tell if this is a microMIPS
1165 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1167 return msymbol_is_micromips (sym
.minsym
);
1169 return is_micromips_addr (gdbarch
, memaddr
);
1172 /* Tell the ISA type of the function the program counter value in MEMADDR
1175 static enum mips_isa
1176 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1178 struct bound_minimal_symbol sym
;
1180 /* A flag indicating that this is a MIPS16 or a microMIPS function
1181 is stored by elfread.c in the high bit of the info field. Use
1182 this to decide if the function is MIPS16 or microMIPS or normal
1183 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1184 flags will tell if this is a MIPS16 or a microMIPS function. */
1185 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1188 if (msymbol_is_micromips (sym
.minsym
))
1189 return ISA_MICROMIPS
;
1190 else if (msymbol_is_mips16 (sym
.minsym
))
1197 if (is_mips_addr (memaddr
))
1199 else if (is_micromips_addr (gdbarch
, memaddr
))
1200 return ISA_MICROMIPS
;
1206 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1208 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1209 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1210 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1211 static const char mips_str_call_stub
[] = "__call_stub_";
1212 static const char mips_str_fn_stub
[] = "__fn_stub_";
1214 /* This is used as a PIC thunk prefix. */
1216 static const char mips_str_pic
[] = ".pic.";
1218 /* Return non-zero if the PC is inside a call thunk (aka stub or
1219 trampoline) that should be treated as a temporary frame. */
1222 mips_in_frame_stub (CORE_ADDR pc
)
1224 CORE_ADDR start_addr
;
1227 /* Find the starting address of the function containing the PC. */
1228 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1231 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1232 if (strncmp (name
, mips_str_mips16_call_stub
,
1233 strlen (mips_str_mips16_call_stub
)) == 0)
1235 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1236 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1238 /* If the PC is in __fn_stub_*, this is a call stub. */
1239 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1242 return 0; /* Not a stub. */
1245 /* MIPS believes that the PC has a sign extended value. Perhaps the
1246 all registers should be sign extended for simplicity? */
1249 mips_read_pc (struct regcache
*regcache
)
1251 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1254 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1255 if (is_compact_addr (pc
))
1256 pc
= unmake_compact_addr (pc
);
1261 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1265 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1266 if (is_compact_addr (pc
))
1267 pc
= unmake_compact_addr (pc
);
1268 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1269 intermediate frames. In this case we can get the caller's address
1270 from $ra, or if $ra contains an address within a thunk as well, then
1271 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1272 and thus the caller's address is in $s2. */
1273 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1275 pc
= frame_unwind_register_signed
1276 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1277 if (is_compact_addr (pc
))
1278 pc
= unmake_compact_addr (pc
);
1279 if (mips_in_frame_stub (pc
))
1281 pc
= frame_unwind_register_signed
1282 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1283 if (is_compact_addr (pc
))
1284 pc
= unmake_compact_addr (pc
);
1291 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1293 return frame_unwind_register_signed
1294 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1297 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1298 dummy frame. The frame ID's base needs to match the TOS value
1299 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1302 static struct frame_id
1303 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1305 return frame_id_build
1306 (get_frame_register_signed (this_frame
,
1307 gdbarch_num_regs (gdbarch
)
1309 get_frame_pc (this_frame
));
1312 /* Implement the "write_pc" gdbarch method. */
1315 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1317 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1319 if (mips_pc_is_mips (pc
))
1320 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1322 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1325 /* Fetch and return instruction from the specified location. Handle
1326 MIPS16/microMIPS as appropriate. */
1329 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1330 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1332 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1333 gdb_byte buf
[MIPS_INSN32_SIZE
];
1341 instlen
= MIPS_INSN16_SIZE
;
1342 addr
= unmake_compact_addr (addr
);
1345 instlen
= MIPS_INSN32_SIZE
;
1348 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1351 status
= target_read_memory (addr
, buf
, instlen
);
1352 if (statusp
!= NULL
)
1356 if (statusp
== NULL
)
1357 memory_error (status
, addr
);
1360 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1363 /* These are the fields of 32 bit mips instructions. */
1364 #define mips32_op(x) (x >> 26)
1365 #define itype_op(x) (x >> 26)
1366 #define itype_rs(x) ((x >> 21) & 0x1f)
1367 #define itype_rt(x) ((x >> 16) & 0x1f)
1368 #define itype_immediate(x) (x & 0xffff)
1370 #define jtype_op(x) (x >> 26)
1371 #define jtype_target(x) (x & 0x03ffffff)
1373 #define rtype_op(x) (x >> 26)
1374 #define rtype_rs(x) ((x >> 21) & 0x1f)
1375 #define rtype_rt(x) ((x >> 16) & 0x1f)
1376 #define rtype_rd(x) ((x >> 11) & 0x1f)
1377 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1378 #define rtype_funct(x) (x & 0x3f)
1380 /* MicroMIPS instruction fields. */
1381 #define micromips_op(x) ((x) >> 10)
1383 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1384 bit and the size respectively of the field extracted. */
1385 #define b0s4_imm(x) ((x) & 0xf)
1386 #define b0s5_imm(x) ((x) & 0x1f)
1387 #define b0s5_reg(x) ((x) & 0x1f)
1388 #define b0s7_imm(x) ((x) & 0x7f)
1389 #define b0s10_imm(x) ((x) & 0x3ff)
1390 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1391 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1392 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1393 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1394 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1395 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1396 #define b6s4_op(x) (((x) >> 6) & 0xf)
1397 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1399 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1400 respectively of the field extracted. */
1401 #define b0s6_op(x) ((x) & 0x3f)
1402 #define b0s11_op(x) ((x) & 0x7ff)
1403 #define b0s12_imm(x) ((x) & 0xfff)
1404 #define b0s16_imm(x) ((x) & 0xffff)
1405 #define b0s26_imm(x) ((x) & 0x3ffffff)
1406 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1407 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1408 #define b12s4_op(x) (((x) >> 12) & 0xf)
1410 /* Return the size in bytes of the instruction INSN encoded in the ISA
1414 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1419 if (micromips_op (insn
) == 0x1f)
1420 return 3 * MIPS_INSN16_SIZE
;
1421 else if (((micromips_op (insn
) & 0x4) == 0x4)
1422 || ((micromips_op (insn
) & 0x7) == 0x0))
1423 return 2 * MIPS_INSN16_SIZE
;
1425 return MIPS_INSN16_SIZE
;
1427 if ((insn
& 0xf800) == 0xf000)
1428 return 2 * MIPS_INSN16_SIZE
;
1430 return MIPS_INSN16_SIZE
;
1432 return MIPS_INSN32_SIZE
;
1434 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1438 mips32_relative_offset (ULONGEST inst
)
1440 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1443 /* Determine the address of the next instruction executed after the INST
1444 floating condition branch instruction at PC. COUNT specifies the
1445 number of the floating condition bits tested by the branch. */
1448 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1449 ULONGEST inst
, CORE_ADDR pc
, int count
)
1451 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1452 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1453 int tf
= itype_rt (inst
) & 1;
1454 int mask
= (1 << count
) - 1;
1459 /* No way to handle; it'll most likely trap anyway. */
1462 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1463 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1465 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1466 pc
+= mips32_relative_offset (inst
);
1473 /* Return nonzero if the gdbarch is an Octeon series. */
1476 is_octeon (struct gdbarch
*gdbarch
)
1478 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1480 return (info
->mach
== bfd_mach_mips_octeon
1481 || info
->mach
== bfd_mach_mips_octeonp
1482 || info
->mach
== bfd_mach_mips_octeon2
);
1485 /* Return true if the OP represents the Octeon's BBIT instruction. */
1488 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1490 if (!is_octeon (gdbarch
))
1492 /* BBIT0 is encoded as LWC2: 110 010. */
1493 /* BBIT032 is encoded as LDC2: 110 110. */
1494 /* BBIT1 is encoded as SWC2: 111 010. */
1495 /* BBIT132 is encoded as SDC2: 111 110. */
1496 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1502 /* Determine where to set a single step breakpoint while considering
1503 branch prediction. */
1506 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1508 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1511 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1512 op
= itype_op (inst
);
1513 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1517 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1528 goto greater_branch
;
1533 else if (op
== 17 && itype_rs (inst
) == 8)
1534 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1535 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1536 else if (op
== 17 && itype_rs (inst
) == 9
1537 && (itype_rt (inst
) & 2) == 0)
1538 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1539 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1540 else if (op
== 17 && itype_rs (inst
) == 10
1541 && (itype_rt (inst
) & 2) == 0)
1542 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1543 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1546 /* The new PC will be alternate mode. */
1550 reg
= jtype_target (inst
) << 2;
1551 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1552 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1554 else if (is_octeon_bbit_op (op
, gdbarch
))
1558 branch_if
= op
== 58 || op
== 62;
1559 bit
= itype_rt (inst
);
1561 /* Take into account the *32 instructions. */
1562 if (op
== 54 || op
== 62)
1565 if (((get_frame_register_signed (frame
,
1566 itype_rs (inst
)) >> bit
) & 1)
1568 pc
+= mips32_relative_offset (inst
) + 4;
1570 pc
+= 8; /* After the delay slot. */
1574 pc
+= 4; /* Not a branch, next instruction is easy. */
1577 { /* This gets way messy. */
1579 /* Further subdivide into SPECIAL, REGIMM and other. */
1580 switch (op
& 0x07) /* Extract bits 28,27,26. */
1582 case 0: /* SPECIAL */
1583 op
= rtype_funct (inst
);
1588 /* Set PC to that address. */
1589 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1591 case 12: /* SYSCALL */
1593 struct gdbarch_tdep
*tdep
;
1595 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1596 if (tdep
->syscall_next_pc
!= NULL
)
1597 pc
= tdep
->syscall_next_pc (frame
);
1606 break; /* end SPECIAL */
1607 case 1: /* REGIMM */
1609 op
= itype_rt (inst
); /* branch condition */
1614 case 16: /* BLTZAL */
1615 case 18: /* BLTZALL */
1617 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1618 pc
+= mips32_relative_offset (inst
) + 4;
1620 pc
+= 8; /* after the delay slot */
1624 case 17: /* BGEZAL */
1625 case 19: /* BGEZALL */
1626 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1627 pc
+= mips32_relative_offset (inst
) + 4;
1629 pc
+= 8; /* after the delay slot */
1631 case 0x1c: /* BPOSGE32 */
1632 case 0x1e: /* BPOSGE64 */
1634 if (itype_rs (inst
) == 0)
1636 unsigned int pos
= (op
& 2) ? 64 : 32;
1637 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1640 /* No way to handle; it'll most likely trap anyway. */
1643 if ((get_frame_register_unsigned (frame
,
1644 dspctl
) & 0x7f) >= pos
)
1645 pc
+= mips32_relative_offset (inst
);
1650 /* All of the other instructions in the REGIMM category */
1655 break; /* end REGIMM */
1660 reg
= jtype_target (inst
) << 2;
1661 /* Upper four bits get never changed... */
1662 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1665 case 4: /* BEQ, BEQL */
1667 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1668 get_frame_register_signed (frame
, itype_rt (inst
)))
1669 pc
+= mips32_relative_offset (inst
) + 4;
1673 case 5: /* BNE, BNEL */
1675 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1676 get_frame_register_signed (frame
, itype_rt (inst
)))
1677 pc
+= mips32_relative_offset (inst
) + 4;
1681 case 6: /* BLEZ, BLEZL */
1682 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1683 pc
+= mips32_relative_offset (inst
) + 4;
1689 greater_branch
: /* BGTZ, BGTZL */
1690 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1691 pc
+= mips32_relative_offset (inst
) + 4;
1698 } /* mips32_next_pc */
1700 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1704 micromips_relative_offset7 (ULONGEST insn
)
1706 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1709 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1713 micromips_relative_offset10 (ULONGEST insn
)
1715 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1718 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1722 micromips_relative_offset16 (ULONGEST insn
)
1724 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1727 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1730 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1734 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1735 return mips_insn_size (ISA_MICROMIPS
, insn
);
1738 /* Calculate the address of the next microMIPS instruction to execute
1739 after the INSN coprocessor 1 conditional branch instruction at the
1740 address PC. COUNT denotes the number of coprocessor condition bits
1741 examined by the branch. */
1744 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1745 ULONGEST insn
, CORE_ADDR pc
, int count
)
1747 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1748 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1749 int tf
= b5s5_op (insn
>> 16) & 1;
1750 int mask
= (1 << count
) - 1;
1755 /* No way to handle; it'll most likely trap anyway. */
1758 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1759 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1761 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1762 pc
+= micromips_relative_offset16 (insn
);
1764 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1769 /* Calculate the address of the next microMIPS instruction to execute
1770 after the instruction at the address PC. */
1773 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1775 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1778 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1779 pc
+= MIPS_INSN16_SIZE
;
1780 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1782 /* 48-bit instructions. */
1783 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1784 /* No branch or jump instructions in this category. */
1785 pc
+= 2 * MIPS_INSN16_SIZE
;
1788 /* 32-bit instructions. */
1789 case 2 * MIPS_INSN16_SIZE
:
1791 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1792 pc
+= MIPS_INSN16_SIZE
;
1793 switch (micromips_op (insn
>> 16))
1795 case 0x00: /* POOL32A: bits 000000 */
1796 if (b0s6_op (insn
) == 0x3c
1797 /* POOL32Axf: bits 000000 ... 111100 */
1798 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1799 /* JALR, JALR.HB: 000000 000x111100 111100 */
1800 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1801 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1804 case 0x10: /* POOL32I: bits 010000 */
1805 switch (b5s5_op (insn
>> 16))
1807 case 0x00: /* BLTZ: bits 010000 00000 */
1808 case 0x01: /* BLTZAL: bits 010000 00001 */
1809 case 0x11: /* BLTZALS: bits 010000 10001 */
1810 if (get_frame_register_signed (frame
,
1811 b0s5_reg (insn
>> 16)) < 0)
1812 pc
+= micromips_relative_offset16 (insn
);
1814 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1817 case 0x02: /* BGEZ: bits 010000 00010 */
1818 case 0x03: /* BGEZAL: bits 010000 00011 */
1819 case 0x13: /* BGEZALS: bits 010000 10011 */
1820 if (get_frame_register_signed (frame
,
1821 b0s5_reg (insn
>> 16)) >= 0)
1822 pc
+= micromips_relative_offset16 (insn
);
1824 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1827 case 0x04: /* BLEZ: bits 010000 00100 */
1828 if (get_frame_register_signed (frame
,
1829 b0s5_reg (insn
>> 16)) <= 0)
1830 pc
+= micromips_relative_offset16 (insn
);
1832 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1835 case 0x05: /* BNEZC: bits 010000 00101 */
1836 if (get_frame_register_signed (frame
,
1837 b0s5_reg (insn
>> 16)) != 0)
1838 pc
+= micromips_relative_offset16 (insn
);
1841 case 0x06: /* BGTZ: bits 010000 00110 */
1842 if (get_frame_register_signed (frame
,
1843 b0s5_reg (insn
>> 16)) > 0)
1844 pc
+= micromips_relative_offset16 (insn
);
1846 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1849 case 0x07: /* BEQZC: bits 010000 00111 */
1850 if (get_frame_register_signed (frame
,
1851 b0s5_reg (insn
>> 16)) == 0)
1852 pc
+= micromips_relative_offset16 (insn
);
1855 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1856 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1857 if (((insn
>> 16) & 0x3) == 0x0)
1858 /* BC2F, BC2T: don't know how to handle these. */
1862 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1863 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1865 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1866 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1869 /* No way to handle; it'll most likely trap anyway. */
1872 if ((get_frame_register_unsigned (frame
,
1873 dspctl
) & 0x7f) >= pos
)
1874 pc
+= micromips_relative_offset16 (insn
);
1876 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1880 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1881 /* BC1ANY2F: bits 010000 11100 xxx01 */
1882 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1883 /* BC1ANY2T: bits 010000 11101 xxx01 */
1884 if (((insn
>> 16) & 0x2) == 0x0)
1885 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1886 ((insn
>> 16) & 0x1) + 1);
1889 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1890 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1891 if (((insn
>> 16) & 0x3) == 0x1)
1892 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1897 case 0x1d: /* JALS: bits 011101 */
1898 case 0x35: /* J: bits 110101 */
1899 case 0x3d: /* JAL: bits 111101 */
1900 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1903 case 0x25: /* BEQ: bits 100101 */
1904 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1905 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1906 pc
+= micromips_relative_offset16 (insn
);
1908 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1911 case 0x2d: /* BNE: bits 101101 */
1912 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1913 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1914 pc
+= micromips_relative_offset16 (insn
);
1916 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1919 case 0x3c: /* JALX: bits 111100 */
1920 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1925 /* 16-bit instructions. */
1926 case MIPS_INSN16_SIZE
:
1927 switch (micromips_op (insn
))
1929 case 0x11: /* POOL16C: bits 010001 */
1930 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1931 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1932 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1933 else if (b5s5_op (insn
) == 0x18)
1934 /* JRADDIUSP: bits 010001 11000 */
1935 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1938 case 0x23: /* BEQZ16: bits 100011 */
1940 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1942 if (get_frame_register_signed (frame
, rs
) == 0)
1943 pc
+= micromips_relative_offset7 (insn
);
1945 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1949 case 0x2b: /* BNEZ16: bits 101011 */
1951 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1953 if (get_frame_register_signed (frame
, rs
) != 0)
1954 pc
+= micromips_relative_offset7 (insn
);
1956 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1960 case 0x33: /* B16: bits 110011 */
1961 pc
+= micromips_relative_offset10 (insn
);
1970 /* Decoding the next place to set a breakpoint is irregular for the
1971 mips 16 variant, but fortunately, there fewer instructions. We have
1972 to cope ith extensions for 16 bit instructions and a pair of actual
1973 32 bit instructions. We dont want to set a single step instruction
1974 on the extend instruction either. */
1976 /* Lots of mips16 instruction formats */
1977 /* Predicting jumps requires itype,ritype,i8type
1978 and their extensions extItype,extritype,extI8type. */
1979 enum mips16_inst_fmts
1981 itype
, /* 0 immediate 5,10 */
1982 ritype
, /* 1 5,3,8 */
1983 rrtype
, /* 2 5,3,3,5 */
1984 rritype
, /* 3 5,3,3,5 */
1985 rrrtype
, /* 4 5,3,3,3,2 */
1986 rriatype
, /* 5 5,3,3,1,4 */
1987 shifttype
, /* 6 5,3,3,3,2 */
1988 i8type
, /* 7 5,3,8 */
1989 i8movtype
, /* 8 5,3,3,5 */
1990 i8mov32rtype
, /* 9 5,3,5,3 */
1991 i64type
, /* 10 5,3,8 */
1992 ri64type
, /* 11 5,3,3,5 */
1993 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1994 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1995 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1996 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1997 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1998 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1999 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2000 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2001 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2002 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2004 /* I am heaping all the fields of the formats into one structure and
2005 then, only the fields which are involved in instruction extension. */
2009 unsigned int regx
; /* Function in i8 type. */
2014 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2015 for the bits which make up the immediate extension. */
2018 extended_offset (unsigned int extension
)
2022 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2024 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2026 value
|= extension
& 0x1f; /* Extract 4:0. */
2031 /* Only call this function if you know that this is an extendable
2032 instruction. It won't malfunction, but why make excess remote memory
2033 references? If the immediate operands get sign extended or something,
2034 do it after the extension is performed. */
2035 /* FIXME: Every one of these cases needs to worry about sign extension
2036 when the offset is to be used in relative addressing. */
2039 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2041 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2044 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2045 target_read_memory (pc
, buf
, 2);
2046 return extract_unsigned_integer (buf
, 2, byte_order
);
2050 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2051 unsigned int extension
,
2053 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2058 switch (insn_format
)
2065 value
= extended_offset ((extension
<< 16) | inst
);
2066 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2070 value
= inst
& 0x7ff;
2071 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2080 { /* A register identifier and an offset. */
2081 /* Most of the fields are the same as I type but the
2082 immediate value is of a different length. */
2086 value
= extended_offset ((extension
<< 16) | inst
);
2087 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2091 value
= inst
& 0xff; /* 8 bits */
2092 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2095 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2101 unsigned long value
;
2102 unsigned int nexthalf
;
2103 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2104 value
= value
<< 16;
2105 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2106 /* Low bit still set. */
2114 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2116 upk
->offset
= offset
;
2123 add_offset_16 (CORE_ADDR pc
, int offset
)
2125 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2129 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2130 unsigned int extension
, unsigned int insn
)
2132 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2133 int op
= (insn
>> 11);
2136 case 2: /* Branch */
2138 struct upk_mips16 upk
;
2139 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2140 pc
+= (upk
.offset
<< 1) + 2;
2143 case 3: /* JAL , JALX - Watch out, these are 32 bit
2146 struct upk_mips16 upk
;
2147 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2148 pc
= add_offset_16 (pc
, upk
.offset
);
2149 if ((insn
>> 10) & 0x01) /* Exchange mode */
2150 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2157 struct upk_mips16 upk
;
2159 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2160 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2162 pc
+= (upk
.offset
<< 1) + 2;
2169 struct upk_mips16 upk
;
2171 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2172 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2174 pc
+= (upk
.offset
<< 1) + 2;
2179 case 12: /* I8 Formats btez btnez */
2181 struct upk_mips16 upk
;
2183 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2184 /* upk.regx contains the opcode */
2185 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2186 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2187 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2188 /* pc = add_offset_16(pc,upk.offset) ; */
2189 pc
+= (upk
.offset
<< 1) + 2;
2194 case 29: /* RR Formats JR, JALR, JALR-RA */
2196 struct upk_mips16 upk
;
2197 /* upk.fmt = rrtype; */
2202 upk
.regx
= (insn
>> 8) & 0x07;
2203 upk
.regy
= (insn
>> 5) & 0x07;
2204 if ((upk
.regy
& 1) == 0)
2205 reg
= mips_reg3_to_reg
[upk
.regx
];
2207 reg
= 31; /* Function return instruction. */
2208 pc
= get_frame_register_signed (frame
, reg
);
2215 /* This is an instruction extension. Fetch the real instruction
2216 (which follows the extension) and decode things based on
2220 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2221 fetch_mips_16 (gdbarch
, pc
));
2234 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2236 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2237 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2238 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2241 /* The mips_next_pc function supports single_step when the remote
2242 target monitor or stub is not developed enough to do a single_step.
2243 It works by decoding the current instruction and predicting where a
2244 branch will go. This isn't hard because all the data is available.
2245 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2247 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2249 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2251 if (mips_pc_is_mips16 (gdbarch
, pc
))
2252 return mips16_next_pc (frame
, pc
);
2253 else if (mips_pc_is_micromips (gdbarch
, pc
))
2254 return micromips_next_pc (frame
, pc
);
2256 return mips32_next_pc (frame
, pc
);
2259 struct mips_frame_cache
2262 struct trad_frame_saved_reg
*saved_regs
;
2265 /* Set a register's saved stack address in temp_saved_regs. If an
2266 address has already been set for this register, do nothing; this
2267 way we will only recognize the first save of a given register in a
2270 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2271 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2272 Strictly speaking, only the second range is used as it is only second
2273 range (the ABI instead of ISA registers) that comes into play when finding
2274 saved registers in a frame. */
2277 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2278 int regnum
, CORE_ADDR offset
)
2280 if (this_cache
!= NULL
2281 && this_cache
->saved_regs
[regnum
].addr
== -1)
2283 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2285 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2291 /* Fetch the immediate value from a MIPS16 instruction.
2292 If the previous instruction was an EXTEND, use it to extend
2293 the upper bits of the immediate value. This is a helper function
2294 for mips16_scan_prologue. */
2297 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2298 unsigned short inst
, /* current instruction */
2299 int nbits
, /* number of bits in imm field */
2300 int scale
, /* scale factor to be applied to imm */
2301 int is_signed
) /* is the imm field signed? */
2305 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2307 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2308 if (offset
& 0x8000) /* check for negative extend */
2309 offset
= 0 - (0x10000 - (offset
& 0xffff));
2310 return offset
| (inst
& 0x1f);
2314 int max_imm
= 1 << nbits
;
2315 int mask
= max_imm
- 1;
2316 int sign_bit
= max_imm
>> 1;
2318 offset
= inst
& mask
;
2319 if (is_signed
&& (offset
& sign_bit
))
2320 offset
= 0 - (max_imm
- offset
);
2321 return offset
* scale
;
2326 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2327 the associated FRAME_CACHE if not null.
2328 Return the address of the first instruction past the prologue. */
2331 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2332 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2333 struct frame_info
*this_frame
,
2334 struct mips_frame_cache
*this_cache
)
2337 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2339 long frame_offset
= 0; /* Size of stack frame. */
2340 long frame_adjust
= 0; /* Offset of FP from SP. */
2341 int frame_reg
= MIPS_SP_REGNUM
;
2342 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2343 unsigned inst
= 0; /* current instruction */
2344 unsigned entry_inst
= 0; /* the entry instruction */
2345 unsigned save_inst
= 0; /* the save instruction */
2348 int extend_bytes
= 0;
2349 int prev_extend_bytes
;
2350 CORE_ADDR end_prologue_addr
= 0;
2352 /* Can be called when there's no process, and hence when there's no
2354 if (this_frame
!= NULL
)
2355 sp
= get_frame_register_signed (this_frame
,
2356 gdbarch_num_regs (gdbarch
)
2361 if (limit_pc
> start_pc
+ 200)
2362 limit_pc
= start_pc
+ 200;
2364 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2366 /* Save the previous instruction. If it's an EXTEND, we'll extract
2367 the immediate offset extension from it in mips16_get_imm. */
2370 /* Fetch and decode the instruction. */
2371 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2374 /* Normally we ignore extend instructions. However, if it is
2375 not followed by a valid prologue instruction, then this
2376 instruction is not part of the prologue either. We must
2377 remember in this case to adjust the end_prologue_addr back
2379 if ((inst
& 0xf800) == 0xf000) /* extend */
2381 extend_bytes
= MIPS_INSN16_SIZE
;
2385 prev_extend_bytes
= extend_bytes
;
2388 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2389 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2391 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2392 if (offset
< 0) /* Negative stack adjustment? */
2393 frame_offset
-= offset
;
2395 /* Exit loop if a positive stack adjustment is found, which
2396 usually means that the stack cleanup code in the function
2397 epilogue is reached. */
2400 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2402 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2403 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2404 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2406 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2408 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2409 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2410 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2412 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2414 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2415 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2417 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2419 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2420 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2422 else if (inst
== 0x673d) /* move $s1, $sp */
2427 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2429 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2430 frame_addr
= sp
+ offset
;
2432 frame_adjust
= offset
;
2434 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2436 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2437 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2438 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2440 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2442 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2443 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2444 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2446 else if ((inst
& 0xf81f) == 0xe809
2447 && (inst
& 0x700) != 0x700) /* entry */
2448 entry_inst
= inst
; /* Save for later processing. */
2449 else if ((inst
& 0xff80) == 0x6480) /* save */
2451 save_inst
= inst
; /* Save for later processing. */
2452 if (prev_extend_bytes
) /* extend */
2453 save_inst
|= prev_inst
<< 16;
2455 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2456 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2457 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2459 /* This instruction is part of the prologue, but we don't
2460 need to do anything special to handle it. */
2464 /* This instruction is not an instruction typically found
2465 in a prologue, so we must have reached the end of the
2467 if (end_prologue_addr
== 0)
2468 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2472 /* The entry instruction is typically the first instruction in a function,
2473 and it stores registers at offsets relative to the value of the old SP
2474 (before the prologue). But the value of the sp parameter to this
2475 function is the new SP (after the prologue has been executed). So we
2476 can't calculate those offsets until we've seen the entire prologue,
2477 and can calculate what the old SP must have been. */
2478 if (entry_inst
!= 0)
2480 int areg_count
= (entry_inst
>> 8) & 7;
2481 int sreg_count
= (entry_inst
>> 6) & 3;
2483 /* The entry instruction always subtracts 32 from the SP. */
2486 /* Now we can calculate what the SP must have been at the
2487 start of the function prologue. */
2490 /* Check if a0-a3 were saved in the caller's argument save area. */
2491 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2493 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2494 offset
+= mips_abi_regsize (gdbarch
);
2497 /* Check if the ra register was pushed on the stack. */
2499 if (entry_inst
& 0x20)
2501 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2502 offset
-= mips_abi_regsize (gdbarch
);
2505 /* Check if the s0 and s1 registers were pushed on the stack. */
2506 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2508 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2509 offset
-= mips_abi_regsize (gdbarch
);
2513 /* The SAVE instruction is similar to ENTRY, except that defined by the
2514 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2515 size of the frame is specified as an immediate field of instruction
2516 and an extended variation exists which lets additional registers and
2517 frame space to be specified. The instruction always treats registers
2518 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2519 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2521 static int args_table
[16] = {
2522 0, 0, 0, 0, 1, 1, 1, 1,
2523 2, 2, 2, 0, 3, 3, 4, -1,
2525 static int astatic_table
[16] = {
2526 0, 1, 2, 3, 0, 1, 2, 3,
2527 0, 1, 2, 4, 0, 1, 0, -1,
2529 int aregs
= (save_inst
>> 16) & 0xf;
2530 int xsregs
= (save_inst
>> 24) & 0x7;
2531 int args
= args_table
[aregs
];
2532 int astatic
= astatic_table
[aregs
];
2537 warning (_("Invalid number of argument registers encoded in SAVE."));
2542 warning (_("Invalid number of static registers encoded in SAVE."));
2546 /* For standard SAVE the frame size of 0 means 128. */
2547 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2548 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2551 frame_offset
+= frame_size
;
2553 /* Now we can calculate what the SP must have been at the
2554 start of the function prologue. */
2557 /* Check if A0-A3 were saved in the caller's argument save area. */
2558 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2560 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2561 offset
+= mips_abi_regsize (gdbarch
);
2566 /* Check if the RA register was pushed on the stack. */
2567 if (save_inst
& 0x40)
2569 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2570 offset
-= mips_abi_regsize (gdbarch
);
2573 /* Check if the S8 register was pushed on the stack. */
2576 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2577 offset
-= mips_abi_regsize (gdbarch
);
2580 /* Check if S2-S7 were pushed on the stack. */
2581 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2583 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2584 offset
-= mips_abi_regsize (gdbarch
);
2587 /* Check if the S1 register was pushed on the stack. */
2588 if (save_inst
& 0x10)
2590 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2591 offset
-= mips_abi_regsize (gdbarch
);
2593 /* Check if the S0 register was pushed on the stack. */
2594 if (save_inst
& 0x20)
2596 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2597 offset
-= mips_abi_regsize (gdbarch
);
2600 /* Check if A0-A3 were pushed on the stack. */
2601 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2603 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2604 offset
-= mips_abi_regsize (gdbarch
);
2608 if (this_cache
!= NULL
)
2611 (get_frame_register_signed (this_frame
,
2612 gdbarch_num_regs (gdbarch
) + frame_reg
)
2613 + frame_offset
- frame_adjust
);
2614 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2615 be able to get rid of the assignment below, evetually. But it's
2616 still needed for now. */
2617 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2618 + mips_regnum (gdbarch
)->pc
]
2619 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2622 /* If we didn't reach the end of the prologue when scanning the function
2623 instructions, then set end_prologue_addr to the address of the
2624 instruction immediately after the last one we scanned. */
2625 if (end_prologue_addr
== 0)
2626 end_prologue_addr
= cur_pc
;
2628 return end_prologue_addr
;
2631 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2632 Procedures that use the 32-bit instruction set are handled by the
2633 mips_insn32 unwinder. */
2635 static struct mips_frame_cache
*
2636 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2638 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2639 struct mips_frame_cache
*cache
;
2641 if ((*this_cache
) != NULL
)
2642 return (*this_cache
);
2643 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2644 (*this_cache
) = cache
;
2645 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2647 /* Analyze the function prologue. */
2649 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2650 CORE_ADDR start_addr
;
2652 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2653 if (start_addr
== 0)
2654 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2655 /* We can't analyze the prologue if we couldn't find the begining
2657 if (start_addr
== 0)
2660 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2663 /* gdbarch_sp_regnum contains the value and not the address. */
2664 trad_frame_set_value (cache
->saved_regs
,
2665 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2668 return (*this_cache
);
2672 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2673 struct frame_id
*this_id
)
2675 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2677 /* This marks the outermost frame. */
2678 if (info
->base
== 0)
2680 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2683 static struct value
*
2684 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2685 void **this_cache
, int regnum
)
2687 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2689 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2693 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2694 struct frame_info
*this_frame
, void **this_cache
)
2696 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2697 CORE_ADDR pc
= get_frame_pc (this_frame
);
2698 if (mips_pc_is_mips16 (gdbarch
, pc
))
2703 static const struct frame_unwind mips_insn16_frame_unwind
=
2706 default_frame_unwind_stop_reason
,
2707 mips_insn16_frame_this_id
,
2708 mips_insn16_frame_prev_register
,
2710 mips_insn16_frame_sniffer
2714 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2717 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2722 static const struct frame_base mips_insn16_frame_base
=
2724 &mips_insn16_frame_unwind
,
2725 mips_insn16_frame_base_address
,
2726 mips_insn16_frame_base_address
,
2727 mips_insn16_frame_base_address
2730 static const struct frame_base
*
2731 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2733 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2734 CORE_ADDR pc
= get_frame_pc (this_frame
);
2735 if (mips_pc_is_mips16 (gdbarch
, pc
))
2736 return &mips_insn16_frame_base
;
2741 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2742 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2743 interpreted directly, and then multiplied by 4. */
2746 micromips_decode_imm9 (int imm
)
2748 imm
= (imm
^ 0x100) - 0x100;
2749 if (imm
> -3 && imm
< 2)
2754 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2755 the address of the first instruction past the prologue. */
2758 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2759 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2760 struct frame_info
*this_frame
,
2761 struct mips_frame_cache
*this_cache
)
2763 CORE_ADDR end_prologue_addr
= 0;
2764 int prev_non_prologue_insn
= 0;
2765 int frame_reg
= MIPS_SP_REGNUM
;
2766 int this_non_prologue_insn
;
2767 int non_prologue_insns
= 0;
2768 long frame_offset
= 0; /* Size of stack frame. */
2769 long frame_adjust
= 0; /* Offset of FP from SP. */
2770 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2773 ULONGEST insn
; /* current instruction */
2777 long v1_off
= 0; /* The assumption is LUI will replace it. */
2788 /* Can be called when there's no process, and hence when there's no
2790 if (this_frame
!= NULL
)
2791 sp
= get_frame_register_signed (this_frame
,
2792 gdbarch_num_regs (gdbarch
)
2797 if (limit_pc
> start_pc
+ 200)
2798 limit_pc
= start_pc
+ 200;
2801 /* Permit at most one non-prologue non-control-transfer instruction
2802 in the middle which may have been reordered by the compiler for
2804 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2806 this_non_prologue_insn
= 0;
2809 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2810 loc
+= MIPS_INSN16_SIZE
;
2811 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2813 /* 48-bit instructions. */
2814 case 3 * MIPS_INSN16_SIZE
:
2815 /* No prologue instructions in this category. */
2816 this_non_prologue_insn
= 1;
2817 loc
+= 2 * MIPS_INSN16_SIZE
;
2820 /* 32-bit instructions. */
2821 case 2 * MIPS_INSN16_SIZE
:
2823 insn
|= mips_fetch_instruction (gdbarch
,
2824 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2825 loc
+= MIPS_INSN16_SIZE
;
2826 switch (micromips_op (insn
>> 16))
2828 /* Record $sp/$fp adjustment. */
2829 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2830 case 0x0: /* POOL32A: bits 000000 */
2831 case 0x16: /* POOL32S: bits 010110 */
2832 op
= b0s11_op (insn
);
2833 sreg
= b0s5_reg (insn
>> 16);
2834 treg
= b5s5_reg (insn
>> 16);
2835 dreg
= b11s5_reg (insn
);
2837 /* SUBU: bits 000000 00111010000 */
2838 /* DSUBU: bits 010110 00111010000 */
2839 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2841 /* (D)SUBU $sp, $v1 */
2843 else if (op
!= 0x150
2844 /* ADDU: bits 000000 00101010000 */
2845 /* DADDU: bits 010110 00101010000 */
2846 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2847 this_non_prologue_insn
= 1;
2850 case 0x8: /* POOL32B: bits 001000 */
2851 op
= b12s4_op (insn
);
2852 breg
= b0s5_reg (insn
>> 16);
2853 reglist
= sreg
= b5s5_reg (insn
>> 16);
2854 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2855 if ((op
== 0x9 || op
== 0xc)
2856 /* SWP: bits 001000 1001 */
2857 /* SDP: bits 001000 1100 */
2858 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2859 /* S[DW]P reg,offset($sp) */
2861 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2862 set_reg_offset (gdbarch
, this_cache
,
2864 set_reg_offset (gdbarch
, this_cache
,
2865 sreg
+ 1, sp
+ offset
+ s
);
2867 else if ((op
== 0xd || op
== 0xf)
2868 /* SWM: bits 001000 1101 */
2869 /* SDM: bits 001000 1111 */
2870 && breg
== MIPS_SP_REGNUM
2871 /* SWM reglist,offset($sp) */
2872 && ((reglist
>= 1 && reglist
<= 9)
2873 || (reglist
>= 16 && reglist
<= 25)))
2875 int sreglist
= min(reglist
& 0xf, 8);
2877 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2878 for (i
= 0; i
< sreglist
; i
++)
2879 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2880 if ((reglist
& 0xf) > 8)
2881 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2882 if ((reglist
& 0x10) == 0x10)
2883 set_reg_offset (gdbarch
, this_cache
,
2884 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2887 this_non_prologue_insn
= 1;
2890 /* Record $sp/$fp adjustment. */
2891 /* Discard (D)ADDIU $gp used for PIC code. */
2892 case 0xc: /* ADDIU: bits 001100 */
2893 case 0x17: /* DADDIU: bits 010111 */
2894 sreg
= b0s5_reg (insn
>> 16);
2895 dreg
= b5s5_reg (insn
>> 16);
2896 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2897 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2898 /* (D)ADDIU $sp, imm */
2900 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2901 /* (D)ADDIU $fp, $sp, imm */
2903 frame_addr
= sp
+ offset
;
2904 frame_adjust
= offset
;
2907 else if (sreg
!= 28 || dreg
!= 28)
2908 /* (D)ADDIU $gp, imm */
2909 this_non_prologue_insn
= 1;
2912 /* LUI $v1 is used for larger $sp adjustments. */
2913 /* Discard LUI $gp used for PIC code. */
2914 case 0x10: /* POOL32I: bits 010000 */
2915 if (b5s5_op (insn
>> 16) == 0xd
2916 /* LUI: bits 010000 001101 */
2917 && b0s5_reg (insn
>> 16) == 3)
2919 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
2920 else if (b5s5_op (insn
>> 16) != 0xd
2921 /* LUI: bits 010000 001101 */
2922 || b0s5_reg (insn
>> 16) != 28)
2924 this_non_prologue_insn
= 1;
2927 /* ORI $v1 is used for larger $sp adjustments. */
2928 case 0x14: /* ORI: bits 010100 */
2929 sreg
= b0s5_reg (insn
>> 16);
2930 dreg
= b5s5_reg (insn
>> 16);
2931 if (sreg
== 3 && dreg
== 3)
2933 v1_off
|= b0s16_imm (insn
);
2935 this_non_prologue_insn
= 1;
2938 case 0x26: /* SWC1: bits 100110 */
2939 case 0x2e: /* SDC1: bits 101110 */
2940 breg
= b0s5_reg (insn
>> 16);
2941 if (breg
!= MIPS_SP_REGNUM
)
2942 /* S[DW]C1 reg,offset($sp) */
2943 this_non_prologue_insn
= 1;
2946 case 0x36: /* SD: bits 110110 */
2947 case 0x3e: /* SW: bits 111110 */
2948 breg
= b0s5_reg (insn
>> 16);
2949 sreg
= b5s5_reg (insn
>> 16);
2950 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2951 if (breg
== MIPS_SP_REGNUM
)
2952 /* S[DW] reg,offset($sp) */
2953 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2955 this_non_prologue_insn
= 1;
2959 this_non_prologue_insn
= 1;
2964 /* 16-bit instructions. */
2965 case MIPS_INSN16_SIZE
:
2966 switch (micromips_op (insn
))
2968 case 0x3: /* MOVE: bits 000011 */
2969 sreg
= b0s5_reg (insn
);
2970 dreg
= b5s5_reg (insn
);
2971 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2977 else if ((sreg
& 0x1c) != 0x4)
2978 /* MOVE reg, $a0-$a3 */
2979 this_non_prologue_insn
= 1;
2982 case 0x11: /* POOL16C: bits 010001 */
2983 if (b6s4_op (insn
) == 0x5)
2984 /* SWM: bits 010001 0101 */
2986 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
2987 reglist
= b4s2_regl (insn
);
2988 for (i
= 0; i
<= reglist
; i
++)
2989 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
2990 set_reg_offset (gdbarch
, this_cache
,
2991 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
2994 this_non_prologue_insn
= 1;
2997 case 0x13: /* POOL16D: bits 010011 */
2998 if ((insn
& 0x1) == 0x1)
2999 /* ADDIUSP: bits 010011 1 */
3000 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3001 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3002 /* ADDIUS5: bits 010011 0 */
3003 /* ADDIUS5 $sp, imm */
3004 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3006 this_non_prologue_insn
= 1;
3009 case 0x32: /* SWSP: bits 110010 */
3010 offset
= b0s5_imm (insn
) << 2;
3011 sreg
= b5s5_reg (insn
);
3012 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3016 this_non_prologue_insn
= 1;
3022 frame_offset
-= sp_adj
;
3024 non_prologue_insns
+= this_non_prologue_insn
;
3025 /* Enough non-prologue insns seen or positive stack adjustment? */
3026 if (end_prologue_addr
== 0 && (non_prologue_insns
> 1 || sp_adj
> 0))
3028 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3031 prev_non_prologue_insn
= this_non_prologue_insn
;
3035 if (this_cache
!= NULL
)
3038 (get_frame_register_signed (this_frame
,
3039 gdbarch_num_regs (gdbarch
) + frame_reg
)
3040 + frame_offset
- frame_adjust
);
3041 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3042 be able to get rid of the assignment below, evetually. But it's
3043 still needed for now. */
3044 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3045 + mips_regnum (gdbarch
)->pc
]
3046 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3049 /* If we didn't reach the end of the prologue when scanning the function
3050 instructions, then set end_prologue_addr to the address of the
3051 instruction immediately after the last one we scanned. Unless the
3052 last one looked like a non-prologue instruction (and we looked ahead),
3053 in which case use its address instead. */
3054 if (end_prologue_addr
== 0)
3055 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3057 return end_prologue_addr
;
3060 /* Heuristic unwinder for procedures using microMIPS instructions.
3061 Procedures that use the 32-bit instruction set are handled by the
3062 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3064 static struct mips_frame_cache
*
3065 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3067 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3068 struct mips_frame_cache
*cache
;
3070 if ((*this_cache
) != NULL
)
3071 return (*this_cache
);
3073 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3074 (*this_cache
) = cache
;
3075 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3077 /* Analyze the function prologue. */
3079 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3080 CORE_ADDR start_addr
;
3082 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3083 if (start_addr
== 0)
3084 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3085 /* We can't analyze the prologue if we couldn't find the begining
3087 if (start_addr
== 0)
3090 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3093 /* gdbarch_sp_regnum contains the value and not the address. */
3094 trad_frame_set_value (cache
->saved_regs
,
3095 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3098 return (*this_cache
);
3102 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3103 struct frame_id
*this_id
)
3105 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3107 /* This marks the outermost frame. */
3108 if (info
->base
== 0)
3110 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3113 static struct value
*
3114 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3115 void **this_cache
, int regnum
)
3117 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3119 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3123 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3124 struct frame_info
*this_frame
, void **this_cache
)
3126 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3127 CORE_ADDR pc
= get_frame_pc (this_frame
);
3129 if (mips_pc_is_micromips (gdbarch
, pc
))
3134 static const struct frame_unwind mips_micro_frame_unwind
=
3137 default_frame_unwind_stop_reason
,
3138 mips_micro_frame_this_id
,
3139 mips_micro_frame_prev_register
,
3141 mips_micro_frame_sniffer
3145 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3148 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3153 static const struct frame_base mips_micro_frame_base
=
3155 &mips_micro_frame_unwind
,
3156 mips_micro_frame_base_address
,
3157 mips_micro_frame_base_address
,
3158 mips_micro_frame_base_address
3161 static const struct frame_base
*
3162 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3164 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3165 CORE_ADDR pc
= get_frame_pc (this_frame
);
3167 if (mips_pc_is_micromips (gdbarch
, pc
))
3168 return &mips_micro_frame_base
;
3173 /* Mark all the registers as unset in the saved_regs array
3174 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3177 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3179 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3183 const int num_regs
= gdbarch_num_regs (gdbarch
);
3186 for (i
= 0; i
< num_regs
; i
++)
3188 this_cache
->saved_regs
[i
].addr
= -1;
3193 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3194 the associated FRAME_CACHE if not null.
3195 Return the address of the first instruction past the prologue. */
3198 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3199 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3200 struct frame_info
*this_frame
,
3201 struct mips_frame_cache
*this_cache
)
3204 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3208 int frame_reg
= MIPS_SP_REGNUM
;
3210 CORE_ADDR end_prologue_addr
= 0;
3211 int seen_sp_adjust
= 0;
3212 int load_immediate_bytes
= 0;
3213 int in_delay_slot
= 0;
3214 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3216 /* Can be called when there's no process, and hence when there's no
3218 if (this_frame
!= NULL
)
3219 sp
= get_frame_register_signed (this_frame
,
3220 gdbarch_num_regs (gdbarch
)
3225 if (limit_pc
> start_pc
+ 200)
3226 limit_pc
= start_pc
+ 200;
3231 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3233 unsigned long inst
, high_word
, low_word
;
3236 /* Fetch the instruction. */
3237 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3240 /* Save some code by pre-extracting some useful fields. */
3241 high_word
= (inst
>> 16) & 0xffff;
3242 low_word
= inst
& 0xffff;
3243 reg
= high_word
& 0x1f;
3245 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3246 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3247 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3249 if (low_word
& 0x8000) /* Negative stack adjustment? */
3250 frame_offset
+= 0x10000 - low_word
;
3252 /* Exit loop if a positive stack adjustment is found, which
3253 usually means that the stack cleanup code in the function
3254 epilogue is reached. */
3258 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3259 && !regsize_is_64_bits
)
3261 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3263 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3264 && regsize_is_64_bits
)
3266 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3267 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3269 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3271 /* Old gcc frame, r30 is virtual frame pointer. */
3272 if ((long) low_word
!= frame_offset
)
3273 frame_addr
= sp
+ low_word
;
3274 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3276 unsigned alloca_adjust
;
3279 frame_addr
= get_frame_register_signed
3280 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3283 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3284 if (alloca_adjust
> 0)
3286 /* FP > SP + frame_size. This may be because of
3287 an alloca or somethings similar. Fix sp to
3288 "pre-alloca" value, and try again. */
3289 sp
+= alloca_adjust
;
3290 /* Need to reset the status of all registers. Otherwise,
3291 we will hit a guard that prevents the new address
3292 for each register to be recomputed during the second
3294 reset_saved_regs (gdbarch
, this_cache
);
3299 /* move $30,$sp. With different versions of gas this will be either
3300 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3301 Accept any one of these. */
3302 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3304 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3305 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3307 unsigned alloca_adjust
;
3310 frame_addr
= get_frame_register_signed
3311 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3313 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3314 if (alloca_adjust
> 0)
3316 /* FP > SP + frame_size. This may be because of
3317 an alloca or somethings similar. Fix sp to
3318 "pre-alloca" value, and try again. */
3320 /* Need to reset the status of all registers. Otherwise,
3321 we will hit a guard that prevents the new address
3322 for each register to be recomputed during the second
3324 reset_saved_regs (gdbarch
, this_cache
);
3329 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3330 && !regsize_is_64_bits
)
3332 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3334 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3335 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3336 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3337 || high_word
== 0x3c1c /* lui $gp,n */
3338 || high_word
== 0x279c /* addiu $gp,$gp,n */
3339 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3340 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3343 /* These instructions are part of the prologue, but we don't
3344 need to do anything special to handle them. */
3346 /* The instructions below load $at or $t0 with an immediate
3347 value in preparation for a stack adjustment via
3348 subu $sp,$sp,[$at,$t0]. These instructions could also
3349 initialize a local variable, so we accept them only before
3350 a stack adjustment instruction was seen. */
3351 else if (!seen_sp_adjust
3352 && (high_word
== 0x3c01 /* lui $at,n */
3353 || high_word
== 0x3c08 /* lui $t0,n */
3354 || high_word
== 0x3421 /* ori $at,$at,n */
3355 || high_word
== 0x3508 /* ori $t0,$t0,n */
3356 || high_word
== 0x3401 /* ori $at,$zero,n */
3357 || high_word
== 0x3408 /* ori $t0,$zero,n */
3360 if (end_prologue_addr
== 0)
3361 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3365 /* This instruction is not an instruction typically found
3366 in a prologue, so we must have reached the end of the
3368 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3369 loop now? Why would we need to continue scanning the function
3371 if (end_prologue_addr
== 0)
3372 end_prologue_addr
= cur_pc
;
3374 /* Check for branches and jumps. For now, only jump to
3375 register are caught (i.e. returns). */
3376 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
3380 /* If the previous instruction was a jump, we must have reached
3381 the end of the prologue by now. Stop scanning so that we do
3382 not go past the function return. */
3387 if (this_cache
!= NULL
)
3390 (get_frame_register_signed (this_frame
,
3391 gdbarch_num_regs (gdbarch
) + frame_reg
)
3393 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3394 this assignment below, eventually. But it's still needed
3396 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3397 + mips_regnum (gdbarch
)->pc
]
3398 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3402 /* If we didn't reach the end of the prologue when scanning the function
3403 instructions, then set end_prologue_addr to the address of the
3404 instruction immediately after the last one we scanned. */
3405 /* brobecker/2004-10-10: I don't think this would ever happen, but
3406 we may as well be careful and do our best if we have a null
3407 end_prologue_addr. */
3408 if (end_prologue_addr
== 0)
3409 end_prologue_addr
= cur_pc
;
3411 /* In a frameless function, we might have incorrectly
3412 skipped some load immediate instructions. Undo the skipping
3413 if the load immediate was not followed by a stack adjustment. */
3414 if (load_immediate_bytes
&& !seen_sp_adjust
)
3415 end_prologue_addr
-= load_immediate_bytes
;
3417 return end_prologue_addr
;
3420 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3421 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3422 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3423 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3425 static struct mips_frame_cache
*
3426 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3428 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3429 struct mips_frame_cache
*cache
;
3431 if ((*this_cache
) != NULL
)
3432 return (*this_cache
);
3434 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3435 (*this_cache
) = cache
;
3436 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3438 /* Analyze the function prologue. */
3440 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3441 CORE_ADDR start_addr
;
3443 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3444 if (start_addr
== 0)
3445 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3446 /* We can't analyze the prologue if we couldn't find the begining
3448 if (start_addr
== 0)
3451 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3454 /* gdbarch_sp_regnum contains the value and not the address. */
3455 trad_frame_set_value (cache
->saved_regs
,
3456 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3459 return (*this_cache
);
3463 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3464 struct frame_id
*this_id
)
3466 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3468 /* This marks the outermost frame. */
3469 if (info
->base
== 0)
3471 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3474 static struct value
*
3475 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3476 void **this_cache
, int regnum
)
3478 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3480 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3484 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3485 struct frame_info
*this_frame
, void **this_cache
)
3487 CORE_ADDR pc
= get_frame_pc (this_frame
);
3488 if (mips_pc_is_mips (pc
))
3493 static const struct frame_unwind mips_insn32_frame_unwind
=
3496 default_frame_unwind_stop_reason
,
3497 mips_insn32_frame_this_id
,
3498 mips_insn32_frame_prev_register
,
3500 mips_insn32_frame_sniffer
3504 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3507 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3512 static const struct frame_base mips_insn32_frame_base
=
3514 &mips_insn32_frame_unwind
,
3515 mips_insn32_frame_base_address
,
3516 mips_insn32_frame_base_address
,
3517 mips_insn32_frame_base_address
3520 static const struct frame_base
*
3521 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3523 CORE_ADDR pc
= get_frame_pc (this_frame
);
3524 if (mips_pc_is_mips (pc
))
3525 return &mips_insn32_frame_base
;
3530 static struct trad_frame_cache
*
3531 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3534 CORE_ADDR start_addr
;
3535 CORE_ADDR stack_addr
;
3536 struct trad_frame_cache
*this_trad_cache
;
3537 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3538 int num_regs
= gdbarch_num_regs (gdbarch
);
3540 if ((*this_cache
) != NULL
)
3541 return (*this_cache
);
3542 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3543 (*this_cache
) = this_trad_cache
;
3545 /* The return address is in the link register. */
3546 trad_frame_set_reg_realreg (this_trad_cache
,
3547 gdbarch_pc_regnum (gdbarch
),
3548 num_regs
+ MIPS_RA_REGNUM
);
3550 /* Frame ID, since it's a frameless / stackless function, no stack
3551 space is allocated and SP on entry is the current SP. */
3552 pc
= get_frame_pc (this_frame
);
3553 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3554 stack_addr
= get_frame_register_signed (this_frame
,
3555 num_regs
+ MIPS_SP_REGNUM
);
3556 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3558 /* Assume that the frame's base is the same as the
3560 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3562 return this_trad_cache
;
3566 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3567 struct frame_id
*this_id
)
3569 struct trad_frame_cache
*this_trad_cache
3570 = mips_stub_frame_cache (this_frame
, this_cache
);
3571 trad_frame_get_id (this_trad_cache
, this_id
);
3574 static struct value
*
3575 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3576 void **this_cache
, int regnum
)
3578 struct trad_frame_cache
*this_trad_cache
3579 = mips_stub_frame_cache (this_frame
, this_cache
);
3580 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3584 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3585 struct frame_info
*this_frame
, void **this_cache
)
3588 struct obj_section
*s
;
3589 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3590 struct bound_minimal_symbol msym
;
3592 /* Use the stub unwinder for unreadable code. */
3593 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3596 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3599 /* Calling a PIC function from a non-PIC function passes through a
3600 stub. The stub for foo is named ".pic.foo". */
3601 msym
= lookup_minimal_symbol_by_pc (pc
);
3602 if (msym
.minsym
!= NULL
3603 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3604 && strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) == 0)
3610 static const struct frame_unwind mips_stub_frame_unwind
=
3613 default_frame_unwind_stop_reason
,
3614 mips_stub_frame_this_id
,
3615 mips_stub_frame_prev_register
,
3617 mips_stub_frame_sniffer
3621 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3624 struct trad_frame_cache
*this_trad_cache
3625 = mips_stub_frame_cache (this_frame
, this_cache
);
3626 return trad_frame_get_this_base (this_trad_cache
);
3629 static const struct frame_base mips_stub_frame_base
=
3631 &mips_stub_frame_unwind
,
3632 mips_stub_frame_base_address
,
3633 mips_stub_frame_base_address
,
3634 mips_stub_frame_base_address
3637 static const struct frame_base
*
3638 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3640 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3641 return &mips_stub_frame_base
;
3646 /* mips_addr_bits_remove - remove useless address bits */
3649 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3653 if (is_compact_addr (addr
))
3654 addr
= unmake_compact_addr (addr
);
3656 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3657 /* This hack is a work-around for existing boards using PMON, the
3658 simulator, and any other 64-bit targets that doesn't have true
3659 64-bit addressing. On these targets, the upper 32 bits of
3660 addresses are ignored by the hardware. Thus, the PC or SP are
3661 likely to have been sign extended to all 1s by instruction
3662 sequences that load 32-bit addresses. For example, a typical
3663 piece of code that loads an address is this:
3665 lui $r2, <upper 16 bits>
3666 ori $r2, <lower 16 bits>
3668 But the lui sign-extends the value such that the upper 32 bits
3669 may be all 1s. The workaround is simply to mask off these
3670 bits. In the future, gcc may be changed to support true 64-bit
3671 addressing, and this masking will have to be disabled. */
3672 return addr
&= 0xffffffffUL
;
3678 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3679 instruction and ending with a SC/SCD instruction. If such a sequence
3680 is found, attempt to step through it. A breakpoint is placed at the end of
3683 /* Instructions used during single-stepping of atomic sequences, standard
3685 #define LL_OPCODE 0x30
3686 #define LLD_OPCODE 0x34
3687 #define SC_OPCODE 0x38
3688 #define SCD_OPCODE 0x3c
3691 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3692 struct address_space
*aspace
, CORE_ADDR pc
)
3694 CORE_ADDR breaks
[2] = {-1, -1};
3696 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3700 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3701 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3703 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3704 /* Assume all atomic sequences start with a ll/lld instruction. */
3705 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3708 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3710 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3713 loc
+= MIPS_INSN32_SIZE
;
3714 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3716 /* Assume that there is at most one branch in the atomic
3717 sequence. If a branch is found, put a breakpoint in its
3718 destination address. */
3719 switch (itype_op (insn
))
3721 case 0: /* SPECIAL */
3722 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3723 return 0; /* fallback to the standard single-step code. */
3725 case 1: /* REGIMM */
3726 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3727 || ((itype_rt (insn
) & 0x1e) == 0
3728 && itype_rs (insn
) == 0)); /* BPOSGE* */
3732 return 0; /* fallback to the standard single-step code. */
3739 case 22: /* BLEZL */
3740 case 23: /* BGTTL */
3744 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3745 && (itype_rt (insn
) & 0x2) == 0);
3746 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3751 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3756 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3757 if (last_breakpoint
>= 1)
3758 return 0; /* More than one branch found, fallback to the
3759 standard single-step code. */
3760 breaks
[1] = branch_bp
;
3764 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3768 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3769 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3772 loc
+= MIPS_INSN32_SIZE
;
3774 /* Insert a breakpoint right after the end of the atomic sequence. */
3777 /* Check for duplicated breakpoints. Check also for a breakpoint
3778 placed (branch instruction's destination) in the atomic sequence. */
3779 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3780 last_breakpoint
= 0;
3782 /* Effectively inserts the breakpoints. */
3783 for (index
= 0; index
<= last_breakpoint
; index
++)
3784 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3790 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3791 struct address_space
*aspace
,
3794 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3795 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3796 CORE_ADDR breaks
[2] = {-1, -1};
3797 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3805 /* Assume all atomic sequences start with a ll/lld instruction. */
3806 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3807 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3809 loc
+= MIPS_INSN16_SIZE
;
3811 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3812 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3814 loc
+= MIPS_INSN16_SIZE
;
3816 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3817 that no atomic sequence is longer than "atomic_sequence_length"
3819 for (insn_count
= 0;
3820 !sc_found
&& insn_count
< atomic_sequence_length
;
3825 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3826 loc
+= MIPS_INSN16_SIZE
;
3828 /* Assume that there is at most one conditional branch in the
3829 atomic sequence. If a branch is found, put a breakpoint in
3830 its destination address. */
3831 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3833 /* 48-bit instructions. */
3834 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3835 loc
+= 2 * MIPS_INSN16_SIZE
;
3838 /* 32-bit instructions. */
3839 case 2 * MIPS_INSN16_SIZE
:
3840 switch (micromips_op (insn
))
3842 case 0x10: /* POOL32I: bits 010000 */
3843 if ((b5s5_op (insn
) & 0x18) != 0x0
3844 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3845 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3846 && (b5s5_op (insn
) & 0x1d) != 0x11
3847 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3848 && ((b5s5_op (insn
) & 0x1e) != 0x14
3849 || (insn
& 0x3) != 0x0)
3850 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3851 && (b5s5_op (insn
) & 0x1e) != 0x1a
3852 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3853 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3854 || (insn
& 0x3) != 0x0)
3855 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3856 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3857 || (insn
& 0x3) != 0x1))
3858 /* BC1ANY*: bits 010000 111xx xxx01 */
3862 case 0x25: /* BEQ: bits 100101 */
3863 case 0x2d: /* BNE: bits 101101 */
3865 insn
|= mips_fetch_instruction (gdbarch
,
3866 ISA_MICROMIPS
, loc
, NULL
);
3867 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3868 + micromips_relative_offset16 (insn
));
3872 case 0x00: /* POOL32A: bits 000000 */
3874 insn
|= mips_fetch_instruction (gdbarch
,
3875 ISA_MICROMIPS
, loc
, NULL
);
3876 if (b0s6_op (insn
) != 0x3c
3877 /* POOL32Axf: bits 000000 ... 111100 */
3878 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3879 /* JALR, JALR.HB: 000000 000x111100 111100 */
3880 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3884 case 0x1d: /* JALS: bits 011101 */
3885 case 0x35: /* J: bits 110101 */
3886 case 0x3d: /* JAL: bits 111101 */
3887 case 0x3c: /* JALX: bits 111100 */
3888 return 0; /* Fall back to the standard single-step code. */
3890 case 0x18: /* POOL32C: bits 011000 */
3891 if ((b12s4_op (insn
) & 0xb) == 0xb)
3892 /* SC, SCD: bits 011000 1x11 */
3896 loc
+= MIPS_INSN16_SIZE
;
3899 /* 16-bit instructions. */
3900 case MIPS_INSN16_SIZE
:
3901 switch (micromips_op (insn
))
3903 case 0x23: /* BEQZ16: bits 100011 */
3904 case 0x2b: /* BNEZ16: bits 101011 */
3905 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
3909 case 0x11: /* POOL16C: bits 010001 */
3910 if ((b5s5_op (insn
) & 0x1c) != 0xc
3911 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3912 && b5s5_op (insn
) != 0x18)
3913 /* JRADDIUSP: bits 010001 11000 */
3915 return 0; /* Fall back to the standard single-step code. */
3917 case 0x33: /* B16: bits 110011 */
3918 return 0; /* Fall back to the standard single-step code. */
3924 if (last_breakpoint
>= 1)
3925 return 0; /* More than one branch found, fallback to the
3926 standard single-step code. */
3927 breaks
[1] = branch_bp
;
3934 /* Insert a breakpoint right after the end of the atomic sequence. */
3937 /* Check for duplicated breakpoints. Check also for a breakpoint
3938 placed (branch instruction's destination) in the atomic sequence */
3939 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3940 last_breakpoint
= 0;
3942 /* Effectively inserts the breakpoints. */
3943 for (index
= 0; index
<= last_breakpoint
; index
++)
3944 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3950 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3951 struct address_space
*aspace
, CORE_ADDR pc
)
3953 if (mips_pc_is_mips (pc
))
3954 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3955 else if (mips_pc_is_micromips (gdbarch
, pc
))
3956 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3961 /* mips_software_single_step() is called just before we want to resume
3962 the inferior, if we want to single-step it but there is no hardware
3963 or kernel single-step support (MIPS on GNU/Linux for example). We find
3964 the target of the coming instruction and breakpoint it. */
3967 mips_software_single_step (struct frame_info
*frame
)
3969 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3970 struct address_space
*aspace
= get_frame_address_space (frame
);
3971 CORE_ADDR pc
, next_pc
;
3973 pc
= get_frame_pc (frame
);
3974 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
3977 next_pc
= mips_next_pc (frame
, pc
);
3979 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3983 /* Test whether the PC points to the return instruction at the
3984 end of a function. */
3987 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3992 /* This used to check for MIPS16, but this piece of code is never
3993 called for MIPS16 functions. And likewise microMIPS ones. */
3994 gdb_assert (mips_pc_is_mips (pc
));
3996 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
3998 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4002 /* This fencepost looks highly suspicious to me. Removing it also
4003 seems suspicious as it could affect remote debugging across serial
4007 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4013 struct inferior
*inf
;
4015 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4017 fence
= start_pc
- heuristic_fence_post
;
4021 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4022 fence
= VM_MIN_ADDRESS
;
4024 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4026 inf
= current_inferior ();
4028 /* Search back for previous return. */
4029 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4030 if (start_pc
< fence
)
4032 /* It's not clear to me why we reach this point when
4033 stop_soon, but with this test, at least we
4034 don't print out warnings for every child forked (eg, on
4035 decstation). 22apr93 rich@cygnus.com. */
4036 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4038 static int blurb_printed
= 0;
4040 warning (_("GDB can't find the start of the function at %s."),
4041 paddress (gdbarch
, pc
));
4045 /* This actually happens frequently in embedded
4046 development, when you first connect to a board
4047 and your stack pointer and pc are nowhere in
4048 particular. This message needs to give people
4049 in that situation enough information to
4050 determine that it's no big deal. */
4051 printf_filtered ("\n\
4052 GDB is unable to find the start of the function at %s\n\
4053 and thus can't determine the size of that function's stack frame.\n\
4054 This means that GDB may be unable to access that stack frame, or\n\
4055 the frames below it.\n\
4056 This problem is most likely caused by an invalid program counter or\n\
4058 However, if you think GDB should simply search farther back\n\
4059 from %s for code which looks like the beginning of a\n\
4060 function, you can increase the range of the search using the `set\n\
4061 heuristic-fence-post' command.\n",
4062 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4069 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4071 unsigned short inst
;
4073 /* On MIPS16, any one of the following is likely to be the
4074 start of a function:
4080 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4081 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4082 if ((inst
& 0xff80) == 0x6480) /* save */
4084 if (start_pc
- instlen
>= fence
)
4086 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4087 start_pc
- instlen
, NULL
);
4088 if ((inst
& 0xf800) == 0xf000) /* extend */
4089 start_pc
-= instlen
;
4093 else if (((inst
& 0xf81f) == 0xe809
4094 && (inst
& 0x700) != 0x700) /* entry */
4095 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4096 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4097 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4099 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4100 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4105 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4113 /* On microMIPS, any one of the following is likely to be the
4114 start of a function:
4118 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4119 switch (micromips_op (insn
))
4121 case 0xc: /* ADDIU: bits 001100 */
4122 case 0x17: /* DADDIU: bits 010111 */
4123 sreg
= b0s5_reg (insn
);
4124 dreg
= b5s5_reg (insn
);
4126 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4127 pc
+ MIPS_INSN16_SIZE
, NULL
);
4128 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4129 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4130 /* (D)ADDIU $sp, imm */
4135 case 0x10: /* POOL32I: bits 010000 */
4136 if (b5s5_op (insn
) == 0xd
4137 /* LUI: bits 010000 001101 */
4138 && b0s5_reg (insn
>> 16) == 28)
4143 case 0x13: /* POOL16D: bits 010011 */
4144 if ((insn
& 0x1) == 0x1)
4145 /* ADDIUSP: bits 010011 1 */
4147 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4153 /* ADDIUS5: bits 010011 0 */
4155 dreg
= b5s5_reg (insn
);
4156 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4157 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4158 /* ADDIUS5 $sp, -imm */
4166 else if (mips_about_to_return (gdbarch
, start_pc
))
4168 /* Skip return and its delay slot. */
4169 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4176 struct mips_objfile_private
4182 /* According to the current ABI, should the type be passed in a
4183 floating-point register (assuming that there is space)? When there
4184 is no FPU, FP are not even considered as possible candidates for
4185 FP registers and, consequently this returns false - forces FP
4186 arguments into integer registers. */
4189 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4190 struct type
*arg_type
)
4192 return ((typecode
== TYPE_CODE_FLT
4193 || (MIPS_EABI (gdbarch
)
4194 && (typecode
== TYPE_CODE_STRUCT
4195 || typecode
== TYPE_CODE_UNION
)
4196 && TYPE_NFIELDS (arg_type
) == 1
4197 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4199 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4202 /* On o32, argument passing in GPRs depends on the alignment of the type being
4203 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4206 mips_type_needs_double_align (struct type
*type
)
4208 enum type_code typecode
= TYPE_CODE (type
);
4210 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4212 else if (typecode
== TYPE_CODE_STRUCT
)
4214 if (TYPE_NFIELDS (type
) < 1)
4216 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4218 else if (typecode
== TYPE_CODE_UNION
)
4222 n
= TYPE_NFIELDS (type
);
4223 for (i
= 0; i
< n
; i
++)
4224 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4231 /* Adjust the address downward (direction of stack growth) so that it
4232 is correctly aligned for a new stack frame. */
4234 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4236 return align_down (addr
, 16);
4239 /* Implement the "push_dummy_code" gdbarch method. */
4242 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4243 CORE_ADDR funaddr
, struct value
**args
,
4244 int nargs
, struct type
*value_type
,
4245 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4246 struct regcache
*regcache
)
4248 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4252 /* Reserve enough room on the stack for our breakpoint instruction. */
4253 bp_slot
= sp
- sizeof (nop_insn
);
4255 /* Return to microMIPS mode if calling microMIPS code to avoid
4256 triggering an address error exception on processors that only
4257 support microMIPS execution. */
4258 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4259 ? make_compact_addr (bp_slot
) : bp_slot
);
4261 /* The breakpoint layer automatically adjusts the address of
4262 breakpoints inserted in a branch delay slot. With enough
4263 bad luck, the 4 bytes located just before our breakpoint
4264 instruction could look like a branch instruction, and thus
4265 trigger the adjustement, and break the function call entirely.
4266 So, we reserve those 4 bytes and write a nop instruction
4267 to prevent that from happening. */
4268 nop_addr
= bp_slot
- sizeof (nop_insn
);
4269 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4270 sp
= mips_frame_align (gdbarch
, nop_addr
);
4272 /* Inferior resumes at the function entry point. */
4279 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4280 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4281 int nargs
, struct value
**args
, CORE_ADDR sp
,
4282 int struct_return
, CORE_ADDR struct_addr
)
4288 int stack_offset
= 0;
4289 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4290 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4291 int regsize
= mips_abi_regsize (gdbarch
);
4293 /* For shared libraries, "t9" needs to point at the function
4295 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4297 /* Set the return address register to point to the entry point of
4298 the program, where a breakpoint lies in wait. */
4299 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4301 /* First ensure that the stack and structure return address (if any)
4302 are properly aligned. The stack has to be at least 64-bit
4303 aligned even on 32-bit machines, because doubles must be 64-bit
4304 aligned. For n32 and n64, stack frames need to be 128-bit
4305 aligned, so we round to this widest known alignment. */
4307 sp
= align_down (sp
, 16);
4308 struct_addr
= align_down (struct_addr
, 16);
4310 /* Now make space on the stack for the args. We allocate more
4311 than necessary for EABI, because the first few arguments are
4312 passed in registers, but that's OK. */
4313 for (argnum
= 0; argnum
< nargs
; argnum
++)
4314 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4315 sp
-= align_up (len
, 16);
4318 fprintf_unfiltered (gdb_stdlog
,
4319 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4320 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4322 /* Initialize the integer and float register pointers. */
4323 argreg
= MIPS_A0_REGNUM
;
4324 float_argreg
= mips_fpa0_regnum (gdbarch
);
4326 /* The struct_return pointer occupies the first parameter-passing reg. */
4330 fprintf_unfiltered (gdb_stdlog
,
4331 "mips_eabi_push_dummy_call: "
4332 "struct_return reg=%d %s\n",
4333 argreg
, paddress (gdbarch
, struct_addr
));
4334 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4337 /* Now load as many as possible of the first arguments into
4338 registers, and push the rest onto the stack. Loop thru args
4339 from first to last. */
4340 for (argnum
= 0; argnum
< nargs
; argnum
++)
4342 const gdb_byte
*val
;
4343 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4344 struct value
*arg
= args
[argnum
];
4345 struct type
*arg_type
= check_typedef (value_type (arg
));
4346 int len
= TYPE_LENGTH (arg_type
);
4347 enum type_code typecode
= TYPE_CODE (arg_type
);
4350 fprintf_unfiltered (gdb_stdlog
,
4351 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4352 argnum
+ 1, len
, (int) typecode
);
4354 /* Function pointer arguments to mips16 code need to be made into
4356 if (typecode
== TYPE_CODE_PTR
4357 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4359 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4361 if (mips_pc_is_mips (addr
))
4362 val
= value_contents (arg
);
4365 store_signed_integer (valbuf
, len
, byte_order
,
4366 make_compact_addr (addr
));
4370 /* The EABI passes structures that do not fit in a register by
4372 else if (len
> regsize
4373 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4375 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4376 value_address (arg
));
4377 typecode
= TYPE_CODE_PTR
;
4381 fprintf_unfiltered (gdb_stdlog
, " push");
4384 val
= value_contents (arg
);
4386 /* 32-bit ABIs always start floating point arguments in an
4387 even-numbered floating point register. Round the FP register
4388 up before the check to see if there are any FP registers
4389 left. Non MIPS_EABI targets also pass the FP in the integer
4390 registers so also round up normal registers. */
4391 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4393 if ((float_argreg
& 1))
4397 /* Floating point arguments passed in registers have to be
4398 treated specially. On 32-bit architectures, doubles
4399 are passed in register pairs; the even register gets
4400 the low word, and the odd register gets the high word.
4401 On non-EABI processors, the first two floating point arguments are
4402 also copied to general registers, because MIPS16 functions
4403 don't use float registers for arguments. This duplication of
4404 arguments in general registers can't hurt non-MIPS16 functions
4405 because those registers are normally skipped. */
4406 /* MIPS_EABI squeezes a struct that contains a single floating
4407 point value into an FP register instead of pushing it onto the
4409 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4410 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4412 /* EABI32 will pass doubles in consecutive registers, even on
4413 64-bit cores. At one time, we used to check the size of
4414 `float_argreg' to determine whether or not to pass doubles
4415 in consecutive registers, but this is not sufficient for
4416 making the ABI determination. */
4417 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4419 int low_offset
= gdbarch_byte_order (gdbarch
)
4420 == BFD_ENDIAN_BIG
? 4 : 0;
4423 /* Write the low word of the double to the even register(s). */
4424 regval
= extract_signed_integer (val
+ low_offset
,
4427 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4428 float_argreg
, phex (regval
, 4));
4429 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4431 /* Write the high word of the double to the odd register(s). */
4432 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4435 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4436 float_argreg
, phex (regval
, 4));
4437 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4441 /* This is a floating point value that fits entirely
4442 in a single register. */
4443 /* On 32 bit ABI's the float_argreg is further adjusted
4444 above to ensure that it is even register aligned. */
4445 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4447 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4448 float_argreg
, phex (regval
, len
));
4449 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4454 /* Copy the argument to general registers or the stack in
4455 register-sized pieces. Large arguments are split between
4456 registers and stack. */
4457 /* Note: structs whose size is not a multiple of regsize
4458 are treated specially: Irix cc passes
4459 them in registers where gcc sometimes puts them on the
4460 stack. For maximum compatibility, we will put them in
4462 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4464 /* Note: Floating-point values that didn't fit into an FP
4465 register are only written to memory. */
4468 /* Remember if the argument was written to the stack. */
4469 int stack_used_p
= 0;
4470 int partial_len
= (len
< regsize
? len
: regsize
);
4473 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4476 /* Write this portion of the argument to the stack. */
4477 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4479 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4481 /* Should shorter than int integer values be
4482 promoted to int before being stored? */
4483 int longword_offset
= 0;
4486 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4489 && (typecode
== TYPE_CODE_INT
4490 || typecode
== TYPE_CODE_PTR
4491 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4492 longword_offset
= regsize
- len
;
4493 else if ((typecode
== TYPE_CODE_STRUCT
4494 || typecode
== TYPE_CODE_UNION
)
4495 && TYPE_LENGTH (arg_type
) < regsize
)
4496 longword_offset
= regsize
- len
;
4501 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4502 paddress (gdbarch
, stack_offset
));
4503 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4504 paddress (gdbarch
, longword_offset
));
4507 addr
= sp
+ stack_offset
+ longword_offset
;
4512 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4513 paddress (gdbarch
, addr
));
4514 for (i
= 0; i
< partial_len
; i
++)
4516 fprintf_unfiltered (gdb_stdlog
, "%02x",
4520 write_memory (addr
, val
, partial_len
);
4523 /* Note!!! This is NOT an else clause. Odd sized
4524 structs may go thru BOTH paths. Floating point
4525 arguments will not. */
4526 /* Write this portion of the argument to a general
4527 purpose register. */
4528 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4529 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4532 extract_signed_integer (val
, partial_len
, byte_order
);
4535 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4537 phex (regval
, regsize
));
4538 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4545 /* Compute the offset into the stack at which we will
4546 copy the next parameter.
4548 In the new EABI (and the NABI32), the stack_offset
4549 only needs to be adjusted when it has been used. */
4552 stack_offset
+= align_up (partial_len
, regsize
);
4556 fprintf_unfiltered (gdb_stdlog
, "\n");
4559 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4561 /* Return adjusted stack pointer. */
4565 /* Determine the return value convention being used. */
4567 static enum return_value_convention
4568 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4569 struct type
*type
, struct regcache
*regcache
,
4570 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4572 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4573 int fp_return_type
= 0;
4574 int offset
, regnum
, xfer
;
4576 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4577 return RETURN_VALUE_STRUCT_CONVENTION
;
4579 /* Floating point type? */
4580 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4582 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4584 /* Structs with a single field of float type
4585 are returned in a floating point register. */
4586 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4587 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4588 && TYPE_NFIELDS (type
) == 1)
4590 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4592 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4599 /* A floating-point value belongs in the least significant part
4602 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4603 regnum
= mips_regnum (gdbarch
)->fp0
;
4607 /* An integer value goes in V0/V1. */
4609 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4610 regnum
= MIPS_V0_REGNUM
;
4613 offset
< TYPE_LENGTH (type
);
4614 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4616 xfer
= mips_abi_regsize (gdbarch
);
4617 if (offset
+ xfer
> TYPE_LENGTH (type
))
4618 xfer
= TYPE_LENGTH (type
) - offset
;
4619 mips_xfer_register (gdbarch
, regcache
,
4620 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4621 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4625 return RETURN_VALUE_REGISTER_CONVENTION
;
4629 /* N32/N64 ABI stuff. */
4631 /* Search for a naturally aligned double at OFFSET inside a struct
4632 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4636 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4641 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4644 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4647 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4650 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4653 struct type
*field_type
;
4655 /* We're only looking at normal fields. */
4656 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4657 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4660 /* If we have gone past the offset, there is no double to pass. */
4661 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4665 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4667 /* If this field is entirely before the requested offset, go
4668 on to the next one. */
4669 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4672 /* If this is our special aligned double, we can stop. */
4673 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4674 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4677 /* This field starts at or before the requested offset, and
4678 overlaps it. If it is a structure, recurse inwards. */
4679 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4686 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4687 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4688 int nargs
, struct value
**args
, CORE_ADDR sp
,
4689 int struct_return
, CORE_ADDR struct_addr
)
4695 int stack_offset
= 0;
4696 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4697 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4699 /* For shared libraries, "t9" needs to point at the function
4701 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4703 /* Set the return address register to point to the entry point of
4704 the program, where a breakpoint lies in wait. */
4705 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4707 /* First ensure that the stack and structure return address (if any)
4708 are properly aligned. The stack has to be at least 64-bit
4709 aligned even on 32-bit machines, because doubles must be 64-bit
4710 aligned. For n32 and n64, stack frames need to be 128-bit
4711 aligned, so we round to this widest known alignment. */
4713 sp
= align_down (sp
, 16);
4714 struct_addr
= align_down (struct_addr
, 16);
4716 /* Now make space on the stack for the args. */
4717 for (argnum
= 0; argnum
< nargs
; argnum
++)
4718 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4719 sp
-= align_up (len
, 16);
4722 fprintf_unfiltered (gdb_stdlog
,
4723 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4724 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4726 /* Initialize the integer and float register pointers. */
4727 argreg
= MIPS_A0_REGNUM
;
4728 float_argreg
= mips_fpa0_regnum (gdbarch
);
4730 /* The struct_return pointer occupies the first parameter-passing reg. */
4734 fprintf_unfiltered (gdb_stdlog
,
4735 "mips_n32n64_push_dummy_call: "
4736 "struct_return reg=%d %s\n",
4737 argreg
, paddress (gdbarch
, struct_addr
));
4738 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4741 /* Now load as many as possible of the first arguments into
4742 registers, and push the rest onto the stack. Loop thru args
4743 from first to last. */
4744 for (argnum
= 0; argnum
< nargs
; argnum
++)
4746 const gdb_byte
*val
;
4747 struct value
*arg
= args
[argnum
];
4748 struct type
*arg_type
= check_typedef (value_type (arg
));
4749 int len
= TYPE_LENGTH (arg_type
);
4750 enum type_code typecode
= TYPE_CODE (arg_type
);
4753 fprintf_unfiltered (gdb_stdlog
,
4754 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4755 argnum
+ 1, len
, (int) typecode
);
4757 val
= value_contents (arg
);
4759 /* A 128-bit long double value requires an even-odd pair of
4760 floating-point registers. */
4762 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4763 && (float_argreg
& 1))
4769 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4770 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4772 /* This is a floating point value that fits entirely
4773 in a single register or a pair of registers. */
4774 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4775 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4777 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4778 float_argreg
, phex (regval
, reglen
));
4779 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4782 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4783 argreg
, phex (regval
, reglen
));
4784 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4789 regval
= extract_unsigned_integer (val
+ reglen
,
4790 reglen
, byte_order
);
4792 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4793 float_argreg
, phex (regval
, reglen
));
4794 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4797 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4798 argreg
, phex (regval
, reglen
));
4799 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4806 /* Copy the argument to general registers or the stack in
4807 register-sized pieces. Large arguments are split between
4808 registers and stack. */
4809 /* For N32/N64, structs, unions, or other composite types are
4810 treated as a sequence of doublewords, and are passed in integer
4811 or floating point registers as though they were simple scalar
4812 parameters to the extent that they fit, with any excess on the
4813 stack packed according to the normal memory layout of the
4815 The caller does not reserve space for the register arguments;
4816 the callee is responsible for reserving it if required. */
4817 /* Note: Floating-point values that didn't fit into an FP
4818 register are only written to memory. */
4821 /* Remember if the argument was written to the stack. */
4822 int stack_used_p
= 0;
4823 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4826 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4829 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4830 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4832 /* Write this portion of the argument to the stack. */
4833 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4835 /* Should shorter than int integer values be
4836 promoted to int before being stored? */
4837 int longword_offset
= 0;
4840 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4842 if ((typecode
== TYPE_CODE_INT
4843 || typecode
== TYPE_CODE_PTR
)
4845 longword_offset
= MIPS64_REGSIZE
- len
;
4850 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4851 paddress (gdbarch
, stack_offset
));
4852 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4853 paddress (gdbarch
, longword_offset
));
4856 addr
= sp
+ stack_offset
+ longword_offset
;
4861 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4862 paddress (gdbarch
, addr
));
4863 for (i
= 0; i
< partial_len
; i
++)
4865 fprintf_unfiltered (gdb_stdlog
, "%02x",
4869 write_memory (addr
, val
, partial_len
);
4872 /* Note!!! This is NOT an else clause. Odd sized
4873 structs may go thru BOTH paths. */
4874 /* Write this portion of the argument to a general
4875 purpose register. */
4876 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4880 /* Sign extend pointers, 32-bit integers and signed
4881 16-bit and 8-bit integers; everything else is taken
4884 if ((partial_len
== 4
4885 && (typecode
== TYPE_CODE_PTR
4886 || typecode
== TYPE_CODE_INT
))
4888 && typecode
== TYPE_CODE_INT
4889 && !TYPE_UNSIGNED (arg_type
)))
4890 regval
= extract_signed_integer (val
, partial_len
,
4893 regval
= extract_unsigned_integer (val
, partial_len
,
4896 /* A non-floating-point argument being passed in a
4897 general register. If a struct or union, and if
4898 the remaining length is smaller than the register
4899 size, we have to adjust the register value on
4902 It does not seem to be necessary to do the
4903 same for integral types. */
4905 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4906 && partial_len
< MIPS64_REGSIZE
4907 && (typecode
== TYPE_CODE_STRUCT
4908 || typecode
== TYPE_CODE_UNION
))
4909 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4913 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4915 phex (regval
, MIPS64_REGSIZE
));
4916 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4918 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
4919 TYPE_LENGTH (arg_type
) - len
))
4922 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
4924 phex (regval
, MIPS64_REGSIZE
));
4925 regcache_cooked_write_unsigned (regcache
, float_argreg
,
4936 /* Compute the offset into the stack at which we will
4937 copy the next parameter.
4939 In N32 (N64?), the stack_offset only needs to be
4940 adjusted when it has been used. */
4943 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4947 fprintf_unfiltered (gdb_stdlog
, "\n");
4950 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4952 /* Return adjusted stack pointer. */
4956 static enum return_value_convention
4957 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4958 struct type
*type
, struct regcache
*regcache
,
4959 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4963 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4965 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4966 if needed), as appropriate for the type. Composite results (struct,
4967 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4970 * A struct with only one or two floating point fields is returned in $f0
4971 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4974 * Any other composite results of at most 128 bits are returned in
4975 $2 (first 64 bits) and $3 (remainder, if necessary).
4977 * Larger composite results are handled by converting the function to a
4978 procedure with an implicit first parameter, which is a pointer to an area
4979 reserved by the caller to receive the result. [The o32-bit ABI requires
4980 that all composite results be handled by conversion to implicit first
4981 parameters. The MIPS/SGI Fortran implementation has always made a
4982 specific exception to return COMPLEX results in the floating point
4985 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
4986 return RETURN_VALUE_STRUCT_CONVENTION
;
4987 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4988 && TYPE_LENGTH (type
) == 16
4989 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4991 /* A 128-bit floating-point value fills both $f0 and $f2. The
4992 two registers are used in the same as memory order, so the
4993 eight bytes with the lower memory address are in $f0. */
4995 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
4996 mips_xfer_register (gdbarch
, regcache
,
4997 (gdbarch_num_regs (gdbarch
)
4998 + mips_regnum (gdbarch
)->fp0
),
4999 8, gdbarch_byte_order (gdbarch
),
5000 readbuf
, writebuf
, 0);
5001 mips_xfer_register (gdbarch
, regcache
,
5002 (gdbarch_num_regs (gdbarch
)
5003 + mips_regnum (gdbarch
)->fp0
+ 2),
5004 8, gdbarch_byte_order (gdbarch
),
5005 readbuf
? readbuf
+ 8 : readbuf
,
5006 writebuf
? writebuf
+ 8 : writebuf
, 0);
5007 return RETURN_VALUE_REGISTER_CONVENTION
;
5009 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5010 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5012 /* A single or double floating-point value that fits in FP0. */
5014 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5015 mips_xfer_register (gdbarch
, regcache
,
5016 (gdbarch_num_regs (gdbarch
)
5017 + mips_regnum (gdbarch
)->fp0
),
5019 gdbarch_byte_order (gdbarch
),
5020 readbuf
, writebuf
, 0);
5021 return RETURN_VALUE_REGISTER_CONVENTION
;
5023 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5024 && TYPE_NFIELDS (type
) <= 2
5025 && TYPE_NFIELDS (type
) >= 1
5026 && ((TYPE_NFIELDS (type
) == 1
5027 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5029 || (TYPE_NFIELDS (type
) == 2
5030 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5032 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5033 == TYPE_CODE_FLT
))))
5035 /* A struct that contains one or two floats. Each value is part
5036 in the least significant part of their floating point
5037 register (or GPR, for soft float). */
5040 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5041 ? mips_regnum (gdbarch
)->fp0
5043 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5045 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5048 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5050 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5052 /* A 16-byte long double field goes in two consecutive
5054 mips_xfer_register (gdbarch
, regcache
,
5055 gdbarch_num_regs (gdbarch
) + regnum
,
5057 gdbarch_byte_order (gdbarch
),
5058 readbuf
, writebuf
, offset
);
5059 mips_xfer_register (gdbarch
, regcache
,
5060 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5062 gdbarch_byte_order (gdbarch
),
5063 readbuf
, writebuf
, offset
+ 8);
5066 mips_xfer_register (gdbarch
, regcache
,
5067 gdbarch_num_regs (gdbarch
) + regnum
,
5068 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5069 gdbarch_byte_order (gdbarch
),
5070 readbuf
, writebuf
, offset
);
5072 return RETURN_VALUE_REGISTER_CONVENTION
;
5074 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5075 || TYPE_CODE (type
) == TYPE_CODE_UNION
5076 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5078 /* A composite type. Extract the left justified value,
5079 regardless of the byte order. I.e. DO NOT USE
5083 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5084 offset
< TYPE_LENGTH (type
);
5085 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5087 int xfer
= register_size (gdbarch
, regnum
);
5088 if (offset
+ xfer
> TYPE_LENGTH (type
))
5089 xfer
= TYPE_LENGTH (type
) - offset
;
5091 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5092 offset
, xfer
, regnum
);
5093 mips_xfer_register (gdbarch
, regcache
,
5094 gdbarch_num_regs (gdbarch
) + regnum
,
5095 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5098 return RETURN_VALUE_REGISTER_CONVENTION
;
5102 /* A scalar extract each part but least-significant-byte
5106 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5107 offset
< TYPE_LENGTH (type
);
5108 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5110 int xfer
= register_size (gdbarch
, regnum
);
5111 if (offset
+ xfer
> TYPE_LENGTH (type
))
5112 xfer
= TYPE_LENGTH (type
) - offset
;
5114 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5115 offset
, xfer
, regnum
);
5116 mips_xfer_register (gdbarch
, regcache
,
5117 gdbarch_num_regs (gdbarch
) + regnum
,
5118 xfer
, gdbarch_byte_order (gdbarch
),
5119 readbuf
, writebuf
, offset
);
5121 return RETURN_VALUE_REGISTER_CONVENTION
;
5125 /* Which registers to use for passing floating-point values between
5126 function calls, one of floating-point, general and both kinds of
5127 registers. O32 and O64 use different register kinds for standard
5128 MIPS and MIPS16 code; to make the handling of cases where we may
5129 not know what kind of code is being used (e.g. no debug information)
5130 easier we sometimes use both kinds. */
5139 /* O32 ABI stuff. */
5142 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5143 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5144 int nargs
, struct value
**args
, CORE_ADDR sp
,
5145 int struct_return
, CORE_ADDR struct_addr
)
5151 int stack_offset
= 0;
5152 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5153 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5155 /* For shared libraries, "t9" needs to point at the function
5157 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5159 /* Set the return address register to point to the entry point of
5160 the program, where a breakpoint lies in wait. */
5161 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5163 /* First ensure that the stack and structure return address (if any)
5164 are properly aligned. The stack has to be at least 64-bit
5165 aligned even on 32-bit machines, because doubles must be 64-bit
5166 aligned. For n32 and n64, stack frames need to be 128-bit
5167 aligned, so we round to this widest known alignment. */
5169 sp
= align_down (sp
, 16);
5170 struct_addr
= align_down (struct_addr
, 16);
5172 /* Now make space on the stack for the args. */
5173 for (argnum
= 0; argnum
< nargs
; argnum
++)
5175 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5177 /* Align to double-word if necessary. */
5178 if (mips_type_needs_double_align (arg_type
))
5179 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5180 /* Allocate space on the stack. */
5181 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5183 sp
-= align_up (len
, 16);
5186 fprintf_unfiltered (gdb_stdlog
,
5187 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5188 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5190 /* Initialize the integer and float register pointers. */
5191 argreg
= MIPS_A0_REGNUM
;
5192 float_argreg
= mips_fpa0_regnum (gdbarch
);
5194 /* The struct_return pointer occupies the first parameter-passing reg. */
5198 fprintf_unfiltered (gdb_stdlog
,
5199 "mips_o32_push_dummy_call: "
5200 "struct_return reg=%d %s\n",
5201 argreg
, paddress (gdbarch
, struct_addr
));
5202 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5203 stack_offset
+= MIPS32_REGSIZE
;
5206 /* Now load as many as possible of the first arguments into
5207 registers, and push the rest onto the stack. Loop thru args
5208 from first to last. */
5209 for (argnum
= 0; argnum
< nargs
; argnum
++)
5211 const gdb_byte
*val
;
5212 struct value
*arg
= args
[argnum
];
5213 struct type
*arg_type
= check_typedef (value_type (arg
));
5214 int len
= TYPE_LENGTH (arg_type
);
5215 enum type_code typecode
= TYPE_CODE (arg_type
);
5218 fprintf_unfiltered (gdb_stdlog
,
5219 "mips_o32_push_dummy_call: %d len=%d type=%d",
5220 argnum
+ 1, len
, (int) typecode
);
5222 val
= value_contents (arg
);
5224 /* 32-bit ABIs always start floating point arguments in an
5225 even-numbered floating point register. Round the FP register
5226 up before the check to see if there are any FP registers
5227 left. O32 targets also pass the FP in the integer registers
5228 so also round up normal registers. */
5229 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5231 if ((float_argreg
& 1))
5235 /* Floating point arguments passed in registers have to be
5236 treated specially. On 32-bit architectures, doubles are
5237 passed in register pairs; the even FP register gets the
5238 low word, and the odd FP register gets the high word.
5239 On O32, the first two floating point arguments are also
5240 copied to general registers, following their memory order,
5241 because MIPS16 functions don't use float registers for
5242 arguments. This duplication of arguments in general
5243 registers can't hurt non-MIPS16 functions, because those
5244 registers are normally skipped. */
5246 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5247 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5249 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5251 int freg_offset
= gdbarch_byte_order (gdbarch
)
5252 == BFD_ENDIAN_BIG
? 1 : 0;
5253 unsigned long regval
;
5256 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5258 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5259 float_argreg
+ freg_offset
,
5261 regcache_cooked_write_unsigned (regcache
,
5262 float_argreg
++ + freg_offset
,
5265 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5266 argreg
, phex (regval
, 4));
5267 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5270 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5272 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5273 float_argreg
- freg_offset
,
5275 regcache_cooked_write_unsigned (regcache
,
5276 float_argreg
++ - freg_offset
,
5279 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5280 argreg
, phex (regval
, 4));
5281 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5285 /* This is a floating point value that fits entirely
5286 in a single register. */
5287 /* On 32 bit ABI's the float_argreg is further adjusted
5288 above to ensure that it is even register aligned. */
5289 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5291 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5292 float_argreg
, phex (regval
, len
));
5293 regcache_cooked_write_unsigned (regcache
,
5294 float_argreg
++, regval
);
5295 /* Although two FP registers are reserved for each
5296 argument, only one corresponding integer register is
5299 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5300 argreg
, phex (regval
, len
));
5301 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5303 /* Reserve space for the FP register. */
5304 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5308 /* Copy the argument to general registers or the stack in
5309 register-sized pieces. Large arguments are split between
5310 registers and stack. */
5311 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5312 are treated specially: Irix cc passes
5313 them in registers where gcc sometimes puts them on the
5314 stack. For maximum compatibility, we will put them in
5316 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5317 && len
% MIPS32_REGSIZE
!= 0);
5318 /* Structures should be aligned to eight bytes (even arg registers)
5319 on MIPS_ABI_O32, if their first member has double precision. */
5320 if (mips_type_needs_double_align (arg_type
))
5325 stack_offset
+= MIPS32_REGSIZE
;
5330 /* Remember if the argument was written to the stack. */
5331 int stack_used_p
= 0;
5332 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5335 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5338 /* Write this portion of the argument to the stack. */
5339 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5340 || odd_sized_struct
)
5342 /* Should shorter than int integer values be
5343 promoted to int before being stored? */
5344 int longword_offset
= 0;
5350 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5351 paddress (gdbarch
, stack_offset
));
5352 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5353 paddress (gdbarch
, longword_offset
));
5356 addr
= sp
+ stack_offset
+ longword_offset
;
5361 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5362 paddress (gdbarch
, addr
));
5363 for (i
= 0; i
< partial_len
; i
++)
5365 fprintf_unfiltered (gdb_stdlog
, "%02x",
5369 write_memory (addr
, val
, partial_len
);
5372 /* Note!!! This is NOT an else clause. Odd sized
5373 structs may go thru BOTH paths. */
5374 /* Write this portion of the argument to a general
5375 purpose register. */
5376 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5378 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5380 /* Value may need to be sign extended, because
5381 mips_isa_regsize() != mips_abi_regsize(). */
5383 /* A non-floating-point argument being passed in a
5384 general register. If a struct or union, and if
5385 the remaining length is smaller than the register
5386 size, we have to adjust the register value on
5389 It does not seem to be necessary to do the
5390 same for integral types.
5392 Also don't do this adjustment on O64 binaries.
5394 cagney/2001-07-23: gdb/179: Also, GCC, when
5395 outputting LE O32 with sizeof (struct) <
5396 mips_abi_regsize(), generates a left shift
5397 as part of storing the argument in a register
5398 (the left shift isn't generated when
5399 sizeof (struct) >= mips_abi_regsize()). Since
5400 it is quite possible that this is GCC
5401 contradicting the LE/O32 ABI, GDB has not been
5402 adjusted to accommodate this. Either someone
5403 needs to demonstrate that the LE/O32 ABI
5404 specifies such a left shift OR this new ABI gets
5405 identified as such and GDB gets tweaked
5408 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5409 && partial_len
< MIPS32_REGSIZE
5410 && (typecode
== TYPE_CODE_STRUCT
5411 || typecode
== TYPE_CODE_UNION
))
5412 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5416 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5418 phex (regval
, MIPS32_REGSIZE
));
5419 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5422 /* Prevent subsequent floating point arguments from
5423 being passed in floating point registers. */
5424 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5430 /* Compute the offset into the stack at which we will
5431 copy the next parameter.
5433 In older ABIs, the caller reserved space for
5434 registers that contained arguments. This was loosely
5435 refered to as their "home". Consequently, space is
5436 always allocated. */
5438 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5442 fprintf_unfiltered (gdb_stdlog
, "\n");
5445 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5447 /* Return adjusted stack pointer. */
5451 static enum return_value_convention
5452 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5453 struct type
*type
, struct regcache
*regcache
,
5454 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5456 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5457 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5459 enum mips_fval_reg fval_reg
;
5461 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5462 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5463 || TYPE_CODE (type
) == TYPE_CODE_UNION
5464 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5465 return RETURN_VALUE_STRUCT_CONVENTION
;
5466 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5467 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5469 /* A single-precision floating-point value. If reading in or copying,
5470 then we get it from/put it to FP0 for standard MIPS code or GPR2
5471 for MIPS16 code. If writing out only, then we put it to both FP0
5472 and GPR2. We do not support reading in with no function known, if
5473 this safety check ever triggers, then we'll have to try harder. */
5474 gdb_assert (function
|| !readbuf
);
5479 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5482 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5484 case mips_fval_both
:
5485 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5488 if (fval_reg
!= mips_fval_gpr
)
5489 mips_xfer_register (gdbarch
, regcache
,
5490 (gdbarch_num_regs (gdbarch
)
5491 + mips_regnum (gdbarch
)->fp0
),
5493 gdbarch_byte_order (gdbarch
),
5494 readbuf
, writebuf
, 0);
5495 if (fval_reg
!= mips_fval_fpr
)
5496 mips_xfer_register (gdbarch
, regcache
,
5497 gdbarch_num_regs (gdbarch
) + 2,
5499 gdbarch_byte_order (gdbarch
),
5500 readbuf
, writebuf
, 0);
5501 return RETURN_VALUE_REGISTER_CONVENTION
;
5503 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5504 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5506 /* A double-precision floating-point value. If reading in or copying,
5507 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5508 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5509 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5510 no function known, if this safety check ever triggers, then we'll
5511 have to try harder. */
5512 gdb_assert (function
|| !readbuf
);
5517 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5520 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5522 case mips_fval_both
:
5523 fprintf_unfiltered (gdb_stderr
,
5524 "Return float in $fp1/$fp0 and $2/$3\n");
5527 if (fval_reg
!= mips_fval_gpr
)
5529 /* The most significant part goes in FP1, and the least significant
5531 switch (gdbarch_byte_order (gdbarch
))
5533 case BFD_ENDIAN_LITTLE
:
5534 mips_xfer_register (gdbarch
, regcache
,
5535 (gdbarch_num_regs (gdbarch
)
5536 + mips_regnum (gdbarch
)->fp0
+ 0),
5537 4, gdbarch_byte_order (gdbarch
),
5538 readbuf
, writebuf
, 0);
5539 mips_xfer_register (gdbarch
, regcache
,
5540 (gdbarch_num_regs (gdbarch
)
5541 + mips_regnum (gdbarch
)->fp0
+ 1),
5542 4, gdbarch_byte_order (gdbarch
),
5543 readbuf
, writebuf
, 4);
5545 case BFD_ENDIAN_BIG
:
5546 mips_xfer_register (gdbarch
, regcache
,
5547 (gdbarch_num_regs (gdbarch
)
5548 + mips_regnum (gdbarch
)->fp0
+ 1),
5549 4, gdbarch_byte_order (gdbarch
),
5550 readbuf
, writebuf
, 0);
5551 mips_xfer_register (gdbarch
, regcache
,
5552 (gdbarch_num_regs (gdbarch
)
5553 + mips_regnum (gdbarch
)->fp0
+ 0),
5554 4, gdbarch_byte_order (gdbarch
),
5555 readbuf
, writebuf
, 4);
5558 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5561 if (fval_reg
!= mips_fval_fpr
)
5563 /* The two 32-bit parts are always placed in GPR2 and GPR3
5564 following these registers' memory order. */
5565 mips_xfer_register (gdbarch
, regcache
,
5566 gdbarch_num_regs (gdbarch
) + 2,
5567 4, gdbarch_byte_order (gdbarch
),
5568 readbuf
, writebuf
, 0);
5569 mips_xfer_register (gdbarch
, regcache
,
5570 gdbarch_num_regs (gdbarch
) + 3,
5571 4, gdbarch_byte_order (gdbarch
),
5572 readbuf
, writebuf
, 4);
5574 return RETURN_VALUE_REGISTER_CONVENTION
;
5577 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5578 && TYPE_NFIELDS (type
) <= 2
5579 && TYPE_NFIELDS (type
) >= 1
5580 && ((TYPE_NFIELDS (type
) == 1
5581 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5583 || (TYPE_NFIELDS (type
) == 2
5584 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5586 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5588 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5590 /* A struct that contains one or two floats. Each value is part
5591 in the least significant part of their floating point
5593 gdb_byte reg
[MAX_REGISTER_SIZE
];
5596 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5597 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5599 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5602 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5604 mips_xfer_register (gdbarch
, regcache
,
5605 gdbarch_num_regs (gdbarch
) + regnum
,
5606 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5607 gdbarch_byte_order (gdbarch
),
5608 readbuf
, writebuf
, offset
);
5610 return RETURN_VALUE_REGISTER_CONVENTION
;
5614 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5615 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5617 /* A structure or union. Extract the left justified value,
5618 regardless of the byte order. I.e. DO NOT USE
5622 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5623 offset
< TYPE_LENGTH (type
);
5624 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5626 int xfer
= register_size (gdbarch
, regnum
);
5627 if (offset
+ xfer
> TYPE_LENGTH (type
))
5628 xfer
= TYPE_LENGTH (type
) - offset
;
5630 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5631 offset
, xfer
, regnum
);
5632 mips_xfer_register (gdbarch
, regcache
,
5633 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5634 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5636 return RETURN_VALUE_REGISTER_CONVENTION
;
5641 /* A scalar extract each part but least-significant-byte
5642 justified. o32 thinks registers are 4 byte, regardless of
5646 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5647 offset
< TYPE_LENGTH (type
);
5648 offset
+= MIPS32_REGSIZE
, regnum
++)
5650 int xfer
= MIPS32_REGSIZE
;
5651 if (offset
+ xfer
> TYPE_LENGTH (type
))
5652 xfer
= TYPE_LENGTH (type
) - offset
;
5654 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5655 offset
, xfer
, regnum
);
5656 mips_xfer_register (gdbarch
, regcache
,
5657 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5658 gdbarch_byte_order (gdbarch
),
5659 readbuf
, writebuf
, offset
);
5661 return RETURN_VALUE_REGISTER_CONVENTION
;
5665 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5669 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5670 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5672 struct value
**args
, CORE_ADDR sp
,
5673 int struct_return
, CORE_ADDR struct_addr
)
5679 int stack_offset
= 0;
5680 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5681 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5683 /* For shared libraries, "t9" needs to point at the function
5685 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5687 /* Set the return address register to point to the entry point of
5688 the program, where a breakpoint lies in wait. */
5689 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5691 /* First ensure that the stack and structure return address (if any)
5692 are properly aligned. The stack has to be at least 64-bit
5693 aligned even on 32-bit machines, because doubles must be 64-bit
5694 aligned. For n32 and n64, stack frames need to be 128-bit
5695 aligned, so we round to this widest known alignment. */
5697 sp
= align_down (sp
, 16);
5698 struct_addr
= align_down (struct_addr
, 16);
5700 /* Now make space on the stack for the args. */
5701 for (argnum
= 0; argnum
< nargs
; argnum
++)
5703 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5705 /* Allocate space on the stack. */
5706 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5708 sp
-= align_up (len
, 16);
5711 fprintf_unfiltered (gdb_stdlog
,
5712 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5713 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5715 /* Initialize the integer and float register pointers. */
5716 argreg
= MIPS_A0_REGNUM
;
5717 float_argreg
= mips_fpa0_regnum (gdbarch
);
5719 /* The struct_return pointer occupies the first parameter-passing reg. */
5723 fprintf_unfiltered (gdb_stdlog
,
5724 "mips_o64_push_dummy_call: "
5725 "struct_return reg=%d %s\n",
5726 argreg
, paddress (gdbarch
, struct_addr
));
5727 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5728 stack_offset
+= MIPS64_REGSIZE
;
5731 /* Now load as many as possible of the first arguments into
5732 registers, and push the rest onto the stack. Loop thru args
5733 from first to last. */
5734 for (argnum
= 0; argnum
< nargs
; argnum
++)
5736 const gdb_byte
*val
;
5737 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5738 struct value
*arg
= args
[argnum
];
5739 struct type
*arg_type
= check_typedef (value_type (arg
));
5740 int len
= TYPE_LENGTH (arg_type
);
5741 enum type_code typecode
= TYPE_CODE (arg_type
);
5744 fprintf_unfiltered (gdb_stdlog
,
5745 "mips_o64_push_dummy_call: %d len=%d type=%d",
5746 argnum
+ 1, len
, (int) typecode
);
5748 val
= value_contents (arg
);
5750 /* Function pointer arguments to mips16 code need to be made into
5752 if (typecode
== TYPE_CODE_PTR
5753 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5755 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5757 if (!mips_pc_is_mips (addr
))
5759 store_signed_integer (valbuf
, len
, byte_order
,
5760 make_compact_addr (addr
));
5765 /* Floating point arguments passed in registers have to be
5766 treated specially. On 32-bit architectures, doubles are
5767 passed in register pairs; the even FP register gets the
5768 low word, and the odd FP register gets the high word.
5769 On O64, the first two floating point arguments are also
5770 copied to general registers, because MIPS16 functions
5771 don't use float registers for arguments. This duplication
5772 of arguments in general registers can't hurt non-MIPS16
5773 functions because those registers are normally skipped. */
5775 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5776 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5778 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5780 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5781 float_argreg
, phex (regval
, len
));
5782 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5784 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5785 argreg
, phex (regval
, len
));
5786 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5788 /* Reserve space for the FP register. */
5789 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5793 /* Copy the argument to general registers or the stack in
5794 register-sized pieces. Large arguments are split between
5795 registers and stack. */
5796 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5797 are treated specially: Irix cc passes them in registers
5798 where gcc sometimes puts them on the stack. For maximum
5799 compatibility, we will put them in both places. */
5800 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5801 && len
% MIPS64_REGSIZE
!= 0);
5804 /* Remember if the argument was written to the stack. */
5805 int stack_used_p
= 0;
5806 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5809 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5812 /* Write this portion of the argument to the stack. */
5813 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5814 || odd_sized_struct
)
5816 /* Should shorter than int integer values be
5817 promoted to int before being stored? */
5818 int longword_offset
= 0;
5821 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5823 if ((typecode
== TYPE_CODE_INT
5824 || typecode
== TYPE_CODE_PTR
5825 || typecode
== TYPE_CODE_FLT
)
5827 longword_offset
= MIPS64_REGSIZE
- len
;
5832 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5833 paddress (gdbarch
, stack_offset
));
5834 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5835 paddress (gdbarch
, longword_offset
));
5838 addr
= sp
+ stack_offset
+ longword_offset
;
5843 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5844 paddress (gdbarch
, addr
));
5845 for (i
= 0; i
< partial_len
; i
++)
5847 fprintf_unfiltered (gdb_stdlog
, "%02x",
5851 write_memory (addr
, val
, partial_len
);
5854 /* Note!!! This is NOT an else clause. Odd sized
5855 structs may go thru BOTH paths. */
5856 /* Write this portion of the argument to a general
5857 purpose register. */
5858 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5860 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5862 /* Value may need to be sign extended, because
5863 mips_isa_regsize() != mips_abi_regsize(). */
5865 /* A non-floating-point argument being passed in a
5866 general register. If a struct or union, and if
5867 the remaining length is smaller than the register
5868 size, we have to adjust the register value on
5871 It does not seem to be necessary to do the
5872 same for integral types. */
5874 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5875 && partial_len
< MIPS64_REGSIZE
5876 && (typecode
== TYPE_CODE_STRUCT
5877 || typecode
== TYPE_CODE_UNION
))
5878 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5882 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5884 phex (regval
, MIPS64_REGSIZE
));
5885 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5888 /* Prevent subsequent floating point arguments from
5889 being passed in floating point registers. */
5890 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5896 /* Compute the offset into the stack at which we will
5897 copy the next parameter.
5899 In older ABIs, the caller reserved space for
5900 registers that contained arguments. This was loosely
5901 refered to as their "home". Consequently, space is
5902 always allocated. */
5904 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5908 fprintf_unfiltered (gdb_stdlog
, "\n");
5911 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5913 /* Return adjusted stack pointer. */
5917 static enum return_value_convention
5918 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5919 struct type
*type
, struct regcache
*regcache
,
5920 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5922 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5923 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5925 enum mips_fval_reg fval_reg
;
5927 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5928 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5929 || TYPE_CODE (type
) == TYPE_CODE_UNION
5930 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5931 return RETURN_VALUE_STRUCT_CONVENTION
;
5932 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
5934 /* A floating-point value. If reading in or copying, then we get it
5935 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5936 If writing out only, then we put it to both FP0 and GPR2. We do
5937 not support reading in with no function known, if this safety
5938 check ever triggers, then we'll have to try harder. */
5939 gdb_assert (function
|| !readbuf
);
5944 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5947 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5949 case mips_fval_both
:
5950 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5953 if (fval_reg
!= mips_fval_gpr
)
5954 mips_xfer_register (gdbarch
, regcache
,
5955 (gdbarch_num_regs (gdbarch
)
5956 + mips_regnum (gdbarch
)->fp0
),
5958 gdbarch_byte_order (gdbarch
),
5959 readbuf
, writebuf
, 0);
5960 if (fval_reg
!= mips_fval_fpr
)
5961 mips_xfer_register (gdbarch
, regcache
,
5962 gdbarch_num_regs (gdbarch
) + 2,
5964 gdbarch_byte_order (gdbarch
),
5965 readbuf
, writebuf
, 0);
5966 return RETURN_VALUE_REGISTER_CONVENTION
;
5970 /* A scalar extract each part but least-significant-byte
5974 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5975 offset
< TYPE_LENGTH (type
);
5976 offset
+= MIPS64_REGSIZE
, regnum
++)
5978 int xfer
= MIPS64_REGSIZE
;
5979 if (offset
+ xfer
> TYPE_LENGTH (type
))
5980 xfer
= TYPE_LENGTH (type
) - offset
;
5982 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5983 offset
, xfer
, regnum
);
5984 mips_xfer_register (gdbarch
, regcache
,
5985 gdbarch_num_regs (gdbarch
) + regnum
,
5986 xfer
, gdbarch_byte_order (gdbarch
),
5987 readbuf
, writebuf
, offset
);
5989 return RETURN_VALUE_REGISTER_CONVENTION
;
5993 /* Floating point register management.
5995 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5996 64bit operations, these early MIPS cpus treat fp register pairs
5997 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5998 registers and offer a compatibility mode that emulates the MIPS2 fp
5999 model. When operating in MIPS2 fp compat mode, later cpu's split
6000 double precision floats into two 32-bit chunks and store them in
6001 consecutive fp regs. To display 64-bit floats stored in this
6002 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6003 Throw in user-configurable endianness and you have a real mess.
6005 The way this works is:
6006 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6007 double-precision value will be split across two logical registers.
6008 The lower-numbered logical register will hold the low-order bits,
6009 regardless of the processor's endianness.
6010 - If we are on a 64-bit processor, and we are looking for a
6011 single-precision value, it will be in the low ordered bits
6012 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6013 save slot in memory.
6014 - If we are in 64-bit mode, everything is straightforward.
6016 Note that this code only deals with "live" registers at the top of the
6017 stack. We will attempt to deal with saved registers later, when
6018 the raw/cooked register interface is in place. (We need a general
6019 interface that can deal with dynamic saved register sizes -- fp
6020 regs could be 32 bits wide in one frame and 64 on the frame above
6023 /* Copy a 32-bit single-precision value from the current frame
6024 into rare_buffer. */
6027 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6028 gdb_byte
*rare_buffer
)
6030 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6031 int raw_size
= register_size (gdbarch
, regno
);
6032 gdb_byte
*raw_buffer
= alloca (raw_size
);
6034 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6035 error (_("can't read register %d (%s)"),
6036 regno
, gdbarch_register_name (gdbarch
, regno
));
6039 /* We have a 64-bit value for this register. Find the low-order
6043 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6048 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6052 memcpy (rare_buffer
, raw_buffer
, 4);
6056 /* Copy a 64-bit double-precision value from the current frame into
6057 rare_buffer. This may include getting half of it from the next
6061 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6062 gdb_byte
*rare_buffer
)
6064 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6065 int raw_size
= register_size (gdbarch
, regno
);
6067 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6069 /* We have a 64-bit value for this register, and we should use
6071 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6072 error (_("can't read register %d (%s)"),
6073 regno
, gdbarch_register_name (gdbarch
, regno
));
6077 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6079 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6080 internal_error (__FILE__
, __LINE__
,
6081 _("mips_read_fp_register_double: bad access to "
6082 "odd-numbered FP register"));
6084 /* mips_read_fp_register_single will find the correct 32 bits from
6086 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6088 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6089 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6093 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6094 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6100 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6102 { /* Do values for FP (float) regs. */
6103 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6104 gdb_byte
*raw_buffer
;
6105 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6108 raw_buffer
= alloca (2 * register_size (gdbarch
,
6109 mips_regnum (gdbarch
)->fp0
));
6111 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6112 fprintf_filtered (file
, "%*s",
6113 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6116 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6118 struct value_print_options opts
;
6120 /* 4-byte registers: Print hex and floating. Also print even
6121 numbered registers as doubles. */
6122 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6123 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6126 get_formatted_print_options (&opts
, 'x');
6127 print_scalar_formatted (raw_buffer
,
6128 builtin_type (gdbarch
)->builtin_uint32
,
6131 fprintf_filtered (file
, " flt: ");
6133 fprintf_filtered (file
, " <invalid float> ");
6135 fprintf_filtered (file
, "%-17.9g", flt1
);
6137 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6139 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6140 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6143 fprintf_filtered (file
, " dbl: ");
6145 fprintf_filtered (file
, "<invalid double>");
6147 fprintf_filtered (file
, "%-24.17g", doub
);
6152 struct value_print_options opts
;
6154 /* Eight byte registers: print each one as hex, float and double. */
6155 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6156 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6159 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6160 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6163 get_formatted_print_options (&opts
, 'x');
6164 print_scalar_formatted (raw_buffer
,
6165 builtin_type (gdbarch
)->builtin_uint64
,
6168 fprintf_filtered (file
, " flt: ");
6170 fprintf_filtered (file
, "<invalid float>");
6172 fprintf_filtered (file
, "%-17.9g", flt1
);
6174 fprintf_filtered (file
, " dbl: ");
6176 fprintf_filtered (file
, "<invalid double>");
6178 fprintf_filtered (file
, "%-24.17g", doub
);
6183 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6186 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6187 struct value_print_options opts
;
6190 if (mips_float_register_p (gdbarch
, regnum
))
6192 mips_print_fp_register (file
, frame
, regnum
);
6196 val
= get_frame_register_value (frame
, regnum
);
6197 if (value_optimized_out (val
))
6199 fprintf_filtered (file
, "%s: [Invalid]",
6200 gdbarch_register_name (gdbarch
, regnum
));
6204 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6206 /* The problem with printing numeric register names (r26, etc.) is that
6207 the user can't use them on input. Probably the best solution is to
6208 fix it so that either the numeric or the funky (a2, etc.) names
6209 are accepted on input. */
6210 if (regnum
< MIPS_NUMREGS
)
6211 fprintf_filtered (file
, "(r%d): ", regnum
);
6213 fprintf_filtered (file
, ": ");
6215 get_formatted_print_options (&opts
, 'x');
6216 val_print_scalar_formatted (value_type (val
),
6217 value_contents_for_printing (val
),
6218 value_embedded_offset (val
),
6223 /* Replacement for generic do_registers_info.
6224 Print regs in pretty columns. */
6227 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6230 fprintf_filtered (file
, " ");
6231 mips_print_fp_register (file
, frame
, regnum
);
6232 fprintf_filtered (file
, "\n");
6237 /* Print a row's worth of GP (int) registers, with name labels above. */
6240 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6244 /* Do values for GP (int) regs. */
6245 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6246 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6251 /* For GP registers, we print a separate row of names above the vals. */
6252 for (col
= 0, regnum
= start_regnum
;
6253 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6254 + gdbarch_num_pseudo_regs (gdbarch
);
6257 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6258 continue; /* unused register */
6259 if (mips_float_register_p (gdbarch
, regnum
))
6260 break; /* End the row: reached FP register. */
6261 /* Large registers are handled separately. */
6262 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6265 break; /* End the row before this register. */
6267 /* Print this register on a row by itself. */
6268 mips_print_register (file
, frame
, regnum
);
6269 fprintf_filtered (file
, "\n");
6273 fprintf_filtered (file
, " ");
6274 fprintf_filtered (file
,
6275 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6276 gdbarch_register_name (gdbarch
, regnum
));
6283 /* Print the R0 to R31 names. */
6284 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6285 fprintf_filtered (file
, "\n R%-4d",
6286 start_regnum
% gdbarch_num_regs (gdbarch
));
6288 fprintf_filtered (file
, "\n ");
6290 /* Now print the values in hex, 4 or 8 to the row. */
6291 for (col
= 0, regnum
= start_regnum
;
6292 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6293 + gdbarch_num_pseudo_regs (gdbarch
);
6296 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6297 continue; /* unused register */
6298 if (mips_float_register_p (gdbarch
, regnum
))
6299 break; /* End row: reached FP register. */
6300 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6301 break; /* End row: large register. */
6303 /* OK: get the data in raw format. */
6304 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6305 error (_("can't read register %d (%s)"),
6306 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6307 /* pad small registers */
6309 byte
< (mips_abi_regsize (gdbarch
)
6310 - register_size (gdbarch
, regnum
)); byte
++)
6311 printf_filtered (" ");
6312 /* Now print the register value in hex, endian order. */
6313 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6315 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6316 byte
< register_size (gdbarch
, regnum
); byte
++)
6317 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6319 for (byte
= register_size (gdbarch
, regnum
) - 1;
6321 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6322 fprintf_filtered (file
, " ");
6325 if (col
> 0) /* ie. if we actually printed anything... */
6326 fprintf_filtered (file
, "\n");
6331 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6334 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6335 struct frame_info
*frame
, int regnum
, int all
)
6337 if (regnum
!= -1) /* Do one specified register. */
6339 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6340 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6341 error (_("Not a valid register for the current processor type"));
6343 mips_print_register (file
, frame
, regnum
);
6344 fprintf_filtered (file
, "\n");
6347 /* Do all (or most) registers. */
6349 regnum
= gdbarch_num_regs (gdbarch
);
6350 while (regnum
< gdbarch_num_regs (gdbarch
)
6351 + gdbarch_num_pseudo_regs (gdbarch
))
6353 if (mips_float_register_p (gdbarch
, regnum
))
6355 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6356 regnum
= print_fp_register_row (file
, frame
, regnum
);
6358 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6361 regnum
= print_gp_register_row (file
, frame
, regnum
);
6367 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6368 struct frame_info
*frame
)
6370 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6371 CORE_ADDR pc
= get_frame_pc (frame
);
6372 struct address_space
*aspace
;
6378 if ((mips_pc_is_mips (pc
)
6379 && !mips32_instruction_has_delay_slot (gdbarch
, pc
))
6380 || (mips_pc_is_micromips (gdbarch
, pc
)
6381 && !micromips_instruction_has_delay_slot (gdbarch
, pc
, 0))
6382 || (mips_pc_is_mips16 (gdbarch
, pc
)
6383 && !mips16_instruction_has_delay_slot (gdbarch
, pc
, 0)))
6386 isa
= mips_pc_isa (gdbarch
, pc
);
6387 /* _has_delay_slot above will have validated the read. */
6388 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6389 size
= mips_insn_size (isa
, insn
);
6390 aspace
= get_frame_address_space (frame
);
6391 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6394 /* To skip prologues, I use this predicate. Returns either PC itself
6395 if the code at PC does not look like a function prologue; otherwise
6396 returns an address that (if we're lucky) follows the prologue. If
6397 LENIENT, then we must skip everything which is involved in setting
6398 up the frame (it's OK to skip more, just so long as we don't skip
6399 anything which might clobber the registers which are being saved.
6400 We must skip more in the case where part of the prologue is in the
6401 delay slot of a non-prologue instruction). */
6404 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6407 CORE_ADDR func_addr
;
6409 /* See if we can determine the end of the prologue via the symbol table.
6410 If so, then return either PC, or the PC after the prologue, whichever
6412 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6414 CORE_ADDR post_prologue_pc
6415 = skip_prologue_using_sal (gdbarch
, func_addr
);
6416 if (post_prologue_pc
!= 0)
6417 return max (pc
, post_prologue_pc
);
6420 /* Can't determine prologue from the symbol table, need to examine
6423 /* Find an upper limit on the function prologue using the debug
6424 information. If the debug information could not be used to provide
6425 that bound, then use an arbitrary large number as the upper bound. */
6426 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6428 limit_pc
= pc
+ 100; /* Magic. */
6430 if (mips_pc_is_mips16 (gdbarch
, pc
))
6431 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6432 else if (mips_pc_is_micromips (gdbarch
, pc
))
6433 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6435 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6438 /* Check whether the PC is in a function epilogue (32-bit version).
6439 This is a helper function for mips_in_function_epilogue_p. */
6441 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6443 CORE_ADDR func_addr
= 0, func_end
= 0;
6445 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6447 /* The MIPS epilogue is max. 12 bytes long. */
6448 CORE_ADDR addr
= func_end
- 12;
6450 if (addr
< func_addr
+ 4)
6451 addr
= func_addr
+ 4;
6455 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6457 unsigned long high_word
;
6460 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6461 high_word
= (inst
>> 16) & 0xffff;
6463 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6464 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6465 && inst
!= 0x03e00008 /* jr $ra */
6466 && inst
!= 0x00000000) /* nop */
6476 /* Check whether the PC is in a function epilogue (microMIPS version).
6477 This is a helper function for mips_in_function_epilogue_p. */
6480 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6482 CORE_ADDR func_addr
= 0;
6483 CORE_ADDR func_end
= 0;
6491 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6494 /* The microMIPS epilogue is max. 12 bytes long. */
6495 addr
= func_end
- 12;
6497 if (addr
< func_addr
+ 2)
6498 addr
= func_addr
+ 2;
6502 for (; pc
< func_end
; pc
+= loc
)
6505 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6506 loc
+= MIPS_INSN16_SIZE
;
6507 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6509 /* 48-bit instructions. */
6510 case 3 * MIPS_INSN16_SIZE
:
6511 /* No epilogue instructions in this category. */
6514 /* 32-bit instructions. */
6515 case 2 * MIPS_INSN16_SIZE
:
6517 insn
|= mips_fetch_instruction (gdbarch
,
6518 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6519 loc
+= MIPS_INSN16_SIZE
;
6520 switch (micromips_op (insn
>> 16))
6522 case 0xc: /* ADDIU: bits 001100 */
6523 case 0x17: /* DADDIU: bits 010111 */
6524 sreg
= b0s5_reg (insn
>> 16);
6525 dreg
= b5s5_reg (insn
>> 16);
6526 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6527 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6528 /* (D)ADDIU $sp, imm */
6538 /* 16-bit instructions. */
6539 case MIPS_INSN16_SIZE
:
6540 switch (micromips_op (insn
))
6542 case 0x3: /* MOVE: bits 000011 */
6543 sreg
= b0s5_reg (insn
);
6544 dreg
= b5s5_reg (insn
);
6545 if (sreg
== 0 && dreg
== 0)
6546 /* MOVE $zero, $zero aka NOP */
6550 case 0x11: /* POOL16C: bits 010001 */
6551 if (b5s5_op (insn
) == 0x18
6552 /* JRADDIUSP: bits 010011 11000 */
6553 || (b5s5_op (insn
) == 0xd
6554 /* JRC: bits 010011 01101 */
6555 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6560 case 0x13: /* POOL16D: bits 010011 */
6561 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6562 if ((insn
& 0x1) == 0x1
6563 /* ADDIUSP: bits 010011 1 */
6577 /* Check whether the PC is in a function epilogue (16-bit version).
6578 This is a helper function for mips_in_function_epilogue_p. */
6580 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6582 CORE_ADDR func_addr
= 0, func_end
= 0;
6584 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6586 /* The MIPS epilogue is max. 12 bytes long. */
6587 CORE_ADDR addr
= func_end
- 12;
6589 if (addr
< func_addr
+ 4)
6590 addr
= func_addr
+ 4;
6594 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6596 unsigned short inst
;
6598 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6600 if ((inst
& 0xf800) == 0xf000) /* extend */
6603 if (inst
!= 0x6300 /* addiu $sp,offset */
6604 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6605 && inst
!= 0xe820 /* jr $ra */
6606 && inst
!= 0xe8a0 /* jrc $ra */
6607 && inst
!= 0x6500) /* nop */
6617 /* The epilogue is defined here as the area at the end of a function,
6618 after an instruction which destroys the function's stack frame. */
6620 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6622 if (mips_pc_is_mips16 (gdbarch
, pc
))
6623 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6624 else if (mips_pc_is_micromips (gdbarch
, pc
))
6625 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6627 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6630 /* Root of all "set mips "/"show mips " commands. This will eventually be
6631 used for all MIPS-specific commands. */
6634 show_mips_command (char *args
, int from_tty
)
6636 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6640 set_mips_command (char *args
, int from_tty
)
6643 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6644 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6647 /* Commands to show/set the MIPS FPU type. */
6650 show_mipsfpu_command (char *args
, int from_tty
)
6654 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6657 ("The MIPS floating-point coprocessor is unknown "
6658 "because the current architecture is not MIPS.\n");
6662 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6664 case MIPS_FPU_SINGLE
:
6665 fpu
= "single-precision";
6667 case MIPS_FPU_DOUBLE
:
6668 fpu
= "double-precision";
6671 fpu
= "absent (none)";
6674 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6676 if (mips_fpu_type_auto
)
6677 printf_unfiltered ("The MIPS floating-point coprocessor "
6678 "is set automatically (currently %s)\n",
6682 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6687 set_mipsfpu_command (char *args
, int from_tty
)
6689 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6690 "\"single\",\"none\" or \"auto\".\n");
6691 show_mipsfpu_command (args
, from_tty
);
6695 set_mipsfpu_single_command (char *args
, int from_tty
)
6697 struct gdbarch_info info
;
6698 gdbarch_info_init (&info
);
6699 mips_fpu_type
= MIPS_FPU_SINGLE
;
6700 mips_fpu_type_auto
= 0;
6701 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6702 instead of relying on globals. Doing that would let generic code
6703 handle the search for this specific architecture. */
6704 if (!gdbarch_update_p (info
))
6705 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6709 set_mipsfpu_double_command (char *args
, int from_tty
)
6711 struct gdbarch_info info
;
6712 gdbarch_info_init (&info
);
6713 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6714 mips_fpu_type_auto
= 0;
6715 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6716 instead of relying on globals. Doing that would let generic code
6717 handle the search for this specific architecture. */
6718 if (!gdbarch_update_p (info
))
6719 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6723 set_mipsfpu_none_command (char *args
, int from_tty
)
6725 struct gdbarch_info info
;
6726 gdbarch_info_init (&info
);
6727 mips_fpu_type
= MIPS_FPU_NONE
;
6728 mips_fpu_type_auto
= 0;
6729 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6730 instead of relying on globals. Doing that would let generic code
6731 handle the search for this specific architecture. */
6732 if (!gdbarch_update_p (info
))
6733 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6737 set_mipsfpu_auto_command (char *args
, int from_tty
)
6739 mips_fpu_type_auto
= 1;
6742 /* Attempt to identify the particular processor model by reading the
6743 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6744 the relevant processor still exists (it dates back to '94) and
6745 secondly this is not the way to do this. The processor type should
6746 be set by forcing an architecture change. */
6749 deprecated_mips_set_processor_regs_hack (void)
6751 struct regcache
*regcache
= get_current_regcache ();
6752 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6756 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6757 if ((prid
& ~0xf) == 0x700)
6758 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6761 /* Just like reinit_frame_cache, but with the right arguments to be
6762 callable as an sfunc. */
6765 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6766 struct cmd_list_element
*c
)
6768 reinit_frame_cache ();
6772 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6774 struct gdbarch
*gdbarch
= info
->application_data
;
6776 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6777 disassembler needs to be able to locally determine the ISA, and
6778 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6780 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6781 info
->mach
= bfd_mach_mips16
;
6782 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6783 info
->mach
= bfd_mach_mips_micromips
;
6785 /* Round down the instruction address to the appropriate boundary. */
6786 memaddr
&= (info
->mach
== bfd_mach_mips16
6787 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6789 /* Set the disassembler options. */
6790 if (!info
->disassembler_options
)
6791 /* This string is not recognized explicitly by the disassembler,
6792 but it tells the disassembler to not try to guess the ABI from
6793 the bfd elf headers, such that, if the user overrides the ABI
6794 of a program linked as NewABI, the disassembly will follow the
6795 register naming conventions specified by the user. */
6796 info
->disassembler_options
= "gpr-names=32";
6798 /* Call the appropriate disassembler based on the target endian-ness. */
6799 if (info
->endian
== BFD_ENDIAN_BIG
)
6800 return print_insn_big_mips (memaddr
, info
);
6802 return print_insn_little_mips (memaddr
, info
);
6806 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6808 /* Set up the disassembler info, so that we get the right
6809 register names from libopcodes. */
6810 info
->disassembler_options
= "gpr-names=n32";
6811 info
->flavour
= bfd_target_elf_flavour
;
6813 return gdb_print_insn_mips (memaddr
, info
);
6817 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6819 /* Set up the disassembler info, so that we get the right
6820 register names from libopcodes. */
6821 info
->disassembler_options
= "gpr-names=64";
6822 info
->flavour
= bfd_target_elf_flavour
;
6824 return gdb_print_insn_mips (memaddr
, info
);
6827 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6828 program counter value to determine whether a 16- or 32-bit breakpoint
6829 should be used. It returns a pointer to a string of bytes that encode a
6830 breakpoint instruction, stores the length of the string to *lenptr, and
6831 adjusts pc (if necessary) to point to the actual memory location where
6832 the breakpoint should be inserted. */
6834 static const gdb_byte
*
6835 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6836 CORE_ADDR
*pcptr
, int *lenptr
)
6838 CORE_ADDR pc
= *pcptr
;
6840 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6842 if (mips_pc_is_mips16 (gdbarch
, pc
))
6844 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6845 *pcptr
= unmake_compact_addr (pc
);
6846 *lenptr
= sizeof (mips16_big_breakpoint
);
6847 return mips16_big_breakpoint
;
6849 else if (mips_pc_is_micromips (gdbarch
, pc
))
6851 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6852 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6857 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6859 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6860 *pcptr
= unmake_compact_addr (pc
);
6862 return (size
== 2) ? micromips16_big_breakpoint
6863 : micromips32_big_breakpoint
;
6867 /* The IDT board uses an unusual breakpoint value, and
6868 sometimes gets confused when it sees the usual MIPS
6869 breakpoint instruction. */
6870 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6871 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6872 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6873 /* Likewise, IRIX appears to expect a different breakpoint,
6874 although this is not apparent until you try to use pthreads. */
6875 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6877 *lenptr
= sizeof (big_breakpoint
);
6879 if (strcmp (target_shortname
, "mips") == 0)
6880 return idt_big_breakpoint
;
6881 else if (strcmp (target_shortname
, "ddb") == 0
6882 || strcmp (target_shortname
, "pmon") == 0
6883 || strcmp (target_shortname
, "lsi") == 0)
6884 return pmon_big_breakpoint
;
6885 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6886 return irix_big_breakpoint
;
6888 return big_breakpoint
;
6893 if (mips_pc_is_mips16 (gdbarch
, pc
))
6895 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
6896 *pcptr
= unmake_compact_addr (pc
);
6897 *lenptr
= sizeof (mips16_little_breakpoint
);
6898 return mips16_little_breakpoint
;
6900 else if (mips_pc_is_micromips (gdbarch
, pc
))
6902 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
6903 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
6908 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6910 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6911 *pcptr
= unmake_compact_addr (pc
);
6913 return (size
== 2) ? micromips16_little_breakpoint
6914 : micromips32_little_breakpoint
;
6918 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
6919 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
6920 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
6922 *lenptr
= sizeof (little_breakpoint
);
6924 if (strcmp (target_shortname
, "mips") == 0)
6925 return idt_little_breakpoint
;
6926 else if (strcmp (target_shortname
, "ddb") == 0
6927 || strcmp (target_shortname
, "pmon") == 0
6928 || strcmp (target_shortname
, "lsi") == 0)
6929 return pmon_little_breakpoint
;
6931 return little_breakpoint
;
6936 /* Determine the remote breakpoint kind suitable for the PC. The following
6939 * 2 -- 16-bit MIPS16 mode breakpoint,
6941 * 3 -- 16-bit microMIPS mode breakpoint,
6943 * 4 -- 32-bit standard MIPS mode breakpoint,
6945 * 5 -- 32-bit microMIPS mode breakpoint. */
6948 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
6951 CORE_ADDR pc
= *pcptr
;
6953 if (mips_pc_is_mips16 (gdbarch
, pc
))
6955 *pcptr
= unmake_compact_addr (pc
);
6958 else if (mips_pc_is_micromips (gdbarch
, pc
))
6964 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6965 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6966 *pcptr
= unmake_compact_addr (pc
);
6967 *kindptr
= size
| 1;
6973 /* Return non-zero if the ADDR instruction has a branch delay slot
6974 (i.e. it is a jump or branch instruction). This function is based
6975 on mips32_next_pc. */
6978 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
6986 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
6990 op
= itype_op (inst
);
6991 if ((inst
& 0xe0000000) != 0)
6993 rs
= itype_rs (inst
);
6994 rt
= itype_rt (inst
);
6995 return (is_octeon_bbit_op (op
, gdbarch
)
6996 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6997 || op
== 29 /* JALX: bits 011101 */
7000 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7001 || (rs
== 9 && (rt
& 0x2) == 0)
7002 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7003 || (rs
== 10 && (rt
& 0x2) == 0))));
7004 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7007 switch (op
& 0x07) /* extract bits 28,27,26 */
7009 case 0: /* SPECIAL */
7010 op
= rtype_funct (inst
);
7011 return (op
== 8 /* JR */
7012 || op
== 9); /* JALR */
7013 break; /* end SPECIAL */
7014 case 1: /* REGIMM */
7015 rs
= itype_rs (inst
);
7016 rt
= itype_rt (inst
); /* branch condition */
7017 return ((rt
& 0xc) == 0
7018 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7019 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7020 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7021 /* BPOSGE32, BPOSGE64: bits 1110x */
7022 break; /* end REGIMM */
7023 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7029 /* Return non-zero if the ADDR instruction, which must be a 32-bit
7030 instruction if MUSTBE32 is set or can be any instruction otherwise,
7031 has a branch delay slot (i.e. it is a non-compact jump instruction). */
7034 micromips_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
7035 CORE_ADDR addr
, int mustbe32
)
7040 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7044 if (!mustbe32
) /* 16-bit instructions. */
7045 return (micromips_op (insn
) == 0x11
7046 /* POOL16C: bits 010001 */
7047 && (b5s5_op (insn
) == 0xc
7048 /* JR16: bits 010001 01100 */
7049 || (b5s5_op (insn
) & 0x1e) == 0xe))
7050 /* JALR16, JALRS16: bits 010001 0111x */
7051 || (micromips_op (insn
) & 0x37) == 0x23
7052 /* BEQZ16, BNEZ16: bits 10x011 */
7053 || micromips_op (insn
) == 0x33;
7054 /* B16: bits 110011 */
7056 /* 32-bit instructions. */
7057 if (micromips_op (insn
) == 0x0)
7058 /* POOL32A: bits 000000 */
7061 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7064 return b0s6_op (insn
) == 0x3c
7065 /* POOL32Axf: bits 000000 ... 111100 */
7066 && (b6s10_ext (insn
) & 0x2bf) == 0x3c;
7067 /* JALR, JALR.HB: 000000 000x111100 111100 */
7068 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7071 return (micromips_op (insn
) == 0x10
7072 /* POOL32I: bits 010000 */
7073 && ((b5s5_op (insn
) & 0x1c) == 0x0
7074 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7075 || (b5s5_op (insn
) & 0x1d) == 0x4
7076 /* BLEZ, BGTZ: bits 010000 001x0 */
7077 || (b5s5_op (insn
) & 0x1d) == 0x11
7078 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7079 || ((b5s5_op (insn
) & 0x1e) == 0x14
7080 && (insn
& 0x3) == 0x0)
7081 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7082 || (b5s5_op (insn
) & 0x1e) == 0x1a
7083 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7084 || ((b5s5_op (insn
) & 0x1e) == 0x1c
7085 && (insn
& 0x3) == 0x0)
7086 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7087 || ((b5s5_op (insn
) & 0x1c) == 0x1c
7088 && (insn
& 0x3) == 0x1)))
7089 /* BC1ANY*: bits 010000 111xx xxx01 */
7090 || (micromips_op (insn
) & 0x1f) == 0x1d
7091 /* JALS, JAL: bits x11101 */
7092 || (micromips_op (insn
) & 0x37) == 0x25
7093 /* BEQ, BNE: bits 10x101 */
7094 || micromips_op (insn
) == 0x35
7095 /* J: bits 110101 */
7096 || micromips_op (insn
) == 0x3c;
7097 /* JALX: bits 111100 */
7101 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
7104 unsigned short inst
;
7107 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7112 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7113 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7116 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7117 This assumes KSSEG exists. */
7120 mips_segment_boundary (CORE_ADDR bpaddr
)
7122 CORE_ADDR mask
= CORE_ADDR_MAX
;
7125 if (sizeof (CORE_ADDR
) == 8)
7126 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7127 a compiler warning produced where CORE_ADDR is a 32-bit type even
7128 though in that case this is dead code). */
7129 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7132 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7133 segsize
= 29; /* 32-bit compatibility segment */
7135 segsize
= 62; /* xkseg */
7137 case 2: /* xkphys */
7140 default: /* xksseg (1), xkuseg/kuseg (0) */
7144 else if (bpaddr
& 0x80000000) /* kernel segment */
7147 segsize
= 31; /* user segment */
7149 return bpaddr
& mask
;
7152 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7153 it backwards if necessary. Return the address of the new location. */
7156 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7158 CORE_ADDR prev_addr
;
7160 CORE_ADDR func_addr
;
7162 /* If a breakpoint is set on the instruction in a branch delay slot,
7163 GDB gets confused. When the breakpoint is hit, the PC isn't on
7164 the instruction in the branch delay slot, the PC will point to
7165 the branch instruction. Since the PC doesn't match any known
7166 breakpoints, GDB reports a trap exception.
7168 There are two possible fixes for this problem.
7170 1) When the breakpoint gets hit, see if the BD bit is set in the
7171 Cause register (which indicates the last exception occurred in a
7172 branch delay slot). If the BD bit is set, fix the PC to point to
7173 the instruction in the branch delay slot.
7175 2) When the user sets the breakpoint, don't allow him to set the
7176 breakpoint on the instruction in the branch delay slot. Instead
7177 move the breakpoint to the branch instruction (which will have
7180 The problem with the first solution is that if the user then
7181 single-steps the processor, the branch instruction will get
7182 skipped (since GDB thinks the PC is on the instruction in the
7185 So, we'll use the second solution. To do this we need to know if
7186 the instruction we're trying to set the breakpoint on is in the
7187 branch delay slot. */
7189 boundary
= mips_segment_boundary (bpaddr
);
7191 /* Make sure we don't scan back before the beginning of the current
7192 function, since we may fetch constant data or insns that look like
7193 a jump. Of course we might do that anyway if the compiler has
7194 moved constants inline. :-( */
7195 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7196 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7197 boundary
= func_addr
;
7199 if (mips_pc_is_mips (bpaddr
))
7201 if (bpaddr
== boundary
)
7204 /* If the previous instruction has a branch delay slot, we have
7205 to move the breakpoint to the branch instruction. */
7206 prev_addr
= bpaddr
- 4;
7207 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
7212 int (*instruction_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7213 CORE_ADDR addr
, jmpaddr
;
7216 boundary
= unmake_compact_addr (boundary
);
7218 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7219 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7220 so try for that first, then try the 2 byte JALR/JR.
7221 The microMIPS ASE has a whole range of jumps and branches
7222 with delay slots, some of which take 4 bytes and some take
7223 2 bytes, so the idea is the same.
7224 FIXME: We have to assume that bpaddr is not the second half
7225 of an extended instruction. */
7226 instruction_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7227 ? micromips_instruction_has_delay_slot
7228 : mips16_instruction_has_delay_slot
);
7232 for (i
= 1; i
< 4; i
++)
7234 if (unmake_compact_addr (addr
) == boundary
)
7236 addr
-= MIPS_INSN16_SIZE
;
7237 if (i
== 1 && instruction_has_delay_slot (gdbarch
, addr
, 0))
7238 /* Looks like a JR/JALR at [target-1], but it could be
7239 the second word of a previous JAL/JALX, so record it
7240 and check back one more. */
7242 else if (i
> 1 && instruction_has_delay_slot (gdbarch
, addr
, 1))
7245 /* Looks like a JAL/JALX at [target-2], but it could also
7246 be the second word of a previous JAL/JALX, record it,
7247 and check back one more. */
7250 /* Looks like a JAL/JALX at [target-3], so any previously
7251 recorded JAL/JALX or JR/JALR must be wrong, because:
7254 -2: JAL-ext (can't be JAL/JALX)
7255 -1: bdslot (can't be JR/JALR)
7258 Of course it could be another JAL-ext which looks
7259 like a JAL, but in that case we'd have broken out
7260 of this loop at [target-2]:
7264 -2: bdslot (can't be jmp)
7271 /* Not a jump instruction: if we're at [target-1] this
7272 could be the second word of a JAL/JALX, so continue;
7273 otherwise we're done. */
7286 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7287 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7290 mips_is_stub_suffix (const char *suffix
, int zero
)
7295 return zero
&& suffix
[1] == '\0';
7297 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7302 return suffix
[1] == '\0';
7308 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7309 call stubs, one of sf, df, sc, or dc. */
7312 mips_is_stub_mode (const char *mode
)
7314 return ((mode
[0] == 's' || mode
[0] == 'd')
7315 && (mode
[1] == 'f' || mode
[1] == 'c'));
7318 /* Code at PC is a compiler-generated stub. Such a stub for a function
7319 bar might have a name like __fn_stub_bar, and might look like this:
7326 followed by (or interspersed with):
7333 addiu $25, $25, %lo(bar)
7336 ($1 may be used in old code; for robustness we accept any register)
7339 lui $28, %hi(_gp_disp)
7340 addiu $28, $28, %lo(_gp_disp)
7343 addiu $25, $25, %lo(bar)
7346 In the case of a __call_stub_bar stub, the sequence to set up
7347 arguments might look like this:
7354 followed by (or interspersed with) one of the jump sequences above.
7356 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7357 of J or JR, respectively, followed by:
7363 We are at the beginning of the stub here, and scan down and extract
7364 the target address from the jump immediate instruction or, if a jump
7365 register instruction is used, from the register referred. Return
7366 the value of PC calculated or 0 if inconclusive.
7368 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7371 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7374 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7375 int addrreg
= MIPS_ZERO_REGNUM
;
7376 CORE_ADDR start_pc
= pc
;
7377 CORE_ADDR target_pc
= 0;
7384 status
== 0 && target_pc
== 0 && i
< 20;
7385 i
++, pc
+= MIPS_INSN32_SIZE
)
7387 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7393 switch (itype_op (inst
))
7395 case 0: /* SPECIAL */
7396 switch (rtype_funct (inst
))
7400 rs
= rtype_rs (inst
);
7401 if (rs
== MIPS_GP_REGNUM
)
7402 target_pc
= gp
; /* Hmm... */
7403 else if (rs
== addrreg
)
7407 case 0x21: /* ADDU */
7408 rt
= rtype_rt (inst
);
7409 rs
= rtype_rs (inst
);
7410 rd
= rtype_rd (inst
);
7411 if (rd
== MIPS_GP_REGNUM
7412 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7413 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7421 target_pc
= jtype_target (inst
) << 2;
7422 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7426 rt
= itype_rt (inst
);
7427 rs
= itype_rs (inst
);
7430 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7431 if (rt
== MIPS_GP_REGNUM
)
7433 else if (rt
== addrreg
)
7439 rt
= itype_rt (inst
);
7440 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7441 if (rt
== MIPS_GP_REGNUM
)
7443 else if (rt
!= MIPS_ZERO_REGNUM
)
7451 rt
= itype_rt (inst
);
7452 rs
= itype_rs (inst
);
7453 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7454 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7458 memset (buf
, 0, sizeof (buf
));
7459 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7461 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7470 /* If PC is in a MIPS16 call or return stub, return the address of the
7471 target PC, which is either the callee or the caller. There are several
7472 cases which must be handled:
7474 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7475 and the target PC is in $31 ($ra).
7476 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7477 and the target PC is in $2.
7478 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7479 i.e. before the JALR instruction, this is effectively a call stub
7480 and the target PC is in $2. Otherwise this is effectively
7481 a return stub and the target PC is in $18.
7482 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7483 JAL or JALR instruction, this is effectively a call stub and the
7484 target PC is buried in the instruction stream. Otherwise this
7485 is effectively a return stub and the target PC is in $18.
7486 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7487 stub and the target PC is buried in the instruction stream.
7489 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7490 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7494 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7496 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7497 CORE_ADDR start_addr
;
7501 /* Find the starting address and name of the function containing the PC. */
7502 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7505 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7506 and the target PC is in $31 ($ra). */
7507 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7508 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7509 && mips_is_stub_mode (name
+ prefixlen
)
7510 && name
[prefixlen
+ 2] == '\0')
7511 return get_frame_register_signed
7512 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7514 /* If the PC is in __mips16_call_stub_*, this is one of the call
7515 call/return stubs. */
7516 prefixlen
= strlen (mips_str_mips16_call_stub
);
7517 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7519 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7520 and the target PC is in $2. */
7521 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7522 return get_frame_register_signed
7523 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7525 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7526 i.e. before the JALR instruction, this is effectively a call stub
7527 and the target PC is in $2. Otherwise this is effectively
7528 a return stub and the target PC is in $18. */
7529 else if (mips_is_stub_mode (name
+ prefixlen
)
7530 && name
[prefixlen
+ 2] == '_'
7531 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7533 if (pc
== start_addr
)
7534 /* This is the 'call' part of a call stub. The return
7535 address is in $2. */
7536 return get_frame_register_signed
7537 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7539 /* This is the 'return' part of a call stub. The return
7540 address is in $18. */
7541 return get_frame_register_signed
7542 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7545 return 0; /* Not a stub. */
7548 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7549 compiler-generated call or call/return stubs. */
7550 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7551 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7553 if (pc
== start_addr
)
7554 /* This is the 'call' part of a call stub. Call this helper
7555 to scan through this code for interesting instructions
7556 and determine the final PC. */
7557 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7559 /* This is the 'return' part of a call stub. The return address
7561 return get_frame_register_signed
7562 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7565 return 0; /* Not a stub. */
7568 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7569 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7572 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7574 CORE_ADDR start_addr
;
7577 /* Find the starting address of the function containing the PC. */
7578 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7581 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7582 the start, i.e. after the JALR instruction, this is effectively
7584 prefixlen
= strlen (mips_str_mips16_call_stub
);
7585 if (pc
!= start_addr
7586 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7587 && mips_is_stub_mode (name
+ prefixlen
)
7588 && name
[prefixlen
+ 2] == '_'
7589 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7592 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7593 the JAL or JALR instruction, this is effectively a return stub. */
7594 prefixlen
= strlen (mips_str_call_fp_stub
);
7595 if (pc
!= start_addr
7596 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7599 /* Consume the .pic. prefix of any PIC stub, this function must return
7600 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7601 or the call stub path will trigger in handle_inferior_event causing
7603 prefixlen
= strlen (mips_str_pic
);
7604 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7607 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7608 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7609 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7610 && mips_is_stub_mode (name
+ prefixlen
)
7611 && name
[prefixlen
+ 2] == '\0')
7614 return 0; /* Not a stub. */
7617 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7618 PC of the stub target. The stub just loads $t9 and jumps to it,
7619 so that $t9 has the correct value at function entry. */
7622 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7624 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7625 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7626 struct bound_minimal_symbol msym
;
7628 gdb_byte stub_code
[16];
7629 int32_t stub_words
[4];
7631 /* The stub for foo is named ".pic.foo", and is either two
7632 instructions inserted before foo or a three instruction sequence
7633 which jumps to foo. */
7634 msym
= lookup_minimal_symbol_by_pc (pc
);
7635 if (msym
.minsym
== NULL
7636 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7637 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7638 || strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) != 0)
7641 /* A two-instruction header. */
7642 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7645 /* A three-instruction (plus delay slot) trampoline. */
7646 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7648 if (target_read_memory (pc
, stub_code
, 16) != 0)
7650 for (i
= 0; i
< 4; i
++)
7651 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7654 /* A stub contains these instructions:
7657 addiu t9, t9, %lo(target)
7660 This works even for N64, since stubs are only generated with
7662 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7663 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7664 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7665 && stub_words
[3] == 0x00000000)
7666 return ((((stub_words
[0] & 0x0000ffff) << 16)
7667 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7670 /* Not a recognized stub. */
7675 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7677 CORE_ADDR requested_pc
= pc
;
7678 CORE_ADDR target_pc
;
7685 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7689 if (is_compact_addr (pc
))
7690 pc
= unmake_compact_addr (pc
);
7693 new_pc
= find_solib_trampoline_target (frame
, pc
);
7697 if (is_compact_addr (pc
))
7698 pc
= unmake_compact_addr (pc
);
7701 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7705 if (is_compact_addr (pc
))
7706 pc
= unmake_compact_addr (pc
);
7709 while (pc
!= target_pc
);
7711 return pc
!= requested_pc
? pc
: 0;
7714 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7715 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7718 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7721 if (num
>= 0 && num
< 32)
7723 else if (num
>= 38 && num
< 70)
7724 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7726 regnum
= mips_regnum (gdbarch
)->hi
;
7728 regnum
= mips_regnum (gdbarch
)->lo
;
7729 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7730 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7732 /* This will hopefully (eventually) provoke a warning. Should
7733 we be calling complaint() here? */
7734 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7735 return gdbarch_num_regs (gdbarch
) + regnum
;
7739 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7740 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7743 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7746 if (num
>= 0 && num
< 32)
7748 else if (num
>= 32 && num
< 64)
7749 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7751 regnum
= mips_regnum (gdbarch
)->hi
;
7753 regnum
= mips_regnum (gdbarch
)->lo
;
7754 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7755 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7757 /* This will hopefully (eventually) provoke a warning. Should we
7758 be calling complaint() here? */
7759 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7760 return gdbarch_num_regs (gdbarch
) + regnum
;
7764 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7766 /* Only makes sense to supply raw registers. */
7767 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7768 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7769 decide if it is valid. Should instead define a standard sim/gdb
7770 register numbering scheme. */
7771 if (gdbarch_register_name (gdbarch
,
7772 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7773 && gdbarch_register_name (gdbarch
,
7774 gdbarch_num_regs (gdbarch
)
7775 + regnum
)[0] != '\0')
7778 return LEGACY_SIM_REGNO_IGNORE
;
7782 /* Convert an integer into an address. Extracting the value signed
7783 guarantees a correctly sign extended address. */
7786 mips_integer_to_address (struct gdbarch
*gdbarch
,
7787 struct type
*type
, const gdb_byte
*buf
)
7789 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7790 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7793 /* Dummy virtual frame pointer method. This is no more or less accurate
7794 than most other architectures; we just need to be explicit about it,
7795 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7796 an assertion failure. */
7799 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7800 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7802 *reg
= MIPS_SP_REGNUM
;
7807 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7809 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7810 const char *name
= bfd_get_section_name (abfd
, sect
);
7812 if (*abip
!= MIPS_ABI_UNKNOWN
)
7815 if (strncmp (name
, ".mdebug.", 8) != 0)
7818 if (strcmp (name
, ".mdebug.abi32") == 0)
7819 *abip
= MIPS_ABI_O32
;
7820 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7821 *abip
= MIPS_ABI_N32
;
7822 else if (strcmp (name
, ".mdebug.abi64") == 0)
7823 *abip
= MIPS_ABI_N64
;
7824 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7825 *abip
= MIPS_ABI_O64
;
7826 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7827 *abip
= MIPS_ABI_EABI32
;
7828 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7829 *abip
= MIPS_ABI_EABI64
;
7831 warning (_("unsupported ABI %s."), name
+ 8);
7835 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7837 int *lbp
= (int *) obj
;
7838 const char *name
= bfd_get_section_name (abfd
, sect
);
7840 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7842 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7844 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7845 warning (_("unrecognized .gcc_compiled_longXX"));
7848 static enum mips_abi
7849 global_mips_abi (void)
7853 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7854 if (mips_abi_strings
[i
] == mips_abi_string
)
7855 return (enum mips_abi
) i
;
7857 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7860 /* Return the default compressed instruction set, either of MIPS16
7861 or microMIPS, selected when none could have been determined from
7862 the ELF header of the binary being executed (or no binary has been
7865 static enum mips_isa
7866 global_mips_compression (void)
7870 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
7871 if (mips_compression_strings
[i
] == mips_compression_string
)
7872 return (enum mips_isa
) i
;
7874 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
7878 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
7880 /* If the size matches the set of 32-bit or 64-bit integer registers,
7881 assume that's what we've got. */
7882 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
7883 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
7885 /* If the size matches the full set of registers GDB traditionally
7886 knows about, including floating point, for either 32-bit or
7887 64-bit, assume that's what we've got. */
7888 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
7889 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
7891 /* Otherwise we don't have a useful guess. */
7894 static struct value
*
7895 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
7897 const int *reg_p
= baton
;
7898 return value_of_register (*reg_p
, frame
);
7901 static struct gdbarch
*
7902 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7904 struct gdbarch
*gdbarch
;
7905 struct gdbarch_tdep
*tdep
;
7907 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
7909 enum mips_fpu_type fpu_type
;
7910 struct tdesc_arch_data
*tdesc_data
= NULL
;
7911 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
7912 const char **reg_names
;
7913 struct mips_regnum mips_regnum
, *regnum
;
7914 enum mips_isa mips_isa
;
7918 /* Fill in the OS dependent register numbers and names. */
7919 if (info
.osabi
== GDB_OSABI_IRIX
)
7921 mips_regnum
.fp0
= 32;
7922 mips_regnum
.pc
= 64;
7923 mips_regnum
.cause
= 65;
7924 mips_regnum
.badvaddr
= 66;
7925 mips_regnum
.hi
= 67;
7926 mips_regnum
.lo
= 68;
7927 mips_regnum
.fp_control_status
= 69;
7928 mips_regnum
.fp_implementation_revision
= 70;
7929 mips_regnum
.dspacc
= dspacc
= -1;
7930 mips_regnum
.dspctl
= dspctl
= -1;
7932 reg_names
= mips_irix_reg_names
;
7934 else if (info
.osabi
== GDB_OSABI_LINUX
)
7936 mips_regnum
.fp0
= 38;
7937 mips_regnum
.pc
= 37;
7938 mips_regnum
.cause
= 36;
7939 mips_regnum
.badvaddr
= 35;
7940 mips_regnum
.hi
= 34;
7941 mips_regnum
.lo
= 33;
7942 mips_regnum
.fp_control_status
= 70;
7943 mips_regnum
.fp_implementation_revision
= 71;
7944 mips_regnum
.dspacc
= -1;
7945 mips_regnum
.dspctl
= -1;
7949 reg_names
= mips_linux_reg_names
;
7953 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
7954 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
7955 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
7956 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
7957 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
7958 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
7959 mips_regnum
.fp_control_status
= 70;
7960 mips_regnum
.fp_implementation_revision
= 71;
7961 mips_regnum
.dspacc
= dspacc
= -1;
7962 mips_regnum
.dspctl
= dspctl
= -1;
7963 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
7964 if (info
.bfd_arch_info
!= NULL
7965 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
7966 reg_names
= mips_tx39_reg_names
;
7968 reg_names
= mips_generic_reg_names
;
7971 /* Check any target description for validity. */
7972 if (tdesc_has_registers (info
.target_desc
))
7974 static const char *const mips_gprs
[] = {
7975 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7976 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7977 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7978 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7980 static const char *const mips_fprs
[] = {
7981 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7982 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7983 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7984 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7987 const struct tdesc_feature
*feature
;
7990 feature
= tdesc_find_feature (info
.target_desc
,
7991 "org.gnu.gdb.mips.cpu");
7992 if (feature
== NULL
)
7995 tdesc_data
= tdesc_data_alloc ();
7998 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
7999 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8003 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8004 mips_regnum
.lo
, "lo");
8005 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8006 mips_regnum
.hi
, "hi");
8007 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8008 mips_regnum
.pc
, "pc");
8012 tdesc_data_cleanup (tdesc_data
);
8016 feature
= tdesc_find_feature (info
.target_desc
,
8017 "org.gnu.gdb.mips.cp0");
8018 if (feature
== NULL
)
8020 tdesc_data_cleanup (tdesc_data
);
8025 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8026 mips_regnum
.badvaddr
, "badvaddr");
8027 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8028 MIPS_PS_REGNUM
, "status");
8029 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8030 mips_regnum
.cause
, "cause");
8034 tdesc_data_cleanup (tdesc_data
);
8038 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8039 backend is not prepared for that, though. */
8040 feature
= tdesc_find_feature (info
.target_desc
,
8041 "org.gnu.gdb.mips.fpu");
8042 if (feature
== NULL
)
8044 tdesc_data_cleanup (tdesc_data
);
8049 for (i
= 0; i
< 32; i
++)
8050 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8051 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8053 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8054 mips_regnum
.fp_control_status
,
8057 &= tdesc_numbered_register (feature
, tdesc_data
,
8058 mips_regnum
.fp_implementation_revision
,
8063 tdesc_data_cleanup (tdesc_data
);
8069 feature
= tdesc_find_feature (info
.target_desc
,
8070 "org.gnu.gdb.mips.dsp");
8071 /* The DSP registers are optional; it's OK if they are absent. */
8072 if (feature
!= NULL
)
8076 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8077 dspacc
+ i
++, "hi1");
8078 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8079 dspacc
+ i
++, "lo1");
8080 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8081 dspacc
+ i
++, "hi2");
8082 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8083 dspacc
+ i
++, "lo2");
8084 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8085 dspacc
+ i
++, "hi3");
8086 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8087 dspacc
+ i
++, "lo3");
8089 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8094 tdesc_data_cleanup (tdesc_data
);
8098 mips_regnum
.dspacc
= dspacc
;
8099 mips_regnum
.dspctl
= dspctl
;
8103 /* It would be nice to detect an attempt to use a 64-bit ABI
8104 when only 32-bit registers are provided. */
8108 /* First of all, extract the elf_flags, if available. */
8109 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8110 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8111 else if (arches
!= NULL
)
8112 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8116 fprintf_unfiltered (gdb_stdlog
,
8117 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8119 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8120 switch ((elf_flags
& EF_MIPS_ABI
))
8122 case E_MIPS_ABI_O32
:
8123 found_abi
= MIPS_ABI_O32
;
8125 case E_MIPS_ABI_O64
:
8126 found_abi
= MIPS_ABI_O64
;
8128 case E_MIPS_ABI_EABI32
:
8129 found_abi
= MIPS_ABI_EABI32
;
8131 case E_MIPS_ABI_EABI64
:
8132 found_abi
= MIPS_ABI_EABI64
;
8135 if ((elf_flags
& EF_MIPS_ABI2
))
8136 found_abi
= MIPS_ABI_N32
;
8138 found_abi
= MIPS_ABI_UNKNOWN
;
8142 /* GCC creates a pseudo-section whose name describes the ABI. */
8143 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8144 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8146 /* If we have no useful BFD information, use the ABI from the last
8147 MIPS architecture (if there is one). */
8148 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8149 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8151 /* Try the architecture for any hint of the correct ABI. */
8152 if (found_abi
== MIPS_ABI_UNKNOWN
8153 && info
.bfd_arch_info
!= NULL
8154 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8156 switch (info
.bfd_arch_info
->mach
)
8158 case bfd_mach_mips3900
:
8159 found_abi
= MIPS_ABI_EABI32
;
8161 case bfd_mach_mips4100
:
8162 case bfd_mach_mips5000
:
8163 found_abi
= MIPS_ABI_EABI64
;
8165 case bfd_mach_mips8000
:
8166 case bfd_mach_mips10000
:
8167 /* On Irix, ELF64 executables use the N64 ABI. The
8168 pseudo-sections which describe the ABI aren't present
8169 on IRIX. (Even for executables created by gcc.) */
8170 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8171 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8172 found_abi
= MIPS_ABI_N64
;
8174 found_abi
= MIPS_ABI_N32
;
8179 /* Default 64-bit objects to N64 instead of O32. */
8180 if (found_abi
== MIPS_ABI_UNKNOWN
8181 && info
.abfd
!= NULL
8182 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8183 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8184 found_abi
= MIPS_ABI_N64
;
8187 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8190 /* What has the user specified from the command line? */
8191 wanted_abi
= global_mips_abi ();
8193 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8196 /* Now that we have found what the ABI for this binary would be,
8197 check whether the user is overriding it. */
8198 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8199 mips_abi
= wanted_abi
;
8200 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8201 mips_abi
= found_abi
;
8203 mips_abi
= MIPS_ABI_O32
;
8205 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8208 /* Determine the default compressed ISA. */
8209 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8210 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8211 mips_isa
= ISA_MICROMIPS
;
8212 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8213 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8214 mips_isa
= ISA_MIPS16
;
8216 mips_isa
= global_mips_compression ();
8217 mips_compression_string
= mips_compression_strings
[mips_isa
];
8219 /* Also used when doing an architecture lookup. */
8221 fprintf_unfiltered (gdb_stdlog
,
8222 "mips_gdbarch_init: "
8223 "mips64_transfers_32bit_regs_p = %d\n",
8224 mips64_transfers_32bit_regs_p
);
8226 /* Determine the MIPS FPU type. */
8229 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8230 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8231 Tag_GNU_MIPS_ABI_FP
);
8232 #endif /* HAVE_ELF */
8234 if (!mips_fpu_type_auto
)
8235 fpu_type
= mips_fpu_type
;
8236 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8238 switch (elf_fpu_type
)
8240 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8241 fpu_type
= MIPS_FPU_DOUBLE
;
8243 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8244 fpu_type
= MIPS_FPU_SINGLE
;
8246 case Val_GNU_MIPS_ABI_FP_SOFT
:
8248 /* Soft float or unknown. */
8249 fpu_type
= MIPS_FPU_NONE
;
8253 else if (info
.bfd_arch_info
!= NULL
8254 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8255 switch (info
.bfd_arch_info
->mach
)
8257 case bfd_mach_mips3900
:
8258 case bfd_mach_mips4100
:
8259 case bfd_mach_mips4111
:
8260 case bfd_mach_mips4120
:
8261 fpu_type
= MIPS_FPU_NONE
;
8263 case bfd_mach_mips4650
:
8264 fpu_type
= MIPS_FPU_SINGLE
;
8267 fpu_type
= MIPS_FPU_DOUBLE
;
8270 else if (arches
!= NULL
)
8271 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8273 fpu_type
= MIPS_FPU_DOUBLE
;
8275 fprintf_unfiltered (gdb_stdlog
,
8276 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8278 /* Check for blatant incompatibilities. */
8280 /* If we have only 32-bit registers, then we can't debug a 64-bit
8282 if (info
.target_desc
8283 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8284 && mips_abi
!= MIPS_ABI_EABI32
8285 && mips_abi
!= MIPS_ABI_O32
)
8287 if (tdesc_data
!= NULL
)
8288 tdesc_data_cleanup (tdesc_data
);
8292 /* Try to find a pre-existing architecture. */
8293 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8295 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8297 /* MIPS needs to be pedantic about which ABI and the compressed
8298 ISA variation the object is using. */
8299 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8301 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8303 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8305 /* Need to be pedantic about which register virtual size is
8307 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8308 != mips64_transfers_32bit_regs_p
)
8310 /* Be pedantic about which FPU is selected. */
8311 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8314 if (tdesc_data
!= NULL
)
8315 tdesc_data_cleanup (tdesc_data
);
8316 return arches
->gdbarch
;
8319 /* Need a new architecture. Fill in a target specific vector. */
8320 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8321 gdbarch
= gdbarch_alloc (&info
, tdep
);
8322 tdep
->elf_flags
= elf_flags
;
8323 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8324 tdep
->found_abi
= found_abi
;
8325 tdep
->mips_abi
= mips_abi
;
8326 tdep
->mips_isa
= mips_isa
;
8327 tdep
->mips_fpu_type
= fpu_type
;
8328 tdep
->register_size_valid_p
= 0;
8329 tdep
->register_size
= 0;
8331 if (info
.target_desc
)
8333 /* Some useful properties can be inferred from the target. */
8334 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8336 tdep
->register_size_valid_p
= 1;
8337 tdep
->register_size
= 4;
8339 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8341 tdep
->register_size_valid_p
= 1;
8342 tdep
->register_size
= 8;
8346 /* Initially set everything according to the default ABI/ISA. */
8347 set_gdbarch_short_bit (gdbarch
, 16);
8348 set_gdbarch_int_bit (gdbarch
, 32);
8349 set_gdbarch_float_bit (gdbarch
, 32);
8350 set_gdbarch_double_bit (gdbarch
, 64);
8351 set_gdbarch_long_double_bit (gdbarch
, 64);
8352 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8353 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8354 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8356 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8357 mips_ax_pseudo_register_collect
);
8358 set_gdbarch_ax_pseudo_register_push_stack
8359 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8361 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8362 mips_elf_make_msymbol_special
);
8364 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8365 *regnum
= mips_regnum
;
8366 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8367 set_gdbarch_num_regs (gdbarch
, num_regs
);
8368 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8369 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8370 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8371 tdep
->mips_processor_reg_names
= reg_names
;
8372 tdep
->regnum
= regnum
;
8377 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8378 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8379 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8380 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8381 tdep
->default_mask_address_p
= 0;
8382 set_gdbarch_long_bit (gdbarch
, 32);
8383 set_gdbarch_ptr_bit (gdbarch
, 32);
8384 set_gdbarch_long_long_bit (gdbarch
, 64);
8387 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8388 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8389 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8390 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8391 tdep
->default_mask_address_p
= 0;
8392 set_gdbarch_long_bit (gdbarch
, 32);
8393 set_gdbarch_ptr_bit (gdbarch
, 32);
8394 set_gdbarch_long_long_bit (gdbarch
, 64);
8396 case MIPS_ABI_EABI32
:
8397 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8398 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8399 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8400 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8401 tdep
->default_mask_address_p
= 0;
8402 set_gdbarch_long_bit (gdbarch
, 32);
8403 set_gdbarch_ptr_bit (gdbarch
, 32);
8404 set_gdbarch_long_long_bit (gdbarch
, 64);
8406 case MIPS_ABI_EABI64
:
8407 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8408 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8409 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8410 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8411 tdep
->default_mask_address_p
= 0;
8412 set_gdbarch_long_bit (gdbarch
, 64);
8413 set_gdbarch_ptr_bit (gdbarch
, 64);
8414 set_gdbarch_long_long_bit (gdbarch
, 64);
8417 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8418 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8419 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8420 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8421 tdep
->default_mask_address_p
= 0;
8422 set_gdbarch_long_bit (gdbarch
, 32);
8423 set_gdbarch_ptr_bit (gdbarch
, 32);
8424 set_gdbarch_long_long_bit (gdbarch
, 64);
8425 set_gdbarch_long_double_bit (gdbarch
, 128);
8426 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8429 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8430 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8431 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8432 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8433 tdep
->default_mask_address_p
= 0;
8434 set_gdbarch_long_bit (gdbarch
, 64);
8435 set_gdbarch_ptr_bit (gdbarch
, 64);
8436 set_gdbarch_long_long_bit (gdbarch
, 64);
8437 set_gdbarch_long_double_bit (gdbarch
, 128);
8438 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8441 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8444 /* GCC creates a pseudo-section whose name specifies the size of
8445 longs, since -mlong32 or -mlong64 may be used independent of
8446 other options. How those options affect pointer sizes is ABI and
8447 architecture dependent, so use them to override the default sizes
8448 set by the ABI. This table shows the relationship between ABI,
8449 -mlongXX, and size of pointers:
8451 ABI -mlongXX ptr bits
8452 --- -------- --------
8466 Note that for o32 and eabi32, pointers are always 32 bits
8467 regardless of any -mlongXX option. For all others, pointers and
8468 longs are the same, as set by -mlongXX or set by defaults. */
8470 if (info
.abfd
!= NULL
)
8474 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8477 set_gdbarch_long_bit (gdbarch
, long_bit
);
8481 case MIPS_ABI_EABI32
:
8486 case MIPS_ABI_EABI64
:
8487 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8490 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8495 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8496 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8499 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8500 flag in object files because to do so would make it impossible to
8501 link with libraries compiled without "-gp32". This is
8502 unnecessarily restrictive.
8504 We could solve this problem by adding "-gp32" multilibs to gcc,
8505 but to set this flag before gcc is built with such multilibs will
8506 break too many systems.''
8508 But even more unhelpfully, the default linker output target for
8509 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8510 for 64-bit programs - you need to change the ABI to change this,
8511 and not all gcc targets support that currently. Therefore using
8512 this flag to detect 32-bit mode would do the wrong thing given
8513 the current gcc - it would make GDB treat these 64-bit programs
8514 as 32-bit programs by default. */
8516 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8517 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8519 /* Add/remove bits from an address. The MIPS needs be careful to
8520 ensure that all 32 bit addresses are sign extended to 64 bits. */
8521 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8523 /* Unwind the frame. */
8524 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8525 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8526 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8528 /* Map debug register numbers onto internal register numbers. */
8529 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8530 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8531 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8532 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8533 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8534 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8536 /* MIPS version of CALL_DUMMY. */
8538 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8539 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8540 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8542 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8543 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8544 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8546 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8547 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8548 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8549 mips_remote_breakpoint_from_pc
);
8550 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8551 mips_adjust_breakpoint_address
);
8553 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8555 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8557 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8558 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8559 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8561 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8563 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8565 if (mips_abi
== MIPS_ABI_N32
)
8566 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8567 else if (mips_abi
== MIPS_ABI_N64
)
8568 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8570 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8572 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8573 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8574 need to all be folded into the target vector. Since they are
8575 being used as guards for target_stopped_by_watchpoint, why not have
8576 target_stopped_by_watchpoint return the type of watchpoint that the code
8578 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8580 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8582 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8583 to support MIPS16. This is a bad thing. Make sure not to do it
8584 if we have an OS ABI that actually supports shared libraries, since
8585 shared library support is more important. If we have an OS someday
8586 that supports both shared libraries and MIPS16, we'll have to find
8587 a better place for these.
8588 macro/2012-04-25: But that applies to return trampolines only and
8589 currently no MIPS OS ABI uses shared libraries that have them. */
8590 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8592 set_gdbarch_single_step_through_delay (gdbarch
,
8593 mips_single_step_through_delay
);
8595 /* Virtual tables. */
8596 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8598 mips_register_g_packet_guesses (gdbarch
);
8600 /* Hook in OS ABI-specific overrides, if they have been registered. */
8601 info
.tdep_info
= (void *) tdesc_data
;
8602 gdbarch_init_osabi (info
, gdbarch
);
8604 /* The hook may have adjusted num_regs, fetch the final value and
8605 set pc_regnum and sp_regnum now that it has been fixed. */
8606 num_regs
= gdbarch_num_regs (gdbarch
);
8607 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8608 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8610 /* Unwind the frame. */
8611 dwarf2_append_unwinders (gdbarch
);
8612 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8613 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8614 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8615 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8616 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8617 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8618 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8619 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8620 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8624 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8625 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8627 /* Override the normal target description methods to handle our
8628 dual real and pseudo registers. */
8629 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8630 set_gdbarch_register_reggroup_p (gdbarch
,
8631 mips_tdesc_register_reggroup_p
);
8633 num_regs
= gdbarch_num_regs (gdbarch
);
8634 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8635 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8636 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8639 /* Add ABI-specific aliases for the registers. */
8640 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8641 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8642 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8643 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8645 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8646 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8647 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8649 /* Add some other standard aliases. */
8650 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8651 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8652 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8654 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8655 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8656 value_of_mips_user_reg
,
8657 &mips_numeric_register_aliases
[i
].regnum
);
8663 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8665 struct gdbarch_info info
;
8667 /* Force the architecture to update, and (if it's a MIPS architecture)
8668 mips_gdbarch_init will take care of the rest. */
8669 gdbarch_info_init (&info
);
8670 gdbarch_update_p (info
);
8673 /* Print out which MIPS ABI is in use. */
8676 show_mips_abi (struct ui_file
*file
,
8678 struct cmd_list_element
*ignored_cmd
,
8679 const char *ignored_value
)
8681 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8684 "The MIPS ABI is unknown because the current architecture "
8688 enum mips_abi global_abi
= global_mips_abi ();
8689 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8690 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8692 if (global_abi
== MIPS_ABI_UNKNOWN
)
8695 "The MIPS ABI is set automatically (currently \"%s\").\n",
8697 else if (global_abi
== actual_abi
)
8700 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8704 /* Probably shouldn't happen... */
8705 fprintf_filtered (file
,
8706 "The (auto detected) MIPS ABI \"%s\" is in use "
8707 "even though the user setting was \"%s\".\n",
8708 actual_abi_str
, mips_abi_strings
[global_abi
]);
8713 /* Print out which MIPS compressed ISA encoding is used. */
8716 show_mips_compression (struct ui_file
*file
, int from_tty
,
8717 struct cmd_list_element
*c
, const char *value
)
8719 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8724 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8730 int ef_mips_32bitmode
;
8731 /* Determine the ISA. */
8732 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8750 /* Determine the size of a pointer. */
8751 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8752 fprintf_unfiltered (file
,
8753 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8755 fprintf_unfiltered (file
,
8756 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8758 fprintf_unfiltered (file
,
8759 "mips_dump_tdep: ef_mips_arch = %d\n",
8761 fprintf_unfiltered (file
,
8762 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8763 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8764 fprintf_unfiltered (file
,
8766 "mips_mask_address_p() %d (default %d)\n",
8767 mips_mask_address_p (tdep
),
8768 tdep
->default_mask_address_p
);
8770 fprintf_unfiltered (file
,
8771 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8772 MIPS_DEFAULT_FPU_TYPE
,
8773 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8774 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8775 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8777 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8778 MIPS_EABI (gdbarch
));
8779 fprintf_unfiltered (file
,
8780 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8781 MIPS_FPU_TYPE (gdbarch
),
8782 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8783 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8784 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8788 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8791 _initialize_mips_tdep (void)
8793 static struct cmd_list_element
*mipsfpulist
= NULL
;
8794 struct cmd_list_element
*c
;
8796 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8797 if (MIPS_ABI_LAST
+ 1
8798 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8799 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8801 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8803 mips_pdr_data
= register_objfile_data ();
8805 /* Create feature sets with the appropriate properties. The values
8806 are not important. */
8807 mips_tdesc_gp32
= allocate_target_description ();
8808 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8810 mips_tdesc_gp64
= allocate_target_description ();
8811 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8813 /* Add root prefix command for all "set mips"/"show mips" commands. */
8814 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8815 _("Various MIPS specific commands."),
8816 &setmipscmdlist
, "set mips ", 0, &setlist
);
8818 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8819 _("Various MIPS specific commands."),
8820 &showmipscmdlist
, "show mips ", 0, &showlist
);
8822 /* Allow the user to override the ABI. */
8823 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8824 &mips_abi_string
, _("\
8825 Set the MIPS ABI used by this program."), _("\
8826 Show the MIPS ABI used by this program."), _("\
8827 This option can be set to one of:\n\
8828 auto - the default ABI associated with the current binary\n\
8837 &setmipscmdlist
, &showmipscmdlist
);
8839 /* Allow the user to set the ISA to assume for compressed code if ELF
8840 file flags don't tell or there is no program file selected. This
8841 setting is updated whenever unambiguous ELF file flags are interpreted,
8842 and carried over to subsequent sessions. */
8843 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8844 &mips_compression_string
, _("\
8845 Set the compressed ISA encoding used by MIPS code."), _("\
8846 Show the compressed ISA encoding used by MIPS code."), _("\
8847 Select the compressed ISA encoding used in functions that have no symbol\n\
8848 information available. The encoding can be set to either of:\n\
8851 and is updated automatically from ELF file flags if available."),
8853 show_mips_compression
,
8854 &setmipscmdlist
, &showmipscmdlist
);
8856 /* Let the user turn off floating point and set the fence post for
8857 heuristic_proc_start. */
8859 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
8860 _("Set use of MIPS floating-point coprocessor."),
8861 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8862 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8863 _("Select single-precision MIPS floating-point coprocessor."),
8865 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8866 _("Select double-precision MIPS floating-point coprocessor."),
8868 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
8869 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
8870 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
8871 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
8872 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
8873 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
8874 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
8875 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
8876 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
8877 _("Select MIPS floating-point coprocessor automatically."),
8879 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
8880 _("Show current use of MIPS floating-point coprocessor target."),
8883 /* We really would like to have both "0" and "unlimited" work, but
8884 command.c doesn't deal with that. So make it a var_zinteger
8885 because the user can always use "999999" or some such for unlimited. */
8886 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
8887 &heuristic_fence_post
, _("\
8888 Set the distance searched for the start of a function."), _("\
8889 Show the distance searched for the start of a function."), _("\
8890 If you are debugging a stripped executable, GDB needs to search through the\n\
8891 program for the start of a function. This command sets the distance of the\n\
8892 search. The only need to set it is when debugging a stripped executable."),
8893 reinit_frame_cache_sfunc
,
8894 NULL
, /* FIXME: i18n: The distance searched for
8895 the start of a function is %s. */
8896 &setlist
, &showlist
);
8898 /* Allow the user to control whether the upper bits of 64-bit
8899 addresses should be zeroed. */
8900 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
8901 &mask_address_var
, _("\
8902 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8903 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8904 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8905 allow GDB to determine the correct value."),
8906 NULL
, show_mask_address
,
8907 &setmipscmdlist
, &showmipscmdlist
);
8909 /* Allow the user to control the size of 32 bit registers within the
8910 raw remote packet. */
8911 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
8912 &mips64_transfers_32bit_regs_p
, _("\
8913 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8915 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8917 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8918 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8919 64 bits for others. Use \"off\" to disable compatibility mode"),
8920 set_mips64_transfers_32bit_regs
,
8921 NULL
, /* FIXME: i18n: Compatibility with 64-bit
8922 MIPS target that transfers 32-bit
8923 quantities is %s. */
8924 &setlist
, &showlist
);
8926 /* Debug this files internals. */
8927 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
8929 Set mips debugging."), _("\
8930 Show mips debugging."), _("\
8931 When non-zero, mips specific debugging is enabled."),
8933 NULL
, /* FIXME: i18n: Mips debugging is
8935 &setdebuglist
, &showdebuglist
);