Replace some xmalloc-family functions with XNEW-family ones
[deliverable/binutils-gdb.git] / gdb / mips-tdep.c
1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7
8 This file is part of GDB.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "inferior.h"
26 #include "symtab.h"
27 #include "value.h"
28 #include "gdbcmd.h"
29 #include "language.h"
30 #include "gdbcore.h"
31 #include "symfile.h"
32 #include "objfiles.h"
33 #include "gdbtypes.h"
34 #include "target.h"
35 #include "arch-utils.h"
36 #include "regcache.h"
37 #include "osabi.h"
38 #include "mips-tdep.h"
39 #include "block.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
42 #include "elf/mips.h"
43 #include "elf-bfd.h"
44 #include "symcat.h"
45 #include "sim-regno.h"
46 #include "dis-asm.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
50 #include "infcall.h"
51 #include "floatformat.h"
52 #include "remote.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
56 #include "valprint.h"
57 #include "ax.h"
58
59 static const struct objfile_data *mips_pdr_data;
60
61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
62
63 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch,
64 ULONGEST inst);
65 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32);
66 static int mips16_instruction_has_delay_slot (unsigned short inst,
67 int mustbe32);
68
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
70 CORE_ADDR addr);
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
72 CORE_ADDR addr, int mustbe32);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
74 CORE_ADDR addr, int mustbe32);
75
76 static void mips_print_float_info (struct gdbarch *, struct ui_file *,
77 struct frame_info *, const char *);
78
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
82
83 /* The sizes of floating point registers. */
84
85 enum
86 {
87 MIPS_FPU_SINGLE_REGSIZE = 4,
88 MIPS_FPU_DOUBLE_REGSIZE = 8
89 };
90
91 enum
92 {
93 MIPS32_REGSIZE = 4,
94 MIPS64_REGSIZE = 8
95 };
96
97 static const char *mips_abi_string;
98
99 static const char *const mips_abi_strings[] = {
100 "auto",
101 "n32",
102 "o32",
103 "n64",
104 "o64",
105 "eabi32",
106 "eabi64",
107 NULL
108 };
109
110 /* For backwards compatibility we default to MIPS16. This flag is
111 overridden as soon as unambiguous ELF file flags tell us the
112 compressed ISA encoding used. */
113 static const char mips_compression_mips16[] = "mips16";
114 static const char mips_compression_micromips[] = "micromips";
115 static const char *const mips_compression_strings[] =
116 {
117 mips_compression_mips16,
118 mips_compression_micromips,
119 NULL
120 };
121
122 static const char *mips_compression_string = mips_compression_mips16;
123
124 /* The standard register names, and all the valid aliases for them. */
125 struct register_alias
126 {
127 const char *name;
128 int regnum;
129 };
130
131 /* Aliases for o32 and most other ABIs. */
132 const struct register_alias mips_o32_aliases[] = {
133 { "ta0", 12 },
134 { "ta1", 13 },
135 { "ta2", 14 },
136 { "ta3", 15 }
137 };
138
139 /* Aliases for n32 and n64. */
140 const struct register_alias mips_n32_n64_aliases[] = {
141 { "ta0", 8 },
142 { "ta1", 9 },
143 { "ta2", 10 },
144 { "ta3", 11 }
145 };
146
147 /* Aliases for ABI-independent registers. */
148 const struct register_alias mips_register_aliases[] = {
149 /* The architecture manuals specify these ABI-independent names for
150 the GPRs. */
151 #define R(n) { "r" #n, n }
152 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
153 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
154 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
155 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #undef R
157
158 /* k0 and k1 are sometimes called these instead (for "kernel
159 temp"). */
160 { "kt0", 26 },
161 { "kt1", 27 },
162
163 /* This is the traditional GDB name for the CP0 status register. */
164 { "sr", MIPS_PS_REGNUM },
165
166 /* This is the traditional GDB name for the CP0 BadVAddr register. */
167 { "bad", MIPS_EMBED_BADVADDR_REGNUM },
168
169 /* This is the traditional GDB name for the FCSR. */
170 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
171 };
172
173 const struct register_alias mips_numeric_register_aliases[] = {
174 #define R(n) { #n, n }
175 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
176 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
177 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
178 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
179 #undef R
180 };
181
182 #ifndef MIPS_DEFAULT_FPU_TYPE
183 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
184 #endif
185 static int mips_fpu_type_auto = 1;
186 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
187
188 static unsigned int mips_debug = 0;
189
190 /* Properties (for struct target_desc) describing the g/G packet
191 layout. */
192 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
193 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
194
195 struct target_desc *mips_tdesc_gp32;
196 struct target_desc *mips_tdesc_gp64;
197
198 const struct mips_regnum *
199 mips_regnum (struct gdbarch *gdbarch)
200 {
201 return gdbarch_tdep (gdbarch)->regnum;
202 }
203
204 static int
205 mips_fpa0_regnum (struct gdbarch *gdbarch)
206 {
207 return mips_regnum (gdbarch)->fp0 + 12;
208 }
209
210 /* Return 1 if REGNUM refers to a floating-point general register, raw
211 or cooked. Otherwise return 0. */
212
213 static int
214 mips_float_register_p (struct gdbarch *gdbarch, int regnum)
215 {
216 int rawnum = regnum % gdbarch_num_regs (gdbarch);
217
218 return (rawnum >= mips_regnum (gdbarch)->fp0
219 && rawnum < mips_regnum (gdbarch)->fp0 + 32);
220 }
221
222 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
223 == MIPS_ABI_EABI32 \
224 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
225
226 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
227 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
228
229 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
230 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
231
232 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
233
234 /* Return the MIPS ABI associated with GDBARCH. */
235 enum mips_abi
236 mips_abi (struct gdbarch *gdbarch)
237 {
238 return gdbarch_tdep (gdbarch)->mips_abi;
239 }
240
241 int
242 mips_isa_regsize (struct gdbarch *gdbarch)
243 {
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245
246 /* If we know how big the registers are, use that size. */
247 if (tdep->register_size_valid_p)
248 return tdep->register_size;
249
250 /* Fall back to the previous behavior. */
251 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
252 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
253 }
254
255 /* Return the currently configured (or set) saved register size. */
256
257 unsigned int
258 mips_abi_regsize (struct gdbarch *gdbarch)
259 {
260 switch (mips_abi (gdbarch))
261 {
262 case MIPS_ABI_EABI32:
263 case MIPS_ABI_O32:
264 return 4;
265 case MIPS_ABI_N32:
266 case MIPS_ABI_N64:
267 case MIPS_ABI_O64:
268 case MIPS_ABI_EABI64:
269 return 8;
270 case MIPS_ABI_UNKNOWN:
271 case MIPS_ABI_LAST:
272 default:
273 internal_error (__FILE__, __LINE__, _("bad switch"));
274 }
275 }
276
277 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
278 are some functions to handle addresses associated with compressed
279 code including but not limited to testing, setting, or clearing
280 bit 0 of such addresses. */
281
282 /* Return one iff compressed code is the MIPS16 instruction set. */
283
284 static int
285 is_mips16_isa (struct gdbarch *gdbarch)
286 {
287 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
288 }
289
290 /* Return one iff compressed code is the microMIPS instruction set. */
291
292 static int
293 is_micromips_isa (struct gdbarch *gdbarch)
294 {
295 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
296 }
297
298 /* Return one iff ADDR denotes compressed code. */
299
300 static int
301 is_compact_addr (CORE_ADDR addr)
302 {
303 return ((addr) & 1);
304 }
305
306 /* Return one iff ADDR denotes standard ISA code. */
307
308 static int
309 is_mips_addr (CORE_ADDR addr)
310 {
311 return !is_compact_addr (addr);
312 }
313
314 /* Return one iff ADDR denotes MIPS16 code. */
315
316 static int
317 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
318 {
319 return is_compact_addr (addr) && is_mips16_isa (gdbarch);
320 }
321
322 /* Return one iff ADDR denotes microMIPS code. */
323
324 static int
325 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
326 {
327 return is_compact_addr (addr) && is_micromips_isa (gdbarch);
328 }
329
330 /* Strip the ISA (compression) bit off from ADDR. */
331
332 static CORE_ADDR
333 unmake_compact_addr (CORE_ADDR addr)
334 {
335 return ((addr) & ~(CORE_ADDR) 1);
336 }
337
338 /* Add the ISA (compression) bit to ADDR. */
339
340 static CORE_ADDR
341 make_compact_addr (CORE_ADDR addr)
342 {
343 return ((addr) | (CORE_ADDR) 1);
344 }
345
346 /* Extern version of unmake_compact_addr; we use a separate function
347 so that unmake_compact_addr can be inlined throughout this file. */
348
349 CORE_ADDR
350 mips_unmake_compact_addr (CORE_ADDR addr)
351 {
352 return unmake_compact_addr (addr);
353 }
354
355 /* Functions for setting and testing a bit in a minimal symbol that
356 marks it as MIPS16 or microMIPS function. The MSB of the minimal
357 symbol's "info" field is used for this purpose.
358
359 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
360 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
361 one of the "special" bits in a minimal symbol to mark it accordingly.
362 The test checks an ELF-private flag that is valid for true function
363 symbols only; for synthetic symbols such as for PLT stubs that have
364 no ELF-private part at all the MIPS BFD backend arranges for this
365 information to be carried in the asymbol's udata field instead.
366
367 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
368 in a minimal symbol. */
369
370 static void
371 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
372 {
373 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
374 unsigned char st_other;
375
376 if ((sym->flags & BSF_SYNTHETIC) == 0)
377 st_other = elfsym->internal_elf_sym.st_other;
378 else if ((sym->flags & BSF_FUNCTION) != 0)
379 st_other = sym->udata.i;
380 else
381 return;
382
383 if (ELF_ST_IS_MICROMIPS (st_other))
384 {
385 MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
386 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
387 }
388 else if (ELF_ST_IS_MIPS16 (st_other))
389 {
390 MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
391 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
392 }
393 }
394
395 /* Return one iff MSYM refers to standard ISA code. */
396
397 static int
398 msymbol_is_mips (struct minimal_symbol *msym)
399 {
400 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
401 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
402 }
403
404 /* Return one iff MSYM refers to MIPS16 code. */
405
406 static int
407 msymbol_is_mips16 (struct minimal_symbol *msym)
408 {
409 return MSYMBOL_TARGET_FLAG_MIPS16 (msym);
410 }
411
412 /* Return one iff MSYM refers to microMIPS code. */
413
414 static int
415 msymbol_is_micromips (struct minimal_symbol *msym)
416 {
417 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
418 }
419
420 /* Set the ISA bit in the main symbol too, complementing the corresponding
421 minimal symbol setting and reflecting the run-time value of the symbol.
422 The need for comes from the ISA bit having been cleared as code in
423 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
424 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
425 of symbols referring to compressed code different in GDB to the values
426 used by actual code. That in turn makes them evaluate incorrectly in
427 expressions, producing results different to what the same expressions
428 yield when compiled into the program being debugged. */
429
430 static void
431 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile)
432 {
433 if (SYMBOL_CLASS (sym) == LOC_BLOCK)
434 {
435 /* We are in symbol reading so it is OK to cast away constness. */
436 struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym);
437 CORE_ADDR compact_block_start;
438 struct bound_minimal_symbol msym;
439
440 compact_block_start = BLOCK_START (block) | 1;
441 msym = lookup_minimal_symbol_by_pc (compact_block_start);
442 if (msym.minsym && !msymbol_is_mips (msym.minsym))
443 {
444 BLOCK_START (block) = compact_block_start;
445 }
446 }
447 }
448
449 /* XFER a value from the big/little/left end of the register.
450 Depending on the size of the value it might occupy the entire
451 register or just part of it. Make an allowance for this, aligning
452 things accordingly. */
453
454 static void
455 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
456 int reg_num, int length,
457 enum bfd_endian endian, gdb_byte *in,
458 const gdb_byte *out, int buf_offset)
459 {
460 int reg_offset = 0;
461
462 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
463 /* Need to transfer the left or right part of the register, based on
464 the targets byte order. */
465 switch (endian)
466 {
467 case BFD_ENDIAN_BIG:
468 reg_offset = register_size (gdbarch, reg_num) - length;
469 break;
470 case BFD_ENDIAN_LITTLE:
471 reg_offset = 0;
472 break;
473 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
474 reg_offset = 0;
475 break;
476 default:
477 internal_error (__FILE__, __LINE__, _("bad switch"));
478 }
479 if (mips_debug)
480 fprintf_unfiltered (gdb_stderr,
481 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
482 reg_num, reg_offset, buf_offset, length);
483 if (mips_debug && out != NULL)
484 {
485 int i;
486 fprintf_unfiltered (gdb_stdlog, "out ");
487 for (i = 0; i < length; i++)
488 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
489 }
490 if (in != NULL)
491 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
492 in + buf_offset);
493 if (out != NULL)
494 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
495 out + buf_offset);
496 if (mips_debug && in != NULL)
497 {
498 int i;
499 fprintf_unfiltered (gdb_stdlog, "in ");
500 for (i = 0; i < length; i++)
501 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
502 }
503 if (mips_debug)
504 fprintf_unfiltered (gdb_stdlog, "\n");
505 }
506
507 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
508 compatiblity mode. A return value of 1 means that we have
509 physical 64-bit registers, but should treat them as 32-bit registers. */
510
511 static int
512 mips2_fp_compat (struct frame_info *frame)
513 {
514 struct gdbarch *gdbarch = get_frame_arch (frame);
515 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
516 meaningful. */
517 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
518 return 0;
519
520 #if 0
521 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
522 in all the places we deal with FP registers. PR gdb/413. */
523 /* Otherwise check the FR bit in the status register - it controls
524 the FP compatiblity mode. If it is clear we are in compatibility
525 mode. */
526 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
527 return 1;
528 #endif
529
530 return 0;
531 }
532
533 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
534
535 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
536
537 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
538
539 /* The list of available "set mips " and "show mips " commands. */
540
541 static struct cmd_list_element *setmipscmdlist = NULL;
542 static struct cmd_list_element *showmipscmdlist = NULL;
543
544 /* Integer registers 0 thru 31 are handled explicitly by
545 mips_register_name(). Processor specific registers 32 and above
546 are listed in the following tables. */
547
548 enum
549 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
550
551 /* Generic MIPS. */
552
553 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
554 "sr", "lo", "hi", "bad", "cause", "pc",
555 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
556 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
557 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
558 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
559 "fsr", "fir",
560 };
561
562 /* Names of IDT R3041 registers. */
563
564 static const char *mips_r3041_reg_names[] = {
565 "sr", "lo", "hi", "bad", "cause", "pc",
566 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
567 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
568 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
569 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
570 "fsr", "fir", "", /*"fp" */ "",
571 "", "", "bus", "ccfg", "", "", "", "",
572 "", "", "port", "cmp", "", "", "epc", "prid",
573 };
574
575 /* Names of tx39 registers. */
576
577 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
578 "sr", "lo", "hi", "bad", "cause", "pc",
579 "", "", "", "", "", "", "", "",
580 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "", "", "", "", "", "",
583 "", "", "", "",
584 "", "", "", "", "", "", "", "",
585 "", "", "config", "cache", "debug", "depc", "epc",
586 };
587
588 /* Names of IRIX registers. */
589 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
590 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
591 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
592 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
593 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
594 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
595 };
596
597 /* Names of registers with Linux kernels. */
598 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
599 "sr", "lo", "hi", "bad", "cause", "pc",
600 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
601 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
602 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
603 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
604 "fsr", "fir"
605 };
606
607
608 /* Return the name of the register corresponding to REGNO. */
609 static const char *
610 mips_register_name (struct gdbarch *gdbarch, int regno)
611 {
612 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
613 /* GPR names for all ABIs other than n32/n64. */
614 static char *mips_gpr_names[] = {
615 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
616 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
617 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
618 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
619 };
620
621 /* GPR names for n32 and n64 ABIs. */
622 static char *mips_n32_n64_gpr_names[] = {
623 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
624 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
625 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
626 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
627 };
628
629 enum mips_abi abi = mips_abi (gdbarch);
630
631 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
632 but then don't make the raw register names visible. This (upper)
633 range of user visible register numbers are the pseudo-registers.
634
635 This approach was adopted accommodate the following scenario:
636 It is possible to debug a 64-bit device using a 32-bit
637 programming model. In such instances, the raw registers are
638 configured to be 64-bits wide, while the pseudo registers are
639 configured to be 32-bits wide. The registers that the user
640 sees - the pseudo registers - match the users expectations
641 given the programming model being used. */
642 int rawnum = regno % gdbarch_num_regs (gdbarch);
643 if (regno < gdbarch_num_regs (gdbarch))
644 return "";
645
646 /* The MIPS integer registers are always mapped from 0 to 31. The
647 names of the registers (which reflects the conventions regarding
648 register use) vary depending on the ABI. */
649 if (0 <= rawnum && rawnum < 32)
650 {
651 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
652 return mips_n32_n64_gpr_names[rawnum];
653 else
654 return mips_gpr_names[rawnum];
655 }
656 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
657 return tdesc_register_name (gdbarch, rawnum);
658 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
659 {
660 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
661 if (tdep->mips_processor_reg_names[rawnum - 32])
662 return tdep->mips_processor_reg_names[rawnum - 32];
663 return "";
664 }
665 else
666 internal_error (__FILE__, __LINE__,
667 _("mips_register_name: bad register number %d"), rawnum);
668 }
669
670 /* Return the groups that a MIPS register can be categorised into. */
671
672 static int
673 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
674 struct reggroup *reggroup)
675 {
676 int vector_p;
677 int float_p;
678 int raw_p;
679 int rawnum = regnum % gdbarch_num_regs (gdbarch);
680 int pseudo = regnum / gdbarch_num_regs (gdbarch);
681 if (reggroup == all_reggroup)
682 return pseudo;
683 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
684 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
685 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
686 (gdbarch), as not all architectures are multi-arch. */
687 raw_p = rawnum < gdbarch_num_regs (gdbarch);
688 if (gdbarch_register_name (gdbarch, regnum) == NULL
689 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
690 return 0;
691 if (reggroup == float_reggroup)
692 return float_p && pseudo;
693 if (reggroup == vector_reggroup)
694 return vector_p && pseudo;
695 if (reggroup == general_reggroup)
696 return (!vector_p && !float_p) && pseudo;
697 /* Save the pseudo registers. Need to make certain that any code
698 extracting register values from a saved register cache also uses
699 pseudo registers. */
700 if (reggroup == save_reggroup)
701 return raw_p && pseudo;
702 /* Restore the same pseudo register. */
703 if (reggroup == restore_reggroup)
704 return raw_p && pseudo;
705 return 0;
706 }
707
708 /* Return the groups that a MIPS register can be categorised into.
709 This version is only used if we have a target description which
710 describes real registers (and their groups). */
711
712 static int
713 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
714 struct reggroup *reggroup)
715 {
716 int rawnum = regnum % gdbarch_num_regs (gdbarch);
717 int pseudo = regnum / gdbarch_num_regs (gdbarch);
718 int ret;
719
720 /* Only save, restore, and display the pseudo registers. Need to
721 make certain that any code extracting register values from a
722 saved register cache also uses pseudo registers.
723
724 Note: saving and restoring the pseudo registers is slightly
725 strange; if we have 64 bits, we should save and restore all
726 64 bits. But this is hard and has little benefit. */
727 if (!pseudo)
728 return 0;
729
730 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
731 if (ret != -1)
732 return ret;
733
734 return mips_register_reggroup_p (gdbarch, regnum, reggroup);
735 }
736
737 /* Map the symbol table registers which live in the range [1 *
738 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
739 registers. Take care of alignment and size problems. */
740
741 static enum register_status
742 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
743 int cookednum, gdb_byte *buf)
744 {
745 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
746 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
747 && cookednum < 2 * gdbarch_num_regs (gdbarch));
748 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
749 return regcache_raw_read (regcache, rawnum, buf);
750 else if (register_size (gdbarch, rawnum) >
751 register_size (gdbarch, cookednum))
752 {
753 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
754 return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
755 else
756 {
757 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
758 LONGEST regval;
759 enum register_status status;
760
761 status = regcache_raw_read_signed (regcache, rawnum, &regval);
762 if (status == REG_VALID)
763 store_signed_integer (buf, 4, byte_order, regval);
764 return status;
765 }
766 }
767 else
768 internal_error (__FILE__, __LINE__, _("bad register size"));
769 }
770
771 static void
772 mips_pseudo_register_write (struct gdbarch *gdbarch,
773 struct regcache *regcache, int cookednum,
774 const gdb_byte *buf)
775 {
776 int rawnum = cookednum % gdbarch_num_regs (gdbarch);
777 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
778 && cookednum < 2 * gdbarch_num_regs (gdbarch));
779 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
780 regcache_raw_write (regcache, rawnum, buf);
781 else if (register_size (gdbarch, rawnum) >
782 register_size (gdbarch, cookednum))
783 {
784 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
785 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
786 else
787 {
788 /* Sign extend the shortened version of the register prior
789 to placing it in the raw register. This is required for
790 some mips64 parts in order to avoid unpredictable behavior. */
791 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
792 LONGEST regval = extract_signed_integer (buf, 4, byte_order);
793 regcache_raw_write_signed (regcache, rawnum, regval);
794 }
795 }
796 else
797 internal_error (__FILE__, __LINE__, _("bad register size"));
798 }
799
800 static int
801 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
802 struct agent_expr *ax, int reg)
803 {
804 int rawnum = reg % gdbarch_num_regs (gdbarch);
805 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
806 && reg < 2 * gdbarch_num_regs (gdbarch));
807
808 ax_reg_mask (ax, rawnum);
809
810 return 0;
811 }
812
813 static int
814 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
815 struct agent_expr *ax, int reg)
816 {
817 int rawnum = reg % gdbarch_num_regs (gdbarch);
818 gdb_assert (reg >= gdbarch_num_regs (gdbarch)
819 && reg < 2 * gdbarch_num_regs (gdbarch));
820 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
821 {
822 ax_reg (ax, rawnum);
823
824 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
825 {
826 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
827 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
828 {
829 ax_const_l (ax, 32);
830 ax_simple (ax, aop_lsh);
831 }
832 ax_const_l (ax, 32);
833 ax_simple (ax, aop_rsh_signed);
834 }
835 }
836 else
837 internal_error (__FILE__, __LINE__, _("bad register size"));
838
839 return 0;
840 }
841
842 /* Table to translate 3-bit register field to actual register number. */
843 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
844
845 /* Heuristic_proc_start may hunt through the text section for a long
846 time across a 2400 baud serial line. Allows the user to limit this
847 search. */
848
849 static int heuristic_fence_post = 0;
850
851 /* Number of bytes of storage in the actual machine representation for
852 register N. NOTE: This defines the pseudo register type so need to
853 rebuild the architecture vector. */
854
855 static int mips64_transfers_32bit_regs_p = 0;
856
857 static void
858 set_mips64_transfers_32bit_regs (char *args, int from_tty,
859 struct cmd_list_element *c)
860 {
861 struct gdbarch_info info;
862 gdbarch_info_init (&info);
863 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
864 instead of relying on globals. Doing that would let generic code
865 handle the search for this specific architecture. */
866 if (!gdbarch_update_p (info))
867 {
868 mips64_transfers_32bit_regs_p = 0;
869 error (_("32-bit compatibility mode not supported"));
870 }
871 }
872
873 /* Convert to/from a register and the corresponding memory value. */
874
875 /* This predicate tests for the case of an 8 byte floating point
876 value that is being transferred to or from a pair of floating point
877 registers each of which are (or are considered to be) only 4 bytes
878 wide. */
879 static int
880 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
881 struct type *type)
882 {
883 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
884 && register_size (gdbarch, regnum) == 4
885 && mips_float_register_p (gdbarch, regnum)
886 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
887 }
888
889 /* This predicate tests for the case of a value of less than 8
890 bytes in width that is being transfered to or from an 8 byte
891 general purpose register. */
892 static int
893 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
894 struct type *type)
895 {
896 int num_regs = gdbarch_num_regs (gdbarch);
897
898 return (register_size (gdbarch, regnum) == 8
899 && regnum % num_regs > 0 && regnum % num_regs < 32
900 && TYPE_LENGTH (type) < 8);
901 }
902
903 static int
904 mips_convert_register_p (struct gdbarch *gdbarch,
905 int regnum, struct type *type)
906 {
907 return (mips_convert_register_float_case_p (gdbarch, regnum, type)
908 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
909 }
910
911 static int
912 mips_register_to_value (struct frame_info *frame, int regnum,
913 struct type *type, gdb_byte *to,
914 int *optimizedp, int *unavailablep)
915 {
916 struct gdbarch *gdbarch = get_frame_arch (frame);
917
918 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
919 {
920 get_frame_register (frame, regnum + 0, to + 4);
921 get_frame_register (frame, regnum + 1, to + 0);
922
923 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
924 optimizedp, unavailablep))
925 return 0;
926
927 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
928 optimizedp, unavailablep))
929 return 0;
930 *optimizedp = *unavailablep = 0;
931 return 1;
932 }
933 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
934 {
935 int len = TYPE_LENGTH (type);
936 CORE_ADDR offset;
937
938 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
939 if (!get_frame_register_bytes (frame, regnum, offset, len, to,
940 optimizedp, unavailablep))
941 return 0;
942
943 *optimizedp = *unavailablep = 0;
944 return 1;
945 }
946 else
947 {
948 internal_error (__FILE__, __LINE__,
949 _("mips_register_to_value: unrecognized case"));
950 }
951 }
952
953 static void
954 mips_value_to_register (struct frame_info *frame, int regnum,
955 struct type *type, const gdb_byte *from)
956 {
957 struct gdbarch *gdbarch = get_frame_arch (frame);
958
959 if (mips_convert_register_float_case_p (gdbarch, regnum, type))
960 {
961 put_frame_register (frame, regnum + 0, from + 4);
962 put_frame_register (frame, regnum + 1, from + 0);
963 }
964 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
965 {
966 gdb_byte fill[8];
967 int len = TYPE_LENGTH (type);
968
969 /* Sign extend values, irrespective of type, that are stored to
970 a 64-bit general purpose register. (32-bit unsigned values
971 are stored as signed quantities within a 64-bit register.
972 When performing an operation, in compiled code, that combines
973 a 32-bit unsigned value with a signed 64-bit value, a type
974 conversion is first performed that zeroes out the high 32 bits.) */
975 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
976 {
977 if (from[0] & 0x80)
978 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
979 else
980 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
981 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
982 put_frame_register_bytes (frame, regnum, 8 - len, len, from);
983 }
984 else
985 {
986 if (from[len-1] & 0x80)
987 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
988 else
989 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
990 put_frame_register_bytes (frame, regnum, 0, len, from);
991 put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
992 }
993 }
994 else
995 {
996 internal_error (__FILE__, __LINE__,
997 _("mips_value_to_register: unrecognized case"));
998 }
999 }
1000
1001 /* Return the GDB type object for the "standard" data type of data in
1002 register REG. */
1003
1004 static struct type *
1005 mips_register_type (struct gdbarch *gdbarch, int regnum)
1006 {
1007 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
1008 if (mips_float_register_p (gdbarch, regnum))
1009 {
1010 /* The floating-point registers raw, or cooked, always match
1011 mips_isa_regsize(), and also map 1:1, byte for byte. */
1012 if (mips_isa_regsize (gdbarch) == 4)
1013 return builtin_type (gdbarch)->builtin_float;
1014 else
1015 return builtin_type (gdbarch)->builtin_double;
1016 }
1017 else if (regnum < gdbarch_num_regs (gdbarch))
1018 {
1019 /* The raw or ISA registers. These are all sized according to
1020 the ISA regsize. */
1021 if (mips_isa_regsize (gdbarch) == 4)
1022 return builtin_type (gdbarch)->builtin_int32;
1023 else
1024 return builtin_type (gdbarch)->builtin_int64;
1025 }
1026 else
1027 {
1028 int rawnum = regnum - gdbarch_num_regs (gdbarch);
1029
1030 /* The cooked or ABI registers. These are sized according to
1031 the ABI (with a few complications). */
1032 if (rawnum == mips_regnum (gdbarch)->fp_control_status
1033 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision)
1034 return builtin_type (gdbarch)->builtin_int32;
1035 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
1036 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1037 && rawnum >= MIPS_FIRST_EMBED_REGNUM
1038 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1039 /* The pseudo/cooked view of the embedded registers is always
1040 32-bit. The raw view is handled below. */
1041 return builtin_type (gdbarch)->builtin_int32;
1042 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
1043 /* The target, while possibly using a 64-bit register buffer,
1044 is only transfering 32-bits of each integer register.
1045 Reflect this in the cooked/pseudo (ABI) register value. */
1046 return builtin_type (gdbarch)->builtin_int32;
1047 else if (mips_abi_regsize (gdbarch) == 4)
1048 /* The ABI is restricted to 32-bit registers (the ISA could be
1049 32- or 64-bit). */
1050 return builtin_type (gdbarch)->builtin_int32;
1051 else
1052 /* 64-bit ABI. */
1053 return builtin_type (gdbarch)->builtin_int64;
1054 }
1055 }
1056
1057 /* Return the GDB type for the pseudo register REGNUM, which is the
1058 ABI-level view. This function is only called if there is a target
1059 description which includes registers, so we know precisely the
1060 types of hardware registers. */
1061
1062 static struct type *
1063 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
1064 {
1065 const int num_regs = gdbarch_num_regs (gdbarch);
1066 int rawnum = regnum % num_regs;
1067 struct type *rawtype;
1068
1069 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
1070
1071 /* Absent registers are still absent. */
1072 rawtype = gdbarch_register_type (gdbarch, rawnum);
1073 if (TYPE_LENGTH (rawtype) == 0)
1074 return rawtype;
1075
1076 if (mips_float_register_p (gdbarch, rawnum))
1077 /* Present the floating point registers however the hardware did;
1078 do not try to convert between FPU layouts. */
1079 return rawtype;
1080
1081 /* Use pointer types for registers if we can. For n32 we can not,
1082 since we do not have a 64-bit pointer type. */
1083 if (mips_abi_regsize (gdbarch)
1084 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
1085 {
1086 if (rawnum == MIPS_SP_REGNUM
1087 || rawnum == mips_regnum (gdbarch)->badvaddr)
1088 return builtin_type (gdbarch)->builtin_data_ptr;
1089 else if (rawnum == mips_regnum (gdbarch)->pc)
1090 return builtin_type (gdbarch)->builtin_func_ptr;
1091 }
1092
1093 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
1094 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
1095 || rawnum == mips_regnum (gdbarch)->lo
1096 || rawnum == mips_regnum (gdbarch)->hi
1097 || rawnum == mips_regnum (gdbarch)->badvaddr
1098 || rawnum == mips_regnum (gdbarch)->cause
1099 || rawnum == mips_regnum (gdbarch)->pc
1100 || (mips_regnum (gdbarch)->dspacc != -1
1101 && rawnum >= mips_regnum (gdbarch)->dspacc
1102 && rawnum < mips_regnum (gdbarch)->dspacc + 6)))
1103 return builtin_type (gdbarch)->builtin_int32;
1104
1105 if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX
1106 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX
1107 && rawnum >= MIPS_EMBED_FP0_REGNUM + 32
1108 && rawnum <= MIPS_LAST_EMBED_REGNUM)
1109 {
1110 /* The pseudo/cooked view of embedded registers is always
1111 32-bit, even if the target transfers 64-bit values for them.
1112 New targets relying on XML descriptions should only transfer
1113 the necessary 32 bits, but older versions of GDB expected 64,
1114 so allow the target to provide 64 bits without interfering
1115 with the displayed type. */
1116 return builtin_type (gdbarch)->builtin_int32;
1117 }
1118
1119 /* For all other registers, pass through the hardware type. */
1120 return rawtype;
1121 }
1122
1123 /* Should the upper word of 64-bit addresses be zeroed? */
1124 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
1125
1126 static int
1127 mips_mask_address_p (struct gdbarch_tdep *tdep)
1128 {
1129 switch (mask_address_var)
1130 {
1131 case AUTO_BOOLEAN_TRUE:
1132 return 1;
1133 case AUTO_BOOLEAN_FALSE:
1134 return 0;
1135 break;
1136 case AUTO_BOOLEAN_AUTO:
1137 return tdep->default_mask_address_p;
1138 default:
1139 internal_error (__FILE__, __LINE__,
1140 _("mips_mask_address_p: bad switch"));
1141 return -1;
1142 }
1143 }
1144
1145 static void
1146 show_mask_address (struct ui_file *file, int from_tty,
1147 struct cmd_list_element *c, const char *value)
1148 {
1149 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
1150
1151 deprecated_show_value_hack (file, from_tty, c, value);
1152 switch (mask_address_var)
1153 {
1154 case AUTO_BOOLEAN_TRUE:
1155 printf_filtered ("The 32 bit mips address mask is enabled\n");
1156 break;
1157 case AUTO_BOOLEAN_FALSE:
1158 printf_filtered ("The 32 bit mips address mask is disabled\n");
1159 break;
1160 case AUTO_BOOLEAN_AUTO:
1161 printf_filtered
1162 ("The 32 bit address mask is set automatically. Currently %s\n",
1163 mips_mask_address_p (tdep) ? "enabled" : "disabled");
1164 break;
1165 default:
1166 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
1167 break;
1168 }
1169 }
1170
1171 /* Tell if the program counter value in MEMADDR is in a standard ISA
1172 function. */
1173
1174 int
1175 mips_pc_is_mips (CORE_ADDR memaddr)
1176 {
1177 struct bound_minimal_symbol sym;
1178
1179 /* Flags indicating that this is a MIPS16 or microMIPS function is
1180 stored by elfread.c in the high bit of the info field. Use this
1181 to decide if the function is standard MIPS. Otherwise if bit 0
1182 of the address is clear, then this is a standard MIPS function. */
1183 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1184 if (sym.minsym)
1185 return msymbol_is_mips (sym.minsym);
1186 else
1187 return is_mips_addr (memaddr);
1188 }
1189
1190 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1191
1192 int
1193 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1194 {
1195 struct bound_minimal_symbol sym;
1196
1197 /* A flag indicating that this is a MIPS16 function is stored by
1198 elfread.c in the high bit of the info field. Use this to decide
1199 if the function is MIPS16. Otherwise if bit 0 of the address is
1200 set, then ELF file flags will tell if this is a MIPS16 function. */
1201 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1202 if (sym.minsym)
1203 return msymbol_is_mips16 (sym.minsym);
1204 else
1205 return is_mips16_addr (gdbarch, memaddr);
1206 }
1207
1208 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1209
1210 int
1211 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1212 {
1213 struct bound_minimal_symbol sym;
1214
1215 /* A flag indicating that this is a microMIPS function is stored by
1216 elfread.c in the high bit of the info field. Use this to decide
1217 if the function is microMIPS. Otherwise if bit 0 of the address
1218 is set, then ELF file flags will tell if this is a microMIPS
1219 function. */
1220 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1221 if (sym.minsym)
1222 return msymbol_is_micromips (sym.minsym);
1223 else
1224 return is_micromips_addr (gdbarch, memaddr);
1225 }
1226
1227 /* Tell the ISA type of the function the program counter value in MEMADDR
1228 is in. */
1229
1230 static enum mips_isa
1231 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr)
1232 {
1233 struct bound_minimal_symbol sym;
1234
1235 /* A flag indicating that this is a MIPS16 or a microMIPS function
1236 is stored by elfread.c in the high bit of the info field. Use
1237 this to decide if the function is MIPS16 or microMIPS or normal
1238 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1239 flags will tell if this is a MIPS16 or a microMIPS function. */
1240 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr));
1241 if (sym.minsym)
1242 {
1243 if (msymbol_is_micromips (sym.minsym))
1244 return ISA_MICROMIPS;
1245 else if (msymbol_is_mips16 (sym.minsym))
1246 return ISA_MIPS16;
1247 else
1248 return ISA_MIPS;
1249 }
1250 else
1251 {
1252 if (is_mips_addr (memaddr))
1253 return ISA_MIPS;
1254 else if (is_micromips_addr (gdbarch, memaddr))
1255 return ISA_MICROMIPS;
1256 else
1257 return ISA_MIPS16;
1258 }
1259 }
1260
1261 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1262 The need for comes from the ISA bit having been cleared, making
1263 addresses in FDE, range records, etc. referring to compressed code
1264 different to those in line information, the symbol table and finally
1265 the PC register. That in turn confuses many operations. */
1266
1267 static CORE_ADDR
1268 mips_adjust_dwarf2_addr (CORE_ADDR pc)
1269 {
1270 pc = unmake_compact_addr (pc);
1271 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc);
1272 }
1273
1274 /* Recalculate the line record requested so that the resulting PC has
1275 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1276 this adjustment comes from some records associated with compressed
1277 code having the ISA bit cleared, most notably at function prologue
1278 ends. The ISA bit is in this context retrieved from the minimal
1279 symbol covering the address requested, which in turn has been
1280 constructed from the binary's symbol table rather than DWARF-2
1281 information. The correct setting of the ISA bit is required for
1282 breakpoint addresses to correctly match against the stop PC.
1283
1284 As line entries can specify relative address adjustments we need to
1285 keep track of the absolute value of the last line address recorded
1286 in line information, so that we can calculate the actual address to
1287 apply the ISA bit adjustment to. We use PC for this tracking and
1288 keep the original address there.
1289
1290 As such relative address adjustments can be odd within compressed
1291 code we need to keep track of the last line address with the ISA
1292 bit adjustment applied too, as the original address may or may not
1293 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1294 the adjusted address there.
1295
1296 For relative address adjustments we then use these variables to
1297 calculate the address intended by line information, which will be
1298 PC-relative, and return an updated adjustment carrying ISA bit
1299 information, which will be ADJ_PC-relative. For absolute address
1300 adjustments we just return the same address that we store in ADJ_PC
1301 too.
1302
1303 As the first line entry can be relative to an implied address value
1304 of 0 we need to have the initial address set up that we store in PC
1305 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1306 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1307
1308 static CORE_ADDR
1309 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel)
1310 {
1311 static CORE_ADDR adj_pc;
1312 static CORE_ADDR pc;
1313 CORE_ADDR isa_pc;
1314
1315 pc = rel ? pc + addr : addr;
1316 isa_pc = mips_adjust_dwarf2_addr (pc);
1317 addr = rel ? isa_pc - adj_pc : isa_pc;
1318 adj_pc = isa_pc;
1319 return addr;
1320 }
1321
1322 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1323
1324 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_";
1325 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_";
1326 static const char mips_str_call_fp_stub[] = "__call_stub_fp_";
1327 static const char mips_str_call_stub[] = "__call_stub_";
1328 static const char mips_str_fn_stub[] = "__fn_stub_";
1329
1330 /* This is used as a PIC thunk prefix. */
1331
1332 static const char mips_str_pic[] = ".pic.";
1333
1334 /* Return non-zero if the PC is inside a call thunk (aka stub or
1335 trampoline) that should be treated as a temporary frame. */
1336
1337 static int
1338 mips_in_frame_stub (CORE_ADDR pc)
1339 {
1340 CORE_ADDR start_addr;
1341 const char *name;
1342
1343 /* Find the starting address of the function containing the PC. */
1344 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
1345 return 0;
1346
1347 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1348 if (startswith (name, mips_str_mips16_call_stub))
1349 return 1;
1350 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1351 if (startswith (name, mips_str_call_stub))
1352 return 1;
1353 /* If the PC is in __fn_stub_*, this is a call stub. */
1354 if (startswith (name, mips_str_fn_stub))
1355 return 1;
1356
1357 return 0; /* Not a stub. */
1358 }
1359
1360 /* MIPS believes that the PC has a sign extended value. Perhaps the
1361 all registers should be sign extended for simplicity? */
1362
1363 static CORE_ADDR
1364 mips_read_pc (struct regcache *regcache)
1365 {
1366 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1367 LONGEST pc;
1368
1369 regcache_cooked_read_signed (regcache, regnum, &pc);
1370 return pc;
1371 }
1372
1373 static CORE_ADDR
1374 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1375 {
1376 CORE_ADDR pc;
1377
1378 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch));
1379 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1380 intermediate frames. In this case we can get the caller's address
1381 from $ra, or if $ra contains an address within a thunk as well, then
1382 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1383 and thus the caller's address is in $s2. */
1384 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc))
1385 {
1386 pc = frame_unwind_register_signed
1387 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
1388 if (mips_in_frame_stub (pc))
1389 pc = frame_unwind_register_signed
1390 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
1391 }
1392 return pc;
1393 }
1394
1395 static CORE_ADDR
1396 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1397 {
1398 return frame_unwind_register_signed
1399 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
1400 }
1401
1402 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1403 dummy frame. The frame ID's base needs to match the TOS value
1404 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1405 breakpoint. */
1406
1407 static struct frame_id
1408 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1409 {
1410 return frame_id_build
1411 (get_frame_register_signed (this_frame,
1412 gdbarch_num_regs (gdbarch)
1413 + MIPS_SP_REGNUM),
1414 get_frame_pc (this_frame));
1415 }
1416
1417 /* Implement the "write_pc" gdbarch method. */
1418
1419 void
1420 mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
1421 {
1422 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
1423
1424 regcache_cooked_write_unsigned (regcache, regnum, pc);
1425 }
1426
1427 /* Fetch and return instruction from the specified location. Handle
1428 MIPS16/microMIPS as appropriate. */
1429
1430 static ULONGEST
1431 mips_fetch_instruction (struct gdbarch *gdbarch,
1432 enum mips_isa isa, CORE_ADDR addr, int *statusp)
1433 {
1434 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1435 gdb_byte buf[MIPS_INSN32_SIZE];
1436 int instlen;
1437 int status;
1438
1439 switch (isa)
1440 {
1441 case ISA_MICROMIPS:
1442 case ISA_MIPS16:
1443 instlen = MIPS_INSN16_SIZE;
1444 addr = unmake_compact_addr (addr);
1445 break;
1446 case ISA_MIPS:
1447 instlen = MIPS_INSN32_SIZE;
1448 break;
1449 default:
1450 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1451 break;
1452 }
1453 status = target_read_memory (addr, buf, instlen);
1454 if (statusp != NULL)
1455 *statusp = status;
1456 if (status)
1457 {
1458 if (statusp == NULL)
1459 memory_error (status, addr);
1460 return 0;
1461 }
1462 return extract_unsigned_integer (buf, instlen, byte_order);
1463 }
1464
1465 /* These are the fields of 32 bit mips instructions. */
1466 #define mips32_op(x) (x >> 26)
1467 #define itype_op(x) (x >> 26)
1468 #define itype_rs(x) ((x >> 21) & 0x1f)
1469 #define itype_rt(x) ((x >> 16) & 0x1f)
1470 #define itype_immediate(x) (x & 0xffff)
1471
1472 #define jtype_op(x) (x >> 26)
1473 #define jtype_target(x) (x & 0x03ffffff)
1474
1475 #define rtype_op(x) (x >> 26)
1476 #define rtype_rs(x) ((x >> 21) & 0x1f)
1477 #define rtype_rt(x) ((x >> 16) & 0x1f)
1478 #define rtype_rd(x) ((x >> 11) & 0x1f)
1479 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1480 #define rtype_funct(x) (x & 0x3f)
1481
1482 /* MicroMIPS instruction fields. */
1483 #define micromips_op(x) ((x) >> 10)
1484
1485 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1486 bit and the size respectively of the field extracted. */
1487 #define b0s4_imm(x) ((x) & 0xf)
1488 #define b0s5_imm(x) ((x) & 0x1f)
1489 #define b0s5_reg(x) ((x) & 0x1f)
1490 #define b0s7_imm(x) ((x) & 0x7f)
1491 #define b0s10_imm(x) ((x) & 0x3ff)
1492 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1493 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1494 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1495 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1496 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1497 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1498 #define b6s4_op(x) (((x) >> 6) & 0xf)
1499 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1500
1501 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1502 respectively of the field extracted. */
1503 #define b0s6_op(x) ((x) & 0x3f)
1504 #define b0s11_op(x) ((x) & 0x7ff)
1505 #define b0s12_imm(x) ((x) & 0xfff)
1506 #define b0s16_imm(x) ((x) & 0xffff)
1507 #define b0s26_imm(x) ((x) & 0x3ffffff)
1508 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1509 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1510 #define b12s4_op(x) (((x) >> 12) & 0xf)
1511
1512 /* Return the size in bytes of the instruction INSN encoded in the ISA
1513 instruction set. */
1514
1515 static int
1516 mips_insn_size (enum mips_isa isa, ULONGEST insn)
1517 {
1518 switch (isa)
1519 {
1520 case ISA_MICROMIPS:
1521 if (micromips_op (insn) == 0x1f)
1522 return 3 * MIPS_INSN16_SIZE;
1523 else if (((micromips_op (insn) & 0x4) == 0x4)
1524 || ((micromips_op (insn) & 0x7) == 0x0))
1525 return 2 * MIPS_INSN16_SIZE;
1526 else
1527 return MIPS_INSN16_SIZE;
1528 case ISA_MIPS16:
1529 if ((insn & 0xf800) == 0xf000)
1530 return 2 * MIPS_INSN16_SIZE;
1531 else
1532 return MIPS_INSN16_SIZE;
1533 case ISA_MIPS:
1534 return MIPS_INSN32_SIZE;
1535 }
1536 internal_error (__FILE__, __LINE__, _("invalid ISA"));
1537 }
1538
1539 static LONGEST
1540 mips32_relative_offset (ULONGEST inst)
1541 {
1542 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
1543 }
1544
1545 /* Determine the address of the next instruction executed after the INST
1546 floating condition branch instruction at PC. COUNT specifies the
1547 number of the floating condition bits tested by the branch. */
1548
1549 static CORE_ADDR
1550 mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1551 ULONGEST inst, CORE_ADDR pc, int count)
1552 {
1553 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1554 int cnum = (itype_rt (inst) >> 2) & (count - 1);
1555 int tf = itype_rt (inst) & 1;
1556 int mask = (1 << count) - 1;
1557 ULONGEST fcs;
1558 int cond;
1559
1560 if (fcsr == -1)
1561 /* No way to handle; it'll most likely trap anyway. */
1562 return pc;
1563
1564 fcs = get_frame_register_unsigned (frame, fcsr);
1565 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1566
1567 if (((cond >> cnum) & mask) != mask * !tf)
1568 pc += mips32_relative_offset (inst);
1569 else
1570 pc += 4;
1571
1572 return pc;
1573 }
1574
1575 /* Return nonzero if the gdbarch is an Octeon series. */
1576
1577 static int
1578 is_octeon (struct gdbarch *gdbarch)
1579 {
1580 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
1581
1582 return (info->mach == bfd_mach_mips_octeon
1583 || info->mach == bfd_mach_mips_octeonp
1584 || info->mach == bfd_mach_mips_octeon2);
1585 }
1586
1587 /* Return true if the OP represents the Octeon's BBIT instruction. */
1588
1589 static int
1590 is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
1591 {
1592 if (!is_octeon (gdbarch))
1593 return 0;
1594 /* BBIT0 is encoded as LWC2: 110 010. */
1595 /* BBIT032 is encoded as LDC2: 110 110. */
1596 /* BBIT1 is encoded as SWC2: 111 010. */
1597 /* BBIT132 is encoded as SDC2: 111 110. */
1598 if (op == 50 || op == 54 || op == 58 || op == 62)
1599 return 1;
1600 return 0;
1601 }
1602
1603
1604 /* Determine where to set a single step breakpoint while considering
1605 branch prediction. */
1606
1607 static CORE_ADDR
1608 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
1609 {
1610 struct gdbarch *gdbarch = get_frame_arch (frame);
1611 unsigned long inst;
1612 int op;
1613 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
1614 op = itype_op (inst);
1615 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
1616 instruction. */
1617 {
1618 if (op >> 2 == 5)
1619 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1620 {
1621 switch (op & 0x03)
1622 {
1623 case 0: /* BEQL */
1624 goto equal_branch;
1625 case 1: /* BNEL */
1626 goto neq_branch;
1627 case 2: /* BLEZL */
1628 goto less_branch;
1629 case 3: /* BGTZL */
1630 goto greater_branch;
1631 default:
1632 pc += 4;
1633 }
1634 }
1635 else if (op == 17 && itype_rs (inst) == 8)
1636 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1637 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1);
1638 else if (op == 17 && itype_rs (inst) == 9
1639 && (itype_rt (inst) & 2) == 0)
1640 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1641 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2);
1642 else if (op == 17 && itype_rs (inst) == 10
1643 && (itype_rt (inst) & 2) == 0)
1644 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1645 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4);
1646 else if (op == 29)
1647 /* JALX: 011101 */
1648 /* The new PC will be alternate mode. */
1649 {
1650 unsigned long reg;
1651
1652 reg = jtype_target (inst) << 2;
1653 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1654 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1;
1655 }
1656 else if (is_octeon_bbit_op (op, gdbarch))
1657 {
1658 int bit, branch_if;
1659
1660 branch_if = op == 58 || op == 62;
1661 bit = itype_rt (inst);
1662
1663 /* Take into account the *32 instructions. */
1664 if (op == 54 || op == 62)
1665 bit += 32;
1666
1667 if (((get_frame_register_signed (frame,
1668 itype_rs (inst)) >> bit) & 1)
1669 == branch_if)
1670 pc += mips32_relative_offset (inst) + 4;
1671 else
1672 pc += 8; /* After the delay slot. */
1673 }
1674
1675 else
1676 pc += 4; /* Not a branch, next instruction is easy. */
1677 }
1678 else
1679 { /* This gets way messy. */
1680
1681 /* Further subdivide into SPECIAL, REGIMM and other. */
1682 switch (op & 0x07) /* Extract bits 28,27,26. */
1683 {
1684 case 0: /* SPECIAL */
1685 op = rtype_funct (inst);
1686 switch (op)
1687 {
1688 case 8: /* JR */
1689 case 9: /* JALR */
1690 /* Set PC to that address. */
1691 pc = get_frame_register_signed (frame, rtype_rs (inst));
1692 break;
1693 case 12: /* SYSCALL */
1694 {
1695 struct gdbarch_tdep *tdep;
1696
1697 tdep = gdbarch_tdep (get_frame_arch (frame));
1698 if (tdep->syscall_next_pc != NULL)
1699 pc = tdep->syscall_next_pc (frame);
1700 else
1701 pc += 4;
1702 }
1703 break;
1704 default:
1705 pc += 4;
1706 }
1707
1708 break; /* end SPECIAL */
1709 case 1: /* REGIMM */
1710 {
1711 op = itype_rt (inst); /* branch condition */
1712 switch (op)
1713 {
1714 case 0: /* BLTZ */
1715 case 2: /* BLTZL */
1716 case 16: /* BLTZAL */
1717 case 18: /* BLTZALL */
1718 less_branch:
1719 if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1720 pc += mips32_relative_offset (inst) + 4;
1721 else
1722 pc += 8; /* after the delay slot */
1723 break;
1724 case 1: /* BGEZ */
1725 case 3: /* BGEZL */
1726 case 17: /* BGEZAL */
1727 case 19: /* BGEZALL */
1728 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1729 pc += mips32_relative_offset (inst) + 4;
1730 else
1731 pc += 8; /* after the delay slot */
1732 break;
1733 case 0x1c: /* BPOSGE32 */
1734 case 0x1e: /* BPOSGE64 */
1735 pc += 4;
1736 if (itype_rs (inst) == 0)
1737 {
1738 unsigned int pos = (op & 2) ? 64 : 32;
1739 int dspctl = mips_regnum (gdbarch)->dspctl;
1740
1741 if (dspctl == -1)
1742 /* No way to handle; it'll most likely trap anyway. */
1743 break;
1744
1745 if ((get_frame_register_unsigned (frame,
1746 dspctl) & 0x7f) >= pos)
1747 pc += mips32_relative_offset (inst);
1748 else
1749 pc += 4;
1750 }
1751 break;
1752 /* All of the other instructions in the REGIMM category */
1753 default:
1754 pc += 4;
1755 }
1756 }
1757 break; /* end REGIMM */
1758 case 2: /* J */
1759 case 3: /* JAL */
1760 {
1761 unsigned long reg;
1762 reg = jtype_target (inst) << 2;
1763 /* Upper four bits get never changed... */
1764 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1765 }
1766 break;
1767 case 4: /* BEQ, BEQL */
1768 equal_branch:
1769 if (get_frame_register_signed (frame, itype_rs (inst)) ==
1770 get_frame_register_signed (frame, itype_rt (inst)))
1771 pc += mips32_relative_offset (inst) + 4;
1772 else
1773 pc += 8;
1774 break;
1775 case 5: /* BNE, BNEL */
1776 neq_branch:
1777 if (get_frame_register_signed (frame, itype_rs (inst)) !=
1778 get_frame_register_signed (frame, itype_rt (inst)))
1779 pc += mips32_relative_offset (inst) + 4;
1780 else
1781 pc += 8;
1782 break;
1783 case 6: /* BLEZ, BLEZL */
1784 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1785 pc += mips32_relative_offset (inst) + 4;
1786 else
1787 pc += 8;
1788 break;
1789 case 7:
1790 default:
1791 greater_branch: /* BGTZ, BGTZL */
1792 if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1793 pc += mips32_relative_offset (inst) + 4;
1794 else
1795 pc += 8;
1796 break;
1797 } /* switch */
1798 } /* else */
1799 return pc;
1800 } /* mips32_next_pc */
1801
1802 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1803 INSN. */
1804
1805 static LONGEST
1806 micromips_relative_offset7 (ULONGEST insn)
1807 {
1808 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1;
1809 }
1810
1811 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1812 INSN. */
1813
1814 static LONGEST
1815 micromips_relative_offset10 (ULONGEST insn)
1816 {
1817 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1;
1818 }
1819
1820 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1821 INSN. */
1822
1823 static LONGEST
1824 micromips_relative_offset16 (ULONGEST insn)
1825 {
1826 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1;
1827 }
1828
1829 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1830
1831 static int
1832 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
1833 {
1834 ULONGEST insn;
1835
1836 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1837 return mips_insn_size (ISA_MICROMIPS, insn);
1838 }
1839
1840 /* Calculate the address of the next microMIPS instruction to execute
1841 after the INSN coprocessor 1 conditional branch instruction at the
1842 address PC. COUNT denotes the number of coprocessor condition bits
1843 examined by the branch. */
1844
1845 static CORE_ADDR
1846 micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
1847 ULONGEST insn, CORE_ADDR pc, int count)
1848 {
1849 int fcsr = mips_regnum (gdbarch)->fp_control_status;
1850 int cnum = b2s3_cc (insn >> 16) & (count - 1);
1851 int tf = b5s5_op (insn >> 16) & 1;
1852 int mask = (1 << count) - 1;
1853 ULONGEST fcs;
1854 int cond;
1855
1856 if (fcsr == -1)
1857 /* No way to handle; it'll most likely trap anyway. */
1858 return pc;
1859
1860 fcs = get_frame_register_unsigned (frame, fcsr);
1861 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
1862
1863 if (((cond >> cnum) & mask) != mask * !tf)
1864 pc += micromips_relative_offset16 (insn);
1865 else
1866 pc += micromips_pc_insn_size (gdbarch, pc);
1867
1868 return pc;
1869 }
1870
1871 /* Calculate the address of the next microMIPS instruction to execute
1872 after the instruction at the address PC. */
1873
1874 static CORE_ADDR
1875 micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1876 {
1877 struct gdbarch *gdbarch = get_frame_arch (frame);
1878 ULONGEST insn;
1879
1880 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1881 pc += MIPS_INSN16_SIZE;
1882 switch (mips_insn_size (ISA_MICROMIPS, insn))
1883 {
1884 /* 48-bit instructions. */
1885 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
1886 /* No branch or jump instructions in this category. */
1887 pc += 2 * MIPS_INSN16_SIZE;
1888 break;
1889
1890 /* 32-bit instructions. */
1891 case 2 * MIPS_INSN16_SIZE:
1892 insn <<= 16;
1893 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
1894 pc += MIPS_INSN16_SIZE;
1895 switch (micromips_op (insn >> 16))
1896 {
1897 case 0x00: /* POOL32A: bits 000000 */
1898 if (b0s6_op (insn) == 0x3c
1899 /* POOL32Axf: bits 000000 ... 111100 */
1900 && (b6s10_ext (insn) & 0x2bf) == 0x3c)
1901 /* JALR, JALR.HB: 000000 000x111100 111100 */
1902 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1903 pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16));
1904 break;
1905
1906 case 0x10: /* POOL32I: bits 010000 */
1907 switch (b5s5_op (insn >> 16))
1908 {
1909 case 0x00: /* BLTZ: bits 010000 00000 */
1910 case 0x01: /* BLTZAL: bits 010000 00001 */
1911 case 0x11: /* BLTZALS: bits 010000 10001 */
1912 if (get_frame_register_signed (frame,
1913 b0s5_reg (insn >> 16)) < 0)
1914 pc += micromips_relative_offset16 (insn);
1915 else
1916 pc += micromips_pc_insn_size (gdbarch, pc);
1917 break;
1918
1919 case 0x02: /* BGEZ: bits 010000 00010 */
1920 case 0x03: /* BGEZAL: bits 010000 00011 */
1921 case 0x13: /* BGEZALS: bits 010000 10011 */
1922 if (get_frame_register_signed (frame,
1923 b0s5_reg (insn >> 16)) >= 0)
1924 pc += micromips_relative_offset16 (insn);
1925 else
1926 pc += micromips_pc_insn_size (gdbarch, pc);
1927 break;
1928
1929 case 0x04: /* BLEZ: bits 010000 00100 */
1930 if (get_frame_register_signed (frame,
1931 b0s5_reg (insn >> 16)) <= 0)
1932 pc += micromips_relative_offset16 (insn);
1933 else
1934 pc += micromips_pc_insn_size (gdbarch, pc);
1935 break;
1936
1937 case 0x05: /* BNEZC: bits 010000 00101 */
1938 if (get_frame_register_signed (frame,
1939 b0s5_reg (insn >> 16)) != 0)
1940 pc += micromips_relative_offset16 (insn);
1941 break;
1942
1943 case 0x06: /* BGTZ: bits 010000 00110 */
1944 if (get_frame_register_signed (frame,
1945 b0s5_reg (insn >> 16)) > 0)
1946 pc += micromips_relative_offset16 (insn);
1947 else
1948 pc += micromips_pc_insn_size (gdbarch, pc);
1949 break;
1950
1951 case 0x07: /* BEQZC: bits 010000 00111 */
1952 if (get_frame_register_signed (frame,
1953 b0s5_reg (insn >> 16)) == 0)
1954 pc += micromips_relative_offset16 (insn);
1955 break;
1956
1957 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1958 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1959 if (((insn >> 16) & 0x3) == 0x0)
1960 /* BC2F, BC2T: don't know how to handle these. */
1961 break;
1962 break;
1963
1964 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1965 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1966 {
1967 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64;
1968 int dspctl = mips_regnum (gdbarch)->dspctl;
1969
1970 if (dspctl == -1)
1971 /* No way to handle; it'll most likely trap anyway. */
1972 break;
1973
1974 if ((get_frame_register_unsigned (frame,
1975 dspctl) & 0x7f) >= pos)
1976 pc += micromips_relative_offset16 (insn);
1977 else
1978 pc += micromips_pc_insn_size (gdbarch, pc);
1979 }
1980 break;
1981
1982 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1983 /* BC1ANY2F: bits 010000 11100 xxx01 */
1984 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1985 /* BC1ANY2T: bits 010000 11101 xxx01 */
1986 if (((insn >> 16) & 0x2) == 0x0)
1987 pc = micromips_bc1_pc (gdbarch, frame, insn, pc,
1988 ((insn >> 16) & 0x1) + 1);
1989 break;
1990
1991 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1992 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1993 if (((insn >> 16) & 0x3) == 0x1)
1994 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4);
1995 break;
1996 }
1997 break;
1998
1999 case 0x1d: /* JALS: bits 011101 */
2000 case 0x35: /* J: bits 110101 */
2001 case 0x3d: /* JAL: bits 111101 */
2002 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1);
2003 break;
2004
2005 case 0x25: /* BEQ: bits 100101 */
2006 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
2007 == get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
2008 pc += micromips_relative_offset16 (insn);
2009 else
2010 pc += micromips_pc_insn_size (gdbarch, pc);
2011 break;
2012
2013 case 0x2d: /* BNE: bits 101101 */
2014 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
2015 != get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
2016 pc += micromips_relative_offset16 (insn);
2017 else
2018 pc += micromips_pc_insn_size (gdbarch, pc);
2019 break;
2020
2021 case 0x3c: /* JALX: bits 111100 */
2022 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2);
2023 break;
2024 }
2025 break;
2026
2027 /* 16-bit instructions. */
2028 case MIPS_INSN16_SIZE:
2029 switch (micromips_op (insn))
2030 {
2031 case 0x11: /* POOL16C: bits 010001 */
2032 if ((b5s5_op (insn) & 0x1c) == 0xc)
2033 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2034 pc = get_frame_register_signed (frame, b0s5_reg (insn));
2035 else if (b5s5_op (insn) == 0x18)
2036 /* JRADDIUSP: bits 010001 11000 */
2037 pc = get_frame_register_signed (frame, MIPS_RA_REGNUM);
2038 break;
2039
2040 case 0x23: /* BEQZ16: bits 100011 */
2041 {
2042 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2043
2044 if (get_frame_register_signed (frame, rs) == 0)
2045 pc += micromips_relative_offset7 (insn);
2046 else
2047 pc += micromips_pc_insn_size (gdbarch, pc);
2048 }
2049 break;
2050
2051 case 0x2b: /* BNEZ16: bits 101011 */
2052 {
2053 int rs = mips_reg3_to_reg[b7s3_reg (insn)];
2054
2055 if (get_frame_register_signed (frame, rs) != 0)
2056 pc += micromips_relative_offset7 (insn);
2057 else
2058 pc += micromips_pc_insn_size (gdbarch, pc);
2059 }
2060 break;
2061
2062 case 0x33: /* B16: bits 110011 */
2063 pc += micromips_relative_offset10 (insn);
2064 break;
2065 }
2066 break;
2067 }
2068
2069 return pc;
2070 }
2071
2072 /* Decoding the next place to set a breakpoint is irregular for the
2073 mips 16 variant, but fortunately, there fewer instructions. We have
2074 to cope ith extensions for 16 bit instructions and a pair of actual
2075 32 bit instructions. We dont want to set a single step instruction
2076 on the extend instruction either. */
2077
2078 /* Lots of mips16 instruction formats */
2079 /* Predicting jumps requires itype,ritype,i8type
2080 and their extensions extItype,extritype,extI8type. */
2081 enum mips16_inst_fmts
2082 {
2083 itype, /* 0 immediate 5,10 */
2084 ritype, /* 1 5,3,8 */
2085 rrtype, /* 2 5,3,3,5 */
2086 rritype, /* 3 5,3,3,5 */
2087 rrrtype, /* 4 5,3,3,3,2 */
2088 rriatype, /* 5 5,3,3,1,4 */
2089 shifttype, /* 6 5,3,3,3,2 */
2090 i8type, /* 7 5,3,8 */
2091 i8movtype, /* 8 5,3,3,5 */
2092 i8mov32rtype, /* 9 5,3,5,3 */
2093 i64type, /* 10 5,3,8 */
2094 ri64type, /* 11 5,3,3,5 */
2095 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
2096 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2097 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
2098 extRRItype, /* 15 5,5,5,5,3,3,5 */
2099 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
2100 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2101 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
2102 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
2103 extRi64type, /* 20 5,6,5,5,3,3,5 */
2104 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2105 };
2106 /* I am heaping all the fields of the formats into one structure and
2107 then, only the fields which are involved in instruction extension. */
2108 struct upk_mips16
2109 {
2110 CORE_ADDR offset;
2111 unsigned int regx; /* Function in i8 type. */
2112 unsigned int regy;
2113 };
2114
2115
2116 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2117 for the bits which make up the immediate extension. */
2118
2119 static CORE_ADDR
2120 extended_offset (unsigned int extension)
2121 {
2122 CORE_ADDR value;
2123
2124 value = (extension >> 16) & 0x1f; /* Extract 15:11. */
2125 value = value << 6;
2126 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */
2127 value = value << 5;
2128 value |= extension & 0x1f; /* Extract 4:0. */
2129
2130 return value;
2131 }
2132
2133 /* Only call this function if you know that this is an extendable
2134 instruction. It won't malfunction, but why make excess remote memory
2135 references? If the immediate operands get sign extended or something,
2136 do it after the extension is performed. */
2137 /* FIXME: Every one of these cases needs to worry about sign extension
2138 when the offset is to be used in relative addressing. */
2139
2140 static unsigned int
2141 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
2142 {
2143 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2144 gdb_byte buf[8];
2145
2146 pc = unmake_compact_addr (pc); /* Clear the low order bit. */
2147 target_read_memory (pc, buf, 2);
2148 return extract_unsigned_integer (buf, 2, byte_order);
2149 }
2150
2151 static void
2152 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
2153 unsigned int extension,
2154 unsigned int inst,
2155 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
2156 {
2157 CORE_ADDR offset;
2158 int regx;
2159 int regy;
2160 switch (insn_format)
2161 {
2162 case itype:
2163 {
2164 CORE_ADDR value;
2165 if (extension)
2166 {
2167 value = extended_offset ((extension << 16) | inst);
2168 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2169 }
2170 else
2171 {
2172 value = inst & 0x7ff;
2173 value = (value ^ 0x400) - 0x400; /* Sign-extend. */
2174 }
2175 offset = value;
2176 regx = -1;
2177 regy = -1;
2178 }
2179 break;
2180 case ritype:
2181 case i8type:
2182 { /* A register identifier and an offset. */
2183 /* Most of the fields are the same as I type but the
2184 immediate value is of a different length. */
2185 CORE_ADDR value;
2186 if (extension)
2187 {
2188 value = extended_offset ((extension << 16) | inst);
2189 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */
2190 }
2191 else
2192 {
2193 value = inst & 0xff; /* 8 bits */
2194 value = (value ^ 0x80) - 0x80; /* Sign-extend. */
2195 }
2196 offset = value;
2197 regx = (inst >> 8) & 0x07; /* i8 funct */
2198 regy = -1;
2199 break;
2200 }
2201 case jalxtype:
2202 {
2203 unsigned long value;
2204 unsigned int nexthalf;
2205 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
2206 value = value << 16;
2207 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL);
2208 /* Low bit still set. */
2209 value |= nexthalf;
2210 offset = value;
2211 regx = -1;
2212 regy = -1;
2213 break;
2214 }
2215 default:
2216 internal_error (__FILE__, __LINE__, _("bad switch"));
2217 }
2218 upk->offset = offset;
2219 upk->regx = regx;
2220 upk->regy = regy;
2221 }
2222
2223
2224 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2225 and having a signed 16-bit OFFSET. */
2226
2227 static CORE_ADDR
2228 add_offset_16 (CORE_ADDR pc, int offset)
2229 {
2230 return pc + (offset << 1) + 2;
2231 }
2232
2233 static CORE_ADDR
2234 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
2235 unsigned int extension, unsigned int insn)
2236 {
2237 struct gdbarch *gdbarch = get_frame_arch (frame);
2238 int op = (insn >> 11);
2239 switch (op)
2240 {
2241 case 2: /* Branch */
2242 {
2243 struct upk_mips16 upk;
2244 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
2245 pc = add_offset_16 (pc, upk.offset);
2246 break;
2247 }
2248 case 3: /* JAL , JALX - Watch out, these are 32 bit
2249 instructions. */
2250 {
2251 struct upk_mips16 upk;
2252 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
2253 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2);
2254 if ((insn >> 10) & 0x01) /* Exchange mode */
2255 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */
2256 else
2257 pc |= 0x01;
2258 break;
2259 }
2260 case 4: /* beqz */
2261 {
2262 struct upk_mips16 upk;
2263 int reg;
2264 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2265 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2266 if (reg == 0)
2267 pc = add_offset_16 (pc, upk.offset);
2268 else
2269 pc += 2;
2270 break;
2271 }
2272 case 5: /* bnez */
2273 {
2274 struct upk_mips16 upk;
2275 int reg;
2276 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
2277 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
2278 if (reg != 0)
2279 pc = add_offset_16 (pc, upk.offset);
2280 else
2281 pc += 2;
2282 break;
2283 }
2284 case 12: /* I8 Formats btez btnez */
2285 {
2286 struct upk_mips16 upk;
2287 int reg;
2288 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
2289 /* upk.regx contains the opcode */
2290 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
2291 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
2292 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
2293 pc = add_offset_16 (pc, upk.offset);
2294 else
2295 pc += 2;
2296 break;
2297 }
2298 case 29: /* RR Formats JR, JALR, JALR-RA */
2299 {
2300 struct upk_mips16 upk;
2301 /* upk.fmt = rrtype; */
2302 op = insn & 0x1f;
2303 if (op == 0)
2304 {
2305 int reg;
2306 upk.regx = (insn >> 8) & 0x07;
2307 upk.regy = (insn >> 5) & 0x07;
2308 if ((upk.regy & 1) == 0)
2309 reg = mips_reg3_to_reg[upk.regx];
2310 else
2311 reg = 31; /* Function return instruction. */
2312 pc = get_frame_register_signed (frame, reg);
2313 }
2314 else
2315 pc += 2;
2316 break;
2317 }
2318 case 30:
2319 /* This is an instruction extension. Fetch the real instruction
2320 (which follows the extension) and decode things based on
2321 that. */
2322 {
2323 pc += 2;
2324 pc = extended_mips16_next_pc (frame, pc, insn,
2325 fetch_mips_16 (gdbarch, pc));
2326 break;
2327 }
2328 default:
2329 {
2330 pc += 2;
2331 break;
2332 }
2333 }
2334 return pc;
2335 }
2336
2337 static CORE_ADDR
2338 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
2339 {
2340 struct gdbarch *gdbarch = get_frame_arch (frame);
2341 unsigned int insn = fetch_mips_16 (gdbarch, pc);
2342 return extended_mips16_next_pc (frame, pc, 0, insn);
2343 }
2344
2345 /* The mips_next_pc function supports single_step when the remote
2346 target monitor or stub is not developed enough to do a single_step.
2347 It works by decoding the current instruction and predicting where a
2348 branch will go. This isn't hard because all the data is available.
2349 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2350 static CORE_ADDR
2351 mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
2352 {
2353 struct gdbarch *gdbarch = get_frame_arch (frame);
2354
2355 if (mips_pc_is_mips16 (gdbarch, pc))
2356 return mips16_next_pc (frame, pc);
2357 else if (mips_pc_is_micromips (gdbarch, pc))
2358 return micromips_next_pc (frame, pc);
2359 else
2360 return mips32_next_pc (frame, pc);
2361 }
2362
2363 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2364 or jump. */
2365
2366 static int
2367 mips16_instruction_is_compact_branch (unsigned short insn)
2368 {
2369 switch (insn & 0xf800)
2370 {
2371 case 0xe800:
2372 return (insn & 0x009f) == 0x80; /* JALRC/JRC */
2373 case 0x6000:
2374 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */
2375 case 0x2800: /* BNEZ */
2376 case 0x2000: /* BEQZ */
2377 case 0x1000: /* B */
2378 return 1;
2379 default:
2380 return 0;
2381 }
2382 }
2383
2384 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2385 or jump. */
2386
2387 static int
2388 micromips_instruction_is_compact_branch (unsigned short insn)
2389 {
2390 switch (micromips_op (insn))
2391 {
2392 case 0x11: /* POOL16C: bits 010001 */
2393 return (b5s5_op (insn) == 0x18
2394 /* JRADDIUSP: bits 010001 11000 */
2395 || b5s5_op (insn) == 0xd);
2396 /* JRC: bits 010011 01101 */
2397 case 0x10: /* POOL32I: bits 010000 */
2398 return (b5s5_op (insn) & 0x1d) == 0x5;
2399 /* BEQZC/BNEZC: bits 010000 001x1 */
2400 default:
2401 return 0;
2402 }
2403 }
2404
2405 struct mips_frame_cache
2406 {
2407 CORE_ADDR base;
2408 struct trad_frame_saved_reg *saved_regs;
2409 };
2410
2411 /* Set a register's saved stack address in temp_saved_regs. If an
2412 address has already been set for this register, do nothing; this
2413 way we will only recognize the first save of a given register in a
2414 function prologue.
2415
2416 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2417 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2418 Strictly speaking, only the second range is used as it is only second
2419 range (the ABI instead of ISA registers) that comes into play when finding
2420 saved registers in a frame. */
2421
2422 static void
2423 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
2424 int regnum, CORE_ADDR offset)
2425 {
2426 if (this_cache != NULL
2427 && this_cache->saved_regs[regnum].addr == -1)
2428 {
2429 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
2430 = offset;
2431 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
2432 = offset;
2433 }
2434 }
2435
2436
2437 /* Fetch the immediate value from a MIPS16 instruction.
2438 If the previous instruction was an EXTEND, use it to extend
2439 the upper bits of the immediate value. This is a helper function
2440 for mips16_scan_prologue. */
2441
2442 static int
2443 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2444 unsigned short inst, /* current instruction */
2445 int nbits, /* number of bits in imm field */
2446 int scale, /* scale factor to be applied to imm */
2447 int is_signed) /* is the imm field signed? */
2448 {
2449 int offset;
2450
2451 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2452 {
2453 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2454 if (offset & 0x8000) /* check for negative extend */
2455 offset = 0 - (0x10000 - (offset & 0xffff));
2456 return offset | (inst & 0x1f);
2457 }
2458 else
2459 {
2460 int max_imm = 1 << nbits;
2461 int mask = max_imm - 1;
2462 int sign_bit = max_imm >> 1;
2463
2464 offset = inst & mask;
2465 if (is_signed && (offset & sign_bit))
2466 offset = 0 - (max_imm - offset);
2467 return offset * scale;
2468 }
2469 }
2470
2471
2472 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2473 the associated FRAME_CACHE if not null.
2474 Return the address of the first instruction past the prologue. */
2475
2476 static CORE_ADDR
2477 mips16_scan_prologue (struct gdbarch *gdbarch,
2478 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2479 struct frame_info *this_frame,
2480 struct mips_frame_cache *this_cache)
2481 {
2482 int prev_non_prologue_insn = 0;
2483 int this_non_prologue_insn;
2484 int non_prologue_insns = 0;
2485 CORE_ADDR prev_pc;
2486 CORE_ADDR cur_pc;
2487 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */
2488 CORE_ADDR sp;
2489 long frame_offset = 0; /* Size of stack frame. */
2490 long frame_adjust = 0; /* Offset of FP from SP. */
2491 int frame_reg = MIPS_SP_REGNUM;
2492 unsigned short prev_inst = 0; /* saved copy of previous instruction. */
2493 unsigned inst = 0; /* current instruction */
2494 unsigned entry_inst = 0; /* the entry instruction */
2495 unsigned save_inst = 0; /* the save instruction */
2496 int prev_delay_slot = 0;
2497 int in_delay_slot;
2498 int reg, offset;
2499
2500 int extend_bytes = 0;
2501 int prev_extend_bytes = 0;
2502 CORE_ADDR end_prologue_addr;
2503
2504 /* Can be called when there's no process, and hence when there's no
2505 THIS_FRAME. */
2506 if (this_frame != NULL)
2507 sp = get_frame_register_signed (this_frame,
2508 gdbarch_num_regs (gdbarch)
2509 + MIPS_SP_REGNUM);
2510 else
2511 sp = 0;
2512
2513 if (limit_pc > start_pc + 200)
2514 limit_pc = start_pc + 200;
2515 prev_pc = start_pc;
2516
2517 /* Permit at most one non-prologue non-control-transfer instruction
2518 in the middle which may have been reordered by the compiler for
2519 optimisation. */
2520 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
2521 {
2522 this_non_prologue_insn = 0;
2523 in_delay_slot = 0;
2524
2525 /* Save the previous instruction. If it's an EXTEND, we'll extract
2526 the immediate offset extension from it in mips16_get_imm. */
2527 prev_inst = inst;
2528
2529 /* Fetch and decode the instruction. */
2530 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16,
2531 cur_pc, NULL);
2532
2533 /* Normally we ignore extend instructions. However, if it is
2534 not followed by a valid prologue instruction, then this
2535 instruction is not part of the prologue either. We must
2536 remember in this case to adjust the end_prologue_addr back
2537 over the extend. */
2538 if ((inst & 0xf800) == 0xf000) /* extend */
2539 {
2540 extend_bytes = MIPS_INSN16_SIZE;
2541 continue;
2542 }
2543
2544 prev_extend_bytes = extend_bytes;
2545 extend_bytes = 0;
2546
2547 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2548 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2549 {
2550 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2551 if (offset < 0) /* Negative stack adjustment? */
2552 frame_offset -= offset;
2553 else
2554 /* Exit loop if a positive stack adjustment is found, which
2555 usually means that the stack cleanup code in the function
2556 epilogue is reached. */
2557 break;
2558 }
2559 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2560 {
2561 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2562 reg = mips_reg3_to_reg[(inst & 0x700) >> 8];
2563 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2564 }
2565 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2566 {
2567 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2568 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2569 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2570 }
2571 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2572 {
2573 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2574 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2575 }
2576 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2577 {
2578 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2579 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2580 }
2581 else if (inst == 0x673d) /* move $s1, $sp */
2582 {
2583 frame_addr = sp;
2584 frame_reg = 17;
2585 }
2586 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2587 {
2588 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2589 frame_addr = sp + offset;
2590 frame_reg = 17;
2591 frame_adjust = offset;
2592 }
2593 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2594 {
2595 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2596 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2597 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2598 }
2599 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2600 {
2601 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2602 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5];
2603 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
2604 }
2605 else if ((inst & 0xf81f) == 0xe809
2606 && (inst & 0x700) != 0x700) /* entry */
2607 entry_inst = inst; /* Save for later processing. */
2608 else if ((inst & 0xff80) == 0x6480) /* save */
2609 {
2610 save_inst = inst; /* Save for later processing. */
2611 if (prev_extend_bytes) /* extend */
2612 save_inst |= prev_inst << 16;
2613 }
2614 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2615 {
2616 /* This instruction is part of the prologue, but we don't
2617 need to do anything special to handle it. */
2618 }
2619 else if (mips16_instruction_has_delay_slot (inst, 0))
2620 /* JAL/JALR/JALX/JR */
2621 {
2622 /* The instruction in the delay slot can be a part
2623 of the prologue, so move forward once more. */
2624 in_delay_slot = 1;
2625 if (mips16_instruction_has_delay_slot (inst, 1))
2626 /* JAL/JALX */
2627 {
2628 prev_extend_bytes = MIPS_INSN16_SIZE;
2629 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
2630 }
2631 }
2632 else
2633 {
2634 this_non_prologue_insn = 1;
2635 }
2636
2637 non_prologue_insns += this_non_prologue_insn;
2638
2639 /* A jump or branch, or enough non-prologue insns seen? If so,
2640 then we must have reached the end of the prologue by now. */
2641 if (prev_delay_slot || non_prologue_insns > 1
2642 || mips16_instruction_is_compact_branch (inst))
2643 break;
2644
2645 prev_non_prologue_insn = this_non_prologue_insn;
2646 prev_delay_slot = in_delay_slot;
2647 prev_pc = cur_pc - prev_extend_bytes;
2648 }
2649
2650 /* The entry instruction is typically the first instruction in a function,
2651 and it stores registers at offsets relative to the value of the old SP
2652 (before the prologue). But the value of the sp parameter to this
2653 function is the new SP (after the prologue has been executed). So we
2654 can't calculate those offsets until we've seen the entire prologue,
2655 and can calculate what the old SP must have been. */
2656 if (entry_inst != 0)
2657 {
2658 int areg_count = (entry_inst >> 8) & 7;
2659 int sreg_count = (entry_inst >> 6) & 3;
2660
2661 /* The entry instruction always subtracts 32 from the SP. */
2662 frame_offset += 32;
2663
2664 /* Now we can calculate what the SP must have been at the
2665 start of the function prologue. */
2666 sp += frame_offset;
2667
2668 /* Check if a0-a3 were saved in the caller's argument save area. */
2669 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2670 {
2671 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2672 offset += mips_abi_regsize (gdbarch);
2673 }
2674
2675 /* Check if the ra register was pushed on the stack. */
2676 offset = -4;
2677 if (entry_inst & 0x20)
2678 {
2679 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2680 offset -= mips_abi_regsize (gdbarch);
2681 }
2682
2683 /* Check if the s0 and s1 registers were pushed on the stack. */
2684 for (reg = 16; reg < sreg_count + 16; reg++)
2685 {
2686 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2687 offset -= mips_abi_regsize (gdbarch);
2688 }
2689 }
2690
2691 /* The SAVE instruction is similar to ENTRY, except that defined by the
2692 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2693 size of the frame is specified as an immediate field of instruction
2694 and an extended variation exists which lets additional registers and
2695 frame space to be specified. The instruction always treats registers
2696 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2697 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
2698 {
2699 static int args_table[16] = {
2700 0, 0, 0, 0, 1, 1, 1, 1,
2701 2, 2, 2, 0, 3, 3, 4, -1,
2702 };
2703 static int astatic_table[16] = {
2704 0, 1, 2, 3, 0, 1, 2, 3,
2705 0, 1, 2, 4, 0, 1, 0, -1,
2706 };
2707 int aregs = (save_inst >> 16) & 0xf;
2708 int xsregs = (save_inst >> 24) & 0x7;
2709 int args = args_table[aregs];
2710 int astatic = astatic_table[aregs];
2711 long frame_size;
2712
2713 if (args < 0)
2714 {
2715 warning (_("Invalid number of argument registers encoded in SAVE."));
2716 args = 0;
2717 }
2718 if (astatic < 0)
2719 {
2720 warning (_("Invalid number of static registers encoded in SAVE."));
2721 astatic = 0;
2722 }
2723
2724 /* For standard SAVE the frame size of 0 means 128. */
2725 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
2726 if (frame_size == 0 && (save_inst >> 16) == 0)
2727 frame_size = 16;
2728 frame_size *= 8;
2729 frame_offset += frame_size;
2730
2731 /* Now we can calculate what the SP must have been at the
2732 start of the function prologue. */
2733 sp += frame_offset;
2734
2735 /* Check if A0-A3 were saved in the caller's argument save area. */
2736 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
2737 {
2738 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2739 offset += mips_abi_regsize (gdbarch);
2740 }
2741
2742 offset = -4;
2743
2744 /* Check if the RA register was pushed on the stack. */
2745 if (save_inst & 0x40)
2746 {
2747 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
2748 offset -= mips_abi_regsize (gdbarch);
2749 }
2750
2751 /* Check if the S8 register was pushed on the stack. */
2752 if (xsregs > 6)
2753 {
2754 set_reg_offset (gdbarch, this_cache, 30, sp + offset);
2755 offset -= mips_abi_regsize (gdbarch);
2756 xsregs--;
2757 }
2758 /* Check if S2-S7 were pushed on the stack. */
2759 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
2760 {
2761 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2762 offset -= mips_abi_regsize (gdbarch);
2763 }
2764
2765 /* Check if the S1 register was pushed on the stack. */
2766 if (save_inst & 0x10)
2767 {
2768 set_reg_offset (gdbarch, this_cache, 17, sp + offset);
2769 offset -= mips_abi_regsize (gdbarch);
2770 }
2771 /* Check if the S0 register was pushed on the stack. */
2772 if (save_inst & 0x20)
2773 {
2774 set_reg_offset (gdbarch, this_cache, 16, sp + offset);
2775 offset -= mips_abi_regsize (gdbarch);
2776 }
2777
2778 /* Check if A0-A3 were pushed on the stack. */
2779 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
2780 {
2781 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
2782 offset -= mips_abi_regsize (gdbarch);
2783 }
2784 }
2785
2786 if (this_cache != NULL)
2787 {
2788 this_cache->base =
2789 (get_frame_register_signed (this_frame,
2790 gdbarch_num_regs (gdbarch) + frame_reg)
2791 + frame_offset - frame_adjust);
2792 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2793 be able to get rid of the assignment below, evetually. But it's
2794 still needed for now. */
2795 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2796 + mips_regnum (gdbarch)->pc]
2797 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
2798 }
2799
2800 /* Set end_prologue_addr to the address of the instruction immediately
2801 after the last one we scanned. Unless the last one looked like a
2802 non-prologue instruction (and we looked ahead), in which case use
2803 its address instead. */
2804 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot
2805 ? prev_pc : cur_pc - prev_extend_bytes);
2806
2807 return end_prologue_addr;
2808 }
2809
2810 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2811 Procedures that use the 32-bit instruction set are handled by the
2812 mips_insn32 unwinder. */
2813
2814 static struct mips_frame_cache *
2815 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
2816 {
2817 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2818 struct mips_frame_cache *cache;
2819
2820 if ((*this_cache) != NULL)
2821 return (*this_cache);
2822 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2823 (*this_cache) = cache;
2824 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2825
2826 /* Analyze the function prologue. */
2827 {
2828 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2829 CORE_ADDR start_addr;
2830
2831 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2832 if (start_addr == 0)
2833 start_addr = heuristic_proc_start (gdbarch, pc);
2834 /* We can't analyze the prologue if we couldn't find the begining
2835 of the function. */
2836 if (start_addr == 0)
2837 return cache;
2838
2839 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2840 }
2841
2842 /* gdbarch_sp_regnum contains the value and not the address. */
2843 trad_frame_set_value (cache->saved_regs,
2844 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2845 cache->base);
2846
2847 return (*this_cache);
2848 }
2849
2850 static void
2851 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
2852 struct frame_id *this_id)
2853 {
2854 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2855 this_cache);
2856 /* This marks the outermost frame. */
2857 if (info->base == 0)
2858 return;
2859 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2860 }
2861
2862 static struct value *
2863 mips_insn16_frame_prev_register (struct frame_info *this_frame,
2864 void **this_cache, int regnum)
2865 {
2866 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2867 this_cache);
2868 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2869 }
2870
2871 static int
2872 mips_insn16_frame_sniffer (const struct frame_unwind *self,
2873 struct frame_info *this_frame, void **this_cache)
2874 {
2875 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2876 CORE_ADDR pc = get_frame_pc (this_frame);
2877 if (mips_pc_is_mips16 (gdbarch, pc))
2878 return 1;
2879 return 0;
2880 }
2881
2882 static const struct frame_unwind mips_insn16_frame_unwind =
2883 {
2884 NORMAL_FRAME,
2885 default_frame_unwind_stop_reason,
2886 mips_insn16_frame_this_id,
2887 mips_insn16_frame_prev_register,
2888 NULL,
2889 mips_insn16_frame_sniffer
2890 };
2891
2892 static CORE_ADDR
2893 mips_insn16_frame_base_address (struct frame_info *this_frame,
2894 void **this_cache)
2895 {
2896 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
2897 this_cache);
2898 return info->base;
2899 }
2900
2901 static const struct frame_base mips_insn16_frame_base =
2902 {
2903 &mips_insn16_frame_unwind,
2904 mips_insn16_frame_base_address,
2905 mips_insn16_frame_base_address,
2906 mips_insn16_frame_base_address
2907 };
2908
2909 static const struct frame_base *
2910 mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
2911 {
2912 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2913 CORE_ADDR pc = get_frame_pc (this_frame);
2914 if (mips_pc_is_mips16 (gdbarch, pc))
2915 return &mips_insn16_frame_base;
2916 else
2917 return NULL;
2918 }
2919
2920 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2921 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2922 interpreted directly, and then multiplied by 4. */
2923
2924 static int
2925 micromips_decode_imm9 (int imm)
2926 {
2927 imm = (imm ^ 0x100) - 0x100;
2928 if (imm > -3 && imm < 2)
2929 imm ^= 0x100;
2930 return imm << 2;
2931 }
2932
2933 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2934 the address of the first instruction past the prologue. */
2935
2936 static CORE_ADDR
2937 micromips_scan_prologue (struct gdbarch *gdbarch,
2938 CORE_ADDR start_pc, CORE_ADDR limit_pc,
2939 struct frame_info *this_frame,
2940 struct mips_frame_cache *this_cache)
2941 {
2942 CORE_ADDR end_prologue_addr;
2943 int prev_non_prologue_insn = 0;
2944 int frame_reg = MIPS_SP_REGNUM;
2945 int this_non_prologue_insn;
2946 int non_prologue_insns = 0;
2947 long frame_offset = 0; /* Size of stack frame. */
2948 long frame_adjust = 0; /* Offset of FP from SP. */
2949 CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */
2950 int prev_delay_slot = 0;
2951 int in_delay_slot;
2952 CORE_ADDR prev_pc;
2953 CORE_ADDR cur_pc;
2954 ULONGEST insn; /* current instruction */
2955 CORE_ADDR sp;
2956 long offset;
2957 long sp_adj;
2958 long v1_off = 0; /* The assumption is LUI will replace it. */
2959 int reglist;
2960 int breg;
2961 int dreg;
2962 int sreg;
2963 int treg;
2964 int loc;
2965 int op;
2966 int s;
2967 int i;
2968
2969 /* Can be called when there's no process, and hence when there's no
2970 THIS_FRAME. */
2971 if (this_frame != NULL)
2972 sp = get_frame_register_signed (this_frame,
2973 gdbarch_num_regs (gdbarch)
2974 + MIPS_SP_REGNUM);
2975 else
2976 sp = 0;
2977
2978 if (limit_pc > start_pc + 200)
2979 limit_pc = start_pc + 200;
2980 prev_pc = start_pc;
2981
2982 /* Permit at most one non-prologue non-control-transfer instruction
2983 in the middle which may have been reordered by the compiler for
2984 optimisation. */
2985 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc)
2986 {
2987 this_non_prologue_insn = 0;
2988 in_delay_slot = 0;
2989 sp_adj = 0;
2990 loc = 0;
2991 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL);
2992 loc += MIPS_INSN16_SIZE;
2993 switch (mips_insn_size (ISA_MICROMIPS, insn))
2994 {
2995 /* 48-bit instructions. */
2996 case 3 * MIPS_INSN16_SIZE:
2997 /* No prologue instructions in this category. */
2998 this_non_prologue_insn = 1;
2999 loc += 2 * MIPS_INSN16_SIZE;
3000 break;
3001
3002 /* 32-bit instructions. */
3003 case 2 * MIPS_INSN16_SIZE:
3004 insn <<= 16;
3005 insn |= mips_fetch_instruction (gdbarch,
3006 ISA_MICROMIPS, cur_pc + loc, NULL);
3007 loc += MIPS_INSN16_SIZE;
3008 switch (micromips_op (insn >> 16))
3009 {
3010 /* Record $sp/$fp adjustment. */
3011 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3012 case 0x0: /* POOL32A: bits 000000 */
3013 case 0x16: /* POOL32S: bits 010110 */
3014 op = b0s11_op (insn);
3015 sreg = b0s5_reg (insn >> 16);
3016 treg = b5s5_reg (insn >> 16);
3017 dreg = b11s5_reg (insn);
3018 if (op == 0x1d0
3019 /* SUBU: bits 000000 00111010000 */
3020 /* DSUBU: bits 010110 00111010000 */
3021 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM
3022 && treg == 3)
3023 /* (D)SUBU $sp, $v1 */
3024 sp_adj = v1_off;
3025 else if (op != 0x150
3026 /* ADDU: bits 000000 00101010000 */
3027 /* DADDU: bits 010110 00101010000 */
3028 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM)
3029 this_non_prologue_insn = 1;
3030 break;
3031
3032 case 0x8: /* POOL32B: bits 001000 */
3033 op = b12s4_op (insn);
3034 breg = b0s5_reg (insn >> 16);
3035 reglist = sreg = b5s5_reg (insn >> 16);
3036 offset = (b0s12_imm (insn) ^ 0x800) - 0x800;
3037 if ((op == 0x9 || op == 0xc)
3038 /* SWP: bits 001000 1001 */
3039 /* SDP: bits 001000 1100 */
3040 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM)
3041 /* S[DW]P reg,offset($sp) */
3042 {
3043 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4);
3044 set_reg_offset (gdbarch, this_cache,
3045 sreg, sp + offset);
3046 set_reg_offset (gdbarch, this_cache,
3047 sreg + 1, sp + offset + s);
3048 }
3049 else if ((op == 0xd || op == 0xf)
3050 /* SWM: bits 001000 1101 */
3051 /* SDM: bits 001000 1111 */
3052 && breg == MIPS_SP_REGNUM
3053 /* SWM reglist,offset($sp) */
3054 && ((reglist >= 1 && reglist <= 9)
3055 || (reglist >= 16 && reglist <= 25)))
3056 {
3057 int sreglist = min(reglist & 0xf, 8);
3058
3059 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2);
3060 for (i = 0; i < sreglist; i++)
3061 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i);
3062 if ((reglist & 0xf) > 8)
3063 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++);
3064 if ((reglist & 0x10) == 0x10)
3065 set_reg_offset (gdbarch, this_cache,
3066 MIPS_RA_REGNUM, sp + s * i++);
3067 }
3068 else
3069 this_non_prologue_insn = 1;
3070 break;
3071
3072 /* Record $sp/$fp adjustment. */
3073 /* Discard (D)ADDIU $gp used for PIC code. */
3074 case 0xc: /* ADDIU: bits 001100 */
3075 case 0x17: /* DADDIU: bits 010111 */
3076 sreg = b0s5_reg (insn >> 16);
3077 dreg = b5s5_reg (insn >> 16);
3078 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3079 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM)
3080 /* (D)ADDIU $sp, imm */
3081 sp_adj = offset;
3082 else if (sreg == MIPS_SP_REGNUM && dreg == 30)
3083 /* (D)ADDIU $fp, $sp, imm */
3084 {
3085 frame_addr = sp + offset;
3086 frame_adjust = offset;
3087 frame_reg = 30;
3088 }
3089 else if (sreg != 28 || dreg != 28)
3090 /* (D)ADDIU $gp, imm */
3091 this_non_prologue_insn = 1;
3092 break;
3093
3094 /* LUI $v1 is used for larger $sp adjustments. */
3095 /* Discard LUI $gp used for PIC code. */
3096 case 0x10: /* POOL32I: bits 010000 */
3097 if (b5s5_op (insn >> 16) == 0xd
3098 /* LUI: bits 010000 001101 */
3099 && b0s5_reg (insn >> 16) == 3)
3100 /* LUI $v1, imm */
3101 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000;
3102 else if (b5s5_op (insn >> 16) != 0xd
3103 /* LUI: bits 010000 001101 */
3104 || b0s5_reg (insn >> 16) != 28)
3105 /* LUI $gp, imm */
3106 this_non_prologue_insn = 1;
3107 break;
3108
3109 /* ORI $v1 is used for larger $sp adjustments. */
3110 case 0x14: /* ORI: bits 010100 */
3111 sreg = b0s5_reg (insn >> 16);
3112 dreg = b5s5_reg (insn >> 16);
3113 if (sreg == 3 && dreg == 3)
3114 /* ORI $v1, imm */
3115 v1_off |= b0s16_imm (insn);
3116 else
3117 this_non_prologue_insn = 1;
3118 break;
3119
3120 case 0x26: /* SWC1: bits 100110 */
3121 case 0x2e: /* SDC1: bits 101110 */
3122 breg = b0s5_reg (insn >> 16);
3123 if (breg != MIPS_SP_REGNUM)
3124 /* S[DW]C1 reg,offset($sp) */
3125 this_non_prologue_insn = 1;
3126 break;
3127
3128 case 0x36: /* SD: bits 110110 */
3129 case 0x3e: /* SW: bits 111110 */
3130 breg = b0s5_reg (insn >> 16);
3131 sreg = b5s5_reg (insn >> 16);
3132 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
3133 if (breg == MIPS_SP_REGNUM)
3134 /* S[DW] reg,offset($sp) */
3135 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3136 else
3137 this_non_prologue_insn = 1;
3138 break;
3139
3140 default:
3141 /* The instruction in the delay slot can be a part
3142 of the prologue, so move forward once more. */
3143 if (micromips_instruction_has_delay_slot (insn, 0))
3144 in_delay_slot = 1;
3145 else
3146 this_non_prologue_insn = 1;
3147 break;
3148 }
3149 insn >>= 16;
3150 break;
3151
3152 /* 16-bit instructions. */
3153 case MIPS_INSN16_SIZE:
3154 switch (micromips_op (insn))
3155 {
3156 case 0x3: /* MOVE: bits 000011 */
3157 sreg = b0s5_reg (insn);
3158 dreg = b5s5_reg (insn);
3159 if (sreg == MIPS_SP_REGNUM && dreg == 30)
3160 /* MOVE $fp, $sp */
3161 {
3162 frame_addr = sp;
3163 frame_reg = 30;
3164 }
3165 else if ((sreg & 0x1c) != 0x4)
3166 /* MOVE reg, $a0-$a3 */
3167 this_non_prologue_insn = 1;
3168 break;
3169
3170 case 0x11: /* POOL16C: bits 010001 */
3171 if (b6s4_op (insn) == 0x5)
3172 /* SWM: bits 010001 0101 */
3173 {
3174 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20;
3175 reglist = b4s2_regl (insn);
3176 for (i = 0; i <= reglist; i++)
3177 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i);
3178 set_reg_offset (gdbarch, this_cache,
3179 MIPS_RA_REGNUM, sp + 4 * i++);
3180 }
3181 else
3182 this_non_prologue_insn = 1;
3183 break;
3184
3185 case 0x13: /* POOL16D: bits 010011 */
3186 if ((insn & 0x1) == 0x1)
3187 /* ADDIUSP: bits 010011 1 */
3188 sp_adj = micromips_decode_imm9 (b1s9_imm (insn));
3189 else if (b5s5_reg (insn) == MIPS_SP_REGNUM)
3190 /* ADDIUS5: bits 010011 0 */
3191 /* ADDIUS5 $sp, imm */
3192 sp_adj = (b1s4_imm (insn) ^ 8) - 8;
3193 else
3194 this_non_prologue_insn = 1;
3195 break;
3196
3197 case 0x32: /* SWSP: bits 110010 */
3198 offset = b0s5_imm (insn) << 2;
3199 sreg = b5s5_reg (insn);
3200 set_reg_offset (gdbarch, this_cache, sreg, sp + offset);
3201 break;
3202
3203 default:
3204 /* The instruction in the delay slot can be a part
3205 of the prologue, so move forward once more. */
3206 if (micromips_instruction_has_delay_slot (insn << 16, 0))
3207 in_delay_slot = 1;
3208 else
3209 this_non_prologue_insn = 1;
3210 break;
3211 }
3212 break;
3213 }
3214 if (sp_adj < 0)
3215 frame_offset -= sp_adj;
3216
3217 non_prologue_insns += this_non_prologue_insn;
3218
3219 /* A jump or branch, enough non-prologue insns seen or positive
3220 stack adjustment? If so, then we must have reached the end
3221 of the prologue by now. */
3222 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0
3223 || micromips_instruction_is_compact_branch (insn))
3224 break;
3225
3226 prev_non_prologue_insn = this_non_prologue_insn;
3227 prev_delay_slot = in_delay_slot;
3228 prev_pc = cur_pc;
3229 }
3230
3231 if (this_cache != NULL)
3232 {
3233 this_cache->base =
3234 (get_frame_register_signed (this_frame,
3235 gdbarch_num_regs (gdbarch) + frame_reg)
3236 + frame_offset - frame_adjust);
3237 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3238 be able to get rid of the assignment below, evetually. But it's
3239 still needed for now. */
3240 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3241 + mips_regnum (gdbarch)->pc]
3242 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
3243 }
3244
3245 /* Set end_prologue_addr to the address of the instruction immediately
3246 after the last one we scanned. Unless the last one looked like a
3247 non-prologue instruction (and we looked ahead), in which case use
3248 its address instead. */
3249 end_prologue_addr
3250 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3251
3252 return end_prologue_addr;
3253 }
3254
3255 /* Heuristic unwinder for procedures using microMIPS instructions.
3256 Procedures that use the 32-bit instruction set are handled by the
3257 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3258
3259 static struct mips_frame_cache *
3260 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
3261 {
3262 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3263 struct mips_frame_cache *cache;
3264
3265 if ((*this_cache) != NULL)
3266 return (*this_cache);
3267
3268 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3269 (*this_cache) = cache;
3270 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3271
3272 /* Analyze the function prologue. */
3273 {
3274 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3275 CORE_ADDR start_addr;
3276
3277 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3278 if (start_addr == 0)
3279 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc);
3280 /* We can't analyze the prologue if we couldn't find the begining
3281 of the function. */
3282 if (start_addr == 0)
3283 return cache;
3284
3285 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3286 }
3287
3288 /* gdbarch_sp_regnum contains the value and not the address. */
3289 trad_frame_set_value (cache->saved_regs,
3290 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3291 cache->base);
3292
3293 return (*this_cache);
3294 }
3295
3296 static void
3297 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
3298 struct frame_id *this_id)
3299 {
3300 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3301 this_cache);
3302 /* This marks the outermost frame. */
3303 if (info->base == 0)
3304 return;
3305 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3306 }
3307
3308 static struct value *
3309 mips_micro_frame_prev_register (struct frame_info *this_frame,
3310 void **this_cache, int regnum)
3311 {
3312 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3313 this_cache);
3314 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3315 }
3316
3317 static int
3318 mips_micro_frame_sniffer (const struct frame_unwind *self,
3319 struct frame_info *this_frame, void **this_cache)
3320 {
3321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3322 CORE_ADDR pc = get_frame_pc (this_frame);
3323
3324 if (mips_pc_is_micromips (gdbarch, pc))
3325 return 1;
3326 return 0;
3327 }
3328
3329 static const struct frame_unwind mips_micro_frame_unwind =
3330 {
3331 NORMAL_FRAME,
3332 default_frame_unwind_stop_reason,
3333 mips_micro_frame_this_id,
3334 mips_micro_frame_prev_register,
3335 NULL,
3336 mips_micro_frame_sniffer
3337 };
3338
3339 static CORE_ADDR
3340 mips_micro_frame_base_address (struct frame_info *this_frame,
3341 void **this_cache)
3342 {
3343 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
3344 this_cache);
3345 return info->base;
3346 }
3347
3348 static const struct frame_base mips_micro_frame_base =
3349 {
3350 &mips_micro_frame_unwind,
3351 mips_micro_frame_base_address,
3352 mips_micro_frame_base_address,
3353 mips_micro_frame_base_address
3354 };
3355
3356 static const struct frame_base *
3357 mips_micro_frame_base_sniffer (struct frame_info *this_frame)
3358 {
3359 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3360 CORE_ADDR pc = get_frame_pc (this_frame);
3361
3362 if (mips_pc_is_micromips (gdbarch, pc))
3363 return &mips_micro_frame_base;
3364 else
3365 return NULL;
3366 }
3367
3368 /* Mark all the registers as unset in the saved_regs array
3369 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3370
3371 static void
3372 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
3373 {
3374 if (this_cache == NULL || this_cache->saved_regs == NULL)
3375 return;
3376
3377 {
3378 const int num_regs = gdbarch_num_regs (gdbarch);
3379 int i;
3380
3381 for (i = 0; i < num_regs; i++)
3382 {
3383 this_cache->saved_regs[i].addr = -1;
3384 }
3385 }
3386 }
3387
3388 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3389 the associated FRAME_CACHE if not null.
3390 Return the address of the first instruction past the prologue. */
3391
3392 static CORE_ADDR
3393 mips32_scan_prologue (struct gdbarch *gdbarch,
3394 CORE_ADDR start_pc, CORE_ADDR limit_pc,
3395 struct frame_info *this_frame,
3396 struct mips_frame_cache *this_cache)
3397 {
3398 int prev_non_prologue_insn;
3399 int this_non_prologue_insn;
3400 int non_prologue_insns;
3401 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for
3402 frame-pointer. */
3403 int prev_delay_slot;
3404 CORE_ADDR prev_pc;
3405 CORE_ADDR cur_pc;
3406 CORE_ADDR sp;
3407 long frame_offset;
3408 int frame_reg = MIPS_SP_REGNUM;
3409
3410 CORE_ADDR end_prologue_addr;
3411 int seen_sp_adjust = 0;
3412 int load_immediate_bytes = 0;
3413 int in_delay_slot;
3414 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
3415
3416 /* Can be called when there's no process, and hence when there's no
3417 THIS_FRAME. */
3418 if (this_frame != NULL)
3419 sp = get_frame_register_signed (this_frame,
3420 gdbarch_num_regs (gdbarch)
3421 + MIPS_SP_REGNUM);
3422 else
3423 sp = 0;
3424
3425 if (limit_pc > start_pc + 200)
3426 limit_pc = start_pc + 200;
3427
3428 restart:
3429 prev_non_prologue_insn = 0;
3430 non_prologue_insns = 0;
3431 prev_delay_slot = 0;
3432 prev_pc = start_pc;
3433
3434 /* Permit at most one non-prologue non-control-transfer instruction
3435 in the middle which may have been reordered by the compiler for
3436 optimisation. */
3437 frame_offset = 0;
3438 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
3439 {
3440 unsigned long inst, high_word;
3441 long offset;
3442 int reg;
3443
3444 this_non_prologue_insn = 0;
3445 in_delay_slot = 0;
3446
3447 /* Fetch the instruction. */
3448 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS,
3449 cur_pc, NULL);
3450
3451 /* Save some code by pre-extracting some useful fields. */
3452 high_word = (inst >> 16) & 0xffff;
3453 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000;
3454 reg = high_word & 0x1f;
3455
3456 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
3457 || high_word == 0x23bd /* addi $sp,$sp,-i */
3458 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
3459 {
3460 if (offset < 0) /* Negative stack adjustment? */
3461 frame_offset -= offset;
3462 else
3463 /* Exit loop if a positive stack adjustment is found, which
3464 usually means that the stack cleanup code in the function
3465 epilogue is reached. */
3466 break;
3467 seen_sp_adjust = 1;
3468 }
3469 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3470 && !regsize_is_64_bits)
3471 {
3472 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3473 }
3474 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3475 && regsize_is_64_bits)
3476 {
3477 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3478 set_reg_offset (gdbarch, this_cache, reg, sp + offset);
3479 }
3480 else if (high_word == 0x27be) /* addiu $30,$sp,size */
3481 {
3482 /* Old gcc frame, r30 is virtual frame pointer. */
3483 if (offset != frame_offset)
3484 frame_addr = sp + offset;
3485 else if (this_frame && frame_reg == MIPS_SP_REGNUM)
3486 {
3487 unsigned alloca_adjust;
3488
3489 frame_reg = 30;
3490 frame_addr = get_frame_register_signed
3491 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3492 frame_offset = 0;
3493
3494 alloca_adjust = (unsigned) (frame_addr - (sp + offset));
3495 if (alloca_adjust > 0)
3496 {
3497 /* FP > SP + frame_size. This may be because of
3498 an alloca or somethings similar. Fix sp to
3499 "pre-alloca" value, and try again. */
3500 sp += alloca_adjust;
3501 /* Need to reset the status of all registers. Otherwise,
3502 we will hit a guard that prevents the new address
3503 for each register to be recomputed during the second
3504 pass. */
3505 reset_saved_regs (gdbarch, this_cache);
3506 goto restart;
3507 }
3508 }
3509 }
3510 /* move $30,$sp. With different versions of gas this will be either
3511 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3512 Accept any one of these. */
3513 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
3514 {
3515 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3516 if (this_frame && frame_reg == MIPS_SP_REGNUM)
3517 {
3518 unsigned alloca_adjust;
3519
3520 frame_reg = 30;
3521 frame_addr = get_frame_register_signed
3522 (this_frame, gdbarch_num_regs (gdbarch) + 30);
3523
3524 alloca_adjust = (unsigned) (frame_addr - sp);
3525 if (alloca_adjust > 0)
3526 {
3527 /* FP > SP + frame_size. This may be because of
3528 an alloca or somethings similar. Fix sp to
3529 "pre-alloca" value, and try again. */
3530 sp = frame_addr;
3531 /* Need to reset the status of all registers. Otherwise,
3532 we will hit a guard that prevents the new address
3533 for each register to be recomputed during the second
3534 pass. */
3535 reset_saved_regs (gdbarch, this_cache);
3536 goto restart;
3537 }
3538 }
3539 }
3540 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3541 && !regsize_is_64_bits)
3542 {
3543 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
3544 }
3545 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3546 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3547 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3548 || high_word == 0x3c1c /* lui $gp,n */
3549 || high_word == 0x279c /* addiu $gp,$gp,n */
3550 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
3551 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
3552 )
3553 {
3554 /* These instructions are part of the prologue, but we don't
3555 need to do anything special to handle them. */
3556 }
3557 /* The instructions below load $at or $t0 with an immediate
3558 value in preparation for a stack adjustment via
3559 subu $sp,$sp,[$at,$t0]. These instructions could also
3560 initialize a local variable, so we accept them only before
3561 a stack adjustment instruction was seen. */
3562 else if (!seen_sp_adjust
3563 && !prev_delay_slot
3564 && (high_word == 0x3c01 /* lui $at,n */
3565 || high_word == 0x3c08 /* lui $t0,n */
3566 || high_word == 0x3421 /* ori $at,$at,n */
3567 || high_word == 0x3508 /* ori $t0,$t0,n */
3568 || high_word == 0x3401 /* ori $at,$zero,n */
3569 || high_word == 0x3408 /* ori $t0,$zero,n */
3570 ))
3571 {
3572 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
3573 }
3574 /* Check for branches and jumps. The instruction in the delay
3575 slot can be a part of the prologue, so move forward once more. */
3576 else if (mips32_instruction_has_delay_slot (gdbarch, inst))
3577 {
3578 in_delay_slot = 1;
3579 }
3580 /* This instruction is not an instruction typically found
3581 in a prologue, so we must have reached the end of the
3582 prologue. */
3583 else
3584 {
3585 this_non_prologue_insn = 1;
3586 }
3587
3588 non_prologue_insns += this_non_prologue_insn;
3589
3590 /* A jump or branch, or enough non-prologue insns seen? If so,
3591 then we must have reached the end of the prologue by now. */
3592 if (prev_delay_slot || non_prologue_insns > 1)
3593 break;
3594
3595 prev_non_prologue_insn = this_non_prologue_insn;
3596 prev_delay_slot = in_delay_slot;
3597 prev_pc = cur_pc;
3598 }
3599
3600 if (this_cache != NULL)
3601 {
3602 this_cache->base =
3603 (get_frame_register_signed (this_frame,
3604 gdbarch_num_regs (gdbarch) + frame_reg)
3605 + frame_offset);
3606 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3607 this assignment below, eventually. But it's still needed
3608 for now. */
3609 this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3610 + mips_regnum (gdbarch)->pc]
3611 = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
3612 + MIPS_RA_REGNUM];
3613 }
3614
3615 /* Set end_prologue_addr to the address of the instruction immediately
3616 after the last one we scanned. Unless the last one looked like a
3617 non-prologue instruction (and we looked ahead), in which case use
3618 its address instead. */
3619 end_prologue_addr
3620 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc;
3621
3622 /* In a frameless function, we might have incorrectly
3623 skipped some load immediate instructions. Undo the skipping
3624 if the load immediate was not followed by a stack adjustment. */
3625 if (load_immediate_bytes && !seen_sp_adjust)
3626 end_prologue_addr -= load_immediate_bytes;
3627
3628 return end_prologue_addr;
3629 }
3630
3631 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3632 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3633 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3634 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3635
3636 static struct mips_frame_cache *
3637 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
3638 {
3639 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3640 struct mips_frame_cache *cache;
3641
3642 if ((*this_cache) != NULL)
3643 return (*this_cache);
3644
3645 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
3646 (*this_cache) = cache;
3647 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3648
3649 /* Analyze the function prologue. */
3650 {
3651 const CORE_ADDR pc = get_frame_address_in_block (this_frame);
3652 CORE_ADDR start_addr;
3653
3654 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3655 if (start_addr == 0)
3656 start_addr = heuristic_proc_start (gdbarch, pc);
3657 /* We can't analyze the prologue if we couldn't find the begining
3658 of the function. */
3659 if (start_addr == 0)
3660 return cache;
3661
3662 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
3663 }
3664
3665 /* gdbarch_sp_regnum contains the value and not the address. */
3666 trad_frame_set_value (cache->saved_regs,
3667 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
3668 cache->base);
3669
3670 return (*this_cache);
3671 }
3672
3673 static void
3674 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
3675 struct frame_id *this_id)
3676 {
3677 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3678 this_cache);
3679 /* This marks the outermost frame. */
3680 if (info->base == 0)
3681 return;
3682 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3683 }
3684
3685 static struct value *
3686 mips_insn32_frame_prev_register (struct frame_info *this_frame,
3687 void **this_cache, int regnum)
3688 {
3689 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3690 this_cache);
3691 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3692 }
3693
3694 static int
3695 mips_insn32_frame_sniffer (const struct frame_unwind *self,
3696 struct frame_info *this_frame, void **this_cache)
3697 {
3698 CORE_ADDR pc = get_frame_pc (this_frame);
3699 if (mips_pc_is_mips (pc))
3700 return 1;
3701 return 0;
3702 }
3703
3704 static const struct frame_unwind mips_insn32_frame_unwind =
3705 {
3706 NORMAL_FRAME,
3707 default_frame_unwind_stop_reason,
3708 mips_insn32_frame_this_id,
3709 mips_insn32_frame_prev_register,
3710 NULL,
3711 mips_insn32_frame_sniffer
3712 };
3713
3714 static CORE_ADDR
3715 mips_insn32_frame_base_address (struct frame_info *this_frame,
3716 void **this_cache)
3717 {
3718 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
3719 this_cache);
3720 return info->base;
3721 }
3722
3723 static const struct frame_base mips_insn32_frame_base =
3724 {
3725 &mips_insn32_frame_unwind,
3726 mips_insn32_frame_base_address,
3727 mips_insn32_frame_base_address,
3728 mips_insn32_frame_base_address
3729 };
3730
3731 static const struct frame_base *
3732 mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
3733 {
3734 CORE_ADDR pc = get_frame_pc (this_frame);
3735 if (mips_pc_is_mips (pc))
3736 return &mips_insn32_frame_base;
3737 else
3738 return NULL;
3739 }
3740
3741 static struct trad_frame_cache *
3742 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
3743 {
3744 CORE_ADDR pc;
3745 CORE_ADDR start_addr;
3746 CORE_ADDR stack_addr;
3747 struct trad_frame_cache *this_trad_cache;
3748 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3749 int num_regs = gdbarch_num_regs (gdbarch);
3750
3751 if ((*this_cache) != NULL)
3752 return (*this_cache);
3753 this_trad_cache = trad_frame_cache_zalloc (this_frame);
3754 (*this_cache) = this_trad_cache;
3755
3756 /* The return address is in the link register. */
3757 trad_frame_set_reg_realreg (this_trad_cache,
3758 gdbarch_pc_regnum (gdbarch),
3759 num_regs + MIPS_RA_REGNUM);
3760
3761 /* Frame ID, since it's a frameless / stackless function, no stack
3762 space is allocated and SP on entry is the current SP. */
3763 pc = get_frame_pc (this_frame);
3764 find_pc_partial_function (pc, NULL, &start_addr, NULL);
3765 stack_addr = get_frame_register_signed (this_frame,
3766 num_regs + MIPS_SP_REGNUM);
3767 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
3768
3769 /* Assume that the frame's base is the same as the
3770 stack-pointer. */
3771 trad_frame_set_this_base (this_trad_cache, stack_addr);
3772
3773 return this_trad_cache;
3774 }
3775
3776 static void
3777 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
3778 struct frame_id *this_id)
3779 {
3780 struct trad_frame_cache *this_trad_cache
3781 = mips_stub_frame_cache (this_frame, this_cache);
3782 trad_frame_get_id (this_trad_cache, this_id);
3783 }
3784
3785 static struct value *
3786 mips_stub_frame_prev_register (struct frame_info *this_frame,
3787 void **this_cache, int regnum)
3788 {
3789 struct trad_frame_cache *this_trad_cache
3790 = mips_stub_frame_cache (this_frame, this_cache);
3791 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
3792 }
3793
3794 static int
3795 mips_stub_frame_sniffer (const struct frame_unwind *self,
3796 struct frame_info *this_frame, void **this_cache)
3797 {
3798 gdb_byte dummy[4];
3799 struct obj_section *s;
3800 CORE_ADDR pc = get_frame_address_in_block (this_frame);
3801 struct bound_minimal_symbol msym;
3802
3803 /* Use the stub unwinder for unreadable code. */
3804 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
3805 return 1;
3806
3807 if (in_plt_section (pc) || in_mips_stubs_section (pc))
3808 return 1;
3809
3810 /* Calling a PIC function from a non-PIC function passes through a
3811 stub. The stub for foo is named ".pic.foo". */
3812 msym = lookup_minimal_symbol_by_pc (pc);
3813 if (msym.minsym != NULL
3814 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL
3815 && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
3816 return 1;
3817
3818 return 0;
3819 }
3820
3821 static const struct frame_unwind mips_stub_frame_unwind =
3822 {
3823 NORMAL_FRAME,
3824 default_frame_unwind_stop_reason,
3825 mips_stub_frame_this_id,
3826 mips_stub_frame_prev_register,
3827 NULL,
3828 mips_stub_frame_sniffer
3829 };
3830
3831 static CORE_ADDR
3832 mips_stub_frame_base_address (struct frame_info *this_frame,
3833 void **this_cache)
3834 {
3835 struct trad_frame_cache *this_trad_cache
3836 = mips_stub_frame_cache (this_frame, this_cache);
3837 return trad_frame_get_this_base (this_trad_cache);
3838 }
3839
3840 static const struct frame_base mips_stub_frame_base =
3841 {
3842 &mips_stub_frame_unwind,
3843 mips_stub_frame_base_address,
3844 mips_stub_frame_base_address,
3845 mips_stub_frame_base_address
3846 };
3847
3848 static const struct frame_base *
3849 mips_stub_frame_base_sniffer (struct frame_info *this_frame)
3850 {
3851 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
3852 return &mips_stub_frame_base;
3853 else
3854 return NULL;
3855 }
3856
3857 /* mips_addr_bits_remove - remove useless address bits */
3858
3859 static CORE_ADDR
3860 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
3861 {
3862 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3863
3864 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
3865 /* This hack is a work-around for existing boards using PMON, the
3866 simulator, and any other 64-bit targets that doesn't have true
3867 64-bit addressing. On these targets, the upper 32 bits of
3868 addresses are ignored by the hardware. Thus, the PC or SP are
3869 likely to have been sign extended to all 1s by instruction
3870 sequences that load 32-bit addresses. For example, a typical
3871 piece of code that loads an address is this:
3872
3873 lui $r2, <upper 16 bits>
3874 ori $r2, <lower 16 bits>
3875
3876 But the lui sign-extends the value such that the upper 32 bits
3877 may be all 1s. The workaround is simply to mask off these
3878 bits. In the future, gcc may be changed to support true 64-bit
3879 addressing, and this masking will have to be disabled. */
3880 return addr &= 0xffffffffUL;
3881 else
3882 return addr;
3883 }
3884
3885
3886 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3887 instruction and ending with a SC/SCD instruction. If such a sequence
3888 is found, attempt to step through it. A breakpoint is placed at the end of
3889 the sequence. */
3890
3891 /* Instructions used during single-stepping of atomic sequences, standard
3892 ISA version. */
3893 #define LL_OPCODE 0x30
3894 #define LLD_OPCODE 0x34
3895 #define SC_OPCODE 0x38
3896 #define SCD_OPCODE 0x3c
3897
3898 static int
3899 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3900 struct address_space *aspace, CORE_ADDR pc)
3901 {
3902 CORE_ADDR breaks[2] = {-1, -1};
3903 CORE_ADDR loc = pc;
3904 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
3905 ULONGEST insn;
3906 int insn_count;
3907 int index;
3908 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
3909 const int atomic_sequence_length = 16; /* Instruction sequence length. */
3910
3911 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3912 /* Assume all atomic sequences start with a ll/lld instruction. */
3913 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
3914 return 0;
3915
3916 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3917 instructions. */
3918 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
3919 {
3920 int is_branch = 0;
3921 loc += MIPS_INSN32_SIZE;
3922 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
3923
3924 /* Assume that there is at most one branch in the atomic
3925 sequence. If a branch is found, put a breakpoint in its
3926 destination address. */
3927 switch (itype_op (insn))
3928 {
3929 case 0: /* SPECIAL */
3930 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
3931 return 0; /* fallback to the standard single-step code. */
3932 break;
3933 case 1: /* REGIMM */
3934 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
3935 || ((itype_rt (insn) & 0x1e) == 0
3936 && itype_rs (insn) == 0)); /* BPOSGE* */
3937 break;
3938 case 2: /* J */
3939 case 3: /* JAL */
3940 return 0; /* fallback to the standard single-step code. */
3941 case 4: /* BEQ */
3942 case 5: /* BNE */
3943 case 6: /* BLEZ */
3944 case 7: /* BGTZ */
3945 case 20: /* BEQL */
3946 case 21: /* BNEL */
3947 case 22: /* BLEZL */
3948 case 23: /* BGTTL */
3949 is_branch = 1;
3950 break;
3951 case 17: /* COP1 */
3952 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10)
3953 && (itype_rt (insn) & 0x2) == 0);
3954 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3955 break;
3956 /* Fall through. */
3957 case 18: /* COP2 */
3958 case 19: /* COP3 */
3959 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3960 break;
3961 }
3962 if (is_branch)
3963 {
3964 branch_bp = loc + mips32_relative_offset (insn) + 4;
3965 if (last_breakpoint >= 1)
3966 return 0; /* More than one branch found, fallback to the
3967 standard single-step code. */
3968 breaks[1] = branch_bp;
3969 last_breakpoint++;
3970 }
3971
3972 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
3973 break;
3974 }
3975
3976 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3977 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
3978 return 0;
3979
3980 loc += MIPS_INSN32_SIZE;
3981
3982 /* Insert a breakpoint right after the end of the atomic sequence. */
3983 breaks[0] = loc;
3984
3985 /* Check for duplicated breakpoints. Check also for a breakpoint
3986 placed (branch instruction's destination) in the atomic sequence. */
3987 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
3988 last_breakpoint = 0;
3989
3990 /* Effectively inserts the breakpoints. */
3991 for (index = 0; index <= last_breakpoint; index++)
3992 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
3993
3994 return 1;
3995 }
3996
3997 static int
3998 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
3999 struct address_space *aspace,
4000 CORE_ADDR pc)
4001 {
4002 const int atomic_sequence_length = 16; /* Instruction sequence length. */
4003 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
4004 CORE_ADDR breaks[2] = {-1, -1};
4005 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
4006 destination. */
4007 CORE_ADDR loc = pc;
4008 int sc_found = 0;
4009 ULONGEST insn;
4010 int insn_count;
4011 int index;
4012
4013 /* Assume all atomic sequences start with a ll/lld instruction. */
4014 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4015 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
4016 return 0;
4017 loc += MIPS_INSN16_SIZE;
4018 insn <<= 16;
4019 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4020 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4021 return 0;
4022 loc += MIPS_INSN16_SIZE;
4023
4024 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4025 that no atomic sequence is longer than "atomic_sequence_length"
4026 instructions. */
4027 for (insn_count = 0;
4028 !sc_found && insn_count < atomic_sequence_length;
4029 ++insn_count)
4030 {
4031 int is_branch = 0;
4032
4033 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
4034 loc += MIPS_INSN16_SIZE;
4035
4036 /* Assume that there is at most one conditional branch in the
4037 atomic sequence. If a branch is found, put a breakpoint in
4038 its destination address. */
4039 switch (mips_insn_size (ISA_MICROMIPS, insn))
4040 {
4041 /* 48-bit instructions. */
4042 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
4043 loc += 2 * MIPS_INSN16_SIZE;
4044 break;
4045
4046 /* 32-bit instructions. */
4047 case 2 * MIPS_INSN16_SIZE:
4048 switch (micromips_op (insn))
4049 {
4050 case 0x10: /* POOL32I: bits 010000 */
4051 if ((b5s5_op (insn) & 0x18) != 0x0
4052 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4053 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4054 && (b5s5_op (insn) & 0x1d) != 0x11
4055 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4056 && ((b5s5_op (insn) & 0x1e) != 0x14
4057 || (insn & 0x3) != 0x0)
4058 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4059 && (b5s5_op (insn) & 0x1e) != 0x1a
4060 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4061 && ((b5s5_op (insn) & 0x1e) != 0x1c
4062 || (insn & 0x3) != 0x0)
4063 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4064 && ((b5s5_op (insn) & 0x1c) != 0x1c
4065 || (insn & 0x3) != 0x1))
4066 /* BC1ANY*: bits 010000 111xx xxx01 */
4067 break;
4068 /* Fall through. */
4069
4070 case 0x25: /* BEQ: bits 100101 */
4071 case 0x2d: /* BNE: bits 101101 */
4072 insn <<= 16;
4073 insn |= mips_fetch_instruction (gdbarch,
4074 ISA_MICROMIPS, loc, NULL);
4075 branch_bp = (loc + MIPS_INSN16_SIZE
4076 + micromips_relative_offset16 (insn));
4077 is_branch = 1;
4078 break;
4079
4080 case 0x00: /* POOL32A: bits 000000 */
4081 insn <<= 16;
4082 insn |= mips_fetch_instruction (gdbarch,
4083 ISA_MICROMIPS, loc, NULL);
4084 if (b0s6_op (insn) != 0x3c
4085 /* POOL32Axf: bits 000000 ... 111100 */
4086 || (b6s10_ext (insn) & 0x2bf) != 0x3c)
4087 /* JALR, JALR.HB: 000000 000x111100 111100 */
4088 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4089 break;
4090 /* Fall through. */
4091
4092 case 0x1d: /* JALS: bits 011101 */
4093 case 0x35: /* J: bits 110101 */
4094 case 0x3d: /* JAL: bits 111101 */
4095 case 0x3c: /* JALX: bits 111100 */
4096 return 0; /* Fall back to the standard single-step code. */
4097
4098 case 0x18: /* POOL32C: bits 011000 */
4099 if ((b12s4_op (insn) & 0xb) == 0xb)
4100 /* SC, SCD: bits 011000 1x11 */
4101 sc_found = 1;
4102 break;
4103 }
4104 loc += MIPS_INSN16_SIZE;
4105 break;
4106
4107 /* 16-bit instructions. */
4108 case MIPS_INSN16_SIZE:
4109 switch (micromips_op (insn))
4110 {
4111 case 0x23: /* BEQZ16: bits 100011 */
4112 case 0x2b: /* BNEZ16: bits 101011 */
4113 branch_bp = loc + micromips_relative_offset7 (insn);
4114 is_branch = 1;
4115 break;
4116
4117 case 0x11: /* POOL16C: bits 010001 */
4118 if ((b5s5_op (insn) & 0x1c) != 0xc
4119 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4120 && b5s5_op (insn) != 0x18)
4121 /* JRADDIUSP: bits 010001 11000 */
4122 break;
4123 return 0; /* Fall back to the standard single-step code. */
4124
4125 case 0x33: /* B16: bits 110011 */
4126 return 0; /* Fall back to the standard single-step code. */
4127 }
4128 break;
4129 }
4130 if (is_branch)
4131 {
4132 if (last_breakpoint >= 1)
4133 return 0; /* More than one branch found, fallback to the
4134 standard single-step code. */
4135 breaks[1] = branch_bp;
4136 last_breakpoint++;
4137 }
4138 }
4139 if (!sc_found)
4140 return 0;
4141
4142 /* Insert a breakpoint right after the end of the atomic sequence. */
4143 breaks[0] = loc;
4144
4145 /* Check for duplicated breakpoints. Check also for a breakpoint
4146 placed (branch instruction's destination) in the atomic sequence */
4147 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
4148 last_breakpoint = 0;
4149
4150 /* Effectively inserts the breakpoints. */
4151 for (index = 0; index <= last_breakpoint; index++)
4152 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
4153
4154 return 1;
4155 }
4156
4157 static int
4158 deal_with_atomic_sequence (struct gdbarch *gdbarch,
4159 struct address_space *aspace, CORE_ADDR pc)
4160 {
4161 if (mips_pc_is_mips (pc))
4162 return mips_deal_with_atomic_sequence (gdbarch, aspace, pc);
4163 else if (mips_pc_is_micromips (gdbarch, pc))
4164 return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc);
4165 else
4166 return 0;
4167 }
4168
4169 /* mips_software_single_step() is called just before we want to resume
4170 the inferior, if we want to single-step it but there is no hardware
4171 or kernel single-step support (MIPS on GNU/Linux for example). We find
4172 the target of the coming instruction and breakpoint it. */
4173
4174 int
4175 mips_software_single_step (struct frame_info *frame)
4176 {
4177 struct gdbarch *gdbarch = get_frame_arch (frame);
4178 struct address_space *aspace = get_frame_address_space (frame);
4179 CORE_ADDR pc, next_pc;
4180
4181 pc = get_frame_pc (frame);
4182 if (deal_with_atomic_sequence (gdbarch, aspace, pc))
4183 return 1;
4184
4185 next_pc = mips_next_pc (frame, pc);
4186
4187 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
4188 return 1;
4189 }
4190
4191 /* Test whether the PC points to the return instruction at the
4192 end of a function. */
4193
4194 static int
4195 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
4196 {
4197 ULONGEST insn;
4198 ULONGEST hint;
4199
4200 /* This used to check for MIPS16, but this piece of code is never
4201 called for MIPS16 functions. And likewise microMIPS ones. */
4202 gdb_assert (mips_pc_is_mips (pc));
4203
4204 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
4205 hint = 0x7c0;
4206 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */
4207 }
4208
4209
4210 /* This fencepost looks highly suspicious to me. Removing it also
4211 seems suspicious as it could affect remote debugging across serial
4212 lines. */
4213
4214 static CORE_ADDR
4215 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
4216 {
4217 CORE_ADDR start_pc;
4218 CORE_ADDR fence;
4219 int instlen;
4220 int seen_adjsp = 0;
4221 struct inferior *inf;
4222
4223 pc = gdbarch_addr_bits_remove (gdbarch, pc);
4224 start_pc = pc;
4225 fence = start_pc - heuristic_fence_post;
4226 if (start_pc == 0)
4227 return 0;
4228
4229 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS)
4230 fence = VM_MIN_ADDRESS;
4231
4232 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE;
4233
4234 inf = current_inferior ();
4235
4236 /* Search back for previous return. */
4237 for (start_pc -= instlen;; start_pc -= instlen)
4238 if (start_pc < fence)
4239 {
4240 /* It's not clear to me why we reach this point when
4241 stop_soon, but with this test, at least we
4242 don't print out warnings for every child forked (eg, on
4243 decstation). 22apr93 rich@cygnus.com. */
4244 if (inf->control.stop_soon == NO_STOP_QUIETLY)
4245 {
4246 static int blurb_printed = 0;
4247
4248 warning (_("GDB can't find the start of the function at %s."),
4249 paddress (gdbarch, pc));
4250
4251 if (!blurb_printed)
4252 {
4253 /* This actually happens frequently in embedded
4254 development, when you first connect to a board
4255 and your stack pointer and pc are nowhere in
4256 particular. This message needs to give people
4257 in that situation enough information to
4258 determine that it's no big deal. */
4259 printf_filtered ("\n\
4260 GDB is unable to find the start of the function at %s\n\
4261 and thus can't determine the size of that function's stack frame.\n\
4262 This means that GDB may be unable to access that stack frame, or\n\
4263 the frames below it.\n\
4264 This problem is most likely caused by an invalid program counter or\n\
4265 stack pointer.\n\
4266 However, if you think GDB should simply search farther back\n\
4267 from %s for code which looks like the beginning of a\n\
4268 function, you can increase the range of the search using the `set\n\
4269 heuristic-fence-post' command.\n",
4270 paddress (gdbarch, pc), paddress (gdbarch, pc));
4271 blurb_printed = 1;
4272 }
4273 }
4274
4275 return 0;
4276 }
4277 else if (mips_pc_is_mips16 (gdbarch, start_pc))
4278 {
4279 unsigned short inst;
4280
4281 /* On MIPS16, any one of the following is likely to be the
4282 start of a function:
4283 extend save
4284 save
4285 entry
4286 addiu sp,-n
4287 daddiu sp,-n
4288 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4289 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL);
4290 if ((inst & 0xff80) == 0x6480) /* save */
4291 {
4292 if (start_pc - instlen >= fence)
4293 {
4294 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16,
4295 start_pc - instlen, NULL);
4296 if ((inst & 0xf800) == 0xf000) /* extend */
4297 start_pc -= instlen;
4298 }
4299 break;
4300 }
4301 else if (((inst & 0xf81f) == 0xe809
4302 && (inst & 0x700) != 0x700) /* entry */
4303 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
4304 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
4305 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
4306 break;
4307 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
4308 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
4309 seen_adjsp = 1;
4310 else
4311 seen_adjsp = 0;
4312 }
4313 else if (mips_pc_is_micromips (gdbarch, start_pc))
4314 {
4315 ULONGEST insn;
4316 int stop = 0;
4317 long offset;
4318 int dreg;
4319 int sreg;
4320
4321 /* On microMIPS, any one of the following is likely to be the
4322 start of a function:
4323 ADDIUSP -imm
4324 (D)ADDIU $sp, -imm
4325 LUI $gp, imm */
4326 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
4327 switch (micromips_op (insn))
4328 {
4329 case 0xc: /* ADDIU: bits 001100 */
4330 case 0x17: /* DADDIU: bits 010111 */
4331 sreg = b0s5_reg (insn);
4332 dreg = b5s5_reg (insn);
4333 insn <<= 16;
4334 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS,
4335 pc + MIPS_INSN16_SIZE, NULL);
4336 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
4337 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
4338 /* (D)ADDIU $sp, imm */
4339 && offset < 0)
4340 stop = 1;
4341 break;
4342
4343 case 0x10: /* POOL32I: bits 010000 */
4344 if (b5s5_op (insn) == 0xd
4345 /* LUI: bits 010000 001101 */
4346 && b0s5_reg (insn >> 16) == 28)
4347 /* LUI $gp, imm */
4348 stop = 1;
4349 break;
4350
4351 case 0x13: /* POOL16D: bits 010011 */
4352 if ((insn & 0x1) == 0x1)
4353 /* ADDIUSP: bits 010011 1 */
4354 {
4355 offset = micromips_decode_imm9 (b1s9_imm (insn));
4356 if (offset < 0)
4357 /* ADDIUSP -imm */
4358 stop = 1;
4359 }
4360 else
4361 /* ADDIUS5: bits 010011 0 */
4362 {
4363 dreg = b5s5_reg (insn);
4364 offset = (b1s4_imm (insn) ^ 8) - 8;
4365 if (dreg == MIPS_SP_REGNUM && offset < 0)
4366 /* ADDIUS5 $sp, -imm */
4367 stop = 1;
4368 }
4369 break;
4370 }
4371 if (stop)
4372 break;
4373 }
4374 else if (mips_about_to_return (gdbarch, start_pc))
4375 {
4376 /* Skip return and its delay slot. */
4377 start_pc += 2 * MIPS_INSN32_SIZE;
4378 break;
4379 }
4380
4381 return start_pc;
4382 }
4383
4384 struct mips_objfile_private
4385 {
4386 bfd_size_type size;
4387 char *contents;
4388 };
4389
4390 /* According to the current ABI, should the type be passed in a
4391 floating-point register (assuming that there is space)? When there
4392 is no FPU, FP are not even considered as possible candidates for
4393 FP registers and, consequently this returns false - forces FP
4394 arguments into integer registers. */
4395
4396 static int
4397 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
4398 struct type *arg_type)
4399 {
4400 return ((typecode == TYPE_CODE_FLT
4401 || (MIPS_EABI (gdbarch)
4402 && (typecode == TYPE_CODE_STRUCT
4403 || typecode == TYPE_CODE_UNION)
4404 && TYPE_NFIELDS (arg_type) == 1
4405 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
4406 == TYPE_CODE_FLT))
4407 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
4408 }
4409
4410 /* On o32, argument passing in GPRs depends on the alignment of the type being
4411 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4412
4413 static int
4414 mips_type_needs_double_align (struct type *type)
4415 {
4416 enum type_code typecode = TYPE_CODE (type);
4417
4418 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
4419 return 1;
4420 else if (typecode == TYPE_CODE_STRUCT)
4421 {
4422 if (TYPE_NFIELDS (type) < 1)
4423 return 0;
4424 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
4425 }
4426 else if (typecode == TYPE_CODE_UNION)
4427 {
4428 int i, n;
4429
4430 n = TYPE_NFIELDS (type);
4431 for (i = 0; i < n; i++)
4432 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
4433 return 1;
4434 return 0;
4435 }
4436 return 0;
4437 }
4438
4439 /* Adjust the address downward (direction of stack growth) so that it
4440 is correctly aligned for a new stack frame. */
4441 static CORE_ADDR
4442 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
4443 {
4444 return align_down (addr, 16);
4445 }
4446
4447 /* Implement the "push_dummy_code" gdbarch method. */
4448
4449 static CORE_ADDR
4450 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
4451 CORE_ADDR funaddr, struct value **args,
4452 int nargs, struct type *value_type,
4453 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
4454 struct regcache *regcache)
4455 {
4456 static gdb_byte nop_insn[] = { 0, 0, 0, 0 };
4457 CORE_ADDR nop_addr;
4458 CORE_ADDR bp_slot;
4459
4460 /* Reserve enough room on the stack for our breakpoint instruction. */
4461 bp_slot = sp - sizeof (nop_insn);
4462
4463 /* Return to microMIPS mode if calling microMIPS code to avoid
4464 triggering an address error exception on processors that only
4465 support microMIPS execution. */
4466 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr)
4467 ? make_compact_addr (bp_slot) : bp_slot);
4468
4469 /* The breakpoint layer automatically adjusts the address of
4470 breakpoints inserted in a branch delay slot. With enough
4471 bad luck, the 4 bytes located just before our breakpoint
4472 instruction could look like a branch instruction, and thus
4473 trigger the adjustement, and break the function call entirely.
4474 So, we reserve those 4 bytes and write a nop instruction
4475 to prevent that from happening. */
4476 nop_addr = bp_slot - sizeof (nop_insn);
4477 write_memory (nop_addr, nop_insn, sizeof (nop_insn));
4478 sp = mips_frame_align (gdbarch, nop_addr);
4479
4480 /* Inferior resumes at the function entry point. */
4481 *real_pc = funaddr;
4482
4483 return sp;
4484 }
4485
4486 static CORE_ADDR
4487 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4488 struct regcache *regcache, CORE_ADDR bp_addr,
4489 int nargs, struct value **args, CORE_ADDR sp,
4490 int struct_return, CORE_ADDR struct_addr)
4491 {
4492 int argreg;
4493 int float_argreg;
4494 int argnum;
4495 int len = 0;
4496 int stack_offset = 0;
4497 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4498 CORE_ADDR func_addr = find_function_addr (function, NULL);
4499 int regsize = mips_abi_regsize (gdbarch);
4500
4501 /* For shared libraries, "t9" needs to point at the function
4502 address. */
4503 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4504
4505 /* Set the return address register to point to the entry point of
4506 the program, where a breakpoint lies in wait. */
4507 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4508
4509 /* First ensure that the stack and structure return address (if any)
4510 are properly aligned. The stack has to be at least 64-bit
4511 aligned even on 32-bit machines, because doubles must be 64-bit
4512 aligned. For n32 and n64, stack frames need to be 128-bit
4513 aligned, so we round to this widest known alignment. */
4514
4515 sp = align_down (sp, 16);
4516 struct_addr = align_down (struct_addr, 16);
4517
4518 /* Now make space on the stack for the args. We allocate more
4519 than necessary for EABI, because the first few arguments are
4520 passed in registers, but that's OK. */
4521 for (argnum = 0; argnum < nargs; argnum++)
4522 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
4523 sp -= align_up (len, 16);
4524
4525 if (mips_debug)
4526 fprintf_unfiltered (gdb_stdlog,
4527 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4528 paddress (gdbarch, sp), (long) align_up (len, 16));
4529
4530 /* Initialize the integer and float register pointers. */
4531 argreg = MIPS_A0_REGNUM;
4532 float_argreg = mips_fpa0_regnum (gdbarch);
4533
4534 /* The struct_return pointer occupies the first parameter-passing reg. */
4535 if (struct_return)
4536 {
4537 if (mips_debug)
4538 fprintf_unfiltered (gdb_stdlog,
4539 "mips_eabi_push_dummy_call: "
4540 "struct_return reg=%d %s\n",
4541 argreg, paddress (gdbarch, struct_addr));
4542 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4543 }
4544
4545 /* Now load as many as possible of the first arguments into
4546 registers, and push the rest onto the stack. Loop thru args
4547 from first to last. */
4548 for (argnum = 0; argnum < nargs; argnum++)
4549 {
4550 const gdb_byte *val;
4551 gdb_byte valbuf[MAX_REGISTER_SIZE];
4552 struct value *arg = args[argnum];
4553 struct type *arg_type = check_typedef (value_type (arg));
4554 int len = TYPE_LENGTH (arg_type);
4555 enum type_code typecode = TYPE_CODE (arg_type);
4556
4557 if (mips_debug)
4558 fprintf_unfiltered (gdb_stdlog,
4559 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4560 argnum + 1, len, (int) typecode);
4561
4562 /* The EABI passes structures that do not fit in a register by
4563 reference. */
4564 if (len > regsize
4565 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
4566 {
4567 store_unsigned_integer (valbuf, regsize, byte_order,
4568 value_address (arg));
4569 typecode = TYPE_CODE_PTR;
4570 len = regsize;
4571 val = valbuf;
4572 if (mips_debug)
4573 fprintf_unfiltered (gdb_stdlog, " push");
4574 }
4575 else
4576 val = value_contents (arg);
4577
4578 /* 32-bit ABIs always start floating point arguments in an
4579 even-numbered floating point register. Round the FP register
4580 up before the check to see if there are any FP registers
4581 left. Non MIPS_EABI targets also pass the FP in the integer
4582 registers so also round up normal registers. */
4583 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
4584 {
4585 if ((float_argreg & 1))
4586 float_argreg++;
4587 }
4588
4589 /* Floating point arguments passed in registers have to be
4590 treated specially. On 32-bit architectures, doubles
4591 are passed in register pairs; the even register gets
4592 the low word, and the odd register gets the high word.
4593 On non-EABI processors, the first two floating point arguments are
4594 also copied to general registers, because MIPS16 functions
4595 don't use float registers for arguments. This duplication of
4596 arguments in general registers can't hurt non-MIPS16 functions
4597 because those registers are normally skipped. */
4598 /* MIPS_EABI squeezes a struct that contains a single floating
4599 point value into an FP register instead of pushing it onto the
4600 stack. */
4601 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4602 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4603 {
4604 /* EABI32 will pass doubles in consecutive registers, even on
4605 64-bit cores. At one time, we used to check the size of
4606 `float_argreg' to determine whether or not to pass doubles
4607 in consecutive registers, but this is not sufficient for
4608 making the ABI determination. */
4609 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
4610 {
4611 int low_offset = gdbarch_byte_order (gdbarch)
4612 == BFD_ENDIAN_BIG ? 4 : 0;
4613 long regval;
4614
4615 /* Write the low word of the double to the even register(s). */
4616 regval = extract_signed_integer (val + low_offset,
4617 4, byte_order);
4618 if (mips_debug)
4619 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4620 float_argreg, phex (regval, 4));
4621 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4622
4623 /* Write the high word of the double to the odd register(s). */
4624 regval = extract_signed_integer (val + 4 - low_offset,
4625 4, byte_order);
4626 if (mips_debug)
4627 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4628 float_argreg, phex (regval, 4));
4629 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4630 }
4631 else
4632 {
4633 /* This is a floating point value that fits entirely
4634 in a single register. */
4635 /* On 32 bit ABI's the float_argreg is further adjusted
4636 above to ensure that it is even register aligned. */
4637 LONGEST regval = extract_signed_integer (val, len, byte_order);
4638 if (mips_debug)
4639 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4640 float_argreg, phex (regval, len));
4641 regcache_cooked_write_signed (regcache, float_argreg++, regval);
4642 }
4643 }
4644 else
4645 {
4646 /* Copy the argument to general registers or the stack in
4647 register-sized pieces. Large arguments are split between
4648 registers and stack. */
4649 /* Note: structs whose size is not a multiple of regsize
4650 are treated specially: Irix cc passes
4651 them in registers where gcc sometimes puts them on the
4652 stack. For maximum compatibility, we will put them in
4653 both places. */
4654 int odd_sized_struct = (len > regsize && len % regsize != 0);
4655
4656 /* Note: Floating-point values that didn't fit into an FP
4657 register are only written to memory. */
4658 while (len > 0)
4659 {
4660 /* Remember if the argument was written to the stack. */
4661 int stack_used_p = 0;
4662 int partial_len = (len < regsize ? len : regsize);
4663
4664 if (mips_debug)
4665 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4666 partial_len);
4667
4668 /* Write this portion of the argument to the stack. */
4669 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4670 || odd_sized_struct
4671 || fp_register_arg_p (gdbarch, typecode, arg_type))
4672 {
4673 /* Should shorter than int integer values be
4674 promoted to int before being stored? */
4675 int longword_offset = 0;
4676 CORE_ADDR addr;
4677 stack_used_p = 1;
4678 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4679 {
4680 if (regsize == 8
4681 && (typecode == TYPE_CODE_INT
4682 || typecode == TYPE_CODE_PTR
4683 || typecode == TYPE_CODE_FLT) && len <= 4)
4684 longword_offset = regsize - len;
4685 else if ((typecode == TYPE_CODE_STRUCT
4686 || typecode == TYPE_CODE_UNION)
4687 && TYPE_LENGTH (arg_type) < regsize)
4688 longword_offset = regsize - len;
4689 }
4690
4691 if (mips_debug)
4692 {
4693 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4694 paddress (gdbarch, stack_offset));
4695 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4696 paddress (gdbarch, longword_offset));
4697 }
4698
4699 addr = sp + stack_offset + longword_offset;
4700
4701 if (mips_debug)
4702 {
4703 int i;
4704 fprintf_unfiltered (gdb_stdlog, " @%s ",
4705 paddress (gdbarch, addr));
4706 for (i = 0; i < partial_len; i++)
4707 {
4708 fprintf_unfiltered (gdb_stdlog, "%02x",
4709 val[i] & 0xff);
4710 }
4711 }
4712 write_memory (addr, val, partial_len);
4713 }
4714
4715 /* Note!!! This is NOT an else clause. Odd sized
4716 structs may go thru BOTH paths. Floating point
4717 arguments will not. */
4718 /* Write this portion of the argument to a general
4719 purpose register. */
4720 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
4721 && !fp_register_arg_p (gdbarch, typecode, arg_type))
4722 {
4723 LONGEST regval =
4724 extract_signed_integer (val, partial_len, byte_order);
4725
4726 if (mips_debug)
4727 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4728 argreg,
4729 phex (regval, regsize));
4730 regcache_cooked_write_signed (regcache, argreg, regval);
4731 argreg++;
4732 }
4733
4734 len -= partial_len;
4735 val += partial_len;
4736
4737 /* Compute the offset into the stack at which we will
4738 copy the next parameter.
4739
4740 In the new EABI (and the NABI32), the stack_offset
4741 only needs to be adjusted when it has been used. */
4742
4743 if (stack_used_p)
4744 stack_offset += align_up (partial_len, regsize);
4745 }
4746 }
4747 if (mips_debug)
4748 fprintf_unfiltered (gdb_stdlog, "\n");
4749 }
4750
4751 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4752
4753 /* Return adjusted stack pointer. */
4754 return sp;
4755 }
4756
4757 /* Determine the return value convention being used. */
4758
4759 static enum return_value_convention
4760 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function,
4761 struct type *type, struct regcache *regcache,
4762 gdb_byte *readbuf, const gdb_byte *writebuf)
4763 {
4764 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4765 int fp_return_type = 0;
4766 int offset, regnum, xfer;
4767
4768 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
4769 return RETURN_VALUE_STRUCT_CONVENTION;
4770
4771 /* Floating point type? */
4772 if (tdep->mips_fpu_type != MIPS_FPU_NONE)
4773 {
4774 if (TYPE_CODE (type) == TYPE_CODE_FLT)
4775 fp_return_type = 1;
4776 /* Structs with a single field of float type
4777 are returned in a floating point register. */
4778 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
4779 || TYPE_CODE (type) == TYPE_CODE_UNION)
4780 && TYPE_NFIELDS (type) == 1)
4781 {
4782 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
4783
4784 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
4785 fp_return_type = 1;
4786 }
4787 }
4788
4789 if (fp_return_type)
4790 {
4791 /* A floating-point value belongs in the least significant part
4792 of FP0/FP1. */
4793 if (mips_debug)
4794 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4795 regnum = mips_regnum (gdbarch)->fp0;
4796 }
4797 else
4798 {
4799 /* An integer value goes in V0/V1. */
4800 if (mips_debug)
4801 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
4802 regnum = MIPS_V0_REGNUM;
4803 }
4804 for (offset = 0;
4805 offset < TYPE_LENGTH (type);
4806 offset += mips_abi_regsize (gdbarch), regnum++)
4807 {
4808 xfer = mips_abi_regsize (gdbarch);
4809 if (offset + xfer > TYPE_LENGTH (type))
4810 xfer = TYPE_LENGTH (type) - offset;
4811 mips_xfer_register (gdbarch, regcache,
4812 gdbarch_num_regs (gdbarch) + regnum, xfer,
4813 gdbarch_byte_order (gdbarch), readbuf, writebuf,
4814 offset);
4815 }
4816
4817 return RETURN_VALUE_REGISTER_CONVENTION;
4818 }
4819
4820
4821 /* N32/N64 ABI stuff. */
4822
4823 /* Search for a naturally aligned double at OFFSET inside a struct
4824 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4825 registers. */
4826
4827 static int
4828 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
4829 int offset)
4830 {
4831 int i;
4832
4833 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
4834 return 0;
4835
4836 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
4837 return 0;
4838
4839 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
4840 return 0;
4841
4842 for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
4843 {
4844 int pos;
4845 struct type *field_type;
4846
4847 /* We're only looking at normal fields. */
4848 if (field_is_static (&TYPE_FIELD (arg_type, i))
4849 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
4850 continue;
4851
4852 /* If we have gone past the offset, there is no double to pass. */
4853 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
4854 if (pos > offset)
4855 return 0;
4856
4857 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
4858
4859 /* If this field is entirely before the requested offset, go
4860 on to the next one. */
4861 if (pos + TYPE_LENGTH (field_type) <= offset)
4862 continue;
4863
4864 /* If this is our special aligned double, we can stop. */
4865 if (TYPE_CODE (field_type) == TYPE_CODE_FLT
4866 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
4867 return 1;
4868
4869 /* This field starts at or before the requested offset, and
4870 overlaps it. If it is a structure, recurse inwards. */
4871 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
4872 }
4873
4874 return 0;
4875 }
4876
4877 static CORE_ADDR
4878 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4879 struct regcache *regcache, CORE_ADDR bp_addr,
4880 int nargs, struct value **args, CORE_ADDR sp,
4881 int struct_return, CORE_ADDR struct_addr)
4882 {
4883 int argreg;
4884 int float_argreg;
4885 int argnum;
4886 int len = 0;
4887 int stack_offset = 0;
4888 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4889 CORE_ADDR func_addr = find_function_addr (function, NULL);
4890
4891 /* For shared libraries, "t9" needs to point at the function
4892 address. */
4893 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4894
4895 /* Set the return address register to point to the entry point of
4896 the program, where a breakpoint lies in wait. */
4897 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4898
4899 /* First ensure that the stack and structure return address (if any)
4900 are properly aligned. The stack has to be at least 64-bit
4901 aligned even on 32-bit machines, because doubles must be 64-bit
4902 aligned. For n32 and n64, stack frames need to be 128-bit
4903 aligned, so we round to this widest known alignment. */
4904
4905 sp = align_down (sp, 16);
4906 struct_addr = align_down (struct_addr, 16);
4907
4908 /* Now make space on the stack for the args. */
4909 for (argnum = 0; argnum < nargs; argnum++)
4910 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
4911 sp -= align_up (len, 16);
4912
4913 if (mips_debug)
4914 fprintf_unfiltered (gdb_stdlog,
4915 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4916 paddress (gdbarch, sp), (long) align_up (len, 16));
4917
4918 /* Initialize the integer and float register pointers. */
4919 argreg = MIPS_A0_REGNUM;
4920 float_argreg = mips_fpa0_regnum (gdbarch);
4921
4922 /* The struct_return pointer occupies the first parameter-passing reg. */
4923 if (struct_return)
4924 {
4925 if (mips_debug)
4926 fprintf_unfiltered (gdb_stdlog,
4927 "mips_n32n64_push_dummy_call: "
4928 "struct_return reg=%d %s\n",
4929 argreg, paddress (gdbarch, struct_addr));
4930 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4931 }
4932
4933 /* Now load as many as possible of the first arguments into
4934 registers, and push the rest onto the stack. Loop thru args
4935 from first to last. */
4936 for (argnum = 0; argnum < nargs; argnum++)
4937 {
4938 const gdb_byte *val;
4939 struct value *arg = args[argnum];
4940 struct type *arg_type = check_typedef (value_type (arg));
4941 int len = TYPE_LENGTH (arg_type);
4942 enum type_code typecode = TYPE_CODE (arg_type);
4943
4944 if (mips_debug)
4945 fprintf_unfiltered (gdb_stdlog,
4946 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4947 argnum + 1, len, (int) typecode);
4948
4949 val = value_contents (arg);
4950
4951 /* A 128-bit long double value requires an even-odd pair of
4952 floating-point registers. */
4953 if (len == 16
4954 && fp_register_arg_p (gdbarch, typecode, arg_type)
4955 && (float_argreg & 1))
4956 {
4957 float_argreg++;
4958 argreg++;
4959 }
4960
4961 if (fp_register_arg_p (gdbarch, typecode, arg_type)
4962 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4963 {
4964 /* This is a floating point value that fits entirely
4965 in a single register or a pair of registers. */
4966 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4967 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
4968 if (mips_debug)
4969 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4970 float_argreg, phex (regval, reglen));
4971 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4972
4973 if (mips_debug)
4974 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4975 argreg, phex (regval, reglen));
4976 regcache_cooked_write_unsigned (regcache, argreg, regval);
4977 float_argreg++;
4978 argreg++;
4979 if (len == 16)
4980 {
4981 regval = extract_unsigned_integer (val + reglen,
4982 reglen, byte_order);
4983 if (mips_debug)
4984 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4985 float_argreg, phex (regval, reglen));
4986 regcache_cooked_write_unsigned (regcache, float_argreg, regval);
4987
4988 if (mips_debug)
4989 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4990 argreg, phex (regval, reglen));
4991 regcache_cooked_write_unsigned (regcache, argreg, regval);
4992 float_argreg++;
4993 argreg++;
4994 }
4995 }
4996 else
4997 {
4998 /* Copy the argument to general registers or the stack in
4999 register-sized pieces. Large arguments are split between
5000 registers and stack. */
5001 /* For N32/N64, structs, unions, or other composite types are
5002 treated as a sequence of doublewords, and are passed in integer
5003 or floating point registers as though they were simple scalar
5004 parameters to the extent that they fit, with any excess on the
5005 stack packed according to the normal memory layout of the
5006 object.
5007 The caller does not reserve space for the register arguments;
5008 the callee is responsible for reserving it if required. */
5009 /* Note: Floating-point values that didn't fit into an FP
5010 register are only written to memory. */
5011 while (len > 0)
5012 {
5013 /* Remember if the argument was written to the stack. */
5014 int stack_used_p = 0;
5015 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5016
5017 if (mips_debug)
5018 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5019 partial_len);
5020
5021 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5022 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
5023
5024 /* Write this portion of the argument to the stack. */
5025 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
5026 {
5027 /* Should shorter than int integer values be
5028 promoted to int before being stored? */
5029 int longword_offset = 0;
5030 CORE_ADDR addr;
5031 stack_used_p = 1;
5032 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5033 {
5034 if ((typecode == TYPE_CODE_INT
5035 || typecode == TYPE_CODE_PTR)
5036 && len <= 4)
5037 longword_offset = MIPS64_REGSIZE - len;
5038 }
5039
5040 if (mips_debug)
5041 {
5042 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5043 paddress (gdbarch, stack_offset));
5044 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5045 paddress (gdbarch, longword_offset));
5046 }
5047
5048 addr = sp + stack_offset + longword_offset;
5049
5050 if (mips_debug)
5051 {
5052 int i;
5053 fprintf_unfiltered (gdb_stdlog, " @%s ",
5054 paddress (gdbarch, addr));
5055 for (i = 0; i < partial_len; i++)
5056 {
5057 fprintf_unfiltered (gdb_stdlog, "%02x",
5058 val[i] & 0xff);
5059 }
5060 }
5061 write_memory (addr, val, partial_len);
5062 }
5063
5064 /* Note!!! This is NOT an else clause. Odd sized
5065 structs may go thru BOTH paths. */
5066 /* Write this portion of the argument to a general
5067 purpose register. */
5068 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5069 {
5070 LONGEST regval;
5071
5072 /* Sign extend pointers, 32-bit integers and signed
5073 16-bit and 8-bit integers; everything else is taken
5074 as is. */
5075
5076 if ((partial_len == 4
5077 && (typecode == TYPE_CODE_PTR
5078 || typecode == TYPE_CODE_INT))
5079 || (partial_len < 4
5080 && typecode == TYPE_CODE_INT
5081 && !TYPE_UNSIGNED (arg_type)))
5082 regval = extract_signed_integer (val, partial_len,
5083 byte_order);
5084 else
5085 regval = extract_unsigned_integer (val, partial_len,
5086 byte_order);
5087
5088 /* A non-floating-point argument being passed in a
5089 general register. If a struct or union, and if
5090 the remaining length is smaller than the register
5091 size, we have to adjust the register value on
5092 big endian targets.
5093
5094 It does not seem to be necessary to do the
5095 same for integral types. */
5096
5097 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5098 && partial_len < MIPS64_REGSIZE
5099 && (typecode == TYPE_CODE_STRUCT
5100 || typecode == TYPE_CODE_UNION))
5101 regval <<= ((MIPS64_REGSIZE - partial_len)
5102 * TARGET_CHAR_BIT);
5103
5104 if (mips_debug)
5105 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5106 argreg,
5107 phex (regval, MIPS64_REGSIZE));
5108 regcache_cooked_write_unsigned (regcache, argreg, regval);
5109
5110 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
5111 TYPE_LENGTH (arg_type) - len))
5112 {
5113 if (mips_debug)
5114 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
5115 float_argreg,
5116 phex (regval, MIPS64_REGSIZE));
5117 regcache_cooked_write_unsigned (regcache, float_argreg,
5118 regval);
5119 }
5120
5121 float_argreg++;
5122 argreg++;
5123 }
5124
5125 len -= partial_len;
5126 val += partial_len;
5127
5128 /* Compute the offset into the stack at which we will
5129 copy the next parameter.
5130
5131 In N32 (N64?), the stack_offset only needs to be
5132 adjusted when it has been used. */
5133
5134 if (stack_used_p)
5135 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
5136 }
5137 }
5138 if (mips_debug)
5139 fprintf_unfiltered (gdb_stdlog, "\n");
5140 }
5141
5142 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5143
5144 /* Return adjusted stack pointer. */
5145 return sp;
5146 }
5147
5148 static enum return_value_convention
5149 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function,
5150 struct type *type, struct regcache *regcache,
5151 gdb_byte *readbuf, const gdb_byte *writebuf)
5152 {
5153 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5154
5155 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5156
5157 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5158 if needed), as appropriate for the type. Composite results (struct,
5159 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5160 following rules:
5161
5162 * A struct with only one or two floating point fields is returned in $f0
5163 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5164 case.
5165
5166 * Any other composite results of at most 128 bits are returned in
5167 $2 (first 64 bits) and $3 (remainder, if necessary).
5168
5169 * Larger composite results are handled by converting the function to a
5170 procedure with an implicit first parameter, which is a pointer to an area
5171 reserved by the caller to receive the result. [The o32-bit ABI requires
5172 that all composite results be handled by conversion to implicit first
5173 parameters. The MIPS/SGI Fortran implementation has always made a
5174 specific exception to return COMPLEX results in the floating point
5175 registers.] */
5176
5177 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
5178 return RETURN_VALUE_STRUCT_CONVENTION;
5179 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5180 && TYPE_LENGTH (type) == 16
5181 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5182 {
5183 /* A 128-bit floating-point value fills both $f0 and $f2. The
5184 two registers are used in the same as memory order, so the
5185 eight bytes with the lower memory address are in $f0. */
5186 if (mips_debug)
5187 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
5188 mips_xfer_register (gdbarch, regcache,
5189 (gdbarch_num_regs (gdbarch)
5190 + mips_regnum (gdbarch)->fp0),
5191 8, gdbarch_byte_order (gdbarch),
5192 readbuf, writebuf, 0);
5193 mips_xfer_register (gdbarch, regcache,
5194 (gdbarch_num_regs (gdbarch)
5195 + mips_regnum (gdbarch)->fp0 + 2),
5196 8, gdbarch_byte_order (gdbarch),
5197 readbuf ? readbuf + 8 : readbuf,
5198 writebuf ? writebuf + 8 : writebuf, 0);
5199 return RETURN_VALUE_REGISTER_CONVENTION;
5200 }
5201 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5202 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5203 {
5204 /* A single or double floating-point value that fits in FP0. */
5205 if (mips_debug)
5206 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5207 mips_xfer_register (gdbarch, regcache,
5208 (gdbarch_num_regs (gdbarch)
5209 + mips_regnum (gdbarch)->fp0),
5210 TYPE_LENGTH (type),
5211 gdbarch_byte_order (gdbarch),
5212 readbuf, writebuf, 0);
5213 return RETURN_VALUE_REGISTER_CONVENTION;
5214 }
5215 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5216 && TYPE_NFIELDS (type) <= 2
5217 && TYPE_NFIELDS (type) >= 1
5218 && ((TYPE_NFIELDS (type) == 1
5219 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5220 == TYPE_CODE_FLT))
5221 || (TYPE_NFIELDS (type) == 2
5222 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
5223 == TYPE_CODE_FLT)
5224 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
5225 == TYPE_CODE_FLT))))
5226 {
5227 /* A struct that contains one or two floats. Each value is part
5228 in the least significant part of their floating point
5229 register (or GPR, for soft float). */
5230 int regnum;
5231 int field;
5232 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
5233 ? mips_regnum (gdbarch)->fp0
5234 : MIPS_V0_REGNUM);
5235 field < TYPE_NFIELDS (type); field++, regnum += 2)
5236 {
5237 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5238 / TARGET_CHAR_BIT);
5239 if (mips_debug)
5240 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5241 offset);
5242 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
5243 {
5244 /* A 16-byte long double field goes in two consecutive
5245 registers. */
5246 mips_xfer_register (gdbarch, regcache,
5247 gdbarch_num_regs (gdbarch) + regnum,
5248 8,
5249 gdbarch_byte_order (gdbarch),
5250 readbuf, writebuf, offset);
5251 mips_xfer_register (gdbarch, regcache,
5252 gdbarch_num_regs (gdbarch) + regnum + 1,
5253 8,
5254 gdbarch_byte_order (gdbarch),
5255 readbuf, writebuf, offset + 8);
5256 }
5257 else
5258 mips_xfer_register (gdbarch, regcache,
5259 gdbarch_num_regs (gdbarch) + regnum,
5260 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5261 gdbarch_byte_order (gdbarch),
5262 readbuf, writebuf, offset);
5263 }
5264 return RETURN_VALUE_REGISTER_CONVENTION;
5265 }
5266 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5267 || TYPE_CODE (type) == TYPE_CODE_UNION
5268 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5269 {
5270 /* A composite type. Extract the left justified value,
5271 regardless of the byte order. I.e. DO NOT USE
5272 mips_xfer_lower. */
5273 int offset;
5274 int regnum;
5275 for (offset = 0, regnum = MIPS_V0_REGNUM;
5276 offset < TYPE_LENGTH (type);
5277 offset += register_size (gdbarch, regnum), regnum++)
5278 {
5279 int xfer = register_size (gdbarch, regnum);
5280 if (offset + xfer > TYPE_LENGTH (type))
5281 xfer = TYPE_LENGTH (type) - offset;
5282 if (mips_debug)
5283 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5284 offset, xfer, regnum);
5285 mips_xfer_register (gdbarch, regcache,
5286 gdbarch_num_regs (gdbarch) + regnum,
5287 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
5288 offset);
5289 }
5290 return RETURN_VALUE_REGISTER_CONVENTION;
5291 }
5292 else
5293 {
5294 /* A scalar extract each part but least-significant-byte
5295 justified. */
5296 int offset;
5297 int regnum;
5298 for (offset = 0, regnum = MIPS_V0_REGNUM;
5299 offset < TYPE_LENGTH (type);
5300 offset += register_size (gdbarch, regnum), regnum++)
5301 {
5302 int xfer = register_size (gdbarch, regnum);
5303 if (offset + xfer > TYPE_LENGTH (type))
5304 xfer = TYPE_LENGTH (type) - offset;
5305 if (mips_debug)
5306 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5307 offset, xfer, regnum);
5308 mips_xfer_register (gdbarch, regcache,
5309 gdbarch_num_regs (gdbarch) + regnum,
5310 xfer, gdbarch_byte_order (gdbarch),
5311 readbuf, writebuf, offset);
5312 }
5313 return RETURN_VALUE_REGISTER_CONVENTION;
5314 }
5315 }
5316
5317 /* Which registers to use for passing floating-point values between
5318 function calls, one of floating-point, general and both kinds of
5319 registers. O32 and O64 use different register kinds for standard
5320 MIPS and MIPS16 code; to make the handling of cases where we may
5321 not know what kind of code is being used (e.g. no debug information)
5322 easier we sometimes use both kinds. */
5323
5324 enum mips_fval_reg
5325 {
5326 mips_fval_fpr,
5327 mips_fval_gpr,
5328 mips_fval_both
5329 };
5330
5331 /* O32 ABI stuff. */
5332
5333 static CORE_ADDR
5334 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5335 struct regcache *regcache, CORE_ADDR bp_addr,
5336 int nargs, struct value **args, CORE_ADDR sp,
5337 int struct_return, CORE_ADDR struct_addr)
5338 {
5339 int argreg;
5340 int float_argreg;
5341 int argnum;
5342 int len = 0;
5343 int stack_offset = 0;
5344 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5345 CORE_ADDR func_addr = find_function_addr (function, NULL);
5346
5347 /* For shared libraries, "t9" needs to point at the function
5348 address. */
5349 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5350
5351 /* Set the return address register to point to the entry point of
5352 the program, where a breakpoint lies in wait. */
5353 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5354
5355 /* First ensure that the stack and structure return address (if any)
5356 are properly aligned. The stack has to be at least 64-bit
5357 aligned even on 32-bit machines, because doubles must be 64-bit
5358 aligned. For n32 and n64, stack frames need to be 128-bit
5359 aligned, so we round to this widest known alignment. */
5360
5361 sp = align_down (sp, 16);
5362 struct_addr = align_down (struct_addr, 16);
5363
5364 /* Now make space on the stack for the args. */
5365 for (argnum = 0; argnum < nargs; argnum++)
5366 {
5367 struct type *arg_type = check_typedef (value_type (args[argnum]));
5368
5369 /* Align to double-word if necessary. */
5370 if (mips_type_needs_double_align (arg_type))
5371 len = align_up (len, MIPS32_REGSIZE * 2);
5372 /* Allocate space on the stack. */
5373 len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE);
5374 }
5375 sp -= align_up (len, 16);
5376
5377 if (mips_debug)
5378 fprintf_unfiltered (gdb_stdlog,
5379 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5380 paddress (gdbarch, sp), (long) align_up (len, 16));
5381
5382 /* Initialize the integer and float register pointers. */
5383 argreg = MIPS_A0_REGNUM;
5384 float_argreg = mips_fpa0_regnum (gdbarch);
5385
5386 /* The struct_return pointer occupies the first parameter-passing reg. */
5387 if (struct_return)
5388 {
5389 if (mips_debug)
5390 fprintf_unfiltered (gdb_stdlog,
5391 "mips_o32_push_dummy_call: "
5392 "struct_return reg=%d %s\n",
5393 argreg, paddress (gdbarch, struct_addr));
5394 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5395 stack_offset += MIPS32_REGSIZE;
5396 }
5397
5398 /* Now load as many as possible of the first arguments into
5399 registers, and push the rest onto the stack. Loop thru args
5400 from first to last. */
5401 for (argnum = 0; argnum < nargs; argnum++)
5402 {
5403 const gdb_byte *val;
5404 struct value *arg = args[argnum];
5405 struct type *arg_type = check_typedef (value_type (arg));
5406 int len = TYPE_LENGTH (arg_type);
5407 enum type_code typecode = TYPE_CODE (arg_type);
5408
5409 if (mips_debug)
5410 fprintf_unfiltered (gdb_stdlog,
5411 "mips_o32_push_dummy_call: %d len=%d type=%d",
5412 argnum + 1, len, (int) typecode);
5413
5414 val = value_contents (arg);
5415
5416 /* 32-bit ABIs always start floating point arguments in an
5417 even-numbered floating point register. Round the FP register
5418 up before the check to see if there are any FP registers
5419 left. O32 targets also pass the FP in the integer registers
5420 so also round up normal registers. */
5421 if (fp_register_arg_p (gdbarch, typecode, arg_type))
5422 {
5423 if ((float_argreg & 1))
5424 float_argreg++;
5425 }
5426
5427 /* Floating point arguments passed in registers have to be
5428 treated specially. On 32-bit architectures, doubles are
5429 passed in register pairs; the even FP register gets the
5430 low word, and the odd FP register gets the high word.
5431 On O32, the first two floating point arguments are also
5432 copied to general registers, following their memory order,
5433 because MIPS16 functions don't use float registers for
5434 arguments. This duplication of arguments in general
5435 registers can't hurt non-MIPS16 functions, because those
5436 registers are normally skipped. */
5437
5438 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5439 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5440 {
5441 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
5442 {
5443 int freg_offset = gdbarch_byte_order (gdbarch)
5444 == BFD_ENDIAN_BIG ? 1 : 0;
5445 unsigned long regval;
5446
5447 /* First word. */
5448 regval = extract_unsigned_integer (val, 4, byte_order);
5449 if (mips_debug)
5450 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5451 float_argreg + freg_offset,
5452 phex (regval, 4));
5453 regcache_cooked_write_unsigned (regcache,
5454 float_argreg++ + freg_offset,
5455 regval);
5456 if (mips_debug)
5457 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5458 argreg, phex (regval, 4));
5459 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5460
5461 /* Second word. */
5462 regval = extract_unsigned_integer (val + 4, 4, byte_order);
5463 if (mips_debug)
5464 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5465 float_argreg - freg_offset,
5466 phex (regval, 4));
5467 regcache_cooked_write_unsigned (regcache,
5468 float_argreg++ - freg_offset,
5469 regval);
5470 if (mips_debug)
5471 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5472 argreg, phex (regval, 4));
5473 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5474 }
5475 else
5476 {
5477 /* This is a floating point value that fits entirely
5478 in a single register. */
5479 /* On 32 bit ABI's the float_argreg is further adjusted
5480 above to ensure that it is even register aligned. */
5481 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5482 if (mips_debug)
5483 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5484 float_argreg, phex (regval, len));
5485 regcache_cooked_write_unsigned (regcache,
5486 float_argreg++, regval);
5487 /* Although two FP registers are reserved for each
5488 argument, only one corresponding integer register is
5489 reserved. */
5490 if (mips_debug)
5491 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5492 argreg, phex (regval, len));
5493 regcache_cooked_write_unsigned (regcache, argreg++, regval);
5494 }
5495 /* Reserve space for the FP register. */
5496 stack_offset += align_up (len, MIPS32_REGSIZE);
5497 }
5498 else
5499 {
5500 /* Copy the argument to general registers or the stack in
5501 register-sized pieces. Large arguments are split between
5502 registers and stack. */
5503 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5504 are treated specially: Irix cc passes
5505 them in registers where gcc sometimes puts them on the
5506 stack. For maximum compatibility, we will put them in
5507 both places. */
5508 int odd_sized_struct = (len > MIPS32_REGSIZE
5509 && len % MIPS32_REGSIZE != 0);
5510 /* Structures should be aligned to eight bytes (even arg registers)
5511 on MIPS_ABI_O32, if their first member has double precision. */
5512 if (mips_type_needs_double_align (arg_type))
5513 {
5514 if ((argreg & 1))
5515 {
5516 argreg++;
5517 stack_offset += MIPS32_REGSIZE;
5518 }
5519 }
5520 while (len > 0)
5521 {
5522 /* Remember if the argument was written to the stack. */
5523 int stack_used_p = 0;
5524 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
5525
5526 if (mips_debug)
5527 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5528 partial_len);
5529
5530 /* Write this portion of the argument to the stack. */
5531 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5532 || odd_sized_struct)
5533 {
5534 /* Should shorter than int integer values be
5535 promoted to int before being stored? */
5536 int longword_offset = 0;
5537 CORE_ADDR addr;
5538 stack_used_p = 1;
5539
5540 if (mips_debug)
5541 {
5542 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
5543 paddress (gdbarch, stack_offset));
5544 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
5545 paddress (gdbarch, longword_offset));
5546 }
5547
5548 addr = sp + stack_offset + longword_offset;
5549
5550 if (mips_debug)
5551 {
5552 int i;
5553 fprintf_unfiltered (gdb_stdlog, " @%s ",
5554 paddress (gdbarch, addr));
5555 for (i = 0; i < partial_len; i++)
5556 {
5557 fprintf_unfiltered (gdb_stdlog, "%02x",
5558 val[i] & 0xff);
5559 }
5560 }
5561 write_memory (addr, val, partial_len);
5562 }
5563
5564 /* Note!!! This is NOT an else clause. Odd sized
5565 structs may go thru BOTH paths. */
5566 /* Write this portion of the argument to a general
5567 purpose register. */
5568 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
5569 {
5570 LONGEST regval = extract_signed_integer (val, partial_len,
5571 byte_order);
5572 /* Value may need to be sign extended, because
5573 mips_isa_regsize() != mips_abi_regsize(). */
5574
5575 /* A non-floating-point argument being passed in a
5576 general register. If a struct or union, and if
5577 the remaining length is smaller than the register
5578 size, we have to adjust the register value on
5579 big endian targets.
5580
5581 It does not seem to be necessary to do the
5582 same for integral types.
5583
5584 Also don't do this adjustment on O64 binaries.
5585
5586 cagney/2001-07-23: gdb/179: Also, GCC, when
5587 outputting LE O32 with sizeof (struct) <
5588 mips_abi_regsize(), generates a left shift
5589 as part of storing the argument in a register
5590 (the left shift isn't generated when
5591 sizeof (struct) >= mips_abi_regsize()). Since
5592 it is quite possible that this is GCC
5593 contradicting the LE/O32 ABI, GDB has not been
5594 adjusted to accommodate this. Either someone
5595 needs to demonstrate that the LE/O32 ABI
5596 specifies such a left shift OR this new ABI gets
5597 identified as such and GDB gets tweaked
5598 accordingly. */
5599
5600 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
5601 && partial_len < MIPS32_REGSIZE
5602 && (typecode == TYPE_CODE_STRUCT
5603 || typecode == TYPE_CODE_UNION))
5604 regval <<= ((MIPS32_REGSIZE - partial_len)
5605 * TARGET_CHAR_BIT);
5606
5607 if (mips_debug)
5608 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
5609 argreg,
5610 phex (regval, MIPS32_REGSIZE));
5611 regcache_cooked_write_unsigned (regcache, argreg, regval);
5612 argreg++;
5613
5614 /* Prevent subsequent floating point arguments from
5615 being passed in floating point registers. */
5616 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
5617 }
5618
5619 len -= partial_len;
5620 val += partial_len;
5621
5622 /* Compute the offset into the stack at which we will
5623 copy the next parameter.
5624
5625 In older ABIs, the caller reserved space for
5626 registers that contained arguments. This was loosely
5627 refered to as their "home". Consequently, space is
5628 always allocated. */
5629
5630 stack_offset += align_up (partial_len, MIPS32_REGSIZE);
5631 }
5632 }
5633 if (mips_debug)
5634 fprintf_unfiltered (gdb_stdlog, "\n");
5635 }
5636
5637 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
5638
5639 /* Return adjusted stack pointer. */
5640 return sp;
5641 }
5642
5643 static enum return_value_convention
5644 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function,
5645 struct type *type, struct regcache *regcache,
5646 gdb_byte *readbuf, const gdb_byte *writebuf)
5647 {
5648 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
5649 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
5650 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5651 enum mips_fval_reg fval_reg;
5652
5653 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
5654 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5655 || TYPE_CODE (type) == TYPE_CODE_UNION
5656 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
5657 return RETURN_VALUE_STRUCT_CONVENTION;
5658 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5659 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5660 {
5661 /* A single-precision floating-point value. If reading in or copying,
5662 then we get it from/put it to FP0 for standard MIPS code or GPR2
5663 for MIPS16 code. If writing out only, then we put it to both FP0
5664 and GPR2. We do not support reading in with no function known, if
5665 this safety check ever triggers, then we'll have to try harder. */
5666 gdb_assert (function || !readbuf);
5667 if (mips_debug)
5668 switch (fval_reg)
5669 {
5670 case mips_fval_fpr:
5671 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
5672 break;
5673 case mips_fval_gpr:
5674 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
5675 break;
5676 case mips_fval_both:
5677 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
5678 break;
5679 }
5680 if (fval_reg != mips_fval_gpr)
5681 mips_xfer_register (gdbarch, regcache,
5682 (gdbarch_num_regs (gdbarch)
5683 + mips_regnum (gdbarch)->fp0),
5684 TYPE_LENGTH (type),
5685 gdbarch_byte_order (gdbarch),
5686 readbuf, writebuf, 0);
5687 if (fval_reg != mips_fval_fpr)
5688 mips_xfer_register (gdbarch, regcache,
5689 gdbarch_num_regs (gdbarch) + 2,
5690 TYPE_LENGTH (type),
5691 gdbarch_byte_order (gdbarch),
5692 readbuf, writebuf, 0);
5693 return RETURN_VALUE_REGISTER_CONVENTION;
5694 }
5695 else if (TYPE_CODE (type) == TYPE_CODE_FLT
5696 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5697 {
5698 /* A double-precision floating-point value. If reading in or copying,
5699 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5700 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5701 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5702 no function known, if this safety check ever triggers, then we'll
5703 have to try harder. */
5704 gdb_assert (function || !readbuf);
5705 if (mips_debug)
5706 switch (fval_reg)
5707 {
5708 case mips_fval_fpr:
5709 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
5710 break;
5711 case mips_fval_gpr:
5712 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
5713 break;
5714 case mips_fval_both:
5715 fprintf_unfiltered (gdb_stderr,
5716 "Return float in $fp1/$fp0 and $2/$3\n");
5717 break;
5718 }
5719 if (fval_reg != mips_fval_gpr)
5720 {
5721 /* The most significant part goes in FP1, and the least significant
5722 in FP0. */
5723 switch (gdbarch_byte_order (gdbarch))
5724 {
5725 case BFD_ENDIAN_LITTLE:
5726 mips_xfer_register (gdbarch, regcache,
5727 (gdbarch_num_regs (gdbarch)
5728 + mips_regnum (gdbarch)->fp0 + 0),
5729 4, gdbarch_byte_order (gdbarch),
5730 readbuf, writebuf, 0);
5731 mips_xfer_register (gdbarch, regcache,
5732 (gdbarch_num_regs (gdbarch)
5733 + mips_regnum (gdbarch)->fp0 + 1),
5734 4, gdbarch_byte_order (gdbarch),
5735 readbuf, writebuf, 4);
5736 break;
5737 case BFD_ENDIAN_BIG:
5738 mips_xfer_register (gdbarch, regcache,
5739 (gdbarch_num_regs (gdbarch)
5740 + mips_regnum (gdbarch)->fp0 + 1),
5741 4, gdbarch_byte_order (gdbarch),
5742 readbuf, writebuf, 0);
5743 mips_xfer_register (gdbarch, regcache,
5744 (gdbarch_num_regs (gdbarch)
5745 + mips_regnum (gdbarch)->fp0 + 0),
5746 4, gdbarch_byte_order (gdbarch),
5747 readbuf, writebuf, 4);
5748 break;
5749 default:
5750 internal_error (__FILE__, __LINE__, _("bad switch"));
5751 }
5752 }
5753 if (fval_reg != mips_fval_fpr)
5754 {
5755 /* The two 32-bit parts are always placed in GPR2 and GPR3
5756 following these registers' memory order. */
5757 mips_xfer_register (gdbarch, regcache,
5758 gdbarch_num_regs (gdbarch) + 2,
5759 4, gdbarch_byte_order (gdbarch),
5760 readbuf, writebuf, 0);
5761 mips_xfer_register (gdbarch, regcache,
5762 gdbarch_num_regs (gdbarch) + 3,
5763 4, gdbarch_byte_order (gdbarch),
5764 readbuf, writebuf, 4);
5765 }
5766 return RETURN_VALUE_REGISTER_CONVENTION;
5767 }
5768 #if 0
5769 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5770 && TYPE_NFIELDS (type) <= 2
5771 && TYPE_NFIELDS (type) >= 1
5772 && ((TYPE_NFIELDS (type) == 1
5773 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5774 == TYPE_CODE_FLT))
5775 || (TYPE_NFIELDS (type) == 2
5776 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
5777 == TYPE_CODE_FLT)
5778 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
5779 == TYPE_CODE_FLT)))
5780 && tdep->mips_fpu_type != MIPS_FPU_NONE)
5781 {
5782 /* A struct that contains one or two floats. Each value is part
5783 in the least significant part of their floating point
5784 register.. */
5785 gdb_byte reg[MAX_REGISTER_SIZE];
5786 int regnum;
5787 int field;
5788 for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
5789 field < TYPE_NFIELDS (type); field++, regnum += 2)
5790 {
5791 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
5792 / TARGET_CHAR_BIT);
5793 if (mips_debug)
5794 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
5795 offset);
5796 mips_xfer_register (gdbarch, regcache,
5797 gdbarch_num_regs (gdbarch) + regnum,
5798 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
5799 gdbarch_byte_order (gdbarch),
5800 readbuf, writebuf, offset);
5801 }
5802 return RETURN_VALUE_REGISTER_CONVENTION;
5803 }
5804 #endif
5805 #if 0
5806 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5807 || TYPE_CODE (type) == TYPE_CODE_UNION)
5808 {
5809 /* A structure or union. Extract the left justified value,
5810 regardless of the byte order. I.e. DO NOT USE
5811 mips_xfer_lower. */
5812 int offset;
5813 int regnum;
5814 for (offset = 0, regnum = MIPS_V0_REGNUM;
5815 offset < TYPE_LENGTH (type);
5816 offset += register_size (gdbarch, regnum), regnum++)
5817 {
5818 int xfer = register_size (gdbarch, regnum);
5819 if (offset + xfer > TYPE_LENGTH (type))
5820 xfer = TYPE_LENGTH (type) - offset;
5821 if (mips_debug)
5822 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5823 offset, xfer, regnum);
5824 mips_xfer_register (gdbarch, regcache,
5825 gdbarch_num_regs (gdbarch) + regnum, xfer,
5826 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
5827 }
5828 return RETURN_VALUE_REGISTER_CONVENTION;
5829 }
5830 #endif
5831 else
5832 {
5833 /* A scalar extract each part but least-significant-byte
5834 justified. o32 thinks registers are 4 byte, regardless of
5835 the ISA. */
5836 int offset;
5837 int regnum;
5838 for (offset = 0, regnum = MIPS_V0_REGNUM;
5839 offset < TYPE_LENGTH (type);
5840 offset += MIPS32_REGSIZE, regnum++)
5841 {
5842 int xfer = MIPS32_REGSIZE;
5843 if (offset + xfer > TYPE_LENGTH (type))
5844 xfer = TYPE_LENGTH (type) - offset;
5845 if (mips_debug)
5846 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5847 offset, xfer, regnum);
5848 mips_xfer_register (gdbarch, regcache,
5849 gdbarch_num_regs (gdbarch) + regnum, xfer,
5850 gdbarch_byte_order (gdbarch),
5851 readbuf, writebuf, offset);
5852 }
5853 return RETURN_VALUE_REGISTER_CONVENTION;
5854 }
5855 }
5856
5857 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5858 ABI. */
5859
5860 static CORE_ADDR
5861 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
5862 struct regcache *regcache, CORE_ADDR bp_addr,
5863 int nargs,
5864 struct value **args, CORE_ADDR sp,
5865 int struct_return, CORE_ADDR struct_addr)
5866 {
5867 int argreg;
5868 int float_argreg;
5869 int argnum;
5870 int len = 0;
5871 int stack_offset = 0;
5872 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5873 CORE_ADDR func_addr = find_function_addr (function, NULL);
5874
5875 /* For shared libraries, "t9" needs to point at the function
5876 address. */
5877 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
5878
5879 /* Set the return address register to point to the entry point of
5880 the program, where a breakpoint lies in wait. */
5881 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
5882
5883 /* First ensure that the stack and structure return address (if any)
5884 are properly aligned. The stack has to be at least 64-bit
5885 aligned even on 32-bit machines, because doubles must be 64-bit
5886 aligned. For n32 and n64, stack frames need to be 128-bit
5887 aligned, so we round to this widest known alignment. */
5888
5889 sp = align_down (sp, 16);
5890 struct_addr = align_down (struct_addr, 16);
5891
5892 /* Now make space on the stack for the args. */
5893 for (argnum = 0; argnum < nargs; argnum++)
5894 {
5895 struct type *arg_type = check_typedef (value_type (args[argnum]));
5896
5897 /* Allocate space on the stack. */
5898 len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE);
5899 }
5900 sp -= align_up (len, 16);
5901
5902 if (mips_debug)
5903 fprintf_unfiltered (gdb_stdlog,
5904 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5905 paddress (gdbarch, sp), (long) align_up (len, 16));
5906
5907 /* Initialize the integer and float register pointers. */
5908 argreg = MIPS_A0_REGNUM;
5909 float_argreg = mips_fpa0_regnum (gdbarch);
5910
5911 /* The struct_return pointer occupies the first parameter-passing reg. */
5912 if (struct_return)
5913 {
5914 if (mips_debug)
5915 fprintf_unfiltered (gdb_stdlog,
5916 "mips_o64_push_dummy_call: "
5917 "struct_return reg=%d %s\n",
5918 argreg, paddress (gdbarch, struct_addr));
5919 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
5920 stack_offset += MIPS64_REGSIZE;
5921 }
5922
5923 /* Now load as many as possible of the first arguments into
5924 registers, and push the rest onto the stack. Loop thru args
5925 from first to last. */
5926 for (argnum = 0; argnum < nargs; argnum++)
5927 {
5928 const gdb_byte *val;
5929 struct value *arg = args[argnum];
5930 struct type *arg_type = check_typedef (value_type (arg));
5931 int len = TYPE_LENGTH (arg_type);
5932 enum type_code typecode = TYPE_CODE (arg_type);
5933
5934 if (mips_debug)
5935 fprintf_unfiltered (gdb_stdlog,
5936 "mips_o64_push_dummy_call: %d len=%d type=%d",
5937 argnum + 1, len, (int) typecode);
5938
5939 val = value_contents (arg);
5940
5941 /* Floating point arguments passed in registers have to be
5942 treated specially. On 32-bit architectures, doubles are
5943 passed in register pairs; the even FP register gets the
5944 low word, and the odd FP register gets the high word.
5945 On O64, the first two floating point arguments are also
5946 copied to general registers, because MIPS16 functions
5947 don't use float registers for arguments. This duplication
5948 of arguments in general registers can't hurt non-MIPS16
5949 functions because those registers are normally skipped. */
5950
5951 if (fp_register_arg_p (gdbarch, typecode, arg_type)
5952 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
5953 {
5954 LONGEST regval = extract_unsigned_integer (val, len, byte_order);
5955 if (mips_debug)
5956 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
5957 float_argreg, phex (regval, len));
5958 regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
5959 if (mips_debug)
5960 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
5961 argreg, phex (regval, len));
5962 regcache_cooked_write_unsigned (regcache, argreg, regval);
5963 argreg++;
5964 /* Reserve space for the FP register. */
5965 stack_offset += align_up (len, MIPS64_REGSIZE);
5966 }
5967 else
5968 {
5969 /* Copy the argument to general registers or the stack in
5970 register-sized pieces. Large arguments are split between
5971 registers and stack. */
5972 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5973 are treated specially: Irix cc passes them in registers
5974 where gcc sometimes puts them on the stack. For maximum
5975 compatibility, we will put them in both places. */
5976 int odd_sized_struct = (len > MIPS64_REGSIZE
5977 && len % MIPS64_REGSIZE != 0);
5978 while (len > 0)
5979 {
5980 /* Remember if the argument was written to the stack. */
5981 int stack_used_p = 0;
5982 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
5983
5984 if (mips_debug)
5985 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
5986 partial_len);
5987
5988 /* Write this portion of the argument to the stack. */
5989 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
5990 || odd_sized_struct)
5991 {
5992 /* Should shorter than int integer values be
5993 promoted to int before being stored? */
5994 int longword_offset = 0;
5995 CORE_ADDR addr;
5996 stack_used_p = 1;
5997 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5998 {
5999 if ((typecode == TYPE_CODE_INT
6000 || typecode == TYPE_CODE_PTR
6001 || typecode == TYPE_CODE_FLT)
6002 && len <= 4)
6003 longword_offset = MIPS64_REGSIZE - len;
6004 }
6005
6006 if (mips_debug)
6007 {
6008 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
6009 paddress (gdbarch, stack_offset));
6010 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
6011 paddress (gdbarch, longword_offset));
6012 }
6013
6014 addr = sp + stack_offset + longword_offset;
6015
6016 if (mips_debug)
6017 {
6018 int i;
6019 fprintf_unfiltered (gdb_stdlog, " @%s ",
6020 paddress (gdbarch, addr));
6021 for (i = 0; i < partial_len; i++)
6022 {
6023 fprintf_unfiltered (gdb_stdlog, "%02x",
6024 val[i] & 0xff);
6025 }
6026 }
6027 write_memory (addr, val, partial_len);
6028 }
6029
6030 /* Note!!! This is NOT an else clause. Odd sized
6031 structs may go thru BOTH paths. */
6032 /* Write this portion of the argument to a general
6033 purpose register. */
6034 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
6035 {
6036 LONGEST regval = extract_signed_integer (val, partial_len,
6037 byte_order);
6038 /* Value may need to be sign extended, because
6039 mips_isa_regsize() != mips_abi_regsize(). */
6040
6041 /* A non-floating-point argument being passed in a
6042 general register. If a struct or union, and if
6043 the remaining length is smaller than the register
6044 size, we have to adjust the register value on
6045 big endian targets.
6046
6047 It does not seem to be necessary to do the
6048 same for integral types. */
6049
6050 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
6051 && partial_len < MIPS64_REGSIZE
6052 && (typecode == TYPE_CODE_STRUCT
6053 || typecode == TYPE_CODE_UNION))
6054 regval <<= ((MIPS64_REGSIZE - partial_len)
6055 * TARGET_CHAR_BIT);
6056
6057 if (mips_debug)
6058 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
6059 argreg,
6060 phex (regval, MIPS64_REGSIZE));
6061 regcache_cooked_write_unsigned (regcache, argreg, regval);
6062 argreg++;
6063
6064 /* Prevent subsequent floating point arguments from
6065 being passed in floating point registers. */
6066 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
6067 }
6068
6069 len -= partial_len;
6070 val += partial_len;
6071
6072 /* Compute the offset into the stack at which we will
6073 copy the next parameter.
6074
6075 In older ABIs, the caller reserved space for
6076 registers that contained arguments. This was loosely
6077 refered to as their "home". Consequently, space is
6078 always allocated. */
6079
6080 stack_offset += align_up (partial_len, MIPS64_REGSIZE);
6081 }
6082 }
6083 if (mips_debug)
6084 fprintf_unfiltered (gdb_stdlog, "\n");
6085 }
6086
6087 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
6088
6089 /* Return adjusted stack pointer. */
6090 return sp;
6091 }
6092
6093 static enum return_value_convention
6094 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function,
6095 struct type *type, struct regcache *regcache,
6096 gdb_byte *readbuf, const gdb_byte *writebuf)
6097 {
6098 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
6099 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
6100 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6101 enum mips_fval_reg fval_reg;
6102
6103 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
6104 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
6105 || TYPE_CODE (type) == TYPE_CODE_UNION
6106 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
6107 return RETURN_VALUE_STRUCT_CONVENTION;
6108 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
6109 {
6110 /* A floating-point value. If reading in or copying, then we get it
6111 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6112 If writing out only, then we put it to both FP0 and GPR2. We do
6113 not support reading in with no function known, if this safety
6114 check ever triggers, then we'll have to try harder. */
6115 gdb_assert (function || !readbuf);
6116 if (mips_debug)
6117 switch (fval_reg)
6118 {
6119 case mips_fval_fpr:
6120 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
6121 break;
6122 case mips_fval_gpr:
6123 fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
6124 break;
6125 case mips_fval_both:
6126 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
6127 break;
6128 }
6129 if (fval_reg != mips_fval_gpr)
6130 mips_xfer_register (gdbarch, regcache,
6131 (gdbarch_num_regs (gdbarch)
6132 + mips_regnum (gdbarch)->fp0),
6133 TYPE_LENGTH (type),
6134 gdbarch_byte_order (gdbarch),
6135 readbuf, writebuf, 0);
6136 if (fval_reg != mips_fval_fpr)
6137 mips_xfer_register (gdbarch, regcache,
6138 gdbarch_num_regs (gdbarch) + 2,
6139 TYPE_LENGTH (type),
6140 gdbarch_byte_order (gdbarch),
6141 readbuf, writebuf, 0);
6142 return RETURN_VALUE_REGISTER_CONVENTION;
6143 }
6144 else
6145 {
6146 /* A scalar extract each part but least-significant-byte
6147 justified. */
6148 int offset;
6149 int regnum;
6150 for (offset = 0, regnum = MIPS_V0_REGNUM;
6151 offset < TYPE_LENGTH (type);
6152 offset += MIPS64_REGSIZE, regnum++)
6153 {
6154 int xfer = MIPS64_REGSIZE;
6155 if (offset + xfer > TYPE_LENGTH (type))
6156 xfer = TYPE_LENGTH (type) - offset;
6157 if (mips_debug)
6158 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
6159 offset, xfer, regnum);
6160 mips_xfer_register (gdbarch, regcache,
6161 gdbarch_num_regs (gdbarch) + regnum,
6162 xfer, gdbarch_byte_order (gdbarch),
6163 readbuf, writebuf, offset);
6164 }
6165 return RETURN_VALUE_REGISTER_CONVENTION;
6166 }
6167 }
6168
6169 /* Floating point register management.
6170
6171 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6172 64bit operations, these early MIPS cpus treat fp register pairs
6173 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6174 registers and offer a compatibility mode that emulates the MIPS2 fp
6175 model. When operating in MIPS2 fp compat mode, later cpu's split
6176 double precision floats into two 32-bit chunks and store them in
6177 consecutive fp regs. To display 64-bit floats stored in this
6178 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6179 Throw in user-configurable endianness and you have a real mess.
6180
6181 The way this works is:
6182 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6183 double-precision value will be split across two logical registers.
6184 The lower-numbered logical register will hold the low-order bits,
6185 regardless of the processor's endianness.
6186 - If we are on a 64-bit processor, and we are looking for a
6187 single-precision value, it will be in the low ordered bits
6188 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6189 save slot in memory.
6190 - If we are in 64-bit mode, everything is straightforward.
6191
6192 Note that this code only deals with "live" registers at the top of the
6193 stack. We will attempt to deal with saved registers later, when
6194 the raw/cooked register interface is in place. (We need a general
6195 interface that can deal with dynamic saved register sizes -- fp
6196 regs could be 32 bits wide in one frame and 64 on the frame above
6197 and below). */
6198
6199 /* Copy a 32-bit single-precision value from the current frame
6200 into rare_buffer. */
6201
6202 static void
6203 mips_read_fp_register_single (struct frame_info *frame, int regno,
6204 gdb_byte *rare_buffer)
6205 {
6206 struct gdbarch *gdbarch = get_frame_arch (frame);
6207 int raw_size = register_size (gdbarch, regno);
6208 gdb_byte *raw_buffer = alloca (raw_size);
6209
6210 if (!deprecated_frame_register_read (frame, regno, raw_buffer))
6211 error (_("can't read register %d (%s)"),
6212 regno, gdbarch_register_name (gdbarch, regno));
6213 if (raw_size == 8)
6214 {
6215 /* We have a 64-bit value for this register. Find the low-order
6216 32 bits. */
6217 int offset;
6218
6219 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6220 offset = 4;
6221 else
6222 offset = 0;
6223
6224 memcpy (rare_buffer, raw_buffer + offset, 4);
6225 }
6226 else
6227 {
6228 memcpy (rare_buffer, raw_buffer, 4);
6229 }
6230 }
6231
6232 /* Copy a 64-bit double-precision value from the current frame into
6233 rare_buffer. This may include getting half of it from the next
6234 register. */
6235
6236 static void
6237 mips_read_fp_register_double (struct frame_info *frame, int regno,
6238 gdb_byte *rare_buffer)
6239 {
6240 struct gdbarch *gdbarch = get_frame_arch (frame);
6241 int raw_size = register_size (gdbarch, regno);
6242
6243 if (raw_size == 8 && !mips2_fp_compat (frame))
6244 {
6245 /* We have a 64-bit value for this register, and we should use
6246 all 64 bits. */
6247 if (!deprecated_frame_register_read (frame, regno, rare_buffer))
6248 error (_("can't read register %d (%s)"),
6249 regno, gdbarch_register_name (gdbarch, regno));
6250 }
6251 else
6252 {
6253 int rawnum = regno % gdbarch_num_regs (gdbarch);
6254
6255 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
6256 internal_error (__FILE__, __LINE__,
6257 _("mips_read_fp_register_double: bad access to "
6258 "odd-numbered FP register"));
6259
6260 /* mips_read_fp_register_single will find the correct 32 bits from
6261 each register. */
6262 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6263 {
6264 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
6265 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
6266 }
6267 else
6268 {
6269 mips_read_fp_register_single (frame, regno, rare_buffer);
6270 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
6271 }
6272 }
6273 }
6274
6275 static void
6276 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
6277 int regnum)
6278 { /* Do values for FP (float) regs. */
6279 struct gdbarch *gdbarch = get_frame_arch (frame);
6280 gdb_byte *raw_buffer;
6281 double doub, flt1; /* Doubles extracted from raw hex data. */
6282 int inv1, inv2;
6283
6284 raw_buffer = alloca (2 * register_size (gdbarch,
6285 mips_regnum (gdbarch)->fp0));
6286
6287 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
6288 fprintf_filtered (file, "%*s",
6289 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
6290 "");
6291
6292 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
6293 {
6294 struct value_print_options opts;
6295
6296 /* 4-byte registers: Print hex and floating. Also print even
6297 numbered registers as doubles. */
6298 mips_read_fp_register_single (frame, regnum, raw_buffer);
6299 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6300 raw_buffer, &inv1);
6301
6302 get_formatted_print_options (&opts, 'x');
6303 print_scalar_formatted (raw_buffer,
6304 builtin_type (gdbarch)->builtin_uint32,
6305 &opts, 'w', file);
6306
6307 fprintf_filtered (file, " flt: ");
6308 if (inv1)
6309 fprintf_filtered (file, " <invalid float> ");
6310 else
6311 fprintf_filtered (file, "%-17.9g", flt1);
6312
6313 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
6314 {
6315 mips_read_fp_register_double (frame, regnum, raw_buffer);
6316 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6317 raw_buffer, &inv2);
6318
6319 fprintf_filtered (file, " dbl: ");
6320 if (inv2)
6321 fprintf_filtered (file, "<invalid double>");
6322 else
6323 fprintf_filtered (file, "%-24.17g", doub);
6324 }
6325 }
6326 else
6327 {
6328 struct value_print_options opts;
6329
6330 /* Eight byte registers: print each one as hex, float and double. */
6331 mips_read_fp_register_single (frame, regnum, raw_buffer);
6332 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
6333 raw_buffer, &inv1);
6334
6335 mips_read_fp_register_double (frame, regnum, raw_buffer);
6336 doub = unpack_double (builtin_type (gdbarch)->builtin_double,
6337 raw_buffer, &inv2);
6338
6339 get_formatted_print_options (&opts, 'x');
6340 print_scalar_formatted (raw_buffer,
6341 builtin_type (gdbarch)->builtin_uint64,
6342 &opts, 'g', file);
6343
6344 fprintf_filtered (file, " flt: ");
6345 if (inv1)
6346 fprintf_filtered (file, "<invalid float>");
6347 else
6348 fprintf_filtered (file, "%-17.9g", flt1);
6349
6350 fprintf_filtered (file, " dbl: ");
6351 if (inv2)
6352 fprintf_filtered (file, "<invalid double>");
6353 else
6354 fprintf_filtered (file, "%-24.17g", doub);
6355 }
6356 }
6357
6358 static void
6359 mips_print_register (struct ui_file *file, struct frame_info *frame,
6360 int regnum)
6361 {
6362 struct gdbarch *gdbarch = get_frame_arch (frame);
6363 struct value_print_options opts;
6364 struct value *val;
6365
6366 if (mips_float_register_p (gdbarch, regnum))
6367 {
6368 mips_print_fp_register (file, frame, regnum);
6369 return;
6370 }
6371
6372 val = get_frame_register_value (frame, regnum);
6373
6374 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
6375
6376 /* The problem with printing numeric register names (r26, etc.) is that
6377 the user can't use them on input. Probably the best solution is to
6378 fix it so that either the numeric or the funky (a2, etc.) names
6379 are accepted on input. */
6380 if (regnum < MIPS_NUMREGS)
6381 fprintf_filtered (file, "(r%d): ", regnum);
6382 else
6383 fprintf_filtered (file, ": ");
6384
6385 get_formatted_print_options (&opts, 'x');
6386 val_print_scalar_formatted (value_type (val),
6387 value_contents_for_printing (val),
6388 value_embedded_offset (val),
6389 val,
6390 &opts, 0, file);
6391 }
6392
6393 /* Print IEEE exception condition bits in FLAGS. */
6394
6395 static void
6396 print_fpu_flags (struct ui_file *file, int flags)
6397 {
6398 if (flags & (1 << 0))
6399 fputs_filtered (" inexact", file);
6400 if (flags & (1 << 1))
6401 fputs_filtered (" uflow", file);
6402 if (flags & (1 << 2))
6403 fputs_filtered (" oflow", file);
6404 if (flags & (1 << 3))
6405 fputs_filtered (" div0", file);
6406 if (flags & (1 << 4))
6407 fputs_filtered (" inval", file);
6408 if (flags & (1 << 5))
6409 fputs_filtered (" unimp", file);
6410 fputc_filtered ('\n', file);
6411 }
6412
6413 /* Print interesting information about the floating point processor
6414 (if present) or emulator. */
6415
6416 static void
6417 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
6418 struct frame_info *frame, const char *args)
6419 {
6420 int fcsr = mips_regnum (gdbarch)->fp_control_status;
6421 enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch);
6422 ULONGEST fcs = 0;
6423 int i;
6424
6425 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs))
6426 type = MIPS_FPU_NONE;
6427
6428 fprintf_filtered (file, "fpu type: %s\n",
6429 type == MIPS_FPU_DOUBLE ? "double-precision"
6430 : type == MIPS_FPU_SINGLE ? "single-precision"
6431 : "none / unused");
6432
6433 if (type == MIPS_FPU_NONE)
6434 return;
6435
6436 fprintf_filtered (file, "reg size: %d bits\n",
6437 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
6438
6439 fputs_filtered ("cond :", file);
6440 if (fcs & (1 << 23))
6441 fputs_filtered (" 0", file);
6442 for (i = 1; i <= 7; i++)
6443 if (fcs & (1 << (24 + i)))
6444 fprintf_filtered (file, " %d", i);
6445 fputc_filtered ('\n', file);
6446
6447 fputs_filtered ("cause :", file);
6448 print_fpu_flags (file, (fcs >> 12) & 0x3f);
6449 fputs ("mask :", stdout);
6450 print_fpu_flags (file, (fcs >> 7) & 0x1f);
6451 fputs ("flags :", stdout);
6452 print_fpu_flags (file, (fcs >> 2) & 0x1f);
6453
6454 fputs_filtered ("rounding: ", file);
6455 switch (fcs & 3)
6456 {
6457 case 0: fputs_filtered ("nearest\n", file); break;
6458 case 1: fputs_filtered ("zero\n", file); break;
6459 case 2: fputs_filtered ("+inf\n", file); break;
6460 case 3: fputs_filtered ("-inf\n", file); break;
6461 }
6462
6463 fputs_filtered ("flush :", file);
6464 if (fcs & (1 << 21))
6465 fputs_filtered (" nearest", file);
6466 if (fcs & (1 << 22))
6467 fputs_filtered (" override", file);
6468 if (fcs & (1 << 24))
6469 fputs_filtered (" zero", file);
6470 if ((fcs & (0xb << 21)) == 0)
6471 fputs_filtered (" no", file);
6472 fputc_filtered ('\n', file);
6473
6474 fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
6475 fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
6476 fputc_filtered ('\n', file);
6477
6478 default_print_float_info (gdbarch, file, frame, args);
6479 }
6480
6481 /* Replacement for generic do_registers_info.
6482 Print regs in pretty columns. */
6483
6484 static int
6485 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
6486 int regnum)
6487 {
6488 fprintf_filtered (file, " ");
6489 mips_print_fp_register (file, frame, regnum);
6490 fprintf_filtered (file, "\n");
6491 return regnum + 1;
6492 }
6493
6494
6495 /* Print a row's worth of GP (int) registers, with name labels above. */
6496
6497 static int
6498 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
6499 int start_regnum)
6500 {
6501 struct gdbarch *gdbarch = get_frame_arch (frame);
6502 /* Do values for GP (int) regs. */
6503 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
6504 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols
6505 per row. */
6506 int col, byte;
6507 int regnum;
6508
6509 /* For GP registers, we print a separate row of names above the vals. */
6510 for (col = 0, regnum = start_regnum;
6511 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6512 + gdbarch_num_pseudo_regs (gdbarch);
6513 regnum++)
6514 {
6515 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6516 continue; /* unused register */
6517 if (mips_float_register_p (gdbarch, regnum))
6518 break; /* End the row: reached FP register. */
6519 /* Large registers are handled separately. */
6520 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6521 {
6522 if (col > 0)
6523 break; /* End the row before this register. */
6524
6525 /* Print this register on a row by itself. */
6526 mips_print_register (file, frame, regnum);
6527 fprintf_filtered (file, "\n");
6528 return regnum + 1;
6529 }
6530 if (col == 0)
6531 fprintf_filtered (file, " ");
6532 fprintf_filtered (file,
6533 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
6534 gdbarch_register_name (gdbarch, regnum));
6535 col++;
6536 }
6537
6538 if (col == 0)
6539 return regnum;
6540
6541 /* Print the R0 to R31 names. */
6542 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
6543 fprintf_filtered (file, "\n R%-4d",
6544 start_regnum % gdbarch_num_regs (gdbarch));
6545 else
6546 fprintf_filtered (file, "\n ");
6547
6548 /* Now print the values in hex, 4 or 8 to the row. */
6549 for (col = 0, regnum = start_regnum;
6550 col < ncols && regnum < gdbarch_num_regs (gdbarch)
6551 + gdbarch_num_pseudo_regs (gdbarch);
6552 regnum++)
6553 {
6554 if (*gdbarch_register_name (gdbarch, regnum) == '\0')
6555 continue; /* unused register */
6556 if (mips_float_register_p (gdbarch, regnum))
6557 break; /* End row: reached FP register. */
6558 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
6559 break; /* End row: large register. */
6560
6561 /* OK: get the data in raw format. */
6562 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
6563 error (_("can't read register %d (%s)"),
6564 regnum, gdbarch_register_name (gdbarch, regnum));
6565 /* pad small registers */
6566 for (byte = 0;
6567 byte < (mips_abi_regsize (gdbarch)
6568 - register_size (gdbarch, regnum)); byte++)
6569 printf_filtered (" ");
6570 /* Now print the register value in hex, endian order. */
6571 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
6572 for (byte =
6573 register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
6574 byte < register_size (gdbarch, regnum); byte++)
6575 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6576 else
6577 for (byte = register_size (gdbarch, regnum) - 1;
6578 byte >= 0; byte--)
6579 fprintf_filtered (file, "%02x", raw_buffer[byte]);
6580 fprintf_filtered (file, " ");
6581 col++;
6582 }
6583 if (col > 0) /* ie. if we actually printed anything... */
6584 fprintf_filtered (file, "\n");
6585
6586 return regnum;
6587 }
6588
6589 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6590
6591 static void
6592 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
6593 struct frame_info *frame, int regnum, int all)
6594 {
6595 if (regnum != -1) /* Do one specified register. */
6596 {
6597 gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
6598 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
6599 error (_("Not a valid register for the current processor type"));
6600
6601 mips_print_register (file, frame, regnum);
6602 fprintf_filtered (file, "\n");
6603 }
6604 else
6605 /* Do all (or most) registers. */
6606 {
6607 regnum = gdbarch_num_regs (gdbarch);
6608 while (regnum < gdbarch_num_regs (gdbarch)
6609 + gdbarch_num_pseudo_regs (gdbarch))
6610 {
6611 if (mips_float_register_p (gdbarch, regnum))
6612 {
6613 if (all) /* True for "INFO ALL-REGISTERS" command. */
6614 regnum = print_fp_register_row (file, frame, regnum);
6615 else
6616 regnum += MIPS_NUMREGS; /* Skip floating point regs. */
6617 }
6618 else
6619 regnum = print_gp_register_row (file, frame, regnum);
6620 }
6621 }
6622 }
6623
6624 static int
6625 mips_single_step_through_delay (struct gdbarch *gdbarch,
6626 struct frame_info *frame)
6627 {
6628 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6629 CORE_ADDR pc = get_frame_pc (frame);
6630 struct address_space *aspace;
6631 enum mips_isa isa;
6632 ULONGEST insn;
6633 int status;
6634 int size;
6635
6636 if ((mips_pc_is_mips (pc)
6637 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc))
6638 || (mips_pc_is_micromips (gdbarch, pc)
6639 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0))
6640 || (mips_pc_is_mips16 (gdbarch, pc)
6641 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0)))
6642 return 0;
6643
6644 isa = mips_pc_isa (gdbarch, pc);
6645 /* _has_delay_slot above will have validated the read. */
6646 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
6647 size = mips_insn_size (isa, insn);
6648 aspace = get_frame_address_space (frame);
6649 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
6650 }
6651
6652 /* To skip prologues, I use this predicate. Returns either PC itself
6653 if the code at PC does not look like a function prologue; otherwise
6654 returns an address that (if we're lucky) follows the prologue. If
6655 LENIENT, then we must skip everything which is involved in setting
6656 up the frame (it's OK to skip more, just so long as we don't skip
6657 anything which might clobber the registers which are being saved.
6658 We must skip more in the case where part of the prologue is in the
6659 delay slot of a non-prologue instruction). */
6660
6661 static CORE_ADDR
6662 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
6663 {
6664 CORE_ADDR limit_pc;
6665 CORE_ADDR func_addr;
6666
6667 /* See if we can determine the end of the prologue via the symbol table.
6668 If so, then return either PC, or the PC after the prologue, whichever
6669 is greater. */
6670 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
6671 {
6672 CORE_ADDR post_prologue_pc
6673 = skip_prologue_using_sal (gdbarch, func_addr);
6674 if (post_prologue_pc != 0)
6675 return max (pc, post_prologue_pc);
6676 }
6677
6678 /* Can't determine prologue from the symbol table, need to examine
6679 instructions. */
6680
6681 /* Find an upper limit on the function prologue using the debug
6682 information. If the debug information could not be used to provide
6683 that bound, then use an arbitrary large number as the upper bound. */
6684 limit_pc = skip_prologue_using_sal (gdbarch, pc);
6685 if (limit_pc == 0)
6686 limit_pc = pc + 100; /* Magic. */
6687
6688 if (mips_pc_is_mips16 (gdbarch, pc))
6689 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6690 else if (mips_pc_is_micromips (gdbarch, pc))
6691 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6692 else
6693 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
6694 }
6695
6696 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6697 This is a helper function for mips_stack_frame_destroyed_p. */
6698
6699 static int
6700 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6701 {
6702 CORE_ADDR func_addr = 0, func_end = 0;
6703
6704 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6705 {
6706 /* The MIPS epilogue is max. 12 bytes long. */
6707 CORE_ADDR addr = func_end - 12;
6708
6709 if (addr < func_addr + 4)
6710 addr = func_addr + 4;
6711 if (pc < addr)
6712 return 0;
6713
6714 for (; pc < func_end; pc += MIPS_INSN32_SIZE)
6715 {
6716 unsigned long high_word;
6717 unsigned long inst;
6718
6719 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
6720 high_word = (inst >> 16) & 0xffff;
6721
6722 if (high_word != 0x27bd /* addiu $sp,$sp,offset */
6723 && high_word != 0x67bd /* daddiu $sp,$sp,offset */
6724 && inst != 0x03e00008 /* jr $ra */
6725 && inst != 0x00000000) /* nop */
6726 return 0;
6727 }
6728
6729 return 1;
6730 }
6731
6732 return 0;
6733 }
6734
6735 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6736 This is a helper function for mips_stack_frame_destroyed_p. */
6737
6738 static int
6739 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6740 {
6741 CORE_ADDR func_addr = 0;
6742 CORE_ADDR func_end = 0;
6743 CORE_ADDR addr;
6744 ULONGEST insn;
6745 long offset;
6746 int dreg;
6747 int sreg;
6748 int loc;
6749
6750 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6751 return 0;
6752
6753 /* The microMIPS epilogue is max. 12 bytes long. */
6754 addr = func_end - 12;
6755
6756 if (addr < func_addr + 2)
6757 addr = func_addr + 2;
6758 if (pc < addr)
6759 return 0;
6760
6761 for (; pc < func_end; pc += loc)
6762 {
6763 loc = 0;
6764 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
6765 loc += MIPS_INSN16_SIZE;
6766 switch (mips_insn_size (ISA_MICROMIPS, insn))
6767 {
6768 /* 48-bit instructions. */
6769 case 3 * MIPS_INSN16_SIZE:
6770 /* No epilogue instructions in this category. */
6771 return 0;
6772
6773 /* 32-bit instructions. */
6774 case 2 * MIPS_INSN16_SIZE:
6775 insn <<= 16;
6776 insn |= mips_fetch_instruction (gdbarch,
6777 ISA_MICROMIPS, pc + loc, NULL);
6778 loc += MIPS_INSN16_SIZE;
6779 switch (micromips_op (insn >> 16))
6780 {
6781 case 0xc: /* ADDIU: bits 001100 */
6782 case 0x17: /* DADDIU: bits 010111 */
6783 sreg = b0s5_reg (insn >> 16);
6784 dreg = b5s5_reg (insn >> 16);
6785 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000;
6786 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM
6787 /* (D)ADDIU $sp, imm */
6788 && offset >= 0)
6789 break;
6790 return 0;
6791
6792 default:
6793 return 0;
6794 }
6795 break;
6796
6797 /* 16-bit instructions. */
6798 case MIPS_INSN16_SIZE:
6799 switch (micromips_op (insn))
6800 {
6801 case 0x3: /* MOVE: bits 000011 */
6802 sreg = b0s5_reg (insn);
6803 dreg = b5s5_reg (insn);
6804 if (sreg == 0 && dreg == 0)
6805 /* MOVE $zero, $zero aka NOP */
6806 break;
6807 return 0;
6808
6809 case 0x11: /* POOL16C: bits 010001 */
6810 if (b5s5_op (insn) == 0x18
6811 /* JRADDIUSP: bits 010011 11000 */
6812 || (b5s5_op (insn) == 0xd
6813 /* JRC: bits 010011 01101 */
6814 && b0s5_reg (insn) == MIPS_RA_REGNUM))
6815 /* JRC $ra */
6816 break;
6817 return 0;
6818
6819 case 0x13: /* POOL16D: bits 010011 */
6820 offset = micromips_decode_imm9 (b1s9_imm (insn));
6821 if ((insn & 0x1) == 0x1
6822 /* ADDIUSP: bits 010011 1 */
6823 && offset > 0)
6824 break;
6825 return 0;
6826
6827 default:
6828 return 0;
6829 }
6830 }
6831 }
6832
6833 return 1;
6834 }
6835
6836 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6837 This is a helper function for mips_stack_frame_destroyed_p. */
6838
6839 static int
6840 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6841 {
6842 CORE_ADDR func_addr = 0, func_end = 0;
6843
6844 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
6845 {
6846 /* The MIPS epilogue is max. 12 bytes long. */
6847 CORE_ADDR addr = func_end - 12;
6848
6849 if (addr < func_addr + 4)
6850 addr = func_addr + 4;
6851 if (pc < addr)
6852 return 0;
6853
6854 for (; pc < func_end; pc += MIPS_INSN16_SIZE)
6855 {
6856 unsigned short inst;
6857
6858 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL);
6859
6860 if ((inst & 0xf800) == 0xf000) /* extend */
6861 continue;
6862
6863 if (inst != 0x6300 /* addiu $sp,offset */
6864 && inst != 0xfb00 /* daddiu $sp,$sp,offset */
6865 && inst != 0xe820 /* jr $ra */
6866 && inst != 0xe8a0 /* jrc $ra */
6867 && inst != 0x6500) /* nop */
6868 return 0;
6869 }
6870
6871 return 1;
6872 }
6873
6874 return 0;
6875 }
6876
6877 /* Implement the stack_frame_destroyed_p gdbarch method.
6878
6879 The epilogue is defined here as the area at the end of a function,
6880 after an instruction which destroys the function's stack frame. */
6881
6882 static int
6883 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
6884 {
6885 if (mips_pc_is_mips16 (gdbarch, pc))
6886 return mips16_stack_frame_destroyed_p (gdbarch, pc);
6887 else if (mips_pc_is_micromips (gdbarch, pc))
6888 return micromips_stack_frame_destroyed_p (gdbarch, pc);
6889 else
6890 return mips32_stack_frame_destroyed_p (gdbarch, pc);
6891 }
6892
6893 /* Root of all "set mips "/"show mips " commands. This will eventually be
6894 used for all MIPS-specific commands. */
6895
6896 static void
6897 show_mips_command (char *args, int from_tty)
6898 {
6899 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
6900 }
6901
6902 static void
6903 set_mips_command (char *args, int from_tty)
6904 {
6905 printf_unfiltered
6906 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6907 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
6908 }
6909
6910 /* Commands to show/set the MIPS FPU type. */
6911
6912 static void
6913 show_mipsfpu_command (char *args, int from_tty)
6914 {
6915 char *fpu;
6916
6917 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
6918 {
6919 printf_unfiltered
6920 ("The MIPS floating-point coprocessor is unknown "
6921 "because the current architecture is not MIPS.\n");
6922 return;
6923 }
6924
6925 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6926 {
6927 case MIPS_FPU_SINGLE:
6928 fpu = "single-precision";
6929 break;
6930 case MIPS_FPU_DOUBLE:
6931 fpu = "double-precision";
6932 break;
6933 case MIPS_FPU_NONE:
6934 fpu = "absent (none)";
6935 break;
6936 default:
6937 internal_error (__FILE__, __LINE__, _("bad switch"));
6938 }
6939 if (mips_fpu_type_auto)
6940 printf_unfiltered ("The MIPS floating-point coprocessor "
6941 "is set automatically (currently %s)\n",
6942 fpu);
6943 else
6944 printf_unfiltered
6945 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
6946 }
6947
6948
6949 static void
6950 set_mipsfpu_command (char *args, int from_tty)
6951 {
6952 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6953 "\"single\",\"none\" or \"auto\".\n");
6954 show_mipsfpu_command (args, from_tty);
6955 }
6956
6957 static void
6958 set_mipsfpu_single_command (char *args, int from_tty)
6959 {
6960 struct gdbarch_info info;
6961 gdbarch_info_init (&info);
6962 mips_fpu_type = MIPS_FPU_SINGLE;
6963 mips_fpu_type_auto = 0;
6964 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6965 instead of relying on globals. Doing that would let generic code
6966 handle the search for this specific architecture. */
6967 if (!gdbarch_update_p (info))
6968 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6969 }
6970
6971 static void
6972 set_mipsfpu_double_command (char *args, int from_tty)
6973 {
6974 struct gdbarch_info info;
6975 gdbarch_info_init (&info);
6976 mips_fpu_type = MIPS_FPU_DOUBLE;
6977 mips_fpu_type_auto = 0;
6978 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6979 instead of relying on globals. Doing that would let generic code
6980 handle the search for this specific architecture. */
6981 if (!gdbarch_update_p (info))
6982 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6983 }
6984
6985 static void
6986 set_mipsfpu_none_command (char *args, int from_tty)
6987 {
6988 struct gdbarch_info info;
6989 gdbarch_info_init (&info);
6990 mips_fpu_type = MIPS_FPU_NONE;
6991 mips_fpu_type_auto = 0;
6992 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6993 instead of relying on globals. Doing that would let generic code
6994 handle the search for this specific architecture. */
6995 if (!gdbarch_update_p (info))
6996 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
6997 }
6998
6999 static void
7000 set_mipsfpu_auto_command (char *args, int from_tty)
7001 {
7002 mips_fpu_type_auto = 1;
7003 }
7004
7005 /* Attempt to identify the particular processor model by reading the
7006 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
7007 the relevant processor still exists (it dates back to '94) and
7008 secondly this is not the way to do this. The processor type should
7009 be set by forcing an architecture change. */
7010
7011 void
7012 deprecated_mips_set_processor_regs_hack (void)
7013 {
7014 struct regcache *regcache = get_current_regcache ();
7015 struct gdbarch *gdbarch = get_regcache_arch (regcache);
7016 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7017 ULONGEST prid;
7018
7019 regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
7020 if ((prid & ~0xf) == 0x700)
7021 tdep->mips_processor_reg_names = mips_r3041_reg_names;
7022 }
7023
7024 /* Just like reinit_frame_cache, but with the right arguments to be
7025 callable as an sfunc. */
7026
7027 static void
7028 reinit_frame_cache_sfunc (char *args, int from_tty,
7029 struct cmd_list_element *c)
7030 {
7031 reinit_frame_cache ();
7032 }
7033
7034 static int
7035 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
7036 {
7037 struct gdbarch *gdbarch = info->application_data;
7038
7039 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7040 disassembler needs to be able to locally determine the ISA, and
7041 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7042 work. */
7043 if (mips_pc_is_mips16 (gdbarch, memaddr))
7044 info->mach = bfd_mach_mips16;
7045 else if (mips_pc_is_micromips (gdbarch, memaddr))
7046 info->mach = bfd_mach_mips_micromips;
7047
7048 /* Round down the instruction address to the appropriate boundary. */
7049 memaddr &= (info->mach == bfd_mach_mips16
7050 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
7051
7052 /* Set the disassembler options. */
7053 if (!info->disassembler_options)
7054 /* This string is not recognized explicitly by the disassembler,
7055 but it tells the disassembler to not try to guess the ABI from
7056 the bfd elf headers, such that, if the user overrides the ABI
7057 of a program linked as NewABI, the disassembly will follow the
7058 register naming conventions specified by the user. */
7059 info->disassembler_options = "gpr-names=32";
7060
7061 /* Call the appropriate disassembler based on the target endian-ness. */
7062 if (info->endian == BFD_ENDIAN_BIG)
7063 return print_insn_big_mips (memaddr, info);
7064 else
7065 return print_insn_little_mips (memaddr, info);
7066 }
7067
7068 static int
7069 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
7070 {
7071 /* Set up the disassembler info, so that we get the right
7072 register names from libopcodes. */
7073 info->disassembler_options = "gpr-names=n32";
7074 info->flavour = bfd_target_elf_flavour;
7075
7076 return gdb_print_insn_mips (memaddr, info);
7077 }
7078
7079 static int
7080 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
7081 {
7082 /* Set up the disassembler info, so that we get the right
7083 register names from libopcodes. */
7084 info->disassembler_options = "gpr-names=64";
7085 info->flavour = bfd_target_elf_flavour;
7086
7087 return gdb_print_insn_mips (memaddr, info);
7088 }
7089
7090 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7091 program counter value to determine whether a 16- or 32-bit breakpoint
7092 should be used. It returns a pointer to a string of bytes that encode a
7093 breakpoint instruction, stores the length of the string to *lenptr, and
7094 adjusts pc (if necessary) to point to the actual memory location where
7095 the breakpoint should be inserted. */
7096
7097 static const gdb_byte *
7098 mips_breakpoint_from_pc (struct gdbarch *gdbarch,
7099 CORE_ADDR *pcptr, int *lenptr)
7100 {
7101 CORE_ADDR pc = *pcptr;
7102
7103 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
7104 {
7105 if (mips_pc_is_mips16 (gdbarch, pc))
7106 {
7107 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
7108 *pcptr = unmake_compact_addr (pc);
7109 *lenptr = sizeof (mips16_big_breakpoint);
7110 return mips16_big_breakpoint;
7111 }
7112 else if (mips_pc_is_micromips (gdbarch, pc))
7113 {
7114 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 };
7115 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 };
7116 ULONGEST insn;
7117 int status;
7118 int size;
7119
7120 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
7121 size = status ? 2
7122 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
7123 *pcptr = unmake_compact_addr (pc);
7124 *lenptr = size;
7125 return (size == 2) ? micromips16_big_breakpoint
7126 : micromips32_big_breakpoint;
7127 }
7128 else
7129 {
7130 /* The IDT board uses an unusual breakpoint value, and
7131 sometimes gets confused when it sees the usual MIPS
7132 breakpoint instruction. */
7133 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
7134 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
7135 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
7136 /* Likewise, IRIX appears to expect a different breakpoint,
7137 although this is not apparent until you try to use pthreads. */
7138 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd };
7139
7140 *lenptr = sizeof (big_breakpoint);
7141
7142 if (strcmp (target_shortname, "mips") == 0)
7143 return idt_big_breakpoint;
7144 else if (strcmp (target_shortname, "ddb") == 0
7145 || strcmp (target_shortname, "pmon") == 0
7146 || strcmp (target_shortname, "lsi") == 0)
7147 return pmon_big_breakpoint;
7148 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX)
7149 return irix_big_breakpoint;
7150 else
7151 return big_breakpoint;
7152 }
7153 }
7154 else
7155 {
7156 if (mips_pc_is_mips16 (gdbarch, pc))
7157 {
7158 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
7159 *pcptr = unmake_compact_addr (pc);
7160 *lenptr = sizeof (mips16_little_breakpoint);
7161 return mips16_little_breakpoint;
7162 }
7163 else if (mips_pc_is_micromips (gdbarch, pc))
7164 {
7165 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 };
7166 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 };
7167 ULONGEST insn;
7168 int status;
7169 int size;
7170
7171 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
7172 size = status ? 2
7173 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
7174 *pcptr = unmake_compact_addr (pc);
7175 *lenptr = size;
7176 return (size == 2) ? micromips16_little_breakpoint
7177 : micromips32_little_breakpoint;
7178 }
7179 else
7180 {
7181 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
7182 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
7183 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
7184
7185 *lenptr = sizeof (little_breakpoint);
7186
7187 if (strcmp (target_shortname, "mips") == 0)
7188 return idt_little_breakpoint;
7189 else if (strcmp (target_shortname, "ddb") == 0
7190 || strcmp (target_shortname, "pmon") == 0
7191 || strcmp (target_shortname, "lsi") == 0)
7192 return pmon_little_breakpoint;
7193 else
7194 return little_breakpoint;
7195 }
7196 }
7197 }
7198
7199 /* Determine the remote breakpoint kind suitable for the PC. The following
7200 kinds are used:
7201
7202 * 2 -- 16-bit MIPS16 mode breakpoint,
7203
7204 * 3 -- 16-bit microMIPS mode breakpoint,
7205
7206 * 4 -- 32-bit standard MIPS mode breakpoint,
7207
7208 * 5 -- 32-bit microMIPS mode breakpoint. */
7209
7210 static void
7211 mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
7212 int *kindptr)
7213 {
7214 CORE_ADDR pc = *pcptr;
7215
7216 if (mips_pc_is_mips16 (gdbarch, pc))
7217 {
7218 *pcptr = unmake_compact_addr (pc);
7219 *kindptr = 2;
7220 }
7221 else if (mips_pc_is_micromips (gdbarch, pc))
7222 {
7223 ULONGEST insn;
7224 int status;
7225 int size;
7226
7227 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status);
7228 size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4;
7229 *pcptr = unmake_compact_addr (pc);
7230 *kindptr = size | 1;
7231 }
7232 else
7233 *kindptr = 4;
7234 }
7235
7236 /* Return non-zero if the standard MIPS instruction INST has a branch
7237 delay slot (i.e. it is a jump or branch instruction). This function
7238 is based on mips32_next_pc. */
7239
7240 static int
7241 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst)
7242 {
7243 int op;
7244 int rs;
7245 int rt;
7246
7247 op = itype_op (inst);
7248 if ((inst & 0xe0000000) != 0)
7249 {
7250 rs = itype_rs (inst);
7251 rt = itype_rt (inst);
7252 return (is_octeon_bbit_op (op, gdbarch)
7253 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7254 || op == 29 /* JALX: bits 011101 */
7255 || (op == 17
7256 && (rs == 8
7257 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7258 || (rs == 9 && (rt & 0x2) == 0)
7259 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7260 || (rs == 10 && (rt & 0x2) == 0))));
7261 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7262 }
7263 else
7264 switch (op & 0x07) /* extract bits 28,27,26 */
7265 {
7266 case 0: /* SPECIAL */
7267 op = rtype_funct (inst);
7268 return (op == 8 /* JR */
7269 || op == 9); /* JALR */
7270 break; /* end SPECIAL */
7271 case 1: /* REGIMM */
7272 rs = itype_rs (inst);
7273 rt = itype_rt (inst); /* branch condition */
7274 return ((rt & 0xc) == 0
7275 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7276 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7277 || ((rt & 0x1e) == 0x1c && rs == 0));
7278 /* BPOSGE32, BPOSGE64: bits 1110x */
7279 break; /* end REGIMM */
7280 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7281 return 1;
7282 break;
7283 }
7284 }
7285
7286 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7287 delay slot (i.e. it is a jump or branch instruction). */
7288
7289 static int
7290 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr)
7291 {
7292 ULONGEST insn;
7293 int status;
7294
7295 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status);
7296 if (status)
7297 return 0;
7298
7299 return mips32_instruction_has_delay_slot (gdbarch, insn);
7300 }
7301
7302 /* Return non-zero if the microMIPS instruction INSN, comprising the
7303 16-bit major opcode word in the high 16 bits and any second word
7304 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7305 jump or branch instruction). The instruction must be 32-bit if
7306 MUSTBE32 is set or can be any instruction otherwise. */
7307
7308 static int
7309 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32)
7310 {
7311 ULONGEST major = insn >> 16;
7312
7313 switch (micromips_op (major))
7314 {
7315 /* 16-bit instructions. */
7316 case 0x33: /* B16: bits 110011 */
7317 case 0x2b: /* BNEZ16: bits 101011 */
7318 case 0x23: /* BEQZ16: bits 100011 */
7319 return !mustbe32;
7320 case 0x11: /* POOL16C: bits 010001 */
7321 return (!mustbe32
7322 && ((b5s5_op (major) == 0xc
7323 /* JR16: bits 010001 01100 */
7324 || (b5s5_op (major) & 0x1e) == 0xe)));
7325 /* JALR16, JALRS16: bits 010001 0111x */
7326 /* 32-bit instructions. */
7327 case 0x3d: /* JAL: bits 111101 */
7328 case 0x3c: /* JALX: bits 111100 */
7329 case 0x35: /* J: bits 110101 */
7330 case 0x2d: /* BNE: bits 101101 */
7331 case 0x25: /* BEQ: bits 100101 */
7332 case 0x1d: /* JALS: bits 011101 */
7333 return 1;
7334 case 0x10: /* POOL32I: bits 010000 */
7335 return ((b5s5_op (major) & 0x1c) == 0x0
7336 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7337 || (b5s5_op (major) & 0x1d) == 0x4
7338 /* BLEZ, BGTZ: bits 010000 001x0 */
7339 || (b5s5_op (major) & 0x1d) == 0x11
7340 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7341 || ((b5s5_op (major) & 0x1e) == 0x14
7342 && (major & 0x3) == 0x0)
7343 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7344 || (b5s5_op (major) & 0x1e) == 0x1a
7345 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7346 || ((b5s5_op (major) & 0x1e) == 0x1c
7347 && (major & 0x3) == 0x0)
7348 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7349 || ((b5s5_op (major) & 0x1c) == 0x1c
7350 && (major & 0x3) == 0x1));
7351 /* BC1ANY*: bits 010000 111xx xxx01 */
7352 case 0x0: /* POOL32A: bits 000000 */
7353 return (b0s6_op (insn) == 0x3c
7354 /* POOL32Axf: bits 000000 ... 111100 */
7355 && (b6s10_ext (insn) & 0x2bf) == 0x3c);
7356 /* JALR, JALR.HB: 000000 000x111100 111100 */
7357 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7358 default:
7359 return 0;
7360 }
7361 }
7362
7363 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7364 slot (i.e. it is a non-compact jump instruction). The instruction
7365 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7366
7367 static int
7368 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7369 CORE_ADDR addr, int mustbe32)
7370 {
7371 ULONGEST insn;
7372 int status;
7373
7374 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7375 if (status)
7376 return 0;
7377 insn <<= 16;
7378 if (mips_insn_size (ISA_MICROMIPS, insn) == 2 * MIPS_INSN16_SIZE)
7379 {
7380 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status);
7381 if (status)
7382 return 0;
7383 }
7384
7385 return micromips_instruction_has_delay_slot (insn, mustbe32);
7386 }
7387
7388 /* Return non-zero if the MIPS16 instruction INST, which must be
7389 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7390 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7391 instruction). This function is based on mips16_next_pc. */
7392
7393 static int
7394 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32)
7395 {
7396 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7397 return !mustbe32;
7398 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7399 }
7400
7401 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7402 slot (i.e. it is a non-compact jump instruction). The instruction
7403 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7404
7405 static int
7406 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
7407 CORE_ADDR addr, int mustbe32)
7408 {
7409 unsigned short insn;
7410 int status;
7411
7412 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status);
7413 if (status)
7414 return 0;
7415
7416 return mips16_instruction_has_delay_slot (insn, mustbe32);
7417 }
7418
7419 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7420 This assumes KSSEG exists. */
7421
7422 static CORE_ADDR
7423 mips_segment_boundary (CORE_ADDR bpaddr)
7424 {
7425 CORE_ADDR mask = CORE_ADDR_MAX;
7426 int segsize;
7427
7428 if (sizeof (CORE_ADDR) == 8)
7429 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7430 a compiler warning produced where CORE_ADDR is a 32-bit type even
7431 though in that case this is dead code). */
7432 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3)
7433 {
7434 case 3:
7435 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr)
7436 segsize = 29; /* 32-bit compatibility segment */
7437 else
7438 segsize = 62; /* xkseg */
7439 break;
7440 case 2: /* xkphys */
7441 segsize = 59;
7442 break;
7443 default: /* xksseg (1), xkuseg/kuseg (0) */
7444 segsize = 62;
7445 break;
7446 }
7447 else if (bpaddr & 0x80000000) /* kernel segment */
7448 segsize = 29;
7449 else
7450 segsize = 31; /* user segment */
7451 mask <<= segsize;
7452 return bpaddr & mask;
7453 }
7454
7455 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7456 it backwards if necessary. Return the address of the new location. */
7457
7458 static CORE_ADDR
7459 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
7460 {
7461 CORE_ADDR prev_addr;
7462 CORE_ADDR boundary;
7463 CORE_ADDR func_addr;
7464
7465 /* If a breakpoint is set on the instruction in a branch delay slot,
7466 GDB gets confused. When the breakpoint is hit, the PC isn't on
7467 the instruction in the branch delay slot, the PC will point to
7468 the branch instruction. Since the PC doesn't match any known
7469 breakpoints, GDB reports a trap exception.
7470
7471 There are two possible fixes for this problem.
7472
7473 1) When the breakpoint gets hit, see if the BD bit is set in the
7474 Cause register (which indicates the last exception occurred in a
7475 branch delay slot). If the BD bit is set, fix the PC to point to
7476 the instruction in the branch delay slot.
7477
7478 2) When the user sets the breakpoint, don't allow him to set the
7479 breakpoint on the instruction in the branch delay slot. Instead
7480 move the breakpoint to the branch instruction (which will have
7481 the same result).
7482
7483 The problem with the first solution is that if the user then
7484 single-steps the processor, the branch instruction will get
7485 skipped (since GDB thinks the PC is on the instruction in the
7486 branch delay slot).
7487
7488 So, we'll use the second solution. To do this we need to know if
7489 the instruction we're trying to set the breakpoint on is in the
7490 branch delay slot. */
7491
7492 boundary = mips_segment_boundary (bpaddr);
7493
7494 /* Make sure we don't scan back before the beginning of the current
7495 function, since we may fetch constant data or insns that look like
7496 a jump. Of course we might do that anyway if the compiler has
7497 moved constants inline. :-( */
7498 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL)
7499 && func_addr > boundary && func_addr <= bpaddr)
7500 boundary = func_addr;
7501
7502 if (mips_pc_is_mips (bpaddr))
7503 {
7504 if (bpaddr == boundary)
7505 return bpaddr;
7506
7507 /* If the previous instruction has a branch delay slot, we have
7508 to move the breakpoint to the branch instruction. */
7509 prev_addr = bpaddr - 4;
7510 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))
7511 bpaddr = prev_addr;
7512 }
7513 else
7514 {
7515 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int);
7516 CORE_ADDR addr, jmpaddr;
7517 int i;
7518
7519 boundary = unmake_compact_addr (boundary);
7520
7521 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7522 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7523 so try for that first, then try the 2 byte JALR/JR.
7524 The microMIPS ASE has a whole range of jumps and branches
7525 with delay slots, some of which take 4 bytes and some take
7526 2 bytes, so the idea is the same.
7527 FIXME: We have to assume that bpaddr is not the second half
7528 of an extended instruction. */
7529 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
7530 ? micromips_insn_at_pc_has_delay_slot
7531 : mips16_insn_at_pc_has_delay_slot);
7532
7533 jmpaddr = 0;
7534 addr = bpaddr;
7535 for (i = 1; i < 4; i++)
7536 {
7537 if (unmake_compact_addr (addr) == boundary)
7538 break;
7539 addr -= MIPS_INSN16_SIZE;
7540 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0))
7541 /* Looks like a JR/JALR at [target-1], but it could be
7542 the second word of a previous JAL/JALX, so record it
7543 and check back one more. */
7544 jmpaddr = addr;
7545 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1))
7546 {
7547 if (i == 2)
7548 /* Looks like a JAL/JALX at [target-2], but it could also
7549 be the second word of a previous JAL/JALX, record it,
7550 and check back one more. */
7551 jmpaddr = addr;
7552 else
7553 /* Looks like a JAL/JALX at [target-3], so any previously
7554 recorded JAL/JALX or JR/JALR must be wrong, because:
7555
7556 >-3: JAL
7557 -2: JAL-ext (can't be JAL/JALX)
7558 -1: bdslot (can't be JR/JALR)
7559 0: target insn
7560
7561 Of course it could be another JAL-ext which looks
7562 like a JAL, but in that case we'd have broken out
7563 of this loop at [target-2]:
7564
7565 -4: JAL
7566 >-3: JAL-ext
7567 -2: bdslot (can't be jmp)
7568 -1: JR/JALR
7569 0: target insn */
7570 jmpaddr = 0;
7571 }
7572 else
7573 {
7574 /* Not a jump instruction: if we're at [target-1] this
7575 could be the second word of a JAL/JALX, so continue;
7576 otherwise we're done. */
7577 if (i > 1)
7578 break;
7579 }
7580 }
7581
7582 if (jmpaddr)
7583 bpaddr = jmpaddr;
7584 }
7585
7586 return bpaddr;
7587 }
7588
7589 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7590 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7591
7592 static int
7593 mips_is_stub_suffix (const char *suffix, int zero)
7594 {
7595 switch (suffix[0])
7596 {
7597 case '0':
7598 return zero && suffix[1] == '\0';
7599 case '1':
7600 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0');
7601 case '2':
7602 case '5':
7603 case '6':
7604 case '9':
7605 return suffix[1] == '\0';
7606 default:
7607 return 0;
7608 }
7609 }
7610
7611 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7612 call stubs, one of sf, df, sc, or dc. */
7613
7614 static int
7615 mips_is_stub_mode (const char *mode)
7616 {
7617 return ((mode[0] == 's' || mode[0] == 'd')
7618 && (mode[1] == 'f' || mode[1] == 'c'));
7619 }
7620
7621 /* Code at PC is a compiler-generated stub. Such a stub for a function
7622 bar might have a name like __fn_stub_bar, and might look like this:
7623
7624 mfc1 $4, $f13
7625 mfc1 $5, $f12
7626 mfc1 $6, $f15
7627 mfc1 $7, $f14
7628
7629 followed by (or interspersed with):
7630
7631 j bar
7632
7633 or:
7634
7635 lui $25, %hi(bar)
7636 addiu $25, $25, %lo(bar)
7637 jr $25
7638
7639 ($1 may be used in old code; for robustness we accept any register)
7640 or, in PIC code:
7641
7642 lui $28, %hi(_gp_disp)
7643 addiu $28, $28, %lo(_gp_disp)
7644 addu $28, $28, $25
7645 lw $25, %got(bar)
7646 addiu $25, $25, %lo(bar)
7647 jr $25
7648
7649 In the case of a __call_stub_bar stub, the sequence to set up
7650 arguments might look like this:
7651
7652 mtc1 $4, $f13
7653 mtc1 $5, $f12
7654 mtc1 $6, $f15
7655 mtc1 $7, $f14
7656
7657 followed by (or interspersed with) one of the jump sequences above.
7658
7659 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7660 of J or JR, respectively, followed by:
7661
7662 mfc1 $2, $f0
7663 mfc1 $3, $f1
7664 jr $18
7665
7666 We are at the beginning of the stub here, and scan down and extract
7667 the target address from the jump immediate instruction or, if a jump
7668 register instruction is used, from the register referred. Return
7669 the value of PC calculated or 0 if inconclusive.
7670
7671 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7672
7673 static CORE_ADDR
7674 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
7675 {
7676 struct gdbarch *gdbarch = get_frame_arch (frame);
7677 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7678 int addrreg = MIPS_ZERO_REGNUM;
7679 CORE_ADDR start_pc = pc;
7680 CORE_ADDR target_pc = 0;
7681 CORE_ADDR addr = 0;
7682 CORE_ADDR gp = 0;
7683 int status = 0;
7684 int i;
7685
7686 for (i = 0;
7687 status == 0 && target_pc == 0 && i < 20;
7688 i++, pc += MIPS_INSN32_SIZE)
7689 {
7690 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
7691 CORE_ADDR imm;
7692 int rt;
7693 int rs;
7694 int rd;
7695
7696 switch (itype_op (inst))
7697 {
7698 case 0: /* SPECIAL */
7699 switch (rtype_funct (inst))
7700 {
7701 case 8: /* JR */
7702 case 9: /* JALR */
7703 rs = rtype_rs (inst);
7704 if (rs == MIPS_GP_REGNUM)
7705 target_pc = gp; /* Hmm... */
7706 else if (rs == addrreg)
7707 target_pc = addr;
7708 break;
7709
7710 case 0x21: /* ADDU */
7711 rt = rtype_rt (inst);
7712 rs = rtype_rs (inst);
7713 rd = rtype_rd (inst);
7714 if (rd == MIPS_GP_REGNUM
7715 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM)
7716 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM)))
7717 gp += start_pc;
7718 break;
7719 }
7720 break;
7721
7722 case 2: /* J */
7723 case 3: /* JAL */
7724 target_pc = jtype_target (inst) << 2;
7725 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
7726 break;
7727
7728 case 9: /* ADDIU */
7729 rt = itype_rt (inst);
7730 rs = itype_rs (inst);
7731 if (rt == rs)
7732 {
7733 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7734 if (rt == MIPS_GP_REGNUM)
7735 gp += imm;
7736 else if (rt == addrreg)
7737 addr += imm;
7738 }
7739 break;
7740
7741 case 0xf: /* LUI */
7742 rt = itype_rt (inst);
7743 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16;
7744 if (rt == MIPS_GP_REGNUM)
7745 gp = imm;
7746 else if (rt != MIPS_ZERO_REGNUM)
7747 {
7748 addrreg = rt;
7749 addr = imm;
7750 }
7751 break;
7752
7753 case 0x23: /* LW */
7754 rt = itype_rt (inst);
7755 rs = itype_rs (inst);
7756 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000;
7757 if (gp != 0 && rs == MIPS_GP_REGNUM)
7758 {
7759 gdb_byte buf[4];
7760
7761 memset (buf, 0, sizeof (buf));
7762 status = target_read_memory (gp + imm, buf, sizeof (buf));
7763 addrreg = rt;
7764 addr = extract_signed_integer (buf, sizeof (buf), byte_order);
7765 }
7766 break;
7767 }
7768 }
7769
7770 return target_pc;
7771 }
7772
7773 /* If PC is in a MIPS16 call or return stub, return the address of the
7774 target PC, which is either the callee or the caller. There are several
7775 cases which must be handled:
7776
7777 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7778 and the target PC is in $31 ($ra).
7779 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7780 and the target PC is in $2.
7781 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7782 i.e. before the JALR instruction, this is effectively a call stub
7783 and the target PC is in $2. Otherwise this is effectively
7784 a return stub and the target PC is in $18.
7785 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7786 JAL or JALR instruction, this is effectively a call stub and the
7787 target PC is buried in the instruction stream. Otherwise this
7788 is effectively a return stub and the target PC is in $18.
7789 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7790 stub and the target PC is buried in the instruction stream.
7791
7792 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7793 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7794 gory details. */
7795
7796 static CORE_ADDR
7797 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7798 {
7799 struct gdbarch *gdbarch = get_frame_arch (frame);
7800 CORE_ADDR start_addr;
7801 const char *name;
7802 size_t prefixlen;
7803
7804 /* Find the starting address and name of the function containing the PC. */
7805 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
7806 return 0;
7807
7808 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7809 and the target PC is in $31 ($ra). */
7810 prefixlen = strlen (mips_str_mips16_ret_stub);
7811 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7812 && mips_is_stub_mode (name + prefixlen)
7813 && name[prefixlen + 2] == '\0')
7814 return get_frame_register_signed
7815 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM);
7816
7817 /* If the PC is in __mips16_call_stub_*, this is one of the call
7818 call/return stubs. */
7819 prefixlen = strlen (mips_str_mips16_call_stub);
7820 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
7821 {
7822 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7823 and the target PC is in $2. */
7824 if (mips_is_stub_suffix (name + prefixlen, 0))
7825 return get_frame_register_signed
7826 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7827
7828 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7829 i.e. before the JALR instruction, this is effectively a call stub
7830 and the target PC is in $2. Otherwise this is effectively
7831 a return stub and the target PC is in $18. */
7832 else if (mips_is_stub_mode (name + prefixlen)
7833 && name[prefixlen + 2] == '_'
7834 && mips_is_stub_suffix (name + prefixlen + 3, 0))
7835 {
7836 if (pc == start_addr)
7837 /* This is the 'call' part of a call stub. The return
7838 address is in $2. */
7839 return get_frame_register_signed
7840 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
7841 else
7842 /* This is the 'return' part of a call stub. The return
7843 address is in $18. */
7844 return get_frame_register_signed
7845 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7846 }
7847 else
7848 return 0; /* Not a stub. */
7849 }
7850
7851 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7852 compiler-generated call or call/return stubs. */
7853 if (startswith (name, mips_str_fn_stub)
7854 || startswith (name, mips_str_call_stub))
7855 {
7856 if (pc == start_addr)
7857 /* This is the 'call' part of a call stub. Call this helper
7858 to scan through this code for interesting instructions
7859 and determine the final PC. */
7860 return mips_get_mips16_fn_stub_pc (frame, pc);
7861 else
7862 /* This is the 'return' part of a call stub. The return address
7863 is in $18. */
7864 return get_frame_register_signed
7865 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM);
7866 }
7867
7868 return 0; /* Not a stub. */
7869 }
7870
7871 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7872 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7873
7874 static int
7875 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
7876 {
7877 CORE_ADDR start_addr;
7878 size_t prefixlen;
7879
7880 /* Find the starting address of the function containing the PC. */
7881 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
7882 return 0;
7883
7884 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7885 the start, i.e. after the JALR instruction, this is effectively
7886 a return stub. */
7887 prefixlen = strlen (mips_str_mips16_call_stub);
7888 if (pc != start_addr
7889 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0
7890 && mips_is_stub_mode (name + prefixlen)
7891 && name[prefixlen + 2] == '_'
7892 && mips_is_stub_suffix (name + prefixlen + 3, 1))
7893 return 1;
7894
7895 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7896 the JAL or JALR instruction, this is effectively a return stub. */
7897 prefixlen = strlen (mips_str_call_fp_stub);
7898 if (pc != start_addr
7899 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0)
7900 return 1;
7901
7902 /* Consume the .pic. prefix of any PIC stub, this function must return
7903 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7904 or the call stub path will trigger in handle_inferior_event causing
7905 it to go astray. */
7906 prefixlen = strlen (mips_str_pic);
7907 if (strncmp (name, mips_str_pic, prefixlen) == 0)
7908 name += prefixlen;
7909
7910 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7911 prefixlen = strlen (mips_str_mips16_ret_stub);
7912 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0
7913 && mips_is_stub_mode (name + prefixlen)
7914 && name[prefixlen + 2] == '\0')
7915 return 1;
7916
7917 return 0; /* Not a stub. */
7918 }
7919
7920 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7921 PC of the stub target. The stub just loads $t9 and jumps to it,
7922 so that $t9 has the correct value at function entry. */
7923
7924 static CORE_ADDR
7925 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7926 {
7927 struct gdbarch *gdbarch = get_frame_arch (frame);
7928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7929 struct bound_minimal_symbol msym;
7930 int i;
7931 gdb_byte stub_code[16];
7932 int32_t stub_words[4];
7933
7934 /* The stub for foo is named ".pic.foo", and is either two
7935 instructions inserted before foo or a three instruction sequence
7936 which jumps to foo. */
7937 msym = lookup_minimal_symbol_by_pc (pc);
7938 if (msym.minsym == NULL
7939 || BMSYMBOL_VALUE_ADDRESS (msym) != pc
7940 || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL
7941 || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
7942 return 0;
7943
7944 /* A two-instruction header. */
7945 if (MSYMBOL_SIZE (msym.minsym) == 8)
7946 return pc + 8;
7947
7948 /* A three-instruction (plus delay slot) trampoline. */
7949 if (MSYMBOL_SIZE (msym.minsym) == 16)
7950 {
7951 if (target_read_memory (pc, stub_code, 16) != 0)
7952 return 0;
7953 for (i = 0; i < 4; i++)
7954 stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
7955 4, byte_order);
7956
7957 /* A stub contains these instructions:
7958 lui t9, %hi(target)
7959 j target
7960 addiu t9, t9, %lo(target)
7961 nop
7962
7963 This works even for N64, since stubs are only generated with
7964 -msym32. */
7965 if ((stub_words[0] & 0xffff0000U) == 0x3c190000
7966 && (stub_words[1] & 0xfc000000U) == 0x08000000
7967 && (stub_words[2] & 0xffff0000U) == 0x27390000
7968 && stub_words[3] == 0x00000000)
7969 return ((((stub_words[0] & 0x0000ffff) << 16)
7970 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7971 }
7972
7973 /* Not a recognized stub. */
7974 return 0;
7975 }
7976
7977 static CORE_ADDR
7978 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
7979 {
7980 CORE_ADDR requested_pc = pc;
7981 CORE_ADDR target_pc;
7982 CORE_ADDR new_pc;
7983
7984 do
7985 {
7986 target_pc = pc;
7987
7988 new_pc = mips_skip_mips16_trampoline_code (frame, pc);
7989 if (new_pc)
7990 pc = new_pc;
7991
7992 new_pc = find_solib_trampoline_target (frame, pc);
7993 if (new_pc)
7994 pc = new_pc;
7995
7996 new_pc = mips_skip_pic_trampoline_code (frame, pc);
7997 if (new_pc)
7998 pc = new_pc;
7999 }
8000 while (pc != target_pc);
8001
8002 return pc != requested_pc ? pc : 0;
8003 }
8004
8005 /* Convert a dbx stab register number (from `r' declaration) to a GDB
8006 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
8007
8008 static int
8009 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
8010 {
8011 int regnum;
8012 if (num >= 0 && num < 32)
8013 regnum = num;
8014 else if (num >= 38 && num < 70)
8015 regnum = num + mips_regnum (gdbarch)->fp0 - 38;
8016 else if (num == 70)
8017 regnum = mips_regnum (gdbarch)->hi;
8018 else if (num == 71)
8019 regnum = mips_regnum (gdbarch)->lo;
8020 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78)
8021 regnum = num + mips_regnum (gdbarch)->dspacc - 72;
8022 else
8023 /* This will hopefully (eventually) provoke a warning. Should
8024 we be calling complaint() here? */
8025 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
8026 return gdbarch_num_regs (gdbarch) + regnum;
8027 }
8028
8029
8030 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
8031 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
8032
8033 static int
8034 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
8035 {
8036 int regnum;
8037 if (num >= 0 && num < 32)
8038 regnum = num;
8039 else if (num >= 32 && num < 64)
8040 regnum = num + mips_regnum (gdbarch)->fp0 - 32;
8041 else if (num == 64)
8042 regnum = mips_regnum (gdbarch)->hi;
8043 else if (num == 65)
8044 regnum = mips_regnum (gdbarch)->lo;
8045 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72)
8046 regnum = num + mips_regnum (gdbarch)->dspacc - 66;
8047 else
8048 /* This will hopefully (eventually) provoke a warning. Should we
8049 be calling complaint() here? */
8050 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
8051 return gdbarch_num_regs (gdbarch) + regnum;
8052 }
8053
8054 static int
8055 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
8056 {
8057 /* Only makes sense to supply raw registers. */
8058 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
8059 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
8060 decide if it is valid. Should instead define a standard sim/gdb
8061 register numbering scheme. */
8062 if (gdbarch_register_name (gdbarch,
8063 gdbarch_num_regs (gdbarch) + regnum) != NULL
8064 && gdbarch_register_name (gdbarch,
8065 gdbarch_num_regs (gdbarch)
8066 + regnum)[0] != '\0')
8067 return regnum;
8068 else
8069 return LEGACY_SIM_REGNO_IGNORE;
8070 }
8071
8072
8073 /* Convert an integer into an address. Extracting the value signed
8074 guarantees a correctly sign extended address. */
8075
8076 static CORE_ADDR
8077 mips_integer_to_address (struct gdbarch *gdbarch,
8078 struct type *type, const gdb_byte *buf)
8079 {
8080 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8081 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
8082 }
8083
8084 /* Dummy virtual frame pointer method. This is no more or less accurate
8085 than most other architectures; we just need to be explicit about it,
8086 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
8087 an assertion failure. */
8088
8089 static void
8090 mips_virtual_frame_pointer (struct gdbarch *gdbarch,
8091 CORE_ADDR pc, int *reg, LONGEST *offset)
8092 {
8093 *reg = MIPS_SP_REGNUM;
8094 *offset = 0;
8095 }
8096
8097 static void
8098 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
8099 {
8100 enum mips_abi *abip = (enum mips_abi *) obj;
8101 const char *name = bfd_get_section_name (abfd, sect);
8102
8103 if (*abip != MIPS_ABI_UNKNOWN)
8104 return;
8105
8106 if (!startswith (name, ".mdebug."))
8107 return;
8108
8109 if (strcmp (name, ".mdebug.abi32") == 0)
8110 *abip = MIPS_ABI_O32;
8111 else if (strcmp (name, ".mdebug.abiN32") == 0)
8112 *abip = MIPS_ABI_N32;
8113 else if (strcmp (name, ".mdebug.abi64") == 0)
8114 *abip = MIPS_ABI_N64;
8115 else if (strcmp (name, ".mdebug.abiO64") == 0)
8116 *abip = MIPS_ABI_O64;
8117 else if (strcmp (name, ".mdebug.eabi32") == 0)
8118 *abip = MIPS_ABI_EABI32;
8119 else if (strcmp (name, ".mdebug.eabi64") == 0)
8120 *abip = MIPS_ABI_EABI64;
8121 else
8122 warning (_("unsupported ABI %s."), name + 8);
8123 }
8124
8125 static void
8126 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
8127 {
8128 int *lbp = (int *) obj;
8129 const char *name = bfd_get_section_name (abfd, sect);
8130
8131 if (startswith (name, ".gcc_compiled_long32"))
8132 *lbp = 32;
8133 else if (startswith (name, ".gcc_compiled_long64"))
8134 *lbp = 64;
8135 else if (startswith (name, ".gcc_compiled_long"))
8136 warning (_("unrecognized .gcc_compiled_longXX"));
8137 }
8138
8139 static enum mips_abi
8140 global_mips_abi (void)
8141 {
8142 int i;
8143
8144 for (i = 0; mips_abi_strings[i] != NULL; i++)
8145 if (mips_abi_strings[i] == mips_abi_string)
8146 return (enum mips_abi) i;
8147
8148 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
8149 }
8150
8151 /* Return the default compressed instruction set, either of MIPS16
8152 or microMIPS, selected when none could have been determined from
8153 the ELF header of the binary being executed (or no binary has been
8154 selected. */
8155
8156 static enum mips_isa
8157 global_mips_compression (void)
8158 {
8159 int i;
8160
8161 for (i = 0; mips_compression_strings[i] != NULL; i++)
8162 if (mips_compression_strings[i] == mips_compression_string)
8163 return (enum mips_isa) i;
8164
8165 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
8166 }
8167
8168 static void
8169 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
8170 {
8171 /* If the size matches the set of 32-bit or 64-bit integer registers,
8172 assume that's what we've got. */
8173 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
8174 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
8175
8176 /* If the size matches the full set of registers GDB traditionally
8177 knows about, including floating point, for either 32-bit or
8178 64-bit, assume that's what we've got. */
8179 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
8180 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
8181
8182 /* Otherwise we don't have a useful guess. */
8183 }
8184
8185 static struct value *
8186 value_of_mips_user_reg (struct frame_info *frame, const void *baton)
8187 {
8188 const int *reg_p = baton;
8189 return value_of_register (*reg_p, frame);
8190 }
8191
8192 static struct gdbarch *
8193 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8194 {
8195 struct gdbarch *gdbarch;
8196 struct gdbarch_tdep *tdep;
8197 int elf_flags;
8198 enum mips_abi mips_abi, found_abi, wanted_abi;
8199 int i, num_regs;
8200 enum mips_fpu_type fpu_type;
8201 struct tdesc_arch_data *tdesc_data = NULL;
8202 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY;
8203 const char **reg_names;
8204 struct mips_regnum mips_regnum, *regnum;
8205 enum mips_isa mips_isa;
8206 int dspacc;
8207 int dspctl;
8208
8209 /* Fill in the OS dependent register numbers and names. */
8210 if (info.osabi == GDB_OSABI_IRIX)
8211 {
8212 mips_regnum.fp0 = 32;
8213 mips_regnum.pc = 64;
8214 mips_regnum.cause = 65;
8215 mips_regnum.badvaddr = 66;
8216 mips_regnum.hi = 67;
8217 mips_regnum.lo = 68;
8218 mips_regnum.fp_control_status = 69;
8219 mips_regnum.fp_implementation_revision = 70;
8220 mips_regnum.dspacc = dspacc = -1;
8221 mips_regnum.dspctl = dspctl = -1;
8222 num_regs = 71;
8223 reg_names = mips_irix_reg_names;
8224 }
8225 else if (info.osabi == GDB_OSABI_LINUX)
8226 {
8227 mips_regnum.fp0 = 38;
8228 mips_regnum.pc = 37;
8229 mips_regnum.cause = 36;
8230 mips_regnum.badvaddr = 35;
8231 mips_regnum.hi = 34;
8232 mips_regnum.lo = 33;
8233 mips_regnum.fp_control_status = 70;
8234 mips_regnum.fp_implementation_revision = 71;
8235 mips_regnum.dspacc = -1;
8236 mips_regnum.dspctl = -1;
8237 dspacc = 72;
8238 dspctl = 78;
8239 num_regs = 79;
8240 reg_names = mips_linux_reg_names;
8241 }
8242 else
8243 {
8244 mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
8245 mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
8246 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
8247 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
8248 mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
8249 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
8250 mips_regnum.fp_control_status = 70;
8251 mips_regnum.fp_implementation_revision = 71;
8252 mips_regnum.dspacc = dspacc = -1;
8253 mips_regnum.dspctl = dspctl = -1;
8254 num_regs = MIPS_LAST_EMBED_REGNUM + 1;
8255 if (info.bfd_arch_info != NULL
8256 && info.bfd_arch_info->mach == bfd_mach_mips3900)
8257 reg_names = mips_tx39_reg_names;
8258 else
8259 reg_names = mips_generic_reg_names;
8260 }
8261
8262 /* Check any target description for validity. */
8263 if (tdesc_has_registers (info.target_desc))
8264 {
8265 static const char *const mips_gprs[] = {
8266 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8267 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8268 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8269 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8270 };
8271 static const char *const mips_fprs[] = {
8272 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8273 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8274 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8275 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8276 };
8277
8278 const struct tdesc_feature *feature;
8279 int valid_p;
8280
8281 feature = tdesc_find_feature (info.target_desc,
8282 "org.gnu.gdb.mips.cpu");
8283 if (feature == NULL)
8284 return NULL;
8285
8286 tdesc_data = tdesc_data_alloc ();
8287
8288 valid_p = 1;
8289 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
8290 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
8291 mips_gprs[i]);
8292
8293
8294 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8295 mips_regnum.lo, "lo");
8296 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8297 mips_regnum.hi, "hi");
8298 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8299 mips_regnum.pc, "pc");
8300
8301 if (!valid_p)
8302 {
8303 tdesc_data_cleanup (tdesc_data);
8304 return NULL;
8305 }
8306
8307 feature = tdesc_find_feature (info.target_desc,
8308 "org.gnu.gdb.mips.cp0");
8309 if (feature == NULL)
8310 {
8311 tdesc_data_cleanup (tdesc_data);
8312 return NULL;
8313 }
8314
8315 valid_p = 1;
8316 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8317 mips_regnum.badvaddr, "badvaddr");
8318 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8319 MIPS_PS_REGNUM, "status");
8320 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8321 mips_regnum.cause, "cause");
8322
8323 if (!valid_p)
8324 {
8325 tdesc_data_cleanup (tdesc_data);
8326 return NULL;
8327 }
8328
8329 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8330 backend is not prepared for that, though. */
8331 feature = tdesc_find_feature (info.target_desc,
8332 "org.gnu.gdb.mips.fpu");
8333 if (feature == NULL)
8334 {
8335 tdesc_data_cleanup (tdesc_data);
8336 return NULL;
8337 }
8338
8339 valid_p = 1;
8340 for (i = 0; i < 32; i++)
8341 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8342 i + mips_regnum.fp0, mips_fprs[i]);
8343
8344 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8345 mips_regnum.fp_control_status,
8346 "fcsr");
8347 valid_p
8348 &= tdesc_numbered_register (feature, tdesc_data,
8349 mips_regnum.fp_implementation_revision,
8350 "fir");
8351
8352 if (!valid_p)
8353 {
8354 tdesc_data_cleanup (tdesc_data);
8355 return NULL;
8356 }
8357
8358 if (dspacc >= 0)
8359 {
8360 feature = tdesc_find_feature (info.target_desc,
8361 "org.gnu.gdb.mips.dsp");
8362 /* The DSP registers are optional; it's OK if they are absent. */
8363 if (feature != NULL)
8364 {
8365 i = 0;
8366 valid_p = 1;
8367 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8368 dspacc + i++, "hi1");
8369 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8370 dspacc + i++, "lo1");
8371 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8372 dspacc + i++, "hi2");
8373 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8374 dspacc + i++, "lo2");
8375 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8376 dspacc + i++, "hi3");
8377 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8378 dspacc + i++, "lo3");
8379
8380 valid_p &= tdesc_numbered_register (feature, tdesc_data,
8381 dspctl, "dspctl");
8382
8383 if (!valid_p)
8384 {
8385 tdesc_data_cleanup (tdesc_data);
8386 return NULL;
8387 }
8388
8389 mips_regnum.dspacc = dspacc;
8390 mips_regnum.dspctl = dspctl;
8391 }
8392 }
8393
8394 /* It would be nice to detect an attempt to use a 64-bit ABI
8395 when only 32-bit registers are provided. */
8396 reg_names = NULL;
8397 }
8398
8399 /* First of all, extract the elf_flags, if available. */
8400 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8401 elf_flags = elf_elfheader (info.abfd)->e_flags;
8402 else if (arches != NULL)
8403 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
8404 else
8405 elf_flags = 0;
8406 if (gdbarch_debug)
8407 fprintf_unfiltered (gdb_stdlog,
8408 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
8409
8410 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8411 switch ((elf_flags & EF_MIPS_ABI))
8412 {
8413 case E_MIPS_ABI_O32:
8414 found_abi = MIPS_ABI_O32;
8415 break;
8416 case E_MIPS_ABI_O64:
8417 found_abi = MIPS_ABI_O64;
8418 break;
8419 case E_MIPS_ABI_EABI32:
8420 found_abi = MIPS_ABI_EABI32;
8421 break;
8422 case E_MIPS_ABI_EABI64:
8423 found_abi = MIPS_ABI_EABI64;
8424 break;
8425 default:
8426 if ((elf_flags & EF_MIPS_ABI2))
8427 found_abi = MIPS_ABI_N32;
8428 else
8429 found_abi = MIPS_ABI_UNKNOWN;
8430 break;
8431 }
8432
8433 /* GCC creates a pseudo-section whose name describes the ABI. */
8434 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
8435 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
8436
8437 /* If we have no useful BFD information, use the ABI from the last
8438 MIPS architecture (if there is one). */
8439 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
8440 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
8441
8442 /* Try the architecture for any hint of the correct ABI. */
8443 if (found_abi == MIPS_ABI_UNKNOWN
8444 && info.bfd_arch_info != NULL
8445 && info.bfd_arch_info->arch == bfd_arch_mips)
8446 {
8447 switch (info.bfd_arch_info->mach)
8448 {
8449 case bfd_mach_mips3900:
8450 found_abi = MIPS_ABI_EABI32;
8451 break;
8452 case bfd_mach_mips4100:
8453 case bfd_mach_mips5000:
8454 found_abi = MIPS_ABI_EABI64;
8455 break;
8456 case bfd_mach_mips8000:
8457 case bfd_mach_mips10000:
8458 /* On Irix, ELF64 executables use the N64 ABI. The
8459 pseudo-sections which describe the ABI aren't present
8460 on IRIX. (Even for executables created by gcc.) */
8461 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8462 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8463 found_abi = MIPS_ABI_N64;
8464 else
8465 found_abi = MIPS_ABI_N32;
8466 break;
8467 }
8468 }
8469
8470 /* Default 64-bit objects to N64 instead of O32. */
8471 if (found_abi == MIPS_ABI_UNKNOWN
8472 && info.abfd != NULL
8473 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
8474 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
8475 found_abi = MIPS_ABI_N64;
8476
8477 if (gdbarch_debug)
8478 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
8479 found_abi);
8480
8481 /* What has the user specified from the command line? */
8482 wanted_abi = global_mips_abi ();
8483 if (gdbarch_debug)
8484 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
8485 wanted_abi);
8486
8487 /* Now that we have found what the ABI for this binary would be,
8488 check whether the user is overriding it. */
8489 if (wanted_abi != MIPS_ABI_UNKNOWN)
8490 mips_abi = wanted_abi;
8491 else if (found_abi != MIPS_ABI_UNKNOWN)
8492 mips_abi = found_abi;
8493 else
8494 mips_abi = MIPS_ABI_O32;
8495 if (gdbarch_debug)
8496 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
8497 mips_abi);
8498
8499 /* Determine the default compressed ISA. */
8500 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
8501 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0)
8502 mips_isa = ISA_MICROMIPS;
8503 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0
8504 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0)
8505 mips_isa = ISA_MIPS16;
8506 else
8507 mips_isa = global_mips_compression ();
8508 mips_compression_string = mips_compression_strings[mips_isa];
8509
8510 /* Also used when doing an architecture lookup. */
8511 if (gdbarch_debug)
8512 fprintf_unfiltered (gdb_stdlog,
8513 "mips_gdbarch_init: "
8514 "mips64_transfers_32bit_regs_p = %d\n",
8515 mips64_transfers_32bit_regs_p);
8516
8517 /* Determine the MIPS FPU type. */
8518 #ifdef HAVE_ELF
8519 if (info.abfd
8520 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
8521 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
8522 Tag_GNU_MIPS_ABI_FP);
8523 #endif /* HAVE_ELF */
8524
8525 if (!mips_fpu_type_auto)
8526 fpu_type = mips_fpu_type;
8527 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY)
8528 {
8529 switch (elf_fpu_type)
8530 {
8531 case Val_GNU_MIPS_ABI_FP_DOUBLE:
8532 fpu_type = MIPS_FPU_DOUBLE;
8533 break;
8534 case Val_GNU_MIPS_ABI_FP_SINGLE:
8535 fpu_type = MIPS_FPU_SINGLE;
8536 break;
8537 case Val_GNU_MIPS_ABI_FP_SOFT:
8538 default:
8539 /* Soft float or unknown. */
8540 fpu_type = MIPS_FPU_NONE;
8541 break;
8542 }
8543 }
8544 else if (info.bfd_arch_info != NULL
8545 && info.bfd_arch_info->arch == bfd_arch_mips)
8546 switch (info.bfd_arch_info->mach)
8547 {
8548 case bfd_mach_mips3900:
8549 case bfd_mach_mips4100:
8550 case bfd_mach_mips4111:
8551 case bfd_mach_mips4120:
8552 fpu_type = MIPS_FPU_NONE;
8553 break;
8554 case bfd_mach_mips4650:
8555 fpu_type = MIPS_FPU_SINGLE;
8556 break;
8557 default:
8558 fpu_type = MIPS_FPU_DOUBLE;
8559 break;
8560 }
8561 else if (arches != NULL)
8562 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
8563 else
8564 fpu_type = MIPS_FPU_DOUBLE;
8565 if (gdbarch_debug)
8566 fprintf_unfiltered (gdb_stdlog,
8567 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
8568
8569 /* Check for blatant incompatibilities. */
8570
8571 /* If we have only 32-bit registers, then we can't debug a 64-bit
8572 ABI. */
8573 if (info.target_desc
8574 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
8575 && mips_abi != MIPS_ABI_EABI32
8576 && mips_abi != MIPS_ABI_O32)
8577 {
8578 if (tdesc_data != NULL)
8579 tdesc_data_cleanup (tdesc_data);
8580 return NULL;
8581 }
8582
8583 /* Try to find a pre-existing architecture. */
8584 for (arches = gdbarch_list_lookup_by_info (arches, &info);
8585 arches != NULL;
8586 arches = gdbarch_list_lookup_by_info (arches->next, &info))
8587 {
8588 /* MIPS needs to be pedantic about which ABI and the compressed
8589 ISA variation the object is using. */
8590 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
8591 continue;
8592 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
8593 continue;
8594 if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa)
8595 continue;
8596 /* Need to be pedantic about which register virtual size is
8597 used. */
8598 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
8599 != mips64_transfers_32bit_regs_p)
8600 continue;
8601 /* Be pedantic about which FPU is selected. */
8602 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
8603 continue;
8604
8605 if (tdesc_data != NULL)
8606 tdesc_data_cleanup (tdesc_data);
8607 return arches->gdbarch;
8608 }
8609
8610 /* Need a new architecture. Fill in a target specific vector. */
8611 tdep = XNEW (struct gdbarch_tdep);
8612 gdbarch = gdbarch_alloc (&info, tdep);
8613 tdep->elf_flags = elf_flags;
8614 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
8615 tdep->found_abi = found_abi;
8616 tdep->mips_abi = mips_abi;
8617 tdep->mips_isa = mips_isa;
8618 tdep->mips_fpu_type = fpu_type;
8619 tdep->register_size_valid_p = 0;
8620 tdep->register_size = 0;
8621
8622 if (info.target_desc)
8623 {
8624 /* Some useful properties can be inferred from the target. */
8625 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
8626 {
8627 tdep->register_size_valid_p = 1;
8628 tdep->register_size = 4;
8629 }
8630 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
8631 {
8632 tdep->register_size_valid_p = 1;
8633 tdep->register_size = 8;
8634 }
8635 }
8636
8637 /* Initially set everything according to the default ABI/ISA. */
8638 set_gdbarch_short_bit (gdbarch, 16);
8639 set_gdbarch_int_bit (gdbarch, 32);
8640 set_gdbarch_float_bit (gdbarch, 32);
8641 set_gdbarch_double_bit (gdbarch, 64);
8642 set_gdbarch_long_double_bit (gdbarch, 64);
8643 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
8644 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
8645 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
8646
8647 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8648 mips_ax_pseudo_register_collect);
8649 set_gdbarch_ax_pseudo_register_push_stack
8650 (gdbarch, mips_ax_pseudo_register_push_stack);
8651
8652 set_gdbarch_elf_make_msymbol_special (gdbarch,
8653 mips_elf_make_msymbol_special);
8654 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special);
8655 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr);
8656 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line);
8657
8658 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum);
8659 *regnum = mips_regnum;
8660 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
8661 set_gdbarch_num_regs (gdbarch, num_regs);
8662 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8663 set_gdbarch_register_name (gdbarch, mips_register_name);
8664 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
8665 tdep->mips_processor_reg_names = reg_names;
8666 tdep->regnum = regnum;
8667
8668 switch (mips_abi)
8669 {
8670 case MIPS_ABI_O32:
8671 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
8672 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
8673 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8674 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8675 tdep->default_mask_address_p = 0;
8676 set_gdbarch_long_bit (gdbarch, 32);
8677 set_gdbarch_ptr_bit (gdbarch, 32);
8678 set_gdbarch_long_long_bit (gdbarch, 64);
8679 break;
8680 case MIPS_ABI_O64:
8681 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
8682 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
8683 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
8684 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
8685 tdep->default_mask_address_p = 0;
8686 set_gdbarch_long_bit (gdbarch, 32);
8687 set_gdbarch_ptr_bit (gdbarch, 32);
8688 set_gdbarch_long_long_bit (gdbarch, 64);
8689 break;
8690 case MIPS_ABI_EABI32:
8691 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8692 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8693 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8694 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8695 tdep->default_mask_address_p = 0;
8696 set_gdbarch_long_bit (gdbarch, 32);
8697 set_gdbarch_ptr_bit (gdbarch, 32);
8698 set_gdbarch_long_long_bit (gdbarch, 64);
8699 break;
8700 case MIPS_ABI_EABI64:
8701 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
8702 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
8703 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8704 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8705 tdep->default_mask_address_p = 0;
8706 set_gdbarch_long_bit (gdbarch, 64);
8707 set_gdbarch_ptr_bit (gdbarch, 64);
8708 set_gdbarch_long_long_bit (gdbarch, 64);
8709 break;
8710 case MIPS_ABI_N32:
8711 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8712 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8713 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8714 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8715 tdep->default_mask_address_p = 0;
8716 set_gdbarch_long_bit (gdbarch, 32);
8717 set_gdbarch_ptr_bit (gdbarch, 32);
8718 set_gdbarch_long_long_bit (gdbarch, 64);
8719 set_gdbarch_long_double_bit (gdbarch, 128);
8720 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8721 break;
8722 case MIPS_ABI_N64:
8723 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
8724 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
8725 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
8726 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
8727 tdep->default_mask_address_p = 0;
8728 set_gdbarch_long_bit (gdbarch, 64);
8729 set_gdbarch_ptr_bit (gdbarch, 64);
8730 set_gdbarch_long_long_bit (gdbarch, 64);
8731 set_gdbarch_long_double_bit (gdbarch, 128);
8732 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
8733 break;
8734 default:
8735 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8736 }
8737
8738 /* GCC creates a pseudo-section whose name specifies the size of
8739 longs, since -mlong32 or -mlong64 may be used independent of
8740 other options. How those options affect pointer sizes is ABI and
8741 architecture dependent, so use them to override the default sizes
8742 set by the ABI. This table shows the relationship between ABI,
8743 -mlongXX, and size of pointers:
8744
8745 ABI -mlongXX ptr bits
8746 --- -------- --------
8747 o32 32 32
8748 o32 64 32
8749 n32 32 32
8750 n32 64 64
8751 o64 32 32
8752 o64 64 64
8753 n64 32 32
8754 n64 64 64
8755 eabi32 32 32
8756 eabi32 64 32
8757 eabi64 32 32
8758 eabi64 64 64
8759
8760 Note that for o32 and eabi32, pointers are always 32 bits
8761 regardless of any -mlongXX option. For all others, pointers and
8762 longs are the same, as set by -mlongXX or set by defaults. */
8763
8764 if (info.abfd != NULL)
8765 {
8766 int long_bit = 0;
8767
8768 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
8769 if (long_bit)
8770 {
8771 set_gdbarch_long_bit (gdbarch, long_bit);
8772 switch (mips_abi)
8773 {
8774 case MIPS_ABI_O32:
8775 case MIPS_ABI_EABI32:
8776 break;
8777 case MIPS_ABI_N32:
8778 case MIPS_ABI_O64:
8779 case MIPS_ABI_N64:
8780 case MIPS_ABI_EABI64:
8781 set_gdbarch_ptr_bit (gdbarch, long_bit);
8782 break;
8783 default:
8784 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
8785 }
8786 }
8787 }
8788
8789 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8790 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8791 comment:
8792
8793 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8794 flag in object files because to do so would make it impossible to
8795 link with libraries compiled without "-gp32". This is
8796 unnecessarily restrictive.
8797
8798 We could solve this problem by adding "-gp32" multilibs to gcc,
8799 but to set this flag before gcc is built with such multilibs will
8800 break too many systems.''
8801
8802 But even more unhelpfully, the default linker output target for
8803 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8804 for 64-bit programs - you need to change the ABI to change this,
8805 and not all gcc targets support that currently. Therefore using
8806 this flag to detect 32-bit mode would do the wrong thing given
8807 the current gcc - it would make GDB treat these 64-bit programs
8808 as 32-bit programs by default. */
8809
8810 set_gdbarch_read_pc (gdbarch, mips_read_pc);
8811 set_gdbarch_write_pc (gdbarch, mips_write_pc);
8812
8813 /* Add/remove bits from an address. The MIPS needs be careful to
8814 ensure that all 32 bit addresses are sign extended to 64 bits. */
8815 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
8816
8817 /* Unwind the frame. */
8818 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
8819 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
8820 set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
8821
8822 /* Map debug register numbers onto internal register numbers. */
8823 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
8824 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
8825 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8826 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
8827 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8828 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
8829
8830 /* MIPS version of CALL_DUMMY. */
8831
8832 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8833 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code);
8834 set_gdbarch_frame_align (gdbarch, mips_frame_align);
8835
8836 set_gdbarch_print_float_info (gdbarch, mips_print_float_info);
8837
8838 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
8839 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
8840 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
8841
8842 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8843 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
8844 set_gdbarch_remote_breakpoint_from_pc (gdbarch,
8845 mips_remote_breakpoint_from_pc);
8846 set_gdbarch_adjust_breakpoint_address (gdbarch,
8847 mips_adjust_breakpoint_address);
8848
8849 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
8850
8851 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p);
8852
8853 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
8854 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
8855 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
8856
8857 set_gdbarch_register_type (gdbarch, mips_register_type);
8858
8859 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
8860
8861 if (mips_abi == MIPS_ABI_N32)
8862 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
8863 else if (mips_abi == MIPS_ABI_N64)
8864 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
8865 else
8866 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
8867
8868 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8869 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8870 need to all be folded into the target vector. Since they are
8871 being used as guards for target_stopped_by_watchpoint, why not have
8872 target_stopped_by_watchpoint return the type of watchpoint that the code
8873 is sitting on? */
8874 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8875
8876 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
8877
8878 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8879 to support MIPS16. This is a bad thing. Make sure not to do it
8880 if we have an OS ABI that actually supports shared libraries, since
8881 shared library support is more important. If we have an OS someday
8882 that supports both shared libraries and MIPS16, we'll have to find
8883 a better place for these.
8884 macro/2012-04-25: But that applies to return trampolines only and
8885 currently no MIPS OS ABI uses shared libraries that have them. */
8886 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
8887
8888 set_gdbarch_single_step_through_delay (gdbarch,
8889 mips_single_step_through_delay);
8890
8891 /* Virtual tables. */
8892 set_gdbarch_vbit_in_delta (gdbarch, 1);
8893
8894 mips_register_g_packet_guesses (gdbarch);
8895
8896 /* Hook in OS ABI-specific overrides, if they have been registered. */
8897 info.tdep_info = (void *) tdesc_data;
8898 gdbarch_init_osabi (info, gdbarch);
8899
8900 /* The hook may have adjusted num_regs, fetch the final value and
8901 set pc_regnum and sp_regnum now that it has been fixed. */
8902 num_regs = gdbarch_num_regs (gdbarch);
8903 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
8904 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8905
8906 /* Unwind the frame. */
8907 dwarf2_append_unwinders (gdbarch);
8908 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
8909 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
8910 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind);
8911 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
8912 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
8913 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
8914 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
8915 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
8916 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
8917
8918 if (tdesc_data)
8919 {
8920 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
8921 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
8922
8923 /* Override the normal target description methods to handle our
8924 dual real and pseudo registers. */
8925 set_gdbarch_register_name (gdbarch, mips_register_name);
8926 set_gdbarch_register_reggroup_p (gdbarch,
8927 mips_tdesc_register_reggroup_p);
8928
8929 num_regs = gdbarch_num_regs (gdbarch);
8930 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
8931 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
8932 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
8933 }
8934
8935 /* Add ABI-specific aliases for the registers. */
8936 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
8937 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
8938 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
8939 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
8940 else
8941 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
8942 user_reg_add (gdbarch, mips_o32_aliases[i].name,
8943 value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
8944
8945 /* Add some other standard aliases. */
8946 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
8947 user_reg_add (gdbarch, mips_register_aliases[i].name,
8948 value_of_mips_user_reg, &mips_register_aliases[i].regnum);
8949
8950 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
8951 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
8952 value_of_mips_user_reg,
8953 &mips_numeric_register_aliases[i].regnum);
8954
8955 return gdbarch;
8956 }
8957
8958 static void
8959 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
8960 {
8961 struct gdbarch_info info;
8962
8963 /* Force the architecture to update, and (if it's a MIPS architecture)
8964 mips_gdbarch_init will take care of the rest. */
8965 gdbarch_info_init (&info);
8966 gdbarch_update_p (info);
8967 }
8968
8969 /* Print out which MIPS ABI is in use. */
8970
8971 static void
8972 show_mips_abi (struct ui_file *file,
8973 int from_tty,
8974 struct cmd_list_element *ignored_cmd,
8975 const char *ignored_value)
8976 {
8977 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
8978 fprintf_filtered
8979 (file,
8980 "The MIPS ABI is unknown because the current architecture "
8981 "is not MIPS.\n");
8982 else
8983 {
8984 enum mips_abi global_abi = global_mips_abi ();
8985 enum mips_abi actual_abi = mips_abi (target_gdbarch ());
8986 const char *actual_abi_str = mips_abi_strings[actual_abi];
8987
8988 if (global_abi == MIPS_ABI_UNKNOWN)
8989 fprintf_filtered
8990 (file,
8991 "The MIPS ABI is set automatically (currently \"%s\").\n",
8992 actual_abi_str);
8993 else if (global_abi == actual_abi)
8994 fprintf_filtered
8995 (file,
8996 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8997 actual_abi_str);
8998 else
8999 {
9000 /* Probably shouldn't happen... */
9001 fprintf_filtered (file,
9002 "The (auto detected) MIPS ABI \"%s\" is in use "
9003 "even though the user setting was \"%s\".\n",
9004 actual_abi_str, mips_abi_strings[global_abi]);
9005 }
9006 }
9007 }
9008
9009 /* Print out which MIPS compressed ISA encoding is used. */
9010
9011 static void
9012 show_mips_compression (struct ui_file *file, int from_tty,
9013 struct cmd_list_element *c, const char *value)
9014 {
9015 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
9016 value);
9017 }
9018
9019 static void
9020 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
9021 {
9022 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9023 if (tdep != NULL)
9024 {
9025 int ef_mips_arch;
9026 int ef_mips_32bitmode;
9027 /* Determine the ISA. */
9028 switch (tdep->elf_flags & EF_MIPS_ARCH)
9029 {
9030 case E_MIPS_ARCH_1:
9031 ef_mips_arch = 1;
9032 break;
9033 case E_MIPS_ARCH_2:
9034 ef_mips_arch = 2;
9035 break;
9036 case E_MIPS_ARCH_3:
9037 ef_mips_arch = 3;
9038 break;
9039 case E_MIPS_ARCH_4:
9040 ef_mips_arch = 4;
9041 break;
9042 default:
9043 ef_mips_arch = 0;
9044 break;
9045 }
9046 /* Determine the size of a pointer. */
9047 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
9048 fprintf_unfiltered (file,
9049 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
9050 tdep->elf_flags);
9051 fprintf_unfiltered (file,
9052 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
9053 ef_mips_32bitmode);
9054 fprintf_unfiltered (file,
9055 "mips_dump_tdep: ef_mips_arch = %d\n",
9056 ef_mips_arch);
9057 fprintf_unfiltered (file,
9058 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
9059 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
9060 fprintf_unfiltered (file,
9061 "mips_dump_tdep: "
9062 "mips_mask_address_p() %d (default %d)\n",
9063 mips_mask_address_p (tdep),
9064 tdep->default_mask_address_p);
9065 }
9066 fprintf_unfiltered (file,
9067 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
9068 MIPS_DEFAULT_FPU_TYPE,
9069 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
9070 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
9071 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
9072 : "???"));
9073 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
9074 MIPS_EABI (gdbarch));
9075 fprintf_unfiltered (file,
9076 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
9077 MIPS_FPU_TYPE (gdbarch),
9078 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
9079 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
9080 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
9081 : "???"));
9082 }
9083
9084 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
9085
9086 void
9087 _initialize_mips_tdep (void)
9088 {
9089 static struct cmd_list_element *mipsfpulist = NULL;
9090 struct cmd_list_element *c;
9091
9092 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
9093 if (MIPS_ABI_LAST + 1
9094 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
9095 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
9096
9097 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
9098
9099 mips_pdr_data = register_objfile_data ();
9100
9101 /* Create feature sets with the appropriate properties. The values
9102 are not important. */
9103 mips_tdesc_gp32 = allocate_target_description ();
9104 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
9105
9106 mips_tdesc_gp64 = allocate_target_description ();
9107 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
9108
9109 /* Add root prefix command for all "set mips"/"show mips" commands. */
9110 add_prefix_cmd ("mips", no_class, set_mips_command,
9111 _("Various MIPS specific commands."),
9112 &setmipscmdlist, "set mips ", 0, &setlist);
9113
9114 add_prefix_cmd ("mips", no_class, show_mips_command,
9115 _("Various MIPS specific commands."),
9116 &showmipscmdlist, "show mips ", 0, &showlist);
9117
9118 /* Allow the user to override the ABI. */
9119 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
9120 &mips_abi_string, _("\
9121 Set the MIPS ABI used by this program."), _("\
9122 Show the MIPS ABI used by this program."), _("\
9123 This option can be set to one of:\n\
9124 auto - the default ABI associated with the current binary\n\
9125 o32\n\
9126 o64\n\
9127 n32\n\
9128 n64\n\
9129 eabi32\n\
9130 eabi64"),
9131 mips_abi_update,
9132 show_mips_abi,
9133 &setmipscmdlist, &showmipscmdlist);
9134
9135 /* Allow the user to set the ISA to assume for compressed code if ELF
9136 file flags don't tell or there is no program file selected. This
9137 setting is updated whenever unambiguous ELF file flags are interpreted,
9138 and carried over to subsequent sessions. */
9139 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings,
9140 &mips_compression_string, _("\
9141 Set the compressed ISA encoding used by MIPS code."), _("\
9142 Show the compressed ISA encoding used by MIPS code."), _("\
9143 Select the compressed ISA encoding used in functions that have no symbol\n\
9144 information available. The encoding can be set to either of:\n\
9145 mips16\n\
9146 micromips\n\
9147 and is updated automatically from ELF file flags if available."),
9148 mips_abi_update,
9149 show_mips_compression,
9150 &setmipscmdlist, &showmipscmdlist);
9151
9152 /* Let the user turn off floating point and set the fence post for
9153 heuristic_proc_start. */
9154
9155 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
9156 _("Set use of MIPS floating-point coprocessor."),
9157 &mipsfpulist, "set mipsfpu ", 0, &setlist);
9158 add_cmd ("single", class_support, set_mipsfpu_single_command,
9159 _("Select single-precision MIPS floating-point coprocessor."),
9160 &mipsfpulist);
9161 add_cmd ("double", class_support, set_mipsfpu_double_command,
9162 _("Select double-precision MIPS floating-point coprocessor."),
9163 &mipsfpulist);
9164 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
9165 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
9166 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
9167 add_cmd ("none", class_support, set_mipsfpu_none_command,
9168 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
9169 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
9170 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
9171 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
9172 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
9173 _("Select MIPS floating-point coprocessor automatically."),
9174 &mipsfpulist);
9175 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
9176 _("Show current use of MIPS floating-point coprocessor target."),
9177 &showlist);
9178
9179 /* We really would like to have both "0" and "unlimited" work, but
9180 command.c doesn't deal with that. So make it a var_zinteger
9181 because the user can always use "999999" or some such for unlimited. */
9182 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
9183 &heuristic_fence_post, _("\
9184 Set the distance searched for the start of a function."), _("\
9185 Show the distance searched for the start of a function."), _("\
9186 If you are debugging a stripped executable, GDB needs to search through the\n\
9187 program for the start of a function. This command sets the distance of the\n\
9188 search. The only need to set it is when debugging a stripped executable."),
9189 reinit_frame_cache_sfunc,
9190 NULL, /* FIXME: i18n: The distance searched for
9191 the start of a function is %s. */
9192 &setlist, &showlist);
9193
9194 /* Allow the user to control whether the upper bits of 64-bit
9195 addresses should be zeroed. */
9196 add_setshow_auto_boolean_cmd ("mask-address", no_class,
9197 &mask_address_var, _("\
9198 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9199 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9200 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9201 allow GDB to determine the correct value."),
9202 NULL, show_mask_address,
9203 &setmipscmdlist, &showmipscmdlist);
9204
9205 /* Allow the user to control the size of 32 bit registers within the
9206 raw remote packet. */
9207 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
9208 &mips64_transfers_32bit_regs_p, _("\
9209 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9210 _("\
9211 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9212 _("\
9213 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9214 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9215 64 bits for others. Use \"off\" to disable compatibility mode"),
9216 set_mips64_transfers_32bit_regs,
9217 NULL, /* FIXME: i18n: Compatibility with 64-bit
9218 MIPS target that transfers 32-bit
9219 quantities is %s. */
9220 &setlist, &showlist);
9221
9222 /* Debug this files internals. */
9223 add_setshow_zuinteger_cmd ("mips", class_maintenance,
9224 &mips_debug, _("\
9225 Set mips debugging."), _("\
9226 Show mips debugging."), _("\
9227 When non-zero, mips specific debugging is enabled."),
9228 NULL,
9229 NULL, /* FIXME: i18n: Mips debugging is
9230 currently %s. */
9231 &setdebuglist, &showdebuglist);
9232 }
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