1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
42 struct frame_extra_info
44 mips_extra_func_info_t proc_desc
;
48 /* Some MIPS boards don't support floating point while others only
49 support single-precision floating-point operations. See also
50 FP_REGISTER_DOUBLE. */
54 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
55 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
56 MIPS_FPU_NONE
/* No floating point. */
59 #ifndef MIPS_DEFAULT_FPU_TYPE
60 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
62 static int mips_fpu_type_auto
= 1;
63 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
64 #define MIPS_FPU_TYPE mips_fpu_type
66 #ifndef MIPS_SAVED_REGSIZE
67 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
70 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
71 #ifndef FP_REGISTER_DOUBLE
72 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
76 /* MIPS specific per-architecture information */
79 /* from the elf header */
83 enum mips_fpu_type mips_fpu_type
;
84 int mips_last_arg_regnum
;
85 int mips_last_fp_arg_regnum
;
86 int mips_saved_regsize
;
87 int mips_fp_register_double
;
92 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi)
96 #undef MIPS_LAST_FP_ARG_REGNUM
97 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
101 #undef MIPS_LAST_ARG_REGNUM
102 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
107 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
111 #undef MIPS_SAVED_REGSIZE
112 #define MIPS_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_saved_regsize)
115 /* Indicate that the ABI makes use of double-precision registers
116 provided by the FPU (rather than combining pairs of registers to
117 form double-precision values). Do not use "TARGET_IS_MIPS64" to
118 determine if the ABI is using double-precision registers. See also
121 #undef FP_REGISTER_DOUBLE
122 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
126 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
129 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
132 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
134 static void mips_print_register
PARAMS ((int, int));
136 static mips_extra_func_info_t
137 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
139 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
141 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
143 int mips_set_processor_type
PARAMS ((char *));
145 static void mips_show_processor_type_command
PARAMS ((char *, int));
147 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
148 struct cmd_list_element
*));
150 static mips_extra_func_info_t
151 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
153 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
154 mips_extra_func_info_t proc_desc
));
156 /* This value is the model of MIPS in use. It is derived from the value
157 of the PrID register. */
159 char *mips_processor_type
;
161 char *tmp_mips_processor_type
;
163 /* A set of original names, to be used when restoring back to generic
164 registers from a specific set. */
166 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
167 char **mips_processor_reg_names
= mips_generic_reg_names
;
170 mips_register_name (i
)
173 return mips_processor_reg_names
[i
];
176 /* Names of IDT R3041 registers. */
178 char *mips_r3041_reg_names
[] = {
179 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
180 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
181 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
182 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
183 "sr", "lo", "hi", "bad", "cause","pc",
184 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
185 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
186 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
187 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
188 "fsr", "fir", "fp", "",
189 "", "", "bus", "ccfg", "", "", "", "",
190 "", "", "port", "cmp", "", "", "epc", "prid",
193 /* Names of IDT R3051 registers. */
195 char *mips_r3051_reg_names
[] = {
196 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
197 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
198 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
199 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
200 "sr", "lo", "hi", "bad", "cause","pc",
201 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
202 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
203 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
204 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
205 "fsr", "fir", "fp", "",
206 "inx", "rand", "elo", "", "ctxt", "", "", "",
207 "", "", "ehi", "", "", "", "epc", "prid",
210 /* Names of IDT R3081 registers. */
212 char *mips_r3081_reg_names
[] = {
213 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
214 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
215 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
216 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
217 "sr", "lo", "hi", "bad", "cause","pc",
218 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
219 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
220 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
221 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
222 "fsr", "fir", "fp", "",
223 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
224 "", "", "ehi", "", "", "", "epc", "prid",
227 /* Names of LSI 33k registers. */
229 char *mips_lsi33k_reg_names
[] = {
230 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
231 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
232 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
233 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
234 "epc", "hi", "lo", "sr", "cause","badvaddr",
235 "dcic", "bpc", "bda", "", "", "", "", "",
236 "", "", "", "", "", "", "", "",
237 "", "", "", "", "", "", "", "",
238 "", "", "", "", "", "", "", "",
240 "", "", "", "", "", "", "", "",
241 "", "", "", "", "", "", "", "",
247 } mips_processor_type_table
[] = {
248 { "generic", mips_generic_reg_names
},
249 { "r3041", mips_r3041_reg_names
},
250 { "r3051", mips_r3051_reg_names
},
251 { "r3071", mips_r3081_reg_names
},
252 { "r3081", mips_r3081_reg_names
},
253 { "lsi33k", mips_lsi33k_reg_names
},
261 /* Table to translate MIPS16 register field to actual register number. */
262 static int mips16_to_32_reg
[8] =
263 {16, 17, 2, 3, 4, 5, 6, 7};
265 /* Heuristic_proc_start may hunt through the text section for a long
266 time across a 2400 baud serial line. Allows the user to limit this
269 static unsigned int heuristic_fence_post
= 0;
271 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
272 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
273 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
274 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
275 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
276 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
277 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
278 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
279 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
280 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
281 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
282 #define _PROC_MAGIC_ 0x0F0F0F0F
283 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
284 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
286 struct linked_proc_info
288 struct mips_extra_func_info info
;
289 struct linked_proc_info
*next
;
291 *linked_proc_desc_table
= NULL
;
294 mips_print_extra_frame_info (fi
)
295 struct frame_info
*fi
;
299 && fi
->extra_info
->proc_desc
300 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
301 printf_filtered (" frame pointer is at %s+%s\n",
302 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
303 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
306 /* Convert between RAW and VIRTUAL registers. The RAW register size
307 defines the remote-gdb packet. */
309 static int mips64_transfers_32bit_regs_p
= 0;
312 mips_register_raw_size (reg_nr
)
315 if (mips64_transfers_32bit_regs_p
)
316 return REGISTER_VIRTUAL_SIZE (reg_nr
);
322 mips_register_convertible (reg_nr
)
325 if (mips64_transfers_32bit_regs_p
)
328 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
332 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
334 struct type
*virtual_type
;
338 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
340 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
341 TYPE_LENGTH (virtual_type
));
345 TYPE_LENGTH (virtual_type
));
349 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
350 struct type
*virtual_type
;
355 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
356 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
357 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
359 TYPE_LENGTH (virtual_type
));
363 TYPE_LENGTH (virtual_type
));
366 /* Should the upper word of 64-bit addresses be zeroed? */
367 static int mask_address_p
= 1;
369 /* Should call_function allocate stack space for a struct return? */
371 mips_use_struct_convention (gcc_p
, type
)
376 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
378 return 1; /* Structures are returned by ref in extra arg0 */
381 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
384 pc_is_mips16 (bfd_vma memaddr
)
386 struct minimal_symbol
*sym
;
388 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
389 if (IS_MIPS16_ADDR (memaddr
))
392 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
393 the high bit of the info field. Use this to decide if the function is
394 MIPS16 or normal MIPS. */
395 sym
= lookup_minimal_symbol_by_pc (memaddr
);
397 return MSYMBOL_IS_SPECIAL (sym
);
403 /* This returns the PC of the first inst after the prologue. If we can't
404 find the prologue, then return 0. */
407 after_prologue (pc
, proc_desc
)
409 mips_extra_func_info_t proc_desc
;
411 struct symtab_and_line sal
;
412 CORE_ADDR func_addr
, func_end
;
415 proc_desc
= find_proc_desc (pc
, NULL
);
419 /* If function is frameless, then we need to do it the hard way. I
420 strongly suspect that frameless always means prologueless... */
421 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
422 && PROC_FRAME_OFFSET (proc_desc
) == 0)
426 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
427 return 0; /* Unknown */
429 sal
= find_pc_line (func_addr
, 0);
431 if (sal
.end
< func_end
)
434 /* The line after the prologue is after the end of the function. In this
435 case, tell the caller to find the prologue the hard way. */
440 /* Decode a MIPS32 instruction that saves a register in the stack, and
441 set the appropriate bit in the general register mask or float register mask
442 to indicate which register is saved. This is a helper function
443 for mips_find_saved_regs. */
446 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
448 unsigned long *gen_mask
;
449 unsigned long *float_mask
;
453 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
454 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
455 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
457 /* It might be possible to use the instruction to
458 find the offset, rather than the code below which
459 is based on things being in a certain order in the
460 frame, but figuring out what the instruction's offset
461 is relative to might be a little tricky. */
462 reg
= (inst
& 0x001f0000) >> 16;
463 *gen_mask
|= (1 << reg
);
465 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
466 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
467 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
470 reg
= ((inst
& 0x001f0000) >> 16);
471 *float_mask
|= (1 << reg
);
475 /* Decode a MIPS16 instruction that saves a register in the stack, and
476 set the appropriate bit in the general register or float register mask
477 to indicate which register is saved. This is a helper function
478 for mips_find_saved_regs. */
481 mips16_decode_reg_save (inst
, gen_mask
)
483 unsigned long *gen_mask
;
485 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
487 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
488 *gen_mask
|= (1 << reg
);
490 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
492 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
493 *gen_mask
|= (1 << reg
);
495 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
496 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
497 *gen_mask
|= (1 << RA_REGNUM
);
501 /* Fetch and return instruction from the specified location. If the PC
502 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
505 mips_fetch_instruction (addr
)
508 char buf
[MIPS_INSTLEN
];
512 if (pc_is_mips16 (addr
))
514 instlen
= MIPS16_INSTLEN
;
515 addr
= UNMAKE_MIPS16_ADDR (addr
);
518 instlen
= MIPS_INSTLEN
;
519 status
= read_memory_nobpt (addr
, buf
, instlen
);
521 memory_error (status
, addr
);
522 return extract_unsigned_integer (buf
, instlen
);
526 /* These the fields of 32 bit mips instructions */
527 #define mips32_op(x) (x >> 25)
528 #define itype_op(x) (x >> 25)
529 #define itype_rs(x) ((x >> 21)& 0x1f)
530 #define itype_rt(x) ((x >> 16) & 0x1f)
531 #define itype_immediate(x) ( x & 0xffff)
533 #define jtype_op(x) (x >> 25)
534 #define jtype_target(x) ( x & 0x03fffff)
536 #define rtype_op(x) (x >>25)
537 #define rtype_rs(x) ((x>>21) & 0x1f)
538 #define rtype_rt(x) ((x>>16) & 0x1f)
539 #define rtype_rd(x) ((x>>11) & 0x1f)
540 #define rtype_shamt(x) ((x>>6) & 0x1f)
541 #define rtype_funct(x) (x & 0x3f )
544 mips32_relative_offset (unsigned long inst
)
547 x
= itype_immediate (inst
);
548 if (x
& 0x8000) /* sign bit set */
550 x
|= 0xffff0000; /* sign extension */
556 /* Determine whate to set a single step breakpoint while considering
559 mips32_next_pc (CORE_ADDR pc
)
563 inst
= mips_fetch_instruction (pc
);
564 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
566 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
568 op
= ((inst
>> 25) & 0x03);
572 goto equal_branch
; /* BEQL */
574 goto neq_branch
; /* BNEZ */
576 goto less_branch
; /* BLEZ */
578 goto greater_branch
; /* BGTZ */
584 pc
+= 4; /* Not a branch, next instruction is easy */
587 { /* This gets way messy */
589 /* Further subdivide into SPECIAL, REGIMM and other */
590 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
592 case 0: /* SPECIAL */
593 op
= rtype_funct (inst
);
598 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
604 break; /* end special */
607 op
= jtype_op (inst
); /* branch condition */
608 switch (jtype_op (inst
))
612 case 16: /* BLTZALL */
613 case 18: /* BLTZALL */
615 if (read_register (itype_rs (inst
)) < 0)
616 pc
+= mips32_relative_offset (inst
) + 4;
618 pc
+= 8; /* after the delay slot */
622 case 17: /* BGEZAL */
623 case 19: /* BGEZALL */
624 greater_equal_branch
:
625 if (read_register (itype_rs (inst
)) >= 0)
626 pc
+= mips32_relative_offset (inst
) + 4;
628 pc
+= 8; /* after the delay slot */
630 /* All of the other intructions in the REGIMM catagory */
635 break; /* end REGIMM */
640 reg
= jtype_target (inst
) << 2;
641 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
642 /* Whats this mysterious 0xf000000 adjustment ??? */
645 /* FIXME case JALX : */
648 reg
= jtype_target (inst
) << 2;
649 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
650 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
652 break; /* The new PC will be alternate mode */
653 case 4: /* BEQ , BEQL */
655 if (read_register (itype_rs (inst
)) ==
656 read_register (itype_rt (inst
)))
657 pc
+= mips32_relative_offset (inst
) + 4;
661 case 5: /* BNE , BNEL */
663 if (read_register (itype_rs (inst
)) !=
664 read_register (itype_rs (inst
)))
665 pc
+= mips32_relative_offset (inst
) + 4;
669 case 6: /* BLEZ , BLEZL */
671 if (read_register (itype_rs (inst
) <= 0))
672 pc
+= mips32_relative_offset (inst
) + 4;
677 greater_branch
: /* BGTZ BGTZL */
678 if (read_register (itype_rs (inst
) > 0))
679 pc
+= mips32_relative_offset (inst
) + 4;
688 } /* mips32_next_pc */
690 /* Decoding the next place to set a breakpoint is irregular for the
691 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
692 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
693 We dont want to set a single step instruction on the extend instruction
697 /* Lots of mips16 instruction formats */
698 /* Predicting jumps requires itype,ritype,i8type
699 and their extensions extItype,extritype,extI8type
701 enum mips16_inst_fmts
703 itype
, /* 0 immediate 5,10 */
704 ritype
, /* 1 5,3,8 */
705 rrtype
, /* 2 5,3,3,5 */
706 rritype
, /* 3 5,3,3,5 */
707 rrrtype
, /* 4 5,3,3,3,2 */
708 rriatype
, /* 5 5,3,3,1,4 */
709 shifttype
, /* 6 5,3,3,3,2 */
710 i8type
, /* 7 5,3,8 */
711 i8movtype
, /* 8 5,3,3,5 */
712 i8mov32rtype
, /* 9 5,3,5,3 */
713 i64type
, /* 10 5,3,8 */
714 ri64type
, /* 11 5,3,3,5 */
715 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
716 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
717 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
718 extRRItype
, /* 15 5,5,5,5,3,3,5 */
719 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
720 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
721 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
722 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
723 extRi64type
, /* 20 5,6,5,5,3,3,5 */
724 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
726 /* I am heaping all the fields of the formats into one structure and then,
727 only the fields which are involved in instruction extension */
731 enum mips16_inst_fmts fmt
;
732 unsigned long offset
;
733 unsigned int regx
; /* Function in i8 type */
740 print_unpack (char *comment
,
741 struct upk_mips16
*u
)
743 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
744 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
747 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
748 format for the bits which make up the immediatate extension.
751 extended_offset (unsigned long extension
)
754 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
756 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
758 value
|= extension
& 0x01f; /* extract 4:0 */
762 /* Only call this function if you know that this is an extendable
763 instruction, It wont malfunction, but why make excess remote memory references?
764 If the immediate operands get sign extended or somthing, do it after
765 the extension is performed.
767 /* FIXME: Every one of these cases needs to worry about sign extension
768 when the offset is to be used in relative addressing */
771 static unsigned short
772 fetch_mips_16 (CORE_ADDR pc
)
775 pc
&= 0xfffffffe; /* clear the low order bit */
776 target_read_memory (pc
, buf
, 2);
777 return extract_unsigned_integer (buf
, 2);
781 unpack_mips16 (CORE_ADDR pc
,
782 struct upk_mips16
*upk
)
785 unsigned long extension
;
787 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
788 /* Decrement to previous address and loose the 16bit mode flag */
789 /* return if the instruction was extendable, but not actually extended */
790 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
793 extension
= mips_fetch_instruction (extpc
);
802 value
= extended_offset (extension
);
803 value
= value
<< 11; /* rom for the original value */
804 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
808 value
= upk
->inst
& 0x7ff;
809 /* FIXME : Consider sign extension */
816 { /* A register identifier and an offset */
817 /* Most of the fields are the same as I type but the
818 immediate value is of a different length */
822 value
= extended_offset (extension
);
823 value
= value
<< 8; /* from the original instruction */
824 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
825 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
826 if (value
& 0x4000) /* test the sign bit , bit 26 */
828 value
&= ~0x3fff; /* remove the sign bit */
834 value
= upk
->inst
& 0xff; /* 8 bits */
835 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
836 /* FIXME: Do sign extension , this format needs it */
837 if (value
& 0x80) /* THIS CONFUSES ME */
839 value
&= 0xef; /* remove the sign bit */
850 unsigned short nexthalf
;
851 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
853 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
859 printf_filtered ("Decoding unimplemented instruction format type\n");
862 /* print_unpack("UPK",upk) ; */
866 #define mips16_op(x) (x >> 11)
868 /* This is a map of the opcodes which ae known to perform branches */
869 static unsigned char map16
[32] =
870 {0, 0, 1, 1, 1, 1, 0, 0,
871 0, 0, 0, 0, 1, 0, 0, 0,
872 0, 0, 0, 0, 0, 0, 0, 0,
873 0, 0, 0, 0, 0, 1, 1, 0
877 add_offset_16 (CORE_ADDR pc
, int offset
)
879 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
885 static struct upk_mips16 upk
;
888 mips16_next_pc (CORE_ADDR pc
)
892 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
893 inst
= fetch_mips_16 (pc
);
895 op
= mips16_op (upk
.inst
);
903 unpack_mips16 (pc
, &upk
);
912 pc
+= (offset
<< 1) + 2;
915 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
917 unpack_mips16 (pc
, &upk
);
918 pc
= add_offset_16 (pc
, upk
.offset
);
919 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
920 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
926 unpack_mips16 (pc
, &upk
);
927 reg
= read_register (upk
.regx
);
929 pc
+= (upk
.offset
<< 1) + 2;
935 unpack_mips16 (pc
, &upk
);
936 reg
= read_register (upk
.regx
);
938 pc
+= (upk
.offset
<< 1) + 2;
942 case 12: /* I8 Formats btez btnez */
944 unpack_mips16 (pc
, &upk
);
945 /* upk.regx contains the opcode */
946 reg
= read_register (24); /* Test register is 24 */
947 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
948 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
949 /* pc = add_offset_16(pc,upk.offset) ; */
950 pc
+= (upk
.offset
<< 1) + 2;
954 case 29: /* RR Formats JR, JALR, JALR-RA */
956 op
= upk
.inst
& 0x1f;
959 upk
.regx
= (upk
.inst
>> 8) & 0x07;
960 upk
.regy
= (upk
.inst
>> 5) & 0x07;
968 break; /* Function return instruction */
974 break; /* BOGUS Guess */
976 pc
= read_register (reg
);
981 case 30: /* This is an extend instruction */
982 pc
+= 4; /* Dont be setting breakpints on the second half */
985 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
991 pc
+= 2; /* just a good old instruction */
992 /* See if we CAN actually break on the next instruction */
993 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
995 } /* mips16_next_pc */
997 /* The mips_next_pc function supports single_tep when the remote target monitor or
998 stub is not developed enough to so a single_step.
999 It works by decoding the current instruction and predicting where a branch
1000 will go. This isnt hard because all the data is available.
1001 The MIPS32 and MIPS16 variants are quite different
1004 mips_next_pc (CORE_ADDR pc
)
1007 /* inst = mips_fetch_instruction(pc) ; */
1008 /* if (pc_is_mips16) <----- This is failing */
1010 return mips16_next_pc (pc
);
1012 return mips32_next_pc (pc
);
1013 } /* mips_next_pc */
1015 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1019 mips_find_saved_regs (fci
)
1020 struct frame_info
*fci
;
1023 CORE_ADDR reg_position
;
1024 /* r0 bit means kernel trap */
1026 /* What registers have been saved? Bitmasks. */
1027 unsigned long gen_mask
, float_mask
;
1028 mips_extra_func_info_t proc_desc
;
1031 frame_saved_regs_zalloc (fci
);
1033 /* If it is the frame for sigtramp, the saved registers are located
1034 in a sigcontext structure somewhere on the stack.
1035 If the stack layout for sigtramp changes we might have to change these
1036 constants and the companion fixup_sigtramp in mdebugread.c */
1037 #ifndef SIGFRAME_BASE
1038 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1039 above the sigtramp frame. */
1040 #define SIGFRAME_BASE MIPS_REGSIZE
1041 /* FIXME! Are these correct?? */
1042 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1043 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1044 #define SIGFRAME_FPREGSAVE_OFF \
1045 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1047 #ifndef SIGFRAME_REG_SIZE
1048 /* FIXME! Is this correct?? */
1049 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1051 if (fci
->signal_handler_caller
)
1053 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1055 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1056 + ireg
* SIGFRAME_REG_SIZE
;
1057 fci
->saved_regs
[ireg
] = reg_position
;
1059 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1061 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1062 + ireg
* SIGFRAME_REG_SIZE
;
1063 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1065 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1069 proc_desc
= fci
->extra_info
->proc_desc
;
1070 if (proc_desc
== NULL
)
1071 /* I'm not sure how/whether this can happen. Normally when we can't
1072 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1073 and set the saved_regs right away. */
1076 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1077 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1078 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1080 if ( /* In any frame other than the innermost or a frame interrupted by
1081 a signal, we assume that all registers have been saved.
1082 This assumes that all register saves in a function happen before
1083 the first function call. */
1084 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1086 /* In a dummy frame we know exactly where things are saved. */
1087 && !PROC_DESC_IS_DUMMY (proc_desc
)
1089 /* Don't bother unless we are inside a function prologue. Outside the
1090 prologue, we know where everything is. */
1092 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1094 /* Not sure exactly what kernel_trap means, but if it means
1095 the kernel saves the registers without a prologue doing it,
1096 we better not examine the prologue to see whether registers
1097 have been saved yet. */
1100 /* We need to figure out whether the registers that the proc_desc
1101 claims are saved have been saved yet. */
1105 /* Bitmasks; set if we have found a save for the register. */
1106 unsigned long gen_save_found
= 0;
1107 unsigned long float_save_found
= 0;
1110 /* If the address is odd, assume this is MIPS16 code. */
1111 addr
= PROC_LOW_ADDR (proc_desc
);
1112 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1114 /* Scan through this function's instructions preceding the current
1115 PC, and look for those that save registers. */
1116 while (addr
< fci
->pc
)
1118 inst
= mips_fetch_instruction (addr
);
1119 if (pc_is_mips16 (addr
))
1120 mips16_decode_reg_save (inst
, &gen_save_found
);
1122 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1125 gen_mask
= gen_save_found
;
1126 float_mask
= float_save_found
;
1129 /* Fill in the offsets for the registers which gen_mask says
1131 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1132 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1133 if (gen_mask
& 0x80000000)
1135 fci
->saved_regs
[ireg
] = reg_position
;
1136 reg_position
-= MIPS_SAVED_REGSIZE
;
1139 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1140 of that normally used by gcc. Therefore, we have to fetch the first
1141 instruction of the function, and if it's an entry instruction that
1142 saves $s0 or $s1, correct their saved addresses. */
1143 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1145 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1146 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1149 int sreg_count
= (inst
>> 6) & 3;
1151 /* Check if the ra register was pushed on the stack. */
1152 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1154 reg_position
-= MIPS_SAVED_REGSIZE
;
1156 /* Check if the s0 and s1 registers were pushed on the stack. */
1157 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1159 fci
->saved_regs
[reg
] = reg_position
;
1160 reg_position
-= MIPS_SAVED_REGSIZE
;
1165 /* Fill in the offsets for the registers which float_mask says
1167 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1169 /* The freg_offset points to where the first *double* register
1170 is saved. So skip to the high-order word. */
1171 if (!GDB_TARGET_IS_MIPS64
)
1172 reg_position
+= MIPS_SAVED_REGSIZE
;
1174 /* Fill in the offsets for the float registers which float_mask says
1176 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1177 if (float_mask
& 0x80000000)
1179 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1180 reg_position
-= MIPS_SAVED_REGSIZE
;
1183 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1187 read_next_frame_reg (fi
, regno
)
1188 struct frame_info
*fi
;
1191 for (; fi
; fi
= fi
->next
)
1193 /* We have to get the saved sp from the sigcontext
1194 if it is a signal handler frame. */
1195 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1199 if (fi
->saved_regs
== NULL
)
1200 mips_find_saved_regs (fi
);
1201 if (fi
->saved_regs
[regno
])
1202 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1205 return read_register (regno
);
1208 /* mips_addr_bits_remove - remove useless address bits */
1211 mips_addr_bits_remove (addr
)
1214 #if GDB_TARGET_IS_MIPS64
1215 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1217 /* This hack is a work-around for existing boards using PMON,
1218 the simulator, and any other 64-bit targets that doesn't have
1219 true 64-bit addressing. On these targets, the upper 32 bits
1220 of addresses are ignored by the hardware. Thus, the PC or SP
1221 are likely to have been sign extended to all 1s by instruction
1222 sequences that load 32-bit addresses. For example, a typical
1223 piece of code that loads an address is this:
1224 lui $r2, <upper 16 bits>
1225 ori $r2, <lower 16 bits>
1226 But the lui sign-extends the value such that the upper 32 bits
1227 may be all 1s. The workaround is simply to mask off these bits.
1228 In the future, gcc may be changed to support true 64-bit
1229 addressing, and this masking will have to be disabled. */
1230 addr
&= (CORE_ADDR
) 0xffffffff;
1233 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1234 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1235 So we still have to mask off useless bits from addresses. */
1236 addr
&= (CORE_ADDR
) 0xffffffff;
1243 mips_init_frame_pc_first (fromleaf
, prev
)
1245 struct frame_info
*prev
;
1249 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1250 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1251 tmp
= mips_skip_stub (pc
);
1252 prev
->pc
= tmp
? tmp
: pc
;
1257 mips_frame_saved_pc (frame
)
1258 struct frame_info
*frame
;
1261 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1262 /* We have to get the saved pc from the sigcontext
1263 if it is a signal handler frame. */
1264 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1265 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1267 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1268 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1270 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1272 return ADDR_BITS_REMOVE (saved_pc
);
1275 static struct mips_extra_func_info temp_proc_desc
;
1276 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1278 /* Set a register's saved stack address in temp_saved_regs. If an address
1279 has already been set for this register, do nothing; this way we will
1280 only recognize the first save of a given register in a function prologue.
1281 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1284 set_reg_offset (regno
, offset
)
1288 if (temp_saved_regs
[regno
] == 0)
1289 temp_saved_regs
[regno
] = offset
;
1293 /* Test whether the PC points to the return instruction at the
1294 end of a function. */
1297 mips_about_to_return (pc
)
1300 if (pc_is_mips16 (pc
))
1301 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1302 generates a "jr $ra"; other times it generates code to load
1303 the return address from the stack to an accessible register (such
1304 as $a3), then a "jr" using that register. This second case
1305 is almost impossible to distinguish from an indirect jump
1306 used for switch statements, so we don't even try. */
1307 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1309 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1313 /* This fencepost looks highly suspicious to me. Removing it also
1314 seems suspicious as it could affect remote debugging across serial
1318 heuristic_proc_start (pc
)
1326 pc
= ADDR_BITS_REMOVE (pc
);
1328 fence
= start_pc
- heuristic_fence_post
;
1332 if (heuristic_fence_post
== UINT_MAX
1333 || fence
< VM_MIN_ADDRESS
)
1334 fence
= VM_MIN_ADDRESS
;
1336 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1338 /* search back for previous return */
1339 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1340 if (start_pc
< fence
)
1342 /* It's not clear to me why we reach this point when
1343 stop_soon_quietly, but with this test, at least we
1344 don't print out warnings for every child forked (eg, on
1345 decstation). 22apr93 rich@cygnus.com. */
1346 if (!stop_soon_quietly
)
1348 static int blurb_printed
= 0;
1350 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1355 /* This actually happens frequently in embedded
1356 development, when you first connect to a board
1357 and your stack pointer and pc are nowhere in
1358 particular. This message needs to give people
1359 in that situation enough information to
1360 determine that it's no big deal. */
1361 printf_filtered ("\n\
1362 GDB is unable to find the start of the function at 0x%s\n\
1363 and thus can't determine the size of that function's stack frame.\n\
1364 This means that GDB may be unable to access that stack frame, or\n\
1365 the frames below it.\n\
1366 This problem is most likely caused by an invalid program counter or\n\
1368 However, if you think GDB should simply search farther back\n\
1369 from 0x%s for code which looks like the beginning of a\n\
1370 function, you can increase the range of the search using the `set\n\
1371 heuristic-fence-post' command.\n",
1372 paddr_nz (pc
), paddr_nz (pc
));
1379 else if (pc_is_mips16 (start_pc
))
1381 unsigned short inst
;
1383 /* On MIPS16, any one of the following is likely to be the
1384 start of a function:
1388 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1389 inst
= mips_fetch_instruction (start_pc
);
1390 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1391 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1392 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1393 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1395 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1396 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1401 else if (mips_about_to_return (start_pc
))
1403 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1408 /* skip nops (usually 1) 0 - is this */
1409 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1410 start_pc
+= MIPS_INSTLEN
;
1415 /* Fetch the immediate value from a MIPS16 instruction.
1416 If the previous instruction was an EXTEND, use it to extend
1417 the upper bits of the immediate value. This is a helper function
1418 for mips16_heuristic_proc_desc. */
1421 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1422 unsigned short prev_inst
; /* previous instruction */
1423 unsigned short inst
; /* current instruction */
1424 int nbits
; /* number of bits in imm field */
1425 int scale
; /* scale factor to be applied to imm */
1426 int is_signed
; /* is the imm field signed? */
1430 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1432 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1433 if (offset
& 0x8000) /* check for negative extend */
1434 offset
= 0 - (0x10000 - (offset
& 0xffff));
1435 return offset
| (inst
& 0x1f);
1439 int max_imm
= 1 << nbits
;
1440 int mask
= max_imm
- 1;
1441 int sign_bit
= max_imm
>> 1;
1443 offset
= inst
& mask
;
1444 if (is_signed
&& (offset
& sign_bit
))
1445 offset
= 0 - (max_imm
- offset
);
1446 return offset
* scale
;
1451 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1452 stream from start_pc to limit_pc. */
1455 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1456 CORE_ADDR start_pc
, limit_pc
;
1457 struct frame_info
*next_frame
;
1461 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1462 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1463 unsigned inst
= 0; /* current instruction */
1464 unsigned entry_inst
= 0; /* the entry instruction */
1467 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1468 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1470 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1472 /* Save the previous instruction. If it's an EXTEND, we'll extract
1473 the immediate offset extension from it in mips16_get_imm. */
1476 /* Fetch and decode the instruction. */
1477 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1478 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1479 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1481 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1482 if (offset
< 0) /* negative stack adjustment? */
1483 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1485 /* Exit loop if a positive stack adjustment is found, which
1486 usually means that the stack cleanup code in the function
1487 epilogue is reached. */
1490 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1492 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1493 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1494 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1495 set_reg_offset (reg
, sp
+ offset
);
1497 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1499 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1500 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1501 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1502 set_reg_offset (reg
, sp
+ offset
);
1504 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1506 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1507 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1508 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1510 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1513 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1514 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1516 else if (inst
== 0x673d) /* move $s1, $sp */
1519 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1521 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1523 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1524 frame_addr
= sp
+ offset
;
1525 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1526 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1528 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1530 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1531 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1532 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1533 set_reg_offset (reg
, frame_addr
+ offset
);
1535 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1537 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1538 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1539 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1540 set_reg_offset (reg
, frame_addr
+ offset
);
1542 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1543 entry_inst
= inst
; /* save for later processing */
1544 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1545 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1548 /* The entry instruction is typically the first instruction in a function,
1549 and it stores registers at offsets relative to the value of the old SP
1550 (before the prologue). But the value of the sp parameter to this
1551 function is the new SP (after the prologue has been executed). So we
1552 can't calculate those offsets until we've seen the entire prologue,
1553 and can calculate what the old SP must have been. */
1554 if (entry_inst
!= 0)
1556 int areg_count
= (entry_inst
>> 8) & 7;
1557 int sreg_count
= (entry_inst
>> 6) & 3;
1559 /* The entry instruction always subtracts 32 from the SP. */
1560 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1562 /* Now we can calculate what the SP must have been at the
1563 start of the function prologue. */
1564 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1566 /* Check if a0-a3 were saved in the caller's argument save area. */
1567 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1569 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1570 set_reg_offset (reg
, sp
+ offset
);
1571 offset
+= MIPS_SAVED_REGSIZE
;
1574 /* Check if the ra register was pushed on the stack. */
1576 if (entry_inst
& 0x20)
1578 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1579 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1580 offset
-= MIPS_SAVED_REGSIZE
;
1583 /* Check if the s0 and s1 registers were pushed on the stack. */
1584 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1586 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1587 set_reg_offset (reg
, sp
+ offset
);
1588 offset
-= MIPS_SAVED_REGSIZE
;
1594 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1595 CORE_ADDR start_pc
, limit_pc
;
1596 struct frame_info
*next_frame
;
1600 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1602 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1603 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1604 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1605 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1607 unsigned long inst
, high_word
, low_word
;
1610 /* Fetch the instruction. */
1611 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1613 /* Save some code by pre-extracting some useful fields. */
1614 high_word
= (inst
>> 16) & 0xffff;
1615 low_word
= inst
& 0xffff;
1616 reg
= high_word
& 0x1f;
1618 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1619 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1620 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1622 if (low_word
& 0x8000) /* negative stack adjustment? */
1623 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1625 /* Exit loop if a positive stack adjustment is found, which
1626 usually means that the stack cleanup code in the function
1627 epilogue is reached. */
1630 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1632 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1633 set_reg_offset (reg
, sp
+ low_word
);
1635 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1637 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1638 but the register size used is only 32 bits. Make the address
1639 for the saved register point to the lower 32 bits. */
1640 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1641 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1643 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1645 /* Old gcc frame, r30 is virtual frame pointer. */
1646 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1647 frame_addr
= sp
+ low_word
;
1648 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1650 unsigned alloca_adjust
;
1651 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1652 frame_addr
= read_next_frame_reg (next_frame
, 30);
1653 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1654 if (alloca_adjust
> 0)
1656 /* FP > SP + frame_size. This may be because
1657 * of an alloca or somethings similar.
1658 * Fix sp to "pre-alloca" value, and try again.
1660 sp
+= alloca_adjust
;
1665 /* move $30,$sp. With different versions of gas this will be either
1666 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1667 Accept any one of these. */
1668 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1670 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1671 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1673 unsigned alloca_adjust
;
1674 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1675 frame_addr
= read_next_frame_reg (next_frame
, 30);
1676 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1677 if (alloca_adjust
> 0)
1679 /* FP > SP + frame_size. This may be because
1680 * of an alloca or somethings similar.
1681 * Fix sp to "pre-alloca" value, and try again.
1683 sp
+= alloca_adjust
;
1688 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1690 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1691 set_reg_offset (reg
, frame_addr
+ low_word
);
1696 static mips_extra_func_info_t
1697 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1698 CORE_ADDR start_pc
, limit_pc
;
1699 struct frame_info
*next_frame
;
1701 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1705 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1706 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1707 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1708 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1709 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1711 if (start_pc
+ 200 < limit_pc
)
1712 limit_pc
= start_pc
+ 200;
1713 if (pc_is_mips16 (start_pc
))
1714 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1716 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1717 return &temp_proc_desc
;
1720 static mips_extra_func_info_t
1721 non_heuristic_proc_desc (pc
, addrptr
)
1725 CORE_ADDR startaddr
;
1726 mips_extra_func_info_t proc_desc
;
1727 struct block
*b
= block_for_pc (pc
);
1730 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1732 *addrptr
= startaddr
;
1733 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1737 if (startaddr
> BLOCK_START (b
))
1738 /* This is the "pathological" case referred to in a comment in
1739 print_frame_info. It might be better to move this check into
1743 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1746 /* If we never found a PDR for this function in symbol reading, then
1747 examine prologues to find the information. */
1750 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1751 if (PROC_FRAME_REG (proc_desc
) == -1)
1761 static mips_extra_func_info_t
1762 find_proc_desc (pc
, next_frame
)
1764 struct frame_info
*next_frame
;
1766 mips_extra_func_info_t proc_desc
;
1767 CORE_ADDR startaddr
;
1769 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1773 /* IF this is the topmost frame AND
1774 * (this proc does not have debugging information OR
1775 * the PC is in the procedure prologue)
1776 * THEN create a "heuristic" proc_desc (by analyzing
1777 * the actual code) to replace the "official" proc_desc.
1779 if (next_frame
== NULL
)
1781 struct symtab_and_line val
;
1782 struct symbol
*proc_symbol
=
1783 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1787 val
= find_pc_line (BLOCK_START
1788 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1790 val
.pc
= val
.end
? val
.end
: pc
;
1792 if (!proc_symbol
|| pc
< val
.pc
)
1794 mips_extra_func_info_t found_heuristic
=
1795 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1797 if (found_heuristic
)
1798 proc_desc
= found_heuristic
;
1804 /* Is linked_proc_desc_table really necessary? It only seems to be used
1805 by procedure call dummys. However, the procedures being called ought
1806 to have their own proc_descs, and even if they don't,
1807 heuristic_proc_desc knows how to create them! */
1809 register struct linked_proc_info
*link
;
1811 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1812 if (PROC_LOW_ADDR (&link
->info
) <= pc
1813 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1817 startaddr
= heuristic_proc_start (pc
);
1820 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1826 get_frame_pointer (frame
, proc_desc
)
1827 struct frame_info
*frame
;
1828 mips_extra_func_info_t proc_desc
;
1830 return ADDR_BITS_REMOVE (
1831 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1832 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1835 mips_extra_func_info_t cached_proc_desc
;
1838 mips_frame_chain (frame
)
1839 struct frame_info
*frame
;
1841 mips_extra_func_info_t proc_desc
;
1843 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1845 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1848 /* Check if the PC is inside a call stub. If it is, fetch the
1849 PC of the caller of that stub. */
1850 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1853 /* Look up the procedure descriptor for this PC. */
1854 proc_desc
= find_proc_desc (saved_pc
, frame
);
1858 cached_proc_desc
= proc_desc
;
1860 /* If no frame pointer and frame size is zero, we must be at end
1861 of stack (or otherwise hosed). If we don't check frame size,
1862 we loop forever if we see a zero size frame. */
1863 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1864 && PROC_FRAME_OFFSET (proc_desc
) == 0
1865 /* The previous frame from a sigtramp frame might be frameless
1866 and have frame size zero. */
1867 && !frame
->signal_handler_caller
)
1870 return get_frame_pointer (frame
, proc_desc
);
1874 mips_init_extra_frame_info (fromleaf
, fci
)
1876 struct frame_info
*fci
;
1880 /* Use proc_desc calculated in frame_chain */
1881 mips_extra_func_info_t proc_desc
=
1882 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1884 fci
->extra_info
= (struct frame_extra_info
*)
1885 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1887 fci
->saved_regs
= NULL
;
1888 fci
->extra_info
->proc_desc
=
1889 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1892 /* Fixup frame-pointer - only needed for top frame */
1893 /* This may not be quite right, if proc has a real frame register.
1894 Get the value of the frame relative sp, procedure might have been
1895 interrupted by a signal at it's very start. */
1896 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1897 && !PROC_DESC_IS_DUMMY (proc_desc
))
1898 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1900 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1902 if (proc_desc
== &temp_proc_desc
)
1906 /* Do not set the saved registers for a sigtramp frame,
1907 mips_find_saved_registers will do that for us.
1908 We can't use fci->signal_handler_caller, it is not yet set. */
1909 find_pc_partial_function (fci
->pc
, &name
,
1910 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1911 if (!IN_SIGTRAMP (fci
->pc
, name
))
1913 frame_saved_regs_zalloc (fci
);
1914 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1915 fci
->saved_regs
[PC_REGNUM
]
1916 = fci
->saved_regs
[RA_REGNUM
];
1920 /* hack: if argument regs are saved, guess these contain args */
1921 /* assume we can't tell how many args for now */
1922 fci
->extra_info
->num_args
= -1;
1923 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1925 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1927 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1934 /* MIPS stack frames are almost impenetrable. When execution stops,
1935 we basically have to look at symbol information for the function
1936 that we stopped in, which tells us *which* register (if any) is
1937 the base of the frame pointer, and what offset from that register
1938 the frame itself is at.
1940 This presents a problem when trying to examine a stack in memory
1941 (that isn't executing at the moment), using the "frame" command. We
1942 don't have a PC, nor do we have any registers except SP.
1944 This routine takes two arguments, SP and PC, and tries to make the
1945 cached frames look as if these two arguments defined a frame on the
1946 cache. This allows the rest of info frame to extract the important
1947 arguments without difficulty. */
1950 setup_arbitrary_frame (argc
, argv
)
1955 error ("MIPS frame specifications require two arguments: sp and pc");
1957 return create_new_frame (argv
[0], argv
[1]);
1961 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1963 * For n32 ABI, eight.
1964 * For all others, he same as the size of a general register.
1966 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1967 #define MIPS_NABI32 1
1968 #define STACK_ARGSIZE 8
1970 #define MIPS_NABI32 0
1971 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1975 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1980 CORE_ADDR struct_addr
;
1986 int stack_offset
= 0;
1988 /* Macros to round N up or down to the next A boundary; A must be
1990 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1991 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1993 /* First ensure that the stack and structure return address (if any)
1994 are properly aligned. The stack has to be at least 64-bit aligned
1995 even on 32-bit machines, because doubles must be 64-bit aligned.
1996 On at least one MIPS variant, stack frames need to be 128-bit
1997 aligned, so we round to this widest known alignment. */
1998 sp
= ROUND_DOWN (sp
, 16);
1999 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
2001 /* Now make space on the stack for the args. We allocate more
2002 than necessary for EABI, because the first few arguments are
2003 passed in registers, but that's OK. */
2004 for (argnum
= 0; argnum
< nargs
; argnum
++)
2005 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
2006 sp
-= ROUND_UP (len
, 16);
2008 /* Initialize the integer and float register pointers. */
2010 float_argreg
= FPA0_REGNUM
;
2012 /* the struct_return pointer occupies the first parameter-passing reg */
2014 write_register (argreg
++, struct_addr
);
2016 /* Now load as many as possible of the first arguments into
2017 registers, and push the rest onto the stack. Loop thru args
2018 from first to last. */
2019 for (argnum
= 0; argnum
< nargs
; argnum
++)
2022 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2023 value_ptr arg
= args
[argnum
];
2024 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2025 int len
= TYPE_LENGTH (arg_type
);
2026 enum type_code typecode
= TYPE_CODE (arg_type
);
2028 /* The EABI passes structures that do not fit in a register by
2029 reference. In all other cases, pass the structure by value. */
2030 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
2031 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2033 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2034 typecode
= TYPE_CODE_PTR
;
2035 len
= MIPS_SAVED_REGSIZE
;
2039 val
= (char *) VALUE_CONTENTS (arg
);
2041 /* 32-bit ABIs always start floating point arguments in an
2042 even-numbered floating point register. */
2043 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2044 && (float_argreg
& 1))
2047 /* Floating point arguments passed in registers have to be
2048 treated specially. On 32-bit architectures, doubles
2049 are passed in register pairs; the even register gets
2050 the low word, and the odd register gets the high word.
2051 On non-EABI processors, the first two floating point arguments are
2052 also copied to general registers, because MIPS16 functions
2053 don't use float registers for arguments. This duplication of
2054 arguments in general registers can't hurt non-MIPS16 functions
2055 because those registers are normally skipped. */
2056 if (typecode
== TYPE_CODE_FLT
2057 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2058 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2060 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2062 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2063 unsigned long regval
;
2065 /* Write the low word of the double to the even register(s). */
2066 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2067 write_register (float_argreg
++, regval
);
2069 write_register (argreg
+ 1, regval
);
2071 /* Write the high word of the double to the odd register(s). */
2072 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2073 write_register (float_argreg
++, regval
);
2076 write_register (argreg
, regval
);
2083 /* This is a floating point value that fits entirely
2084 in a single register. */
2085 /* On 32 bit ABI's the float_argreg is further adjusted
2086 above to ensure that it is even register aligned. */
2087 CORE_ADDR regval
= extract_address (val
, len
);
2088 write_register (float_argreg
++, regval
);
2091 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2092 registers for each argument. The below is (my
2093 guess) to ensure that the corresponding integer
2094 register has reserved the same space. */
2095 write_register (argreg
, regval
);
2096 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2102 /* Copy the argument to general registers or the stack in
2103 register-sized pieces. Large arguments are split between
2104 registers and stack. */
2105 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2106 are treated specially: Irix cc passes them in registers
2107 where gcc sometimes puts them on the stack. For maximum
2108 compatibility, we will put them in both places. */
2110 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2111 (len
% MIPS_SAVED_REGSIZE
!= 0));
2114 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2116 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2118 /* Write this portion of the argument to the stack. */
2119 /* Should shorter than int integer values be
2120 promoted to int before being stored? */
2122 int longword_offset
= 0;
2123 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2125 if (STACK_ARGSIZE
== 8 &&
2126 (typecode
== TYPE_CODE_INT
||
2127 typecode
== TYPE_CODE_PTR
||
2128 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2129 longword_offset
= STACK_ARGSIZE
- len
;
2130 else if ((typecode
== TYPE_CODE_STRUCT
||
2131 typecode
== TYPE_CODE_UNION
) &&
2132 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2133 longword_offset
= STACK_ARGSIZE
- len
;
2136 write_memory (sp
+ stack_offset
+ longword_offset
,
2140 /* Note!!! This is NOT an else clause.
2141 Odd sized structs may go thru BOTH paths. */
2142 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2144 CORE_ADDR regval
= extract_address (val
, partial_len
);
2146 /* A non-floating-point argument being passed in a
2147 general register. If a struct or union, and if
2148 the remaining length is smaller than the register
2149 size, we have to adjust the register value on
2152 It does not seem to be necessary to do the
2153 same for integral types.
2155 Also don't do this adjustment on EABI and O64
2159 && MIPS_SAVED_REGSIZE
< 8
2160 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2161 && partial_len
< MIPS_SAVED_REGSIZE
2162 && (typecode
== TYPE_CODE_STRUCT
||
2163 typecode
== TYPE_CODE_UNION
))
2164 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2167 write_register (argreg
, regval
);
2170 /* If this is the old ABI, prevent subsequent floating
2171 point arguments from being passed in floating point
2174 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2180 /* The offset onto the stack at which we will start
2181 copying parameters (after the registers are used up)
2182 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2183 leaves room for the "home" area for register parameters.
2185 In the new EABI (and the NABI32), the 8 register parameters
2186 do not have "home" stack space reserved for them, so the
2187 stack offset does not get incremented until after
2188 we have used up the 8 parameter registers. */
2190 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2192 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2197 /* Return adjusted stack pointer. */
2202 mips_push_return_address (pc
, sp
)
2206 /* Set the return address register to point to the entry
2207 point of the program, where a breakpoint lies in wait. */
2208 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2213 mips_push_register (CORE_ADDR
* sp
, int regno
)
2215 char buffer
[MAX_REGISTER_RAW_SIZE
];
2218 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2220 regsize
= MIPS_SAVED_REGSIZE
;
2221 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2222 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2227 regsize
= REGISTER_RAW_SIZE (regno
);
2231 read_register_gen (regno
, buffer
);
2232 write_memory (*sp
, buffer
+ offset
, regsize
);
2235 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2236 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2239 mips_push_dummy_frame ()
2242 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2243 xmalloc (sizeof (struct linked_proc_info
));
2244 mips_extra_func_info_t proc_desc
= &link
->info
;
2245 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2246 CORE_ADDR old_sp
= sp
;
2247 link
->next
= linked_proc_desc_table
;
2248 linked_proc_desc_table
= link
;
2250 /* FIXME! are these correct ? */
2251 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2252 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2253 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2254 #define FLOAT_SINGLE_REG_SAVE_MASK \
2255 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2257 * The registers we must save are all those not preserved across
2258 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2259 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2260 * and FP Control/Status registers.
2263 * Dummy frame layout:
2266 * Saved MMHI, MMLO, FPC_CSR
2271 * Saved D18 (i.e. F19, F18)
2273 * Saved D0 (i.e. F1, F0)
2274 * Argument build area and stack arguments written via mips_push_arguments
2278 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2279 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2280 PROC_FRAME_OFFSET (proc_desc
) = 0;
2281 PROC_FRAME_ADJUST (proc_desc
) = 0;
2282 mips_push_register (&sp
, PC_REGNUM
);
2283 mips_push_register (&sp
, HI_REGNUM
);
2284 mips_push_register (&sp
, LO_REGNUM
);
2285 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2287 /* Save general CPU registers */
2288 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2289 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2290 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2291 for (ireg
= 32; --ireg
>= 0;)
2292 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2293 mips_push_register (&sp
, ireg
);
2295 /* Save floating point registers starting with high order word */
2296 PROC_FREG_MASK (proc_desc
) =
2297 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2298 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2299 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2301 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2302 for (ireg
= 32; --ireg
>= 0;)
2303 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2304 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2306 /* Update the frame pointer for the call dummy and the stack pointer.
2307 Set the procedure's starting and ending addresses to point to the
2308 call dummy address at the entry point. */
2309 write_register (PUSH_FP_REGNUM
, old_sp
);
2310 write_register (SP_REGNUM
, sp
);
2311 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2312 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2313 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2314 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2320 register int regnum
;
2321 struct frame_info
*frame
= get_current_frame ();
2322 CORE_ADDR new_sp
= FRAME_FP (frame
);
2324 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2326 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2327 if (frame
->saved_regs
== NULL
)
2328 mips_find_saved_regs (frame
);
2329 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2331 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2332 && frame
->saved_regs
[regnum
])
2333 write_register (regnum
,
2334 read_memory_integer (frame
->saved_regs
[regnum
],
2335 MIPS_SAVED_REGSIZE
));
2337 write_register (SP_REGNUM
, new_sp
);
2338 flush_cached_frames ();
2340 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2342 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2344 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2346 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2348 if (&pi_ptr
->info
== proc_desc
)
2353 error ("Can't locate dummy extra frame info\n");
2355 if (prev_ptr
!= NULL
)
2356 prev_ptr
->next
= pi_ptr
->next
;
2358 linked_proc_desc_table
= pi_ptr
->next
;
2362 write_register (HI_REGNUM
,
2363 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2364 MIPS_SAVED_REGSIZE
));
2365 write_register (LO_REGNUM
,
2366 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2367 MIPS_SAVED_REGSIZE
));
2368 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2369 write_register (FCRCS_REGNUM
,
2370 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2371 MIPS_SAVED_REGSIZE
));
2376 mips_print_register (regnum
, all
)
2379 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2381 /* Get the data in raw format. */
2382 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2384 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2388 /* If an even floating point register, also print as double. */
2389 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2390 && !((regnum
- FP0_REGNUM
) & 1))
2391 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2393 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2395 read_relative_register_raw_bytes (regnum
, dbuffer
);
2396 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2397 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2399 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2400 val_print (builtin_type_double
, dbuffer
, 0, 0,
2401 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2402 printf_filtered ("); ");
2404 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2406 /* The problem with printing numeric register names (r26, etc.) is that
2407 the user can't use them on input. Probably the best solution is to
2408 fix it so that either the numeric or the funky (a2, etc.) names
2409 are accepted on input. */
2410 if (regnum
< MIPS_NUMREGS
)
2411 printf_filtered ("(r%d): ", regnum
);
2413 printf_filtered (": ");
2415 /* If virtual format is floating, print it that way. */
2416 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2417 if (FP_REGISTER_DOUBLE
)
2418 { /* show 8-byte floats as float AND double: */
2419 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2421 printf_filtered (" (float) ");
2422 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2423 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2424 printf_filtered (", (double) ");
2425 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2426 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2429 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2430 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2431 /* Else print as integer in hex. */
2433 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2434 'x', 0, gdb_stdout
);
2437 /* Replacement for generic do_registers_info.
2438 Print regs in pretty columns. */
2441 do_fp_register_row (regnum
)
2443 { /* do values for FP (float) regs */
2444 char *raw_buffer
[2];
2446 /* use HI and LO to control the order of combining two flt regs */
2447 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2448 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2449 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2450 int inv1
, inv2
, inv3
;
2452 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2453 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2454 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2456 /* Get the data in raw format. */
2457 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2458 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2459 if (REGISTER_RAW_SIZE (regnum
) == 4)
2461 /* 4-byte registers: we can fit two registers per row. */
2462 /* Also print every pair of 4-byte regs as an 8-byte double. */
2463 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2464 error ("can't read register %d (%s)",
2465 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2467 /* copy the two floats into one double, and unpack both */
2468 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2469 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2470 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2471 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2473 printf_filtered (inv1
? " %-5s: <invalid float>" :
2474 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2475 printf_filtered (inv2
? " %-5s: <invalid float>" :
2476 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2477 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2478 " dbl: %-24.17g\n", doub
);
2479 /* may want to do hex display here (future enhancement) */
2483 { /* eight byte registers: print each one as float AND as double. */
2484 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2486 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2487 flt1
= unpack_double (builtin_type_float
,
2488 &raw_buffer
[HI
][offset
], &inv1
);
2489 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2491 printf_filtered (inv1
? " %-5s: <invalid float>" :
2492 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2493 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2494 " dbl: %-24.17g\n", doub
);
2495 /* may want to do hex display here (future enhancement) */
2501 /* Print a row's worth of GP (int) registers, with name labels above */
2504 do_gp_register_row (regnum
)
2507 /* do values for GP (int) regs */
2508 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2509 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2511 int start_regnum
= regnum
;
2512 int numregs
= NUM_REGS
;
2515 /* For GP registers, we print a separate row of names above the vals */
2516 printf_filtered (" ");
2517 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2519 if (*REGISTER_NAME (regnum
) == '\0')
2520 continue; /* unused register */
2521 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2522 break; /* end the row: reached FP register */
2523 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2524 REGISTER_NAME (regnum
));
2527 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2528 start_regnum
); /* print the R0 to R31 names */
2530 regnum
= start_regnum
; /* go back to start of row */
2531 /* now print the values in hex, 4 or 8 to the row */
2532 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2534 if (*REGISTER_NAME (regnum
) == '\0')
2535 continue; /* unused register */
2536 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2537 break; /* end row: reached FP register */
2538 /* OK: get the data in raw format. */
2539 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2540 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2541 /* pad small registers */
2542 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2543 printf_filtered (" ");
2544 /* Now print the register value in hex, endian order. */
2545 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2546 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2547 byte
< REGISTER_RAW_SIZE (regnum
);
2549 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2551 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2554 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2555 printf_filtered (" ");
2558 if (col
> 0) /* ie. if we actually printed anything... */
2559 printf_filtered ("\n");
2564 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2567 mips_do_registers_info (regnum
, fpregs
)
2571 if (regnum
!= -1) /* do one specified register */
2573 if (*(REGISTER_NAME (regnum
)) == '\0')
2574 error ("Not a valid register for the current processor type");
2576 mips_print_register (regnum
, 0);
2577 printf_filtered ("\n");
2580 /* do all (or most) registers */
2583 while (regnum
< NUM_REGS
)
2585 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2586 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2587 regnum
= do_fp_register_row (regnum
); /* FP regs */
2589 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2591 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2596 /* Return number of args passed to a frame. described by FIP.
2597 Can return -1, meaning no way to tell. */
2600 mips_frame_num_args (frame
)
2601 struct frame_info
*frame
;
2603 #if 0 /* FIXME Use or lose this! */
2604 struct chain_info_t
*p
;
2606 p
= mips_find_cached_frame (FRAME_FP (frame
));
2608 return p
->the_info
.numargs
;
2613 /* Is this a branch with a delay slot? */
2615 static int is_delayed
PARAMS ((unsigned long));
2622 for (i
= 0; i
< NUMOPCODES
; ++i
)
2623 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2624 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2626 return (i
< NUMOPCODES
2627 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2628 | INSN_COND_BRANCH_DELAY
2629 | INSN_COND_BRANCH_LIKELY
)));
2633 mips_step_skips_delay (pc
)
2636 char buf
[MIPS_INSTLEN
];
2638 /* There is no branch delay slot on MIPS16. */
2639 if (pc_is_mips16 (pc
))
2642 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2643 /* If error reading memory, guess that it is not a delayed branch. */
2645 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2649 /* Skip the PC past function prologue instructions (32-bit version).
2650 This is a helper function for mips_skip_prologue. */
2653 mips32_skip_prologue (pc
, lenient
)
2654 CORE_ADDR pc
; /* starting PC to search from */
2659 int seen_sp_adjust
= 0;
2660 int load_immediate_bytes
= 0;
2662 /* Skip the typical prologue instructions. These are the stack adjustment
2663 instruction and the instructions that save registers on the stack
2664 or in the gcc frame. */
2665 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2667 unsigned long high_word
;
2669 inst
= mips_fetch_instruction (pc
);
2670 high_word
= (inst
>> 16) & 0xffff;
2673 if (lenient
&& is_delayed (inst
))
2677 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2678 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2680 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2681 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2683 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2684 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2685 && (inst
& 0x001F0000)) /* reg != $zero */
2688 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2690 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2692 continue; /* reg != $zero */
2694 /* move $s8,$sp. With different versions of gas this will be either
2695 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2696 Accept any one of these. */
2697 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2700 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2702 else if (high_word
== 0x3c1c) /* lui $gp,n */
2704 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2706 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2707 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2709 /* The following instructions load $at or $t0 with an immediate
2710 value in preparation for a stack adjustment via
2711 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2712 a local variable, so we accept them only before a stack adjustment
2713 instruction was seen. */
2714 else if (!seen_sp_adjust
)
2716 if (high_word
== 0x3c01 || /* lui $at,n */
2717 high_word
== 0x3c08) /* lui $t0,n */
2719 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2722 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2723 high_word
== 0x3508 || /* ori $t0,$t0,n */
2724 high_word
== 0x3401 || /* ori $at,$zero,n */
2725 high_word
== 0x3408) /* ori $t0,$zero,n */
2727 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2737 /* In a frameless function, we might have incorrectly
2738 skipped some load immediate instructions. Undo the skipping
2739 if the load immediate was not followed by a stack adjustment. */
2740 if (load_immediate_bytes
&& !seen_sp_adjust
)
2741 pc
-= load_immediate_bytes
;
2745 /* Skip the PC past function prologue instructions (16-bit version).
2746 This is a helper function for mips_skip_prologue. */
2749 mips16_skip_prologue (pc
, lenient
)
2750 CORE_ADDR pc
; /* starting PC to search from */
2754 int extend_bytes
= 0;
2755 int prev_extend_bytes
;
2757 /* Table of instructions likely to be found in a function prologue. */
2760 unsigned short inst
;
2761 unsigned short mask
;
2768 , /* addiu $sp,offset */
2772 , /* daddiu $sp,offset */
2776 , /* sw reg,n($sp) */
2780 , /* sd reg,n($sp) */
2784 , /* sw $ra,n($sp) */
2788 , /* sd $ra,n($sp) */
2796 , /* sw $a0-$a3,n($s1) */
2800 , /* move reg,$a0-$a3 */
2804 , /* entry pseudo-op */
2808 , /* addiu $s1,$sp,n */
2811 } /* end of table marker */
2814 /* Skip the typical prologue instructions. These are the stack adjustment
2815 instruction and the instructions that save registers on the stack
2816 or in the gcc frame. */
2817 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2819 unsigned short inst
;
2822 inst
= mips_fetch_instruction (pc
);
2824 /* Normally we ignore an extend instruction. However, if it is
2825 not followed by a valid prologue instruction, we must adjust
2826 the pc back over the extend so that it won't be considered
2827 part of the prologue. */
2828 if ((inst
& 0xf800) == 0xf000) /* extend */
2830 extend_bytes
= MIPS16_INSTLEN
;
2833 prev_extend_bytes
= extend_bytes
;
2836 /* Check for other valid prologue instructions besides extend. */
2837 for (i
= 0; table
[i
].mask
!= 0; i
++)
2838 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2840 if (table
[i
].mask
!= 0) /* it was in table? */
2841 continue; /* ignore it */
2845 /* Return the current pc, adjusted backwards by 2 if
2846 the previous instruction was an extend. */
2847 return pc
- prev_extend_bytes
;
2853 /* To skip prologues, I use this predicate. Returns either PC itself
2854 if the code at PC does not look like a function prologue; otherwise
2855 returns an address that (if we're lucky) follows the prologue. If
2856 LENIENT, then we must skip everything which is involved in setting
2857 up the frame (it's OK to skip more, just so long as we don't skip
2858 anything which might clobber the registers which are being saved.
2859 We must skip more in the case where part of the prologue is in the
2860 delay slot of a non-prologue instruction). */
2863 mips_skip_prologue (pc
, lenient
)
2867 /* See if we can determine the end of the prologue via the symbol table.
2868 If so, then return either PC, or the PC after the prologue, whichever
2871 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2873 if (post_prologue_pc
!= 0)
2874 return max (pc
, post_prologue_pc
);
2876 /* Can't determine prologue from the symbol table, need to examine
2879 if (pc_is_mips16 (pc
))
2880 return mips16_skip_prologue (pc
, lenient
);
2882 return mips32_skip_prologue (pc
, lenient
);
2886 /* The lenient prologue stuff should be superseded by the code in
2887 init_extra_frame_info which looks to see whether the stores mentioned
2888 in the proc_desc have actually taken place. */
2890 /* Is address PC in the prologue (loosely defined) for function at
2894 mips_in_lenient_prologue (startaddr
, pc
)
2895 CORE_ADDR startaddr
;
2898 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2899 return pc
>= startaddr
&& pc
< end_prologue
;
2903 /* Determine how a return value is stored within the MIPS register
2904 file, given the return type `valtype'. */
2906 struct return_value_word
2914 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2917 return_value_location (valtype
, hi
, lo
)
2918 struct type
*valtype
;
2919 struct return_value_word
*hi
;
2920 struct return_value_word
*lo
;
2922 int len
= TYPE_LENGTH (valtype
);
2924 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2925 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2926 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2928 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2930 /* We need to break a 64bit float in two 32 bit halves and
2931 spread them across a floating-point register pair. */
2932 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2933 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2934 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2935 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2937 hi
->reg_offset
= lo
->reg_offset
;
2938 lo
->reg
= FP0_REGNUM
+ 0;
2939 hi
->reg
= FP0_REGNUM
+ 1;
2945 /* The floating point value fits in a single floating-point
2947 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2948 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2951 lo
->reg
= FP0_REGNUM
;
2962 /* Locate a result possibly spread across two registers. */
2964 lo
->reg
= regnum
+ 0;
2965 hi
->reg
= regnum
+ 1;
2966 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2967 && len
< MIPS_SAVED_REGSIZE
)
2969 /* "un-left-justify" the value in the low register */
2970 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2975 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2976 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2977 && len
< MIPS_SAVED_REGSIZE
* 2
2978 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2979 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2981 /* "un-left-justify" the value spread across two registers. */
2982 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2983 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2985 hi
->len
= len
- lo
->len
;
2989 /* Only perform a partial copy of the second register. */
2992 if (len
> MIPS_SAVED_REGSIZE
)
2994 lo
->len
= MIPS_SAVED_REGSIZE
;
2995 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3003 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3004 && REGISTER_RAW_SIZE (regnum
) == 8
3005 && MIPS_SAVED_REGSIZE
== 4)
3007 /* Account for the fact that only the least-signficant part
3008 of the register is being used */
3009 lo
->reg_offset
+= 4;
3010 hi
->reg_offset
+= 4;
3013 hi
->buf_offset
= lo
->len
;
3017 /* Given a return value in `regbuf' with a type `valtype', extract and
3018 copy its value into `valbuf'. */
3021 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3022 struct type
*valtype
;
3023 char regbuf
[REGISTER_BYTES
];
3026 struct return_value_word lo
;
3027 struct return_value_word hi
;
3028 return_value_location (valtype
, &lo
, &hi
);
3030 memcpy (valbuf
+ lo
.buf_offset
,
3031 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3035 memcpy (valbuf
+ hi
.buf_offset
,
3036 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3042 int len
= TYPE_LENGTH (valtype
);
3045 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3046 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3047 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3048 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3049 regnum
= FP0_REGNUM
;
3051 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3052 { /* "un-left-justify" the value from the register */
3053 if (len
< REGISTER_RAW_SIZE (regnum
))
3054 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3055 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3056 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3057 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3058 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3059 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3061 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3062 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3066 /* Given a return value in `valbuf' with a type `valtype', write it's
3067 value into the appropriate register. */
3070 mips_store_return_value (valtype
, valbuf
)
3071 struct type
*valtype
;
3074 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3075 struct return_value_word lo
;
3076 struct return_value_word hi
;
3077 return_value_location (valtype
, &lo
, &hi
);
3079 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3080 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3081 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3083 REGISTER_RAW_SIZE (lo
.reg
));
3087 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3088 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3089 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3091 REGISTER_RAW_SIZE (hi
.reg
));
3097 int len
= TYPE_LENGTH (valtype
);
3098 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3101 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3102 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3103 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3104 && len
<= MIPS_REGSIZE
)))
3105 regnum
= FP0_REGNUM
;
3107 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3108 { /* "left-justify" the value in the register */
3109 if (len
< REGISTER_RAW_SIZE (regnum
))
3110 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3111 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3112 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3113 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3114 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3115 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3117 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3118 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3119 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3120 len
> REGISTER_RAW_SIZE (regnum
) ?
3121 len
: REGISTER_RAW_SIZE (regnum
));
3125 /* Exported procedure: Is PC in the signal trampoline code */
3128 in_sigtramp (pc
, ignore
)
3130 char *ignore
; /* function name */
3132 if (sigtramp_address
== 0)
3134 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3137 /* Commands to show/set the MIPS FPU type. */
3139 static void show_mipsfpu_command
PARAMS ((char *, int));
3141 show_mipsfpu_command (args
, from_tty
)
3147 switch (MIPS_FPU_TYPE
)
3149 case MIPS_FPU_SINGLE
:
3150 fpu
= "single-precision";
3152 case MIPS_FPU_DOUBLE
:
3153 fpu
= "double-precision";
3156 fpu
= "absent (none)";
3159 if (mips_fpu_type_auto
)
3160 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3163 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3168 static void set_mipsfpu_command
PARAMS ((char *, int));
3170 set_mipsfpu_command (args
, from_tty
)
3174 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3175 show_mipsfpu_command (args
, from_tty
);
3178 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3180 set_mipsfpu_single_command (args
, from_tty
)
3184 mips_fpu_type
= MIPS_FPU_SINGLE
;
3185 mips_fpu_type_auto
= 0;
3188 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3192 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3194 set_mipsfpu_double_command (args
, from_tty
)
3198 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3199 mips_fpu_type_auto
= 0;
3202 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3206 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3208 set_mipsfpu_none_command (args
, from_tty
)
3212 mips_fpu_type
= MIPS_FPU_NONE
;
3213 mips_fpu_type_auto
= 0;
3216 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3220 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3222 set_mipsfpu_auto_command (args
, from_tty
)
3226 mips_fpu_type_auto
= 1;
3229 /* Command to set the processor type. */
3232 mips_set_processor_type_command (args
, from_tty
)
3238 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3240 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3241 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3242 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3244 /* Restore the value. */
3245 tmp_mips_processor_type
= strsave (mips_processor_type
);
3250 if (!mips_set_processor_type (tmp_mips_processor_type
))
3252 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3253 /* Restore its value. */
3254 tmp_mips_processor_type
= strsave (mips_processor_type
);
3259 mips_show_processor_type_command (args
, from_tty
)
3265 /* Modify the actual processor type. */
3268 mips_set_processor_type (str
)
3276 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3278 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3280 mips_processor_type
= str
;
3281 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3283 /* FIXME tweak fpu flag too */
3290 /* Attempt to identify the particular processor model by reading the
3294 mips_read_processor_type ()
3298 prid
= read_register (PRID_REGNUM
);
3300 if ((prid
& ~0xf) == 0x700)
3301 return savestring ("r3041", strlen ("r3041"));
3306 /* Just like reinit_frame_cache, but with the right arguments to be
3307 callable as an sfunc. */
3310 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3313 struct cmd_list_element
*c
;
3315 reinit_frame_cache ();
3319 gdb_print_insn_mips (memaddr
, info
)
3321 disassemble_info
*info
;
3323 mips_extra_func_info_t proc_desc
;
3325 /* Search for the function containing this address. Set the low bit
3326 of the address when searching, in case we were given an even address
3327 that is the start of a 16-bit function. If we didn't do this,
3328 the search would fail because the symbol table says the function
3329 starts at an odd address, i.e. 1 byte past the given address. */
3330 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3331 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3333 /* Make an attempt to determine if this is a 16-bit function. If
3334 the procedure descriptor exists and the address therein is odd,
3335 it's definitely a 16-bit function. Otherwise, we have to just
3336 guess that if the address passed in is odd, it's 16-bits. */
3338 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3340 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3342 /* Round down the instruction address to the appropriate boundary. */
3343 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3345 /* Call the appropriate disassembler based on the target endian-ness. */
3346 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3347 return print_insn_big_mips (memaddr
, info
);
3349 return print_insn_little_mips (memaddr
, info
);
3352 /* Old-style breakpoint macros.
3353 The IDT board uses an unusual breakpoint value, and sometimes gets
3354 confused when it sees the usual MIPS breakpoint instruction. */
3356 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3357 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3358 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3359 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3360 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3361 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3362 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3363 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3365 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3366 counter value to determine whether a 16- or 32-bit breakpoint should be
3367 used. It returns a pointer to a string of bytes that encode a breakpoint
3368 instruction, stores the length of the string to *lenptr, and adjusts pc
3369 (if necessary) to point to the actual memory location where the
3370 breakpoint should be inserted. */
3373 mips_breakpoint_from_pc (pcptr
, lenptr
)
3377 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3379 if (pc_is_mips16 (*pcptr
))
3381 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3382 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3383 *lenptr
= sizeof (mips16_big_breakpoint
);
3384 return mips16_big_breakpoint
;
3388 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3389 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3390 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3392 *lenptr
= sizeof (big_breakpoint
);
3394 if (strcmp (target_shortname
, "mips") == 0)
3395 return idt_big_breakpoint
;
3396 else if (strcmp (target_shortname
, "ddb") == 0
3397 || strcmp (target_shortname
, "pmon") == 0
3398 || strcmp (target_shortname
, "lsi") == 0)
3399 return pmon_big_breakpoint
;
3401 return big_breakpoint
;
3406 if (pc_is_mips16 (*pcptr
))
3408 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3409 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3410 *lenptr
= sizeof (mips16_little_breakpoint
);
3411 return mips16_little_breakpoint
;
3415 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3416 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3417 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3419 *lenptr
= sizeof (little_breakpoint
);
3421 if (strcmp (target_shortname
, "mips") == 0)
3422 return idt_little_breakpoint
;
3423 else if (strcmp (target_shortname
, "ddb") == 0
3424 || strcmp (target_shortname
, "pmon") == 0
3425 || strcmp (target_shortname
, "lsi") == 0)
3426 return pmon_little_breakpoint
;
3428 return little_breakpoint
;
3433 /* If PC is in a mips16 call or return stub, return the address of the target
3434 PC, which is either the callee or the caller. There are several
3435 cases which must be handled:
3437 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3438 target PC is in $31 ($ra).
3439 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3440 and the target PC is in $2.
3441 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3442 before the jal instruction, this is effectively a call stub
3443 and the the target PC is in $2. Otherwise this is effectively
3444 a return stub and the target PC is in $18.
3446 See the source code for the stubs in gcc/config/mips/mips16.S for
3449 This function implements the SKIP_TRAMPOLINE_CODE macro.
3457 CORE_ADDR start_addr
;
3459 /* Find the starting address and name of the function containing the PC. */
3460 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3463 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3464 target PC is in $31 ($ra). */
3465 if (strcmp (name
, "__mips16_ret_sf") == 0
3466 || strcmp (name
, "__mips16_ret_df") == 0)
3467 return read_register (RA_REGNUM
);
3469 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3471 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3472 and the target PC is in $2. */
3473 if (name
[19] >= '0' && name
[19] <= '9')
3474 return read_register (2);
3476 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3477 before the jal instruction, this is effectively a call stub
3478 and the the target PC is in $2. Otherwise this is effectively
3479 a return stub and the target PC is in $18. */
3480 else if (name
[19] == 's' || name
[19] == 'd')
3482 if (pc
== start_addr
)
3484 /* Check if the target of the stub is a compiler-generated
3485 stub. Such a stub for a function bar might have a name
3486 like __fn_stub_bar, and might look like this:
3491 la $1,bar (becomes a lui/addiu pair)
3493 So scan down to the lui/addi and extract the target
3494 address from those two instructions. */
3496 CORE_ADDR target_pc
= read_register (2);
3500 /* See if the name of the target function is __fn_stub_*. */
3501 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3503 if (strncmp (name
, "__fn_stub_", 10) != 0
3504 && strcmp (name
, "etext") != 0
3505 && strcmp (name
, "_etext") != 0)
3508 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3509 The limit on the search is arbitrarily set to 20
3510 instructions. FIXME. */
3511 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3513 inst
= mips_fetch_instruction (target_pc
);
3514 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3515 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3516 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3517 return pc
| (inst
& 0xffff); /* low word */
3520 /* Couldn't find the lui/addui pair, so return stub address. */
3524 /* This is the 'return' part of a call stub. The return
3525 address is in $r18. */
3526 return read_register (18);
3529 return 0; /* not a stub */
3533 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3534 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3537 mips_in_call_stub (pc
, name
)
3541 CORE_ADDR start_addr
;
3543 /* Find the starting address of the function containing the PC. If the
3544 caller didn't give us a name, look it up at the same time. */
3545 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3548 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3550 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3551 if (name
[19] >= '0' && name
[19] <= '9')
3553 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3554 before the jal instruction, this is effectively a call stub. */
3555 else if (name
[19] == 's' || name
[19] == 'd')
3556 return pc
== start_addr
;
3559 return 0; /* not a stub */
3563 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3564 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3567 mips_in_return_stub (pc
, name
)
3571 CORE_ADDR start_addr
;
3573 /* Find the starting address of the function containing the PC. */
3574 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3577 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3578 if (strcmp (name
, "__mips16_ret_sf") == 0
3579 || strcmp (name
, "__mips16_ret_df") == 0)
3582 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3583 i.e. after the jal instruction, this is effectively a return stub. */
3584 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3585 && (name
[19] == 's' || name
[19] == 'd')
3586 && pc
!= start_addr
)
3589 return 0; /* not a stub */
3593 /* Return non-zero if the PC is in a library helper function that should
3594 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3597 mips_ignore_helper (pc
)
3602 /* Find the starting address and name of the function containing the PC. */
3603 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3606 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3607 that we want to ignore. */
3608 return (strcmp (name
, "__mips16_ret_sf") == 0
3609 || strcmp (name
, "__mips16_ret_df") == 0);
3613 /* Return a location where we can set a breakpoint that will be hit
3614 when an inferior function call returns. This is normally the
3615 program's entry point. Executables that don't have an entry
3616 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3617 whose address is the location where the breakpoint should be placed. */
3620 mips_call_dummy_address ()
3622 struct minimal_symbol
*sym
;
3624 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3626 return SYMBOL_VALUE_ADDRESS (sym
);
3628 return entry_point_address ();
3633 static gdbarch_init_ftype mips_gdbarch_init
;
3634 static struct gdbarch
*
3635 mips_gdbarch_init (info
, arches
)
3636 struct gdbarch_info info
;
3637 struct gdbarch_list
*arches
;
3639 static LONGEST mips_call_dummy_words
[] =
3641 struct gdbarch
*gdbarch
;
3642 struct gdbarch_tdep
*tdep
;
3645 int ef_mips_bitptrs
;
3648 /* Extract the elf_flags if available */
3649 if (info
.abfd
!= NULL
3650 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3651 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3655 /* try to find a pre-existing architecture */
3656 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3658 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3660 /* MIPS needs to be pedantic about which ABI the object is
3662 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3664 return arches
->gdbarch
;
3667 /* Need a new architecture. Fill in a target specific vector. */
3668 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3669 gdbarch
= gdbarch_alloc (&info
, tdep
);
3670 tdep
->elf_flags
= elf_flags
;
3672 /* Initially set everything according to the ABI. */
3673 set_gdbarch_short_bit (gdbarch
, 16);
3674 set_gdbarch_int_bit (gdbarch
, 32);
3675 set_gdbarch_float_bit (gdbarch
, 32);
3676 set_gdbarch_double_bit (gdbarch
, 64);
3677 set_gdbarch_long_double_bit (gdbarch
, 64);
3678 switch ((elf_flags
& EF_MIPS_ABI
))
3680 case E_MIPS_ABI_O32
:
3681 ef_mips_abi
= "o32";
3682 tdep
->mips_eabi
= 0;
3683 tdep
->mips_saved_regsize
= 4;
3684 tdep
->mips_fp_register_double
= 0;
3685 set_gdbarch_long_bit (gdbarch
, 32);
3686 set_gdbarch_ptr_bit (gdbarch
, 32);
3687 set_gdbarch_long_long_bit (gdbarch
, 64);
3689 case E_MIPS_ABI_O64
:
3690 ef_mips_abi
= "o64";
3691 tdep
->mips_eabi
= 0;
3692 tdep
->mips_saved_regsize
= 8;
3693 tdep
->mips_fp_register_double
= 1;
3694 set_gdbarch_long_bit (gdbarch
, 32);
3695 set_gdbarch_ptr_bit (gdbarch
, 32);
3696 set_gdbarch_long_long_bit (gdbarch
, 64);
3698 case E_MIPS_ABI_EABI32
:
3699 ef_mips_abi
= "eabi32";
3700 tdep
->mips_eabi
= 1;
3701 tdep
->mips_saved_regsize
= 4;
3702 tdep
->mips_fp_register_double
= 0;
3703 set_gdbarch_long_bit (gdbarch
, 32);
3704 set_gdbarch_ptr_bit (gdbarch
, 32);
3705 set_gdbarch_long_long_bit (gdbarch
, 64);
3707 case E_MIPS_ABI_EABI64
:
3708 ef_mips_abi
= "eabi64";
3709 tdep
->mips_eabi
= 1;
3710 tdep
->mips_saved_regsize
= 8;
3711 tdep
->mips_fp_register_double
= 1;
3712 set_gdbarch_long_bit (gdbarch
, 64);
3713 set_gdbarch_ptr_bit (gdbarch
, 64);
3714 set_gdbarch_long_long_bit (gdbarch
, 64);
3717 ef_mips_abi
= "default";
3718 tdep
->mips_eabi
= 0;
3719 tdep
->mips_saved_regsize
= MIPS_REGSIZE
;
3720 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3721 set_gdbarch_long_bit (gdbarch
, 32);
3722 set_gdbarch_ptr_bit (gdbarch
, 32);
3723 set_gdbarch_long_long_bit (gdbarch
, 64);
3727 /* determine the ISA */
3728 switch (elf_flags
& EF_MIPS_ARCH
)
3747 /* determine the size of a pointer */
3748 if ((elf_flags
& EF_MIPS_32BITPTRS
))
3750 ef_mips_bitptrs
= 32;
3752 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
3754 ef_mips_bitptrs
= 64;
3758 ef_mips_bitptrs
= 0;
3762 /* Select either of the two alternative ABI's */
3763 if (tdep
->mips_eabi
)
3765 /* EABI uses R4 through R11 for args */
3766 tdep
->mips_last_arg_regnum
= 11;
3767 /* EABI uses F12 through F19 for args */
3768 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3772 /* old ABI uses R4 through R7 for args */
3773 tdep
->mips_last_arg_regnum
= 7;
3774 /* old ABI uses F12 through F15 for args */
3775 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3778 /* enable/disable the MIPS FPU */
3779 if (!mips_fpu_type_auto
)
3780 tdep
->mips_fpu_type
= mips_fpu_type
;
3781 else if (info
.bfd_arch_info
!= NULL
3782 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3783 switch (info
.bfd_arch_info
->mach
)
3785 case bfd_mach_mips4100
:
3786 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
3789 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3793 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3795 /* MIPS version of register names. NOTE: At present the MIPS
3796 register name management is part way between the old -
3797 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
3798 Further work on it is required. */
3799 set_gdbarch_register_name (gdbarch
, mips_register_name
);
3800 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3801 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3802 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3803 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3804 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3805 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3807 /* Initialize a frame */
3808 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
3810 /* MIPS version of CALL_DUMMY */
3812 set_gdbarch_call_dummy_p (gdbarch
, 1);
3813 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
3814 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3815 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3816 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
3817 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3818 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
3819 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3820 set_gdbarch_call_dummy_length (gdbarch
, 0);
3821 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3822 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
3823 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
3824 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
3825 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
3826 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
3828 set_gdbarch_frame_chain_valid (gdbarch
, default_frame_chain_valid
);
3829 set_gdbarch_get_saved_register (gdbarch
, default_get_saved_register
);
3833 fprintf_unfiltered (gdb_stderr
,
3834 "mips_gdbarch_init: (info)elf_flags = 0x%x\n",
3836 fprintf_unfiltered (gdb_stderr
,
3837 "mips_gdbarch_init: (info)ef_mips_abi = %s\n",
3839 fprintf_unfiltered (gdb_stderr
,
3840 "mips_gdbarch_init: (info)ef_mips_arch = %d\n",
3842 fprintf_unfiltered (gdb_stderr
,
3843 "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n",
3845 fprintf_unfiltered (gdb_stderr
,
3846 "mips_gdbarch_init: MIPS_EABI = %d\n",
3848 fprintf_unfiltered (gdb_stderr
,
3849 "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n",
3850 tdep
->mips_last_arg_regnum
);
3851 fprintf_unfiltered (gdb_stderr
,
3852 "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n",
3853 tdep
->mips_last_fp_arg_regnum
,
3854 tdep
->mips_last_fp_arg_regnum
- FP0_REGNUM
);
3855 fprintf_unfiltered (gdb_stderr
,
3856 "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
3857 tdep
->mips_fpu_type
,
3858 (tdep
->mips_fpu_type
== MIPS_FPU_NONE
? "none"
3859 : tdep
->mips_fpu_type
== MIPS_FPU_SINGLE
? "single"
3860 : tdep
->mips_fpu_type
== MIPS_FPU_DOUBLE
? "double"
3862 fprintf_unfiltered (gdb_stderr
,
3863 "mips_gdbarch_init: tdep->mips_saved_regsize = %d\n",
3864 tdep
->mips_saved_regsize
);
3865 fprintf_unfiltered (gdb_stderr
,
3866 "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n",
3867 tdep
->mips_fp_register_double
,
3868 (tdep
->mips_fp_register_double
? "true" : "false"));
3876 _initialize_mips_tdep ()
3878 static struct cmd_list_element
*mipsfpulist
= NULL
;
3879 struct cmd_list_element
*c
;
3882 register_gdbarch_init (bfd_arch_mips
, mips_gdbarch_init
);
3883 if (!tm_print_insn
) /* Someone may have already set it */
3884 tm_print_insn
= gdb_print_insn_mips
;
3886 /* Let the user turn off floating point and set the fence post for
3887 heuristic_proc_start. */
3889 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3890 "Set use of MIPS floating-point coprocessor.",
3891 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3892 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3893 "Select single-precision MIPS floating-point coprocessor.",
3895 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3896 "Select double-precision MIPS floating-point coprocessor .",
3898 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3899 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3900 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3901 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3902 "Select no MIPS floating-point coprocessor.",
3904 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3905 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3906 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3907 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3908 "Select MIPS floating-point coprocessor automatically.",
3910 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3911 "Show current use of MIPS floating-point coprocessor target.",
3915 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3916 (char *) &tmp_mips_processor_type
,
3917 "Set the type of MIPS processor in use.\n\
3918 Set this to be able to access processor-type-specific registers.\n\
3921 c
->function
.cfunc
= mips_set_processor_type_command
;
3922 c
= add_show_from_set (c
, &showlist
);
3923 c
->function
.cfunc
= mips_show_processor_type_command
;
3925 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3926 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3929 /* We really would like to have both "0" and "unlimited" work, but
3930 command.c doesn't deal with that. So make it a var_zinteger
3931 because the user can always use "999999" or some such for unlimited. */
3932 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3933 (char *) &heuristic_fence_post
,
3935 Set the distance searched for the start of a function.\n\
3936 If you are debugging a stripped executable, GDB needs to search through the\n\
3937 program for the start of a function. This command sets the distance of the\n\
3938 search. The only need to set it is when debugging a stripped executable.",
3940 /* We need to throw away the frame cache when we set this, since it
3941 might change our ability to get backtraces. */
3942 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3943 add_show_from_set (c
, &showlist
);
3945 /* Allow the user to control whether the upper bits of 64-bit
3946 addresses should be zeroed. */
3948 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
3949 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3950 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3951 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
3954 /* Allow the user to control the size of 32 bit registers within the
3955 raw remote packet. */
3956 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
3959 (char *)&mips64_transfers_32bit_regs_p
, "\
3960 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
3961 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
3962 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
3963 64 bits for others. Use \"off\" to disable compatibility mode",